opcodes/openrisc-desc.h

   1 /* CPU data header for openrisc.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef OPENRISC_CPU_H
  26 #define OPENRISC_CPU_H
  27
  28 #define CGEN_ARCH openrisc
  29
  30 /* Given symbol S, return openrisc_cgen_<S>.  */
  31 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  32 #define CGEN_SYM(s) openrisc##_cgen_##s
  33 #else
  34 #define CGEN_SYM(s) openrisc/**/_cgen_/**/s
  35 #endif
  36
  37
  38 /* Selected cpu families.  */
  39 #define HAVE_CPU_OPENRISCBF
  40
  41 #define CGEN_INSN_LSB0_P 1
  42
  43 /* Minimum size of any insn (in bytes).  */
  44 #define CGEN_MIN_INSN_SIZE 4
  45
  46 /* Maximum size of any insn (in bytes).  */
  47 #define CGEN_MAX_INSN_SIZE 4
  48
  49 #define CGEN_INT_INSN_P 1
  50
  51 /* Maximum number of syntax elements in an instruction.  */
  52 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 14
  53
  54 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  55    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  56    we can't hash on everything up to the space.  */
  57 #define CGEN_MNEMONIC_OPERANDS
  58
  59 /* Maximum number of fields in an instruction.  */
  60 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
  61
  62 /* Enums.  */
  63
  64 /* Enum declaration for exception vectors.  */
  65 typedef enum e_exception {
  66   E_RESET, E_BUSERR, E_DPF, E_IPF
  67  , E_EXTINT, E_ALIGN, E_ILLEGAL, E_PEINT
  68  , E_DTLBMISS, E_ITLBMISS, E_RRANGE, E_SYSCALL
  69  , E_BREAK, E_RESERVED
  70 } E_EXCEPTION;
  71
  72 /* Enum declaration for FIXME.  */
  73 typedef enum insn_class {
  74   OP1_0, OP1_1, OP1_2, OP1_3
  75 } INSN_CLASS;
  76
  77 /* Enum declaration for FIXME.  */
  78 typedef enum insn_sub {
  79   OP2_0, OP2_1, OP2_2, OP2_3
  80  , OP2_4, OP2_5, OP2_6, OP2_7
  81  , OP2_8, OP2_9, OP2_10, OP2_11
  82  , OP2_12, OP2_13, OP2_14, OP2_15
  83 } INSN_SUB;
  84
  85 /* Enum declaration for FIXME.  */
  86 typedef enum insn_op3 {
  87   OP3_0, OP3_1, OP3_2, OP3_3
  88 } INSN_OP3;
  89
  90 /* Enum declaration for FIXME.  */
  91 typedef enum insn_op4 {
  92   OP4_0, OP4_1, OP4_2, OP4_3
  93  , OP4_4, OP4_5, OP4_6, OP4_7
  94 } INSN_OP4;
  95
  96 /* Enum declaration for FIXME.  */
  97 typedef enum insn_op5 {
  98   OP5_0, OP5_1, OP5_2, OP5_3
  99  , OP5_4, OP5_5, OP5_6, OP5_7
 100  , OP5_8, OP5_9, OP5_10, OP5_11
 101  , OP5_12, OP5_13, OP5_14, OP5_15
 102  , OP5_16, OP5_17, OP5_18, OP5_19
 103  , OP5_20, OP5_21, OP5_22, OP5_23
 104  , OP5_24, OP5_25, OP5_26, OP5_27
 105  , OP5_28, OP5_29, OP5_30, OP5_31
 106 } INSN_OP5;
 107
 108 /* Enum declaration for FIXME.  */
 109 typedef enum insn_op6 {
 110   OP6_0, OP6_1, OP6_2, OP6_3
 111  , OP6_4, OP6_5, OP6_6, OP6_7
 112 } INSN_OP6;
 113
 114 /* Enum declaration for FIXME.  */
 115 typedef enum insn_op7 {
 116   OP7_0, OP7_1, OP7_2, OP7_3
 117  , OP7_4, OP7_5, OP7_6, OP7_7
 118  , OP7_8, OP7_9, OP7_10, OP7_11
 119  , OP7_12, OP7_13, OP7_14, OP7_15
 120 } INSN_OP7;
 121
 122 /* Attributes.  */
 123
 124 /* Enum declaration for machine type selection.  */
 125 typedef enum mach_attr {
 126   MACH_BASE, MACH_OPENRISC, MACH_OR1300, MACH_MAX
 127 } MACH_ATTR;
 128
 129 /* Enum declaration for instruction set selection.  */
 130 typedef enum isa_attr {
 131   ISA_OR32, ISA_MAX
 132 } ISA_ATTR;
 133
 134 /* Enum declaration for if this model has caches.  */
 135 typedef enum has_cache_attr {
 136   HAS_CACHE_DATA_CACHE, HAS_CACHE_INSN_CACHE
 137 } HAS_CACHE_ATTR;
 138
 139 /* Number of architecture variants.  */
 140 #define MAX_ISAS  1
 141 #define MAX_MACHS ((int) MACH_MAX)
 142
 143 /* Ifield support.  */
 144
 145 extern const struct cgen_ifld openrisc_cgen_ifld_table[];
 146
 147 /* Ifield attribute indices.  */
 148
 149 /* Enum declaration for cgen_ifld attrs.  */
 150 typedef enum cgen_ifld_attr {
 151   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 152  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 153  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 154 } CGEN_IFLD_ATTR;
 155
 156 /* Number of non-boolean elements in cgen_ifld_attr.  */
 157 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 158
 159 /* Enum declaration for openrisc ifield types.  */
 160 typedef enum ifield_type {
 161   OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB
 162  , OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3, OPENRISC_F_SIMM16
 163  , OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16, OPENRISC_F_LO16
 164  , OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3, OPENRISC_F_OP4
 165  , OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7, OPENRISC_F_I16_1
 166  , OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26, OPENRISC_F_I16NC
 167  , OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1, OPENRISC_F_F_7_3
 168  , OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX
 169 } IFIELD_TYPE;
 170
 171 #define MAX_IFLD ((int) OPENRISC_F_MAX)
 172
 173 /* Hardware attribute indices.  */
 174
 175 /* Enum declaration for cgen_hw attrs.  */
 176 typedef enum cgen_hw_attr {
 177   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 178  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 179 } CGEN_HW_ATTR;
 180
 181 /* Number of non-boolean elements in cgen_hw_attr.  */
 182 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 183
 184 /* Enum declaration for openrisc hardware types.  */
 185 typedef enum cgen_hw_type {
 186   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 187  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_SR
 188  , HW_H_HI16, HW_H_LO16, HW_H_CBIT, HW_H_DELAY_INSN
 189  , HW_MAX
 190 } CGEN_HW_TYPE;
 191
 192 #define MAX_HW ((int) HW_MAX)
 193
 194 /* Operand attribute indices.  */
 195
 196 /* Enum declaration for cgen_operand attrs.  */
 197 typedef enum cgen_operand_attr {
 198   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 199  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 200  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 201 } CGEN_OPERAND_ATTR;
 202
 203 /* Number of non-boolean elements in cgen_operand_attr.  */
 204 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 205
 206 /* Enum declaration for openrisc operand types.  */
 207 typedef enum cgen_operand_type {
 208   OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16
 209  , OPENRISC_OPERAND_UIMM_16, OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5
 210  , OPENRISC_OPERAND_RD, OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23
 211  , OPENRISC_OPERAND_OP_F_3, OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC
 212  , OPENRISC_OPERAND_MAX
 213 } CGEN_OPERAND_TYPE;
 214
 215 /* Number of operands types.  */
 216 #define MAX_OPERANDS 16
 217
 218 /* Maximum number of operands referenced by any insn.  */
 219 #define MAX_OPERAND_INSTANCES 8
 220
 221 /* Insn attribute indices.  */
 222
 223 /* Enum declaration for cgen_insn attrs.  */
 224 typedef enum cgen_insn_attr {
 225   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 226  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
 227  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
 228  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 229 } CGEN_INSN_ATTR;
 230
 231 /* Number of non-boolean elements in cgen_insn_attr.  */
 232 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 233
 234 /* cgen.h uses things we just defined.  */
 235 #include "opcode/cgen.h"
 236
 237 /* Attributes.  */
 238 extern const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[];
 239 extern const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[];
 240 extern const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[];
 241 extern const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[];
 242
 243 /* Hardware decls.  */
 244
 245 extern CGEN_KEYWORD openrisc_cgen_opval_h_gr;
 246
 247
 248
 249
 250 #endif /* OPENRISC_CPU_H */