1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "opcode/ppc.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat
PARAMS ((unsigned long, long, const char **));
42 static long extract_bat
PARAMS ((unsigned long, int *));
43 static unsigned long insert_bba
PARAMS ((unsigned long, long, const char **));
44 static long extract_bba
PARAMS ((unsigned long, int *));
45 static unsigned long insert_bd
PARAMS ((unsigned long, long, const char **));
46 static long extract_bd
PARAMS ((unsigned long, int *));
47 static unsigned long insert_bdm
PARAMS ((unsigned long, long, const char **));
48 static long extract_bdm
PARAMS ((unsigned long, int *));
49 static unsigned long insert_bdp
PARAMS ((unsigned long, long, const char **));
50 static long extract_bdp
PARAMS ((unsigned long, int *));
51 static int valid_bo
PARAMS ((long));
52 static unsigned long insert_bo
PARAMS ((unsigned long, long, const char **));
53 static long extract_bo
PARAMS ((unsigned long, int *));
54 static unsigned long insert_boe
PARAMS ((unsigned long, long, const char **));
55 static long extract_boe
PARAMS ((unsigned long, int *));
56 static unsigned long insert_ds
PARAMS ((unsigned long, long, const char **));
57 static long extract_ds
PARAMS ((unsigned long, int *));
58 static unsigned long insert_li
PARAMS ((unsigned long, long, const char **));
59 static long extract_li
PARAMS ((unsigned long, int *));
60 static unsigned long insert_mbe
PARAMS ((unsigned long, long, const char **));
61 static long extract_mbe
PARAMS ((unsigned long, int *));
62 static unsigned long insert_mb6
PARAMS ((unsigned long, long, const char **));
63 static long extract_mb6
PARAMS ((unsigned long, int *));
64 static unsigned long insert_nb
PARAMS ((unsigned long, long, const char **));
65 static long extract_nb
PARAMS ((unsigned long, int *));
66 static unsigned long insert_nsi
PARAMS ((unsigned long, long, const char **));
67 static long extract_nsi
PARAMS ((unsigned long, int *));
68 static unsigned long insert_ral
PARAMS ((unsigned long, long, const char **));
69 static unsigned long insert_ram
PARAMS ((unsigned long, long, const char **));
70 static unsigned long insert_ras
PARAMS ((unsigned long, long, const char **));
71 static unsigned long insert_rbs
PARAMS ((unsigned long, long, const char **));
72 static long extract_rbs
PARAMS ((unsigned long, int *));
73 static unsigned long insert_sh6
PARAMS ((unsigned long, long, const char **));
74 static long extract_sh6
PARAMS ((unsigned long, int *));
75 static unsigned long insert_spr
PARAMS ((unsigned long, long, const char **));
76 static long extract_spr
PARAMS ((unsigned long, int *));
77 static unsigned long insert_tbr
PARAMS ((unsigned long, long, const char **));
78 static long extract_tbr
PARAMS ((unsigned long, int *));
80 /* The operands table.
82 The fields are bits, shift, insert, extract, flags.
84 We used to put parens around the various additions, like the one
85 for BA just below. However, that caused trouble with feeble
86 compilers with a limit on depth of a parenthesized expression, like
87 (reportedly) the compiler in Microsoft Developer Studio 5. So we
88 omit the parens, since the macros are never used in a context where
89 the addition will be ambiguous. */
91 const struct powerpc_operand powerpc_operands
[] =
93 /* The zero index is used to indicate the end of the list of
98 /* The BA field in an XL form instruction. */
100 #define BA_MASK (0x1f << 16)
101 { 5, 16, 0, 0, PPC_OPERAND_CR
},
103 /* The BA field in an XL form instruction when it must be the same
104 as the BT field in the same instruction. */
106 { 5, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
108 /* The BB field in an XL form instruction. */
110 #define BB_MASK (0x1f << 11)
111 { 5, 11, 0, 0, PPC_OPERAND_CR
},
113 /* The BB field in an XL form instruction when it must be the same
114 as the BA field in the same instruction. */
116 { 5, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
118 /* The BD field in a B form instruction. The lower two bits are
121 { 16, 0, insert_bd
, extract_bd
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
123 /* The BD field in a B form instruction when absolute addressing is
126 { 16, 0, insert_bd
, extract_bd
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
128 /* The BD field in a B form instruction when the - modifier is used.
129 This sets the y bit of the BO field appropriately. */
131 { 16, 0, insert_bdm
, extract_bdm
,
132 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
134 /* The BD field in a B form instruction when the - modifier is used
135 and absolute address is used. */
137 { 16, 0, insert_bdm
, extract_bdm
,
138 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
140 /* The BD field in a B form instruction when the + modifier is used.
141 This sets the y bit of the BO field appropriately. */
143 { 16, 0, insert_bdp
, extract_bdp
,
144 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
146 /* The BD field in a B form instruction when the + modifier is used
147 and absolute addressing is used. */
149 { 16, 0, insert_bdp
, extract_bdp
,
150 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
152 /* The BF field in an X or XL form instruction. */
154 { 3, 23, 0, 0, PPC_OPERAND_CR
},
156 /* An optional BF field. This is used for comparison instructions,
157 in which an omitted BF field is taken as zero. */
159 { 3, 23, 0, 0, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
161 /* The BFA field in an X or XL form instruction. */
163 { 3, 18, 0, 0, PPC_OPERAND_CR
},
165 /* The BI field in a B form or XL form instruction. */
167 #define BI_MASK (0x1f << 16)
168 { 5, 16, 0, 0, PPC_OPERAND_CR
},
170 /* The BO field in a B form instruction. Certain values are
173 #define BO_MASK (0x1f << 21)
174 { 5, 21, insert_bo
, extract_bo
, 0 },
176 /* The BO field in a B form instruction when the + or - modifier is
177 used. This is like the BO field, but it must be even. */
179 { 5, 21, insert_boe
, extract_boe
, 0 },
181 /* The BT field in an X or XL form instruction. */
183 { 5, 21, 0, 0, PPC_OPERAND_CR
},
185 /* The condition register number portion of the BI field in a B form
186 or XL form instruction. This is used for the extended
187 conditional branch mnemonics, which set the lower two bits of the
188 BI field. This field is optional. */
190 { 3, 18, 0, 0, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
192 /* The D field in a D form instruction. This is a displacement off
193 a register, and implies that the next operand is a register in
196 { 16, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
198 /* The DS field in a DS form instruction. This is like D, but the
199 lower two bits are forced to zero. */
201 { 16, 0, insert_ds
, extract_ds
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
203 /* The E field in a wrteei instruction. */
207 /* The FL1 field in a POWER SC form instruction. */
211 /* The FL2 field in a POWER SC form instruction. */
215 /* The FLM field in an XFL form instruction. */
219 /* The FRA field in an X or A form instruction. */
221 #define FRA_MASK (0x1f << 16)
222 { 5, 16, 0, 0, PPC_OPERAND_FPR
},
224 /* The FRB field in an X or A form instruction. */
226 #define FRB_MASK (0x1f << 11)
227 { 5, 11, 0, 0, PPC_OPERAND_FPR
},
229 /* The FRC field in an A form instruction. */
231 #define FRC_MASK (0x1f << 6)
232 { 5, 6, 0, 0, PPC_OPERAND_FPR
},
234 /* The FRS field in an X form instruction or the FRT field in a D, X
235 or A form instruction. */
238 { 5, 21, 0, 0, PPC_OPERAND_FPR
},
240 /* The FXM field in an XFX instruction. */
242 #define FXM_MASK (0xff << 12)
245 /* The L field in a D or X form instruction. */
247 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL
},
249 /* The LEV field in a POWER SC form instruction. */
253 /* The LI field in an I form instruction. The lower two bits are
256 { 26, 0, insert_li
, extract_li
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
258 /* The LI field in an I form instruction when used as an absolute
261 { 26, 0, insert_li
, extract_li
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
263 /* The MB field in an M form instruction. */
265 #define MB_MASK (0x1f << 6)
268 /* The ME field in an M form instruction. */
270 #define ME_MASK (0x1f << 1)
273 /* The MB and ME fields in an M form instruction expressed a single
274 operand which is a bitmask indicating which bits to select. This
275 is a two operand form using PPC_OPERAND_NEXT. See the
276 description in opcode/ppc.h for what this means. */
278 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
279 { 32, 0, insert_mbe
, extract_mbe
, 0 },
281 /* The MB or ME field in an MD or MDS form instruction. The high
282 bit is wrapped to the low end. */
285 #define MB6_MASK (0x3f << 5)
286 { 6, 5, insert_mb6
, extract_mb6
, 0 },
288 /* The NB field in an X form instruction. The value 32 is stored as
291 { 6, 11, insert_nb
, extract_nb
, 0 },
293 /* The NSI field in a D form instruction. This is the same as the
294 SI field, only negated. */
296 { 16, 0, insert_nsi
, extract_nsi
,
297 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
299 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
301 #define RA_MASK (0x1f << 16)
302 { 5, 16, 0, 0, PPC_OPERAND_GPR
},
304 /* The RA field in a D or X form instruction which is an updating
305 load, which means that the RA field may not be zero and may not
306 equal the RT field. */
308 { 5, 16, insert_ral
, 0, PPC_OPERAND_GPR
},
310 /* The RA field in an lmw instruction, which has special value
313 { 5, 16, insert_ram
, 0, PPC_OPERAND_GPR
},
315 /* The RA field in a D or X form instruction which is an updating
316 store or an updating floating point load, which means that the RA
317 field may not be zero. */
319 { 5, 16, insert_ras
, 0, PPC_OPERAND_GPR
},
321 /* The RB field in an X, XO, M, or MDS form instruction. */
323 #define RB_MASK (0x1f << 11)
324 { 5, 11, 0, 0, PPC_OPERAND_GPR
},
326 /* The RB field in an X form instruction when it must be the same as
327 the RS field in the instruction. This is used for extended
328 mnemonics like mr. */
330 { 5, 1, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
332 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
333 instruction or the RT field in a D, DS, X, XFX or XO form
337 #define RT_MASK (0x1f << 21)
338 { 5, 21, 0, 0, PPC_OPERAND_GPR
},
340 /* The SH field in an X or M form instruction. */
342 #define SH_MASK (0x1f << 11)
345 /* The SH field in an MD form instruction. This is split. */
347 #define SH6_MASK ((0x1f << 11) | (1 << 1))
348 { 6, 1, insert_sh6
, extract_sh6
, 0 },
350 /* The SI field in a D form instruction. */
352 { 16, 0, 0, 0, PPC_OPERAND_SIGNED
},
354 /* The SI field in a D form instruction when we accept a wide range
355 of positive values. */
356 #define SISIGNOPT SI + 1
357 { 16, 0, 0, 0, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
359 /* The SPR field in an XFX form instruction. This is flipped--the
360 lower 5 bits are stored in the upper 5 and vice- versa. */
361 #define SPR SISIGNOPT + 1
362 #define SPR_MASK (0x3ff << 11)
363 { 10, 11, insert_spr
, extract_spr
, 0 },
365 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
366 #define SPRBAT SPR + 1
367 #define SPRBAT_MASK (0x3 << 17)
370 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
371 #define SPRG SPRBAT + 1
372 #define SPRG_MASK (0x3 << 16)
375 /* The SR field in an X form instruction. */
379 /* The SV field in a POWER SC form instruction. */
383 /* The TBR field in an XFX form instruction. This is like the SPR
384 field, but it is optional. */
386 { 10, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
388 /* The TO field in a D or X form instruction. */
390 #define TO_MASK (0x1f << 21)
393 /* The U field in an X form instruction. */
397 /* The UI field in a D form instruction. */
401 /* The VA field in a VA, VX or VXR form instruction. */
403 #define VA_MASK (0x1f << 16)
404 {5, 16, 0, 0, PPC_OPERAND_VR
},
406 /* The VB field in a VA, VX or VXR form instruction. */
408 #define VB_MASK (0x1f << 11)
409 {5, 11, 0, 0, PPC_OPERAND_VR
},
411 /* The VC field in a VA form instruction. */
413 #define VC_MASK (0x1f << 6)
414 {5, 6, 0, 0, PPC_OPERAND_VR
},
416 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
419 #define VD_MASK (0x1f << 21)
420 {5, 21, 0, 0, PPC_OPERAND_VR
},
422 /* The SIMM field in a VX form instruction. */
424 { 5, 16, 0, 0, PPC_OPERAND_SIGNED
},
426 /* The UIMM field in a VX form instruction. */
427 #define UIMM SIMM + 1
430 /* The SHB field in a VA form instruction. */
435 /* The functions used to insert and extract complicated operands. */
437 /* The BA field in an XL form instruction when it must be the same as
438 the BT field in the same instruction. This operand is marked FAKE.
439 The insertion function just copies the BT field into the BA field,
440 and the extraction function just checks that the fields are the
445 insert_bat (insn
, value
, errmsg
)
447 long value ATTRIBUTE_UNUSED
;
448 const char **errmsg ATTRIBUTE_UNUSED
;
450 return insn
| (((insn
>> 21) & 0x1f) << 16);
454 extract_bat (insn
, invalid
)
458 if (invalid
!= (int *) NULL
459 && ((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
464 /* The BB field in an XL form instruction when it must be the same as
465 the BA field in the same instruction. This operand is marked FAKE.
466 The insertion function just copies the BA field into the BB field,
467 and the extraction function just checks that the fields are the
472 insert_bba (insn
, value
, errmsg
)
474 long value ATTRIBUTE_UNUSED
;
475 const char **errmsg ATTRIBUTE_UNUSED
;
477 return insn
| (((insn
>> 16) & 0x1f) << 11);
481 extract_bba (insn
, invalid
)
485 if (invalid
!= (int *) NULL
486 && ((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
491 /* The BD field in a B form instruction. The lower two bits are
496 insert_bd (insn
, value
, errmsg
)
499 const char **errmsg ATTRIBUTE_UNUSED
;
501 return insn
| (value
& 0xfffc);
506 extract_bd (insn
, invalid
)
508 int *invalid ATTRIBUTE_UNUSED
;
510 if ((insn
& 0x8000) != 0)
511 return (insn
& 0xfffc) - 0x10000;
513 return insn
& 0xfffc;
516 /* The BD field in a B form instruction when the - modifier is used.
517 This modifier means that the branch is not expected to be taken.
518 We must set the y bit of the BO field to 1 if the offset is
519 negative. When extracting, we require that the y bit be 1 and that
520 the offset be positive, since if the y bit is 0 we just want to
521 print the normal form of the instruction. */
525 insert_bdm (insn
, value
, errmsg
)
528 const char **errmsg ATTRIBUTE_UNUSED
;
530 if ((value
& 0x8000) != 0)
532 return insn
| (value
& 0xfffc);
536 extract_bdm (insn
, invalid
)
540 if (invalid
!= (int *) NULL
541 && ((insn
& (1 << 21)) == 0
542 || (insn
& (1 << 15)) == 0))
544 if ((insn
& 0x8000) != 0)
545 return (insn
& 0xfffc) - 0x10000;
547 return insn
& 0xfffc;
550 /* The BD field in a B form instruction when the + modifier is used.
551 This is like BDM, above, except that the branch is expected to be
556 insert_bdp (insn
, value
, errmsg
)
559 const char **errmsg ATTRIBUTE_UNUSED
;
561 if ((value
& 0x8000) == 0)
563 return insn
| (value
& 0xfffc);
567 extract_bdp (insn
, invalid
)
571 if (invalid
!= (int *) NULL
572 && ((insn
& (1 << 21)) == 0
573 || (insn
& (1 << 15)) != 0))
575 if ((insn
& 0x8000) != 0)
576 return (insn
& 0xfffc) - 0x10000;
578 return insn
& 0xfffc;
581 /* Check for legal values of a BO field. */
587 /* Certain encodings have bits that are required to be zero. These
588 are (z must be zero, y may be anything):
595 switch (value
& 0x14)
601 return (value
& 0x2) == 0;
603 return (value
& 0x8) == 0;
605 return value
== 0x14;
609 /* The BO field in a B form instruction. Warn about attempts to set
610 the field to an illegal value. */
613 insert_bo (insn
, value
, errmsg
)
618 if (errmsg
!= (const char **) NULL
619 && ! valid_bo (value
))
620 *errmsg
= _("invalid conditional option");
621 return insn
| ((value
& 0x1f) << 21);
625 extract_bo (insn
, invalid
)
631 value
= (insn
>> 21) & 0x1f;
632 if (invalid
!= (int *) NULL
633 && ! valid_bo (value
))
638 /* The BO field in a B form instruction when the + or - modifier is
639 used. This is like the BO field, but it must be even. When
640 extracting it, we force it to be even. */
643 insert_boe (insn
, value
, errmsg
)
648 if (errmsg
!= (const char **) NULL
)
650 if (! valid_bo (value
))
651 *errmsg
= _("invalid conditional option");
652 else if ((value
& 1) != 0)
653 *errmsg
= _("attempt to set y bit when using + or - modifier");
655 return insn
| ((value
& 0x1f) << 21);
659 extract_boe (insn
, invalid
)
665 value
= (insn
>> 21) & 0x1f;
666 if (invalid
!= (int *) NULL
667 && ! valid_bo (value
))
672 /* The DS field in a DS form instruction. This is like D, but the
673 lower two bits are forced to zero. */
677 insert_ds (insn
, value
, errmsg
)
680 const char **errmsg ATTRIBUTE_UNUSED
;
682 return insn
| (value
& 0xfffc);
687 extract_ds (insn
, invalid
)
689 int *invalid ATTRIBUTE_UNUSED
;
691 if ((insn
& 0x8000) != 0)
692 return (insn
& 0xfffc) - 0x10000;
694 return insn
& 0xfffc;
697 /* The LI field in an I form instruction. The lower two bits are
702 insert_li (insn
, value
, errmsg
)
707 if ((value
& 3) != 0 && errmsg
!= (const char **) NULL
)
708 *errmsg
= _("ignoring least significant bits in branch offset");
709 return insn
| (value
& 0x3fffffc);
714 extract_li (insn
, invalid
)
716 int *invalid ATTRIBUTE_UNUSED
;
718 if ((insn
& 0x2000000) != 0)
719 return (insn
& 0x3fffffc) - 0x4000000;
721 return insn
& 0x3fffffc;
724 /* The MB and ME fields in an M form instruction expressed as a single
725 operand which is itself a bitmask. The extraction function always
726 marks it as invalid, since we never want to recognize an
727 instruction which uses a field of this type. */
730 insert_mbe (insn
, value
, errmsg
)
735 unsigned long uval
, mask
;
736 int mb
, me
, mx
, count
, last
;
742 if (errmsg
!= (const char **) NULL
)
743 *errmsg
= _("illegal bitmask");
755 /* mb: location of last 0->1 transition */
756 /* me: location of last 1->0 transition */
757 /* count: # transitions */
759 for (mx
= 0, mask
= (long) 1 << 31; mx
< 32; ++mx
, mask
>>= 1)
761 if ((uval
& mask
) && !last
)
767 else if (!(uval
& mask
) && last
)
777 if (count
!= 2 && (count
!= 0 || ! last
))
779 if (errmsg
!= (const char **) NULL
)
780 *errmsg
= _("illegal bitmask");
783 return insn
| (mb
<< 6) | ((me
- 1) << 1);
787 extract_mbe (insn
, invalid
)
795 if (invalid
!= (int *) NULL
)
798 mb
= (insn
>> 6) & 0x1f;
799 me
= (insn
>> 1) & 0x1f;
803 for (i
= mb
; i
<= me
; i
++)
804 ret
|= (long) 1 << (31 - i
);
806 else if (mb
== me
+ 1)
808 else /* (mb > me + 1) */
811 for (i
= me
+ 1; i
< mb
; i
++)
812 ret
&= ~ ((long) 1 << (31 - i
));
817 /* The MB or ME field in an MD or MDS form instruction. The high bit
818 is wrapped to the low end. */
822 insert_mb6 (insn
, value
, errmsg
)
825 const char **errmsg ATTRIBUTE_UNUSED
;
827 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
832 extract_mb6 (insn
, invalid
)
834 int *invalid ATTRIBUTE_UNUSED
;
836 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
839 /* The NB field in an X form instruction. The value 32 is stored as
843 insert_nb (insn
, value
, errmsg
)
848 if (value
< 0 || value
> 32)
849 *errmsg
= _("value out of range");
852 return insn
| ((value
& 0x1f) << 11);
857 extract_nb (insn
, invalid
)
859 int *invalid ATTRIBUTE_UNUSED
;
863 ret
= (insn
>> 11) & 0x1f;
869 /* The NSI field in a D form instruction. This is the same as the SI
870 field, only negated. The extraction function always marks it as
871 invalid, since we never want to recognize an instruction which uses
872 a field of this type. */
876 insert_nsi (insn
, value
, errmsg
)
879 const char **errmsg ATTRIBUTE_UNUSED
;
881 return insn
| ((- value
) & 0xffff);
885 extract_nsi (insn
, invalid
)
889 if (invalid
!= (int *) NULL
)
891 if ((insn
& 0x8000) != 0)
892 return - ((long)(insn
& 0xffff) - 0x10000);
894 return - (long)(insn
& 0xffff);
897 /* The RA field in a D or X form instruction which is an updating
898 load, which means that the RA field may not be zero and may not
899 equal the RT field. */
902 insert_ral (insn
, value
, errmsg
)
908 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
909 *errmsg
= "invalid register operand when updating";
910 return insn
| ((value
& 0x1f) << 16);
913 /* The RA field in an lmw instruction, which has special value
917 insert_ram (insn
, value
, errmsg
)
922 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
923 *errmsg
= _("index register in load range");
924 return insn
| ((value
& 0x1f) << 16);
927 /* The RA field in a D or X form instruction which is an updating
928 store or an updating floating point load, which means that the RA
929 field may not be zero. */
932 insert_ras (insn
, value
, errmsg
)
938 *errmsg
= _("invalid register operand when updating");
939 return insn
| ((value
& 0x1f) << 16);
942 /* The RB field in an X form instruction when it must be the same as
943 the RS field in the instruction. This is used for extended
944 mnemonics like mr. This operand is marked FAKE. The insertion
945 function just copies the BT field into the BA field, and the
946 extraction function just checks that the fields are the same. */
950 insert_rbs (insn
, value
, errmsg
)
952 long value ATTRIBUTE_UNUSED
;
953 const char **errmsg ATTRIBUTE_UNUSED
;
955 return insn
| (((insn
>> 21) & 0x1f) << 11);
959 extract_rbs (insn
, invalid
)
963 if (invalid
!= (int *) NULL
964 && ((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
969 /* The SH field in an MD form instruction. This is split. */
973 insert_sh6 (insn
, value
, errmsg
)
976 const char **errmsg ATTRIBUTE_UNUSED
;
978 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
983 extract_sh6 (insn
, invalid
)
985 int *invalid ATTRIBUTE_UNUSED
;
987 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
990 /* The SPR field in an XFX form instruction. This is flipped--the
991 lower 5 bits are stored in the upper 5 and vice- versa. */
994 insert_spr (insn
, value
, errmsg
)
997 const char **errmsg ATTRIBUTE_UNUSED
;
999 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1003 extract_spr (insn
, invalid
)
1005 int *invalid ATTRIBUTE_UNUSED
;
1007 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1010 /* The TBR field in an XFX instruction. This is just like SPR, but it
1011 is optional. When TBR is omitted, it must be inserted as 268 (the
1012 magic number of the TB register). These functions treat 0
1013 (indicating an omitted optional operand) as 268. This means that
1014 ``mftb 4,0'' is not handled correctly. This does not matter very
1015 much, since the architecture manual does not define mftb as
1016 accepting any values other than 268 or 269. */
1020 static unsigned long
1021 insert_tbr (insn
, value
, errmsg
)
1024 const char **errmsg ATTRIBUTE_UNUSED
;
1028 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1032 extract_tbr (insn
, invalid
)
1034 int *invalid ATTRIBUTE_UNUSED
;
1038 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1044 /* Macros used to form opcodes. */
1046 /* The main opcode. */
1047 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1048 #define OP_MASK OP (0x3f)
1050 /* The main opcode combined with a trap code in the TO field of a D
1051 form instruction. Used for extended mnemonics for the trap
1053 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1054 #define OPTO_MASK (OP_MASK | TO_MASK)
1056 /* The main opcode combined with a comparison size bit in the L field
1057 of a D form or X form instruction. Used for extended mnemonics for
1058 the comparison instructions. */
1059 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1060 #define OPL_MASK OPL (0x3f,1)
1062 /* An A form instruction. */
1063 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1064 #define A_MASK A (0x3f, 0x1f, 1)
1066 /* An A_MASK with the FRB field fixed. */
1067 #define AFRB_MASK (A_MASK | FRB_MASK)
1069 /* An A_MASK with the FRC field fixed. */
1070 #define AFRC_MASK (A_MASK | FRC_MASK)
1072 /* An A_MASK with the FRA and FRC fields fixed. */
1073 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1075 /* A B form instruction. */
1076 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1077 #define B_MASK B (0x3f, 1, 1)
1079 /* A B form instruction setting the BO field. */
1080 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1081 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1083 /* A BBO_MASK with the y bit of the BO field removed. This permits
1084 matching a conditional branch regardless of the setting of the y
1086 #define Y_MASK (((unsigned long)1) << 21)
1087 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1089 /* A B form instruction setting the BO field and the condition bits of
1091 #define BBOCB(op, bo, cb, aa, lk) \
1092 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1093 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1095 /* A BBOCB_MASK with the y bit of the BO field removed. */
1096 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1098 /* A BBOYCB_MASK in which the BI field is fixed. */
1099 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1101 /* The main opcode mask with the RA field clear. */
1102 #define DRA_MASK (OP_MASK | RA_MASK)
1104 /* A DS form instruction. */
1105 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1106 #define DS_MASK DSO (0x3f, 3)
1108 /* An M form instruction. */
1109 #define M(op, rc) (OP (op) | ((rc) & 1))
1110 #define M_MASK M (0x3f, 1)
1112 /* An M form instruction with the ME field specified. */
1113 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1115 /* An M_MASK with the MB and ME fields fixed. */
1116 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1118 /* An M_MASK with the SH and ME fields fixed. */
1119 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1121 /* An MD form instruction. */
1122 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1123 #define MD_MASK MD (0x3f, 0x7, 1)
1125 /* An MD_MASK with the MB field fixed. */
1126 #define MDMB_MASK (MD_MASK | MB6_MASK)
1128 /* An MD_MASK with the SH field fixed. */
1129 #define MDSH_MASK (MD_MASK | SH6_MASK)
1131 /* An MDS form instruction. */
1132 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1133 #define MDS_MASK MDS (0x3f, 0xf, 1)
1135 /* An MDS_MASK with the MB field fixed. */
1136 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1138 /* An SC form instruction. */
1139 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1140 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1142 /* An VX form instruction. */
1143 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1145 /* The mask for an VX form instruction. */
1146 #define VX_MASK VX(0x3f, 0x7ff)
1148 /* An VA form instruction. */
1149 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f))
1151 /* The mask for an VA form instruction. */
1152 #define VXA_MASK VXA(0x3f, 0x7f)
1154 /* An VXR form instruction. */
1155 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1157 /* The mask for a VXR form instruction. */
1158 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1160 /* An X form instruction. */
1161 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1163 /* An X form instruction with the RC bit specified. */
1164 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1166 /* The mask for an X form instruction. */
1167 #define X_MASK XRC (0x3f, 0x3ff, 1)
1169 /* An X_MASK with the RA field fixed. */
1170 #define XRA_MASK (X_MASK | RA_MASK)
1172 /* An X_MASK with the RB field fixed. */
1173 #define XRB_MASK (X_MASK | RB_MASK)
1175 /* An X_MASK with the RT field fixed. */
1176 #define XRT_MASK (X_MASK | RT_MASK)
1178 /* An X_MASK with the RA and RB fields fixed. */
1179 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1181 /* An X_MASK with the RT and RA fields fixed. */
1182 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1184 /* An X form comparison instruction. */
1185 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1187 /* The mask for an X form comparison instruction. */
1188 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1190 /* The mask for an X form comparison instruction with the L field
1192 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1194 /* An X form trap instruction with the TO field specified. */
1195 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1196 #define XTO_MASK (X_MASK | TO_MASK)
1198 /* An X form tlb instruction with the SH field specified. */
1199 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1200 #define XTLB_MASK (X_MASK | SH_MASK)
1202 /* An XFL form instruction. */
1203 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1204 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1206 /* An XL form instruction with the LK field set to 0. */
1207 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1209 /* An XL form instruction which uses the LK field. */
1210 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1212 /* The mask for an XL form instruction. */
1213 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1215 /* An XL form instruction which explicitly sets the BO field. */
1216 #define XLO(op, bo, xop, lk) \
1217 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1218 #define XLO_MASK (XL_MASK | BO_MASK)
1220 /* An XL form instruction which explicitly sets the y bit of the BO
1222 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1223 #define XLYLK_MASK (XL_MASK | Y_MASK)
1225 /* An XL form instruction which sets the BO field and the condition
1226 bits of the BI field. */
1227 #define XLOCB(op, bo, cb, xop, lk) \
1228 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1229 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1231 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1232 #define XLBB_MASK (XL_MASK | BB_MASK)
1233 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1234 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1236 /* An XL_MASK with the BO and BB fields fixed. */
1237 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1239 /* An XL_MASK with the BO, BI and BB fields fixed. */
1240 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1242 /* An XO form instruction. */
1243 #define XO(op, xop, oe, rc) \
1244 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1245 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1247 /* An XO_MASK with the RB field fixed. */
1248 #define XORB_MASK (XO_MASK | RB_MASK)
1250 /* An XS form instruction. */
1251 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1252 #define XS_MASK XS (0x3f, 0x1ff, 1)
1254 /* A mask for the FXM version of an XFX form instruction. */
1255 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1257 /* An XFX form instruction with the FXM field filled in. */
1258 #define XFXM(op, xop, fxm) \
1259 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1261 /* An XFX form instruction with the SPR field filled in. */
1262 #define XSPR(op, xop, spr) \
1263 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1264 #define XSPR_MASK (X_MASK | SPR_MASK)
1266 /* An XFX form instruction with the SPR field filled in except for the
1268 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1270 /* An XFX form instruction with the SPR field filled in except for the
1272 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1274 /* An X form instruction with everything filled in except the E field. */
1275 #define XE_MASK (0xffff7fff)
1277 /* The BO encodings used in extended conditional branch mnemonics. */
1278 #define BODNZF (0x0)
1279 #define BODNZFP (0x1)
1281 #define BODZFP (0x3)
1284 #define BODNZT (0x8)
1285 #define BODNZTP (0x9)
1287 #define BODZTP (0xb)
1290 #define BODNZ (0x10)
1291 #define BODNZP (0x11)
1293 #define BODZP (0x13)
1296 /* The BI condition bit encodings used in extended conditional branch
1303 /* The TO encodings used in extended trap mnemonics. */
1320 /* Smaller names for the flags so each entry in the opcodes table will
1321 fit on a single line. */
1323 #define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1324 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1325 #define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
1326 #define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
1327 #define PPCONLY PPC_OPCODE_PPC
1329 #define PPC405 PPC403
1332 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
1333 #define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1334 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1335 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1336 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1337 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1338 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1339 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1340 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1341 #define MFDEC1 PPC_OPCODE_POWER
1342 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
1344 /* The opcode table.
1346 The format of the opcode table is:
1348 NAME OPCODE MASK FLAGS { OPERANDS }
1350 NAME is the name of the instruction.
1351 OPCODE is the instruction opcode.
1352 MASK is the opcode mask; this is used to tell the disassembler
1353 which bits in the actual opcode must match OPCODE.
1354 FLAGS are flags indicated what processors support the instruction.
1355 OPERANDS is the list of operands.
1357 The disassembler reads the table in order and prints the first
1358 instruction which matches, so this table is sorted to put more
1359 specific instructions before more general instructions. It is also
1360 sorted by major opcode. */
1362 const struct powerpc_opcode powerpc_opcodes
[] = {
1363 { "tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1364 { "tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1365 { "tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1366 { "tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1367 { "tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1368 { "tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1369 { "tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1370 { "tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1371 { "tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1372 { "tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1373 { "tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1374 { "tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1375 { "tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1376 { "tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1377 { "tdi", OP(2), OP_MASK
, PPC64
, { TO
, RA
, SI
} },
1379 { "twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1380 { "tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1381 { "twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1382 { "tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1383 { "tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1384 { "teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1385 { "twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1386 { "tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1387 { "twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1388 { "tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1389 { "twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1390 { "tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1391 { "twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1392 { "tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1393 { "twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1394 { "tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1395 { "twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1396 { "tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1397 { "twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1398 { "tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1399 { "twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1400 { "tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1401 { "twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1402 { "tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1403 { "twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1404 { "tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1405 { "twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1406 { "tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1407 { "twi", OP(3), OP_MASK
, PPCCOM
, { TO
, RA
, SI
} },
1408 { "ti", OP(3), OP_MASK
, PWRCOM
, { TO
, RA
, SI
} },
1410 { "macchw", XO(4,172,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1411 { "macchw.", XO(4,172,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1412 { "macchwo", XO(4,172,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1413 { "macchwo.", XO(4,172,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1414 { "macchws", XO(4,236,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1415 { "macchws.", XO(4,236,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1416 { "macchwso", XO(4,236,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1417 { "macchwso.", XO(4,236,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1418 { "macchwsu", XO(4,204,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1419 { "macchwsu.", XO(4,204,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1420 { "macchwsuo", XO(4,204,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1421 { "macchwsuo.", XO(4,204,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1422 { "macchwu", XO(4,140,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1423 { "macchwu.", XO(4,140,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1424 { "macchwuo", XO(4,140,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1425 { "macchwuo.", XO(4,140,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1426 { "machhw", XO(4,44,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1427 { "machhw.", XO(4,44,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1428 { "machhwo", XO(4,44,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1429 { "machhwo.", XO(4,44,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1430 { "machhws", XO(4,108,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1431 { "machhws.", XO(4,108,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1432 { "machhwso", XO(4,108,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1433 { "machhwso.", XO(4,108,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1434 { "machhwsu", XO(4,76,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1435 { "machhwsu.", XO(4,76,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1436 { "machhwsuo", XO(4,76,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1437 { "machhwsuo.", XO(4,76,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1438 { "machhwu", XO(4,12,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1439 { "machhwu.", XO(4,12,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1440 { "machhwuo", XO(4,12,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1441 { "machhwuo.", XO(4,12,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1442 { "maclhw", XO(4,428,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1443 { "maclhw.", XO(4,428,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1444 { "maclhwo", XO(4,428,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1445 { "maclhwo.", XO(4,428,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1446 { "maclhws", XO(4,492,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1447 { "maclhws.", XO(4,492,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1448 { "maclhwso", XO(4,492,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1449 { "maclhwso.", XO(4,492,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1450 { "maclhwsu", XO(4,460,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1451 { "maclhwsu.", XO(4,460,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1452 { "maclhwsuo", XO(4,460,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1453 { "maclhwsuo.", XO(4,460,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1454 { "maclhwu", XO(4,396,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1455 { "maclhwu.", XO(4,396,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1456 { "maclhwuo", XO(4,396,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1457 { "maclhwuo.", XO(4,396,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1458 { "mulchw", XRC(4,168,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1459 { "mulchw.", XRC(4,168,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1460 { "mulchwu", XRC(4,136,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1461 { "mulchwu.", XRC(4,136,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1462 { "mulhhw", XRC(4,40,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1463 { "mulhhw.", XRC(4,40,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1464 { "mulhhwu", XRC(4,8,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1465 { "mulhhwu.", XRC(4,8,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1466 { "mullhw", XRC(4,424,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1467 { "mullhw.", XRC(4,424,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1468 { "mullhwu", XRC(4,392,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1469 { "mullhwu.", XRC(4,392,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1470 { "nmacchw", XO(4,174,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1471 { "nmacchw.", XO(4,174,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1472 { "nmacchwo", XO(4,174,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1473 { "nmacchwo.", XO(4,174,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1474 { "nmacchws", XO(4,238,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1475 { "nmacchws.", XO(4,238,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1476 { "nmacchwso", XO(4,238,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1477 { "nmacchwso.", XO(4,238,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1478 { "nmachhw", XO(4,46,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1479 { "nmachhw.", XO(4,46,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1480 { "nmachhwo", XO(4,46,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1481 { "nmachhwo.", XO(4,46,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1482 { "nmachhws", XO(4,110,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1483 { "nmachhws.", XO(4,110,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1484 { "nmachhwso", XO(4,110,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1485 { "nmachhwso.", XO(4,110,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1486 { "nmaclhw", XO(4,430,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1487 { "nmaclhw.", XO(4,430,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1488 { "nmaclhwo", XO(4,430,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1489 { "nmaclhwo.", XO(4,430,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1490 { "nmaclhws", XO(4,494,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1491 { "nmaclhws.", XO(4,494,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1492 { "nmaclhwso", XO(4,494,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1493 { "nmaclhwso.", XO(4,494,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1494 { "mfvscr", VX(4, 1540), VX_MASK
, PPCVEC
, { VD
} },
1495 { "mtvscr", VX(4, 1604), VX_MASK
, PPCVEC
, { VD
} },
1496 { "vaddcuw", VX(4, 384), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1497 { "vaddfp", VX(4, 10), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1498 { "vaddsbs", VX(4, 768), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1499 { "vaddshs", VX(4, 832), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1500 { "vaddsws", VX(4, 896), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1501 { "vaddubm", VX(4, 0), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1502 { "vaddubs", VX(4, 512), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1503 { "vadduhm", VX(4, 64), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1504 { "vadduhs", VX(4, 576), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1505 { "vadduwm", VX(4, 128), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1506 { "vadduws", VX(4, 640), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1507 { "vand", VX(4, 1028), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1508 { "vandc", VX(4, 1092), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1509 { "vavgsb", VX(4, 1282), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1510 { "vavgsh", VX(4, 1346), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1511 { "vavgsw", VX(4, 1410), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1512 { "vavgub", VX(4, 1026), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1513 { "vavguh", VX(4, 1090), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1514 { "vavguw", VX(4, 1154), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1515 { "vcfsx", VX(4, 842), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1516 { "vcfux", VX(4, 778), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1517 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1518 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1519 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1520 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1521 { "vcmpequb", VXR(4, 6, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1522 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1523 { "vcmpequh", VXR(4, 70, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1524 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1525 { "vcmpequw", VXR(4, 134, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1526 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1527 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1528 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1529 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1530 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1531 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1532 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1533 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1534 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1535 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1536 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1537 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1538 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1539 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1540 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1541 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1542 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1543 { "vctsxs", VX(4, 970), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1544 { "vctuxs", VX(4, 906), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1545 { "vexptefp", VX(4, 394), VX_MASK
, PPCVEC
, { VD
, VB
} },
1546 { "vlogefp", VX(4, 458), VX_MASK
, PPCVEC
, { VD
, VB
} },
1547 { "vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1548 { "vmaxfp", VX(4, 1034), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1549 { "vmaxsb", VX(4, 258), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1550 { "vmaxsh", VX(4, 322), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1551 { "vmaxsw", VX(4, 386), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1552 { "vmaxub", VX(4, 2), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1553 { "vmaxuh", VX(4, 66), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1554 { "vmaxuw", VX(4, 130), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1555 { "vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1556 { "vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1557 { "vminfp", VX(4, 1098), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1558 { "vminsb", VX(4, 770), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1559 { "vminsh", VX(4, 834), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1560 { "vminsw", VX(4, 898), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1561 { "vminub", VX(4, 514), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1562 { "vminuh", VX(4, 578), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1563 { "vminuw", VX(4, 642), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1564 { "vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1565 { "vmrghb", VX(4, 12), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1566 { "vmrghh", VX(4, 76), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1567 { "vmrghw", VX(4, 140), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1568 { "vmrglb", VX(4, 268), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1569 { "vmrglh", VX(4, 332), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1570 { "vmrglw", VX(4, 396), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1571 { "vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1572 { "vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1573 { "vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1574 { "vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1575 { "vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1576 { "vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1577 { "vmulesb", VX(4, 776), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1578 { "vmulesh", VX(4, 840), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1579 { "vmuleub", VX(4, 520), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1580 { "vmuleuh", VX(4, 584), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1581 { "vmulosb", VX(4, 264), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1582 { "vmulosh", VX(4, 328), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1583 { "vmuloub", VX(4, 8), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1584 { "vmulouh", VX(4, 72), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1585 { "vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
, { VD
, VA
, VC
, VB
} },
1586 { "vnor", VX(4, 1284), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1587 { "vor", VX(4, 1156), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1588 { "vperm", VXA(4, 43), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1589 { "vpkpx", VX(4, 782), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1590 { "vpkshss", VX(4, 398), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1591 { "vpkshus", VX(4, 270), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1592 { "vpkswss", VX(4, 462), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1593 { "vpkswus", VX(4, 334), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1594 { "vpkuhum", VX(4, 14), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1595 { "vpkuhus", VX(4, 142), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1596 { "vpkuwum", VX(4, 78), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1597 { "vpkuwus", VX(4, 206), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1598 { "vrefp", VX(4, 266), VX_MASK
, PPCVEC
, { VD
, VB
} },
1599 { "vrfim", VX(4, 714), VX_MASK
, PPCVEC
, { VD
, VB
} },
1600 { "vrfin", VX(4, 522), VX_MASK
, PPCVEC
, { VD
, VB
} },
1601 { "vrfip", VX(4, 650), VX_MASK
, PPCVEC
, { VD
, VB
} },
1602 { "vrfiz", VX(4, 586), VX_MASK
, PPCVEC
, { VD
, VB
} },
1603 { "vrlb", VX(4, 4), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1604 { "vrlh", VX(4, 68), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1605 { "vrlw", VX(4, 132), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1606 { "vrsqrtefp", VX(4, 330), VX_MASK
, PPCVEC
, { VD
, VB
} },
1607 { "vsel", VXA(4, 42), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1608 { "vsl", VX(4, 452), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1609 { "vslb", VX(4, 260), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1610 { "vsldoi", VXA(4, 44), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, SHB
} },
1611 { "vslh", VX(4, 324), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1612 { "vslo", VX(4, 1036), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1613 { "vslw", VX(4, 388), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1614 { "vspltb", VX(4, 524), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1615 { "vsplth", VX(4, 588), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1616 { "vspltisb", VX(4, 780), VX_MASK
, PPCVEC
, { VD
, SIMM
} },
1617 { "vspltish", VX(4, 844), VX_MASK
, PPCVEC
, { VD
, SIMM
} },
1618 { "vspltisw", VX(4, 908), VX_MASK
, PPCVEC
, { VD
, SIMM
} },
1619 { "vspltw", VX(4, 652), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1620 { "vsr", VX(4, 708), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1621 { "vsrab", VX(4, 772), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1622 { "vsrah", VX(4, 836), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1623 { "vsraw", VX(4, 900), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1624 { "vsrb", VX(4, 516), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1625 { "vsrh", VX(4, 580), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1626 { "vsro", VX(4, 1100), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1627 { "vsrw", VX(4, 644), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1628 { "vsubcuw", VX(4, 1408), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1629 { "vsubfp", VX(4, 74), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1630 { "vsubsbs", VX(4, 1792), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1631 { "vsubshs", VX(4, 1856), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1632 { "vsubsws", VX(4, 1920), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1633 { "vsububm", VX(4, 1024), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1634 { "vsububs", VX(4, 1536), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1635 { "vsubuhm", VX(4, 1088), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1636 { "vsubuhs", VX(4, 1600), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1637 { "vsubuwm", VX(4, 1152), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1638 { "vsubuws", VX(4, 1664), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1639 { "vsumsws", VX(4, 1928), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1640 { "vsum2sws", VX(4, 1672), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1641 { "vsum4sbs", VX(4, 1800), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1642 { "vsum4shs", VX(4, 1608), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1643 { "vsum4ubs", VX(4, 1544), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1644 { "vupkhpx", VX(4, 846), VX_MASK
, PPCVEC
, { VD
, VB
} },
1645 { "vupkhsb", VX(4, 526), VX_MASK
, PPCVEC
, { VD
, VB
} },
1646 { "vupkhsh", VX(4, 590), VX_MASK
, PPCVEC
, { VD
, VB
} },
1647 { "vupklpx", VX(4, 974), VX_MASK
, PPCVEC
, { VD
, VB
} },
1648 { "vupklsb", VX(4, 654), VX_MASK
, PPCVEC
, { VD
, VB
} },
1649 { "vupklsh", VX(4, 718), VX_MASK
, PPCVEC
, { VD
, VB
} },
1650 { "vxor", VX(4, 1220), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1652 { "mulli", OP(7), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1653 { "muli", OP(7), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
1655 { "subfic", OP(8), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1656 { "sfi", OP(8), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
1658 { "dozi", OP(9), OP_MASK
, M601
, { RT
, RA
, SI
} },
1660 { "cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, { OBF
, RA
, UI
} },
1661 { "cmpldi", OPL(10,1), OPL_MASK
, PPC64
, { OBF
, RA
, UI
} },
1662 { "cmpli", OP(10), OP_MASK
, PPCONLY
, { BF
, L
, RA
, UI
} },
1663 { "cmpli", OP(10), OP_MASK
, PWRCOM
, { BF
, RA
, UI
} },
1665 { "cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, { OBF
, RA
, SI
} },
1666 { "cmpdi", OPL(11,1), OPL_MASK
, PPC64
, { OBF
, RA
, SI
} },
1667 { "cmpi", OP(11), OP_MASK
, PPCONLY
, { BF
, L
, RA
, SI
} },
1668 { "cmpi", OP(11), OP_MASK
, PWRCOM
, { BF
, RA
, SI
} },
1670 { "addic", OP(12), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1671 { "ai", OP(12), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
1672 { "subic", OP(12), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
1674 { "addic.", OP(13), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1675 { "ai.", OP(13), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
1676 { "subic.", OP(13), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
1678 { "li", OP(14), DRA_MASK
, PPCCOM
, { RT
, SI
} },
1679 { "lil", OP(14), DRA_MASK
, PWRCOM
, { RT
, SI
} },
1680 { "addi", OP(14), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1681 { "cal", OP(14), OP_MASK
, PWRCOM
, { RT
, D
, RA
} },
1682 { "subi", OP(14), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
1683 { "la", OP(14), OP_MASK
, PPCCOM
, { RT
, D
, RA
} },
1685 { "lis", OP(15), DRA_MASK
, PPCCOM
, { RT
, SISIGNOPT
} },
1686 { "liu", OP(15), DRA_MASK
, PWRCOM
, { RT
, SISIGNOPT
} },
1687 { "addis", OP(15), OP_MASK
, PPCCOM
, { RT
,RA
,SISIGNOPT
} },
1688 { "cau", OP(15), OP_MASK
, PWRCOM
, { RT
,RA
,SISIGNOPT
} },
1689 { "subis", OP(15), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
1691 { "bdnz-", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PPCCOM
, { BDM
} },
1692 { "bdnz+", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PPCCOM
, { BDP
} },
1693 { "bdnz", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PPCCOM
, { BD
} },
1694 { "bdn", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PWRCOM
, { BD
} },
1695 { "bdnzl-", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PPCCOM
, { BDM
} },
1696 { "bdnzl+", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PPCCOM
, { BDP
} },
1697 { "bdnzl", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PPCCOM
, { BD
} },
1698 { "bdnl", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PWRCOM
, { BD
} },
1699 { "bdnza-", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PPCCOM
, { BDMA
} },
1700 { "bdnza+", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PPCCOM
, { BDPA
} },
1701 { "bdnza", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PPCCOM
, { BDA
} },
1702 { "bdna", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PWRCOM
, { BDA
} },
1703 { "bdnzla-", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PPCCOM
, { BDMA
} },
1704 { "bdnzla+", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PPCCOM
, { BDPA
} },
1705 { "bdnzla", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PPCCOM
, { BDA
} },
1706 { "bdnla", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PWRCOM
, { BDA
} },
1707 { "bdz-", BBO(16,BODZ
,0,0), BBOYBI_MASK
, PPCCOM
, { BDM
} },
1708 { "bdz+", BBO(16,BODZ
,0,0), BBOYBI_MASK
, PPCCOM
, { BDP
} },
1709 { "bdz", BBO(16,BODZ
,0,0), BBOYBI_MASK
, COM
, { BD
} },
1710 { "bdzl-", BBO(16,BODZ
,0,1), BBOYBI_MASK
, PPCCOM
, { BDM
} },
1711 { "bdzl+", BBO(16,BODZ
,0,1), BBOYBI_MASK
, PPCCOM
, { BDP
} },
1712 { "bdzl", BBO(16,BODZ
,0,1), BBOYBI_MASK
, COM
, { BD
} },
1713 { "bdza-", BBO(16,BODZ
,1,0), BBOYBI_MASK
, PPCCOM
, { BDMA
} },
1714 { "bdza+", BBO(16,BODZ
,1,0), BBOYBI_MASK
, PPCCOM
, { BDPA
} },
1715 { "bdza", BBO(16,BODZ
,1,0), BBOYBI_MASK
, COM
, { BDA
} },
1716 { "bdzla-", BBO(16,BODZ
,1,1), BBOYBI_MASK
, PPCCOM
, { BDMA
} },
1717 { "bdzla+", BBO(16,BODZ
,1,1), BBOYBI_MASK
, PPCCOM
, { BDPA
} },
1718 { "bdzla", BBO(16,BODZ
,1,1), BBOYBI_MASK
, COM
, { BDA
} },
1719 { "blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1720 { "blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1721 { "blt", BBOCB(16,BOT
,CBLT
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1722 { "bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1723 { "bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1724 { "bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1725 { "blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1726 { "blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1727 { "blta", BBOCB(16,BOT
,CBLT
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1728 { "bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1729 { "bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1730 { "bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1731 { "bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1732 { "bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1733 { "bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1734 { "bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1735 { "bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1736 { "bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1737 { "bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1738 { "bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1739 { "bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1740 { "bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1741 { "bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1742 { "bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1743 { "beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1744 { "beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1745 { "beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1746 { "beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1747 { "beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1748 { "beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1749 { "beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1750 { "beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1751 { "beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1752 { "beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1753 { "beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1754 { "beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1755 { "bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1756 { "bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1757 { "bso", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1758 { "bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1759 { "bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1760 { "bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1761 { "bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1762 { "bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1763 { "bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1764 { "bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1765 { "bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1766 { "bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1767 { "bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1768 { "bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1769 { "bun", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BD
} },
1770 { "bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1771 { "bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1772 { "bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BD
} },
1773 { "buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1774 { "buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1775 { "buna", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDA
} },
1776 { "bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1777 { "bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1778 { "bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDA
} },
1779 { "bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1780 { "bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1781 { "bge", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1782 { "bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1783 { "bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1784 { "bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1785 { "bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1786 { "bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1787 { "bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1788 { "bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1789 { "bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1790 { "bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1791 { "bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1792 { "bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1793 { "bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1794 { "bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1795 { "bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1796 { "bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1797 { "bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1798 { "bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1799 { "bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1800 { "bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1801 { "bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1802 { "bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1803 { "ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1804 { "ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1805 { "ble", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1806 { "blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1807 { "blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1808 { "blel", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1809 { "blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1810 { "blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1811 { "blea", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1812 { "blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1813 { "blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1814 { "blela", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1815 { "bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1816 { "bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1817 { "bng", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1818 { "bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1819 { "bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1820 { "bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1821 { "bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1822 { "bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1823 { "bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1824 { "bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1825 { "bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1826 { "bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1827 { "bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1828 { "bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1829 { "bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1830 { "bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1831 { "bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1832 { "bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1833 { "bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1834 { "bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1835 { "bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1836 { "bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1837 { "bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1838 { "bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1839 { "bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1840 { "bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1841 { "bns", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, COM
, { CR
, BD
} },
1842 { "bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1843 { "bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1844 { "bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, COM
, { CR
, BD
} },
1845 { "bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1846 { "bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1847 { "bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1848 { "bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1849 { "bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1850 { "bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, COM
, { CR
, BDA
} },
1851 { "bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1852 { "bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1853 { "bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPCCOM
, { CR
, BD
} },
1854 { "bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDM
} },
1855 { "bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDP
} },
1856 { "bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPCCOM
, { CR
, BD
} },
1857 { "bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1858 { "bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1859 { "bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPCCOM
, { CR
, BDA
} },
1860 { "bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDMA
} },
1861 { "bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDPA
} },
1862 { "bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPCCOM
, { CR
, BDA
} },
1863 { "bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1864 { "bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1865 { "bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1866 { "bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1867 { "bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1868 { "bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1869 { "bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1870 { "bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1871 { "bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1872 { "bdnztla-",BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1873 { "bdnztla+",BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1874 { "bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1875 { "bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1876 { "bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1877 { "bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1878 { "bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1879 { "bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1880 { "bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1881 { "bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1882 { "bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1883 { "bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1884 { "bdnzfla-",BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1885 { "bdnzfla+",BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1886 { "bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1887 { "bt-", BBO(16,BOT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1888 { "bt+", BBO(16,BOT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1889 { "bt", BBO(16,BOT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1890 { "bbt", BBO(16,BOT
,0,0), BBOY_MASK
, PWRCOM
, { BI
, BD
} },
1891 { "btl-", BBO(16,BOT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1892 { "btl+", BBO(16,BOT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1893 { "btl", BBO(16,BOT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1894 { "bbtl", BBO(16,BOT
,0,1), BBOY_MASK
, PWRCOM
, { BI
, BD
} },
1895 { "bta-", BBO(16,BOT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1896 { "bta+", BBO(16,BOT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1897 { "bta", BBO(16,BOT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1898 { "bbta", BBO(16,BOT
,1,0), BBOY_MASK
, PWRCOM
, { BI
, BDA
} },
1899 { "btla-", BBO(16,BOT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1900 { "btla+", BBO(16,BOT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1901 { "btla", BBO(16,BOT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1902 { "bbtla", BBO(16,BOT
,1,1), BBOY_MASK
, PWRCOM
, { BI
, BDA
} },
1903 { "bf-", BBO(16,BOF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1904 { "bf+", BBO(16,BOF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1905 { "bf", BBO(16,BOF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1906 { "bbf", BBO(16,BOF
,0,0), BBOY_MASK
, PWRCOM
, { BI
, BD
} },
1907 { "bfl-", BBO(16,BOF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1908 { "bfl+", BBO(16,BOF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1909 { "bfl", BBO(16,BOF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1910 { "bbfl", BBO(16,BOF
,0,1), BBOY_MASK
, PWRCOM
, { BI
, BD
} },
1911 { "bfa-", BBO(16,BOF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1912 { "bfa+", BBO(16,BOF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1913 { "bfa", BBO(16,BOF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1914 { "bbfa", BBO(16,BOF
,1,0), BBOY_MASK
, PWRCOM
, { BI
, BDA
} },
1915 { "bfla-", BBO(16,BOF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1916 { "bfla+", BBO(16,BOF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1917 { "bfla", BBO(16,BOF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1918 { "bbfla", BBO(16,BOF
,1,1), BBOY_MASK
, PWRCOM
, { BI
, BDA
} },
1919 { "bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1920 { "bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1921 { "bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1922 { "bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1923 { "bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1924 { "bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1925 { "bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1926 { "bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1927 { "bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1928 { "bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1929 { "bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1930 { "bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1931 { "bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1932 { "bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1933 { "bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1934 { "bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDM
} },
1935 { "bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BDP
} },
1936 { "bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
1937 { "bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1938 { "bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1939 { "bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1940 { "bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDMA
} },
1941 { "bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDPA
} },
1942 { "bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
1943 { "bc-", B(16,0,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDM
} },
1944 { "bc+", B(16,0,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDP
} },
1945 { "bc", B(16,0,0), B_MASK
, COM
, { BO
, BI
, BD
} },
1946 { "bcl-", B(16,0,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDM
} },
1947 { "bcl+", B(16,0,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDP
} },
1948 { "bcl", B(16,0,1), B_MASK
, COM
, { BO
, BI
, BD
} },
1949 { "bca-", B(16,1,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDMA
} },
1950 { "bca+", B(16,1,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDPA
} },
1951 { "bca", B(16,1,0), B_MASK
, COM
, { BO
, BI
, BDA
} },
1952 { "bcla-", B(16,1,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDMA
} },
1953 { "bcla+", B(16,1,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDPA
} },
1954 { "bcla", B(16,1,1), B_MASK
, COM
, { BO
, BI
, BDA
} },
1956 { "sc", SC(17,1,0), 0xffffffff, PPC
, { 0 } },
1957 { "svc", SC(17,0,0), SC_MASK
, POWER
, { LEV
, FL1
, FL2
} },
1958 { "svcl", SC(17,0,1), SC_MASK
, POWER
, { LEV
, FL1
, FL2
} },
1959 { "svca", SC(17,1,0), SC_MASK
, PWRCOM
, { SV
} },
1960 { "svcla", SC(17,1,1), SC_MASK
, POWER
, { SV
} },
1962 { "b", B(18,0,0), B_MASK
, COM
, { LI
} },
1963 { "bl", B(18,0,1), B_MASK
, COM
, { LI
} },
1964 { "ba", B(18,1,0), B_MASK
, COM
, { LIA
} },
1965 { "bla", B(18,1,1), B_MASK
, COM
, { LIA
} },
1967 { "mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, { BF
, BFA
} },
1969 { "blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1970 { "br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, { 0 } },
1971 { "blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1972 { "brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, { 0 } },
1973 { "bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1974 { "bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1975 { "bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1976 { "bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1977 { "bdnzlrl-",XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1978 { "bdnzlrl+",XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1979 { "bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1980 { "bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1981 { "bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1982 { "bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1983 { "bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1984 { "bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
1985 { "bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1986 { "bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1987 { "bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1988 { "bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
1989 { "bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1990 { "bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1991 { "bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1992 { "bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
1993 { "bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1994 { "bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1995 { "bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1996 { "bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
1997 { "bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1998 { "bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
1999 { "bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2000 { "bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2001 { "beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2002 { "beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2003 { "beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2004 { "beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2005 { "beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2006 { "beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2007 { "beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2008 { "beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2009 { "bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2010 { "bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2011 { "bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2012 { "bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2013 { "bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2014 { "bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2015 { "bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2016 { "bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2017 { "bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2018 { "bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2019 { "bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2020 { "bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2021 { "bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2022 { "bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2023 { "bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2024 { "bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2025 { "bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2026 { "bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2027 { "bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2028 { "bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2029 { "bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2030 { "bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2031 { "bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2032 { "bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2033 { "bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2034 { "bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2035 { "bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2036 { "bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2037 { "bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2038 { "bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2039 { "blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2040 { "blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2041 { "blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2042 { "bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2043 { "blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2044 { "blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2045 { "blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2046 { "blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2047 { "bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2048 { "bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2049 { "bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2050 { "bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2051 { "bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2052 { "bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2053 { "bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2054 { "bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2055 { "bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2056 { "bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2057 { "bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2058 { "bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2059 { "bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2060 { "bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2061 { "bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2062 { "bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2063 { "bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2064 { "bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2065 { "bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2066 { "bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2067 { "bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2068 { "bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2069 { "bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2070 { "bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2071 { "bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2072 { "bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2073 { "bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2074 { "bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2075 { "bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2076 { "bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2077 { "btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2078 { "btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2079 { "btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2080 { "bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, { BI
} },
2081 { "btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2082 { "btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2083 { "btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2084 { "bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, { BI
} },
2085 { "bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2086 { "bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2087 { "bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2088 { "bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, { BI
} },
2089 { "bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2090 { "bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2091 { "bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2092 { "bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, { BI
} },
2093 { "bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2094 { "bdnztlr-",XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2095 { "bdnztlr+",XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2096 { "bdnztlrl",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2097 { "bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2098 { "bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
,{ BI
} },
2099 { "bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2100 { "bdnzflr-",XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2101 { "bdnzflr+",XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2102 { "bdnzflrl",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2103 { "bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2104 { "bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
,{ BI
} },
2105 { "bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2106 { "bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2107 { "bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2108 { "bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2109 { "bdztlrl-",XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2110 { "bdztlrl+",XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2111 { "bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2112 { "bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2113 { "bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2114 { "bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2115 { "bdzflrl-",XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2116 { "bdzflrl+",XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2117 { "bclr", XLLK(19,16,0), XLYBB_MASK
, PPCCOM
, { BO
, BI
} },
2118 { "bclrl", XLLK(19,16,1), XLYBB_MASK
, PPCCOM
, { BO
, BI
} },
2119 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2120 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2121 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2122 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2123 { "bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
2124 { "bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
2126 { "rfid", XL(19,18), 0xffffffff, PPC64
, { 0 } },
2128 { "crnot", XL(19,33), XL_MASK
, PPCCOM
, { BT
, BA
, BBA
} },
2129 { "crnor", XL(19,33), XL_MASK
, COM
, { BT
, BA
, BB
} },
2131 { "rfi", XL(19,50), 0xffffffff, COM
, { 0 } },
2132 { "rfci", XL(19,51), 0xffffffff, PPC403
, { 0 } },
2134 { "rfsvc", XL(19,82), 0xffffffff, POWER
, { 0 } },
2136 { "crandc", XL(19,129), XL_MASK
, COM
, { BT
, BA
, BB
} },
2138 { "isync", XL(19,150), 0xffffffff, PPCCOM
, { 0 } },
2139 { "ics", XL(19,150), 0xffffffff, PWRCOM
, { 0 } },
2141 { "crclr", XL(19,193), XL_MASK
, PPCCOM
, { BT
, BAT
, BBA
} },
2142 { "crxor", XL(19,193), XL_MASK
, COM
, { BT
, BA
, BB
} },
2144 { "crnand", XL(19,225), XL_MASK
, COM
, { BT
, BA
, BB
} },
2146 { "crand", XL(19,257), XL_MASK
, COM
, { BT
, BA
, BB
} },
2148 { "crset", XL(19,289), XL_MASK
, PPCCOM
, { BT
, BAT
, BBA
} },
2149 { "creqv", XL(19,289), XL_MASK
, COM
, { BT
, BA
, BB
} },
2151 { "crorc", XL(19,417), XL_MASK
, COM
, { BT
, BA
, BB
} },
2153 { "crmove", XL(19,449), XL_MASK
, PPCCOM
, { BT
, BA
, BBA
} },
2154 { "cror", XL(19,449), XL_MASK
, COM
, { BT
, BA
, BB
} },
2156 { "bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, { 0 } },
2157 { "bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, { 0 } },
2158 { "bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2159 { "bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2160 { "bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2161 { "bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2162 { "bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2163 { "bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2164 { "bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2165 { "bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2166 { "bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2167 { "bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2168 { "bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2169 { "bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2170 { "beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2171 { "beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2172 { "beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2173 { "beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2174 { "beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2175 { "beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2176 { "bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2177 { "bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2178 { "bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2179 { "bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2180 { "bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2181 { "bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2182 { "bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2183 { "bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2184 { "bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2185 { "bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2186 { "bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2187 { "bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2188 { "bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2189 { "bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2190 { "bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2191 { "bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2192 { "bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2193 { "bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2194 { "bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2195 { "bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2196 { "bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2197 { "bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2198 { "bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2199 { "bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2200 { "blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2201 { "blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2202 { "blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2203 { "blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2204 { "blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2205 { "blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2206 { "bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2207 { "bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2208 { "bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2209 { "bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2210 { "bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2211 { "bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2212 { "bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2213 { "bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2214 { "bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2215 { "bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2216 { "bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2217 { "bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2218 { "bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2219 { "bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2220 { "bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2221 { "bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2222 { "bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2223 { "bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2224 { "bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2225 { "bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2226 { "bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2227 { "bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2228 { "bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2229 { "bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2230 { "btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2231 { "btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2232 { "btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2233 { "btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2234 { "btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2235 { "btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2236 { "bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2237 { "bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2238 { "bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2239 { "bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2240 { "bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2241 { "bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2242 { "bcctr", XLLK(19,528,0), XLYBB_MASK
, PPCCOM
, { BO
, BI
} },
2243 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2244 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2245 { "bcctrl", XLLK(19,528,1), XLYBB_MASK
, PPCCOM
, { BO
, BI
} },
2246 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2247 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2248 { "bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
2249 { "bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
2251 { "rlwimi", M(20,0), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2252 { "rlimi", M(20,0), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2254 { "rlwimi.", M(20,1), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2255 { "rlimi.", M(20,1), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2257 { "rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, { RA
, RS
, SH
} },
2258 { "clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, { RA
, RS
, MB
} },
2259 { "rlwinm", M(21,0), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2260 { "rlinm", M(21,0), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2261 { "rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, { RA
,RS
,SH
} },
2262 { "clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, { RA
, RS
, MB
} },
2263 { "rlwinm.", M(21,1), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2264 { "rlinm.", M(21,1), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2266 { "rlmi", M(22,0), M_MASK
, M601
, { RA
,RS
,RB
,MBE
,ME
} },
2267 { "rlmi.", M(22,1), M_MASK
, M601
, { RA
,RS
,RB
,MBE
,ME
} },
2269 { "rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, { RA
, RS
, RB
} },
2270 { "rlwnm", M(23,0), M_MASK
, PPCCOM
, { RA
,RS
,RB
,MBE
,ME
} },
2271 { "rlnm", M(23,0), M_MASK
, PWRCOM
, { RA
,RS
,RB
,MBE
,ME
} },
2272 { "rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, { RA
, RS
, RB
} },
2273 { "rlwnm.", M(23,1), M_MASK
, PPCCOM
, { RA
,RS
,RB
,MBE
,ME
} },
2274 { "rlnm.", M(23,1), M_MASK
, PWRCOM
, { RA
,RS
,RB
,MBE
,ME
} },
2276 { "nop", OP(24), 0xffffffff, PPCCOM
, { 0 } },
2277 { "ori", OP(24), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2278 { "oril", OP(24), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2280 { "oris", OP(25), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2281 { "oriu", OP(25), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2283 { "xori", OP(26), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2284 { "xoril", OP(26), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2286 { "xoris", OP(27), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2287 { "xoriu", OP(27), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2289 { "andi.", OP(28), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2290 { "andil.", OP(28), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2292 { "andis.", OP(29), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2293 { "andiu.", OP(29), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2295 { "rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, { RA
, RS
, SH6
} },
2296 { "clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, { RA
, RS
, MB6
} },
2297 { "rldicl", MD(30,0,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2298 { "rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, { RA
, RS
, SH6
} },
2299 { "clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, { RA
, RS
, MB6
} },
2300 { "rldicl.", MD(30,0,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2302 { "rldicr", MD(30,1,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, ME6
} },
2303 { "rldicr.", MD(30,1,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, ME6
} },
2305 { "rldic", MD(30,2,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2306 { "rldic.", MD(30,2,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2308 { "rldimi", MD(30,3,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2309 { "rldimi.", MD(30,3,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2311 { "rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, { RA
, RS
, RB
} },
2312 { "rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, { RA
, RS
, RB
, MB6
} },
2313 { "rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, { RA
, RS
, RB
} },
2314 { "rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, { RA
, RS
, RB
, MB6
} },
2316 { "rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, { RA
, RS
, RB
, ME6
} },
2317 { "rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, { RA
, RS
, RB
, ME6
} },
2319 { "cmpw", XCMPL(31,0,0), XCMPL_MASK
, PPCCOM
, { OBF
, RA
, RB
} },
2320 { "cmpd", XCMPL(31,0,1), XCMPL_MASK
, PPC64
, { OBF
, RA
, RB
} },
2321 { "cmp", X(31,0), XCMP_MASK
, PPCONLY
, { BF
, L
, RA
, RB
} },
2322 { "cmp", X(31,0), XCMPL_MASK
, PWRCOM
, { BF
, RA
, RB
} },
2324 { "twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2325 { "tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2326 { "twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2327 { "tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2328 { "tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2329 { "teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2330 { "twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2331 { "tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2332 { "twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2333 { "tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2334 { "twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2335 { "tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2336 { "twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2337 { "tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2338 { "twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2339 { "tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2340 { "twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2341 { "tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2342 { "twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2343 { "tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2344 { "twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2345 { "tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2346 { "twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2347 { "tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2348 { "twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2349 { "tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2350 { "twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2351 { "tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2352 { "trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
, { 0 } },
2353 { "tw", X(31,4), X_MASK
, PPCCOM
, { TO
, RA
, RB
} },
2354 { "t", X(31,4), X_MASK
, PWRCOM
, { TO
, RA
, RB
} },
2356 { "subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2357 { "sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2358 { "subc", XO(31,8,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2359 { "subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2360 { "sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2361 { "subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, { RT
, RB
, RA
} },
2362 { "subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2363 { "sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2364 { "subco", XO(31,8,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2365 { "subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2366 { "sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2367 { "subco.", XO(31,8,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2369 { "mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2370 { "mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2372 { "addc", XO(31,10,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2373 { "a", XO(31,10,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2374 { "addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2375 { "a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2376 { "addco", XO(31,10,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2377 { "ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2378 { "addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2379 { "ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2381 { "mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2382 { "mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2384 { "mfcr", X(31,19), XRARB_MASK
, COM
, { RT
} },
2386 { "lwarx", X(31,20), X_MASK
, PPC
, { RT
, RA
, RB
} },
2388 { "ldx", X(31,21), X_MASK
, PPC64
, { RT
, RA
, RB
} },
2390 { "lwzx", X(31,23), X_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2391 { "lx", X(31,23), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2393 { "slw", XRC(31,24,0), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
2394 { "sl", XRC(31,24,0), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
2395 { "slw.", XRC(31,24,1), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
2396 { "sl.", XRC(31,24,1), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
2398 { "cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
, { RA
, RS
} },
2399 { "cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, { RA
, RS
} },
2400 { "cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
, { RA
, RS
} },
2401 { "cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, { RA
, RS
} },
2403 { "sld", XRC(31,27,0), X_MASK
, PPC64
, { RA
, RS
, RB
} },
2404 { "sld.", XRC(31,27,1), X_MASK
, PPC64
, { RA
, RS
, RB
} },
2406 { "and", XRC(31,28,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2407 { "and.", XRC(31,28,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2409 { "maskg", XRC(31,29,0), X_MASK
, M601
, { RA
, RS
, RB
} },
2410 { "maskg.", XRC(31,29,1), X_MASK
, M601
, { RA
, RS
, RB
} },
2412 { "cmplw", XCMPL(31,32,0), XCMPL_MASK
, PPCCOM
, { OBF
, RA
, RB
} },
2413 { "cmpld", XCMPL(31,32,1), XCMPL_MASK
, PPC64
, { OBF
, RA
, RB
} },
2414 { "cmpl", X(31,32), XCMP_MASK
, PPCONLY
, { BF
, L
, RA
, RB
} },
2415 { "cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, { BF
, RA
, RB
} },
2417 { "subf", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2418 { "sub", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2419 { "subf.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2420 { "sub.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2421 { "subfo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2422 { "subo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2423 { "subfo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2424 { "subo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2426 { "ldux", X(31,53), X_MASK
, PPC64
, { RT
, RAL
, RB
} },
2428 { "dcbst", X(31,54), XRT_MASK
, PPC
, { RA
, RB
} },
2430 { "lwzux", X(31,55), X_MASK
, PPCCOM
, { RT
, RAL
, RB
} },
2431 { "lux", X(31,55), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2433 { "cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
, { RA
, RS
} },
2434 { "cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
, { RA
, RS
} },
2436 { "andc", XRC(31,60,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2437 { "andc.", XRC(31,60,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2439 { "tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, { RA
, RB
} },
2440 { "tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, { RA
, RB
} },
2441 { "tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, { RA
, RB
} },
2442 { "tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2443 { "tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, { RA
, RB
} },
2444 { "tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2445 { "tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, { RA
, RB
} },
2446 { "tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, { RA
, RB
} },
2447 { "tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2448 { "tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, { RA
, RB
} },
2449 { "tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, { RA
, RB
} },
2450 { "tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2451 { "tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, { RA
, RB
} },
2452 { "tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2453 { "td", X(31,68), X_MASK
, PPC64
, { TO
, RA
, RB
} },
2455 { "mulhd", XO(31,73,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2456 { "mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2458 { "mulhw", XO(31,75,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2459 { "mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2461 { "mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, { SR
, RS
} },
2463 { "mfmsr", X(31,83), XRARB_MASK
, COM
, { RT
} },
2465 { "ldarx", X(31,84), X_MASK
, PPC64
, { RT
, RA
, RB
} },
2467 { "dcbf", X(31,86), XRT_MASK
, PPC
, { RA
, RB
} },
2469 { "lbzx", X(31,87), X_MASK
, COM
, { RT
, RA
, RB
} },
2471 { "neg", XO(31,104,0,0), XORB_MASK
, COM
, { RT
, RA
} },
2472 { "neg.", XO(31,104,0,1), XORB_MASK
, COM
, { RT
, RA
} },
2473 { "nego", XO(31,104,1,0), XORB_MASK
, COM
, { RT
, RA
} },
2474 { "nego.", XO(31,104,1,1), XORB_MASK
, COM
, { RT
, RA
} },
2476 { "mul", XO(31,107,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2477 { "mul.", XO(31,107,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2478 { "mulo", XO(31,107,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2479 { "mulo.", XO(31,107,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2481 { "mtsrdin", X(31,114), XRA_MASK
, PPC64
, { RS
, RB
} },
2483 { "clf", X(31,118), XRB_MASK
, POWER
, { RT
, RA
} },
2485 { "lbzux", X(31,119), X_MASK
, COM
, { RT
, RAL
, RB
} },
2487 { "not", XRC(31,124,0), X_MASK
, COM
, { RA
, RS
, RBS
} },
2488 { "nor", XRC(31,124,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2489 { "not.", XRC(31,124,1), X_MASK
, COM
, { RA
, RS
, RBS
} },
2490 { "nor.", XRC(31,124,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2492 { "wrtee", X(31,131), XRARB_MASK
, PPC403
, { RS
} },
2494 { "subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2495 { "sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2496 { "subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2497 { "sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2498 { "subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2499 { "sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2500 { "subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2501 { "sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2503 { "adde", XO(31,138,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2504 { "ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2505 { "adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2506 { "ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2507 { "addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2508 { "aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2509 { "addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2510 { "aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2512 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK
|FXM_MASK
, COM
, { RS
}},
2513 { "mtcrf", X(31,144), XFXFXM_MASK
, COM
, { FXM
, RS
} },
2515 { "mtmsr", X(31,146), XRARB_MASK
, COM
, { RS
} },
2517 { "stdx", X(31,149), X_MASK
, PPC64
, { RS
, RA
, RB
} },
2519 { "stwcx.", XRC(31,150,1), X_MASK
, PPC
, { RS
, RA
, RB
} },
2521 { "stwx", X(31,151), X_MASK
, PPCCOM
, { RS
, RA
, RB
} },
2522 { "stx", X(31,151), X_MASK
, PWRCOM
, { RS
, RA
, RB
} },
2524 { "slq", XRC(31,152,0), X_MASK
, M601
, { RA
, RS
, RB
} },
2525 { "slq.", XRC(31,152,1), X_MASK
, M601
, { RA
, RS
, RB
} },
2527 { "sle", XRC(31,153,0), X_MASK
, M601
, { RA
, RS
, RB
} },
2528 { "sle.", XRC(31,153,1), X_MASK
, M601
, { RA
, RS
, RB
} },
2530 { "wrteei", X(31,163), XE_MASK
, PPC403
, { E
} },
2532 { "mtmsrd", X(31,178), XRARB_MASK
, PPC64
, { RS
} },
2534 { "stdux", X(31,181), X_MASK
, PPC64
, { RS
, RAS
, RB
} },
2536 { "stwux", X(31,183), X_MASK
, PPCCOM
, { RS
, RAS
, RB
} },
2537 { "stux", X(31,183), X_MASK
, PWRCOM
, { RS
, RA
, RB
} },
2539 { "sliq", XRC(31,184,0), X_MASK
, M601
, { RA
, RS
, SH
} },
2540 { "sliq.", XRC(31,184,1), X_MASK
, M601
, { RA
, RS
, SH
} },
2542 { "subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2543 { "sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2544 { "subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2545 { "sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2546 { "subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2547 { "sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2548 { "subfzeo.",XO(31,200,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2549 { "sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2551 { "addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2552 { "aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2553 { "addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2554 { "aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2555 { "addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2556 { "azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2557 { "addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2558 { "azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2560 { "mtsr", X(31,210), XRB_MASK
|(1<<20), COM32
, { SR
, RS
} },
2562 { "stdcx.", XRC(31,214,1), X_MASK
, PPC64
, { RS
, RA
, RB
} },
2564 { "stbx", X(31,215), X_MASK
, COM
, { RS
, RA
, RB
} },
2566 { "sllq", XRC(31,216,0), X_MASK
, M601
, { RA
, RS
, RB
} },
2567 { "sllq.", XRC(31,216,1), X_MASK
, M601
, { RA
, RS
, RB
} },
2569 { "sleq", XRC(31,217,0), X_MASK
, M601
, { RA
, RS
, RB
} },
2570 { "sleq.", XRC(31,217,1), X_MASK
, M601
, { RA
, RS
, RB
} },
2572 { "subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2573 { "sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2574 { "subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2575 { "sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2576 { "subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2577 { "sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2578 { "subfmeo.",XO(31,232,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2579 { "sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2581 { "mulld", XO(31,233,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2582 { "mulld.", XO(31,233,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2583 { "mulldo", XO(31,233,1,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2584 { "mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2586 { "addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2587 { "ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2588 { "addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2589 { "ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2590 { "addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2591 { "ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2592 { "addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2593 { "ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2595 { "mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2596 { "muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2597 { "mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2598 { "muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2599 { "mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2600 { "mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2601 { "mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2602 { "mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2604 { "mtsrin", X(31,242), XRA_MASK
, PPC32
, { RS
, RB
} },
2605 { "mtsri", X(31,242), XRA_MASK
, POWER32
, { RS
, RB
} },
2607 { "dcbtst", X(31,246), XRT_MASK
, PPC
, { RA
, RB
} },
2609 { "stbux", X(31,247), X_MASK
, COM
, { RS
, RAS
, RB
} },
2611 { "slliq", XRC(31,248,0), X_MASK
, M601
, { RA
, RS
, SH
} },
2612 { "slliq.", XRC(31,248,1), X_MASK
, M601
, { RA
, RS
, SH
} },
2614 { "doz", XO(31,264,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2615 { "doz.", XO(31,264,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2616 { "dozo", XO(31,264,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2617 { "dozo.", XO(31,264,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2619 { "add", XO(31,266,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2620 { "cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2621 { "add.", XO(31,266,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2622 { "cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2623 { "addo", XO(31,266,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2624 { "caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2625 { "addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2626 { "caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2628 { "lscbx", XRC(31,277,0), X_MASK
, M601
, { RT
, RA
, RB
} },
2629 { "lscbx.", XRC(31,277,1), X_MASK
, M601
, { RT
, RA
, RB
} },
2631 { "dcbt", X(31,278), XRT_MASK
, PPC
, { RA
, RB
} },
2633 { "lhzx", X(31,279), X_MASK
, COM
, { RT
, RA
, RB
} },
2635 { "icbt", X(31,262), XRT_MASK
, PPC403
, { RA
, RB
} },
2637 { "eqv", XRC(31,284,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2638 { "eqv.", XRC(31,284,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2640 { "tlbie", X(31,306), XRTRA_MASK
, PPC
, { RB
} },
2641 { "tlbi", X(31,306), XRT_MASK
, POWER
, { RA
, RB
} },
2643 { "eciwx", X(31,310), X_MASK
, PPC
, { RT
, RA
, RB
} },
2645 { "lhzux", X(31,311), X_MASK
, COM
, { RT
, RAL
, RB
} },
2647 { "xor", XRC(31,316,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2648 { "xor.", XRC(31,316,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2650 { "mfexisr", XSPR(31,323,64), XSPR_MASK
, PPC403
, { RT
} },
2651 { "mfexier", XSPR(31,323,66), XSPR_MASK
, PPC403
, { RT
} },
2652 { "mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, { RT
} },
2653 { "mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, { RT
} },
2654 { "mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, { RT
} },
2655 { "mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, { RT
} },
2656 { "mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, { RT
} },
2657 { "mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, { RT
} },
2658 { "mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, { RT
} },
2659 { "mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, { RT
} },
2660 { "mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, { RT
} },
2661 { "mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, { RT
} },
2662 { "mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, { RT
} },
2663 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, { RT
} },
2664 { "mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, { RT
} },
2665 { "mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, { RT
} },
2666 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, { RT
} },
2667 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, { RT
} },
2668 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, { RT
} },
2669 { "mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, { RT
} },
2670 { "mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, { RT
} },
2671 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, { RT
} },
2672 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, { RT
} },
2673 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, { RT
} },
2674 { "mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, { RT
} },
2675 { "mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, { RT
} },
2676 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, { RT
} },
2677 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, { RT
} },
2678 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, { RT
} },
2679 { "mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, { RT
} },
2680 { "mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, { RT
} },
2681 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, { RT
} },
2682 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, { RT
} },
2683 { "mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, { RT
} },
2684 { "mfdcr", X(31,323), X_MASK
, PPC403
, { RT
, SPR
} },
2686 { "div", XO(31,331,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2687 { "div.", XO(31,331,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2688 { "divo", XO(31,331,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2689 { "divo.", XO(31,331,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2691 { "mfmq", XSPR(31,339,0), XSPR_MASK
, M601
, { RT
} },
2692 { "mfxer", XSPR(31,339,1), XSPR_MASK
, COM
, { RT
} },
2693 { "mfrtcu", XSPR(31,339,4), XSPR_MASK
, COM
, { RT
} },
2694 { "mfrtcl", XSPR(31,339,5), XSPR_MASK
, COM
, { RT
} },
2695 { "mfdec", XSPR(31,339,6), XSPR_MASK
, MFDEC1
, { RT
} },
2696 { "mflr", XSPR(31,339,8), XSPR_MASK
, COM
, { RT
} },
2697 { "mfctr", XSPR(31,339,9), XSPR_MASK
, COM
, { RT
} },
2698 { "mftid", XSPR(31,339,17), XSPR_MASK
, POWER
, { RT
} },
2699 { "mfdsisr", XSPR(31,339,18), XSPR_MASK
, COM
, { RT
} },
2700 { "mfdar", XSPR(31,339,19), XSPR_MASK
, COM
, { RT
} },
2701 { "mfdec", XSPR(31,339,22), XSPR_MASK
, MFDEC2
, { RT
} },
2702 { "mfsdr0", XSPR(31,339,24), XSPR_MASK
, POWER
, { RT
} },
2703 { "mfsdr1", XSPR(31,339,25), XSPR_MASK
, COM
, { RT
} },
2704 { "mfsrr0", XSPR(31,339,26), XSPR_MASK
, COM
, { RT
} },
2705 { "mfsrr1", XSPR(31,339,27), XSPR_MASK
, COM
, { RT
} },
2706 { "mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, { RT
} },
2707 { "mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, { RT
} },
2708 { "mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, { RT
} },
2709 { "mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, { RT
} },
2710 { "mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, { RT
} },
2711 { "mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, { RT
} },
2712 { "mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, { RT
} },
2713 { "mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, { RT
} },
2714 { "mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, { RT
} },
2715 { "mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, { RT
} },
2716 { "mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, { RT
} },
2717 { "mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, { RT
} },
2718 { "mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, { RT
} },
2719 { "mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, { RT
} },
2720 { "mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, { RT
} },
2721 { "mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, { RT
} },
2722 { "mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
, { RT
} },
2723 { "mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
, { RT
} },
2724 { "mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
, { RT
} },
2725 { "mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
, { RT
} },
2726 { "mfsprg", XSPR(31,339,272), XSPRG_MASK
, PPC
, { RT
, SPRG
} },
2727 { "mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
, { RT
} },
2728 { "mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
, { RT
} },
2729 { "mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
, { RT
} },
2730 { "mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
, { RT
} },
2731 { "mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, { RT
} },
2732 { "mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, { RT
} },
2733 { "mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, { RT
} },
2734 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
2735 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
2736 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
2737 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
2738 { "mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, { RT
} },
2739 { "mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, { RT
} },
2740 { "mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, { RT
} },
2741 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, { RT
} },
2742 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, { RT
} },
2743 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, { RT
} },
2744 { "mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, { RT
} },
2745 { "mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, { RT
} },
2746 { "mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, { RT
} },
2747 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, { RT
} },
2748 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, { RT
} },
2749 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, { RT
} },
2750 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, { RT
} },
2751 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, { RT
} },
2752 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, { RT
} },
2753 { "mfm_casid",XSPR(31,339,793), XSPR_MASK
, PPC860
, { RT
} },
2754 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, { RT
} },
2755 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, { RT
} },
2756 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, { RT
} },
2757 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, { RT
} },
2758 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, { RT
} },
2759 { "mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, { RT
} },
2760 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK
, PPC860
, { RT
} },
2761 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK
, PPC860
, { RT
} },
2762 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK
, PPC860
, { RT
} },
2763 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, { RT
} },
2764 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK
, PPC860
, { RT
} },
2765 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK
, PPC860
, { RT
} },
2766 { "mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, { RT
} },
2767 { "mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, { RT
} },
2768 { "mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
, { RT
} },
2769 { "mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
, { RT
} },
2770 { "mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, { RT
} },
2771 { "mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, { RT
} },
2772 { "mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, { RT
} },
2773 { "mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, { RT
} },
2774 { "mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, { RT
} },
2775 { "mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, { RT
} },
2776 { "mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, { RT
} },
2777 { "mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, { RT
} },
2778 { "mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, { RT
} },
2779 { "mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, { RT
} },
2780 { "mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, { RT
} },
2781 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, { RT
} },
2782 { "mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, { RT
} },
2783 { "mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, { RT
} },
2784 { "mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, { RT
} },
2785 { "mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, { RT
} },
2786 { "mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, { RT
} },
2787 { "mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, { RT
} },
2788 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, { RT
} },
2789 { "mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, { RT
} },
2790 { "mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, { RT
} },
2791 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, { RT
} },
2792 { "mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, { RT
} },
2793 { "mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, { RT
} },
2794 { "mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, { RT
} },
2795 { "mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, { RT
} },
2796 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, { RT
} },
2797 { "mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, { RT
} },
2798 { "mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, { RT
} },
2799 { "mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, { RT
} },
2800 { "mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, { RT
} },
2801 { "mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, { RT
} },
2802 { "mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, { RT
} },
2803 { "mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, { RT
} },
2804 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, { RT
} },
2805 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, { RT
} },
2806 { "mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, { RT
} },
2807 { "mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, { RT
} },
2808 { "mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, { RT
} },
2809 { "mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, { RT
} },
2810 { "mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, { RT
} },
2811 { "mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, { RT
} },
2812 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, { RT
} },
2813 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, { RT
} },
2814 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, { RT
} },
2815 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, { RT
} },
2816 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, { RT
} },
2817 { "mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, { RT
} },
2818 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, { RT
} },
2819 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, { RT
} },
2820 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, { RT
} },
2821 { "mfspr", X(31,339), X_MASK
, COM
, { RT
, SPR
} },
2823 { "lwax", X(31,341), X_MASK
, PPC64
, { RT
, RA
, RB
} },
2825 { "lhax", X(31,343), X_MASK
, COM
, { RT
, RA
, RB
} },
2827 { "dccci", X(31,454), XRT_MASK
, PPC403
, { RA
, RB
} },
2829 { "abs", XO(31,360,0,0), XORB_MASK
, M601
, { RT
, RA
} },
2830 { "abs.", XO(31,360,0,1), XORB_MASK
, M601
, { RT
, RA
} },
2831 { "abso", XO(31,360,1,0), XORB_MASK
, M601
, { RT
, RA
} },
2832 { "abso.", XO(31,360,1,1), XORB_MASK
, M601
, { RT
, RA
} },
2834 { "divs", XO(31,363,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2835 { "divs.", XO(31,363,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2836 { "divso", XO(31,363,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2837 { "divso.", XO(31,363,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2839 { "tlbia", X(31,370), 0xffffffff, PPC
, { 0 } },
2841 { "mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, { RT
} },
2842 { "mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, { RT
} },
2843 { "mftb", X(31,371), X_MASK
, PPC
, { RT
, TBR
} },
2845 { "lwaux", X(31,373), X_MASK
, PPC64
, { RT
, RAL
, RB
} },
2847 { "lhaux", X(31,375), X_MASK
, COM
, { RT
, RAL
, RB
} },
2849 { "sthx", X(31,407), X_MASK
, COM
, { RS
, RA
, RB
} },
2851 { "lfqx", X(31,791), X_MASK
, POWER2
, { FRT
, RA
, RB
} },
2853 { "lfqux", X(31,823), X_MASK
, POWER2
, { FRT
, RA
, RB
} },
2855 { "stfqx", X(31,919), X_MASK
, POWER2
, { FRS
, RA
, RB
} },
2857 { "stfqux", X(31,951), X_MASK
, POWER2
, { FRS
, RA
, RB
} },
2859 { "orc", XRC(31,412,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2860 { "orc.", XRC(31,412,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2862 { "sradi", XS(31,413,0), XS_MASK
, PPC64
, { RA
, RS
, SH6
} },
2863 { "sradi.", XS(31,413,1), XS_MASK
, PPC64
, { RA
, RS
, SH6
} },
2865 { "slbie", X(31,434), XRTRA_MASK
, PPC64
, { RB
} },
2867 { "ecowx", X(31,438), X_MASK
, PPC
, { RT
, RA
, RB
} },
2869 { "sthux", X(31,439), X_MASK
, COM
, { RS
, RAS
, RB
} },
2871 { "mr", XRC(31,444,0), X_MASK
, COM
, { RA
, RS
, RBS
} },
2872 { "or", XRC(31,444,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2873 { "mr.", XRC(31,444,1), X_MASK
, COM
, { RA
, RS
, RBS
} },
2874 { "or.", XRC(31,444,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2876 { "mtexisr", XSPR(31,451,64), XSPR_MASK
, PPC403
, { RT
} },
2877 { "mtexier", XSPR(31,451,66), XSPR_MASK
, PPC403
, { RT
} },
2878 { "mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, { RT
} },
2879 { "mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, { RT
} },
2880 { "mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, { RT
} },
2881 { "mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, { RT
} },
2882 { "mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, { RT
} },
2883 { "mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, { RT
} },
2884 { "mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, { RT
} },
2885 { "mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, { RT
} },
2886 { "mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, { RT
} },
2887 { "mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, { RT
} },
2888 { "mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, { RT
} },
2889 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, { RT
} },
2890 { "mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, { RT
} },
2891 { "mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, { RT
} },
2892 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, { RT
} },
2893 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, { RT
} },
2894 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, { RT
} },
2895 { "mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, { RT
} },
2896 { "mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, { RT
} },
2897 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, { RT
} },
2898 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, { RT
} },
2899 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, { RT
} },
2900 { "mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, { RT
} },
2901 { "mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, { RT
} },
2902 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, { RT
} },
2903 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, { RT
} },
2904 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, { RT
} },
2905 { "mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, { RT
} },
2906 { "mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, { RT
} },
2907 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, { RT
} },
2908 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, { RT
} },
2909 { "mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, { RT
} },
2910 { "mtummcr0", XSPR(31,451,936), XSPR_MASK
, PPC750
, { RT
} },
2911 { "mtupmc1", XSPR(31,451,937), XSPR_MASK
, PPC750
, { RT
} },
2912 { "mtupmc2", XSPR(31,451,938), XSPR_MASK
, PPC750
, { RT
} },
2913 { "mtusia", XSPR(31,451,939), XSPR_MASK
, PPC750
, { RT
} },
2914 { "mtummcr1", XSPR(31,451,940), XSPR_MASK
, PPC750
, { RT
} },
2915 { "mtupmc3", XSPR(31,451,941), XSPR_MASK
, PPC750
, { RT
} },
2916 { "mtupmc4", XSPR(31,451,942), XSPR_MASK
, PPC750
, { RT
} },
2917 { "mtmmcr0", XSPR(31,451,952), XSPR_MASK
, PPC750
, { RT
} },
2918 { "mtpmc1", XSPR(31,451,953), XSPR_MASK
, PPC750
, { RT
} },
2919 { "mtpmc2", XSPR(31,451,954), XSPR_MASK
, PPC750
, { RT
} },
2920 { "mtsia", XSPR(31,451,955), XSPR_MASK
, PPC750
, { RT
} },
2921 { "mtmmcr1", XSPR(31,451,956), XSPR_MASK
, PPC750
, { RT
} },
2922 { "mtpmc3", XSPR(31,451,957), XSPR_MASK
, PPC750
, { RT
} },
2923 { "mtpmc4", XSPR(31,451,958), XSPR_MASK
, PPC750
, { RT
} },
2924 { "mtl2cr", XSPR(31,451,1017), XSPR_MASK
, PPC750
, { RT
} },
2925 { "mtictc", XSPR(31,451,1019), XSPR_MASK
, PPC750
, { RT
} },
2926 { "mtthrm1", XSPR(31,451,1020), XSPR_MASK
, PPC750
, { RT
} },
2927 { "mtthrm2", XSPR(31,451,1021), XSPR_MASK
, PPC750
, { RT
} },
2928 { "mtthrm3", XSPR(31,451,1022), XSPR_MASK
, PPC750
, { RT
} },
2929 { "mtdcr", X(31,451), X_MASK
, PPC403
, { SPR
, RS
} },
2931 { "divdu", XO(31,457,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2932 { "divdu.", XO(31,457,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2933 { "divduo", XO(31,457,1,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2934 { "divduo.", XO(31,457,1,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2936 { "divwu", XO(31,459,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2937 { "divwu.", XO(31,459,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2938 { "divwuo", XO(31,459,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2939 { "divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2941 { "mtmq", XSPR(31,467,0), XSPR_MASK
, M601
, { RS
} },
2942 { "mtxer", XSPR(31,467,1), XSPR_MASK
, COM
, { RS
} },
2943 { "mtlr", XSPR(31,467,8), XSPR_MASK
, COM
, { RS
} },
2944 { "mtctr", XSPR(31,467,9), XSPR_MASK
, COM
, { RS
} },
2945 { "mttid", XSPR(31,467,17), XSPR_MASK
, POWER
, { RS
} },
2946 { "mtdsisr", XSPR(31,467,18), XSPR_MASK
, COM
, { RS
} },
2947 { "mtdar", XSPR(31,467,19), XSPR_MASK
, COM
, { RS
} },
2948 { "mtrtcu", XSPR(31,467,20), XSPR_MASK
, COM
, { RS
} },
2949 { "mtrtcl", XSPR(31,467,21), XSPR_MASK
, COM
, { RS
} },
2950 { "mtdec", XSPR(31,467,22), XSPR_MASK
, COM
, { RS
} },
2951 { "mtsdr0", XSPR(31,467,24), XSPR_MASK
, POWER
, { RS
} },
2952 { "mtsdr1", XSPR(31,467,25), XSPR_MASK
, COM
, { RS
} },
2953 { "mtsrr0", XSPR(31,467,26), XSPR_MASK
, COM
, { RS
} },
2954 { "mtsrr1", XSPR(31,467,27), XSPR_MASK
, COM
, { RS
} },
2955 { "mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, { RT
} },
2956 { "mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, { RT
} },
2957 { "mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, { RT
} },
2958 { "mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, { RT
} },
2959 { "mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, { RT
} },
2960 { "mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, { RT
} },
2961 { "mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, { RT
} },
2962 { "mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, { RT
} },
2963 { "mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, { RT
} },
2964 { "mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, { RT
} },
2965 { "mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, { RT
} },
2966 { "mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, { RT
} },
2967 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, { RT
} },
2968 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, { RT
} },
2969 { "mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, { RT
} },
2970 { "mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, { RT
} },
2971 { "mtsprg", XSPR(31,467,272), XSPRG_MASK
, PPC
, { SPRG
, RS
} },
2972 { "mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
, { RT
} },
2973 { "mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
, { RT
} },
2974 { "mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
, { RT
} },
2975 { "mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
, { RT
} },
2976 { "mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
, { RT
} },
2977 { "mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
, { RT
} },
2978 { "mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
, { RT
} },
2979 { "mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
, { RT
} },
2980 { "mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, { RS
} },
2981 { "mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, { RS
} },
2982 { "mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, { RS
} },
2983 { "mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, { RS
} },
2984 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
2985 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
2986 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
2987 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
2988 { "mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, { RT
} },
2989 { "mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, { RT
} },
2990 { "mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
, { RT
} },
2991 { "mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, { RT
} },
2992 { "mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, { RT
} },
2993 { "mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, { RT
} },
2994 { "mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, { RT
} },
2995 { "mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, { RT
} },
2996 { "mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, { RT
} },
2997 { "mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, { RT
} },
2998 { "mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, { RT
} },
2999 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, { RT
} },
3000 { "mticdbdr",XSPR(31,467,979), XSPR_MASK
, PPC403
, { RT
} },
3001 { "mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, { RT
} },
3002 { "mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, { RT
} },
3003 { "mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, { RT
} },
3004 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, { RT
} },
3005 { "mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, { RT
} },
3006 { "mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, { RT
} },
3007 { "mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, { RT
} },
3008 { "mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, { RT
} },
3009 { "mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, { RT
} },
3010 { "mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, { RT
} },
3011 { "mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, { RT
} },
3012 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, { RT
} },
3013 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, { RT
} },
3014 { "mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, { RT
} },
3015 { "mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, { RT
} },
3016 { "mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, { RT
} },
3017 { "mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, { RT
} },
3018 { "mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, { RT
} },
3019 { "mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, { RT
} },
3020 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, { RT
} },
3021 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, { RT
} },
3022 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, { RT
} },
3023 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, { RT
} },
3024 { "mtspr", X(31,467), X_MASK
, COM
, { SPR
, RS
} },
3026 { "dcbi", X(31,470), XRT_MASK
, PPC
, { RA
, RB
} },
3028 { "nand", XRC(31,476,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3029 { "nand.", XRC(31,476,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3031 { "dcread", X(31,486), X_MASK
, PPC403
, { RT
, RA
, RB
}},
3033 { "nabs", XO(31,488,0,0), XORB_MASK
, M601
, { RT
, RA
} },
3034 { "nabs.", XO(31,488,0,1), XORB_MASK
, M601
, { RT
, RA
} },
3035 { "nabso", XO(31,488,1,0), XORB_MASK
, M601
, { RT
, RA
} },
3036 { "nabso.", XO(31,488,1,1), XORB_MASK
, M601
, { RT
, RA
} },
3038 { "divd", XO(31,489,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3039 { "divd.", XO(31,489,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3040 { "divdo", XO(31,489,1,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3041 { "divdo.", XO(31,489,1,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3043 { "divw", XO(31,491,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3044 { "divw.", XO(31,491,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3045 { "divwo", XO(31,491,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3046 { "divwo.", XO(31,491,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3048 { "slbia", X(31,498), 0xffffffff, PPC64
, { 0 } },
3050 { "cli", X(31,502), XRB_MASK
, POWER
, { RT
, RA
} },
3052 { "mcrxr", X(31,512), XRARB_MASK
|(3<<21), COM
, { BF
} },
3054 { "clcs", X(31,531), XRB_MASK
, M601
, { RT
, RA
} },
3056 { "lswx", X(31,533), X_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3057 { "lsx", X(31,533), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3059 { "lwbrx", X(31,534), X_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3060 { "lbrx", X(31,534), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3062 { "lfsx", X(31,535), X_MASK
, COM
, { FRT
, RA
, RB
} },
3064 { "srw", XRC(31,536,0), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3065 { "sr", XRC(31,536,0), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3066 { "srw.", XRC(31,536,1), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3067 { "sr.", XRC(31,536,1), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3069 { "rrib", XRC(31,537,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3070 { "rrib.", XRC(31,537,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3072 { "srd", XRC(31,539,0), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3073 { "srd.", XRC(31,539,1), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3075 { "maskir", XRC(31,541,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3076 { "maskir.", XRC(31,541,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3078 { "tlbsync", X(31,566), 0xffffffff, PPC
, { 0 } },
3080 { "lfsux", X(31,567), X_MASK
, COM
, { FRT
, RAS
, RB
} },
3082 { "mfsr", X(31,595), XRB_MASK
|(1<<20), COM32
, { RT
, SR
} },
3084 { "lswi", X(31,597), X_MASK
, PPCCOM
, { RT
, RA
, NB
} },
3085 { "lsi", X(31,597), X_MASK
, PWRCOM
, { RT
, RA
, NB
} },
3087 { "sync", X(31,598), 0xffffffff, PPCCOM
, { 0 } },
3088 { "dcs", X(31,598), 0xffffffff, PWRCOM
, { 0 } },
3090 { "lfdx", X(31,599), X_MASK
, COM
, { FRT
, RA
, RB
} },
3092 { "mfsri", X(31,627), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3094 { "dclst", X(31,630), XRB_MASK
, PWRCOM
, { RS
, RA
} },
3096 { "lfdux", X(31,631), X_MASK
, COM
, { FRT
, RAS
, RB
} },
3098 { "mfsrin", X(31,659), XRA_MASK
, PPC32
, { RT
, RB
} },
3100 { "stswx", X(31,661), X_MASK
, PPCCOM
, { RS
, RA
, RB
} },
3101 { "stsx", X(31,661), X_MASK
, PWRCOM
, { RS
, RA
, RB
} },
3103 { "stwbrx", X(31,662), X_MASK
, PPCCOM
, { RS
, RA
, RB
} },
3104 { "stbrx", X(31,662), X_MASK
, PWRCOM
, { RS
, RA
, RB
} },
3106 { "stfsx", X(31,663), X_MASK
, COM
, { FRS
, RA
, RB
} },
3108 { "srq", XRC(31,664,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3109 { "srq.", XRC(31,664,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3111 { "sre", XRC(31,665,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3112 { "sre.", XRC(31,665,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3114 { "stfsux", X(31,695), X_MASK
, COM
, { FRS
, RAS
, RB
} },
3116 { "sriq", XRC(31,696,0), X_MASK
, M601
, { RA
, RS
, SH
} },
3117 { "sriq.", XRC(31,696,1), X_MASK
, M601
, { RA
, RS
, SH
} },
3119 { "stswi", X(31,725), X_MASK
, PPCCOM
, { RS
, RA
, NB
} },
3120 { "stsi", X(31,725), X_MASK
, PWRCOM
, { RS
, RA
, NB
} },
3122 { "stfdx", X(31,727), X_MASK
, COM
, { FRS
, RA
, RB
} },
3124 { "srlq", XRC(31,728,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3125 { "srlq.", XRC(31,728,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3127 { "sreq", XRC(31,729,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3128 { "sreq.", XRC(31,729,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3130 { "dcba", X(31,758), XRT_MASK
, PPC405
, { RA
, RB
} },
3132 { "stfdux", X(31,759), X_MASK
, COM
, { FRS
, RAS
, RB
} },
3134 { "srliq", XRC(31,760,0), X_MASK
, M601
, { RA
, RS
, SH
} },
3135 { "srliq.", XRC(31,760,1), X_MASK
, M601
, { RA
, RS
, SH
} },
3137 { "lhbrx", X(31,790), X_MASK
, COM
, { RT
, RA
, RB
} },
3139 { "sraw", XRC(31,792,0), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3140 { "sra", XRC(31,792,0), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3141 { "sraw.", XRC(31,792,1), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3142 { "sra.", XRC(31,792,1), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3144 { "srad", XRC(31,794,0), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3145 { "srad.", XRC(31,794,1), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3147 { "rac", X(31,818), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3149 { "srawi", XRC(31,824,0), X_MASK
, PPCCOM
, { RA
, RS
, SH
} },
3150 { "srai", XRC(31,824,0), X_MASK
, PWRCOM
, { RA
, RS
, SH
} },
3151 { "srawi.", XRC(31,824,1), X_MASK
, PPCCOM
, { RA
, RS
, SH
} },
3152 { "srai.", XRC(31,824,1), X_MASK
, PWRCOM
, { RA
, RS
, SH
} },
3154 { "eieio", X(31,854), 0xffffffff, PPC
, { 0 } },
3156 { "tlbsx", XRC(31,914,0), X_MASK
, PPC403
, { RT
, RA
, RB
} },
3157 { "tlbsx.", XRC(31,914,1), X_MASK
, PPC403
, { RT
, RA
, RB
} },
3159 { "sthbrx", X(31,918), X_MASK
, COM
, { RS
, RA
, RB
} },
3161 { "sraq", XRC(31,920,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3162 { "sraq.", XRC(31,920,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3164 { "srea", XRC(31,921,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3165 { "srea.", XRC(31,921,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3167 { "extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
, { RA
, RS
} },
3168 { "exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, { RA
, RS
} },
3169 { "extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
, { RA
, RS
} },
3170 { "exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, { RA
, RS
} },
3172 { "tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, { RT
, RA
} },
3173 { "tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, { RT
, RA
} },
3174 { "tlbre", X(31,946), X_MASK
, PPC403
, { RT
, RA
, SH
} },
3176 { "sraiq", XRC(31,952,0), X_MASK
, M601
, { RA
, RS
, SH
} },
3177 { "sraiq.", XRC(31,952,1), X_MASK
, M601
, { RA
, RS
, SH
} },
3179 { "extsb", XRC(31,954,0), XRB_MASK
, PPC
, { RA
, RS
} },
3180 { "extsb.", XRC(31,954,1), XRB_MASK
, PPC
, { RA
, RS
} },
3182 { "iccci", X(31,966), XRT_MASK
, PPC403
, { RA
, RB
} },
3184 { "tlbld", X(31,978), XRTRA_MASK
, PPC
, { RB
} },
3186 { "tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, { RT
, RA
} },
3187 { "tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, { RT
, RA
} },
3188 { "tlbwe", X(31,978), X_MASK
, PPC403
, { RS
, RA
, SH
} },
3190 { "icbi", X(31,982), XRT_MASK
, PPC
, { RA
, RB
} },
3192 { "stfiwx", X(31,983), X_MASK
, PPC
, { FRS
, RA
, RB
} },
3194 { "extsw", XRC(31,986,0), XRB_MASK
, PPC
, { RA
, RS
} },
3195 { "extsw.", XRC(31,986,1), XRB_MASK
, PPC
, { RA
, RS
} },
3197 { "icread", X(31,998), XRT_MASK
, PPC403
, { RA
, RB
} },
3199 { "tlbli", X(31,1010), XRTRA_MASK
, PPC
, { RB
} },
3201 { "dcbz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
3202 { "dclz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
3204 { "lvebx", X(31, 7), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3205 { "lvehx", X(31, 39), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3206 { "lvewx", X(31, 71), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3207 { "lvsl", X(31, 6), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3208 { "lvsr", X(31, 38), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3209 { "lvx", X(31, 103), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3210 { "lvxl", X(31, 359), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3211 { "stvebx", X(31, 135), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3212 { "stvehx", X(31, 167), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3213 { "stvewx", X(31, 199), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3214 { "stvx", X(31, 231), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3215 { "stvxl", X(31, 487), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3217 { "lwz", OP(32), OP_MASK
, PPCCOM
, { RT
, D
, RA
} },
3218 { "l", OP(32), OP_MASK
, PWRCOM
, { RT
, D
, RA
} },
3220 { "lwzu", OP(33), OP_MASK
, PPCCOM
, { RT
, D
, RAL
} },
3221 { "lu", OP(33), OP_MASK
, PWRCOM
, { RT
, D
, RA
} },
3223 { "lbz", OP(34), OP_MASK
, COM
, { RT
, D
, RA
} },
3225 { "lbzu", OP(35), OP_MASK
, COM
, { RT
, D
, RAL
} },
3227 { "stw", OP(36), OP_MASK
, PPCCOM
, { RS
, D
, RA
} },
3228 { "st", OP(36), OP_MASK
, PWRCOM
, { RS
, D
, RA
} },
3230 { "stwu", OP(37), OP_MASK
, PPCCOM
, { RS
, D
, RAS
} },
3231 { "stu", OP(37), OP_MASK
, PWRCOM
, { RS
, D
, RA
} },
3233 { "stb", OP(38), OP_MASK
, COM
, { RS
, D
, RA
} },
3235 { "stbu", OP(39), OP_MASK
, COM
, { RS
, D
, RAS
} },
3237 { "lhz", OP(40), OP_MASK
, COM
, { RT
, D
, RA
} },
3239 { "lhzu", OP(41), OP_MASK
, COM
, { RT
, D
, RAL
} },
3241 { "lha", OP(42), OP_MASK
, COM
, { RT
, D
, RA
} },
3243 { "lhau", OP(43), OP_MASK
, COM
, { RT
, D
, RAL
} },
3245 { "sth", OP(44), OP_MASK
, COM
, { RS
, D
, RA
} },
3247 { "sthu", OP(45), OP_MASK
, COM
, { RS
, D
, RAS
} },
3249 { "lmw", OP(46), OP_MASK
, PPCCOM
, { RT
, D
, RAM
} },
3250 { "lm", OP(46), OP_MASK
, PWRCOM
, { RT
, D
, RA
} },
3252 { "stmw", OP(47), OP_MASK
, PPCCOM
, { RS
, D
, RA
} },
3253 { "stm", OP(47), OP_MASK
, PWRCOM
, { RS
, D
, RA
} },
3255 { "lfs", OP(48), OP_MASK
, COM
, { FRT
, D
, RA
} },
3257 { "lfsu", OP(49), OP_MASK
, COM
, { FRT
, D
, RAS
} },
3259 { "lfd", OP(50), OP_MASK
, COM
, { FRT
, D
, RA
} },
3261 { "lfdu", OP(51), OP_MASK
, COM
, { FRT
, D
, RAS
} },
3263 { "stfs", OP(52), OP_MASK
, COM
, { FRS
, D
, RA
} },
3265 { "stfsu", OP(53), OP_MASK
, COM
, { FRS
, D
, RAS
} },
3267 { "stfd", OP(54), OP_MASK
, COM
, { FRS
, D
, RA
} },
3269 { "stfdu", OP(55), OP_MASK
, COM
, { FRS
, D
, RAS
} },
3271 { "lfq", OP(56), OP_MASK
, POWER2
, { FRT
, D
, RA
} },
3273 { "lfqu", OP(57), OP_MASK
, POWER2
, { FRT
, D
, RA
} },
3275 { "ld", DSO(58,0), DS_MASK
, PPC64
, { RT
, DS
, RA
} },
3277 { "ldu", DSO(58,1), DS_MASK
, PPC64
, { RT
, DS
, RAL
} },
3279 { "lwa", DSO(58,2), DS_MASK
, PPC64
, { RT
, DS
, RA
} },
3281 { "fdivs", A(59,18,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3282 { "fdivs.", A(59,18,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3284 { "fsubs", A(59,20,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3285 { "fsubs.", A(59,20,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3287 { "fadds", A(59,21,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3288 { "fadds.", A(59,21,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3290 { "fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3291 { "fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3293 { "fres", A(59,24,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3294 { "fres.", A(59,24,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3296 { "fmuls", A(59,25,0), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
3297 { "fmuls.", A(59,25,1), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
3299 { "fmsubs", A(59,28,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3300 { "fmsubs.", A(59,28,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3302 { "fmadds", A(59,29,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3303 { "fmadds.", A(59,29,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3305 { "fnmsubs", A(59,30,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3306 { "fnmsubs.",A(59,30,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3308 { "fnmadds", A(59,31,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3309 { "fnmadds.",A(59,31,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3311 { "stfq", OP(60), OP_MASK
, POWER2
, { FRS
, D
, RA
} },
3313 { "stfqu", OP(61), OP_MASK
, POWER2
, { FRS
, D
, RA
} },
3315 { "std", DSO(62,0), DS_MASK
, PPC64
, { RS
, DS
, RA
} },
3317 { "stdu", DSO(62,1), DS_MASK
, PPC64
, { RS
, DS
, RAS
} },
3319 { "fcmpu", X(63,0), X_MASK
|(3<<21), COM
, { BF
, FRA
, FRB
} },
3321 { "frsp", XRC(63,12,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3322 { "frsp.", XRC(63,12,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3324 { "fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
3325 { "fcir", XRC(63,14,0), XRA_MASK
, POWER2
, { FRT
, FRB
} },
3326 { "fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
3327 { "fcir.", XRC(63,14,1), XRA_MASK
, POWER2
, { FRT
, FRB
} },
3329 { "fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
3330 { "fcirz", XRC(63,15,0), XRA_MASK
, POWER2
, { FRT
, FRB
} },
3331 { "fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
3332 { "fcirz.", XRC(63,15,1), XRA_MASK
, POWER2
, { FRT
, FRB
} },
3334 { "fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3335 { "fd", A(63,18,0), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3336 { "fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3337 { "fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3339 { "fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3340 { "fs", A(63,20,0), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3341 { "fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3342 { "fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3344 { "fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3345 { "fa", A(63,21,0), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3346 { "fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3347 { "fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3349 { "fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, { FRT
, FRB
} },
3350 { "fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, { FRT
, FRB
} },
3352 { "fsel", A(63,23,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3353 { "fsel.", A(63,23,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3355 { "fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, { FRT
, FRA
, FRC
} },
3356 { "fm", A(63,25,0), AFRB_MASK
, PWRCOM
, { FRT
, FRA
, FRC
} },
3357 { "fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, { FRT
, FRA
, FRC
} },
3358 { "fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, { FRT
, FRA
, FRC
} },
3360 { "frsqrte", A(63,26,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3361 { "frsqrte.",A(63,26,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3363 { "fmsub", A(63,28,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3364 { "fms", A(63,28,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3365 { "fmsub.", A(63,28,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3366 { "fms.", A(63,28,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3368 { "fmadd", A(63,29,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3369 { "fma", A(63,29,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3370 { "fmadd.", A(63,29,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3371 { "fma.", A(63,29,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3373 { "fnmsub", A(63,30,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3374 { "fnms", A(63,30,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3375 { "fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3376 { "fnms.", A(63,30,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3378 { "fnmadd", A(63,31,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3379 { "fnma", A(63,31,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3380 { "fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3381 { "fnma.", A(63,31,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3383 { "fcmpo", X(63,32), X_MASK
|(3<<21), COM
, { BF
, FRA
, FRB
} },
3385 { "mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, { BT
} },
3386 { "mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, { BT
} },
3388 { "fneg", XRC(63,40,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3389 { "fneg.", XRC(63,40,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3391 { "mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, { BF
, BFA
} },
3393 { "mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, { BT
} },
3394 { "mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, { BT
} },
3396 { "fmr", XRC(63,72,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3397 { "fmr.", XRC(63,72,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3399 { "mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, { BF
, U
} },
3400 { "mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, { BF
, U
} },
3402 { "fnabs", XRC(63,136,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3403 { "fnabs.", XRC(63,136,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3405 { "fabs", XRC(63,264,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3406 { "fabs.", XRC(63,264,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3408 { "mffs", XRC(63,583,0), XRARB_MASK
, COM
, { FRT
} },
3409 { "mffs.", XRC(63,583,1), XRARB_MASK
, COM
, { FRT
} },
3411 { "mtfsf", XFL(63,711,0), XFL_MASK
, COM
, { FLM
, FRB
} },
3412 { "mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, { FLM
, FRB
} },
3414 { "fctid", XRC(63,814,0), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3415 { "fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3417 { "fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3418 { "fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3420 { "fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3421 { "fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3425 const int powerpc_num_opcodes
=
3426 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
3428 /* The macro table. This is only used by the assembler. */
3430 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3431 when x=0; 32-x when x is between 1 and 31; are negative if x is
3432 negative; and are 32 or more otherwise. This is what you want
3433 when, for instance, you are emulating a right shift by a
3434 rotate-left-and-mask, because the underlying instructions support
3435 shifts of size 0 but not shifts of size 32. By comparison, when
3436 extracting x bits from some word you want to use just 32-x, because
3437 the underlying instructions don't support extracting 0 bits but do
3438 support extracting the whole word (32 bits in this case). */
3440 const struct powerpc_macro powerpc_macros
[] = {
3441 { "extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1" },
3442 { "extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1" },
3443 { "extrdi", 4, PPC64
, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3444 { "extrdi.", 4, PPC64
, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3445 { "insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3" },
3446 { "insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3447 { "rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
3448 { "rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
3449 { "sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)" },
3450 { "sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)" },
3451 { "srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
3452 { "srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
3453 { "clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)" },
3454 { "clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)" },
3455 { "clrlsldi",4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)" },
3456 { "clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)" },
3458 { "extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1" },
3459 { "extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1" },
3460 { "extrwi", 4, PPCCOM
, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3461 { "extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3462 { "inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
3463 { "inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
3464 { "insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3465 { "insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3466 { "rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3467 { "rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3468 { "slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)" },
3469 { "sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)" },
3470 { "slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)" },
3471 { "sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)" },
3472 { "srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3473 { "sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3474 { "srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3475 { "sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3476 { "clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)" },
3477 { "clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)" },
3478 { "clrlslwi",4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3479 { "clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3483 const int powerpc_num_macros
=
3484 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);