1 /* tc-m32r.c -- Assembler for the Renesas M32R.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
27 #include "opcodes/m32r-desc.h"
28 #include "opcodes/m32r-opc.h"
32 /* Linked list of symbols that are debugging symbols to be defined as the
33 beginning of the current instruction. */
34 typedef struct sym_link
36 struct sym_link
*next
;
40 static sym_linkS
*debug_sym_link
= (sym_linkS
*) 0;
42 /* Structure to hold all of the different components describing
43 an individual instruction. */
46 const CGEN_INSN
*insn
;
47 const CGEN_INSN
*orig_insn
;
50 CGEN_INSN_INT buffer
[1];
51 #define INSN_VALUE(buf) (*(buf))
53 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
54 #define INSN_VALUE(buf) (buf)
59 fixS
*fixups
[GAS_CGEN_MAX_FIXUPS
];
60 int indices
[MAX_OPERAND_INSTANCES
];
61 sym_linkS
*debug_sym_link
;
65 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
66 boundary (i.e. was the first of two 16 bit insns). */
67 static m32r_insn prev_insn
;
69 /* Non-zero if we've seen a relaxable insn since the last 32 bit
71 static int seen_relaxable_p
= 0;
73 /* Non-zero if we are generating PIC code. */
76 /* Non-zero if -relax specified, in which case sufficient relocs are output
77 for the linker to do relaxing.
78 We do simple forms of relaxing internally, but they are always done.
79 This flag does not apply to them. */
80 static int m32r_relax
;
83 /* Not supported yet. */
84 /* If non-NULL, pointer to cpu description file to read.
85 This allows runtime additions to the assembler. */
86 static const char *m32r_cpu_desc
;
89 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
90 Each high/shigh reloc must be paired with it's low cousin in order to
91 properly calculate the addend in a relocatable link (since there is a
92 potential carry from the low to the high/shigh).
93 This option is off by default though for user-written assembler code it
94 might make sense to make the default be on (i.e. have gcc pass a flag
95 to turn it off). This warning must not be on for GCC created code as
96 optimization may delete the low but not the high/shigh (at least we
97 shouldn't assume or require it to). */
98 static int warn_unmatched_high
= 0;
100 /* 1 if -m32rx has been specified, in which case support for
101 the extended M32RX instruction set should be enabled.
102 2 if -m32r2 has been specified, in which case support for
103 the extended M32R2 instruction set should be enabled. */
104 static int enable_m32rx
= 0; /* Default to M32R. */
106 /* Non-zero if -m32rx -hidden has been specified, in which case support for
107 the special M32RX instruction set should be enabled. */
108 static int enable_special
= 0;
110 /* Non-zero if -bitinst has been specified, in which case support
111 for extended M32R bit-field instruction set should be enabled. */
112 static int enable_special_m32r
= 1;
114 /* Non-zero if -float has been specified, in which case support for
115 extended M32R floating point instruction set should be enabled. */
116 static int enable_special_float
= 0;
118 /* Non-zero if the programmer should be warned when an explicit parallel
119 instruction might have constraint violations. */
120 static int warn_explicit_parallel_conflicts
= 1;
122 /* Non-zero if the programmer should not receive any messages about
123 parallel instruction with potential or real constraint violations.
124 The ability to suppress these messages is intended only for hardware
125 vendors testing the chip. It superceedes
126 warn_explicit_parallel_conflicts. */
127 static int ignore_parallel_conflicts
= 0;
129 /* Non-zero if insns can be made parallel. */
130 static int use_parallel
= 1;
132 /* Non-zero if optimizations should be performed. */
136 static int m32r_flags
= 0;
138 /* Stuff for .scomm symbols. */
139 static segT sbss_section
;
140 static asection scom_section
;
141 static asymbol scom_symbol
;
143 const char comment_chars
[] = ";";
144 const char line_comment_chars
[] = "#";
145 const char line_separator_chars
[] = "!";
146 const char EXP_CHARS
[] = "eE";
147 const char FLT_CHARS
[] = "dD";
149 /* Relocations against symbols are done in two
150 parts, with a HI relocation and a LO relocation. Each relocation
151 has only 16 bits of space to store an addend. This means that in
152 order for the linker to handle carries correctly, it must be able
153 to locate both the HI and the LO relocation. This means that the
154 relocations must appear in order in the relocation table.
156 In order to implement this, we keep track of each unmatched HI
157 relocation. We then sort them so that they immediately precede the
158 corresponding LO relocation. */
163 struct m32r_hi_fixup
*next
;
168 /* The section this fixup is in. */
172 /* The list of unmatched HI relocs. */
174 static struct m32r_hi_fixup
*m32r_hi_fixup_list
;
177 enum bfd_architecture bfd_mach
;
181 { bfd_mach_m32r
, (1<<MACH_M32R
) },
182 { bfd_mach_m32rx
, (1<<MACH_M32RX
) },
183 { bfd_mach_m32r2
, (1<<MACH_M32R2
) }
186 static void allow_m32rx (int);
193 if (stdoutput
!= NULL
)
194 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach_table
[on
].bfd_mach
);
196 if (gas_cgen_cpu_desc
!= NULL
)
197 gas_cgen_cpu_desc
->machs
= mach_table
[on
].mach_flags
;
200 #define M32R_SHORTOPTS "O::K:"
202 const char *md_shortopts
= M32R_SHORTOPTS
;
204 struct option md_longopts
[] =
206 #define OPTION_M32R (OPTION_MD_BASE)
207 #define OPTION_M32RX (OPTION_M32R + 1)
208 #define OPTION_M32R2 (OPTION_M32RX + 1)
209 #define OPTION_BIG (OPTION_M32R2 + 1)
210 #define OPTION_LITTLE (OPTION_BIG + 1)
211 #define OPTION_PARALLEL (OPTION_LITTLE + 1)
212 #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1)
213 #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1)
214 #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
215 #define OPTION_IGNORE_PARALLEL (OPTION_NO_WARN_PARALLEL + 1)
216 #define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1)
217 #define OPTION_SPECIAL (OPTION_NO_IGNORE_PARALLEL + 1)
218 #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1)
219 #define OPTION_NO_SPECIAL_M32R (OPTION_SPECIAL_M32R + 1)
220 #define OPTION_SPECIAL_FLOAT (OPTION_NO_SPECIAL_M32R + 1)
221 #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1)
222 #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
223 {"m32r", no_argument
, NULL
, OPTION_M32R
},
224 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
225 {"m32r2", no_argument
, NULL
, OPTION_M32R2
},
226 {"big", no_argument
, NULL
, OPTION_BIG
},
227 {"little", no_argument
, NULL
, OPTION_LITTLE
},
228 {"EB", no_argument
, NULL
, OPTION_BIG
},
229 {"EL", no_argument
, NULL
, OPTION_LITTLE
},
230 {"parallel", no_argument
, NULL
, OPTION_PARALLEL
},
231 {"no-parallel", no_argument
, NULL
, OPTION_NO_PARALLEL
},
232 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
233 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
234 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
235 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
236 {"ignore-parallel-conflicts", no_argument
, NULL
, OPTION_IGNORE_PARALLEL
},
237 {"Ip", no_argument
, NULL
, OPTION_IGNORE_PARALLEL
},
238 {"no-ignore-parallel-conflicts", no_argument
, NULL
, OPTION_NO_IGNORE_PARALLEL
},
239 {"nIp", no_argument
, NULL
, OPTION_NO_IGNORE_PARALLEL
},
240 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
241 {"bitinst", no_argument
, NULL
, OPTION_SPECIAL_M32R
},
242 {"no-bitinst", no_argument
, NULL
, OPTION_NO_SPECIAL_M32R
},
243 {"float", no_argument
, NULL
, OPTION_SPECIAL_FLOAT
},
244 /* Sigh. I guess all warnings must now have both variants. */
245 {"warn-unmatched-high", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
246 {"Wuh", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
247 {"no-warn-unmatched-high", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
248 {"Wnuh", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
251 /* Not supported yet. */
252 #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1)
253 #define OPTION_CPU_DESC (OPTION_RELAX + 1)
254 {"relax", no_argument
, NULL
, OPTION_RELAX
},
255 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
257 {NULL
, no_argument
, NULL
, 0}
260 size_t md_longopts_size
= sizeof (md_longopts
);
262 static void little (int);
263 static int parallel (void);
268 target_big_endian
= ! on
;
271 /* Use parallel execution. */
279 if (use_parallel
== 1)
286 md_parse_option (c
, arg
)
288 char *arg ATTRIBUTE_UNUSED
;
308 enable_special_m32r
= 1;
312 target_big_endian
= 1;
316 target_big_endian
= 0;
319 case OPTION_PARALLEL
:
323 case OPTION_NO_PARALLEL
:
327 case OPTION_WARN_PARALLEL
:
328 warn_explicit_parallel_conflicts
= 1;
331 case OPTION_NO_WARN_PARALLEL
:
332 warn_explicit_parallel_conflicts
= 0;
335 case OPTION_IGNORE_PARALLEL
:
336 ignore_parallel_conflicts
= 1;
339 case OPTION_NO_IGNORE_PARALLEL
:
340 ignore_parallel_conflicts
= 0;
348 /* Pretend that we do not recognise this option. */
349 as_bad (_("Unrecognised option: -hidden"));
354 case OPTION_SPECIAL_M32R
:
355 enable_special_m32r
= 1;
358 case OPTION_NO_SPECIAL_M32R
:
359 enable_special_m32r
= 0;
362 case OPTION_SPECIAL_FLOAT
:
363 enable_special_float
= 1;
366 case OPTION_WARN_UNMATCHED
:
367 warn_unmatched_high
= 1;
370 case OPTION_NO_WARN_UNMATCHED
:
371 warn_unmatched_high
= 0;
375 if (strcmp (arg
, "PIC") != 0)
376 as_warn (_("Unrecognized option following -K"));
382 /* Not supported yet. */
386 case OPTION_CPU_DESC
:
399 md_show_usage (stream
)
402 fprintf (stream
, _(" M32R specific command line options:\n"));
404 fprintf (stream
, _("\
405 -m32r disable support for the m32rx instruction set\n"));
406 fprintf (stream
, _("\
407 -m32rx support the extended m32rx instruction set\n"));
408 fprintf (stream
, _("\
409 -m32r2 support the extended m32r2 instruction set\n"));
410 fprintf (stream
, _("\
411 -EL,-little produce little endian code and data\n"));
412 fprintf (stream
, _("\
413 -EB,-big produce big endian code and data\n"));
414 fprintf (stream
, _("\
415 -parallel try to combine instructions in parallel\n"));
416 fprintf (stream
, _("\
417 -no-parallel disable -parallel\n"));
418 fprintf (stream
, _("\
419 -no-bitinst disallow the M32R2's extended bit-field instructions\n"));
420 fprintf (stream
, _("\
421 -O try to optimize code. Implies -parallel\n"));
423 fprintf (stream
, _("\
424 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
425 fprintf (stream
, _("\
426 might violate contraints\n"));
427 fprintf (stream
, _("\
428 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
429 fprintf (stream
, _("\
430 instructions might violate contraints\n"));
431 fprintf (stream
, _("\
432 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
433 fprintf (stream
, _("\
434 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
435 fprintf (stream
, _("\
436 -ignore-parallel-conflicts do not check parallel instructions\n"));
437 fprintf (stream
, _("\
438 fo contraint violations\n"));
439 fprintf (stream
, _("\
440 -no-ignore-parallel-conflicts check parallel instructions for\n"));
441 fprintf (stream
, _("\
442 contraint violations\n"));
443 fprintf (stream
, _("\
444 -Ip synonym for -ignore-parallel-conflicts\n"));
445 fprintf (stream
, _("\
446 -nIp synonym for -no-ignore-parallel-conflicts\n"));
448 fprintf (stream
, _("\
449 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
450 fprintf (stream
, _("\
451 -no-warn-unmatched-high do not warn about missing low relocs\n"));
452 fprintf (stream
, _("\
453 -Wuh synonym for -warn-unmatched-high\n"));
454 fprintf (stream
, _("\
455 -Wnuh synonym for -no-warn-unmatched-high\n"));
457 fprintf (stream
, _("\
458 -KPIC generate PIC\n"));
461 fprintf (stream
, _("\
462 -relax create linker relaxable code\n"));
463 fprintf (stream
, _("\
464 -cpu-desc provide runtime cpu description file\n"));
468 static void fill_insn
PARAMS ((int));
469 static void m32r_scomm
PARAMS ((int));
470 static void debug_sym
PARAMS ((int));
471 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
473 /* Set by md_assemble for use by m32r_fill_insn. */
474 static subsegT prev_subseg
;
475 static segT prev_seg
;
477 /* The target specific pseudo-ops which we support. */
478 const pseudo_typeS md_pseudo_table
[] =
481 { "fillinsn", fill_insn
, 0 },
482 { "scomm", m32r_scomm
, 0 },
483 { "debugsym", debug_sym
, 0 },
484 { "m32r", allow_m32rx
, 0 },
485 { "m32rx", allow_m32rx
, 1 },
486 { "m32r2", allow_m32rx
, 2 },
487 { "little", little
, 1 },
488 { "big", little
, 0 },
492 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
493 symbolS
* GOT_symbol
;
496 m32r_PIC_related_p (symbolS
*sym
)
503 if (sym
== GOT_symbol
)
506 exp
= symbol_get_value_expression (sym
);
508 return (exp
->X_op
== O_PIC_reloc
509 || exp
->X_md
== BFD_RELOC_M32R_26_PLTREL
510 || m32r_PIC_related_p (exp
->X_add_symbol
)
511 || m32r_PIC_related_p (exp
->X_op_symbol
));
515 m32r_check_fixup (expressionS
*main_exp
, bfd_reloc_code_real_type
*r_type_p
)
517 expressionS
*exp
= main_exp
;
519 if (exp
->X_op
== O_add
&& m32r_PIC_related_p (exp
->X_op_symbol
))
522 if (exp
->X_op
== O_symbol
&& exp
->X_add_symbol
)
524 if (exp
->X_add_symbol
== GOT_symbol
)
526 *r_type_p
= BFD_RELOC_M32R_GOTPC24
;
530 else if (exp
->X_op
== O_add
)
532 exp
= symbol_get_value_expression (exp
->X_add_symbol
);
537 if (exp
->X_op
== O_PIC_reloc
|| exp
->X_md
!= BFD_RELOC_UNUSED
)
539 *r_type_p
= exp
->X_md
;
541 exp
->X_op
= O_symbol
;
544 main_exp
->X_add_symbol
= exp
->X_add_symbol
;
545 main_exp
->X_add_number
+= exp
->X_add_number
;
549 return (m32r_PIC_related_p (exp
->X_add_symbol
)
550 || m32r_PIC_related_p (exp
->X_op_symbol
));
555 /* FIXME: Should be machine generated. */
556 #define NOP_INSN 0x7000
557 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
559 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
560 of an rs_align_code fragment. */
563 m32r_handle_align (fragp
)
566 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
567 static const unsigned char multi_nop_pattern
[] = { 0x70, 0x00, 0xf0, 0x00 };
572 if (fragp
->fr_type
!= rs_align_code
)
575 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
576 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
588 memcpy (p
, nop_pattern
, 2);
594 memcpy (p
, multi_nop_pattern
, 4);
596 fragp
->fr_fix
+= fix
;
600 /* If the last instruction was the first of 2 16 bit insns,
601 output a nop to move the PC to a 32 bit boundary.
603 This is done via an alignment specification since branch relaxing
604 may make it unnecessary.
606 Internally, we need to output one of these each time a 32 bit insn is
607 seen after an insn that is relaxable. */
611 int ignore ATTRIBUTE_UNUSED
;
613 frag_align_code (2, 0);
614 prev_insn
.insn
= NULL
;
615 seen_relaxable_p
= 0;
618 /* Record the symbol so that when we output the insn, we can create
619 a symbol that is at the start of the instruction. This is used
620 to emit the label for the start of a breakpoint without causing
621 the assembler to emit a NOP if the previous instruction was a
622 16 bit instruction. */
626 int ignore ATTRIBUTE_UNUSED
;
630 register char *end_name
;
631 register symbolS
*symbolP
;
632 register sym_linkS
*link
;
634 name
= input_line_pointer
;
635 delim
= get_symbol_end ();
636 end_name
= input_line_pointer
;
638 if ((symbolP
= symbol_find (name
)) == NULL
639 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
641 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
644 symbol_table_insert (symbolP
);
645 if (S_IS_DEFINED (symbolP
) && (S_GET_SEGMENT (symbolP
) != reg_section
646 || S_IS_EXTERNAL (symbolP
)
647 || S_IS_WEAK (symbolP
)))
648 /* xgettext:c-format */
649 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
653 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
654 link
->symbol
= symbolP
;
655 link
->next
= debug_sym_link
;
656 debug_sym_link
= link
;
657 symbol_get_obj (symbolP
)->local
= 1;
661 demand_empty_rest_of_line ();
664 /* Second pass to expanding the debug symbols, go through linked
665 list of symbols and reassign the address. */
668 expand_debug_syms (syms
, align
)
672 char *save_input_line
= input_line_pointer
;
673 sym_linkS
*next_syms
;
678 (void) frag_align_code (align
, 0);
679 for (; syms
!= (sym_linkS
*) 0; syms
= next_syms
)
681 symbolS
*symbolP
= syms
->symbol
;
682 next_syms
= syms
->next
;
683 input_line_pointer
= ".\n";
684 pseudo_set (symbolP
);
685 free ((char *) syms
);
688 input_line_pointer
= save_input_line
;
692 m32r_flush_pending_output()
696 expand_debug_syms (debug_sym_link
, 1);
697 debug_sym_link
= (sym_linkS
*) 0;
701 /* Cover function to fill_insn called after a label and at end of assembly.
702 The result is always 1: we're called in a conditional to see if the
703 current line is a label. */
706 m32r_fill_insn (done
)
709 if (prev_seg
!= NULL
)
712 subsegT subseg
= now_subseg
;
714 subseg_set (prev_seg
, prev_subseg
);
718 subseg_set (seg
, subseg
);
721 if (done
&& debug_sym_link
)
723 expand_debug_syms (debug_sym_link
, 1);
724 debug_sym_link
= (sym_linkS
*) 0;
730 /* The default target format to use. */
733 m32r_target_format ()
736 if (target_big_endian
)
737 return "elf32-m32r-linux";
739 return "elf32-m32rle-linux";
741 if (target_big_endian
)
744 return "elf32-m32rle";
755 /* Initialize the `cgen' interface. */
757 /* Set the machine number and endian. */
758 gas_cgen_cpu_desc
= m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, 0,
759 CGEN_CPU_OPEN_ENDIAN
,
761 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
),
763 m32r_cgen_init_asm (gas_cgen_cpu_desc
);
765 /* The operand instance table is used during optimization to determine
766 which insns can be executed in parallel. It is also used to give
767 warnings regarding operand interference in parallel insns. */
768 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc
);
770 /* This is a callback from cgen to gas to parse operands. */
771 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, gas_cgen_parse_operand
);
774 /* Not supported yet. */
775 /* If a runtime cpu description file was provided, parse it. */
776 if (m32r_cpu_desc
!= NULL
)
780 errmsg
= cgen_read_cpu_file (gas_cgen_cpu_desc
, m32r_cpu_desc
);
782 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
786 /* Save the current subseg so we can restore it [it's the default one and
787 we don't want the initial section to be .sbss]. */
791 /* The sbss section is for local .scomm symbols. */
792 sbss_section
= subseg_new (".sbss", 0);
794 /* This is copied from perform_an_assembly_pass. */
795 applicable
= bfd_applicable_section_flags (stdoutput
);
796 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
799 /* What does this do? [see perform_an_assembly_pass] */
800 seg_info (bss_section
)->bss
= 1;
803 subseg_set (seg
, subseg
);
805 /* We must construct a fake section similar to bfd_com_section
806 but with the name .scommon. */
807 scom_section
= bfd_com_section
;
808 scom_section
.name
= ".scommon";
809 scom_section
.output_section
= &scom_section
;
810 scom_section
.symbol
= &scom_symbol
;
811 scom_section
.symbol_ptr_ptr
= &scom_section
.symbol
;
812 scom_symbol
= *bfd_com_section
.symbol
;
813 scom_symbol
.name
= ".scommon";
814 scom_symbol
.section
= &scom_section
;
816 allow_m32rx (enable_m32rx
);
818 gas_cgen_initialize_saved_fixups_array ();
821 #define OPERAND_IS_COND_BIT(operand, indices, index) \
822 ((operand)->hw_type == HW_H_COND \
823 || ((operand)->hw_type == HW_H_PSW) \
824 || ((operand)->hw_type == HW_H_CR \
825 && (indices [index] == 0 || indices [index] == 1)))
827 /* Returns true if an output of instruction 'a' is referenced by an operand
828 of instruction 'b'. If 'check_outputs' is true then b's outputs are
829 checked, otherwise its inputs are examined. */
831 static int first_writes_to_seconds_operands
832 PARAMS ((m32r_insn
*, m32r_insn
*, const int));
835 first_writes_to_seconds_operands (a
, b
, check_outputs
)
838 const int check_outputs
;
840 const CGEN_OPINST
*a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
841 const CGEN_OPINST
*b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
844 if (ignore_parallel_conflicts
)
847 /* If at least one of the instructions takes no operands, then there is
848 nothing to check. There really are instructions without operands,
850 if (a_operands
== NULL
|| b_ops
== NULL
)
853 /* Scan the operand list of 'a' looking for an output operand. */
855 a_operands
->type
!= CGEN_OPINST_END
;
856 a_index
++, a_operands
++)
858 if (a_operands
->type
== CGEN_OPINST_OUTPUT
)
861 const CGEN_OPINST
*b_operands
= b_ops
;
864 The Condition bit 'C' is a shadow of the CBR register (control
865 register 1) and also a shadow of bit 31 of the program status
866 word (control register 0). For now this is handled here, rather
869 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
871 /* Scan operand list of 'b' looking for another reference to the
872 condition bit, which goes in the right direction. */
874 b_operands
->type
!= CGEN_OPINST_END
;
875 b_index
++, b_operands
++)
877 if ((b_operands
->type
880 : CGEN_OPINST_INPUT
))
881 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
887 /* Scan operand list of 'b' looking for an operand that
888 references the same hardware element, and which goes in the
891 b_operands
->type
!= CGEN_OPINST_END
;
892 b_index
++, b_operands
++)
894 if ((b_operands
->type
897 : CGEN_OPINST_INPUT
))
898 && (b_operands
->hw_type
== a_operands
->hw_type
)
899 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
909 /* Returns true if the insn can (potentially) alter the program counter. */
911 static int writes_to_pc
PARAMS ((m32r_insn
*));
918 /* Once PC operands are working.... */
919 const CGEN_OPINST
*a_operands
== CGEN_INSN_OPERANDS (gas_cgen_cpu_desc
,
922 if (a_operands
== NULL
)
925 while (a_operands
->type
!= CGEN_OPINST_END
)
927 if (a_operands
->operand
!= NULL
928 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc
,
929 a_operands
->operand
) == M32R_OPERAND_PC
)
935 if (CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_UNCOND_CTI
)
936 || CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_COND_CTI
))
942 /* Return NULL if the two 16 bit insns can be executed in parallel.
943 Otherwise return a pointer to an error message explaining why not. */
945 static const char *can_make_parallel
PARAMS ((m32r_insn
*, m32r_insn
*));
948 can_make_parallel (a
, b
)
955 /* Make sure the instructions are the right length. */
956 if (CGEN_FIELDS_BITSIZE (&a
->fields
) != 16
957 || CGEN_FIELDS_BITSIZE (&b
->fields
) != 16)
960 if (first_writes_to_seconds_operands (a
, b
, TRUE
))
961 return _("instructions write to the same destination register.");
963 a_pipe
= CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_PIPE
);
964 b_pipe
= CGEN_INSN_ATTR_VALUE (b
->insn
, CGEN_INSN_PIPE
);
966 /* Make sure that the instructions use the correct execution pipelines. */
967 if (a_pipe
== PIPE_NONE
968 || b_pipe
== PIPE_NONE
)
969 return _("Instructions do not use parallel execution pipelines.");
971 /* Leave this test for last, since it is the only test that can
972 go away if the instructions are swapped, and we want to make
973 sure that any other errors are detected before this happens. */
976 || (b_pipe
== PIPE_O_OS
&& (enable_m32rx
!= 2)))
977 return _("Instructions share the same execution pipeline");
982 /* Force the top bit of the second 16-bit insn to be set. */
984 static void make_parallel
PARAMS ((CGEN_INSN_BYTES_PTR
));
987 make_parallel (buffer
)
988 CGEN_INSN_BYTES_PTR buffer
;
993 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
998 /* Same as make_parallel except buffer contains the bytes in target order. */
1000 static void target_make_parallel
PARAMS ((char *));
1003 target_make_parallel (buffer
)
1006 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
1010 /* Assemble two instructions with an explicit parallel operation (||) or
1011 sequential operation (->). */
1013 static void assemble_two_insns
PARAMS ((char *, char *, int));
1016 assemble_two_insns (str
, str2
, parallel_p
)
1025 char save_str2
= *str2
;
1027 /* Separate the two instructions. */
1030 /* Make sure the two insns begin on a 32 bit boundary.
1031 This is also done for the serial case (foo -> bar), relaxing doesn't
1032 affect insns written like this.
1033 Note that we must always do this as we can't assume anything about
1034 whether we're currently on a 32 bit boundary or not. Relaxing may
1038 first
.debug_sym_link
= debug_sym_link
;
1039 debug_sym_link
= (sym_linkS
*) 0;
1041 /* Parse the first instruction. */
1042 if (! (first
.insn
= m32r_cgen_assemble_insn
1043 (gas_cgen_cpu_desc
, str
, & first
.fields
, first
.buffer
, & errmsg
)))
1050 if (CGEN_FIELDS_BITSIZE (&first
.fields
) != 16)
1052 /* xgettext:c-format */
1053 as_bad (_("not a 16 bit instruction '%s'"), str
);
1057 else if ((enable_m32rx
== 1)
1058 /* FIXME: Need standard macro to perform this test. */
1059 && ((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1060 & (1 << MACH_M32R2
))
1061 && !((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1062 & (1 << MACH_M32RX
)))))
1064 /* xgettext:c-format */
1065 as_bad (_("instruction '%s' is for the M32R2 only"), str
);
1068 else if ((! enable_special
1069 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
1070 || (! enable_special_m32r
1071 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL_M32R
)))
1073 else if (! enable_special
1074 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
1077 /* xgettext:c-format */
1078 as_bad (_("unknown instruction '%s'"), str
);
1081 else if (! enable_m32rx
1082 /* FIXME: Need standard macro to perform this test. */
1083 && (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1084 == (1 << MACH_M32RX
)))
1086 /* xgettext:c-format */
1087 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1091 /* Check to see if this is an allowable parallel insn. */
1093 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
1095 /* xgettext:c-format */
1096 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
1100 /* Restore the original assembly text, just in case it is needed. */
1103 /* Save the original string pointer. */
1106 /* Advanced past the parsed string. */
1109 /* Remember the entire string in case it is needed for error
1113 /* Convert the opcode to lower case. */
1117 while (ISSPACE (*s2
++))
1122 while (ISALNUM (*s2
))
1124 *s2
= TOLOWER (*s2
);
1129 /* Preserve any fixups that have been generated and reset the list
1131 gas_cgen_save_fixups (0);
1133 /* Get the indices of the operands of the instruction. */
1134 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
1135 doesn't seem right. Perhaps allow passing fields like we do insn. */
1136 /* FIXME: ALIAS insns do not have operands, so we use this function
1137 to find the equivalent insn and overwrite the value stored in our
1138 structure. We still need the original insn, however, since this
1139 may have certain attributes that are not present in the unaliased
1140 version (eg relaxability). When aliases behave differently this
1141 may have to change. */
1142 first
.orig_insn
= first
.insn
;
1144 CGEN_FIELDS tmp_fields
;
1145 first
.insn
= cgen_lookup_get_insn_operands
1146 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (first
.buffer
), NULL
, 16,
1147 first
.indices
, &tmp_fields
);
1150 if (first
.insn
== NULL
)
1151 as_fatal (_("internal error: lookup/get operands failed"));
1153 second
.debug_sym_link
= NULL
;
1155 /* Parse the second instruction. */
1156 if (! (second
.insn
= m32r_cgen_assemble_insn
1157 (gas_cgen_cpu_desc
, str
, & second
.fields
, second
.buffer
, & errmsg
)))
1164 if (CGEN_FIELDS_BITSIZE (&second
.fields
) != 16)
1166 /* xgettext:c-format */
1167 as_bad (_("not a 16 bit instruction '%s'"), str
);
1171 else if ((enable_m32rx
== 1)
1172 /* FIXME: Need standard macro to perform this test. */
1173 && ((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1174 & (1 << MACH_M32R2
))
1175 && !((CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
)
1176 & (1 << MACH_M32RX
)))))
1178 /* xgettext:c-format */
1179 as_bad (_("instruction '%s' is for the M32R2 only"), str
);
1182 else if ((! enable_special
1183 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
1184 || (! enable_special_m32r
1185 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL_M32R
)))
1187 else if (! enable_special
1188 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
1191 /* xgettext:c-format */
1192 as_bad (_("unknown instruction '%s'"), str
);
1195 else if (! enable_m32rx
1196 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1198 /* xgettext:c-format */
1199 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1203 /* Check to see if this is an allowable parallel insn. */
1205 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
1207 /* xgettext:c-format */
1208 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
1212 if (parallel_p
&& ! enable_m32rx
)
1214 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
1215 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
1217 /* xgettext:c-format */
1218 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
1223 /* Get the indices of the operands of the instruction. */
1224 second
.orig_insn
= second
.insn
;
1226 CGEN_FIELDS tmp_fields
;
1227 second
.insn
= cgen_lookup_get_insn_operands
1228 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (second
.buffer
), NULL
, 16,
1229 second
.indices
, &tmp_fields
);
1232 if (second
.insn
== NULL
)
1233 as_fatal (_("internal error: lookup/get operands failed"));
1235 /* We assume that if the first instruction writes to a register that is
1236 read by the second instruction it is because the programmer intended
1237 this to happen, (after all they have explicitly requested that these
1238 two instructions be executed in parallel). Although if the global
1239 variable warn_explicit_parallel_conflicts is true then we do generate
1240 a warning message. Similarly we assume that parallel branch and jump
1241 instructions are deliberate and should not produce errors. */
1243 if (parallel_p
&& warn_explicit_parallel_conflicts
)
1245 if (first_writes_to_seconds_operands (&first
, &second
, FALSE
))
1246 /* xgettext:c-format */
1247 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
1249 if (first_writes_to_seconds_operands (&second
, &first
, FALSE
))
1250 /* xgettext:c-format */
1251 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
1255 || (errmsg
= (char *) can_make_parallel (&first
, &second
)) == NULL
)
1257 /* Get the fixups for the first instruction. */
1258 gas_cgen_swap_fixups (0);
1261 expand_debug_syms (first
.debug_sym_link
, 1);
1262 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
1263 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
1265 /* Force the top bit of the second insn to be set. */
1267 make_parallel (second
.buffer
);
1269 /* Get its fixups. */
1270 gas_cgen_restore_fixups (0);
1273 expand_debug_syms (second
.debug_sym_link
, 1);
1274 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
1275 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
1277 /* Try swapping the instructions to see if they work that way. */
1278 else if (can_make_parallel (&second
, &first
) == NULL
)
1280 /* Write out the second instruction first. */
1281 expand_debug_syms (second
.debug_sym_link
, 1);
1282 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
1283 CGEN_FIELDS_BITSIZE (&second
.fields
), 0, NULL
);
1285 /* Force the top bit of the first instruction to be set. */
1286 make_parallel (first
.buffer
);
1288 /* Get the fixups for the first instruction. */
1289 gas_cgen_restore_fixups (0);
1291 /* Write out the first instruction. */
1292 expand_debug_syms (first
.debug_sym_link
, 1);
1293 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
1294 CGEN_FIELDS_BITSIZE (&first
.fields
), 0, NULL
);
1298 as_bad ("'%s': %s", str2
, errmsg
);
1302 if (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
)
1303 || CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
1304 m32r_flags
|= E_M32R_HAS_HIDDEN_INST
;
1305 if (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL_M32R
)
1306 || CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL_M32R
))
1307 m32r_flags
|= E_M32R_HAS_BIT_INST
;
1308 if (CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL_FLOAT
)
1309 || CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL_FLOAT
))
1310 m32r_flags
|= E_M32R_HAS_FLOAT_INST
;
1312 /* Set these so m32r_fill_insn can use them. */
1314 prev_subseg
= now_subseg
;
1325 /* Initialize GAS's cgen interface for a new instruction. */
1326 gas_cgen_init_parse ();
1328 /* Look for a parallel instruction separator. */
1329 if ((str2
= strstr (str
, "||")) != NULL
)
1331 assemble_two_insns (str
, str2
, 1);
1332 m32r_flags
|= E_M32R_HAS_PARALLEL
;
1336 /* Also look for a sequential instruction separator. */
1337 if ((str2
= strstr (str
, "->")) != NULL
)
1339 assemble_two_insns (str
, str2
, 0);
1343 insn
.debug_sym_link
= debug_sym_link
;
1344 debug_sym_link
= (sym_linkS
*) 0;
1346 insn
.insn
= m32r_cgen_assemble_insn
1347 (gas_cgen_cpu_desc
, str
, &insn
.fields
, insn
.buffer
, & errmsg
);
1356 if ((enable_m32rx
== 1)
1357 /* FIXME: Need standard macro to perform this test. */
1358 && ((CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
)
1359 & (1 << MACH_M32R2
))
1360 && !((CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
)
1361 & (1 << MACH_M32RX
)))))
1363 /* xgettext:c-format */
1364 as_bad (_("instruction '%s' is for the M32R2 only"), str
);
1367 else if ((! enable_special
1368 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1369 || (! enable_special_m32r
1370 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL_M32R
)))
1372 if (! enable_special
1373 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1376 /* xgettext:c-format */
1377 as_bad (_("unknown instruction '%s'"), str
);
1380 else if (! enable_m32rx
1381 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1383 /* xgettext:c-format */
1384 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1388 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1389 m32r_flags
|= E_M32R_HAS_HIDDEN_INST
;
1390 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL_M32R
))
1391 m32r_flags
|= E_M32R_HAS_BIT_INST
;
1392 if (CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL_FLOAT
))
1393 m32r_flags
|= E_M32R_HAS_FLOAT_INST
;
1395 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
1397 /* 32 bit insns must live on 32 bit boundaries. */
1398 if (prev_insn
.insn
|| seen_relaxable_p
)
1400 /* ??? If calling fill_insn too many times turns us into a memory
1401 pig, can we call a fn to assemble a nop instead of
1402 !seen_relaxable_p? */
1406 expand_debug_syms (insn
.debug_sym_link
, 2);
1408 /* Doesn't really matter what we pass for RELAX_P here. */
1409 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1410 CGEN_FIELDS_BITSIZE (&insn
.fields
), 1, NULL
);
1414 int on_32bit_boundary_p
;
1417 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1420 insn
.orig_insn
= insn
.insn
;
1422 /* If the previous insn was relaxable, then it may be expanded
1423 to fill the current 16 bit slot. Emit a NOP here to occupy
1424 this slot, so that we can start at optimizing at a 32 bit
1426 if (prev_insn
.insn
&& seen_relaxable_p
&& optimize
)
1431 /* Get the indices of the operands of the instruction.
1432 FIXME: See assemble_parallel for notes on orig_insn. */
1434 CGEN_FIELDS tmp_fields
;
1435 insn
.insn
= cgen_lookup_get_insn_operands
1436 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (insn
.buffer
), NULL
,
1437 16, insn
.indices
, &tmp_fields
);
1440 if (insn
.insn
== NULL
)
1441 as_fatal (_("internal error: lookup/get operands failed"));
1444 /* Compute whether we're on a 32 bit boundary or not.
1445 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1446 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1448 /* Change a frag to, if each insn to swap is in a different frag.
1449 It must keep only one instruction in a frag. */
1450 if (parallel() && on_32bit_boundary_p
)
1452 frag_wane (frag_now
);
1456 /* Look to see if this instruction can be combined with the
1457 previous instruction to make one, parallel, 32 bit instruction.
1458 If the previous instruction (potentially) changed the flow of
1459 program control, then it cannot be combined with the current
1460 instruction. If the current instruction is relaxable, then it
1461 might be replaced with a longer version, so we cannot combine it.
1462 Also if the output of the previous instruction is used as an
1463 input to the current instruction then it cannot be combined.
1464 Otherwise call can_make_parallel() with both orderings of the
1465 instructions to see if they can be combined. */
1466 if (! on_32bit_boundary_p
1468 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1469 && ! writes_to_pc (&prev_insn
)
1470 && ! first_writes_to_seconds_operands (&prev_insn
, &insn
, FALSE
))
1472 if (can_make_parallel (&prev_insn
, &insn
) == NULL
)
1473 make_parallel (insn
.buffer
);
1474 else if (can_make_parallel (&insn
, &prev_insn
) == NULL
)
1478 expand_debug_syms (insn
.debug_sym_link
, 1);
1484 /* Ensure each pair of 16 bit insns is in the same frag. */
1487 gas_cgen_finish_insn (insn
.orig_insn
, insn
.buffer
,
1488 CGEN_FIELDS_BITSIZE (&insn
.fields
),
1489 1 /* relax_p */, &fi
);
1490 insn
.addr
= fi
.addr
;
1491 insn
.frag
= fi
.frag
;
1492 insn
.num_fixups
= fi
.num_fixups
;
1493 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1494 insn
.fixups
[i
] = fi
.fixups
[i
];
1501 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1503 /* Swap the two insns */
1504 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1505 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1507 target_make_parallel (insn
.addr
);
1509 /* Swap any relaxable frags recorded for the two insns. */
1510 /* FIXME: Clarify. relaxation precludes parallel insns */
1511 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1512 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1513 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1514 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1516 /* Change a frag to, if each insn is in a different frag.
1517 It must keep only one instruction in a frag. */
1518 if (prev_insn
.frag
!= insn
.frag
)
1520 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1521 prev_insn
.fixups
[i
]->fx_frag
= insn
.frag
;
1522 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1523 insn
.fixups
[i
]->fx_frag
= prev_insn
.frag
;
1527 /* Update the addresses in any fixups.
1528 Note that we don't have to handle the case where each insn is in
1529 a different frag as we ensure they're in the same frag above. */
1530 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1531 prev_insn
.fixups
[i
]->fx_where
+= 2;
1532 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1533 insn
.fixups
[i
]->fx_where
-= 2;
1537 /* Keep track of whether we've seen a pair of 16 bit insns.
1538 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1539 if (on_32bit_boundary_p
)
1542 prev_insn
.insn
= NULL
;
1544 /* If the insn needs the following one to be on a 32 bit boundary
1545 (e.g. subroutine calls), fill this insn's slot. */
1546 if (on_32bit_boundary_p
1547 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1550 /* If this is a relaxable insn (can be replaced with a larger version)
1551 mark the fact so that we can emit an alignment directive for a
1552 following 32 bit insn if we see one. */
1553 if (CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1554 seen_relaxable_p
= 1;
1557 /* Set these so m32r_fill_insn can use them. */
1559 prev_subseg
= now_subseg
;
1562 /* The syntax in the manual says constants begin with '#'.
1563 We just ignore it. */
1566 md_operand (expressionP
)
1567 expressionS
*expressionP
;
1569 if (*input_line_pointer
== '#')
1571 input_line_pointer
++;
1572 expression (expressionP
);
1577 md_section_align (segment
, size
)
1581 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1582 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1586 md_undefined_symbol (name
)
1587 char *name ATTRIBUTE_UNUSED
;
1592 /* .scomm pseudo-op handler.
1594 This is a new pseudo-op to handle putting objects in .scommon.
1595 By doing this the linker won't need to do any work,
1596 and more importantly it removes the implicit -G arg necessary to
1597 correctly link the object file. */
1601 int ignore ATTRIBUTE_UNUSED
;
1603 register char *name
;
1607 register symbolS
*symbolP
;
1611 name
= input_line_pointer
;
1612 c
= get_symbol_end ();
1614 /* Just after name is now '\0'. */
1615 p
= input_line_pointer
;
1618 if (*input_line_pointer
!= ',')
1620 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1621 ignore_rest_of_line ();
1626 input_line_pointer
++;
1627 if ((size
= get_absolute_expression ()) < 0)
1629 /* xgettext:c-format */
1630 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1631 ignore_rest_of_line ();
1635 /* The third argument to .scomm is the alignment. */
1636 if (*input_line_pointer
!= ',')
1640 ++input_line_pointer
;
1641 align
= get_absolute_expression ();
1644 as_warn (_("ignoring bad alignment"));
1649 /* Convert to a power of 2 alignment. */
1652 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++align2
)
1656 as_bad (_("Common alignment not a power of 2"));
1657 ignore_rest_of_line ();
1665 symbolP
= symbol_find_or_make (name
);
1668 if (S_IS_DEFINED (symbolP
))
1670 /* xgettext:c-format */
1671 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1672 S_GET_NAME (symbolP
));
1673 ignore_rest_of_line ();
1677 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1679 /* xgettext:c-format */
1680 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1681 S_GET_NAME (symbolP
),
1682 (long) S_GET_VALUE (symbolP
),
1685 ignore_rest_of_line ();
1689 if (symbol_get_obj (symbolP
)->local
)
1691 segT old_sec
= now_seg
;
1692 int old_subsec
= now_subseg
;
1695 record_alignment (sbss_section
, align2
);
1696 subseg_set (sbss_section
, 0);
1699 frag_align (align2
, 0, 0);
1701 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1702 symbol_get_frag (symbolP
)->fr_symbol
= 0;
1704 symbol_set_frag (symbolP
, frag_now
);
1706 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1709 S_SET_SIZE (symbolP
, size
);
1710 S_SET_SEGMENT (symbolP
, sbss_section
);
1711 S_CLEAR_EXTERNAL (symbolP
);
1712 subseg_set (old_sec
, old_subsec
);
1716 S_SET_VALUE (symbolP
, (valueT
) size
);
1717 S_SET_ALIGN (symbolP
, align2
);
1718 S_SET_EXTERNAL (symbolP
);
1719 S_SET_SEGMENT (symbolP
, &scom_section
);
1722 demand_empty_rest_of_line ();
1725 /* Interface to relax_segment. */
1727 /* FIXME: Build table by hand, get it working, then machine generate. */
1729 const relax_typeS md_relax_table
[] =
1732 1) most positive reach of this state,
1733 2) most negative reach of this state,
1734 3) how many bytes this mode will add to the size of the current frag
1735 4) which index into the table to try if we can't fit into this one. */
1737 /* The first entry must be unused because an `rlx_more' value of zero ends
1741 /* The displacement used by GAS is from the end of the 2 byte insn,
1742 so we subtract 2 from the following. */
1743 /* 16 bit insn, 8 bit disp -> 10 bit range.
1744 This doesn't handle a branch in the right slot at the border:
1745 the "& -4" isn't taken into account. It's not important enough to
1746 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1748 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1749 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1750 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1751 /* Same thing, but with leading nop for alignment. */
1752 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1756 m32r_relax_frag (segment
, fragP
, stretch
)
1761 /* Address of branch insn. */
1762 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1765 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1766 if (fragP
->fr_subtype
== 2)
1768 if ((address
& 3) != 0)
1770 fragP
->fr_subtype
= 3;
1774 else if (fragP
->fr_subtype
== 3)
1776 if ((address
& 3) == 0)
1778 fragP
->fr_subtype
= 2;
1784 growth
= relax_frag (segment
, fragP
, stretch
);
1786 /* Long jump on odd halfword boundary? */
1787 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1789 fragP
->fr_subtype
= 3;
1797 /* Return an initial guess of the length by which a fragment must grow to
1798 hold a branch to reach its destination.
1799 Also updates fr_type/fr_subtype as necessary.
1801 Called just before doing relaxation.
1802 Any symbol that is now undefined will not become defined.
1803 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1804 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1805 Although it may not be explicit in the frag, pretend fr_var starts
1809 md_estimate_size_before_relax (fragP
, segment
)
1813 /* The only thing we have to handle here are symbols outside of the
1814 current segment. They may be undefined or in a different segment in
1815 which case linker scripts may place them anywhere.
1816 However, we can't finish the fragment here and emit the reloc as insn
1817 alignment requirements may move the insn about. */
1819 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
1820 || S_IS_EXTERNAL (fragP
->fr_symbol
)
1821 || S_IS_WEAK (fragP
->fr_symbol
))
1824 int old_fr_fix
= fragP
->fr_fix
;
1827 /* The symbol is undefined in this segment.
1828 Change the relaxation subtype to the max allowable and leave
1829 all further handling to md_convert_frag. */
1830 fragP
->fr_subtype
= 2;
1833 /* Can't use this, but leave in for illustration. */
1834 /* Change 16 bit insn to 32 bit insn. */
1835 fragP
->fr_opcode
[0] |= 0x80;
1837 /* Increase known (fixed) size of fragment. */
1840 /* Create a relocation for it. */
1841 fix_new (fragP
, old_fr_fix
, 4,
1843 fragP
->fr_offset
, 1 /* pcrel */,
1844 /* FIXME: Can't use a real BFD reloc here.
1845 gas_cgen_md_apply_fix3 can't handle it. */
1846 BFD_RELOC_M32R_26_PCREL
);
1848 /* Mark this fragment as finished. */
1850 return fragP
->fr_fix
- old_fr_fix
;
1853 const CGEN_INSN
*insn
;
1856 /* Update the recorded insn.
1857 Fortunately we don't have to look very far.
1858 FIXME: Change this to record in the instruction the next higher
1859 relaxable insn to use. */
1860 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1862 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1863 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1865 && CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_RELAXED
))
1871 fragP
->fr_cgen
.insn
= insn
;
1877 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
1880 /* *FRAGP has been relaxed to its final size, and now needs to have
1881 the bytes inside it modified to conform to the new size.
1883 Called after relaxation is finished.
1884 fragP->fr_type == rs_machine_dependent.
1885 fragP->fr_subtype is the subtype of what the address relaxed to. */
1888 md_convert_frag (abfd
, sec
, fragP
)
1889 bfd
*abfd ATTRIBUTE_UNUSED
;
1900 opcode
= fragP
->fr_opcode
;
1902 /* Address opcode resides at in file space. */
1903 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1905 switch (fragP
->fr_subtype
)
1909 displacement
= &opcode
[1];
1914 displacement
= &opcode
[1];
1917 opcode
[2] = opcode
[0] | 0x80;
1918 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1919 opcode_address
+= 2;
1921 displacement
= &opcode
[3];
1927 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
1928 || S_IS_EXTERNAL (fragP
->fr_symbol
)
1929 || S_IS_WEAK (fragP
->fr_symbol
))
1931 /* Symbol must be resolved by linker. */
1932 if (fragP
->fr_offset
& 3)
1933 as_warn (_("Addend to unresolved symbol not on word boundary."));
1934 #ifdef USE_M32R_OLD_RELOC
1935 addend
= fragP
->fr_offset
>> 2; /* Old M32R used USE_REL. */
1942 /* Address we want to reach in file space. */
1943 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1944 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1947 /* Create a relocation for symbols that must be resolved by the linker.
1948 Otherwise output the completed insn. */
1950 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
1951 || S_IS_EXTERNAL (fragP
->fr_symbol
)
1952 || S_IS_WEAK (fragP
->fr_symbol
))
1956 assert (fragP
->fr_subtype
!= 1);
1957 assert (fragP
->fr_cgen
.insn
!= 0);
1959 fixP
= gas_cgen_record_fixup (fragP
,
1960 /* Offset of branch insn in frag. */
1961 fragP
->fr_fix
+ extension
- 4,
1962 fragP
->fr_cgen
.insn
,
1964 /* FIXME: quick hack. */
1966 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1967 fragP
->fr_cgen
.opindex
),
1969 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1970 M32R_OPERAND_DISP24
),
1972 fragP
->fr_cgen
.opinfo
,
1973 fragP
->fr_symbol
, fragP
->fr_offset
);
1974 if (fragP
->fr_cgen
.opinfo
)
1975 fixP
->fx_r_type
= fragP
->fr_cgen
.opinfo
;
1978 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1980 md_number_to_chars (displacement
, (valueT
) addend
,
1981 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1983 fragP
->fr_fix
+= extension
;
1986 /* Functions concerning relocs. */
1988 /* The location from which a PC relative jump should be calculated,
1989 given a PC relative reloc. */
1992 md_pcrel_from_section (fixP
, sec
)
1996 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1997 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1998 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
1999 || S_IS_EXTERNAL (fixP
->fx_addsy
)
2000 || S_IS_WEAK (fixP
->fx_addsy
)))
2002 /* The symbol is undefined (or is defined but not in this section).
2003 Let the linker figure it out. */
2007 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
2010 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
2011 Returns BFD_RELOC_NONE if no reloc type can be found.
2012 *FIXP may be modified if desired. */
2014 bfd_reloc_code_real_type
2015 md_cgen_lookup_reloc (insn
, operand
, fixP
)
2016 const CGEN_INSN
*insn ATTRIBUTE_UNUSED
;
2017 const CGEN_OPERAND
*operand
;
2020 switch (operand
->type
)
2022 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
2023 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
2024 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
2025 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
2026 case M32R_OPERAND_HI16
:
2027 case M32R_OPERAND_SLO16
:
2028 case M32R_OPERAND_ULO16
:
2029 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
2030 if (fixP
->fx_cgen
.opinfo
!= 0)
2031 return fixP
->fx_cgen
.opinfo
;
2034 /* Avoid -Wall warning. */
2037 return BFD_RELOC_NONE
;
2040 /* Record a HI16 reloc for later matching with its LO16 cousin. */
2042 static void m32r_record_hi16
PARAMS ((int, fixS
*, segT
));
2045 m32r_record_hi16 (reloc_type
, fixP
, seg
)
2048 segT seg ATTRIBUTE_UNUSED
;
2050 struct m32r_hi_fixup
*hi_fixup
;
2052 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
2053 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
2055 hi_fixup
= ((struct m32r_hi_fixup
*)
2056 xmalloc (sizeof (struct m32r_hi_fixup
)));
2057 hi_fixup
->fixp
= fixP
;
2058 hi_fixup
->seg
= now_seg
;
2059 hi_fixup
->next
= m32r_hi_fixup_list
;
2061 m32r_hi_fixup_list
= hi_fixup
;
2064 /* Called while parsing an instruction to create a fixup.
2065 We need to check for HI16 relocs and queue them up for later sorting. */
2068 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
2071 const CGEN_INSN
*insn
;
2073 const CGEN_OPERAND
*operand
;
2078 bfd_reloc_code_real_type r_type
= BFD_RELOC_UNUSED
;
2080 if (m32r_check_fixup (exp
, &r_type
))
2081 as_bad (_("Invalid PIC expression."));
2083 fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
2084 operand
, opinfo
, exp
);
2086 switch (operand
->type
)
2088 case M32R_OPERAND_HI16
:
2089 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
2090 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
2091 || fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
2092 m32r_record_hi16 (fixP
->fx_cgen
.opinfo
, fixP
, now_seg
);
2096 /* Avoid -Wall warning. */
2102 case BFD_RELOC_UNUSED
:
2106 case BFD_RELOC_M32R_GOTPC24
:
2107 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
)
2108 r_type
= BFD_RELOC_M32R_GOTPC_HI_SLO
;
2109 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
2110 r_type
= BFD_RELOC_M32R_GOTPC_HI_ULO
;
2111 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_LO16
)
2112 r_type
= BFD_RELOC_M32R_GOTPC_LO
;
2114 case BFD_RELOC_M32R_GOT24
:
2115 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
)
2116 r_type
= BFD_RELOC_M32R_GOT16_HI_SLO
;
2117 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
2118 r_type
= BFD_RELOC_M32R_GOT16_HI_ULO
;
2119 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_LO16
)
2120 r_type
= BFD_RELOC_M32R_GOT16_LO
;
2122 case BFD_RELOC_M32R_GOTOFF
:
2123 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
)
2124 r_type
= BFD_RELOC_M32R_GOTOFF_HI_SLO
;
2125 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
2126 r_type
= BFD_RELOC_M32R_GOTOFF_HI_ULO
;
2127 else if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_LO16
)
2128 r_type
= BFD_RELOC_M32R_GOTOFF_LO
;
2130 case BFD_RELOC_M32R_26_PLTREL
:
2131 as_bad (_("Invalid PIC expression."));
2135 fixP
->fx_r_type
= r_type
;
2140 /* Return BFD reloc type from opinfo field in a fixS.
2141 It's tricky using fx_r_type in m32r_frob_file because the values
2142 are BFD_RELOC_UNUSED + operand number. */
2143 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
2145 /* Sort any unmatched HI16 relocs so that they immediately precede
2146 the corresponding LO16 reloc. This is called before md_apply_fix3 and
2152 struct m32r_hi_fixup
*l
;
2154 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
2156 segment_info_type
*seginfo
;
2159 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
2160 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
2162 /* Check quickly whether the next fixup happens to be a matching low. */
2163 if (l
->fixp
->fx_next
!= NULL
2164 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
2165 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
2166 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
2169 /* Look through the fixups for this segment for a matching `low'.
2170 When we find one, move the high/shigh just in front of it. We do
2171 this in two passes. In the first pass, we try to find a
2172 unique `low'. In the second pass, we permit multiple high's
2173 relocs for a single `low'. */
2174 seginfo
= seg_info (l
->seg
);
2175 for (pass
= 0; pass
< 2; pass
++)
2181 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
2183 /* Check whether this is a `low' fixup which matches l->fixp. */
2184 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
2185 && f
->fx_addsy
== l
->fixp
->fx_addsy
2186 && f
->fx_offset
== l
->fixp
->fx_offset
2189 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
2190 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
2191 || prev
->fx_addsy
!= f
->fx_addsy
2192 || prev
->fx_offset
!= f
->fx_offset
))
2196 /* Move l->fixp before f. */
2197 for (pf
= &seginfo
->fix_root
;
2199 pf
= & (*pf
)->fx_next
)
2200 assert (*pf
!= NULL
);
2202 *pf
= l
->fixp
->fx_next
;
2204 l
->fixp
->fx_next
= f
;
2206 seginfo
->fix_root
= l
->fixp
;
2208 prev
->fx_next
= l
->fixp
;
2220 && warn_unmatched_high
)
2221 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
2222 _("Unmatched high/shigh reloc"));
2227 /* See whether we need to force a relocation into the output file.
2228 This is used to force out switch and PC relative relocations when
2232 m32r_force_relocation (fix
)
2235 if (generic_force_reloc (fix
))
2241 return fix
->fx_pcrel
;
2244 /* Write a value out to the object file, using the appropriate endianness. */
2247 md_number_to_chars (buf
, val
, n
)
2252 if (target_big_endian
)
2253 number_to_chars_bigendian (buf
, val
, n
);
2255 number_to_chars_littleendian (buf
, val
, n
);
2258 /* Turn a string in input_line_pointer into a floating point constant
2259 of type TYPE, and store the appropriate bytes in *LITP. The number
2260 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2261 returned, or NULL on OK. */
2263 /* Equal to MAX_PRECISION in atof-ieee.c. */
2264 #define MAX_LITTLENUMS 6
2267 md_atof (type
, litP
, sizeP
)
2274 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2293 /* FIXME: Some targets allow other format chars for bigger sizes
2298 return _("Bad call to md_atof()");
2301 t
= atof_ieee (input_line_pointer
, type
, words
);
2303 input_line_pointer
= t
;
2304 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2306 if (target_big_endian
)
2308 for (i
= 0; i
< prec
; i
++)
2310 md_number_to_chars (litP
, (valueT
) words
[i
],
2311 sizeof (LITTLENUM_TYPE
));
2312 litP
+= sizeof (LITTLENUM_TYPE
);
2317 for (i
= prec
- 1; i
>= 0; i
--)
2319 md_number_to_chars (litP
, (valueT
) words
[i
],
2320 sizeof (LITTLENUM_TYPE
));
2321 litP
+= sizeof (LITTLENUM_TYPE
);
2329 m32r_elf_section_change_hook ()
2331 /* If we have reached the end of a section and we have just emitted a
2332 16 bit insn, then emit a nop to make sure that the section ends on
2333 a 32 bit boundary. */
2335 if (prev_insn
.insn
|| seen_relaxable_p
)
2336 (void) m32r_fill_insn (0);
2339 /* Return true if can adjust the reloc to be relative to its section
2340 (such as .data) instead of relative to some symbol. */
2343 m32r_fix_adjustable (fixP
)
2346 bfd_reloc_code_real_type reloc_type
;
2348 if ((int) fixP
->fx_r_type
>= (int) BFD_RELOC_UNUSED
)
2350 const CGEN_INSN
*insn
= NULL
;
2351 int opindex
= (int) fixP
->fx_r_type
- (int) BFD_RELOC_UNUSED
;
2352 const CGEN_OPERAND
*operand
=
2353 cgen_operand_lookup_by_num(gas_cgen_cpu_desc
, opindex
);
2354 reloc_type
= md_cgen_lookup_reloc (insn
, operand
, fixP
);
2357 reloc_type
= fixP
->fx_r_type
;
2359 if (fixP
->fx_addsy
== NULL
)
2362 /* Prevent all adjustments to global symbols. */
2363 if (S_IS_EXTERN (fixP
->fx_addsy
))
2365 if (S_IS_WEAK (fixP
->fx_addsy
))
2369 && (reloc_type
== BFD_RELOC_M32R_24
2370 || reloc_type
== BFD_RELOC_M32R_26_PCREL
2371 || reloc_type
== BFD_RELOC_M32R_HI16_SLO
2372 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
2373 || reloc_type
== BFD_RELOC_M32R_LO16
))
2376 if (reloc_type
== BFD_RELOC_M32R_GOT24
2377 || reloc_type
== BFD_RELOC_M32R_26_PLTREL
2378 || reloc_type
== BFD_RELOC_M32R_GOTPC_HI_SLO
2379 || reloc_type
== BFD_RELOC_M32R_GOTPC_HI_ULO
2380 || reloc_type
== BFD_RELOC_M32R_GOTPC_LO
2381 || reloc_type
== BFD_RELOC_M32R_GOT16_HI_SLO
2382 || reloc_type
== BFD_RELOC_M32R_GOT16_HI_ULO
2383 || reloc_type
== BFD_RELOC_M32R_GOT16_LO
)
2386 /* We need the symbol name for the VTABLE entries. */
2387 if (reloc_type
== BFD_RELOC_VTABLE_INHERIT
2388 || reloc_type
== BFD_RELOC_VTABLE_ENTRY
)
2395 m32r_elf_final_processing (void)
2398 m32r_flags
|= E_M32R_HAS_PARALLEL
;
2399 elf_elfheader (stdoutput
)->e_flags
|= m32r_flags
;
2402 /* Translate internal representation of relocation info to BFD target
2406 tc_gen_reloc (section
, fixP
)
2411 bfd_reloc_code_real_type code
;
2413 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2415 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2416 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
2417 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
2419 code
= fixP
->fx_r_type
;
2423 printf("%s",bfd_get_reloc_code_name(code
));
2427 case BFD_RELOC_M32R_26_PCREL
:
2428 code
= BFD_RELOC_M32R_26_PLTREL
;
2430 case BFD_RELOC_M32R_24
:
2431 if (fixP
->fx_addsy
!= NULL
2432 && strcmp (S_GET_NAME (fixP
->fx_addsy
), GOT_NAME
) == 0)
2433 code
= BFD_RELOC_M32R_GOTPC24
;
2435 code
= BFD_RELOC_M32R_GOT24
;
2437 case BFD_RELOC_M32R_HI16_ULO
:
2438 if (fixP
->fx_addsy
!= NULL
2439 && strcmp (S_GET_NAME (fixP
->fx_addsy
), GOT_NAME
) == 0)
2440 code
= BFD_RELOC_M32R_GOTPC_HI_ULO
;
2442 code
= BFD_RELOC_M32R_GOT16_HI_ULO
;
2444 case BFD_RELOC_M32R_HI16_SLO
:
2445 if (fixP
->fx_addsy
!= NULL
2446 && strcmp (S_GET_NAME (fixP
->fx_addsy
), GOT_NAME
) == 0)
2447 code
= BFD_RELOC_M32R_GOTPC_HI_SLO
;
2449 code
= BFD_RELOC_M32R_GOT16_HI_SLO
;
2451 case BFD_RELOC_M32R_LO16
:
2452 if (fixP
->fx_addsy
!= NULL
2453 && strcmp (S_GET_NAME (fixP
->fx_addsy
), GOT_NAME
) == 0)
2454 code
= BFD_RELOC_M32R_GOTPC_LO
;
2456 code
= BFD_RELOC_M32R_GOT16_LO
;
2462 printf(" => %s",bfd_get_reloc_code_name(code
));
2466 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2468 printf(" => %s\n",reloc
->howto
->name
);
2470 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
2472 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2473 _("internal error: can't export reloc type %d (`%s')"),
2474 fixP
->fx_r_type
, bfd_get_reloc_code_name (code
));
2478 /* Use fx_offset for these cases. */
2479 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
2480 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
)
2481 reloc
->addend
= fixP
->fx_offset
;
2483 && code
!= BFD_RELOC_M32R_26_PLTREL
)
2485 && fixP
->fx_addsy
!= NULL
2486 && (S_GET_SEGMENT(fixP
->fx_addsy
) != section
)
2487 && S_IS_DEFINED (fixP
->fx_addsy
)
2488 && ! S_IS_EXTERNAL(fixP
->fx_addsy
)
2489 && ! S_IS_WEAK(fixP
->fx_addsy
))
2490 /* Already used fx_offset in the opcode field itseld. */
2493 reloc
->addend
= fixP
->fx_addnumber
;
2498 inline static char *
2499 m32r_end_of_match (char *cont
, char *what
)
2501 int len
= strlen (what
);
2503 if (strncasecmp (cont
, what
, strlen (what
)) == 0
2504 && ! is_part_of_name (cont
[len
]))
2511 m32r_parse_name (char const *name
, expressionS
*exprP
, char *nextcharP
)
2513 char *next
= input_line_pointer
;
2519 exprP
->X_op_symbol
= NULL
;
2520 exprP
->X_md
= BFD_RELOC_UNUSED
;
2522 if (strcmp (name
, GOT_NAME
) == 0)
2525 GOT_symbol
= symbol_find_or_make (name
);
2527 exprP
->X_add_symbol
= GOT_symbol
;
2529 /* If we have an absolute symbol or a
2530 reg, then we know its value now. */
2531 segment
= S_GET_SEGMENT (exprP
->X_add_symbol
);
2532 if (segment
== absolute_section
)
2534 exprP
->X_op
= O_constant
;
2535 exprP
->X_add_number
= S_GET_VALUE (exprP
->X_add_symbol
);
2536 exprP
->X_add_symbol
= NULL
;
2538 else if (segment
== reg_section
)
2540 exprP
->X_op
= O_register
;
2541 exprP
->X_add_number
= S_GET_VALUE (exprP
->X_add_symbol
);
2542 exprP
->X_add_symbol
= NULL
;
2546 exprP
->X_op
= O_symbol
;
2547 exprP
->X_add_number
= 0;
2553 exprP
->X_add_symbol
= symbol_find_or_make (name
);
2555 if (*nextcharP
!= '@')
2557 else if ((next_end
= m32r_end_of_match (next
+ 1, "GOTOFF")))
2559 reloc_type
= BFD_RELOC_M32R_GOTOFF
;
2560 op_type
= O_PIC_reloc
;
2562 else if ((next_end
= m32r_end_of_match (next
+ 1, "GOT")))
2564 reloc_type
= BFD_RELOC_M32R_GOT24
;
2565 op_type
= O_PIC_reloc
;
2567 else if ((next_end
= m32r_end_of_match (next
+ 1, "PLT")))
2569 reloc_type
= BFD_RELOC_M32R_26_PLTREL
;
2570 op_type
= O_PIC_reloc
;
2575 *input_line_pointer
= *nextcharP
;
2576 input_line_pointer
= next_end
;
2577 *nextcharP
= *input_line_pointer
;
2578 *input_line_pointer
= '\0';
2580 exprP
->X_op
= op_type
;
2581 exprP
->X_add_number
= 0;
2582 exprP
->X_md
= reloc_type
;
2588 m32r_cgen_parse_fix_exp(int opinfo
, expressionS
*exp
)
2590 if (exp
->X_op
== O_PIC_reloc
2591 && exp
->X_md
== BFD_RELOC_M32R_26_PLTREL
)
2593 exp
->X_op
= O_symbol
;