1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
3 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d10v.h"
29 const char comment_chars
[] = ";";
30 const char line_comment_chars
[] = "#";
31 const char line_separator_chars
[] = "";
32 const char *md_shortopts
= "O";
33 const char EXP_CHARS
[] = "eE";
34 const char FLT_CHARS
[] = "dD";
38 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
39 && (X)->X_op_symbol != NULL \
40 && (X)->X_op_symbol->sy_value.X_op == O_constant \
41 && (X)->X_op_symbol->sy_value.X_add_number == AT_WORD_RIGHT_SHIFT)
42 #define AT_WORD_RIGHT_SHIFT 2
46 #define MAX_INSN_FIXUPS (5)
53 bfd_reloc_code_real_type reloc
;
56 typedef struct _fixups
59 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
63 static Fixups FixUps
[2];
64 static Fixups
*fixups
;
66 /* True if instruction swapping warnings should be inhibited. */
67 static unsigned char flag_warn_suppress_instructionswap
; /* --nowarnswap */
70 static int reg_name_search
PARAMS ((char *name
));
71 static int register_name
PARAMS ((expressionS
*expressionP
));
72 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
73 static int postfix
PARAMS ((char *p
));
74 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
75 static int get_operands
PARAMS ((expressionS exp
[]));
76 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
77 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
78 static void write_long
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
79 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
80 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
81 struct d10v_opcode
*opcode2
, unsigned long insn2
, int exec_type
, Fixups
*fx
));
82 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
83 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
84 offsetT value
, int left
, fixS
*fix
));
85 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
86 struct d10v_opcode
*opcode2
, unsigned long insn2
,
88 static symbolS
* find_symbol_matching_register
PARAMS ((expressionS
*));
90 struct option md_longopts
[] =
92 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
93 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
94 {NULL
, no_argument
, NULL
, 0}
96 size_t md_longopts_size
= sizeof(md_longopts
);
98 static void d10v_dot_word
PARAMS ((int));
100 /* The target specific pseudo-ops which we support. */
101 const pseudo_typeS md_pseudo_table
[] =
103 { "word", d10v_dot_word
, 2 },
107 /* Opcode hash table. */
108 static struct hash_control
*d10v_hash
;
110 /* reg_name_search does a binary search of the d10v_predefined_registers
111 array to see if "name" is a valid regiter name. Returns the register
112 number from the array on success, or -1 on failure. */
115 reg_name_search (name
)
118 int middle
, low
, high
;
122 high
= d10v_reg_name_cnt() - 1;
126 middle
= (low
+ high
) / 2;
127 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
133 return d10v_predefined_registers
[middle
].value
;
139 /* register_name() checks the string at input_line_pointer
140 to see if it is a valid register name */
143 register_name (expressionP
)
144 expressionS
*expressionP
;
147 char c
, *p
= input_line_pointer
;
149 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
156 /* look to see if it's in the register table */
157 reg_number
= reg_name_search (input_line_pointer
);
160 expressionP
->X_op
= O_register
;
161 /* temporarily store a pointer to the string here */
162 expressionP
->X_op_symbol
= (symbolS
*)input_line_pointer
;
163 expressionP
->X_add_number
= reg_number
;
164 input_line_pointer
= p
;
174 check_range (num
, bits
, flags
)
182 /* don't bother checking 16-bit values */
186 if (flags
& OPERAND_SHIFT
)
188 /* all special shift operands are unsigned */
189 /* and <= 16. We allow 0 for now. */
196 if (flags
& OPERAND_SIGNED
)
198 max
= (1 << (bits
- 1))-1;
199 min
= - (1 << (bits
- 1));
200 if (((long)num
> max
) || ((long)num
< min
))
205 max
= (1 << bits
) - 1;
207 if ((num
> max
) || (num
< min
))
215 md_show_usage (stream
)
218 fprintf(stream
, _("D10V options:\n\
219 -O optimize. Will do some operations in parallel.\n"));
223 md_parse_option (c
, arg
)
230 /* Optimize. Will attempt to parallelize operations */
233 case OPTION_NOWARNSWAP
:
234 flag_warn_suppress_instructionswap
= 1;
243 md_undefined_symbol (name
)
249 /* Turn a string in input_line_pointer into a floating point constant of type
250 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
251 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
254 md_atof (type
, litP
, sizeP
)
260 LITTLENUM_TYPE words
[4];
274 return _("bad call to md_atof");
277 t
= atof_ieee (input_line_pointer
, type
, words
);
279 input_line_pointer
= t
;
283 for (i
= 0; i
< prec
; i
++)
285 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
292 md_convert_frag (abfd
, sec
, fragP
)
301 md_section_align (seg
, addr
)
305 int align
= bfd_get_section_alignment (stdoutput
, seg
);
306 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
313 char *prev_name
= "";
314 struct d10v_opcode
*opcode
;
315 d10v_hash
= hash_new();
317 /* Insert unique names into hash table. The D10v instruction set
318 has many identical opcode names that have different opcodes based
319 on the operands. This hash table then provides a quick index to
320 the first opcode with a particular name in the opcode table. */
322 for (opcode
= (struct d10v_opcode
*)d10v_opcodes
; opcode
->name
; opcode
++)
324 if (strcmp (prev_name
, opcode
->name
))
326 prev_name
= (char *)opcode
->name
;
327 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
332 FixUps
[0].next
= &FixUps
[1];
333 FixUps
[1].next
= &FixUps
[0];
337 /* this function removes the postincrement or postdecrement
338 operator ( '+' or '-' ) from an expression */
340 static int postfix (p
)
343 while (*p
!= '-' && *p
!= '+')
345 if (*p
==0 || *p
=='\n' || *p
=='\r')
365 static bfd_reloc_code_real_type
367 struct d10v_operand
*op
;
374 if (op
->flags
& OPERAND_ADDR
)
377 return (BFD_RELOC_D10V_10_PCREL_R
);
379 return (BFD_RELOC_D10V_18_PCREL
);
382 return (BFD_RELOC_16
);
386 /* get_operands parses a string of operands and returns
387 an array of expressions */
393 char *p
= input_line_pointer
;
399 while (*p
== ' ' || *p
== '\t' || *p
== ',')
401 if (*p
==0 || *p
=='\n' || *p
=='\r')
407 exp
[numops
].X_op
= O_absent
;
411 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
416 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
420 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
429 /* just skip the trailing paren */
434 input_line_pointer
= p
;
436 /* check to see if it might be a register name */
437 if (!register_name (&exp
[numops
]))
439 /* parse as an expression */
440 expression (&exp
[numops
]);
443 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
445 input_line_pointer
+= 5;
446 if (exp
[numops
].X_op
== O_register
)
448 /* if it looked like a register name but was followed by
449 "@word" then it was really a symbol, so change it to
451 exp
[numops
].X_op
= O_symbol
;
452 exp
[numops
].X_add_symbol
= symbol_find_or_make ((char *)exp
[numops
].X_op_symbol
);
455 /* check for identifier@word+constant */
456 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
458 char *orig_line
= input_line_pointer
;
460 expression (&new_exp
);
461 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
464 /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */
467 memset (&new_exp
, 0, sizeof new_exp
);
468 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
469 new_exp
.X_op
= O_constant
;
470 new_exp
.X_unsigned
= 1;
471 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
472 exp
[numops
].X_op
= O_right_shift
;
475 know (AT_WORD_P (&exp
[numops
]));
478 if (exp
[numops
].X_op
== O_illegal
)
479 as_bad (_("illegal operand"));
480 else if (exp
[numops
].X_op
== O_absent
)
481 as_bad (_("missing operand"));
484 p
= input_line_pointer
;
489 case -1: /* postdecrement mode */
490 exp
[numops
].X_op
= O_absent
;
491 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
493 case 1: /* postincrement mode */
494 exp
[numops
].X_op
= O_absent
;
495 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
499 exp
[numops
].X_op
= 0;
504 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
513 shift
= d10v_operands
[op_type
].shift
;
517 bits
= d10v_operands
[op_type
].bits
;
519 /* truncate to the proper number of bits */
520 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
521 as_bad_where (fix
->fx_file
, fix
->fx_line
, _("operand out of range: %d"), value
);
523 value
&= 0x7FFFFFFF >> (31 - bits
);
524 insn
|= (value
<< shift
);
530 /* build_insn takes a pointer to the opcode entry in the opcode table
531 and the array of operand expressions and returns the instruction */
534 build_insn (opcode
, opers
, insn
)
535 struct d10v_opcode
*opcode
;
539 int i
, bits
, shift
, flags
, format
;
540 unsigned long number
;
542 /* the insn argument is only used for the DIVS kludge */
547 insn
= opcode
->opcode
;
548 format
= opcode
->format
;
551 for (i
=0;opcode
->operands
[i
];i
++)
553 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
554 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
555 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
556 number
= opers
[i
].X_add_number
;
558 if (flags
& OPERAND_REG
)
560 number
&= REGISTER_MASK
;
561 if (format
== LONG_L
)
565 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
567 /* now create a fixup */
569 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
570 as_fatal (_("too many fixups"));
572 if (AT_WORD_P (&opers
[i
]))
574 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */
575 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
576 opers
[i
].X_op
= O_symbol
;
577 opers
[i
].X_op_symbol
= NULL
; /* Should free it */
578 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
579 that, it is aligned with the symbol's value. Later,
580 BFD_RELOC_D10V_18 will right shift (symbol_value +
582 number
<<= AT_WORD_RIGHT_SHIFT
;
583 opers
[i
].X_add_number
= number
;
586 fixups
->fix
[fixups
->fc
].reloc
=
587 get_reloc((struct d10v_operand
*)&d10v_operands
[opcode
->operands
[i
]]);
589 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
590 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
591 fixups
->fix
[fixups
->fc
].size
= 2;
593 fixups
->fix
[fixups
->fc
].size
= 4;
595 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
596 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
597 fixups
->fix
[fixups
->fc
].pcrel
= (flags
& OPERAND_ADDR
) ? true : false;
601 /* truncate to the proper number of bits */
602 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
603 as_bad (_("operand out of range: %d"),number
);
604 number
&= 0x7FFFFFFF >> (31 - bits
);
605 insn
= insn
| (number
<< shift
);
608 /* kludge: for DIVS, we need to put the operands in twice */
609 /* on the second pass, format is changed to LONG_R to force */
610 /* the second set of operands to not be shifted over 15 */
611 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
==LONG_L
))
612 insn
= build_insn (opcode
, opers
, insn
);
617 /* write out a long form instruction */
619 write_long (opcode
, insn
, fx
)
620 struct d10v_opcode
*opcode
;
625 char *f
= frag_more(4);
628 number_to_chars_bigendian (f
, insn
, 4);
630 for (i
=0; i
< fx
->fc
; i
++)
632 if (fx
->fix
[i
].reloc
)
634 where
= f
- frag_now
->fr_literal
;
635 if (fx
->fix
[i
].size
== 2)
638 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
639 fx
->fix
[i
].operand
|= 4096;
641 fix_new_exp (frag_now
,
646 fx
->fix
[i
].operand
|2048);
653 /* write out a short form instruction by itself */
655 write_1_short (opcode
, insn
, fx
)
656 struct d10v_opcode
*opcode
;
660 char *f
= frag_more(4);
663 if (opcode
->exec_type
& PARONLY
)
664 as_fatal (_("Instruction must be executed in parallel with another instruction."));
666 /* the other container needs to be NOP */
667 /* according to 4.3.1: for FM=00, sub-instructions performed only
668 by IU cannot be encoded in L-container. */
669 if (opcode
->unit
== IU
)
670 insn
|= FM00
| (NOP
<< 15); /* right container */
672 insn
= FM00
| (insn
<< 15) | NOP
; /* left container */
674 number_to_chars_bigendian (f
, insn
, 4);
675 for (i
=0; i
< fx
->fc
; i
++)
677 if (fx
->fix
[i
].reloc
)
679 where
= f
- frag_now
->fr_literal
;
680 if (fx
->fix
[i
].size
== 2)
683 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
684 fx
->fix
[i
].operand
|= 4096;
686 /* if it's an R reloc, we may have to switch it to L */
687 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (opcode
->unit
!= IU
) )
688 fx
->fix
[i
].operand
|= 1024;
690 fix_new_exp (frag_now
,
695 fx
->fix
[i
].operand
|2048);
701 /* write out a short form instruction if possible */
702 /* return number of instructions not written out */
704 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
705 struct d10v_opcode
*opcode1
, *opcode2
;
706 unsigned long insn1
, insn2
;
714 if ( (exec_type
!= 1) && ((opcode1
->exec_type
& PARONLY
)
715 || (opcode2
->exec_type
& PARONLY
)))
716 as_fatal (_("Instruction must be executed in parallel"));
718 if ( (opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
719 as_fatal (_("Long instructions may not be combined."));
721 if(opcode1
->exec_type
& BRANCH_LINK
&& exec_type
== 0)
723 /* Instructions paired with a subroutine call are executed before the
724 subroutine, so don't do these pairings unless explicitly requested. */
725 write_1_short (opcode1
, insn1
, fx
->next
);
731 case 0: /* order not specified */
732 if ( Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
735 if (opcode1
->unit
== IU
)
736 insn
= FM00
| (insn2
<< 15) | insn1
;
737 else if (opcode2
->unit
== MU
)
738 insn
= FM00
| (insn2
<< 15) | insn1
;
741 insn
= FM00
| (insn1
<< 15) | insn2
;
745 else if (opcode1
->unit
== IU
)
747 /* reverse sequential */
748 insn
= FM10
| (insn2
<< 15) | insn1
;
753 insn
= FM01
| (insn1
<< 15) | insn2
;
757 case 1: /* parallel */
758 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
759 as_fatal (_("One of these instructions may not be executed in parallel."));
761 if (opcode1
->unit
== IU
)
763 if (opcode2
->unit
== IU
)
764 as_fatal (_("Two IU instructions may not be executed in parallel"));
765 if (!flag_warn_suppress_instructionswap
)
766 as_warn (_("Swapping instruction order"));
767 insn
= FM00
| (insn2
<< 15) | insn1
;
769 else if (opcode2
->unit
== MU
)
771 if (opcode1
->unit
== MU
)
772 as_fatal (_("Two MU instructions may not be executed in parallel"));
773 if (!flag_warn_suppress_instructionswap
)
774 as_warn (_("Swapping instruction order"));
775 insn
= FM00
| (insn2
<< 15) | insn1
;
779 insn
= FM00
| (insn1
<< 15) | insn2
;
783 case 2: /* sequential */
784 if (opcode1
->unit
!= IU
)
785 insn
= FM01
| (insn1
<< 15) | insn2
;
786 else if (opcode2
->unit
== MU
|| opcode2
->unit
== EITHER
)
788 if (!flag_warn_suppress_instructionswap
)
789 as_warn (_("Swapping instruction order"));
790 insn
= FM10
| (insn2
<< 15) | insn1
;
793 as_fatal (_("IU instruction may not be in the left container"));
796 case 3: /* reverse sequential */
797 if (opcode2
->unit
!= MU
)
798 insn
= FM10
| (insn1
<< 15) | insn2
;
799 else if (opcode1
->unit
== IU
|| opcode1
->unit
== EITHER
)
801 if (!flag_warn_suppress_instructionswap
)
802 as_warn (_("Swapping instruction order"));
803 insn
= FM01
| (insn2
<< 15) | insn1
;
806 as_fatal (_("MU instruction may not be in the right container"));
810 as_fatal (_("unknown execution type passed to write_2_short()"));
814 number_to_chars_bigendian (f
, insn
, 4);
818 for (i
=0; i
< fx
->fc
; i
++)
820 if (fx
->fix
[i
].reloc
)
822 where
= f
- frag_now
->fr_literal
;
823 if (fx
->fix
[i
].size
== 2)
826 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0) )
827 fx
->fix
[i
].operand
|= 1024;
829 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
830 fx
->fix
[i
].operand
|= 4096;
832 fix_new_exp (frag_now
,
837 fx
->fix
[i
].operand
|2048);
847 /* Check 2 instructions and determine if they can be safely */
848 /* executed in parallel. Returns 1 if they can be. */
850 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
851 struct d10v_opcode
*op1
, *op2
;
852 unsigned long insn1
, insn2
;
855 int i
, j
, flags
, mask
, shift
, regno
;
856 unsigned long ins
, mod
[2], used
[2];
857 struct d10v_opcode
*op
;
859 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
860 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
861 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
862 || (op1
->unit
== IU
&& op2
->unit
== IU
)
863 || (op1
->unit
== MU
&& op2
->unit
== MU
))
866 /* If the first instruction is a branch and this is auto parallazation,
867 don't combine with any second instruction. */
868 if (exec_type
== 0 && (op1
->exec_type
& BRANCH
) != 0)
871 /* The idea here is to create two sets of bitmasks (mod and used)
872 which indicate which registers are modified or used by each
873 instruction. The operation can only be done in parallel if
874 instruction 1 and instruction 2 modify different registers, and
875 the first instruction does not modify registers that the second
876 is using (The second instruction can modify registers that the
877 first is using as they are only written back after the first
878 instruction has completed). Accesses to control registers, PSW,
879 and memory are treated as accesses to a single register. So if
880 both instructions write memory or if the first instruction writes
881 memory and the second reads, then they cannot be done in
882 parallel. Likewise, if the first instruction mucks with the psw
883 and the second reads the PSW (which includes C, F0, and F1), then
884 they cannot operate safely in parallel. */
886 /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
889 /* cr (not psw) 18 */
905 mod
[j
] = used
[j
] = 0;
906 if (op
->exec_type
& BRANCH_LINK
)
909 for (i
= 0; op
->operands
[i
]; i
++)
911 flags
= d10v_operands
[op
->operands
[i
]].flags
;
912 shift
= d10v_operands
[op
->operands
[i
]].shift
;
913 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
914 if (flags
& OPERAND_REG
)
916 regno
= (ins
>> shift
) & mask
;
917 if (flags
& (OPERAND_ACC0
|OPERAND_ACC1
))
919 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc */
926 else if (flags
& (OPERAND_FFLAG
|OPERAND_CFLAG
))
929 if ( flags
& OPERAND_DEST
)
931 mod
[j
] |= 1 << regno
;
932 if (flags
& OPERAND_EVEN
)
933 mod
[j
] |= 1 << (regno
+ 1);
937 used
[j
] |= 1 << regno
;
938 if (flags
& OPERAND_EVEN
)
939 used
[j
] |= 1 << (regno
+ 1);
941 /* Auto inc/dec also modifies the register. */
942 if (op
->operands
[i
+1] != 0
943 && (d10v_operands
[op
->operands
[i
+1]].flags
944 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
945 mod
[j
] |= 1 << regno
;
948 else if (flags
& OPERAND_ATMINUS
)
950 /* SP implicitly used/modified */
955 if (op
->exec_type
& RMEM
)
957 else if (op
->exec_type
& WMEM
)
959 else if (op
->exec_type
& RF0
)
961 else if (op
->exec_type
& WF0
)
963 else if (op
->exec_type
& WCAR
)
966 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
972 /* This is the main entry point for the machine-dependent assembler. str points to a
973 machine-dependent instruction. This function is supposed to emit the frags/bytes
974 it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
975 and leaves the difficult stuff to do_assemble().
978 static unsigned long prev_insn
;
979 static struct d10v_opcode
*prev_opcode
= 0;
980 static subsegT prev_subseg
;
981 static segT prev_seg
= 0;;
982 static int etype
= 0; /* saved extype. used for multiline instructions */
988 struct d10v_opcode
* opcode
;
990 int extype
= 0; /* execution type; parallel, etc */
995 /* look for the special multiple instruction separators */
996 str2
= strstr (str
, "||");
1001 str2
= strstr (str
, "->");
1006 str2
= strstr (str
, "<-");
1011 /* str2 points to the separator, if one */
1016 /* if two instructions are present and we already have one saved
1017 then first write it out */
1020 /* assemble first instruction and save it */
1021 prev_insn
= do_assemble (str
, &prev_opcode
);
1022 if (prev_insn
== -1)
1023 as_fatal (_("can't find opcode "));
1024 fixups
= fixups
->next
;
1029 insn
= do_assemble (str
, &opcode
);
1037 as_fatal (_("can't find opcode "));
1046 /* if this is a long instruction, write it and any previous short instruction */
1047 if (opcode
->format
& LONG_OPCODE
)
1050 as_fatal (_("Unable to mix instructions as specified"));
1052 write_long (opcode
, insn
, fixups
);
1057 if (prev_opcode
&& prev_seg
&& ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1060 if (prev_opcode
&& (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1062 /* no instructions saved */
1068 as_fatal (_("Unable to mix instructions as specified"));
1069 /* save off last instruction so it may be packed on next pass */
1070 prev_opcode
= opcode
;
1073 prev_subseg
= now_subseg
;
1074 fixups
= fixups
->next
;
1079 /* do_assemble assembles a single instruction and returns an opcode */
1080 /* it returns -1 (an invalid opcode) on error */
1082 static unsigned long
1083 do_assemble (str
, opcode
)
1085 struct d10v_opcode
**opcode
;
1087 unsigned char *op_start
, *save
;
1088 unsigned char *op_end
;
1091 expressionS myops
[6];
1094 /* Drop leading whitespace. */
1098 /* Find the opcode end. */
1099 for (op_start
= op_end
= (unsigned char *) (str
);
1102 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1105 name
[nlen
] = tolower (op_start
[nlen
]);
1113 /* Find the first opcode with the proper name. */
1114 *opcode
= (struct d10v_opcode
*)hash_find (d10v_hash
, name
);
1115 if (*opcode
== NULL
)
1116 as_fatal (_("unknown opcode: %s"),name
);
1118 save
= input_line_pointer
;
1119 input_line_pointer
= op_end
;
1120 *opcode
= find_opcode (*opcode
, myops
);
1123 input_line_pointer
= save
;
1125 insn
= build_insn ((*opcode
), myops
, 0);
1129 /* Find the symbol which has the same name as the register in the given expression. */
1131 find_symbol_matching_register (exp
)
1136 if (exp
->X_op
!= O_register
)
1139 /* Find the name of the register. */
1140 for (i
= d10v_reg_name_cnt (); i
--;)
1141 if (d10v_predefined_registers
[i
].value
== exp
->X_add_number
)
1147 /* Now see if a symbol has been defined with the same name. */
1148 return symbol_find (d10v_predefined_registers
[i
].name
);
1152 /* find_opcode() gets a pointer to an entry in the opcode table. */
1153 /* It must look at all opcodes with the same name and use the operands */
1154 /* to choose the correct opcode. */
1156 static struct d10v_opcode
*
1157 find_opcode (opcode
, myops
)
1158 struct d10v_opcode
*opcode
;
1159 expressionS myops
[];
1162 struct d10v_opcode
*next_opcode
;
1164 /* get all the operands and save them as expressions */
1165 get_operands (myops
);
1167 /* now see if the operand is a fake. If so, find the correct size */
1168 /* instruction, if possible */
1169 if (opcode
->format
== OPCODE_FAKE
)
1171 int opnum
= opcode
->operands
[0];
1174 if (myops
[opnum
].X_op
== O_register
)
1176 myops
[opnum
].X_op
= O_symbol
;
1177 myops
[opnum
].X_add_symbol
= symbol_find_or_make ((char *)myops
[opnum
].X_op_symbol
);
1178 myops
[opnum
].X_add_number
= 0;
1179 myops
[opnum
].X_op_symbol
= NULL
;
1182 next_opcode
=opcode
+1;
1184 /* If the first operand is supposed to be a register, make sure
1185 we got a valid one. */
1186 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1187 if (flags
& OPERAND_REG
)
1189 int X_op
= myops
[0].X_op
;
1190 int num
= myops
[0].X_add_number
;
1192 if (X_op
!= O_register
1194 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1195 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
)))
1197 as_bad (_("bad opcode or operands"));
1202 if (myops
[opnum
].X_op
== O_constant
|| (myops
[opnum
].X_op
== O_symbol
&&
1203 S_IS_DEFINED(myops
[opnum
].X_add_symbol
) &&
1204 (S_GET_SEGMENT(myops
[opnum
].X_add_symbol
) == now_seg
)))
1206 for (i
=0; opcode
->operands
[i
+1]; i
++)
1208 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1209 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1210 if (flags
& OPERAND_ADDR
)
1212 if (myops
[opnum
].X_op
== O_constant
)
1214 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1221 /* calculate the current address by running through the previous frags */
1222 /* and adding our current offset */
1223 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1224 value
+= f
->fr_fix
+ f
->fr_offset
;
1226 if (flags
& OPERAND_ADDR
)
1227 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
) - value
-
1228 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1230 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
);
1232 if (AT_WORD_P (&myops
[opnum
]))
1237 if (!check_range (value
, bits
, flags
))
1241 else if (!check_range (value
, bits
, flags
))
1246 as_fatal (_("value out of range"));
1250 /* not a constant, so use a long instruction */
1257 /* now search the opcode table table for one with operands */
1258 /* that matches what we've got */
1262 for (i
= 0; opcode
->operands
[i
]; i
++)
1264 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1265 int X_op
= myops
[i
].X_op
;
1266 int num
= myops
[i
].X_add_number
;
1274 if (flags
& OPERAND_REG
)
1276 if ((X_op
!= O_register
)
1278 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1279 | OPERAND_FFLAG
| OPERAND_CFLAG
1280 | OPERAND_CONTROL
)))
1287 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1288 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1289 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1290 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1291 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
1297 /* Unfortunatly, for the indirect operand in instructions such as
1298 ``ldb r1, @(c,r14)'' this function can be passed X_op == O_register
1299 (because 'c' is a valid register name). However we cannot just
1300 ignore the case when X_op == O_register but flags & OPERAND_REG is
1301 null, so we check to see if a symbol of the same name as the register
1302 exists. If the symbol does exist, then the parser was unable to
1303 distinguish the two cases and we fix things here. (Ref: PR14826) */
1305 if (!(flags
& OPERAND_REG
) && (X_op
== O_register
))
1309 sym
= find_symbol_matching_register (& myops
[i
]);
1313 myops
[i
].X_op
== X_op
== O_symbol
;
1314 myops
[i
].X_add_symbol
= sym
;
1318 (_("illegal operand - register name found where none expected"));
1322 /* We're only done if the operands matched so far AND there
1323 are no more to check. */
1324 if (match
&& myops
[i
].X_op
== 0)
1329 next_opcode
= opcode
+ 1;
1331 if (next_opcode
->opcode
== 0)
1334 if (strcmp (next_opcode
->name
, opcode
->name
))
1337 opcode
= next_opcode
;
1343 as_bad (_("bad opcode or operands"));
1347 /* Check that all registers that are required to be even are. */
1348 /* Also, if any operands were marked as registers, but were really symbols */
1349 /* fix that here. */
1350 for (i
=0; opcode
->operands
[i
]; i
++)
1352 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1353 (myops
[i
].X_add_number
& 1))
1354 as_fatal (_("Register number must be EVEN"));
1355 if (myops
[i
].X_op
== O_register
)
1357 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1359 myops
[i
].X_op
= O_symbol
;
1360 myops
[i
].X_add_symbol
= symbol_find_or_make ((char *)myops
[i
].X_op_symbol
);
1361 myops
[i
].X_add_number
= 0;
1362 myops
[i
].X_op_symbol
= NULL
;
1369 /* if while processing a fixup, a reloc really needs to be created */
1370 /* then it is done here */
1373 tc_gen_reloc (seg
, fixp
)
1378 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1379 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1380 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1381 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1382 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1384 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1385 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1389 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1390 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1391 reloc
->address
= fixp
->fx_offset
;
1393 reloc
->addend
= fixp
->fx_addnumber
;
1399 md_estimate_size_before_relax (fragp
, seg
)
1408 md_pcrel_from_section (fixp
, sec
)
1412 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1413 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1415 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1419 md_apply_fix3 (fixp
, valuep
, seg
)
1430 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1435 else if (fixp
->fx_pcrel
)
1439 value
= fixp
->fx_offset
;
1440 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1442 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1443 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1446 /* We don't actually support subtracting a symbol. */
1447 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1448 _("expression too complex"));
1453 op_type
= fixp
->fx_r_type
;
1460 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1463 else if (op_type
& 4096)
1466 fixp
->fx_r_type
= BFD_RELOC_D10V_18
;
1469 fixp
->fx_r_type
= get_reloc((struct d10v_operand
*)&d10v_operands
[op_type
]);
1472 /* Fetch the instruction, insert the fully resolved operand
1473 value, and stuff the instruction back again. */
1474 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1475 insn
= bfd_getb32 ((unsigned char *) where
);
1477 switch (fixp
->fx_r_type
)
1479 case BFD_RELOC_D10V_10_PCREL_L
:
1480 case BFD_RELOC_D10V_10_PCREL_R
:
1481 case BFD_RELOC_D10V_18_PCREL
:
1482 case BFD_RELOC_D10V_18
:
1483 /* instruction addresses are always right-shifted by 2 */
1484 value
>>= AT_WORD_RIGHT_SHIFT
;
1485 if (fixp
->fx_size
== 2)
1486 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1489 struct d10v_opcode
*rep
, *repi
;
1491 rep
= (struct d10v_opcode
*) hash_find (d10v_hash
, "rep");
1492 repi
= (struct d10v_opcode
*) hash_find (d10v_hash
, "repi");
1493 if ((insn
& FM11
) == FM11
1494 && (repi
!= NULL
&& (insn
& repi
->mask
) == repi
->opcode
1495 || rep
!= NULL
&& (insn
& rep
->mask
) == rep
->opcode
)
1498 (_("line %d: rep or repi must include at least 4 instructions"),
1500 insn
= d10v_insert_operand (insn
, op_type
, (offsetT
)value
, left
, fixp
);
1501 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1505 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1508 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1511 case BFD_RELOC_VTABLE_INHERIT
:
1512 case BFD_RELOC_VTABLE_ENTRY
:
1517 as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp
->fx_line
,fixp
->fx_r_type
);
1522 /* d10v_cleanup() is called after the assembler has finished parsing the input
1523 file or after a label is defined. Because the D10V assembler sometimes saves short
1524 instructions to see if it can package them with the next instruction, there may
1525 be a short instruction that still needs written. */
1532 if (prev_opcode
&& etype
== 0)
1535 subseg
= now_subseg
;
1537 subseg_set (prev_seg
, prev_subseg
);
1538 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1539 subseg_set (seg
, subseg
);
1545 /* Like normal .word, except support @word */
1546 /* clobbers input_line_pointer, checks end-of-line. */
1548 d10v_dot_word (nbytes
)
1549 register int nbytes
; /* 1=.byte, 2=.word, 4=.long */
1552 bfd_reloc_code_real_type reloc
;
1556 if (is_it_end_of_statement ())
1558 demand_empty_rest_of_line ();
1565 if (!strncasecmp (input_line_pointer
, "@word", 5))
1567 exp
.X_add_number
= 0;
1568 input_line_pointer
+= 5;
1571 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1572 &exp
, 0, BFD_RELOC_D10V_18
);
1575 emit_expr (&exp
, 2);
1577 while (*input_line_pointer
++ == ',');
1579 input_line_pointer
--; /* Put terminator back into stream. */
1580 demand_empty_rest_of_line ();
1584 /* Mitsubishi asked that we support some old syntax that apparently */
1585 /* had immediate operands starting with '#'. This is in some of their */
1586 /* sample code but is not documented (although it appears in some */
1587 /* examples in their assembler manual). For now, we'll solve this */
1588 /* compatibility problem by simply ignoring any '#' at the beginning */
1589 /* of an operand. */
1591 /* operands that begin with '#' should fall through to here */
1595 md_operand (expressionP
)
1596 expressionS
*expressionP
;
1598 if (*input_line_pointer
== '#')
1600 input_line_pointer
++;
1601 expression (expressionP
);
1606 d10v_fix_adjustable (fixP
)
1610 if (fixP
->fx_addsy
== NULL
)
1613 /* Prevent all adjustments to global symbols. */
1614 if (S_IS_EXTERN (fixP
->fx_addsy
))
1616 if (S_IS_WEAK (fixP
->fx_addsy
))
1619 /* We need the symbol name for the VTABLE entries */
1620 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1621 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1628 d10v_force_relocation (fixp
)
1631 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1632 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)