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(coff_link_hash_entry): Only define for non WINCE targets.
[binutils.git] / opcodes / or32-opc.c
blobdd4df6c913623f550c9d10231f622d568aeeef98
1 /* Table of opcodes for the OpenRISC 1000 ISA.
2 Copyright 2002, 2004 Free Software Foundation, Inc.
3 Contributed by Damjan Lampret (lampret@opencores.org).
4
5 This file is part of gen_or1k_isa, or1k, GDB and GAS.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21 /* We treat all letters the same in encode/decode routines so
22 we need to assign some characteristics to them like signess etc. */
23 #include <string.h>
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include "safe-ctype.h"
27 #include "ansidecl.h"
28 #ifdef HAVE_CONFIG_H
29 # include "config.h"
30 #endif
31 #include "opcode/or32.h"
32
33 static unsigned long insn_extract PARAMS ((char, char *));
34 static unsigned long * cover_insn PARAMS ((unsigned long *, int, unsigned int));
35 static int num_ones PARAMS ((unsigned long));
36 static struct insn_op_struct * parse_params PARAMS ((const struct or32_opcode *, struct insn_op_struct *));
37 static unsigned long or32_extract PARAMS ((char, char *, unsigned long));
38 static void or32_print_register PARAMS ((char, char *, unsigned long));
39 static void or32_print_immediate PARAMS ((char, char *, unsigned long));
40 static unsigned long extend_imm PARAMS ((unsigned long, char));
41
42 const struct or32_letter or32_letters[] =
43 {
44 { 'A', NUM_UNSIGNED },
45 { 'B', NUM_UNSIGNED },
46 { 'D', NUM_UNSIGNED },
47 { 'I', NUM_SIGNED },
48 { 'K', NUM_UNSIGNED },
49 { 'L', NUM_UNSIGNED },
50 { 'N', NUM_SIGNED },
51 { '0', NUM_UNSIGNED },
52 { '\0', 0 } /* Dummy entry. */
53 };
54
55 /* Opcode encoding:
56 machine[31:30]: first two bits of opcode
57 00 - neither of source operands is GPR
58 01 - second source operand is GPR (rB)
59 10 - first source operand is GPR (rA)
60 11 - both source operands are GPRs (rA and rB)
61 machine[29:26]: next four bits of opcode
62 machine[25:00]: instruction operands (specific to individual instruction)
63
64 Recommendation: irrelevant instruction bits should be set with a value of
65 bits in same positions of instruction preceding current instruction in the
66 code (when assembling). */
67
68 #define EFN &l_none
69
70 #ifdef HAS_EXECUTION
71 #define EF(func) &(func)
72 #define EFI &l_invalid
73 #else /* HAS_EXECUTION */
74 #define EF(func) EFN
75 #define EFI EFN
76 #endif /* HAS_EXECUTION */
77
78 const struct or32_opcode or32_opcodes[] =
79 {
80 { "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY },
81 { "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY },
82 { "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG},
83 { "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG },
84 { "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 },
85 { "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/
86 { "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/
87
88 { "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 },
89 { "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */
90 { "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 },
91 { "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 },
92 { "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 },
93 { "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY },
94
95 { "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
96 { "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
97 { "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
98 { "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
99 { "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
100 { "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
101 { "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
102 { "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
103 { "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
104 { "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
105 { "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
106 { "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
107 { "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 },
108 { "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 },
109 { "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 },
110 { "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 },
111 { "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 },
112 { "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 },
113 { "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 },
114 { "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 },
115 { "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 },
116 { "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 },
117 { "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 },
118 { "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 },
119 { "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 },
120 { "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 },
121 { "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 },
122 { "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 },
123 { "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 },
124 { "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 },
125 { "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 },
126 { "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 },
127 { "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 },
128 { "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 },
129 { "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 },
130 { "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 },
131 { "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 },
132 { "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 },
133 { "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 },
134 { "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 },
135 { "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 },
136 { "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 },
137 { "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 },
138 { "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 },
139 { "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 },
140 { "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 },
141 { "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 },
142 { "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 },
143 { "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 },
144 { "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 },
145 { "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 },
146 { "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 },
147 { "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 },
148 { "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 },
149 { "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 },
150 { "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 },
151 { "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 },
152 { "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 },
153 { "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 },
154 { "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 },
155 { "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 },
156 { "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 },
157 { "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 },
158 { "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 },
159 { "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 },
160 { "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 },
161 { "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 },
162 { "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 },
163 { "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 },
164 { "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 },
165 { "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 },
166 { "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 },
167 { "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 },
168 { "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 },
169 { "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 },
170 { "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 },
171 { "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 },
172 { "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 },
173 { "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 },
174 { "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 },
175 { "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 },
176 { "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 },
177 { "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 },
178 { "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 },
179 { "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 },
180 { "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 },
181 { "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 },
182 { "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 },
183 { "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 },
184 { "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 },
185 { "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 },
186
187 { "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
188 { "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
189 { "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
190 { "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
191 { "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
192 { "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
193 { "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
194 { "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
195 { "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
196 { "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
197 { "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
198 { "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
199 { "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
200 { "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
201 { "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 },
202
203 { "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
204 { "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
205 { "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
206 { "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
207 { "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
208 { "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
209 { "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
210 { "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
211 { "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
212 { "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
213 { "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
214 { "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
215 { "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
216 { "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
217 { "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 },
218
219 { "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 },
220 { "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 },
221 { "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
222 { "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
223
224 { "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY },
225 { "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY },
226 { "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 },
227 { "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 },
228 { "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 },
229 { "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 },
230 { "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 },
231
232 { "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
233 { "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 },
234 { "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
235 { "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 },
236 { "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 },
237 { "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 },
238 { "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 },
239
240 { "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 },
241 { "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
242 { "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 },
243 { "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 },
244 { "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 },
245 { "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
246 { "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 },
247 { "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 },
248 { "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 },
249 { "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 },
250 { "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 },
251
252 { "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG },
253 { "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG },
254 { "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG },
255 { "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG },
256 { "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG },
257 { "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG },
258 { "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG },
259 { "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG },
260 { "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG },
261 { "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG },
262
263 { "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 },
264 { "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/
265 { "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/
266
267 { "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 },
268 { "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 },
269 { "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 },
270 { "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 },
271
272 { "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 },
273 { "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 },
274 { "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 },
275 { "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 },
276 { "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 },
277 { "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 },
278 { "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 },
279
280 { "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 },
281 { "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 },
282 { "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 },
283 { "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 },
284 { "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 },
285 { "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 },
286 { "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 },
287 { "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 },
288 { "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 },
289 { "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 },
290 { "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 },
291 { "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 },
292 { "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 },
293 { "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 },
294 { "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 },
295
296 { "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG },
297 { "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG },
298 { "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG },
299 { "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG },
300 { "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG },
301 { "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG },
302 { "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG },
303 { "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG },
304 { "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG },
305 { "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG },
306
307 { "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 },
308 { "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 },
309 { "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 },
310 { "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 },
311
312 /* This section should not be defined in or1ksim, since it contains duplicates,
313 which would cause machine builder to complain. */
314 #ifdef HAS_CUST
315 { "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 },
316 { "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
317 { "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
318
319 { "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 },
320 { "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
321 { "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
322
323 { "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 },
324 { "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
325 { "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
326
327 { "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 },
328 { "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
329 { "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
330 #endif
331
332 /* Dummy entry, not included in num_opcodes. This
333 lets code examine entry i+1 without checking
334 if we've run off the end of the table. */
335 { "", "", "", EFI, 0 }
336 };
337
338 #undef EFI
339 #undef EFN
340 #undef EF
341
342 /* Define dummy, if debug is not defined. */
343
344 #if !defined HAS_DEBUG
345 static void debug PARAMS ((int, const char *, ...));
346
347 static void
348 debug (int level ATTRIBUTE_UNUSED, const char *format ATTRIBUTE_UNUSED, ...)
349 {
350 }
351 #endif
352
353 const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1;
354
355 /* Calculates instruction length in bytes. Always 4 for OR32. */
356
357 int
358 insn_len (insn_index)
359 int insn_index ATTRIBUTE_UNUSED;
360 {
361 return 4;
362 }
363
364 /* Is individual insn's operand signed or unsigned? */
365
366 int
367 letter_signed (l)
368 char l;
369 {
370 const struct or32_letter *pletter;
371
372 for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
373 if (pletter->letter == l)
374 return pletter->sign;
375
376 printf ("letter_signed(%c): Unknown letter.\n", l);
377 return 0;
378 }
379
380 /* Number of letters in the individual lettered operand. */
381
382 int
383 letter_range (l)
384 char l;
385 {
386 const struct or32_opcode *pinsn;
387 char *enc;
388 int range = 0;
389
390 for (pinsn = or32_opcodes; strlen(pinsn->name); pinsn++)
391 {
392 if (strchr (pinsn->encoding,l))
393 {
394 for (enc = pinsn->encoding; *enc != '\0'; enc++)
395 if ((*enc == '0') && (*(enc+1) == 'x'))
396 enc += 2;
397 else if (*enc == l)
398 range++;
399 return range;
400 }
401 }
402
403 printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
404 exit (1);
405 }
406
407 /* MM: Returns index of given instruction name. */
408
409 int
410 insn_index (char *insn)
411 {
412 unsigned int i;
413 int found = -1;
414
415 for (i = 0; i < or32_num_opcodes; i++)
416 if (!strcmp (or32_opcodes[i].name, insn))
417 {
418 found = i;
419 break;
420 }
421 return found;
422 }
423
424 const char *
425 insn_name (index)
426 int index;
427 {
428 if (index >= 0 && index < (int) or32_num_opcodes)
429 return or32_opcodes[index].name;
430 else
431 return "???";
432 }
433
434 void
435 l_none ()
436 {
437 }
438
439 /* Finite automata for instruction decoding building code. */
440
441 /* Find simbols in encoding. */
442 static unsigned long
443 insn_extract (param_ch, enc_initial)
444 char param_ch;
445 char *enc_initial;
446 {
447 char *enc;
448 unsigned long ret = 0;
449 unsigned opc_pos = 32;
450
451 for (enc = enc_initial; *enc != '\0'; )
452 if ((*enc == '0') && (*(enc + 1) == 'x'))
453 {
454 unsigned long tmp = strtol (enc+2, NULL, 16);
455
456 opc_pos -= 4;
457 if (param_ch == '0' || param_ch == '1')
458 {
459 if (param_ch == '0')
460 tmp = 15 - tmp;
461 ret |= tmp << opc_pos;
462 }
463 enc += 3;
464 }
465 else
466 {
467 if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc))
468 {
469 opc_pos--;
470 if (param_ch == *enc)
471 ret |= 1 << opc_pos;
472 }
473 enc++;
474 }
475 return ret;
476 }
477
478 #define MAX_AUTOMATA_SIZE (1200)
479 #define MAX_OP_TABLE_SIZE (1200)
480 #define LEAF_FLAG (0x80000000)
481 #define MAX_LEN (8)
482
483 #ifndef MIN
484 # define MIN(x,y) ((x) < (y) ? (x) : (y))
485 #endif
486
487 unsigned long *automata;
488 int nuncovered;
489 int curpass = 0;
490
491 /* MM: Struct that hold runtime build information about instructions. */
492 struct temp_insn_struct
493 {
494 unsigned long insn;
495 unsigned long insn_mask;
496 int in_pass;
497 } *ti;
498
499 struct insn_op_struct *op_data, **op_start;
500
501 /* Recursive utility function used to find best match and to build automata. */
502
503 static unsigned long *
504 cover_insn (cur, pass, mask)
505 unsigned long * cur;
506 int pass;
507 unsigned int mask;
508 {
509 int best_first = 0, last_match = -1, ninstr = 0;
510 unsigned int best_len = 0;
511 unsigned int i;
512 unsigned long cur_mask = mask;
513 unsigned long *next;
514
515 for (i = 0; i < or32_num_opcodes; i++)
516 if (ti[i].in_pass == pass)
517 {
518 cur_mask &= ti[i].insn_mask;
519 ninstr++;
520 last_match = i;
521 }
522
523 debug (8, "%08X %08X\n", mask, cur_mask);
524
525 if (ninstr == 0)
526 return 0;
527
528 if (ninstr == 1)
529 {
530 /* Leaf holds instruction index. */
531 debug (8, "%i>I%i %s\n",
532 cur - automata, last_match, or32_opcodes[last_match].name);
533
534 *cur = LEAF_FLAG | last_match;
535 cur++;
536 nuncovered--;
537 }
538 else
539 {
540 /* Find longest match. */
541 for (i = 0; i < 32; i++)
542 {
543 unsigned int len;
544
545 for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
546 {
547 unsigned long m = (1UL << ((unsigned long)len)) - 1;
548
549 debug (9, " (%i(%08X & %08X>>%i = %08X, %08X)",
550 len,m, cur_mask, i, (cur_mask >> (unsigned)i),
551 (cur_mask >> (unsigned)i) & m);
552
553 if ((m & (cur_mask >> (unsigned)i)) == m)
554 {
555 best_len = len;
556 best_first = i;
557 debug (9, "!");
558 }
559 else
560 break;
561 }
562 }
563
564 debug (9, "\n");
565
566 if (!best_len)
567 {
568 fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
569
570 for (i = 0; i < or32_num_opcodes; i++)
571 if (ti[i].in_pass == pass)
572 fprintf (stderr, "%s ", or32_opcodes[i].name);
573
574 fprintf (stderr, "\n");
575 exit (1);
576 }
577
578 debug (8, "%i> #### %i << %i (%i) ####\n",
579 cur - automata, best_len, best_first, ninstr);
580
581 *cur = best_first;
582 cur++;
583 *cur = (1 << best_len) - 1;
584 cur++;
585 next = cur;
586
587 /* Allocate space for pointers. */
588 cur += 1 << best_len;
589 cur_mask = (1 << (unsigned long)best_len) - 1;
590
591 for (i = 0; i < ((unsigned) 1 << best_len); i++)
592 {
593 unsigned int j;
594 unsigned long *c;
595
596 curpass++;
597 for (j = 0; j < or32_num_opcodes; j++)
598 if (ti[j].in_pass == pass
599 && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i
600 && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
601 ti[j].in_pass = curpass;
602
603 debug (9, "%08X %08X %i\n", mask, cur_mask, best_first);
604 c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
605 if (c)
606 {
607 debug (8, "%i> #%X -> %u\n", next - automata, i, cur - automata);
608 *next = cur - automata;
609 cur = c;
610 }
611 else
612 {
613 debug (8, "%i> N/A\n", next - automata);
614 *next = 0;
615 }
616 next++;
617 }
618 }
619 return cur;
620 }
621
622 /* Returns number of nonzero bits. */
623
624 static int
625 num_ones (value)
626 unsigned long value;
627 {
628 int c = 0;
629
630 while (value)
631 {
632 if (value & 1)
633 c++;
634 value >>= 1;
635 }
636 return c;
637 }
638
639 /* Utility function, which converts parameters from or32_opcode format to more binary form.
640 Parameters are stored in ti struct. */
641
642 static struct insn_op_struct *
643 parse_params (opcode, cur)
644 const struct or32_opcode * opcode;
645 struct insn_op_struct * cur;
646 {
647 char *args = opcode->args;
648 int i, type;
649
650 i = 0;
651 type = 0;
652 /* In case we don't have any parameters, we add dummy read from r0. */
653
654 if (!(*args))
655 {
656 cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
657 cur->data = 0;
658 debug (9, "#%08X %08X\n", cur->type, cur->data);
659 cur++;
660 return cur;
661 }
662
663 while (*args != '\0')
664 {
665 if (*args == 'r')
666 {
667 args++;
668 type |= OPTYPE_REG;
669 }
670 else if (ISALPHA (*args))
671 {
672 unsigned long arg;
673
674 arg = insn_extract (*args, opcode->encoding);
675 debug (9, "%s : %08X ------\n", opcode->name, arg);
676 if (letter_signed (*args))
677 {
678 type |= OPTYPE_SIG;
679 type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
680 }
681
682 /* Split argument to sequences of consecutive ones. */
683 while (arg)
684 {
685 int shr = 0;
686 unsigned long tmp = arg, mask = 0;
687
688 while ((tmp & 1) == 0)
689 {
690 shr++;
691 tmp >>= 1;
692 }
693 while (tmp & 1)
694 {
695 mask++;
696 tmp >>= 1;
697 }
698 cur->type = type | shr;
699 cur->data = mask;
700 arg &= ~(((1 << mask) - 1) << shr);
701 debug (6, "|%08X %08X\n", cur->type, cur->data);
702 cur++;
703 }
704 args++;
705 }
706 else if (*args == '(')
707 {
708 /* Next param is displacement. Later we will treat them as one operand. */
709 cur--;
710 cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
711 debug (9, ">%08X %08X\n", cur->type, cur->data);
712 cur++;
713 type = 0;
714 i++;
715 args++;
716 }
717 else if (*args == OPERAND_DELIM)
718 {
719 cur--;
720 cur->type = type | cur->type | OPTYPE_OP;
721 debug (9, ">%08X %08X\n", cur->type, cur->data);
722 cur++;
723 type = 0;
724 i++;
725 args++;
726 }
727 else if (*args == '0')
728 {
729 cur->type = type;
730 cur->data = 0;
731 debug (9, ">%08X %08X\n", cur->type, cur->data);
732 cur++;
733 type = 0;
734 i++;
735 args++;
736 }
737 else if (*args == ')')
738 args++;
739 else
740 {
741 fprintf (stderr, "%s : parse error in args.\n", opcode->name);
742 exit (1);
743 }
744 }
745
746 cur--;
747 cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
748 debug (9, "#%08X %08X\n", cur->type, cur->data);
749 cur++;
750
751 return cur;
752 }
753
754 /* Constructs new automata based on or32_opcodes array. */
755
756 void
757 build_automata ()
758 {
759 unsigned int i;
760 unsigned long *end;
761 struct insn_op_struct *cur;
762
763 automata = (unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
764 ti = (struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
765
766 nuncovered = or32_num_opcodes;
767 printf ("Building automata... ");
768 /* Build temporary information about instructions. */
769 for (i = 0; i < or32_num_opcodes; i++)
770 {
771 unsigned long ones, zeros;
772 char *encoding = or32_opcodes[i].encoding;
773
774 ones = insn_extract('1', encoding);
775 zeros = insn_extract('0', encoding);
776
777 ti[i].insn_mask = ones | zeros;
778 ti[i].insn = ones;
779 ti[i].in_pass = curpass = 0;
780
781 /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
782 or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
783 }
784
785 /* Until all are covered search for best criteria to separate them. */
786 end = cover_insn (automata, curpass, 0xFFFFFFFF);
787
788 if (end - automata > MAX_AUTOMATA_SIZE)
789 {
790 fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
791 exit (1);
792 }
793
794 printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes);
795 printf ("Parsing operands data... ");
796
797 op_data = (struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
798 op_start = (struct insn_op_struct **) malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
799 cur = op_data;
800
801 for (i = 0; i < or32_num_opcodes; i++)
802 {
803 op_start[i] = cur;
804 cur = parse_params (&or32_opcodes[i], cur);
805
806 if (cur - op_data > MAX_OP_TABLE_SIZE)
807 {
808 fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
809 exit (1);
810 }
811 }
812 printf ("done.\n");
813 }
814
815 void
816 destruct_automata ()
817 {
818 free (ti);
819 free (automata);
820 free (op_data);
821 free (op_start);
822 }
823
824 /* Decodes instruction and returns instruction index. */
825
826 int
827 insn_decode (insn)
828 unsigned int insn;
829 {
830 unsigned long *a = automata;
831 int i;
832
833 while (!(*a & LEAF_FLAG))
834 {
835 unsigned int first = *a;
836
837 debug (9, "%i ", a - automata);
838
839 a++;
840 i = (insn >> first) & *a;
841 a++;
842 if (!*(a + i))
843 {
844 /* Invalid instruction found? */
845 debug (9, "XXX\n", i);
846 return -1;
847 }
848 a = automata + *(a + i);
849 }
850
851 i = *a & ~LEAF_FLAG;
852
853 debug (9, "%i\n", i);
854
855 /* Final check - do we have direct match?
856 (based on or32_opcodes this should be the only possibility,
857 but in case of invalid/missing instruction we must perform a check) */
858 if ((ti[i].insn_mask & insn) == ti[i].insn)
859 return i;
860 else
861 return -1;
862 }
863
864 static char disassembled_str[50];
865 char *disassembled = &disassembled_str[0];
866
867 /* Automagically does zero- or sign- extension and also finds correct
868 sign bit position if sign extension is correct extension. Which extension
869 is proper is figured out from letter description. */
870
871 static unsigned long
872 extend_imm (imm, l)
873 unsigned long imm;
874 char l;
875 {
876 unsigned long mask;
877 int letter_bits;
878
879 /* First truncate all bits above valid range for this letter
880 in case it is zero extend. */
881 letter_bits = letter_range (l);
882 mask = (1 << letter_bits) - 1;
883 imm &= mask;
884
885 /* Do sign extend if this is the right one. */
886 if (letter_signed(l) && (imm >> (letter_bits - 1)))
887 imm |= (~mask);
888
889 return imm;
890 }
891
892 static unsigned long
893 or32_extract (param_ch, enc_initial, insn)
894 char param_ch;
895 char *enc_initial;
896 unsigned long insn;
897 {
898 char *enc;
899 unsigned long ret = 0;
900 int opc_pos = 0;
901 int param_pos = 0;
902
903 for (enc = enc_initial; *enc != '\0'; enc++)
904 if (*enc == param_ch)
905 {
906 if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
907 continue;
908 else
909 param_pos++;
910 }
911
912 #if DEBUG
913 printf ("or32_extract: %x ", param_pos);
914 #endif
915 opc_pos = 32;
916
917 for (enc = enc_initial; *enc != '\0'; )
918 if ((*enc == '0') && (*(enc + 1) == 'x'))
919 {
920 opc_pos -= 4;
921 if ((param_ch == '0') || (param_ch == '1'))
922 {
923 unsigned long tmp = strtol (enc, NULL, 16);
924 #if DEBUG
925 printf (" enc=%s, tmp=%x ", enc, tmp);
926 #endif
927 if (param_ch == '0')
928 tmp = 15 - tmp;
929 ret |= tmp << opc_pos;
930 }
931 enc += 3;
932 }
933 else if ((*enc == '0') || (*enc == '1'))
934 {
935 opc_pos--;
936 if (param_ch == *enc)
937 ret |= 1 << opc_pos;
938 enc++;
939 }
940 else if (*enc == param_ch)
941 {
942 opc_pos--;
943 param_pos--;
944 #if DEBUG
945 printf ("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos);
946 #endif
947 if (ISLOWER (param_ch))
948 ret -= ((insn >> opc_pos) & 0x1) << param_pos;
949 else
950 ret += ((insn >> opc_pos) & 0x1) << param_pos;
951 enc++;
952 }
953 else if (ISALPHA (*enc))
954 {
955 opc_pos--;
956 enc++;
957 }
958 else if (*enc == '-')
959 {
960 opc_pos--;
961 enc++;
962 }
963 else
964 enc++;
965
966 #if DEBUG
967 printf ("ret=%x\n", ret);
968 #endif
969 return ret;
970 }
971
972 /* Print register. Used only by print_insn. */
973
974 static void
975 or32_print_register (param_ch, encoding, insn)
976 char param_ch;
977 char *encoding;
978 unsigned long insn;
979 {
980 int regnum = or32_extract(param_ch, encoding, insn);
981
982 sprintf (disassembled, "%sr%d", disassembled, regnum);
983 }
984
985 /* Print immediate. Used only by print_insn. */
986
987 static void
988 or32_print_immediate (param_ch, encoding, insn)
989 char param_ch;
990 char *encoding;
991 unsigned long insn;
992 {
993 int imm = or32_extract (param_ch, encoding, insn);
994
995 imm = extend_imm (imm, param_ch);
996
997 if (letter_signed (param_ch))
998 {
999 if (imm < 0)
1000 sprintf (disassembled, "%s%d", disassembled, imm);
1001 else
1002 sprintf (disassembled, "%s0x%x", disassembled, imm);
1003 }
1004 else
1005 sprintf (disassembled, "%s%#x", disassembled, imm);
1006 }
1007
1008 /* Disassemble one instruction from insn to disassemble.
1009 Return the size of the instruction. */
1010
1011 int
1012 disassemble_insn (insn)
1013 unsigned long insn;
1014 {
1015 int index;
1016 index = insn_decode (insn);
1017
1018 if (index >= 0)
1019 {
1020 struct or32_opcode const *opcode = &or32_opcodes[index];
1021 char *s;
1022
1023 sprintf (disassembled, "%s ", opcode->name);
1024 for (s = opcode->args; *s != '\0'; ++s)
1025 {
1026 switch (*s)
1027 {
1028 case '\0':
1029 return 4;
1030
1031 case 'r':
1032 or32_print_register (*++s, opcode->encoding, insn);
1033 break;
1034
1035 default:
1036 if (strchr (opcode->encoding, *s))
1037 or32_print_immediate (*s, opcode->encoding, insn);
1038 else
1039 sprintf (disassembled, "%s%c", disassembled, *s);
1040 }
1041 }
1042 }
1043 else
1044 {
1045 /* This used to be %8x for binutils. */
1046 sprintf (disassembled, "%s.word 0x%08lx", disassembled, insn);
1047 }
1048
1049 return insn_len (insn);
1050 }
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