opcodes/fr30-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   8
   9 This file is part of the GNU Binutils and GDB, the GNU debugger.
  10
  11 This program is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 2, or (at your option)
  14 any later version.
  15
  16 This program is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with this program; if not, write to the Free Software Foundation, Inc.,
  23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  24
  25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  26    Keep that in mind.  */
  27
  28 #include "sysdep.h"
  29 #include <stdio.h>
  30 #include "ansidecl.h"
  31 #include "dis-asm.h"
  32 #include "bfd.h"
  33 #include "symcat.h"
  34 #include "fr30-desc.h"
  35 #include "fr30-opc.h"
  36 #include "opintl.h"
  37
  38 /* Default text to print if an instruction isn't recognized.  */
  39 #define UNKNOWN_INSN_MSG _("*unknown*")
  40
  41 static void print_normal
  42      PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
  43 static void print_address
  44      PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
  45 static void print_keyword
  46      PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
  47 static void print_insn_normal
  48      PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
  49               bfd_vma, int));
  50 static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
  51                                disassemble_info *, char *, int));
  52 static int default_print_insn
  53      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  54 \f
  55 /* -- disassembler routines inserted here */
  56
  57 /* -- dis.c */
  58
  59 static void
  60 print_register_list (dis_info, value, offset, load_store)
  61      PTR dis_info;
  62      long value;
  63      long offset;
  64      int load_store; /* 0 == load, 1 == store */
  65 {
  66   disassemble_info *info = dis_info;
  67   int mask;
  68   int index = 0;
  69   char* comma = "";
  70
  71   if (load_store)
  72     mask = 0x80;
  73   else
  74     mask = 1;
  75
  76   if (value & mask)
  77     {
  78       (*info->fprintf_func) (info->stream, "r%i", index + offset);
  79       comma = ",";
  80     }
  81
  82   for (index = 1; index <= 7; ++index)
  83     {
  84       if (load_store)
  85         mask >>= 1;
  86       else
  87         mask <<= 1;
  88
  89       if (value & mask)
  90         {
  91           (*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset);
  92           comma = ",";
  93         }
  94     }
  95 }
  96
  97 static void
  98 print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length)
  99      CGEN_CPU_DESC cd;
 100      PTR dis_info;
 101      long value;
 102      unsigned int attrs;
 103      bfd_vma pc;
 104      int length;
 105 {
 106   print_register_list (dis_info, value, 8, 0/*load*/);
 107 }
 108
 109 static void
 110 print_low_register_list_ld (cd, dis_info, value, attrs, pc, length)
 111      CGEN_CPU_DESC cd;
 112      PTR dis_info;
 113      long value;
 114      unsigned int attrs;
 115      bfd_vma pc;
 116      int length;
 117 {
 118   print_register_list (dis_info, value, 0, 0/*load*/);
 119 }
 120
 121 static void
 122 print_hi_register_list_st (cd, dis_info, value, attrs, pc, length)
 123      CGEN_CPU_DESC cd;
 124      PTR dis_info;
 125      long value;
 126      unsigned int attrs;
 127      bfd_vma pc;
 128      int length;
 129 {
 130   print_register_list (dis_info, value, 8, 1/*store*/);
 131 }
 132
 133 static void
 134 print_low_register_list_st (cd, dis_info, value, attrs, pc, length)
 135      CGEN_CPU_DESC cd;
 136      PTR dis_info;
 137      long value;
 138      unsigned int attrs;
 139      bfd_vma pc;
 140      int length;
 141 {
 142   print_register_list (dis_info, value, 0, 1/*store*/);
 143 }
 144
 145 static void
 146 print_m4 (cd, dis_info, value, attrs, pc, length)
 147      CGEN_CPU_DESC cd;
 148      PTR dis_info;
 149      long value;
 150      unsigned int attrs;
 151      bfd_vma pc;
 152      int length;
 153 {
 154   disassemble_info *info = (disassemble_info *) dis_info;
 155   (*info->fprintf_func) (info->stream, "%ld", value);
 156 }
 157 /* -- */
 158
 159 /* Main entry point for printing operands.
 160    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 161    of dis-asm.h on cgen.h.
 162
 163    This function is basically just a big switch statement.  Earlier versions
 164    used tables to look up the function to use, but
 165    - if the table contains both assembler and disassembler functions then
 166      the disassembler contains much of the assembler and vice-versa,
 167    - there's a lot of inlining possibilities as things grow,
 168    - using a switch statement avoids the function call overhead.
 169
 170    This function could be moved into `print_insn_normal', but keeping it
 171    separate makes clear the interface between `print_insn_normal' and each of
 172    the handlers.
 173 */
 174
 175 void
 176 fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 177      CGEN_CPU_DESC cd;
 178      int opindex;
 179      PTR xinfo;
 180      CGEN_FIELDS *fields;
 181      void const *attrs;
 182      bfd_vma pc;
 183      int length;
 184 {
 185  disassemble_info *info = (disassemble_info *) xinfo;
 186
 187   switch (opindex)
 188     {
 189     case FR30_OPERAND_CRI :
 190       print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0);
 191       break;
 192     case FR30_OPERAND_CRJ :
 193       print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0);
 194       break;
 195     case FR30_OPERAND_R13 :
 196       print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0);
 197       break;
 198     case FR30_OPERAND_R14 :
 199       print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0);
 200       break;
 201     case FR30_OPERAND_R15 :
 202       print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0);
 203       break;
 204     case FR30_OPERAND_RI :
 205       print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0);
 206       break;
 207     case FR30_OPERAND_RIC :
 208       print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0);
 209       break;
 210     case FR30_OPERAND_RJ :
 211       print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0);
 212       break;
 213     case FR30_OPERAND_RJC :
 214       print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0);
 215       break;
 216     case FR30_OPERAND_RS1 :
 217       print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0);
 218       break;
 219     case FR30_OPERAND_RS2 :
 220       print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0);
 221       break;
 222     case FR30_OPERAND_CC :
 223       print_normal (cd, info, fields->f_cc, 0, pc, length);
 224       break;
 225     case FR30_OPERAND_CCC :
 226       print_normal (cd, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 227       break;
 228     case FR30_OPERAND_DIR10 :
 229       print_normal (cd, info, fields->f_dir10, 0, pc, length);
 230       break;
 231     case FR30_OPERAND_DIR8 :
 232       print_normal (cd, info, fields->f_dir8, 0, pc, length);
 233       break;
 234     case FR30_OPERAND_DIR9 :
 235       print_normal (cd, info, fields->f_dir9, 0, pc, length);
 236       break;
 237     case FR30_OPERAND_DISP10 :
 238       print_normal (cd, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 239       break;
 240     case FR30_OPERAND_DISP8 :
 241       print_normal (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 242       break;
 243     case FR30_OPERAND_DISP9 :
 244       print_normal (cd, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 245       break;
 246     case FR30_OPERAND_I20 :
 247       print_normal (cd, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 248       break;
 249     case FR30_OPERAND_I32 :
 250       print_normal (cd, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 251       break;
 252     case FR30_OPERAND_I8 :
 253       print_normal (cd, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 254       break;
 255     case FR30_OPERAND_LABEL12 :
 256       print_address (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 257       break;
 258     case FR30_OPERAND_LABEL9 :
 259       print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 260       break;
 261     case FR30_OPERAND_M4 :
 262       print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 263       break;
 264     case FR30_OPERAND_PS :
 265       print_keyword (cd, info, & fr30_cgen_opval_h_ps, 0, 0);
 266       break;
 267     case FR30_OPERAND_REGLIST_HI_LD :
 268       print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length);
 269       break;
 270     case FR30_OPERAND_REGLIST_HI_ST :
 271       print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length);
 272       break;
 273     case FR30_OPERAND_REGLIST_LOW_LD :
 274       print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length);
 275       break;
 276     case FR30_OPERAND_REGLIST_LOW_ST :
 277       print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length);
 278       break;
 279     case FR30_OPERAND_S10 :
 280       print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 281       break;
 282     case FR30_OPERAND_U10 :
 283       print_normal (cd, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 284       break;
 285     case FR30_OPERAND_U4 :
 286       print_normal (cd, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 287       break;
 288     case FR30_OPERAND_U4C :
 289       print_normal (cd, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 290       break;
 291     case FR30_OPERAND_U8 :
 292       print_normal (cd, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 293       break;
 294     case FR30_OPERAND_UDISP6 :
 295       print_normal (cd, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 296       break;
 297
 298     default :
 299       /* xgettext:c-format */
 300       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 301                opindex);
 302     abort ();
 303   }
 304 }
 305
 306 cgen_print_fn * const fr30_cgen_print_handlers[] =
 307 {
 308   print_insn_normal,
 309 };
 310
 311
 312 void
 313 fr30_cgen_init_dis (cd)
 314      CGEN_CPU_DESC cd;
 315 {
 316   fr30_cgen_init_opcode_table (cd);
 317   fr30_cgen_init_ibld_table (cd);
 318   cd->print_handlers = & fr30_cgen_print_handlers[0];
 319   cd->print_operand = fr30_cgen_print_operand;
 320 }
 321
 322 \f
 323 /* Default print handler.  */
 324
 325 static void
 326 print_normal (cd, dis_info, value, attrs, pc, length)
 327      CGEN_CPU_DESC cd;
 328      PTR dis_info;
 329      long value;
 330      unsigned int attrs;
 331      bfd_vma pc;
 332      int length;
 333 {
 334   disassemble_info *info = (disassemble_info *) dis_info;
 335
 336 #ifdef CGEN_PRINT_NORMAL
 337   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 338 #endif
 339
 340   /* Print the operand as directed by the attributes.  */
 341   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 342     ; /* nothing to do */
 343   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 344     (*info->fprintf_func) (info->stream, "%ld", value);
 345   else
 346     (*info->fprintf_func) (info->stream, "0x%lx", value);
 347 }
 348
 349 /* Default address handler.  */
 350
 351 static void
 352 print_address (cd, dis_info, value, attrs, pc, length)
 353      CGEN_CPU_DESC cd;
 354      PTR dis_info;
 355      bfd_vma value;
 356      unsigned int attrs;
 357      bfd_vma pc;
 358      int length;
 359 {
 360   disassemble_info *info = (disassemble_info *) dis_info;
 361
 362 #ifdef CGEN_PRINT_ADDRESS
 363   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 364 #endif
 365
 366   /* Print the operand as directed by the attributes.  */
 367   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 368     ; /* nothing to do */
 369   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 370     (*info->print_address_func) (value, info);
 371   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 372     (*info->print_address_func) (value, info);
 373   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 374     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 375   else
 376     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 377 }
 378
 379 /* Keyword print handler.  */
 380
 381 static void
 382 print_keyword (cd, dis_info, keyword_table, value, attrs)
 383      CGEN_CPU_DESC cd;
 384      PTR dis_info;
 385      CGEN_KEYWORD *keyword_table;
 386      long value;
 387      unsigned int attrs;
 388 {
 389   disassemble_info *info = (disassemble_info *) dis_info;
 390   const CGEN_KEYWORD_ENTRY *ke;
 391
 392   ke = cgen_keyword_lookup_value (keyword_table, value);
 393   if (ke != NULL)
 394     (*info->fprintf_func) (info->stream, "%s", ke->name);
 395   else
 396     (*info->fprintf_func) (info->stream, "???");
 397 }
 398 \f
 399 /* Default insn printer.
 400
 401    DIS_INFO is defined as `PTR' so the disassembler needn't know anything
 402    about disassemble_info.  */
 403
 404 static void
 405 print_insn_normal (cd, dis_info, insn, fields, pc, length)
 406      CGEN_CPU_DESC cd;
 407      PTR dis_info;
 408      const CGEN_INSN *insn;
 409      CGEN_FIELDS *fields;
 410      bfd_vma pc;
 411      int length;
 412 {
 413   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 414   disassemble_info *info = (disassemble_info *) dis_info;
 415   const unsigned char *syn;
 416
 417   CGEN_INIT_PRINT (cd);
 418
 419   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 420     {
 421       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 422         {
 423           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 424           continue;
 425         }
 426       if (CGEN_SYNTAX_CHAR_P (*syn))
 427         {
 428           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 429           continue;
 430         }
 431
 432       /* We have an operand.  */
 433       fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 434                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 435     }
 436 }
 437 \f
 438 /* Utility to print an insn.
 439    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 440    The result is the size of the insn in bytes or zero for an unknown insn
 441    or -1 if an error occurs fetching data (memory_error_func will have
 442    been called).  */
 443
 444 static int
 445 print_insn (cd, pc, info, buf, buflen)
 446      CGEN_CPU_DESC cd;
 447      bfd_vma pc;
 448      disassemble_info *info;
 449      char *buf;
 450      int buflen;
 451 {
 452   unsigned long insn_value;
 453   const CGEN_INSN_LIST *insn_list;
 454   CGEN_EXTRACT_INFO ex_info;
 455
 456   ex_info.dis_info = info;
 457   ex_info.valid = (1 << (cd->base_insn_bitsize / 8)) - 1;
 458   ex_info.insn_bytes = buf;
 459
 460   switch (buflen)
 461     {
 462     case 1:
 463       insn_value = buf[0];
 464       break;
 465     case 2:
 466       insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
 467       break;
 468     case 4:
 469       insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
 470       break;
 471     default:
 472       abort ();
 473     }
 474
 475   /* The instructions are stored in hash lists.
 476      Pick the first one and keep trying until we find the right one.  */
 477
 478   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 479   while (insn_list != NULL)
 480     {
 481       const CGEN_INSN *insn = insn_list->insn;
 482       CGEN_FIELDS fields;
 483       int length;
 484
 485 #if 0 /* not needed as insn shouldn't be in hash lists if not supported */
 486       /* Supported by this cpu?  */
 487       if (! fr30_cgen_insn_supported (cd, insn))
 488         continue;
 489 #endif
 490
 491       /* Basic bit mask must be correct.  */
 492       /* ??? May wish to allow target to defer this check until the extract
 493          handler.  */
 494       if ((insn_value & CGEN_INSN_BASE_MASK (insn))
 495           == CGEN_INSN_BASE_VALUE (insn))
 496         {
 497           /* Printing is handled in two passes.  The first pass parses the
 498              machine insn and extracts the fields.  The second pass prints
 499              them.  */
 500
 501           length = CGEN_EXTRACT_FN (cd, insn)
 502             (cd, insn, &ex_info, insn_value, &fields, pc);
 503           /* length < 0 -> error */
 504           if (length < 0)
 505             return length;
 506           if (length > 0)
 507             {
 508               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 509               /* length is in bits, result is in bytes */
 510               return length / 8;
 511             }
 512         }
 513
 514       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 515     }
 516
 517   return 0;
 518 }
 519
 520 /* Default value for CGEN_PRINT_INSN.
 521    The result is the size of the insn in bytes or zero for an unknown insn
 522    or -1 if an error occured fetching bytes.  */
 523
 524 #ifndef CGEN_PRINT_INSN
 525 #define CGEN_PRINT_INSN default_print_insn
 526 #endif
 527
 528 static int
 529 default_print_insn (cd, pc, info)
 530      CGEN_CPU_DESC cd;
 531      bfd_vma pc;
 532      disassemble_info *info;
 533 {
 534   char buf[CGEN_MAX_INSN_SIZE];
 535   int status;
 536
 537   /* Read the base part of the insn.  */
 538
 539   status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info);
 540   if (status != 0)
 541     {
 542       (*info->memory_error_func) (status, pc, info);
 543       return -1;
 544     }
 545
 546   return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8);
 547 }
 548
 549 /* Main entry point.
 550    Print one instruction from PC on INFO->STREAM.
 551    Return the size of the instruction (in bytes).  */
 552
 553 int
 554 print_insn_fr30 (pc, info)
 555      bfd_vma pc;
 556      disassemble_info *info;
 557 {
 558   static CGEN_CPU_DESC cd = 0;
 559   static prev_isa,prev_mach,prev_endian;
 560   int length;
 561   int isa,mach;
 562   int endian = (info->endian == BFD_ENDIAN_BIG
 563                 ? CGEN_ENDIAN_BIG
 564                 : CGEN_ENDIAN_LITTLE);
 565   enum bfd_architecture arch;
 566
 567   /* ??? gdb will set mach but leave the architecture as "unknown" */
 568 #ifndef CGEN_BFD_ARCH
 569 #define CGEN_BFD_ARCH bfd_arch_fr30
 570 #endif
 571   arch = info->arch;
 572   if (arch == bfd_arch_unknown)
 573     arch = CGEN_BFD_ARCH;
 574
 575   /* There's no standard way to compute the isa number (e.g. for arm thumb)
 576      so we leave it to the target.  */
 577 #ifdef CGEN_COMPUTE_ISA
 578   isa = CGEN_COMPUTE_ISA (info);
 579 #else
 580   isa = 0;
 581 #endif
 582
 583   mach = info->mach;
 584
 585   /* If we've switched cpu's, close the current table and open a new one.  */
 586   if (cd
 587       && (isa != prev_isa
 588           || mach != prev_mach
 589           || endian != prev_endian))
 590     {
 591       fr30_cgen_cpu_close (cd);
 592       cd = 0;
 593     }
 594
 595   /* If we haven't initialized yet, initialize the opcode table.  */
 596   if (! cd)
 597     {
 598       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 599       const char *mach_name;
 600
 601       if (!arch_type)
 602         abort ();
 603       mach_name = arch_type->printable_name;
 604
 605       prev_isa = isa;
 606       prev_mach = mach;
 607       prev_endian = endian;
 608       cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 609                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 610                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 611                                  CGEN_CPU_OPEN_END);
 612       if (!cd)
 613         abort ();
 614       fr30_cgen_init_dis (cd);
 615     }
 616
 617   /* We try to have as much common code as possible.
 618      But at this point some targets need to take over.  */
 619   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 620      but if not possible try to move this hook elsewhere rather than
 621      have two hooks.  */
 622   length = CGEN_PRINT_INSN (cd, pc, info);
 623   if (length > 0)
 624     return length;
 625   if (length < 0)
 626     return -1;
 627
 628   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 629   return cd->default_insn_bitsize / 8;
 630 }