1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian
;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode
*insn_mo
;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend
;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode
;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p
: 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p
: 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p
: 1;
160 /* True if this instruction is complete. */
161 unsigned int complete_p
: 1;
164 /* The ABI to use. */
175 /* MIPS ABI we are using for this output file. */
176 static enum mips_abi_level mips_abi
= NO_ABI
;
178 /* Whether or not we have code that can call pic code. */
179 int mips_abicalls
= FALSE
;
181 /* Whether or not we have code which can be put into a shared
183 static bfd_boolean mips_in_shared
= TRUE
;
185 /* This is the set of options which may be modified by the .set
186 pseudo-op. We use a struct so that .set push and .set pop are more
189 struct mips_set_options
191 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
192 if it has not been initialized. Changed by `.set mipsN', and the
193 -mipsN command line option, and the default CPU. */
195 /* Enabled Application Specific Extensions (ASEs). These are set to -1
196 if they have not been initialized. Changed by `.set <asename>', by
197 command line options, and based on the default architecture. */
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Non-zero if we should not reorder instructions. Changed by `.set
210 reorder' and `.set noreorder'. */
212 /* Non-zero if we should not permit the register designated "assembler
213 temporary" to be used in instructions. The value is the register
214 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
215 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
217 /* Non-zero if we should warn when a macro instruction expands into
218 more than one machine instruction. Changed by `.set nomacro' and
220 int warn_about_macros
;
221 /* Non-zero if we should not move instructions. Changed by `.set
222 move', `.set volatile', `.set nomove', and `.set novolatile'. */
224 /* Non-zero if we should not optimize branches by moving the target
225 of the branch into the delay slot. Actually, we don't perform
226 this optimization anyhow. Changed by `.set bopt' and `.set
229 /* Non-zero if we should not autoextend mips16 instructions.
230 Changed by `.set autoextend' and `.set noautoextend'. */
232 /* Restrict general purpose registers and floating point registers
233 to 32 bit. This is initially determined when -mgp32 or -mfp32
234 is passed but can changed if the assembler code uses .set mipsN. */
237 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
238 command line option, and the default CPU. */
240 /* True if ".set sym32" is in effect. */
242 /* True if floating-point operations are not allowed. Changed by .set
243 softfloat or .set hardfloat, by command line options -msoft-float or
244 -mhard-float. The default is false. */
245 bfd_boolean soft_float
;
247 /* True if only single-precision floating-point operations are allowed.
248 Changed by .set singlefloat or .set doublefloat, command-line options
249 -msingle-float or -mdouble-float. The default is false. */
250 bfd_boolean single_float
;
253 /* This is the struct we use to hold the current set of options. Note
254 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
255 -1 to indicate that they have not been initialized. */
257 /* True if -mgp32 was passed. */
258 static int file_mips_gp32
= -1;
260 /* True if -mfp32 was passed. */
261 static int file_mips_fp32
= -1;
263 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
264 static int file_mips_soft_float
= 0;
266 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
267 static int file_mips_single_float
= 0;
269 static struct mips_set_options mips_opts
=
271 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
272 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
273 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
274 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
275 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
276 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
279 /* These variables are filled in with the masks of registers used.
280 The object format code reads them and puts them in the appropriate
282 unsigned long mips_gprmask
;
283 unsigned long mips_cprmask
[4];
285 /* MIPS ISA we are using for this output file. */
286 static int file_mips_isa
= ISA_UNKNOWN
;
288 /* True if any MIPS16 code was produced. */
289 static int file_ase_mips16
;
291 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
292 || mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64 \
294 || mips_opts.isa == ISA_MIPS64R2)
296 /* True if we want to create R_MIPS_JALR for jalr $25. */
298 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
300 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
301 because there's no place for any addend, the only acceptable
302 expression is a bare symbol. */
303 #define MIPS_JALR_HINT_P(EXPR) \
304 (!HAVE_IN_PLACE_ADDENDS \
305 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
308 /* True if -mips3d was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_mips3d
;
312 /* True if -mdmx was passed or implied by arguments passed on the
313 command line (e.g., by -march). */
314 static int file_ase_mdmx
;
316 /* True if -msmartmips was passed or implied by arguments passed on the
317 command line (e.g., by -march). */
318 static int file_ase_smartmips
;
320 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
321 || mips_opts.isa == ISA_MIPS32R2)
323 /* True if -mdsp was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_dsp
;
327 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS64R2)
330 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
332 /* True if -mdspr2 was passed or implied by arguments passed on the
333 command line (e.g., by -march). */
334 static int file_ase_dspr2
;
336 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
337 || mips_opts.isa == ISA_MIPS64R2)
339 /* True if -mmt was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mt
;
343 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
344 || mips_opts.isa == ISA_MIPS64R2)
346 /* The argument of the -march= flag. The architecture we are assembling. */
347 static int file_mips_arch
= CPU_UNKNOWN
;
348 static const char *mips_arch_string
;
350 /* The argument of the -mtune= flag. The architecture for which we
352 static int mips_tune
= CPU_UNKNOWN
;
353 static const char *mips_tune_string
;
355 /* True when generating 32-bit code for a 64-bit processor. */
356 static int mips_32bitmode
= 0;
358 /* True if the given ABI requires 32-bit registers. */
359 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
361 /* Likewise 64-bit registers. */
362 #define ABI_NEEDS_64BIT_REGS(ABI) \
364 || (ABI) == N64_ABI \
367 /* Return true if ISA supports 64 bit wide gp registers. */
368 #define ISA_HAS_64BIT_REGS(ISA) \
369 ((ISA) == ISA_MIPS3 \
370 || (ISA) == ISA_MIPS4 \
371 || (ISA) == ISA_MIPS5 \
372 || (ISA) == ISA_MIPS64 \
373 || (ISA) == ISA_MIPS64R2)
375 /* Return true if ISA supports 64 bit wide float registers. */
376 #define ISA_HAS_64BIT_FPRS(ISA) \
377 ((ISA) == ISA_MIPS3 \
378 || (ISA) == ISA_MIPS4 \
379 || (ISA) == ISA_MIPS5 \
380 || (ISA) == ISA_MIPS32R2 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2)
384 /* Return true if ISA supports 64-bit right rotate (dror et al.)
386 #define ISA_HAS_DROR(ISA) \
387 ((ISA) == ISA_MIPS64R2)
389 /* Return true if ISA supports 32-bit right rotate (ror et al.)
391 #define ISA_HAS_ROR(ISA) \
392 ((ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS64R2 \
394 || mips_opts.ase_smartmips)
396 /* Return true if ISA supports single-precision floats in odd registers. */
397 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
398 ((ISA) == ISA_MIPS32 \
399 || (ISA) == ISA_MIPS32R2 \
400 || (ISA) == ISA_MIPS64 \
401 || (ISA) == ISA_MIPS64R2)
403 /* Return true if ISA supports move to/from high part of a 64-bit
404 floating-point register. */
405 #define ISA_HAS_MXHC1(ISA) \
406 ((ISA) == ISA_MIPS32R2 \
407 || (ISA) == ISA_MIPS64R2)
409 #define HAVE_32BIT_GPRS \
410 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
412 #define HAVE_32BIT_FPRS \
413 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
415 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
416 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
418 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
420 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
422 /* True if relocations are stored in-place. */
423 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
425 /* The ABI-derived address size. */
426 #define HAVE_64BIT_ADDRESSES \
427 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
428 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
430 /* The size of symbolic constants (i.e., expressions of the form
431 "SYMBOL" or "SYMBOL + OFFSET"). */
432 #define HAVE_32BIT_SYMBOLS \
433 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
434 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
436 /* Addresses are loaded in different ways, depending on the address size
437 in use. The n32 ABI Documentation also mandates the use of additions
438 with overflow checking, but existing implementations don't follow it. */
439 #define ADDRESS_ADD_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
442 #define ADDRESS_ADDI_INSN \
443 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
445 #define ADDRESS_LOAD_INSN \
446 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
448 #define ADDRESS_STORE_INSN \
449 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
451 /* Return true if the given CPU supports the MIPS16 ASE. */
452 #define CPU_HAS_MIPS16(cpu) \
453 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
454 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
456 /* True if CPU has a dror instruction. */
457 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
459 /* True if CPU has a ror instruction. */
460 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
462 /* True if CPU has seq/sne and seqi/snei instructions. */
463 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
465 /* True if CPU does not implement the all the coprocessor insns. For these
466 CPUs only those COP insns are accepted that are explicitly marked to be
467 available on the CPU. ISA membership for COP insns is ignored. */
468 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
470 /* True if mflo and mfhi can be immediately followed by instructions
471 which write to the HI and LO registers.
473 According to MIPS specifications, MIPS ISAs I, II, and III need
474 (at least) two instructions between the reads of HI/LO and
475 instructions which write them, and later ISAs do not. Contradicting
476 the MIPS specifications, some MIPS IV processor user manuals (e.g.
477 the UM for the NEC Vr5000) document needing the instructions between
478 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
479 MIPS64 and later ISAs to have the interlocks, plus any specific
480 earlier-ISA CPUs for which CPU documentation declares that the
481 instructions are really interlocked. */
482 #define hilo_interlocks \
483 (mips_opts.isa == ISA_MIPS32 \
484 || mips_opts.isa == ISA_MIPS32R2 \
485 || mips_opts.isa == ISA_MIPS64 \
486 || mips_opts.isa == ISA_MIPS64R2 \
487 || mips_opts.arch == CPU_R4010 \
488 || mips_opts.arch == CPU_R10000 \
489 || mips_opts.arch == CPU_R12000 \
490 || mips_opts.arch == CPU_R14000 \
491 || mips_opts.arch == CPU_R16000 \
492 || mips_opts.arch == CPU_RM7000 \
493 || mips_opts.arch == CPU_VR5500 \
496 /* Whether the processor uses hardware interlocks to protect reads
497 from the GPRs after they are loaded from memory, and thus does not
498 require nops to be inserted. This applies to instructions marked
499 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
501 #define gpr_interlocks \
502 (mips_opts.isa != ISA_MIPS1 \
503 || mips_opts.arch == CPU_R3900)
505 /* Whether the processor uses hardware interlocks to avoid delays
506 required by coprocessor instructions, and thus does not require
507 nops to be inserted. This applies to instructions marked
508 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
509 between instructions marked INSN_WRITE_COND_CODE and ones marked
510 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
511 levels I, II, and III. */
512 /* Itbl support may require additional care here. */
513 #define cop_interlocks \
514 ((mips_opts.isa != ISA_MIPS1 \
515 && mips_opts.isa != ISA_MIPS2 \
516 && mips_opts.isa != ISA_MIPS3) \
517 || mips_opts.arch == CPU_R4300 \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I. */
525 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
527 /* Is this a mfhi or mflo instruction? */
528 #define MF_HILO_INSN(PINFO) \
529 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
531 /* Returns true for a (non floating-point) coprocessor instruction. Reading
532 or writing the condition code is only possible on the coprocessors and
533 these insns are not marked with INSN_COP. Thus for these insns use the
534 condition-code flags. */
535 #define COP_INSN(PINFO) \
536 (PINFO != INSN_MACRO \
537 && ((PINFO) & (FP_S | FP_D)) == 0 \
538 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
540 /* MIPS PIC level. */
542 enum mips_pic_level mips_pic
;
544 /* 1 if we should generate 32 bit offsets from the $gp register in
545 SVR4_PIC mode. Currently has no meaning in other modes. */
546 static int mips_big_got
= 0;
548 /* 1 if trap instructions should used for overflow rather than break
550 static int mips_trap
= 0;
552 /* 1 if double width floating point constants should not be constructed
553 by assembling two single width halves into two single width floating
554 point registers which just happen to alias the double width destination
555 register. On some architectures this aliasing can be disabled by a bit
556 in the status register, and the setting of this bit cannot be determined
557 automatically at assemble time. */
558 static int mips_disable_float_construction
;
560 /* Non-zero if any .set noreorder directives were used. */
562 static int mips_any_noreorder
;
564 /* Non-zero if nops should be inserted when the register referenced in
565 an mfhi/mflo instruction is read in the next two instructions. */
566 static int mips_7000_hilo_fix
;
568 /* The size of objects in the small data section. */
569 static unsigned int g_switch_value
= 8;
570 /* Whether the -G option was used. */
571 static int g_switch_seen
= 0;
576 /* If we can determine in advance that GP optimization won't be
577 possible, we can skip the relaxation stuff that tries to produce
578 GP-relative references. This makes delay slot optimization work
581 This function can only provide a guess, but it seems to work for
582 gcc output. It needs to guess right for gcc, otherwise gcc
583 will put what it thinks is a GP-relative instruction in a branch
586 I don't know if a fix is needed for the SVR4_PIC mode. I've only
587 fixed it for the non-PIC mode. KR 95/04/07 */
588 static int nopic_need_relax (symbolS
*, int);
590 /* handle of the OPCODE hash table */
591 static struct hash_control
*op_hash
= NULL
;
593 /* The opcode hash table we use for the mips16. */
594 static struct hash_control
*mips16_op_hash
= NULL
;
596 /* This array holds the chars that always start a comment. If the
597 pre-processor is disabled, these aren't very useful */
598 const char comment_chars
[] = "#";
600 /* This array holds the chars that only start a comment at the beginning of
601 a line. If the line seems to have the form '# 123 filename'
602 .line and .file directives will appear in the pre-processed output */
603 /* Note that input_file.c hand checks for '#' at the beginning of the
604 first line of the input file. This is because the compiler outputs
605 #NO_APP at the beginning of its output. */
606 /* Also note that C style comments are always supported. */
607 const char line_comment_chars
[] = "#";
609 /* This array holds machine specific line separator characters. */
610 const char line_separator_chars
[] = ";";
612 /* Chars that can be used to separate mant from exp in floating point nums */
613 const char EXP_CHARS
[] = "eE";
615 /* Chars that mean this number is a floating point constant */
618 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
620 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
621 changed in read.c . Ideally it shouldn't have to know about it at all,
622 but nothing is ideal around here.
625 static char *insn_error
;
627 static int auto_align
= 1;
629 /* When outputting SVR4 PIC code, the assembler needs to know the
630 offset in the stack frame from which to restore the $gp register.
631 This is set by the .cprestore pseudo-op, and saved in this
633 static offsetT mips_cprestore_offset
= -1;
635 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
636 more optimizations, it can use a register value instead of a memory-saved
637 offset and even an other register than $gp as global pointer. */
638 static offsetT mips_cpreturn_offset
= -1;
639 static int mips_cpreturn_register
= -1;
640 static int mips_gp_register
= GP
;
641 static int mips_gprel_offset
= 0;
643 /* Whether mips_cprestore_offset has been set in the current function
644 (or whether it has already been warned about, if not). */
645 static int mips_cprestore_valid
= 0;
647 /* This is the register which holds the stack frame, as set by the
648 .frame pseudo-op. This is needed to implement .cprestore. */
649 static int mips_frame_reg
= SP
;
651 /* Whether mips_frame_reg has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_frame_reg_valid
= 0;
655 /* To output NOP instructions correctly, we need to keep information
656 about the previous two instructions. */
658 /* Whether we are optimizing. The default value of 2 means to remove
659 unneeded NOPs and swap branch instructions when possible. A value
660 of 1 means to not swap branches. A value of 0 means to always
662 static int mips_optimize
= 2;
664 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
665 equivalent to seeing no -g option at all. */
666 static int mips_debug
= 0;
668 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
669 #define MAX_VR4130_NOPS 4
671 /* The maximum number of NOPs needed to fill delay slots. */
672 #define MAX_DELAY_NOPS 2
674 /* The maximum number of NOPs needed for any purpose. */
677 /* A list of previous instructions, with index 0 being the most recent.
678 We need to look back MAX_NOPS instructions when filling delay slots
679 or working around processor errata. We need to look back one
680 instruction further if we're thinking about using history[0] to
681 fill a branch delay slot. */
682 static struct mips_cl_insn history
[1 + MAX_NOPS
];
684 /* Nop instructions used by emit_nop. */
685 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
687 /* The appropriate nop for the current mode. */
688 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
690 /* If this is set, it points to a frag holding nop instructions which
691 were inserted before the start of a noreorder section. If those
692 nops turn out to be unnecessary, the size of the frag can be
694 static fragS
*prev_nop_frag
;
696 /* The number of nop instructions we created in prev_nop_frag. */
697 static int prev_nop_frag_holds
;
699 /* The number of nop instructions that we know we need in
701 static int prev_nop_frag_required
;
703 /* The number of instructions we've seen since prev_nop_frag. */
704 static int prev_nop_frag_since
;
706 /* For ECOFF and ELF, relocations against symbols are done in two
707 parts, with a HI relocation and a LO relocation. Each relocation
708 has only 16 bits of space to store an addend. This means that in
709 order for the linker to handle carries correctly, it must be able
710 to locate both the HI and the LO relocation. This means that the
711 relocations must appear in order in the relocation table.
713 In order to implement this, we keep track of each unmatched HI
714 relocation. We then sort them so that they immediately precede the
715 corresponding LO relocation. */
720 struct mips_hi_fixup
*next
;
723 /* The section this fixup is in. */
727 /* The list of unmatched HI relocs. */
729 static struct mips_hi_fixup
*mips_hi_fixup_list
;
731 /* The frag containing the last explicit relocation operator.
732 Null if explicit relocations have not been used. */
734 static fragS
*prev_reloc_op_frag
;
736 /* Map normal MIPS register numbers to mips16 register numbers. */
738 #define X ILLEGAL_REG
739 static const int mips32_to_16_reg_map
[] =
741 X
, X
, 2, 3, 4, 5, 6, 7,
742 X
, X
, X
, X
, X
, X
, X
, X
,
743 0, 1, X
, X
, X
, X
, X
, X
,
744 X
, X
, X
, X
, X
, X
, X
, X
748 /* Map mips16 register numbers to normal MIPS register numbers. */
750 static const unsigned int mips16_to_32_reg_map
[] =
752 16, 17, 2, 3, 4, 5, 6, 7
755 /* Classifies the kind of instructions we're interested in when
756 implementing -mfix-vr4120. */
757 enum fix_vr4120_class
765 NUM_FIX_VR4120_CLASSES
768 /* ...likewise -mfix-loongson2f-jump. */
769 static bfd_boolean mips_fix_loongson2f_jump
;
771 /* ...likewise -mfix-loongson2f-nop. */
772 static bfd_boolean mips_fix_loongson2f_nop
;
774 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
775 static bfd_boolean mips_fix_loongson2f
;
777 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
778 there must be at least one other instruction between an instruction
779 of type X and an instruction of type Y. */
780 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
782 /* True if -mfix-vr4120 is in force. */
783 static int mips_fix_vr4120
;
785 /* ...likewise -mfix-vr4130. */
786 static int mips_fix_vr4130
;
788 /* ...likewise -mfix-24k. */
789 static int mips_fix_24k
;
791 /* ...likewise -mfix-cn63xxp1 */
792 static bfd_boolean mips_fix_cn63xxp1
;
794 /* We don't relax branches by default, since this causes us to expand
795 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
796 fail to compute the offset before expanding the macro to the most
797 efficient expansion. */
799 static int mips_relax_branch
;
801 /* The expansion of many macros depends on the type of symbol that
802 they refer to. For example, when generating position-dependent code,
803 a macro that refers to a symbol may have two different expansions,
804 one which uses GP-relative addresses and one which uses absolute
805 addresses. When generating SVR4-style PIC, a macro may have
806 different expansions for local and global symbols.
808 We handle these situations by generating both sequences and putting
809 them in variant frags. In position-dependent code, the first sequence
810 will be the GP-relative one and the second sequence will be the
811 absolute one. In SVR4 PIC, the first sequence will be for global
812 symbols and the second will be for local symbols.
814 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
815 SECOND are the lengths of the two sequences in bytes. These fields
816 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
817 the subtype has the following flags:
820 Set if it has been decided that we should use the second
821 sequence instead of the first.
824 Set in the first variant frag if the macro's second implementation
825 is longer than its first. This refers to the macro as a whole,
826 not an individual relaxation.
829 Set in the first variant frag if the macro appeared in a .set nomacro
830 block and if one alternative requires a warning but the other does not.
833 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
836 The frag's "opcode" points to the first fixup for relaxable code.
838 Relaxable macros are generated using a sequence such as:
840 relax_start (SYMBOL);
841 ... generate first expansion ...
843 ... generate second expansion ...
846 The code and fixups for the unwanted alternative are discarded
847 by md_convert_frag. */
848 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
850 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
851 #define RELAX_SECOND(X) ((X) & 0xff)
852 #define RELAX_USE_SECOND 0x10000
853 #define RELAX_SECOND_LONGER 0x20000
854 #define RELAX_NOMACRO 0x40000
855 #define RELAX_DELAY_SLOT 0x80000
857 /* Branch without likely bit. If label is out of range, we turn:
859 beq reg1, reg2, label
869 with the following opcode replacements:
876 bltzal <-> bgezal (with jal label instead of j label)
878 Even though keeping the delay slot instruction in the delay slot of
879 the branch would be more efficient, it would be very tricky to do
880 correctly, because we'd have to introduce a variable frag *after*
881 the delay slot instruction, and expand that instead. Let's do it
882 the easy way for now, even if the branch-not-taken case now costs
883 one additional instruction. Out-of-range branches are not supposed
884 to be common, anyway.
886 Branch likely. If label is out of range, we turn:
888 beql reg1, reg2, label
889 delay slot (annulled if branch not taken)
898 delay slot (executed only if branch taken)
901 It would be possible to generate a shorter sequence by losing the
902 likely bit, generating something like:
907 delay slot (executed only if branch taken)
919 bltzall -> bgezal (with jal label instead of j label)
920 bgezall -> bltzal (ditto)
923 but it's not clear that it would actually improve performance. */
924 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
928 | ((toofar) ? 0x20 : 0) \
929 | ((link) ? 0x40 : 0) \
930 | ((likely) ? 0x80 : 0) \
931 | ((uncond) ? 0x100 : 0)))
932 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
933 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
934 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
935 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
936 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
937 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
939 /* For mips16 code, we use an entirely different form of relaxation.
940 mips16 supports two versions of most instructions which take
941 immediate values: a small one which takes some small value, and a
942 larger one which takes a 16 bit value. Since branches also follow
943 this pattern, relaxing these values is required.
945 We can assemble both mips16 and normal MIPS code in a single
946 object. Therefore, we need to support this type of relaxation at
947 the same time that we support the relaxation described above. We
948 use the high bit of the subtype field to distinguish these cases.
950 The information we store for this type of relaxation is the
951 argument code found in the opcode file for this relocation, whether
952 the user explicitly requested a small or extended form, and whether
953 the relocation is in a jump or jal delay slot. That tells us the
954 size of the value, and how it should be stored. We also store
955 whether the fragment is considered to be extended or not. We also
956 store whether this is known to be a branch to a different section,
957 whether we have tried to relax this frag yet, and whether we have
958 ever extended a PC relative fragment because of a shift count. */
959 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
962 | ((small) ? 0x100 : 0) \
963 | ((ext) ? 0x200 : 0) \
964 | ((dslot) ? 0x400 : 0) \
965 | ((jal_dslot) ? 0x800 : 0))
966 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
967 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
968 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
969 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
970 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
971 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
972 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
973 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
974 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
975 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
976 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
977 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
979 /* Is the given value a sign-extended 32-bit value? */
980 #define IS_SEXT_32BIT_NUM(x) \
981 (((x) &~ (offsetT) 0x7fffffff) == 0 \
982 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
984 /* Is the given value a sign-extended 16-bit value? */
985 #define IS_SEXT_16BIT_NUM(x) \
986 (((x) &~ (offsetT) 0x7fff) == 0 \
987 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
989 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
990 #define IS_ZEXT_32BIT_NUM(x) \
991 (((x) &~ (offsetT) 0xffffffff) == 0 \
992 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
994 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
995 VALUE << SHIFT. VALUE is evaluated exactly once. */
996 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
997 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
998 | (((VALUE) & (MASK)) << (SHIFT)))
1000 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1002 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1003 (((STRUCT) >> (SHIFT)) & (MASK))
1005 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1006 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1008 include/opcode/mips.h specifies operand fields using the macros
1009 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1010 with "MIPS16OP" instead of "OP". */
1011 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1012 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1014 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1015 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1017 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1018 #define EXTRACT_OPERAND(FIELD, INSN) \
1019 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1020 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1021 EXTRACT_BITS ((INSN).insn_opcode, \
1022 MIPS16OP_MASK_##FIELD, \
1023 MIPS16OP_SH_##FIELD)
1025 /* Global variables used when generating relaxable macros. See the
1026 comment above RELAX_ENCODE for more details about how relaxation
1029 /* 0 if we're not emitting a relaxable macro.
1030 1 if we're emitting the first of the two relaxation alternatives.
1031 2 if we're emitting the second alternative. */
1034 /* The first relaxable fixup in the current frag. (In other words,
1035 the first fixup that refers to relaxable code.) */
1038 /* sizes[0] says how many bytes of the first alternative are stored in
1039 the current frag. Likewise sizes[1] for the second alternative. */
1040 unsigned int sizes
[2];
1042 /* The symbol on which the choice of sequence depends. */
1046 /* Global variables used to decide whether a macro needs a warning. */
1048 /* True if the macro is in a branch delay slot. */
1049 bfd_boolean delay_slot_p
;
1051 /* For relaxable macros, sizes[0] is the length of the first alternative
1052 in bytes and sizes[1] is the length of the second alternative.
1053 For non-relaxable macros, both elements give the length of the
1055 unsigned int sizes
[2];
1057 /* The first variant frag for this macro. */
1059 } mips_macro_warning
;
1061 /* Prototypes for static functions. */
1063 #define internalError() \
1064 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1066 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1068 static void append_insn
1069 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*);
1070 static void mips_no_prev_insn (void);
1071 static void macro_build (expressionS
*, const char *, const char *, ...);
1072 static void mips16_macro_build
1073 (expressionS
*, const char *, const char *, va_list *);
1074 static void load_register (int, expressionS
*, int);
1075 static void macro_start (void);
1076 static void macro_end (void);
1077 static void macro (struct mips_cl_insn
* ip
);
1078 static void mips16_macro (struct mips_cl_insn
* ip
);
1079 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1080 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1081 static void mips16_immed
1082 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1083 unsigned long *, bfd_boolean
*, unsigned short *);
1084 static size_t my_getSmallExpression
1085 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1086 static void my_getExpression (expressionS
*, char *);
1087 static void s_align (int);
1088 static void s_change_sec (int);
1089 static void s_change_section (int);
1090 static void s_cons (int);
1091 static void s_float_cons (int);
1092 static void s_mips_globl (int);
1093 static void s_option (int);
1094 static void s_mipsset (int);
1095 static void s_abicalls (int);
1096 static void s_cpload (int);
1097 static void s_cpsetup (int);
1098 static void s_cplocal (int);
1099 static void s_cprestore (int);
1100 static void s_cpreturn (int);
1101 static void s_dtprelword (int);
1102 static void s_dtpreldword (int);
1103 static void s_gpvalue (int);
1104 static void s_gpword (int);
1105 static void s_gpdword (int);
1106 static void s_cpadd (int);
1107 static void s_insn (int);
1108 static void md_obj_begin (void);
1109 static void md_obj_end (void);
1110 static void s_mips_ent (int);
1111 static void s_mips_end (int);
1112 static void s_mips_frame (int);
1113 static void s_mips_mask (int reg_type
);
1114 static void s_mips_stab (int);
1115 static void s_mips_weakext (int);
1116 static void s_mips_file (int);
1117 static void s_mips_loc (int);
1118 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1119 static int relaxed_branch_length (fragS
*, asection
*, int);
1120 static int validate_mips_insn (const struct mips_opcode
*);
1122 /* Table and functions used to map between CPU/ISA names, and
1123 ISA levels, and CPU numbers. */
1125 struct mips_cpu_info
1127 const char *name
; /* CPU or ISA name. */
1128 int flags
; /* ASEs available, or ISA flag. */
1129 int isa
; /* ISA level. */
1130 int cpu
; /* CPU number (default CPU if ISA). */
1133 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1134 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1135 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1136 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1137 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1138 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1139 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1141 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1142 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1143 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1147 The following pseudo-ops from the Kane and Heinrich MIPS book
1148 should be defined here, but are currently unsupported: .alias,
1149 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1151 The following pseudo-ops from the Kane and Heinrich MIPS book are
1152 specific to the type of debugging information being generated, and
1153 should be defined by the object format: .aent, .begin, .bend,
1154 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1157 The following pseudo-ops from the Kane and Heinrich MIPS book are
1158 not MIPS CPU specific, but are also not specific to the object file
1159 format. This file is probably the best place to define them, but
1160 they are not currently supported: .asm0, .endr, .lab, .struct. */
1162 static const pseudo_typeS mips_pseudo_table
[] =
1164 /* MIPS specific pseudo-ops. */
1165 {"option", s_option
, 0},
1166 {"set", s_mipsset
, 0},
1167 {"rdata", s_change_sec
, 'r'},
1168 {"sdata", s_change_sec
, 's'},
1169 {"livereg", s_ignore
, 0},
1170 {"abicalls", s_abicalls
, 0},
1171 {"cpload", s_cpload
, 0},
1172 {"cpsetup", s_cpsetup
, 0},
1173 {"cplocal", s_cplocal
, 0},
1174 {"cprestore", s_cprestore
, 0},
1175 {"cpreturn", s_cpreturn
, 0},
1176 {"dtprelword", s_dtprelword
, 0},
1177 {"dtpreldword", s_dtpreldword
, 0},
1178 {"gpvalue", s_gpvalue
, 0},
1179 {"gpword", s_gpword
, 0},
1180 {"gpdword", s_gpdword
, 0},
1181 {"cpadd", s_cpadd
, 0},
1182 {"insn", s_insn
, 0},
1184 /* Relatively generic pseudo-ops that happen to be used on MIPS
1186 {"asciiz", stringer
, 8 + 1},
1187 {"bss", s_change_sec
, 'b'},
1189 {"half", s_cons
, 1},
1190 {"dword", s_cons
, 3},
1191 {"weakext", s_mips_weakext
, 0},
1192 {"origin", s_org
, 0},
1193 {"repeat", s_rept
, 0},
1195 /* For MIPS this is non-standard, but we define it for consistency. */
1196 {"sbss", s_change_sec
, 'B'},
1198 /* These pseudo-ops are defined in read.c, but must be overridden
1199 here for one reason or another. */
1200 {"align", s_align
, 0},
1201 {"byte", s_cons
, 0},
1202 {"data", s_change_sec
, 'd'},
1203 {"double", s_float_cons
, 'd'},
1204 {"float", s_float_cons
, 'f'},
1205 {"globl", s_mips_globl
, 0},
1206 {"global", s_mips_globl
, 0},
1207 {"hword", s_cons
, 1},
1209 {"long", s_cons
, 2},
1210 {"octa", s_cons
, 4},
1211 {"quad", s_cons
, 3},
1212 {"section", s_change_section
, 0},
1213 {"short", s_cons
, 1},
1214 {"single", s_float_cons
, 'f'},
1215 {"stabn", s_mips_stab
, 'n'},
1216 {"text", s_change_sec
, 't'},
1217 {"word", s_cons
, 2},
1219 { "extern", ecoff_directive_extern
, 0},
1224 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1226 /* These pseudo-ops should be defined by the object file format.
1227 However, a.out doesn't support them, so we have versions here. */
1228 {"aent", s_mips_ent
, 1},
1229 {"bgnb", s_ignore
, 0},
1230 {"end", s_mips_end
, 0},
1231 {"endb", s_ignore
, 0},
1232 {"ent", s_mips_ent
, 0},
1233 {"file", s_mips_file
, 0},
1234 {"fmask", s_mips_mask
, 'F'},
1235 {"frame", s_mips_frame
, 0},
1236 {"loc", s_mips_loc
, 0},
1237 {"mask", s_mips_mask
, 'R'},
1238 {"verstamp", s_ignore
, 0},
1242 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1243 purpose of the `.dc.a' internal pseudo-op. */
1246 mips_address_bytes (void)
1248 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1251 extern void pop_insert (const pseudo_typeS
*);
1254 mips_pop_insert (void)
1256 pop_insert (mips_pseudo_table
);
1257 if (! ECOFF_DEBUGGING
)
1258 pop_insert (mips_nonecoff_pseudo_table
);
1261 /* Symbols labelling the current insn. */
1263 struct insn_label_list
1265 struct insn_label_list
*next
;
1269 static struct insn_label_list
*free_insn_labels
;
1270 #define label_list tc_segment_info_data.labels
1272 static void mips_clear_insn_labels (void);
1275 mips_clear_insn_labels (void)
1277 register struct insn_label_list
**pl
;
1278 segment_info_type
*si
;
1282 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1285 si
= seg_info (now_seg
);
1286 *pl
= si
->label_list
;
1287 si
->label_list
= NULL
;
1292 static char *expr_end
;
1294 /* Expressions which appear in instructions. These are set by
1297 static expressionS imm_expr
;
1298 static expressionS imm2_expr
;
1299 static expressionS offset_expr
;
1301 /* Relocs associated with imm_expr and offset_expr. */
1303 static bfd_reloc_code_real_type imm_reloc
[3]
1304 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1305 static bfd_reloc_code_real_type offset_reloc
[3]
1306 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1308 /* These are set by mips16_ip if an explicit extension is used. */
1310 static bfd_boolean mips16_small
, mips16_ext
;
1313 /* The pdr segment for per procedure frame/regmask info. Not used for
1316 static segT pdr_seg
;
1319 /* The default target format to use. */
1321 #if defined (TE_FreeBSD)
1322 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1323 #elif defined (TE_TMIPS)
1324 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1326 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1330 mips_target_format (void)
1332 switch (OUTPUT_FLAVOR
)
1334 case bfd_target_ecoff_flavour
:
1335 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1336 case bfd_target_coff_flavour
:
1338 case bfd_target_elf_flavour
:
1340 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1341 return (target_big_endian
1342 ? "elf32-bigmips-vxworks"
1343 : "elf32-littlemips-vxworks");
1345 return (target_big_endian
1346 ? (HAVE_64BIT_OBJECTS
1347 ? ELF_TARGET ("elf64-", "big")
1349 ? ELF_TARGET ("elf32-n", "big")
1350 : ELF_TARGET ("elf32-", "big")))
1351 : (HAVE_64BIT_OBJECTS
1352 ? ELF_TARGET ("elf64-", "little")
1354 ? ELF_TARGET ("elf32-n", "little")
1355 : ELF_TARGET ("elf32-", "little"))));
1362 /* Return the length of instruction INSN. */
1364 static inline unsigned int
1365 insn_length (const struct mips_cl_insn
*insn
)
1367 if (!mips_opts
.mips16
)
1369 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1372 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1375 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1380 insn
->use_extend
= FALSE
;
1382 insn
->insn_opcode
= mo
->match
;
1385 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1386 insn
->fixp
[i
] = NULL
;
1387 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1388 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1389 insn
->mips16_absolute_jump_p
= 0;
1390 insn
->complete_p
= 0;
1393 /* Record the current MIPS16 mode in now_seg. */
1396 mips_record_mips16_mode (void)
1398 segment_info_type
*si
;
1400 si
= seg_info (now_seg
);
1401 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1402 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1405 /* Install INSN at the location specified by its "frag" and "where" fields. */
1408 install_insn (const struct mips_cl_insn
*insn
)
1410 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1411 if (!mips_opts
.mips16
)
1412 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1413 else if (insn
->mips16_absolute_jump_p
)
1415 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1416 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1420 if (insn
->use_extend
)
1422 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1425 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1427 mips_record_mips16_mode ();
1430 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1431 and install the opcode in the new location. */
1434 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1439 insn
->where
= where
;
1440 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1441 if (insn
->fixp
[i
] != NULL
)
1443 insn
->fixp
[i
]->fx_frag
= frag
;
1444 insn
->fixp
[i
]->fx_where
= where
;
1446 install_insn (insn
);
1449 /* Add INSN to the end of the output. */
1452 add_fixed_insn (struct mips_cl_insn
*insn
)
1454 char *f
= frag_more (insn_length (insn
));
1455 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1458 /* Start a variant frag and move INSN to the start of the variant part,
1459 marking it as fixed. The other arguments are as for frag_var. */
1462 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1463 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1465 frag_grow (max_chars
);
1466 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1468 frag_var (rs_machine_dependent
, max_chars
, var
,
1469 subtype
, symbol
, offset
, NULL
);
1472 /* Insert N copies of INSN into the history buffer, starting at
1473 position FIRST. Neither FIRST nor N need to be clipped. */
1476 insert_into_history (unsigned int first
, unsigned int n
,
1477 const struct mips_cl_insn
*insn
)
1479 if (mips_relax
.sequence
!= 2)
1483 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1485 history
[i
] = history
[i
- n
];
1491 /* Emit a nop instruction, recording it in the history buffer. */
1496 add_fixed_insn (NOP_INSN
);
1497 insert_into_history (0, 1, NOP_INSN
);
1500 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1501 the idea is to make it obvious at a glance that each errata is
1505 init_vr4120_conflicts (void)
1507 #define CONFLICT(FIRST, SECOND) \
1508 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1510 /* Errata 21 - [D]DIV[U] after [D]MACC */
1511 CONFLICT (MACC
, DIV
);
1512 CONFLICT (DMACC
, DIV
);
1514 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1515 CONFLICT (DMULT
, DMULT
);
1516 CONFLICT (DMULT
, DMACC
);
1517 CONFLICT (DMACC
, DMULT
);
1518 CONFLICT (DMACC
, DMACC
);
1520 /* Errata 24 - MT{LO,HI} after [D]MACC */
1521 CONFLICT (MACC
, MTHILO
);
1522 CONFLICT (DMACC
, MTHILO
);
1524 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1525 instruction is executed immediately after a MACC or DMACC
1526 instruction, the result of [either instruction] is incorrect." */
1527 CONFLICT (MACC
, MULT
);
1528 CONFLICT (MACC
, DMULT
);
1529 CONFLICT (DMACC
, MULT
);
1530 CONFLICT (DMACC
, DMULT
);
1532 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1533 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1534 DDIV or DDIVU instruction, the result of the MACC or
1535 DMACC instruction is incorrect.". */
1536 CONFLICT (DMULT
, MACC
);
1537 CONFLICT (DMULT
, DMACC
);
1538 CONFLICT (DIV
, MACC
);
1539 CONFLICT (DIV
, DMACC
);
1549 #define RTYPE_MASK 0x1ff00
1550 #define RTYPE_NUM 0x00100
1551 #define RTYPE_FPU 0x00200
1552 #define RTYPE_FCC 0x00400
1553 #define RTYPE_VEC 0x00800
1554 #define RTYPE_GP 0x01000
1555 #define RTYPE_CP0 0x02000
1556 #define RTYPE_PC 0x04000
1557 #define RTYPE_ACC 0x08000
1558 #define RTYPE_CCC 0x10000
1559 #define RNUM_MASK 0x000ff
1560 #define RWARN 0x80000
1562 #define GENERIC_REGISTER_NUMBERS \
1563 {"$0", RTYPE_NUM | 0}, \
1564 {"$1", RTYPE_NUM | 1}, \
1565 {"$2", RTYPE_NUM | 2}, \
1566 {"$3", RTYPE_NUM | 3}, \
1567 {"$4", RTYPE_NUM | 4}, \
1568 {"$5", RTYPE_NUM | 5}, \
1569 {"$6", RTYPE_NUM | 6}, \
1570 {"$7", RTYPE_NUM | 7}, \
1571 {"$8", RTYPE_NUM | 8}, \
1572 {"$9", RTYPE_NUM | 9}, \
1573 {"$10", RTYPE_NUM | 10}, \
1574 {"$11", RTYPE_NUM | 11}, \
1575 {"$12", RTYPE_NUM | 12}, \
1576 {"$13", RTYPE_NUM | 13}, \
1577 {"$14", RTYPE_NUM | 14}, \
1578 {"$15", RTYPE_NUM | 15}, \
1579 {"$16", RTYPE_NUM | 16}, \
1580 {"$17", RTYPE_NUM | 17}, \
1581 {"$18", RTYPE_NUM | 18}, \
1582 {"$19", RTYPE_NUM | 19}, \
1583 {"$20", RTYPE_NUM | 20}, \
1584 {"$21", RTYPE_NUM | 21}, \
1585 {"$22", RTYPE_NUM | 22}, \
1586 {"$23", RTYPE_NUM | 23}, \
1587 {"$24", RTYPE_NUM | 24}, \
1588 {"$25", RTYPE_NUM | 25}, \
1589 {"$26", RTYPE_NUM | 26}, \
1590 {"$27", RTYPE_NUM | 27}, \
1591 {"$28", RTYPE_NUM | 28}, \
1592 {"$29", RTYPE_NUM | 29}, \
1593 {"$30", RTYPE_NUM | 30}, \
1594 {"$31", RTYPE_NUM | 31}
1596 #define FPU_REGISTER_NAMES \
1597 {"$f0", RTYPE_FPU | 0}, \
1598 {"$f1", RTYPE_FPU | 1}, \
1599 {"$f2", RTYPE_FPU | 2}, \
1600 {"$f3", RTYPE_FPU | 3}, \
1601 {"$f4", RTYPE_FPU | 4}, \
1602 {"$f5", RTYPE_FPU | 5}, \
1603 {"$f6", RTYPE_FPU | 6}, \
1604 {"$f7", RTYPE_FPU | 7}, \
1605 {"$f8", RTYPE_FPU | 8}, \
1606 {"$f9", RTYPE_FPU | 9}, \
1607 {"$f10", RTYPE_FPU | 10}, \
1608 {"$f11", RTYPE_FPU | 11}, \
1609 {"$f12", RTYPE_FPU | 12}, \
1610 {"$f13", RTYPE_FPU | 13}, \
1611 {"$f14", RTYPE_FPU | 14}, \
1612 {"$f15", RTYPE_FPU | 15}, \
1613 {"$f16", RTYPE_FPU | 16}, \
1614 {"$f17", RTYPE_FPU | 17}, \
1615 {"$f18", RTYPE_FPU | 18}, \
1616 {"$f19", RTYPE_FPU | 19}, \
1617 {"$f20", RTYPE_FPU | 20}, \
1618 {"$f21", RTYPE_FPU | 21}, \
1619 {"$f22", RTYPE_FPU | 22}, \
1620 {"$f23", RTYPE_FPU | 23}, \
1621 {"$f24", RTYPE_FPU | 24}, \
1622 {"$f25", RTYPE_FPU | 25}, \
1623 {"$f26", RTYPE_FPU | 26}, \
1624 {"$f27", RTYPE_FPU | 27}, \
1625 {"$f28", RTYPE_FPU | 28}, \
1626 {"$f29", RTYPE_FPU | 29}, \
1627 {"$f30", RTYPE_FPU | 30}, \
1628 {"$f31", RTYPE_FPU | 31}
1630 #define FPU_CONDITION_CODE_NAMES \
1631 {"$fcc0", RTYPE_FCC | 0}, \
1632 {"$fcc1", RTYPE_FCC | 1}, \
1633 {"$fcc2", RTYPE_FCC | 2}, \
1634 {"$fcc3", RTYPE_FCC | 3}, \
1635 {"$fcc4", RTYPE_FCC | 4}, \
1636 {"$fcc5", RTYPE_FCC | 5}, \
1637 {"$fcc6", RTYPE_FCC | 6}, \
1638 {"$fcc7", RTYPE_FCC | 7}
1640 #define COPROC_CONDITION_CODE_NAMES \
1641 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1642 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1643 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1644 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1645 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1646 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1647 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1648 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1650 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1651 {"$a4", RTYPE_GP | 8}, \
1652 {"$a5", RTYPE_GP | 9}, \
1653 {"$a6", RTYPE_GP | 10}, \
1654 {"$a7", RTYPE_GP | 11}, \
1655 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1656 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1657 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1658 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1659 {"$t0", RTYPE_GP | 12}, \
1660 {"$t1", RTYPE_GP | 13}, \
1661 {"$t2", RTYPE_GP | 14}, \
1662 {"$t3", RTYPE_GP | 15}
1664 #define O32_SYMBOLIC_REGISTER_NAMES \
1665 {"$t0", RTYPE_GP | 8}, \
1666 {"$t1", RTYPE_GP | 9}, \
1667 {"$t2", RTYPE_GP | 10}, \
1668 {"$t3", RTYPE_GP | 11}, \
1669 {"$t4", RTYPE_GP | 12}, \
1670 {"$t5", RTYPE_GP | 13}, \
1671 {"$t6", RTYPE_GP | 14}, \
1672 {"$t7", RTYPE_GP | 15}, \
1673 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1674 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1675 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1676 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1678 /* Remaining symbolic register names */
1679 #define SYMBOLIC_REGISTER_NAMES \
1680 {"$zero", RTYPE_GP | 0}, \
1681 {"$at", RTYPE_GP | 1}, \
1682 {"$AT", RTYPE_GP | 1}, \
1683 {"$v0", RTYPE_GP | 2}, \
1684 {"$v1", RTYPE_GP | 3}, \
1685 {"$a0", RTYPE_GP | 4}, \
1686 {"$a1", RTYPE_GP | 5}, \
1687 {"$a2", RTYPE_GP | 6}, \
1688 {"$a3", RTYPE_GP | 7}, \
1689 {"$s0", RTYPE_GP | 16}, \
1690 {"$s1", RTYPE_GP | 17}, \
1691 {"$s2", RTYPE_GP | 18}, \
1692 {"$s3", RTYPE_GP | 19}, \
1693 {"$s4", RTYPE_GP | 20}, \
1694 {"$s5", RTYPE_GP | 21}, \
1695 {"$s6", RTYPE_GP | 22}, \
1696 {"$s7", RTYPE_GP | 23}, \
1697 {"$t8", RTYPE_GP | 24}, \
1698 {"$t9", RTYPE_GP | 25}, \
1699 {"$k0", RTYPE_GP | 26}, \
1700 {"$kt0", RTYPE_GP | 26}, \
1701 {"$k1", RTYPE_GP | 27}, \
1702 {"$kt1", RTYPE_GP | 27}, \
1703 {"$gp", RTYPE_GP | 28}, \
1704 {"$sp", RTYPE_GP | 29}, \
1705 {"$s8", RTYPE_GP | 30}, \
1706 {"$fp", RTYPE_GP | 30}, \
1707 {"$ra", RTYPE_GP | 31}
1709 #define MIPS16_SPECIAL_REGISTER_NAMES \
1710 {"$pc", RTYPE_PC | 0}
1712 #define MDMX_VECTOR_REGISTER_NAMES \
1713 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1714 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1715 {"$v2", RTYPE_VEC | 2}, \
1716 {"$v3", RTYPE_VEC | 3}, \
1717 {"$v4", RTYPE_VEC | 4}, \
1718 {"$v5", RTYPE_VEC | 5}, \
1719 {"$v6", RTYPE_VEC | 6}, \
1720 {"$v7", RTYPE_VEC | 7}, \
1721 {"$v8", RTYPE_VEC | 8}, \
1722 {"$v9", RTYPE_VEC | 9}, \
1723 {"$v10", RTYPE_VEC | 10}, \
1724 {"$v11", RTYPE_VEC | 11}, \
1725 {"$v12", RTYPE_VEC | 12}, \
1726 {"$v13", RTYPE_VEC | 13}, \
1727 {"$v14", RTYPE_VEC | 14}, \
1728 {"$v15", RTYPE_VEC | 15}, \
1729 {"$v16", RTYPE_VEC | 16}, \
1730 {"$v17", RTYPE_VEC | 17}, \
1731 {"$v18", RTYPE_VEC | 18}, \
1732 {"$v19", RTYPE_VEC | 19}, \
1733 {"$v20", RTYPE_VEC | 20}, \
1734 {"$v21", RTYPE_VEC | 21}, \
1735 {"$v22", RTYPE_VEC | 22}, \
1736 {"$v23", RTYPE_VEC | 23}, \
1737 {"$v24", RTYPE_VEC | 24}, \
1738 {"$v25", RTYPE_VEC | 25}, \
1739 {"$v26", RTYPE_VEC | 26}, \
1740 {"$v27", RTYPE_VEC | 27}, \
1741 {"$v28", RTYPE_VEC | 28}, \
1742 {"$v29", RTYPE_VEC | 29}, \
1743 {"$v30", RTYPE_VEC | 30}, \
1744 {"$v31", RTYPE_VEC | 31}
1746 #define MIPS_DSP_ACCUMULATOR_NAMES \
1747 {"$ac0", RTYPE_ACC | 0}, \
1748 {"$ac1", RTYPE_ACC | 1}, \
1749 {"$ac2", RTYPE_ACC | 2}, \
1750 {"$ac3", RTYPE_ACC | 3}
1752 static const struct regname reg_names
[] = {
1753 GENERIC_REGISTER_NUMBERS
,
1755 FPU_CONDITION_CODE_NAMES
,
1756 COPROC_CONDITION_CODE_NAMES
,
1758 /* The $txx registers depends on the abi,
1759 these will be added later into the symbol table from
1760 one of the tables below once mips_abi is set after
1761 parsing of arguments from the command line. */
1762 SYMBOLIC_REGISTER_NAMES
,
1764 MIPS16_SPECIAL_REGISTER_NAMES
,
1765 MDMX_VECTOR_REGISTER_NAMES
,
1766 MIPS_DSP_ACCUMULATOR_NAMES
,
1770 static const struct regname reg_names_o32
[] = {
1771 O32_SYMBOLIC_REGISTER_NAMES
,
1775 static const struct regname reg_names_n32n64
[] = {
1776 N32N64_SYMBOLIC_REGISTER_NAMES
,
1781 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1788 /* Find end of name. */
1790 if (is_name_beginner (*e
))
1792 while (is_part_of_name (*e
))
1795 /* Terminate name. */
1799 /* Look for a register symbol. */
1800 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1802 int r
= S_GET_VALUE (symbolP
);
1804 reg
= r
& RNUM_MASK
;
1805 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1806 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1807 reg
= (r
& RNUM_MASK
) - 2;
1809 /* Else see if this is a register defined in an itbl entry. */
1810 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1817 if (itbl_get_reg_val (n
, &r
))
1818 reg
= r
& RNUM_MASK
;
1821 /* Advance to next token if a register was recognised. */
1824 else if (types
& RWARN
)
1825 as_warn (_("Unrecognized register name `%s'"), *s
);
1833 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1834 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1837 is_opcode_valid (const struct mips_opcode
*mo
)
1839 int isa
= mips_opts
.isa
;
1842 if (mips_opts
.ase_mdmx
)
1844 if (mips_opts
.ase_dsp
)
1846 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1848 if (mips_opts
.ase_dspr2
)
1850 if (mips_opts
.ase_mt
)
1852 if (mips_opts
.ase_mips3d
)
1854 if (mips_opts
.ase_smartmips
)
1855 isa
|= INSN_SMARTMIPS
;
1857 /* Don't accept instructions based on the ISA if the CPU does not implement
1858 all the coprocessor insns. */
1859 if (NO_ISA_COP (mips_opts
.arch
)
1860 && COP_INSN (mo
->pinfo
))
1863 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1866 /* Check whether the instruction or macro requires single-precision or
1867 double-precision floating-point support. Note that this information is
1868 stored differently in the opcode table for insns and macros. */
1869 if (mo
->pinfo
== INSN_MACRO
)
1871 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1872 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1876 fp_s
= mo
->pinfo
& FP_S
;
1877 fp_d
= mo
->pinfo
& FP_D
;
1880 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1883 if (fp_s
&& mips_opts
.soft_float
)
1889 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1890 selected ISA and architecture. */
1893 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1895 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1898 /* This function is called once, at assembler startup time. It should set up
1899 all the tables, etc. that the MD part of the assembler will need. */
1904 const char *retval
= NULL
;
1908 if (mips_pic
!= NO_PIC
)
1910 if (g_switch_seen
&& g_switch_value
!= 0)
1911 as_bad (_("-G may not be used in position-independent code"));
1915 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1916 as_warn (_("Could not set architecture and machine"));
1918 op_hash
= hash_new ();
1920 for (i
= 0; i
< NUMOPCODES
;)
1922 const char *name
= mips_opcodes
[i
].name
;
1924 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1927 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1928 mips_opcodes
[i
].name
, retval
);
1929 /* Probably a memory allocation problem? Give up now. */
1930 as_fatal (_("Broken assembler. No assembly attempted."));
1934 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1936 if (!validate_mips_insn (&mips_opcodes
[i
]))
1938 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1940 create_insn (&nop_insn
, mips_opcodes
+ i
);
1941 if (mips_fix_loongson2f_nop
)
1942 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
1943 nop_insn
.fixed_p
= 1;
1948 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1951 mips16_op_hash
= hash_new ();
1954 while (i
< bfd_mips16_num_opcodes
)
1956 const char *name
= mips16_opcodes
[i
].name
;
1958 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1960 as_fatal (_("internal: can't hash `%s': %s"),
1961 mips16_opcodes
[i
].name
, retval
);
1964 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1965 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1966 != mips16_opcodes
[i
].match
))
1968 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1969 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1972 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1974 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1975 mips16_nop_insn
.fixed_p
= 1;
1979 while (i
< bfd_mips16_num_opcodes
1980 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1984 as_fatal (_("Broken assembler. No assembly attempted."));
1986 /* We add all the general register names to the symbol table. This
1987 helps us detect invalid uses of them. */
1988 for (i
= 0; reg_names
[i
].name
; i
++)
1989 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1990 reg_names
[i
].num
, /* & RNUM_MASK, */
1991 &zero_address_frag
));
1993 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1994 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1995 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
1996 &zero_address_frag
));
1998 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1999 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2000 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2001 &zero_address_frag
));
2003 mips_no_prev_insn ();
2006 mips_cprmask
[0] = 0;
2007 mips_cprmask
[1] = 0;
2008 mips_cprmask
[2] = 0;
2009 mips_cprmask
[3] = 0;
2011 /* set the default alignment for the text section (2**2) */
2012 record_alignment (text_section
, 2);
2014 bfd_set_gp_size (stdoutput
, g_switch_value
);
2019 /* On a native system other than VxWorks, sections must be aligned
2020 to 16 byte boundaries. When configured for an embedded ELF
2021 target, we don't bother. */
2022 if (strncmp (TARGET_OS
, "elf", 3) != 0
2023 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2025 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2026 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2027 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2030 /* Create a .reginfo section for register masks and a .mdebug
2031 section for debugging information. */
2039 subseg
= now_subseg
;
2041 /* The ABI says this section should be loaded so that the
2042 running program can access it. However, we don't load it
2043 if we are configured for an embedded target */
2044 flags
= SEC_READONLY
| SEC_DATA
;
2045 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2046 flags
|= SEC_ALLOC
| SEC_LOAD
;
2048 if (mips_abi
!= N64_ABI
)
2050 sec
= subseg_new (".reginfo", (subsegT
) 0);
2052 bfd_set_section_flags (stdoutput
, sec
, flags
);
2053 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2055 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2059 /* The 64-bit ABI uses a .MIPS.options section rather than
2060 .reginfo section. */
2061 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2062 bfd_set_section_flags (stdoutput
, sec
, flags
);
2063 bfd_set_section_alignment (stdoutput
, sec
, 3);
2065 /* Set up the option header. */
2067 Elf_Internal_Options opthdr
;
2070 opthdr
.kind
= ODK_REGINFO
;
2071 opthdr
.size
= (sizeof (Elf_External_Options
)
2072 + sizeof (Elf64_External_RegInfo
));
2075 f
= frag_more (sizeof (Elf_External_Options
));
2076 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2077 (Elf_External_Options
*) f
);
2079 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2083 if (ECOFF_DEBUGGING
)
2085 sec
= subseg_new (".mdebug", (subsegT
) 0);
2086 (void) bfd_set_section_flags (stdoutput
, sec
,
2087 SEC_HAS_CONTENTS
| SEC_READONLY
);
2088 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2090 else if (mips_flag_pdr
)
2092 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2093 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2094 SEC_READONLY
| SEC_RELOC
2096 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2099 subseg_set (seg
, subseg
);
2102 #endif /* OBJ_ELF */
2104 if (! ECOFF_DEBUGGING
)
2107 if (mips_fix_vr4120
)
2108 init_vr4120_conflicts ();
2114 mips_emit_delays ();
2115 if (! ECOFF_DEBUGGING
)
2120 md_assemble (char *str
)
2122 struct mips_cl_insn insn
;
2123 bfd_reloc_code_real_type unused_reloc
[3]
2124 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2126 imm_expr
.X_op
= O_absent
;
2127 imm2_expr
.X_op
= O_absent
;
2128 offset_expr
.X_op
= O_absent
;
2129 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2130 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2131 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2132 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2133 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2134 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2136 if (mips_opts
.mips16
)
2137 mips16_ip (str
, &insn
);
2140 mips_ip (str
, &insn
);
2141 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2142 str
, insn
.insn_opcode
));
2147 as_bad ("%s `%s'", insn_error
, str
);
2151 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2154 if (mips_opts
.mips16
)
2155 mips16_macro (&insn
);
2162 if (imm_expr
.X_op
!= O_absent
)
2163 append_insn (&insn
, &imm_expr
, imm_reloc
);
2164 else if (offset_expr
.X_op
!= O_absent
)
2165 append_insn (&insn
, &offset_expr
, offset_reloc
);
2167 append_insn (&insn
, NULL
, unused_reloc
);
2171 /* Convenience functions for abstracting away the differences between
2172 MIPS16 and non-MIPS16 relocations. */
2174 static inline bfd_boolean
2175 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2179 case BFD_RELOC_MIPS16_JMP
:
2180 case BFD_RELOC_MIPS16_GPREL
:
2181 case BFD_RELOC_MIPS16_GOT16
:
2182 case BFD_RELOC_MIPS16_CALL16
:
2183 case BFD_RELOC_MIPS16_HI16_S
:
2184 case BFD_RELOC_MIPS16_HI16
:
2185 case BFD_RELOC_MIPS16_LO16
:
2193 static inline bfd_boolean
2194 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2196 return reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
;
2199 static inline bfd_boolean
2200 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2202 return reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
;
2205 static inline bfd_boolean
2206 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2208 return reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
;
2211 /* Return true if the given relocation might need a matching %lo().
2212 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2213 need a matching %lo() when applied to local symbols. */
2215 static inline bfd_boolean
2216 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2218 return (HAVE_IN_PLACE_ADDENDS
2219 && (hi16_reloc_p (reloc
)
2220 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2221 all GOT16 relocations evaluate to "G". */
2222 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2225 /* Return the type of %lo() reloc needed by RELOC, given that
2226 reloc_needs_lo_p. */
2228 static inline bfd_reloc_code_real_type
2229 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2231 return mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
: BFD_RELOC_LO16
;
2234 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2237 static inline bfd_boolean
2238 fixup_has_matching_lo_p (fixS
*fixp
)
2240 return (fixp
->fx_next
!= NULL
2241 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2242 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2243 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2246 /* See whether instruction IP reads register REG. CLASS is the type
2250 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2251 enum mips_regclass regclass
)
2253 if (regclass
== MIPS16_REG
)
2255 gas_assert (mips_opts
.mips16
);
2256 reg
= mips16_to_32_reg_map
[reg
];
2257 regclass
= MIPS_GR_REG
;
2260 /* Don't report on general register ZERO, since it never changes. */
2261 if (regclass
== MIPS_GR_REG
&& reg
== ZERO
)
2264 if (regclass
== MIPS_FP_REG
)
2266 gas_assert (! mips_opts
.mips16
);
2267 /* If we are called with either $f0 or $f1, we must check $f0.
2268 This is not optimal, because it will introduce an unnecessary
2269 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2270 need to distinguish reading both $f0 and $f1 or just one of
2271 them. Note that we don't have to check the other way,
2272 because there is no instruction that sets both $f0 and $f1
2273 and requires a delay. */
2274 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2275 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2276 == (reg
&~ (unsigned) 1)))
2278 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2279 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2280 == (reg
&~ (unsigned) 1)))
2282 if ((ip
->insn_mo
->pinfo2
& INSN2_READ_FPR_Z
)
2283 && ((EXTRACT_OPERAND (FZ
, *ip
) & ~(unsigned) 1)
2284 == (reg
&~ (unsigned) 1)))
2287 else if (! mips_opts
.mips16
)
2289 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2290 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2292 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2293 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2295 if ((ip
->insn_mo
->pinfo2
& INSN2_READ_GPR_D
)
2296 && EXTRACT_OPERAND (RD
, *ip
) == reg
)
2298 if ((ip
->insn_mo
->pinfo2
& INSN2_READ_GPR_Z
)
2299 && EXTRACT_OPERAND (RZ
, *ip
) == reg
)
2304 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2305 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2307 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2308 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2310 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2311 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2314 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2316 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2318 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2320 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2321 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2328 /* This function returns true if modifying a register requires a
2332 reg_needs_delay (unsigned int reg
)
2334 unsigned long prev_pinfo
;
2336 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2337 if (! mips_opts
.noreorder
2338 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2339 && ! gpr_interlocks
)
2340 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2341 && ! cop_interlocks
)))
2343 /* A load from a coprocessor or from memory. All load delays
2344 delay the use of general register rt for one instruction. */
2345 /* Itbl support may require additional care here. */
2346 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2347 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2354 /* Move all labels in insn_labels to the current insertion point. */
2357 mips_move_labels (void)
2359 segment_info_type
*si
= seg_info (now_seg
);
2360 struct insn_label_list
*l
;
2363 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2365 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2366 symbol_set_frag (l
->label
, frag_now
);
2367 val
= (valueT
) frag_now_fix ();
2368 /* mips16 text labels are stored as odd. */
2369 if (mips_opts
.mips16
)
2371 S_SET_VALUE (l
->label
, val
);
2376 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2378 bfd_boolean linkonce
= FALSE
;
2379 segT symseg
= S_GET_SEGMENT (sym
);
2381 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2383 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2386 /* The GNU toolchain uses an extension for ELF: a section
2387 beginning with the magic string .gnu.linkonce is a
2388 linkonce section. */
2389 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2390 sizeof ".gnu.linkonce" - 1) == 0)
2397 /* Mark instruction labels in mips16 mode. This permits the linker to
2398 handle them specially, such as generating jalx instructions when
2399 needed. We also make them odd for the duration of the assembly, in
2400 order to generate the right sort of code. We will make them even
2401 in the adjust_symtab routine, while leaving them marked. This is
2402 convenient for the debugger and the disassembler. The linker knows
2403 to make them odd again. */
2406 mips16_mark_labels (void)
2408 segment_info_type
*si
= seg_info (now_seg
);
2409 struct insn_label_list
*l
;
2411 if (!mips_opts
.mips16
)
2414 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2416 symbolS
*label
= l
->label
;
2418 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2420 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2422 if ((S_GET_VALUE (label
) & 1) == 0
2423 /* Don't adjust the address if the label is global or weak, or
2424 in a link-once section, since we'll be emitting symbol reloc
2425 references to it which will be patched up by the linker, and
2426 the final value of the symbol may or may not be MIPS16. */
2427 && ! S_IS_WEAK (label
)
2428 && ! S_IS_EXTERNAL (label
)
2429 && ! s_is_linkonce (label
, now_seg
))
2430 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2434 /* End the current frag. Make it a variant frag and record the
2438 relax_close_frag (void)
2440 mips_macro_warning
.first_frag
= frag_now
;
2441 frag_var (rs_machine_dependent
, 0, 0,
2442 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2443 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2445 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2446 mips_relax
.first_fixup
= 0;
2449 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2450 See the comment above RELAX_ENCODE for more details. */
2453 relax_start (symbolS
*symbol
)
2455 gas_assert (mips_relax
.sequence
== 0);
2456 mips_relax
.sequence
= 1;
2457 mips_relax
.symbol
= symbol
;
2460 /* Start generating the second version of a relaxable sequence.
2461 See the comment above RELAX_ENCODE for more details. */
2466 gas_assert (mips_relax
.sequence
== 1);
2467 mips_relax
.sequence
= 2;
2470 /* End the current relaxable sequence. */
2475 gas_assert (mips_relax
.sequence
== 2);
2476 relax_close_frag ();
2477 mips_relax
.sequence
= 0;
2480 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2481 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2482 by VR4120 errata. */
2485 classify_vr4120_insn (const char *name
)
2487 if (strncmp (name
, "macc", 4) == 0)
2488 return FIX_VR4120_MACC
;
2489 if (strncmp (name
, "dmacc", 5) == 0)
2490 return FIX_VR4120_DMACC
;
2491 if (strncmp (name
, "mult", 4) == 0)
2492 return FIX_VR4120_MULT
;
2493 if (strncmp (name
, "dmult", 5) == 0)
2494 return FIX_VR4120_DMULT
;
2495 if (strstr (name
, "div"))
2496 return FIX_VR4120_DIV
;
2497 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2498 return FIX_VR4120_MTHILO
;
2499 return NUM_FIX_VR4120_CLASSES
;
2502 #define INSN_ERET 0x42000018
2503 #define INSN_DERET 0x4200001f
2505 /* Return the number of instructions that must separate INSN1 and INSN2,
2506 where INSN1 is the earlier instruction. Return the worst-case value
2507 for any INSN2 if INSN2 is null. */
2510 insns_between (const struct mips_cl_insn
*insn1
,
2511 const struct mips_cl_insn
*insn2
)
2513 unsigned long pinfo1
, pinfo2
;
2515 /* This function needs to know which pinfo flags are set for INSN2
2516 and which registers INSN2 uses. The former is stored in PINFO2 and
2517 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2518 will have every flag set and INSN2_USES_REG will always return true. */
2519 pinfo1
= insn1
->insn_mo
->pinfo
;
2520 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2522 #define INSN2_USES_REG(REG, CLASS) \
2523 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2525 /* For most targets, write-after-read dependencies on the HI and LO
2526 registers must be separated by at least two instructions. */
2527 if (!hilo_interlocks
)
2529 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2531 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2535 /* If we're working around r7000 errata, there must be two instructions
2536 between an mfhi or mflo and any instruction that uses the result. */
2537 if (mips_7000_hilo_fix
2538 && MF_HILO_INSN (pinfo1
)
2539 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2542 /* If we're working around 24K errata, one instruction is required
2543 if an ERET or DERET is followed by a branch instruction. */
2546 if (insn1
->insn_opcode
== INSN_ERET
2547 || insn1
->insn_opcode
== INSN_DERET
)
2550 || insn2
->insn_opcode
== INSN_ERET
2551 || insn2
->insn_opcode
== INSN_DERET
2552 || (insn2
->insn_mo
->pinfo
2553 & (INSN_UNCOND_BRANCH_DELAY
2554 | INSN_COND_BRANCH_DELAY
2555 | INSN_COND_BRANCH_LIKELY
)) != 0)
2560 /* If working around VR4120 errata, check for combinations that need
2561 a single intervening instruction. */
2562 if (mips_fix_vr4120
)
2564 unsigned int class1
, class2
;
2566 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2567 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2571 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2572 if (vr4120_conflicts
[class1
] & (1 << class2
))
2577 if (!mips_opts
.mips16
)
2579 /* Check for GPR or coprocessor load delays. All such delays
2580 are on the RT register. */
2581 /* Itbl support may require additional care here. */
2582 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2583 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2585 know (pinfo1
& INSN_WRITE_GPR_T
);
2586 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2590 /* Check for generic coprocessor hazards.
2592 This case is not handled very well. There is no special
2593 knowledge of CP0 handling, and the coprocessors other than
2594 the floating point unit are not distinguished at all. */
2595 /* Itbl support may require additional care here. FIXME!
2596 Need to modify this to include knowledge about
2597 user specified delays! */
2598 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2599 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2601 /* Handle cases where INSN1 writes to a known general coprocessor
2602 register. There must be a one instruction delay before INSN2
2603 if INSN2 reads that register, otherwise no delay is needed. */
2604 if (pinfo1
& INSN_WRITE_FPR_T
)
2606 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2609 else if (pinfo1
& INSN_WRITE_FPR_S
)
2611 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2616 /* Read-after-write dependencies on the control registers
2617 require a two-instruction gap. */
2618 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2619 && (pinfo2
& INSN_READ_COND_CODE
))
2622 /* We don't know exactly what INSN1 does. If INSN2 is
2623 also a coprocessor instruction, assume there must be
2624 a one instruction gap. */
2625 if (pinfo2
& INSN_COP
)
2630 /* Check for read-after-write dependencies on the coprocessor
2631 control registers in cases where INSN1 does not need a general
2632 coprocessor delay. This means that INSN1 is a floating point
2633 comparison instruction. */
2634 /* Itbl support may require additional care here. */
2635 else if (!cop_interlocks
2636 && (pinfo1
& INSN_WRITE_COND_CODE
)
2637 && (pinfo2
& INSN_READ_COND_CODE
))
2641 #undef INSN2_USES_REG
2646 /* Return the number of nops that would be needed to work around the
2647 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2648 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2649 that are contained within the first IGNORE instructions of HIST. */
2652 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
2653 const struct mips_cl_insn
*insn
)
2657 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2658 are not affected by the errata. */
2660 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2661 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2662 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2665 /* Search for the first MFLO or MFHI. */
2666 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2667 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
2669 /* Extract the destination register. */
2670 if (mips_opts
.mips16
)
2671 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, hist
[i
])];
2673 reg
= EXTRACT_OPERAND (RD
, hist
[i
]);
2675 /* No nops are needed if INSN reads that register. */
2676 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2679 /* ...or if any of the intervening instructions do. */
2680 for (j
= 0; j
< i
; j
++)
2681 if (insn_uses_reg (&hist
[j
], reg
, MIPS_GR_REG
))
2685 return MAX_VR4130_NOPS
- i
;
2690 #define BASE_REG_EQ(INSN1, INSN2) \
2691 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2692 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2694 /* Return the minimum alignment for this store instruction. */
2697 fix_24k_align_to (const struct mips_opcode
*mo
)
2699 if (strcmp (mo
->name
, "sh") == 0)
2702 if (strcmp (mo
->name
, "swc1") == 0
2703 || strcmp (mo
->name
, "swc2") == 0
2704 || strcmp (mo
->name
, "sw") == 0
2705 || strcmp (mo
->name
, "sc") == 0
2706 || strcmp (mo
->name
, "s.s") == 0)
2709 if (strcmp (mo
->name
, "sdc1") == 0
2710 || strcmp (mo
->name
, "sdc2") == 0
2711 || strcmp (mo
->name
, "s.d") == 0)
2718 struct fix_24k_store_info
2720 /* Immediate offset, if any, for this store instruction. */
2722 /* Alignment required by this store instruction. */
2724 /* True for register offsets. */
2725 int register_offset
;
2728 /* Comparison function used by qsort. */
2731 fix_24k_sort (const void *a
, const void *b
)
2733 const struct fix_24k_store_info
*pos1
= a
;
2734 const struct fix_24k_store_info
*pos2
= b
;
2736 return (pos1
->off
- pos2
->off
);
2739 /* INSN is a store instruction. Try to record the store information
2740 in STINFO. Return false if the information isn't known. */
2743 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
2744 const struct mips_cl_insn
*insn
)
2746 /* The instruction must have a known offset. */
2747 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
2750 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
2751 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
2755 /* Return the number of nops that would be needed to work around the 24k
2756 "lost data on stores during refill" errata if instruction INSN
2757 immediately followed the 2 instructions described by HIST.
2758 Ignore hazards that are contained within the first IGNORE
2759 instructions of HIST.
2761 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2762 for the data cache refills and store data. The following describes
2763 the scenario where the store data could be lost.
2765 * A data cache miss, due to either a load or a store, causing fill
2766 data to be supplied by the memory subsystem
2767 * The first three doublewords of fill data are returned and written
2769 * A sequence of four stores occurs in consecutive cycles around the
2770 final doubleword of the fill:
2774 * Zero, One or more instructions
2777 The four stores A-D must be to different doublewords of the line that
2778 is being filled. The fourth instruction in the sequence above permits
2779 the fill of the final doubleword to be transferred from the FSB into
2780 the cache. In the sequence above, the stores may be either integer
2781 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2782 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2783 different doublewords on the line. If the floating point unit is
2784 running in 1:2 mode, it is not possible to create the sequence above
2785 using only floating point store instructions.
2787 In this case, the cache line being filled is incorrectly marked
2788 invalid, thereby losing the data from any store to the line that
2789 occurs between the original miss and the completion of the five
2790 cycle sequence shown above.
2792 The workarounds are:
2794 * Run the data cache in write-through mode.
2795 * Insert a non-store instruction between
2796 Store A and Store B or Store B and Store C. */
2799 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
2800 const struct mips_cl_insn
*insn
)
2802 struct fix_24k_store_info pos
[3];
2803 int align
, i
, base_offset
;
2808 /* If the previous instruction wasn't a store, there's nothing to
2810 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
2813 /* If the instructions after the previous one are unknown, we have
2814 to assume the worst. */
2818 /* Check whether we are dealing with three consecutive stores. */
2819 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
2820 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
2823 /* If we don't know the relationship between the store addresses,
2824 assume the worst. */
2825 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
2826 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
2829 if (!fix_24k_record_store_info (&pos
[0], insn
)
2830 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
2831 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
2834 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
2836 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2837 X bytes and such that the base register + X is known to be aligned
2840 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
2844 align
= pos
[0].align_to
;
2845 base_offset
= pos
[0].off
;
2846 for (i
= 1; i
< 3; i
++)
2847 if (align
< pos
[i
].align_to
)
2849 align
= pos
[i
].align_to
;
2850 base_offset
= pos
[i
].off
;
2852 for (i
= 0; i
< 3; i
++)
2853 pos
[i
].off
-= base_offset
;
2856 pos
[0].off
&= ~align
+ 1;
2857 pos
[1].off
&= ~align
+ 1;
2858 pos
[2].off
&= ~align
+ 1;
2860 /* If any two stores write to the same chunk, they also write to the
2861 same doubleword. The offsets are still sorted at this point. */
2862 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
2865 /* A range of at least 9 bytes is needed for the stores to be in
2866 non-overlapping doublewords. */
2867 if (pos
[2].off
- pos
[0].off
<= 8)
2870 if (pos
[2].off
- pos
[1].off
>= 24
2871 || pos
[1].off
- pos
[0].off
>= 24
2872 || pos
[2].off
- pos
[0].off
>= 32)
2878 /* Return the number of nops that would be needed if instruction INSN
2879 immediately followed the MAX_NOPS instructions given by HIST,
2880 where HIST[0] is the most recent instruction. Ignore hazards
2881 between INSN and the first IGNORE instructions in HIST.
2883 If INSN is null, return the worse-case number of nops for any
2887 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
2888 const struct mips_cl_insn
*insn
)
2890 int i
, nops
, tmp_nops
;
2893 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
2895 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
2896 if (tmp_nops
> nops
)
2900 if (mips_fix_vr4130
)
2902 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
2903 if (tmp_nops
> nops
)
2909 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
2910 if (tmp_nops
> nops
)
2917 /* The variable arguments provide NUM_INSNS extra instructions that
2918 might be added to HIST. Return the largest number of nops that
2919 would be needed after the extended sequence, ignoring hazards
2920 in the first IGNORE instructions. */
2923 nops_for_sequence (int num_insns
, int ignore
,
2924 const struct mips_cl_insn
*hist
, ...)
2927 struct mips_cl_insn buffer
[MAX_NOPS
];
2928 struct mips_cl_insn
*cursor
;
2931 va_start (args
, hist
);
2932 cursor
= buffer
+ num_insns
;
2933 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2934 while (cursor
> buffer
)
2935 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2937 nops
= nops_for_insn (ignore
, buffer
, NULL
);
2942 /* Like nops_for_insn, but if INSN is a branch, take into account the
2943 worst-case delay for the branch target. */
2946 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
2947 const struct mips_cl_insn
*insn
)
2951 nops
= nops_for_insn (ignore
, hist
, insn
);
2952 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2953 | INSN_COND_BRANCH_DELAY
2954 | INSN_COND_BRANCH_LIKELY
))
2956 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
2957 hist
, insn
, NOP_INSN
);
2958 if (tmp_nops
> nops
)
2961 else if (mips_opts
.mips16
2962 && (insn
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2963 | MIPS16_INSN_COND_BRANCH
)))
2965 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
2966 if (tmp_nops
> nops
)
2972 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2975 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
2977 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
2978 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
2981 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2982 jr target pc &= 'hffff_ffff_cfff_ffff. */
2985 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
2987 if (strcmp (ip
->insn_mo
->name
, "j") == 0
2988 || strcmp (ip
->insn_mo
->name
, "jr") == 0
2989 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
2997 sreg
= EXTRACT_OPERAND (RS
, *ip
);
2998 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3001 ep
.X_op
= O_constant
;
3002 ep
.X_add_number
= 0xcfff0000;
3003 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3004 ep
.X_add_number
= 0xffff;
3005 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3006 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3011 fix_loongson2f (struct mips_cl_insn
* ip
)
3013 if (mips_fix_loongson2f_nop
)
3014 fix_loongson2f_nop (ip
);
3016 if (mips_fix_loongson2f_jump
)
3017 fix_loongson2f_jump (ip
);
3020 /* Output an instruction. IP is the instruction information.
3021 ADDRESS_EXPR is an operand of the instruction to be used with
3025 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3026 bfd_reloc_code_real_type
*reloc_type
)
3028 unsigned long prev_pinfo
, pinfo
;
3029 unsigned long prev_pinfo2
, pinfo2
;
3030 relax_stateT prev_insn_frag_type
= 0;
3031 bfd_boolean relaxed_branch
= FALSE
;
3032 segment_info_type
*si
= seg_info (now_seg
);
3034 if (mips_fix_loongson2f
)
3035 fix_loongson2f (ip
);
3037 /* Mark instruction labels in mips16 mode. */
3038 mips16_mark_labels ();
3040 file_ase_mips16
|= mips_opts
.mips16
;
3042 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3043 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3044 pinfo
= ip
->insn_mo
->pinfo
;
3045 pinfo2
= ip
->insn_mo
->pinfo2
;
3047 if (address_expr
== NULL
)
3049 else if (*reloc_type
<= BFD_RELOC_UNUSED
3050 && address_expr
->X_op
== O_constant
)
3055 switch (*reloc_type
)
3058 ip
->insn_opcode
|= address_expr
->X_add_number
;
3061 case BFD_RELOC_MIPS_HIGHEST
:
3062 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
3063 ip
->insn_opcode
|= tmp
& 0xffff;
3066 case BFD_RELOC_MIPS_HIGHER
:
3067 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
3068 ip
->insn_opcode
|= tmp
& 0xffff;
3071 case BFD_RELOC_HI16_S
:
3072 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
3073 ip
->insn_opcode
|= tmp
& 0xffff;
3076 case BFD_RELOC_HI16
:
3077 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
3080 case BFD_RELOC_UNUSED
:
3081 case BFD_RELOC_LO16
:
3082 case BFD_RELOC_MIPS_GOT_DISP
:
3083 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
3086 case BFD_RELOC_MIPS_JMP
:
3087 if ((address_expr
->X_add_number
& 3) != 0)
3088 as_bad (_("jump to misaligned address (0x%lx)"),
3089 (unsigned long) address_expr
->X_add_number
);
3090 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
3094 case BFD_RELOC_MIPS16_JMP
:
3095 if ((address_expr
->X_add_number
& 3) != 0)
3096 as_bad (_("jump to misaligned address (0x%lx)"),
3097 (unsigned long) address_expr
->X_add_number
);
3099 (((address_expr
->X_add_number
& 0x7c0000) << 3)
3100 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
3101 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
3105 case BFD_RELOC_16_PCREL_S2
:
3106 if ((address_expr
->X_add_number
& 3) != 0)
3107 as_bad (_("branch to misaligned address (0x%lx)"),
3108 (unsigned long) address_expr
->X_add_number
);
3109 if (mips_relax_branch
)
3111 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
3112 as_bad (_("branch address range overflow (0x%lx)"),
3113 (unsigned long) address_expr
->X_add_number
);
3114 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
3123 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3125 /* There are a lot of optimizations we could do that we don't.
3126 In particular, we do not, in general, reorder instructions.
3127 If you use gcc with optimization, it will reorder
3128 instructions and generally do much more optimization then we
3129 do here; repeating all that work in the assembler would only
3130 benefit hand written assembly code, and does not seem worth
3132 int nops
= (mips_optimize
== 0
3133 ? nops_for_insn (0, history
, NULL
)
3134 : nops_for_insn_or_target (0, history
, ip
));
3138 unsigned long old_frag_offset
;
3141 old_frag
= frag_now
;
3142 old_frag_offset
= frag_now_fix ();
3144 for (i
= 0; i
< nops
; i
++)
3149 listing_prev_line ();
3150 /* We may be at the start of a variant frag. In case we
3151 are, make sure there is enough space for the frag
3152 after the frags created by listing_prev_line. The
3153 argument to frag_grow here must be at least as large
3154 as the argument to all other calls to frag_grow in
3155 this file. We don't have to worry about being in the
3156 middle of a variant frag, because the variants insert
3157 all needed nop instructions themselves. */
3161 mips_move_labels ();
3163 #ifndef NO_ECOFF_DEBUGGING
3164 if (ECOFF_DEBUGGING
)
3165 ecoff_fix_loc (old_frag
, old_frag_offset
);
3169 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
3173 /* Work out how many nops in prev_nop_frag are needed by IP,
3174 ignoring hazards generated by the first prev_nop_frag_since
3176 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
3177 gas_assert (nops
<= prev_nop_frag_holds
);
3179 /* Enforce NOPS as a minimum. */
3180 if (nops
> prev_nop_frag_required
)
3181 prev_nop_frag_required
= nops
;
3183 if (prev_nop_frag_holds
== prev_nop_frag_required
)
3185 /* Settle for the current number of nops. Update the history
3186 accordingly (for the benefit of any future .set reorder code). */
3187 prev_nop_frag
= NULL
;
3188 insert_into_history (prev_nop_frag_since
,
3189 prev_nop_frag_holds
, NOP_INSN
);
3193 /* Allow this instruction to replace one of the nops that was
3194 tentatively added to prev_nop_frag. */
3195 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
3196 prev_nop_frag_holds
--;
3197 prev_nop_frag_since
++;
3202 /* The value passed to dwarf2_emit_insn is the distance between
3203 the beginning of the current instruction and the address that
3204 should be recorded in the debug tables. For MIPS16 debug info
3205 we want to use ISA-encoded addresses, so we pass -1 for an
3206 address higher by one than the current. */
3207 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
3210 /* Record the frag type before frag_var. */
3211 if (history
[0].frag
)
3212 prev_insn_frag_type
= history
[0].frag
->fr_type
;
3215 && *reloc_type
== BFD_RELOC_16_PCREL_S2
3216 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
3217 || pinfo
& INSN_COND_BRANCH_LIKELY
)
3218 && mips_relax_branch
3219 /* Don't try branch relaxation within .set nomacro, or within
3220 .set noat if we use $at for PIC computations. If it turns
3221 out that the branch was out-of-range, we'll get an error. */
3222 && !mips_opts
.warn_about_macros
3223 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
3224 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3225 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
))
3226 && !mips_opts
.mips16
)
3228 relaxed_branch
= TRUE
;
3229 add_relaxed_insn (ip
, (relaxed_branch_length
3231 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
3232 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
3236 pinfo
& INSN_UNCOND_BRANCH_DELAY
,
3237 pinfo
& INSN_COND_BRANCH_LIKELY
,
3238 pinfo
& INSN_WRITE_GPR_31
,
3240 address_expr
->X_add_symbol
,
3241 address_expr
->X_add_number
);
3242 *reloc_type
= BFD_RELOC_UNUSED
;
3244 else if (*reloc_type
> BFD_RELOC_UNUSED
)
3246 /* We need to set up a variant frag. */
3247 gas_assert (mips_opts
.mips16
&& address_expr
!= NULL
);
3248 add_relaxed_insn (ip
, 4, 0,
3250 (*reloc_type
- BFD_RELOC_UNUSED
,
3251 mips16_small
, mips16_ext
,
3252 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
3253 history
[0].mips16_absolute_jump_p
),
3254 make_expr_symbol (address_expr
), 0);
3256 else if (mips_opts
.mips16
3258 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
3260 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
3261 /* Make sure there is enough room to swap this instruction with
3262 a following jump instruction. */
3264 add_fixed_insn (ip
);
3268 if (mips_opts
.mips16
3269 && mips_opts
.noreorder
3270 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
3271 as_warn (_("extended instruction in delay slot"));
3273 if (mips_relax
.sequence
)
3275 /* If we've reached the end of this frag, turn it into a variant
3276 frag and record the information for the instructions we've
3278 if (frag_room () < 4)
3279 relax_close_frag ();
3280 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3283 if (mips_relax
.sequence
!= 2)
3284 mips_macro_warning
.sizes
[0] += 4;
3285 if (mips_relax
.sequence
!= 1)
3286 mips_macro_warning
.sizes
[1] += 4;
3288 if (mips_opts
.mips16
)
3291 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
3293 add_fixed_insn (ip
);
3296 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
3299 && *reloc_type
< BFD_RELOC_UNUSED
)
3302 reloc_howto_type
*howto
;
3305 /* In a compound relocation, it is the final (outermost)
3306 operator that determines the relocated field. */
3307 for (i
= 1; i
< 3; i
++)
3308 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
3311 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
3314 /* To reproduce this failure try assembling gas/testsuites/
3315 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3317 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type
[i
- 1]);
3318 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
3321 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
3322 bfd_get_reloc_size (howto
),
3324 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
3327 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3328 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
3329 && ip
->fixp
[0]->fx_addsy
)
3330 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
3332 /* These relocations can have an addend that won't fit in
3333 4 octets for 64bit assembly. */
3335 && ! howto
->partial_inplace
3336 && (reloc_type
[0] == BFD_RELOC_16
3337 || reloc_type
[0] == BFD_RELOC_32
3338 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
3339 || reloc_type
[0] == BFD_RELOC_GPREL16
3340 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
3341 || reloc_type
[0] == BFD_RELOC_GPREL32
3342 || reloc_type
[0] == BFD_RELOC_64
3343 || reloc_type
[0] == BFD_RELOC_CTOR
3344 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
3345 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
3346 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
3347 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
3348 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
3349 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
3350 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
3351 || hi16_reloc_p (reloc_type
[0])
3352 || lo16_reloc_p (reloc_type
[0])))
3353 ip
->fixp
[0]->fx_no_overflow
= 1;
3355 if (mips_relax
.sequence
)
3357 if (mips_relax
.first_fixup
== 0)
3358 mips_relax
.first_fixup
= ip
->fixp
[0];
3360 else if (reloc_needs_lo_p (*reloc_type
))
3362 struct mips_hi_fixup
*hi_fixup
;
3364 /* Reuse the last entry if it already has a matching %lo. */
3365 hi_fixup
= mips_hi_fixup_list
;
3367 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
3369 hi_fixup
= ((struct mips_hi_fixup
*)
3370 xmalloc (sizeof (struct mips_hi_fixup
)));
3371 hi_fixup
->next
= mips_hi_fixup_list
;
3372 mips_hi_fixup_list
= hi_fixup
;
3374 hi_fixup
->fixp
= ip
->fixp
[0];
3375 hi_fixup
->seg
= now_seg
;
3378 /* Add fixups for the second and third relocations, if given.
3379 Note that the ABI allows the second relocation to be
3380 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3381 moment we only use RSS_UNDEF, but we could add support
3382 for the others if it ever becomes necessary. */
3383 for (i
= 1; i
< 3; i
++)
3384 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
3386 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
3387 ip
->fixp
[0]->fx_size
, NULL
, 0,
3388 FALSE
, reloc_type
[i
]);
3390 /* Use fx_tcbit to mark compound relocs. */
3391 ip
->fixp
[0]->fx_tcbit
= 1;
3392 ip
->fixp
[i
]->fx_tcbit
= 1;
3398 /* Update the register mask information. */
3399 if (! mips_opts
.mips16
)
3401 if ((pinfo
& INSN_WRITE_GPR_D
) || (pinfo2
& INSN2_READ_GPR_D
))
3402 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
3403 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
3404 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
3405 if (pinfo
& INSN_READ_GPR_S
)
3406 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
3407 if (pinfo
& INSN_WRITE_GPR_31
)
3408 mips_gprmask
|= 1 << RA
;
3409 if (pinfo2
& (INSN2_WRITE_GPR_Z
| INSN2_READ_GPR_Z
))
3410 mips_gprmask
|= 1 << EXTRACT_OPERAND (RZ
, *ip
);
3411 if (pinfo
& INSN_WRITE_FPR_D
)
3412 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
3413 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
3414 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
3415 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
3416 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
3417 if ((pinfo
& INSN_READ_FPR_R
) != 0)
3418 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
3419 if (pinfo2
& (INSN2_WRITE_FPR_Z
| INSN2_READ_FPR_Z
))
3420 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FZ
, *ip
);
3421 if (pinfo
& INSN_COP
)
3423 /* We don't keep enough information to sort these cases out.
3424 The itbl support does keep this information however, although
3425 we currently don't support itbl fprmats as part of the cop
3426 instruction. May want to add this support in the future. */
3428 /* Never set the bit for $0, which is always zero. */
3429 mips_gprmask
&= ~1 << 0;
3433 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3434 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3435 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3436 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3437 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3438 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3439 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3440 mips_gprmask
|= 1 << TREG
;
3441 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3442 mips_gprmask
|= 1 << SP
;
3443 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3444 mips_gprmask
|= 1 << RA
;
3445 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3446 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3447 if (pinfo
& MIPS16_INSN_READ_Z
)
3448 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3449 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3450 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3453 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3455 /* Filling the branch delay slot is more complex. We try to
3456 switch the branch with the previous instruction, which we can
3457 do if the previous instruction does not set up a condition
3458 that the branch tests and if the branch is not itself the
3459 target of any branch. */
3460 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3461 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3463 if (mips_optimize
< 2
3464 /* If we have seen .set volatile or .set nomove, don't
3466 || mips_opts
.nomove
!= 0
3467 /* We can't swap if the previous instruction's position
3469 || history
[0].fixed_p
3470 /* If the previous previous insn was in a .set
3471 noreorder, we can't swap. Actually, the MIPS
3472 assembler will swap in this situation. However, gcc
3473 configured -with-gnu-as will generate code like
3479 in which we can not swap the bne and INSN. If gcc is
3480 not configured -with-gnu-as, it does not output the
3482 || history
[1].noreorder_p
3483 /* If the branch is itself the target of a branch, we
3484 can not swap. We cheat on this; all we check for is
3485 whether there is a label on this instruction. If
3486 there are any branches to anything other than a
3487 label, users must use .set noreorder. */
3488 || si
->label_list
!= NULL
3489 /* If the previous instruction is in a variant frag
3490 other than this branch's one, we cannot do the swap.
3491 This does not apply to the mips16, which uses variant
3492 frags for different purposes. */
3493 || (! mips_opts
.mips16
3494 && prev_insn_frag_type
== rs_machine_dependent
)
3495 /* Check for conflicts between the branch and the instructions
3496 before the candidate delay slot. */
3497 || nops_for_insn (0, history
+ 1, ip
) > 0
3498 /* Check for conflicts between the swapped sequence and the
3499 target of the branch. */
3500 || nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0
3501 /* We do not swap with a trap instruction, since it
3502 complicates trap handlers to have the trap
3503 instruction be in a delay slot. */
3504 || (prev_pinfo
& INSN_TRAP
)
3505 /* If the branch reads a register that the previous
3506 instruction sets, we can not swap. */
3507 || (! mips_opts
.mips16
3508 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3509 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3511 || (! mips_opts
.mips16
3512 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3513 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3515 || (! mips_opts
.mips16
3516 && (prev_pinfo2
& INSN2_WRITE_GPR_Z
)
3517 && insn_uses_reg (ip
, EXTRACT_OPERAND (RZ
, history
[0]),
3519 || (mips_opts
.mips16
3520 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3522 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3524 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3526 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3528 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3530 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3532 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3533 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3534 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3535 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3536 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3537 && insn_uses_reg (ip
,
3538 MIPS16OP_EXTRACT_REG32R
3539 (history
[0].insn_opcode
),
3541 /* If the branch writes a register that the previous
3542 instruction sets, we can not swap (we know that
3543 branches write only to RD or to $31). */
3544 || (! mips_opts
.mips16
3545 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3546 && (((pinfo
& INSN_WRITE_GPR_D
)
3547 && (EXTRACT_OPERAND (RT
, history
[0])
3548 == EXTRACT_OPERAND (RD
, *ip
)))
3549 || ((pinfo
& INSN_WRITE_GPR_31
)
3550 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3551 || (! mips_opts
.mips16
3552 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3553 && (((pinfo
& INSN_WRITE_GPR_D
)
3554 && (EXTRACT_OPERAND (RD
, history
[0])
3555 == EXTRACT_OPERAND (RD
, *ip
)))
3556 || ((pinfo
& INSN_WRITE_GPR_31
)
3557 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3558 || (mips_opts
.mips16
3559 && (pinfo
& MIPS16_INSN_WRITE_31
)
3560 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3561 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3562 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3564 /* If the branch writes a register that the previous
3565 instruction reads, we can not swap (we know that
3566 branches only write to RD or to $31). */
3567 || (! mips_opts
.mips16
3568 && (pinfo
& INSN_WRITE_GPR_D
)
3569 && insn_uses_reg (&history
[0],
3570 EXTRACT_OPERAND (RD
, *ip
),
3572 || (! mips_opts
.mips16
3573 && (pinfo
& INSN_WRITE_GPR_31
)
3574 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3575 || (mips_opts
.mips16
3576 && (pinfo
& MIPS16_INSN_WRITE_31
)
3577 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3578 /* If one instruction sets a condition code and the
3579 other one uses a condition code, we can not swap. */
3580 || ((pinfo
& INSN_READ_COND_CODE
)
3581 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3582 || ((pinfo
& INSN_WRITE_COND_CODE
)
3583 && (prev_pinfo
& INSN_READ_COND_CODE
))
3584 /* If the previous instruction uses the PC, we can not
3586 || (mips_opts
.mips16
3587 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3588 /* If the previous instruction had a fixup in mips16
3589 mode, we can not swap. This normally means that the
3590 previous instruction was a 4 byte branch anyhow. */
3591 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3592 /* If the previous instruction is a sync, sync.l, or
3593 sync.p, we can not swap. */
3594 || (prev_pinfo
& INSN_SYNC
)
3595 /* If the previous instruction is an ERET or
3596 DERET, avoid the swap. */
3597 || (history
[0].insn_opcode
== INSN_ERET
)
3598 || (history
[0].insn_opcode
== INSN_DERET
))
3600 if (mips_opts
.mips16
3601 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3602 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3603 && ISA_SUPPORTS_MIPS16E
)
3605 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3606 ip
->insn_opcode
|= 0x0080;
3608 insert_into_history (0, 1, ip
);
3612 /* We could do even better for unconditional branches to
3613 portions of this object file; we could pick up the
3614 instruction at the destination, put it in the delay
3615 slot, and bump the destination address. */
3616 insert_into_history (0, 1, ip
);
3620 if (mips_relax
.sequence
)
3621 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3625 /* It looks like we can actually do the swap. */
3626 struct mips_cl_insn delay
= history
[0];
3627 if (mips_opts
.mips16
)
3629 know (delay
.frag
== ip
->frag
);
3630 move_insn (ip
, delay
.frag
, delay
.where
);
3631 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3633 else if (relaxed_branch
)
3635 /* Add the delay slot instruction to the end of the
3636 current frag and shrink the fixed part of the
3637 original frag. If the branch occupies the tail of
3638 the latter, move it backwards to cover the gap. */
3639 delay
.frag
->fr_fix
-= 4;
3640 if (delay
.frag
== ip
->frag
)
3641 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3642 add_fixed_insn (&delay
);
3646 move_insn (&delay
, ip
->frag
, ip
->where
);
3647 move_insn (ip
, history
[0].frag
, history
[0].where
);
3651 insert_into_history (0, 1, &delay
);
3654 /* If that was an unconditional branch, forget the previous
3655 insn information. */
3656 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3658 mips_no_prev_insn ();
3661 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3663 /* We don't yet optimize a branch likely. What we should do
3664 is look at the target, copy the instruction found there
3665 into the delay slot, and increment the branch to jump to
3666 the next instruction. */
3667 insert_into_history (0, 1, ip
);
3671 insert_into_history (0, 1, ip
);
3674 insert_into_history (0, 1, ip
);
3676 /* We just output an insn, so the next one doesn't have a label. */
3677 mips_clear_insn_labels ();
3680 /* Forget that there was any previous instruction or label. */
3683 mips_no_prev_insn (void)
3685 prev_nop_frag
= NULL
;
3686 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3687 mips_clear_insn_labels ();
3690 /* This function must be called before we emit something other than
3691 instructions. It is like mips_no_prev_insn except that it inserts
3692 any NOPS that might be needed by previous instructions. */
3695 mips_emit_delays (void)
3697 if (! mips_opts
.noreorder
)
3699 int nops
= nops_for_insn (0, history
, NULL
);
3703 add_fixed_insn (NOP_INSN
);
3704 mips_move_labels ();
3707 mips_no_prev_insn ();
3710 /* Start a (possibly nested) noreorder block. */
3713 start_noreorder (void)
3715 if (mips_opts
.noreorder
== 0)
3720 /* None of the instructions before the .set noreorder can be moved. */
3721 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3722 history
[i
].fixed_p
= 1;
3724 /* Insert any nops that might be needed between the .set noreorder
3725 block and the previous instructions. We will later remove any
3726 nops that turn out not to be needed. */
3727 nops
= nops_for_insn (0, history
, NULL
);
3730 if (mips_optimize
!= 0)
3732 /* Record the frag which holds the nop instructions, so
3733 that we can remove them if we don't need them. */
3734 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3735 prev_nop_frag
= frag_now
;
3736 prev_nop_frag_holds
= nops
;
3737 prev_nop_frag_required
= 0;
3738 prev_nop_frag_since
= 0;
3741 for (; nops
> 0; --nops
)
3742 add_fixed_insn (NOP_INSN
);
3744 /* Move on to a new frag, so that it is safe to simply
3745 decrease the size of prev_nop_frag. */
3746 frag_wane (frag_now
);
3748 mips_move_labels ();
3750 mips16_mark_labels ();
3751 mips_clear_insn_labels ();
3753 mips_opts
.noreorder
++;
3754 mips_any_noreorder
= 1;
3757 /* End a nested noreorder block. */
3760 end_noreorder (void)
3763 mips_opts
.noreorder
--;
3764 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3766 /* Commit to inserting prev_nop_frag_required nops and go back to
3767 handling nop insertion the .set reorder way. */
3768 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3769 * (mips_opts
.mips16
? 2 : 4));
3770 insert_into_history (prev_nop_frag_since
,
3771 prev_nop_frag_required
, NOP_INSN
);
3772 prev_nop_frag
= NULL
;
3776 /* Set up global variables for the start of a new macro. */
3781 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3782 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3783 && (history
[0].insn_mo
->pinfo
3784 & (INSN_UNCOND_BRANCH_DELAY
3785 | INSN_COND_BRANCH_DELAY
3786 | INSN_COND_BRANCH_LIKELY
)) != 0);
3789 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3790 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3791 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3794 macro_warning (relax_substateT subtype
)
3796 if (subtype
& RELAX_DELAY_SLOT
)
3797 return _("Macro instruction expanded into multiple instructions"
3798 " in a branch delay slot");
3799 else if (subtype
& RELAX_NOMACRO
)
3800 return _("Macro instruction expanded into multiple instructions");
3805 /* Finish up a macro. Emit warnings as appropriate. */
3810 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3812 relax_substateT subtype
;
3814 /* Set up the relaxation warning flags. */
3816 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3817 subtype
|= RELAX_SECOND_LONGER
;
3818 if (mips_opts
.warn_about_macros
)
3819 subtype
|= RELAX_NOMACRO
;
3820 if (mips_macro_warning
.delay_slot_p
)
3821 subtype
|= RELAX_DELAY_SLOT
;
3823 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3825 /* Either the macro has a single implementation or both
3826 implementations are longer than 4 bytes. Emit the
3828 const char *msg
= macro_warning (subtype
);
3830 as_warn ("%s", msg
);
3834 /* One implementation might need a warning but the other
3835 definitely doesn't. */
3836 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3841 /* Read a macro's relocation codes from *ARGS and store them in *R.
3842 The first argument in *ARGS will be either the code for a single
3843 relocation or -1 followed by the three codes that make up a
3844 composite relocation. */
3847 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3851 next
= va_arg (*args
, int);
3853 r
[0] = (bfd_reloc_code_real_type
) next
;
3855 for (i
= 0; i
< 3; i
++)
3856 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3859 /* Build an instruction created by a macro expansion. This is passed
3860 a pointer to the count of instructions created so far, an
3861 expression, the name of the instruction to build, an operand format
3862 string, and corresponding arguments. */
3865 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3867 const struct mips_opcode
*mo
;
3868 struct mips_cl_insn insn
;
3869 bfd_reloc_code_real_type r
[3];
3872 va_start (args
, fmt
);
3874 if (mips_opts
.mips16
)
3876 mips16_macro_build (ep
, name
, fmt
, &args
);
3881 r
[0] = BFD_RELOC_UNUSED
;
3882 r
[1] = BFD_RELOC_UNUSED
;
3883 r
[2] = BFD_RELOC_UNUSED
;
3884 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3886 gas_assert (strcmp (name
, mo
->name
) == 0);
3890 /* Search until we get a match for NAME. It is assumed here that
3891 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3892 if (strcmp (fmt
, mo
->args
) == 0
3893 && mo
->pinfo
!= INSN_MACRO
3894 && is_opcode_valid (mo
))
3898 gas_assert (mo
->name
);
3899 gas_assert (strcmp (name
, mo
->name
) == 0);
3902 create_insn (&insn
, mo
);
3920 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3925 /* Note that in the macro case, these arguments are already
3926 in MSB form. (When handling the instruction in the
3927 non-macro case, these arguments are sizes from which
3928 MSB values must be calculated.) */
3929 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3935 /* Note that in the macro case, these arguments are already
3936 in MSBD form. (When handling the instruction in the
3937 non-macro case, these arguments are sizes from which
3938 MSBD values must be calculated.) */
3939 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3943 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3952 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3958 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3962 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3967 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3973 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3978 int tmp
= va_arg (args
, int);
3980 INSERT_OPERAND (RT
, insn
, tmp
);
3981 INSERT_OPERAND (RD
, insn
, tmp
);
3987 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3994 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3998 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
4002 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
4006 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
4010 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
4017 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
4022 macro_read_relocs (&args
, r
);
4023 gas_assert (*r
== BFD_RELOC_GPREL16
4024 || *r
== BFD_RELOC_MIPS_HIGHER
4025 || *r
== BFD_RELOC_HI16_S
4026 || *r
== BFD_RELOC_LO16
4027 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
4031 macro_read_relocs (&args
, r
);
4035 macro_read_relocs (&args
, r
);
4036 gas_assert (ep
!= NULL
4037 && (ep
->X_op
== O_constant
4038 || (ep
->X_op
== O_symbol
4039 && (*r
== BFD_RELOC_MIPS_HIGHEST
4040 || *r
== BFD_RELOC_HI16_S
4041 || *r
== BFD_RELOC_HI16
4042 || *r
== BFD_RELOC_GPREL16
4043 || *r
== BFD_RELOC_MIPS_GOT_HI16
4044 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
4048 gas_assert (ep
!= NULL
);
4051 * This allows macro() to pass an immediate expression for
4052 * creating short branches without creating a symbol.
4054 * We don't allow branch relaxation for these branches, as
4055 * they should only appear in ".set nomacro" anyway.
4057 if (ep
->X_op
== O_constant
)
4059 if ((ep
->X_add_number
& 3) != 0)
4060 as_bad (_("branch to misaligned address (0x%lx)"),
4061 (unsigned long) ep
->X_add_number
);
4062 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
4063 as_bad (_("branch address range overflow (0x%lx)"),
4064 (unsigned long) ep
->X_add_number
);
4065 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
4069 *r
= BFD_RELOC_16_PCREL_S2
;
4073 gas_assert (ep
!= NULL
);
4074 *r
= BFD_RELOC_MIPS_JMP
;
4078 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
4082 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
4091 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
4093 append_insn (&insn
, ep
, r
);
4097 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
4100 struct mips_opcode
*mo
;
4101 struct mips_cl_insn insn
;
4102 bfd_reloc_code_real_type r
[3]
4103 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4105 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
4107 gas_assert (strcmp (name
, mo
->name
) == 0);
4109 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
4112 gas_assert (mo
->name
);
4113 gas_assert (strcmp (name
, mo
->name
) == 0);
4116 create_insn (&insn
, mo
);
4134 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
4139 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
4143 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
4147 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
4157 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
4164 regno
= va_arg (*args
, int);
4165 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
4166 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
4187 gas_assert (ep
!= NULL
);
4189 if (ep
->X_op
!= O_constant
)
4190 *r
= (int) BFD_RELOC_UNUSED
+ c
;
4193 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
4194 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
4197 *r
= BFD_RELOC_UNUSED
;
4203 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
4210 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
4212 append_insn (&insn
, ep
, r
);
4216 * Sign-extend 32-bit mode constants that have bit 31 set and all
4217 * higher bits unset.
4220 normalize_constant_expr (expressionS
*ex
)
4222 if (ex
->X_op
== O_constant
4223 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
4224 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
4229 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4230 * all higher bits unset.
4233 normalize_address_expr (expressionS
*ex
)
4235 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
4236 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
4237 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
4238 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
4243 * Generate a "jalr" instruction with a relocation hint to the called
4244 * function. This occurs in NewABI PIC code.
4247 macro_build_jalr (expressionS
*ep
)
4251 if (MIPS_JALR_HINT_P (ep
))
4256 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
4257 if (MIPS_JALR_HINT_P (ep
))
4258 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
4259 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
4263 * Generate a "lui" instruction.
4266 macro_build_lui (expressionS
*ep
, int regnum
)
4268 expressionS high_expr
;
4269 const struct mips_opcode
*mo
;
4270 struct mips_cl_insn insn
;
4271 bfd_reloc_code_real_type r
[3]
4272 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4273 const char *name
= "lui";
4274 const char *fmt
= "t,u";
4276 gas_assert (! mips_opts
.mips16
);
4280 if (high_expr
.X_op
== O_constant
)
4282 /* We can compute the instruction now without a relocation entry. */
4283 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
4285 *r
= BFD_RELOC_UNUSED
;
4289 gas_assert (ep
->X_op
== O_symbol
);
4290 /* _gp_disp is a special case, used from s_cpload.
4291 __gnu_local_gp is used if mips_no_shared. */
4292 gas_assert (mips_pic
== NO_PIC
4294 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
4295 || (! mips_in_shared
4296 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
4297 "__gnu_local_gp") == 0));
4298 *r
= BFD_RELOC_HI16_S
;
4301 mo
= hash_find (op_hash
, name
);
4302 gas_assert (strcmp (name
, mo
->name
) == 0);
4303 gas_assert (strcmp (fmt
, mo
->args
) == 0);
4304 create_insn (&insn
, mo
);
4306 insn
.insn_opcode
= insn
.insn_mo
->match
;
4307 INSERT_OPERAND (RT
, insn
, regnum
);
4308 if (*r
== BFD_RELOC_UNUSED
)
4310 insn
.insn_opcode
|= high_expr
.X_add_number
;
4311 append_insn (&insn
, NULL
, r
);
4314 append_insn (&insn
, &high_expr
, r
);
4317 /* Generate a sequence of instructions to do a load or store from a constant
4318 offset off of a base register (breg) into/from a target register (treg),
4319 using AT if necessary. */
4321 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
4322 int treg
, int breg
, int dbl
)
4324 gas_assert (ep
->X_op
== O_constant
);
4326 /* Sign-extending 32-bit constants makes their handling easier. */
4328 normalize_constant_expr (ep
);
4330 /* Right now, this routine can only handle signed 32-bit constants. */
4331 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
4332 as_warn (_("operand overflow"));
4334 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
4336 /* Signed 16-bit offset will fit in the op. Easy! */
4337 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
4341 /* 32-bit offset, need multiple instructions and AT, like:
4342 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4343 addu $tempreg,$tempreg,$breg
4344 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4345 to handle the complete offset. */
4346 macro_build_lui (ep
, AT
);
4347 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
4348 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
4351 as_bad (_("Macro used $at after \".set noat\""));
4356 * Generates code to set the $at register to true (one)
4357 * if reg is less than the immediate expression.
4360 set_at (int reg
, int unsignedp
)
4362 if (imm_expr
.X_op
== O_constant
4363 && imm_expr
.X_add_number
>= -0x8000
4364 && imm_expr
.X_add_number
< 0x8000)
4365 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
4366 AT
, reg
, BFD_RELOC_LO16
);
4369 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4370 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
4374 /* Warn if an expression is not a constant. */
4377 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
4379 if (ex
->X_op
== O_big
)
4380 as_bad (_("unsupported large constant"));
4381 else if (ex
->X_op
!= O_constant
)
4382 as_bad (_("Instruction %s requires absolute expression"),
4385 if (HAVE_32BIT_GPRS
)
4386 normalize_constant_expr (ex
);
4389 /* Count the leading zeroes by performing a binary chop. This is a
4390 bulky bit of source, but performance is a LOT better for the
4391 majority of values than a simple loop to count the bits:
4392 for (lcnt = 0; (lcnt < 32); lcnt++)
4393 if ((v) & (1 << (31 - lcnt)))
4395 However it is not code size friendly, and the gain will drop a bit
4396 on certain cached systems.
4398 #define COUNT_TOP_ZEROES(v) \
4399 (((v) & ~0xffff) == 0 \
4400 ? ((v) & ~0xff) == 0 \
4401 ? ((v) & ~0xf) == 0 \
4402 ? ((v) & ~0x3) == 0 \
4403 ? ((v) & ~0x1) == 0 \
4408 : ((v) & ~0x7) == 0 \
4411 : ((v) & ~0x3f) == 0 \
4412 ? ((v) & ~0x1f) == 0 \
4415 : ((v) & ~0x7f) == 0 \
4418 : ((v) & ~0xfff) == 0 \
4419 ? ((v) & ~0x3ff) == 0 \
4420 ? ((v) & ~0x1ff) == 0 \
4423 : ((v) & ~0x7ff) == 0 \
4426 : ((v) & ~0x3fff) == 0 \
4427 ? ((v) & ~0x1fff) == 0 \
4430 : ((v) & ~0x7fff) == 0 \
4433 : ((v) & ~0xffffff) == 0 \
4434 ? ((v) & ~0xfffff) == 0 \
4435 ? ((v) & ~0x3ffff) == 0 \
4436 ? ((v) & ~0x1ffff) == 0 \
4439 : ((v) & ~0x7ffff) == 0 \
4442 : ((v) & ~0x3fffff) == 0 \
4443 ? ((v) & ~0x1fffff) == 0 \
4446 : ((v) & ~0x7fffff) == 0 \
4449 : ((v) & ~0xfffffff) == 0 \
4450 ? ((v) & ~0x3ffffff) == 0 \
4451 ? ((v) & ~0x1ffffff) == 0 \
4454 : ((v) & ~0x7ffffff) == 0 \
4457 : ((v) & ~0x3fffffff) == 0 \
4458 ? ((v) & ~0x1fffffff) == 0 \
4461 : ((v) & ~0x7fffffff) == 0 \
4466 * This routine generates the least number of instructions necessary to load
4467 * an absolute expression value into a register.
4470 load_register (int reg
, expressionS
*ep
, int dbl
)
4473 expressionS hi32
, lo32
;
4475 if (ep
->X_op
!= O_big
)
4477 gas_assert (ep
->X_op
== O_constant
);
4479 /* Sign-extending 32-bit constants makes their handling easier. */
4481 normalize_constant_expr (ep
);
4483 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4485 /* We can handle 16 bit signed values with an addiu to
4486 $zero. No need to ever use daddiu here, since $zero and
4487 the result are always correct in 32 bit mode. */
4488 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4491 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4493 /* We can handle 16 bit unsigned values with an ori to
4495 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4498 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4500 /* 32 bit values require an lui. */
4501 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4502 if ((ep
->X_add_number
& 0xffff) != 0)
4503 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4508 /* The value is larger than 32 bits. */
4510 if (!dbl
|| HAVE_32BIT_GPRS
)
4514 sprintf_vma (value
, ep
->X_add_number
);
4515 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4516 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4520 if (ep
->X_op
!= O_big
)
4523 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4524 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4525 hi32
.X_add_number
&= 0xffffffff;
4527 lo32
.X_add_number
&= 0xffffffff;
4531 gas_assert (ep
->X_add_number
> 2);
4532 if (ep
->X_add_number
== 3)
4533 generic_bignum
[3] = 0;
4534 else if (ep
->X_add_number
> 4)
4535 as_bad (_("Number larger than 64 bits"));
4536 lo32
.X_op
= O_constant
;
4537 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4538 hi32
.X_op
= O_constant
;
4539 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4542 if (hi32
.X_add_number
== 0)
4547 unsigned long hi
, lo
;
4549 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4551 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4553 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4556 if (lo32
.X_add_number
& 0x80000000)
4558 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4559 if (lo32
.X_add_number
& 0xffff)
4560 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4565 /* Check for 16bit shifted constant. We know that hi32 is
4566 non-zero, so start the mask on the first bit of the hi32
4571 unsigned long himask
, lomask
;
4575 himask
= 0xffff >> (32 - shift
);
4576 lomask
= (0xffff << shift
) & 0xffffffff;
4580 himask
= 0xffff << (shift
- 32);
4583 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4584 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4588 tmp
.X_op
= O_constant
;
4590 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4591 | (lo32
.X_add_number
>> shift
));
4593 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4594 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4595 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4596 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4601 while (shift
<= (64 - 16));
4603 /* Find the bit number of the lowest one bit, and store the
4604 shifted value in hi/lo. */
4605 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4606 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4610 while ((lo
& 1) == 0)
4615 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4621 while ((hi
& 1) == 0)
4630 /* Optimize if the shifted value is a (power of 2) - 1. */
4631 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4632 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4634 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4639 /* This instruction will set the register to be all
4641 tmp
.X_op
= O_constant
;
4642 tmp
.X_add_number
= (offsetT
) -1;
4643 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4647 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4648 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4650 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4651 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4656 /* Sign extend hi32 before calling load_register, because we can
4657 generally get better code when we load a sign extended value. */
4658 if ((hi32
.X_add_number
& 0x80000000) != 0)
4659 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4660 load_register (reg
, &hi32
, 0);
4663 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4667 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4675 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4677 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4678 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4684 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4688 mid16
.X_add_number
>>= 16;
4689 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4690 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4693 if ((lo32
.X_add_number
& 0xffff) != 0)
4694 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4698 load_delay_nop (void)
4700 if (!gpr_interlocks
)
4701 macro_build (NULL
, "nop", "");
4704 /* Load an address into a register. */
4707 load_address (int reg
, expressionS
*ep
, int *used_at
)
4709 if (ep
->X_op
!= O_constant
4710 && ep
->X_op
!= O_symbol
)
4712 as_bad (_("expression too complex"));
4713 ep
->X_op
= O_constant
;
4716 if (ep
->X_op
== O_constant
)
4718 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4722 if (mips_pic
== NO_PIC
)
4724 /* If this is a reference to a GP relative symbol, we want
4725 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4727 lui $reg,<sym> (BFD_RELOC_HI16_S)
4728 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4729 If we have an addend, we always use the latter form.
4731 With 64bit address space and a usable $at we want
4732 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4733 lui $at,<sym> (BFD_RELOC_HI16_S)
4734 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4735 daddiu $at,<sym> (BFD_RELOC_LO16)
4739 If $at is already in use, we use a path which is suboptimal
4740 on superscalar processors.
4741 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4742 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4744 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4746 daddiu $reg,<sym> (BFD_RELOC_LO16)
4748 For GP relative symbols in 64bit address space we can use
4749 the same sequence as in 32bit address space. */
4750 if (HAVE_64BIT_SYMBOLS
)
4752 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4753 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4755 relax_start (ep
->X_add_symbol
);
4756 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4757 mips_gp_register
, BFD_RELOC_GPREL16
);
4761 if (*used_at
== 0 && mips_opts
.at
)
4763 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4764 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4765 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4766 BFD_RELOC_MIPS_HIGHER
);
4767 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4768 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4769 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4774 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4775 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4776 BFD_RELOC_MIPS_HIGHER
);
4777 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4778 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4779 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4780 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4783 if (mips_relax
.sequence
)
4788 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4789 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4791 relax_start (ep
->X_add_symbol
);
4792 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4793 mips_gp_register
, BFD_RELOC_GPREL16
);
4796 macro_build_lui (ep
, reg
);
4797 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4798 reg
, reg
, BFD_RELOC_LO16
);
4799 if (mips_relax
.sequence
)
4803 else if (!mips_big_got
)
4807 /* If this is a reference to an external symbol, we want
4808 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4810 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4812 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4813 If there is a constant, it must be added in after.
4815 If we have NewABI, we want
4816 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4817 unless we're referencing a global symbol with a non-zero
4818 offset, in which case cst must be added separately. */
4821 if (ep
->X_add_number
)
4823 ex
.X_add_number
= ep
->X_add_number
;
4824 ep
->X_add_number
= 0;
4825 relax_start (ep
->X_add_symbol
);
4826 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4827 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4828 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4829 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4830 ex
.X_op
= O_constant
;
4831 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4832 reg
, reg
, BFD_RELOC_LO16
);
4833 ep
->X_add_number
= ex
.X_add_number
;
4836 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4837 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4838 if (mips_relax
.sequence
)
4843 ex
.X_add_number
= ep
->X_add_number
;
4844 ep
->X_add_number
= 0;
4845 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4846 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4848 relax_start (ep
->X_add_symbol
);
4850 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4854 if (ex
.X_add_number
!= 0)
4856 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4857 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4858 ex
.X_op
= O_constant
;
4859 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4860 reg
, reg
, BFD_RELOC_LO16
);
4864 else if (mips_big_got
)
4868 /* This is the large GOT case. If this is a reference to an
4869 external symbol, we want
4870 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4872 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4874 Otherwise, for a reference to a local symbol in old ABI, we want
4875 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4877 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4878 If there is a constant, it must be added in after.
4880 In the NewABI, for local symbols, with or without offsets, we want:
4881 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4882 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4886 ex
.X_add_number
= ep
->X_add_number
;
4887 ep
->X_add_number
= 0;
4888 relax_start (ep
->X_add_symbol
);
4889 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4890 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4891 reg
, reg
, mips_gp_register
);
4892 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4893 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4894 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4895 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4896 else if (ex
.X_add_number
)
4898 ex
.X_op
= O_constant
;
4899 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4903 ep
->X_add_number
= ex
.X_add_number
;
4905 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4906 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4907 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4908 BFD_RELOC_MIPS_GOT_OFST
);
4913 ex
.X_add_number
= ep
->X_add_number
;
4914 ep
->X_add_number
= 0;
4915 relax_start (ep
->X_add_symbol
);
4916 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4917 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4918 reg
, reg
, mips_gp_register
);
4919 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4920 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4922 if (reg_needs_delay (mips_gp_register
))
4924 /* We need a nop before loading from $gp. This special
4925 check is required because the lui which starts the main
4926 instruction stream does not refer to $gp, and so will not
4927 insert the nop which may be required. */
4928 macro_build (NULL
, "nop", "");
4930 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4931 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4933 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4937 if (ex
.X_add_number
!= 0)
4939 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4940 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4941 ex
.X_op
= O_constant
;
4942 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4950 if (!mips_opts
.at
&& *used_at
== 1)
4951 as_bad (_("Macro used $at after \".set noat\""));
4954 /* Move the contents of register SOURCE into register DEST. */
4957 move_register (int dest
, int source
)
4959 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4963 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4964 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4965 The two alternatives are:
4967 Global symbol Local sybmol
4968 ------------- ------------
4969 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4971 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4973 load_got_offset emits the first instruction and add_got_offset
4974 emits the second for a 16-bit offset or add_got_offset_hilo emits
4975 a sequence to add a 32-bit offset using a scratch register. */
4978 load_got_offset (int dest
, expressionS
*local
)
4983 global
.X_add_number
= 0;
4985 relax_start (local
->X_add_symbol
);
4986 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4987 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4989 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4990 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4995 add_got_offset (int dest
, expressionS
*local
)
4999 global
.X_op
= O_constant
;
5000 global
.X_op_symbol
= NULL
;
5001 global
.X_add_symbol
= NULL
;
5002 global
.X_add_number
= local
->X_add_number
;
5004 relax_start (local
->X_add_symbol
);
5005 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
5006 dest
, dest
, BFD_RELOC_LO16
);
5008 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
5013 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
5016 int hold_mips_optimize
;
5018 global
.X_op
= O_constant
;
5019 global
.X_op_symbol
= NULL
;
5020 global
.X_add_symbol
= NULL
;
5021 global
.X_add_number
= local
->X_add_number
;
5023 relax_start (local
->X_add_symbol
);
5024 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
5026 /* Set mips_optimize around the lui instruction to avoid
5027 inserting an unnecessary nop after the lw. */
5028 hold_mips_optimize
= mips_optimize
;
5030 macro_build_lui (&global
, tmp
);
5031 mips_optimize
= hold_mips_optimize
;
5032 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
5035 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
5040 * This routine implements the seemingly endless macro or synthesized
5041 * instructions and addressing modes in the mips assembly language. Many
5042 * of these macros are simple and are similar to each other. These could
5043 * probably be handled by some kind of table or grammar approach instead of
5044 * this verbose method. Others are not simple macros but are more like
5045 * optimizing code generation.
5046 * One interesting optimization is when several store macros appear
5047 * consecutively that would load AT with the upper half of the same address.
5048 * The ensuing load upper instructions are ommited. This implies some kind
5049 * of global optimization. We currently only optimize within a single macro.
5050 * For many of the load and store macros if the address is specified as a
5051 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5052 * first load register 'at' with zero and use it as the base register. The
5053 * mips assembler simply uses register $zero. Just one tiny optimization
5057 macro (struct mips_cl_insn
*ip
)
5059 unsigned int treg
, sreg
, dreg
, breg
;
5060 unsigned int tempreg
;
5075 bfd_reloc_code_real_type r
;
5076 int hold_mips_optimize
;
5078 gas_assert (! mips_opts
.mips16
);
5080 treg
= EXTRACT_OPERAND (RT
, *ip
);
5081 dreg
= EXTRACT_OPERAND (RD
, *ip
);
5082 sreg
= breg
= EXTRACT_OPERAND (RS
, *ip
);
5083 mask
= ip
->insn_mo
->mask
;
5085 expr1
.X_op
= O_constant
;
5086 expr1
.X_op_symbol
= NULL
;
5087 expr1
.X_add_symbol
= NULL
;
5088 expr1
.X_add_number
= 1;
5102 expr1
.X_add_number
= 8;
5103 macro_build (&expr1
, "bgez", "s,p", sreg
);
5105 macro_build (NULL
, "nop", "");
5107 move_register (dreg
, sreg
);
5108 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
5131 if (imm_expr
.X_op
== O_constant
5132 && imm_expr
.X_add_number
>= -0x8000
5133 && imm_expr
.X_add_number
< 0x8000)
5135 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5139 load_register (AT
, &imm_expr
, dbl
);
5140 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
5159 if (imm_expr
.X_op
== O_constant
5160 && imm_expr
.X_add_number
>= 0
5161 && imm_expr
.X_add_number
< 0x10000)
5163 if (mask
!= M_NOR_I
)
5164 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
5167 macro_build (&imm_expr
, "ori", "t,r,i",
5168 treg
, sreg
, BFD_RELOC_LO16
);
5169 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
5175 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5176 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
5180 switch (imm_expr
.X_add_number
)
5183 macro_build (NULL
, "nop", "");
5186 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
5189 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
5190 (int) imm_expr
.X_add_number
);
5209 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5211 macro_build (&offset_expr
, s
, "s,t,p", sreg
, ZERO
);
5215 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5216 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
5224 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
5229 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
5233 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5234 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5240 /* Check for > max integer. */
5241 maxnum
= 0x7fffffff;
5242 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5249 if (imm_expr
.X_op
== O_constant
5250 && imm_expr
.X_add_number
>= maxnum
5251 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5254 /* Result is always false. */
5256 macro_build (NULL
, "nop", "");
5258 macro_build (&offset_expr
, "bnel", "s,t,p", ZERO
, ZERO
);
5261 if (imm_expr
.X_op
!= O_constant
)
5262 as_bad (_("Unsupported large constant"));
5263 ++imm_expr
.X_add_number
;
5267 if (mask
== M_BGEL_I
)
5269 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5271 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
5274 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5276 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5279 maxnum
= 0x7fffffff;
5280 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5287 maxnum
= - maxnum
- 1;
5288 if (imm_expr
.X_op
== O_constant
5289 && imm_expr
.X_add_number
<= maxnum
5290 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5293 /* result is always true */
5294 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
5295 macro_build (&offset_expr
, "b", "p");
5300 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5310 macro_build (&offset_expr
, likely
? "beql" : "beq",
5311 "s,t,p", ZERO
, treg
);
5315 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5316 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5324 && imm_expr
.X_op
== O_constant
5325 && imm_expr
.X_add_number
== -1))
5327 if (imm_expr
.X_op
!= O_constant
)
5328 as_bad (_("Unsupported large constant"));
5329 ++imm_expr
.X_add_number
;
5333 if (mask
== M_BGEUL_I
)
5335 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5337 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5339 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5340 "s,t,p", sreg
, ZERO
);
5345 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5353 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5358 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
5362 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5363 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5371 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5372 "s,t,p", sreg
, ZERO
);
5378 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5379 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5387 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5392 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
5396 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5397 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5403 maxnum
= 0x7fffffff;
5404 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5411 if (imm_expr
.X_op
== O_constant
5412 && imm_expr
.X_add_number
>= maxnum
5413 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5415 if (imm_expr
.X_op
!= O_constant
)
5416 as_bad (_("Unsupported large constant"));
5417 ++imm_expr
.X_add_number
;
5421 if (mask
== M_BLTL_I
)
5423 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5425 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5428 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5430 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5435 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5443 macro_build (&offset_expr
, likely
? "beql" : "beq",
5444 "s,t,p", sreg
, ZERO
);
5450 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5451 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, ZERO
);
5459 && imm_expr
.X_op
== O_constant
5460 && imm_expr
.X_add_number
== -1))
5462 if (imm_expr
.X_op
!= O_constant
)
5463 as_bad (_("Unsupported large constant"));
5464 ++imm_expr
.X_add_number
;
5468 if (mask
== M_BLTUL_I
)
5470 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5472 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5474 macro_build (&offset_expr
, likely
? "beql" : "beq",
5475 "s,t,p", sreg
, ZERO
);
5480 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5488 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5493 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5497 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5498 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5508 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5509 "s,t,p", ZERO
, treg
);
5513 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5514 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, ZERO
);
5519 /* Use unsigned arithmetic. */
5523 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5525 as_bad (_("Unsupported large constant"));
5530 pos
= imm_expr
.X_add_number
;
5531 size
= imm2_expr
.X_add_number
;
5536 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
5539 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
5541 as_bad (_("Improper extract size (%lu, position %lu)"),
5542 (unsigned long) size
, (unsigned long) pos
);
5546 if (size
<= 32 && pos
< 32)
5551 else if (size
<= 32)
5561 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5568 /* Use unsigned arithmetic. */
5572 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5574 as_bad (_("Unsupported large constant"));
5579 pos
= imm_expr
.X_add_number
;
5580 size
= imm2_expr
.X_add_number
;
5585 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
5588 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
5590 as_bad (_("Improper insert size (%lu, position %lu)"),
5591 (unsigned long) size
, (unsigned long) pos
);
5595 if (pos
< 32 && (pos
+ size
- 1) < 32)
5610 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5611 (int) (pos
+ size
- 1));
5627 as_warn (_("Divide by zero."));
5629 macro_build (NULL
, "teq", "s,t,q", ZERO
, ZERO
, 7);
5631 macro_build (NULL
, "break", "c", 7);
5638 macro_build (NULL
, "teq", "s,t,q", treg
, ZERO
, 7);
5639 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5643 expr1
.X_add_number
= 8;
5644 macro_build (&expr1
, "bne", "s,t,p", treg
, ZERO
);
5645 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5646 macro_build (NULL
, "break", "c", 7);
5648 expr1
.X_add_number
= -1;
5650 load_register (AT
, &expr1
, dbl
);
5651 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5652 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5655 expr1
.X_add_number
= 1;
5656 load_register (AT
, &expr1
, dbl
);
5657 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5661 expr1
.X_add_number
= 0x80000000;
5662 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5666 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5667 /* We want to close the noreorder block as soon as possible, so
5668 that later insns are available for delay slot filling. */
5673 expr1
.X_add_number
= 8;
5674 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5675 macro_build (NULL
, "nop", "");
5677 /* We want to close the noreorder block as soon as possible, so
5678 that later insns are available for delay slot filling. */
5681 macro_build (NULL
, "break", "c", 6);
5683 macro_build (NULL
, s
, "d", dreg
);
5722 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5724 as_warn (_("Divide by zero."));
5726 macro_build (NULL
, "teq", "s,t,q", ZERO
, ZERO
, 7);
5728 macro_build (NULL
, "break", "c", 7);
5731 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5733 if (strcmp (s2
, "mflo") == 0)
5734 move_register (dreg
, sreg
);
5736 move_register (dreg
, ZERO
);
5739 if (imm_expr
.X_op
== O_constant
5740 && imm_expr
.X_add_number
== -1
5741 && s
[strlen (s
) - 1] != 'u')
5743 if (strcmp (s2
, "mflo") == 0)
5745 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5748 move_register (dreg
, ZERO
);
5753 load_register (AT
, &imm_expr
, dbl
);
5754 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5755 macro_build (NULL
, s2
, "d", dreg
);
5777 macro_build (NULL
, "teq", "s,t,q", treg
, ZERO
, 7);
5778 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5779 /* We want to close the noreorder block as soon as possible, so
5780 that later insns are available for delay slot filling. */
5785 expr1
.X_add_number
= 8;
5786 macro_build (&expr1
, "bne", "s,t,p", treg
, ZERO
);
5787 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5789 /* We want to close the noreorder block as soon as possible, so
5790 that later insns are available for delay slot filling. */
5792 macro_build (NULL
, "break", "c", 7);
5794 macro_build (NULL
, s2
, "d", dreg
);
5806 /* Load the address of a symbol into a register. If breg is not
5807 zero, we then add a base register to it. */
5809 if (dbl
&& HAVE_32BIT_GPRS
)
5810 as_warn (_("dla used to load 32-bit register"));
5812 if (!dbl
&& HAVE_64BIT_OBJECTS
)
5813 as_warn (_("la used to load 64-bit address"));
5815 if (offset_expr
.X_op
== O_constant
5816 && offset_expr
.X_add_number
>= -0x8000
5817 && offset_expr
.X_add_number
< 0x8000)
5819 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5820 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5824 if (mips_opts
.at
&& (treg
== breg
))
5834 if (offset_expr
.X_op
!= O_symbol
5835 && offset_expr
.X_op
!= O_constant
)
5837 as_bad (_("Expression too complex"));
5838 offset_expr
.X_op
= O_constant
;
5841 if (offset_expr
.X_op
== O_constant
)
5842 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5843 else if (mips_pic
== NO_PIC
)
5845 /* If this is a reference to a GP relative symbol, we want
5846 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5848 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5849 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5850 If we have a constant, we need two instructions anyhow,
5851 so we may as well always use the latter form.
5853 With 64bit address space and a usable $at we want
5854 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5855 lui $at,<sym> (BFD_RELOC_HI16_S)
5856 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5857 daddiu $at,<sym> (BFD_RELOC_LO16)
5859 daddu $tempreg,$tempreg,$at
5861 If $at is already in use, we use a path which is suboptimal
5862 on superscalar processors.
5863 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5864 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5866 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5868 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5870 For GP relative symbols in 64bit address space we can use
5871 the same sequence as in 32bit address space. */
5872 if (HAVE_64BIT_SYMBOLS
)
5874 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5875 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5877 relax_start (offset_expr
.X_add_symbol
);
5878 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5879 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5883 if (used_at
== 0 && mips_opts
.at
)
5885 macro_build (&offset_expr
, "lui", "t,u",
5886 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5887 macro_build (&offset_expr
, "lui", "t,u",
5888 AT
, BFD_RELOC_HI16_S
);
5889 macro_build (&offset_expr
, "daddiu", "t,r,j",
5890 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5891 macro_build (&offset_expr
, "daddiu", "t,r,j",
5892 AT
, AT
, BFD_RELOC_LO16
);
5893 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5894 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5899 macro_build (&offset_expr
, "lui", "t,u",
5900 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5901 macro_build (&offset_expr
, "daddiu", "t,r,j",
5902 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5903 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5904 macro_build (&offset_expr
, "daddiu", "t,r,j",
5905 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5906 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5907 macro_build (&offset_expr
, "daddiu", "t,r,j",
5908 tempreg
, tempreg
, BFD_RELOC_LO16
);
5911 if (mips_relax
.sequence
)
5916 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5917 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5919 relax_start (offset_expr
.X_add_symbol
);
5920 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5921 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5924 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5925 as_bad (_("Offset too large"));
5926 macro_build_lui (&offset_expr
, tempreg
);
5927 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5928 tempreg
, tempreg
, BFD_RELOC_LO16
);
5929 if (mips_relax
.sequence
)
5933 else if (!mips_big_got
&& !HAVE_NEWABI
)
5935 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5937 /* If this is a reference to an external symbol, and there
5938 is no constant, we want
5939 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5940 or for lca or if tempreg is PIC_CALL_REG
5941 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5942 For a local symbol, we want
5943 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5945 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5947 If we have a small constant, and this is a reference to
5948 an external symbol, we want
5949 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5951 addiu $tempreg,$tempreg,<constant>
5952 For a local symbol, we want the same instruction
5953 sequence, but we output a BFD_RELOC_LO16 reloc on the
5956 If we have a large constant, and this is a reference to
5957 an external symbol, we want
5958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5959 lui $at,<hiconstant>
5960 addiu $at,$at,<loconstant>
5961 addu $tempreg,$tempreg,$at
5962 For a local symbol, we want the same instruction
5963 sequence, but we output a BFD_RELOC_LO16 reloc on the
5967 if (offset_expr
.X_add_number
== 0)
5969 if (mips_pic
== SVR4_PIC
5971 && (call
|| tempreg
== PIC_CALL_REG
))
5972 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5974 relax_start (offset_expr
.X_add_symbol
);
5975 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5976 lw_reloc_type
, mips_gp_register
);
5979 /* We're going to put in an addu instruction using
5980 tempreg, so we may as well insert the nop right
5985 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5986 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5988 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5989 tempreg
, tempreg
, BFD_RELOC_LO16
);
5991 /* FIXME: If breg == 0, and the next instruction uses
5992 $tempreg, then if this variant case is used an extra
5993 nop will be generated. */
5995 else if (offset_expr
.X_add_number
>= -0x8000
5996 && offset_expr
.X_add_number
< 0x8000)
5998 load_got_offset (tempreg
, &offset_expr
);
6000 add_got_offset (tempreg
, &offset_expr
);
6004 expr1
.X_add_number
= offset_expr
.X_add_number
;
6005 offset_expr
.X_add_number
=
6006 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
6007 load_got_offset (tempreg
, &offset_expr
);
6008 offset_expr
.X_add_number
= expr1
.X_add_number
;
6009 /* If we are going to add in a base register, and the
6010 target register and the base register are the same,
6011 then we are using AT as a temporary register. Since
6012 we want to load the constant into AT, we add our
6013 current AT (from the global offset table) and the
6014 register into the register now, and pretend we were
6015 not using a base register. */
6019 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6024 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
6028 else if (!mips_big_got
&& HAVE_NEWABI
)
6030 int add_breg_early
= 0;
6032 /* If this is a reference to an external, and there is no
6033 constant, or local symbol (*), with or without a
6035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6036 or for lca or if tempreg is PIC_CALL_REG
6037 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6039 If we have a small constant, and this is a reference to
6040 an external symbol, we want
6041 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6042 addiu $tempreg,$tempreg,<constant>
6044 If we have a large constant, and this is a reference to
6045 an external symbol, we want
6046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6047 lui $at,<hiconstant>
6048 addiu $at,$at,<loconstant>
6049 addu $tempreg,$tempreg,$at
6051 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6052 local symbols, even though it introduces an additional
6055 if (offset_expr
.X_add_number
)
6057 expr1
.X_add_number
= offset_expr
.X_add_number
;
6058 offset_expr
.X_add_number
= 0;
6060 relax_start (offset_expr
.X_add_symbol
);
6061 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6062 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6064 if (expr1
.X_add_number
>= -0x8000
6065 && expr1
.X_add_number
< 0x8000)
6067 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
6068 tempreg
, tempreg
, BFD_RELOC_LO16
);
6070 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
6072 /* If we are going to add in a base register, and the
6073 target register and the base register are the same,
6074 then we are using AT as a temporary register. Since
6075 we want to load the constant into AT, we add our
6076 current AT (from the global offset table) and the
6077 register into the register now, and pretend we were
6078 not using a base register. */
6083 gas_assert (tempreg
== AT
);
6084 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6090 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6091 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6097 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6100 offset_expr
.X_add_number
= expr1
.X_add_number
;
6102 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6103 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6106 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6107 treg
, tempreg
, breg
);
6113 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
6115 relax_start (offset_expr
.X_add_symbol
);
6116 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6117 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
6119 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6120 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6125 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6126 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6129 else if (mips_big_got
&& !HAVE_NEWABI
)
6132 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
6133 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
6134 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6136 /* This is the large GOT case. If this is a reference to an
6137 external symbol, and there is no constant, we want
6138 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6139 addu $tempreg,$tempreg,$gp
6140 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6141 or for lca or if tempreg is PIC_CALL_REG
6142 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6143 addu $tempreg,$tempreg,$gp
6144 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6145 For a local symbol, we want
6146 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6148 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6150 If we have a small constant, and this is a reference to
6151 an external symbol, we want
6152 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6153 addu $tempreg,$tempreg,$gp
6154 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6156 addiu $tempreg,$tempreg,<constant>
6157 For a local symbol, we want
6158 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6160 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6162 If we have a large constant, and this is a reference to
6163 an external symbol, we want
6164 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6165 addu $tempreg,$tempreg,$gp
6166 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6167 lui $at,<hiconstant>
6168 addiu $at,$at,<loconstant>
6169 addu $tempreg,$tempreg,$at
6170 For a local symbol, we want
6171 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6172 lui $at,<hiconstant>
6173 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6174 addu $tempreg,$tempreg,$at
6177 expr1
.X_add_number
= offset_expr
.X_add_number
;
6178 offset_expr
.X_add_number
= 0;
6179 relax_start (offset_expr
.X_add_symbol
);
6180 gpdelay
= reg_needs_delay (mips_gp_register
);
6181 if (expr1
.X_add_number
== 0 && breg
== 0
6182 && (call
|| tempreg
== PIC_CALL_REG
))
6184 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
6185 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
6187 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
6188 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6189 tempreg
, tempreg
, mips_gp_register
);
6190 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6191 tempreg
, lw_reloc_type
, tempreg
);
6192 if (expr1
.X_add_number
== 0)
6196 /* We're going to put in an addu instruction using
6197 tempreg, so we may as well insert the nop right
6202 else if (expr1
.X_add_number
>= -0x8000
6203 && expr1
.X_add_number
< 0x8000)
6206 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
6207 tempreg
, tempreg
, BFD_RELOC_LO16
);
6211 /* If we are going to add in a base register, and the
6212 target register and the base register are the same,
6213 then we are using AT as a temporary register. Since
6214 we want to load the constant into AT, we add our
6215 current AT (from the global offset table) and the
6216 register into the register now, and pretend we were
6217 not using a base register. */
6222 gas_assert (tempreg
== AT
);
6224 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6229 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6230 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6234 offset_expr
.X_add_number
=
6235 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
6240 /* This is needed because this instruction uses $gp, but
6241 the first instruction on the main stream does not. */
6242 macro_build (NULL
, "nop", "");
6245 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6246 local_reloc_type
, mips_gp_register
);
6247 if (expr1
.X_add_number
>= -0x8000
6248 && expr1
.X_add_number
< 0x8000)
6251 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6252 tempreg
, tempreg
, BFD_RELOC_LO16
);
6253 /* FIXME: If add_number is 0, and there was no base
6254 register, the external symbol case ended with a load,
6255 so if the symbol turns out to not be external, and
6256 the next instruction uses tempreg, an unnecessary nop
6257 will be inserted. */
6263 /* We must add in the base register now, as in the
6264 external symbol case. */
6265 gas_assert (tempreg
== AT
);
6267 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6270 /* We set breg to 0 because we have arranged to add
6271 it in in both cases. */
6275 macro_build_lui (&expr1
, AT
);
6276 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6277 AT
, AT
, BFD_RELOC_LO16
);
6278 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6279 tempreg
, tempreg
, AT
);
6284 else if (mips_big_got
&& HAVE_NEWABI
)
6286 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
6287 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
6288 int add_breg_early
= 0;
6290 /* This is the large GOT case. If this is a reference to an
6291 external symbol, and there is no constant, we want
6292 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6293 add $tempreg,$tempreg,$gp
6294 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6295 or for lca or if tempreg is PIC_CALL_REG
6296 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6297 add $tempreg,$tempreg,$gp
6298 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6300 If we have a small constant, and this is a reference to
6301 an external symbol, we want
6302 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6303 add $tempreg,$tempreg,$gp
6304 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6305 addi $tempreg,$tempreg,<constant>
6307 If we have a large constant, and this is a reference to
6308 an external symbol, we want
6309 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6310 addu $tempreg,$tempreg,$gp
6311 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6312 lui $at,<hiconstant>
6313 addi $at,$at,<loconstant>
6314 add $tempreg,$tempreg,$at
6316 If we have NewABI, and we know it's a local symbol, we want
6317 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6318 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6319 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6321 relax_start (offset_expr
.X_add_symbol
);
6323 expr1
.X_add_number
= offset_expr
.X_add_number
;
6324 offset_expr
.X_add_number
= 0;
6326 if (expr1
.X_add_number
== 0 && breg
== 0
6327 && (call
|| tempreg
== PIC_CALL_REG
))
6329 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
6330 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
6332 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
6333 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6334 tempreg
, tempreg
, mips_gp_register
);
6335 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6336 tempreg
, lw_reloc_type
, tempreg
);
6338 if (expr1
.X_add_number
== 0)
6340 else if (expr1
.X_add_number
>= -0x8000
6341 && expr1
.X_add_number
< 0x8000)
6343 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
6344 tempreg
, tempreg
, BFD_RELOC_LO16
);
6346 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
6348 /* If we are going to add in a base register, and the
6349 target register and the base register are the same,
6350 then we are using AT as a temporary register. Since
6351 we want to load the constant into AT, we add our
6352 current AT (from the global offset table) and the
6353 register into the register now, and pretend we were
6354 not using a base register. */
6359 gas_assert (tempreg
== AT
);
6360 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6366 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6367 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6372 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6375 offset_expr
.X_add_number
= expr1
.X_add_number
;
6376 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6377 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6378 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6379 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
6382 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6383 treg
, tempreg
, breg
);
6393 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
6398 unsigned long temp
= (treg
<< 16) | (0x01);
6399 macro_build (NULL
, "c2", "C", temp
);
6405 unsigned long temp
= (0x02);
6406 macro_build (NULL
, "c2", "C", temp
);
6412 unsigned long temp
= (treg
<< 16) | (0x02);
6413 macro_build (NULL
, "c2", "C", temp
);
6418 macro_build (NULL
, "c2", "C", 3);
6423 unsigned long temp
= (treg
<< 16) | 0x03;
6424 macro_build (NULL
, "c2", "C", temp
);
6429 /* The j instruction may not be used in PIC code, since it
6430 requires an absolute address. We convert it to a b
6432 if (mips_pic
== NO_PIC
)
6433 macro_build (&offset_expr
, "j", "a");
6435 macro_build (&offset_expr
, "b", "p");
6438 /* The jal instructions must be handled as macros because when
6439 generating PIC code they expand to multi-instruction
6440 sequences. Normally they are simple instructions. */
6445 if (mips_pic
== NO_PIC
)
6446 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6449 if (sreg
!= PIC_CALL_REG
)
6450 as_warn (_("MIPS PIC call to register other than $25"));
6452 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6453 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6455 if (mips_cprestore_offset
< 0)
6456 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6459 if (!mips_frame_reg_valid
)
6461 as_warn (_("No .frame pseudo-op used in PIC code"));
6462 /* Quiet this warning. */
6463 mips_frame_reg_valid
= 1;
6465 if (!mips_cprestore_valid
)
6467 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6468 /* Quiet this warning. */
6469 mips_cprestore_valid
= 1;
6471 if (mips_opts
.noreorder
)
6472 macro_build (NULL
, "nop", "");
6473 expr1
.X_add_number
= mips_cprestore_offset
;
6474 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6477 HAVE_64BIT_ADDRESSES
);
6485 if (mips_pic
== NO_PIC
)
6486 macro_build (&offset_expr
, "jal", "a");
6487 else if (mips_pic
== SVR4_PIC
)
6489 /* If this is a reference to an external symbol, and we are
6490 using a small GOT, we want
6491 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6495 lw $gp,cprestore($sp)
6496 The cprestore value is set using the .cprestore
6497 pseudo-op. If we are using a big GOT, we want
6498 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6500 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6504 lw $gp,cprestore($sp)
6505 If the symbol is not external, we want
6506 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6508 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6511 lw $gp,cprestore($sp)
6513 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6514 sequences above, minus nops, unless the symbol is local,
6515 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6521 relax_start (offset_expr
.X_add_symbol
);
6522 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6523 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6526 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6527 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6533 relax_start (offset_expr
.X_add_symbol
);
6534 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6535 BFD_RELOC_MIPS_CALL_HI16
);
6536 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6537 PIC_CALL_REG
, mips_gp_register
);
6538 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6539 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6542 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6543 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6545 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6546 PIC_CALL_REG
, PIC_CALL_REG
,
6547 BFD_RELOC_MIPS_GOT_OFST
);
6551 macro_build_jalr (&offset_expr
);
6555 relax_start (offset_expr
.X_add_symbol
);
6558 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6559 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6568 gpdelay
= reg_needs_delay (mips_gp_register
);
6569 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6570 BFD_RELOC_MIPS_CALL_HI16
);
6571 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6572 PIC_CALL_REG
, mips_gp_register
);
6573 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6574 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6579 macro_build (NULL
, "nop", "");
6581 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6582 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6585 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6586 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6588 macro_build_jalr (&offset_expr
);
6590 if (mips_cprestore_offset
< 0)
6591 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6594 if (!mips_frame_reg_valid
)
6596 as_warn (_("No .frame pseudo-op used in PIC code"));
6597 /* Quiet this warning. */
6598 mips_frame_reg_valid
= 1;
6600 if (!mips_cprestore_valid
)
6602 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6603 /* Quiet this warning. */
6604 mips_cprestore_valid
= 1;
6606 if (mips_opts
.noreorder
)
6607 macro_build (NULL
, "nop", "");
6608 expr1
.X_add_number
= mips_cprestore_offset
;
6609 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6612 HAVE_64BIT_ADDRESSES
);
6616 else if (mips_pic
== VXWORKS_PIC
)
6617 as_bad (_("Non-PIC jump used in PIC library"));
6640 /* Itbl support may require additional care here. */
6645 /* Itbl support may require additional care here. */
6650 /* Itbl support may require additional care here. */
6655 /* Itbl support may require additional care here. */
6668 /* Itbl support may require additional care here. */
6673 /* Itbl support may require additional care here. */
6678 /* Itbl support may require additional care here. */
6698 if (breg
== treg
|| coproc
|| lr
)
6719 /* Itbl support may require additional care here. */
6724 /* Itbl support may require additional care here. */
6729 /* Itbl support may require additional care here. */
6734 /* Itbl support may require additional care here. */
6758 /* Itbl support may require additional care here. */
6762 /* Itbl support may require additional care here. */
6767 /* Itbl support may require additional care here. */
6780 && NO_ISA_COP (mips_opts
.arch
)
6781 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6783 as_bad (_("Opcode not supported on this processor: %s"),
6784 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6788 /* Itbl support may require additional care here. */
6789 if (mask
== M_LWC1_AB
6790 || mask
== M_SWC1_AB
6791 || mask
== M_LDC1_AB
6792 || mask
== M_SDC1_AB
6796 else if (mask
== M_CACHE_AB
|| mask
== M_PREF_AB
)
6803 if (offset_expr
.X_op
!= O_constant
6804 && offset_expr
.X_op
!= O_symbol
)
6806 as_bad (_("Expression too complex"));
6807 offset_expr
.X_op
= O_constant
;
6810 if (HAVE_32BIT_ADDRESSES
6811 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6815 sprintf_vma (value
, offset_expr
.X_add_number
);
6816 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6819 /* A constant expression in PIC code can be handled just as it
6820 is in non PIC code. */
6821 if (offset_expr
.X_op
== O_constant
)
6823 expr1
.X_add_number
= offset_expr
.X_add_number
;
6824 normalize_address_expr (&expr1
);
6825 if (!IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
6827 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
6828 & ~(bfd_vma
) 0xffff);
6829 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6831 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6832 tempreg
, tempreg
, breg
);
6835 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
6837 else if (mips_pic
== NO_PIC
)
6839 /* If this is a reference to a GP relative symbol, and there
6840 is no base register, we want
6841 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6842 Otherwise, if there is no base register, we want
6843 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6844 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6845 If we have a constant, we need two instructions anyhow,
6846 so we always use the latter form.
6848 If we have a base register, and this is a reference to a
6849 GP relative symbol, we want
6850 addu $tempreg,$breg,$gp
6851 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6853 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6854 addu $tempreg,$tempreg,$breg
6855 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6856 With a constant we always use the latter case.
6858 With 64bit address space and no base register and $at usable,
6860 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6861 lui $at,<sym> (BFD_RELOC_HI16_S)
6862 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6865 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6866 If we have a base register, we want
6867 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6868 lui $at,<sym> (BFD_RELOC_HI16_S)
6869 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6873 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6875 Without $at we can't generate the optimal path for superscalar
6876 processors here since this would require two temporary registers.
6877 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6878 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6880 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6882 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6883 If we have a base register, we want
6884 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6885 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6887 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6889 daddu $tempreg,$tempreg,$breg
6890 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6892 For GP relative symbols in 64bit address space we can use
6893 the same sequence as in 32bit address space. */
6894 if (HAVE_64BIT_SYMBOLS
)
6896 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6897 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6899 relax_start (offset_expr
.X_add_symbol
);
6902 macro_build (&offset_expr
, s
, fmt
, treg
,
6903 BFD_RELOC_GPREL16
, mips_gp_register
);
6907 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6908 tempreg
, breg
, mips_gp_register
);
6909 macro_build (&offset_expr
, s
, fmt
, treg
,
6910 BFD_RELOC_GPREL16
, tempreg
);
6915 if (used_at
== 0 && mips_opts
.at
)
6917 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6918 BFD_RELOC_MIPS_HIGHEST
);
6919 macro_build (&offset_expr
, "lui", "t,u", AT
,
6921 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6922 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6924 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6925 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6926 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6927 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6933 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6934 BFD_RELOC_MIPS_HIGHEST
);
6935 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6936 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6937 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6938 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6939 tempreg
, BFD_RELOC_HI16_S
);
6940 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6942 macro_build (NULL
, "daddu", "d,v,t",
6943 tempreg
, tempreg
, breg
);
6944 macro_build (&offset_expr
, s
, fmt
, treg
,
6945 BFD_RELOC_LO16
, tempreg
);
6948 if (mips_relax
.sequence
)
6955 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6956 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6958 relax_start (offset_expr
.X_add_symbol
);
6959 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6963 macro_build_lui (&offset_expr
, tempreg
);
6964 macro_build (&offset_expr
, s
, fmt
, treg
,
6965 BFD_RELOC_LO16
, tempreg
);
6966 if (mips_relax
.sequence
)
6971 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6972 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6974 relax_start (offset_expr
.X_add_symbol
);
6975 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6976 tempreg
, breg
, mips_gp_register
);
6977 macro_build (&offset_expr
, s
, fmt
, treg
,
6978 BFD_RELOC_GPREL16
, tempreg
);
6981 macro_build_lui (&offset_expr
, tempreg
);
6982 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6983 tempreg
, tempreg
, breg
);
6984 macro_build (&offset_expr
, s
, fmt
, treg
,
6985 BFD_RELOC_LO16
, tempreg
);
6986 if (mips_relax
.sequence
)
6990 else if (!mips_big_got
)
6992 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6994 /* If this is a reference to an external symbol, we want
6995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6997 <op> $treg,0($tempreg)
6999 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7001 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7002 <op> $treg,0($tempreg)
7005 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7006 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
7008 If there is a base register, we add it to $tempreg before
7009 the <op>. If there is a constant, we stick it in the
7010 <op> instruction. We don't handle constants larger than
7011 16 bits, because we have no way to load the upper 16 bits
7012 (actually, we could handle them for the subset of cases
7013 in which we are not using $at). */
7014 gas_assert (offset_expr
.X_op
== O_symbol
);
7017 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7018 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7020 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7021 tempreg
, tempreg
, breg
);
7022 macro_build (&offset_expr
, s
, fmt
, treg
,
7023 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
7026 expr1
.X_add_number
= offset_expr
.X_add_number
;
7027 offset_expr
.X_add_number
= 0;
7028 if (expr1
.X_add_number
< -0x8000
7029 || expr1
.X_add_number
>= 0x8000)
7030 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7031 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7032 lw_reloc_type
, mips_gp_register
);
7034 relax_start (offset_expr
.X_add_symbol
);
7036 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7037 tempreg
, BFD_RELOC_LO16
);
7040 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7041 tempreg
, tempreg
, breg
);
7042 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
7044 else if (mips_big_got
&& !HAVE_NEWABI
)
7048 /* If this is a reference to an external symbol, we want
7049 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7050 addu $tempreg,$tempreg,$gp
7051 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7052 <op> $treg,0($tempreg)
7054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7056 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7057 <op> $treg,0($tempreg)
7058 If there is a base register, we add it to $tempreg before
7059 the <op>. If there is a constant, we stick it in the
7060 <op> instruction. We don't handle constants larger than
7061 16 bits, because we have no way to load the upper 16 bits
7062 (actually, we could handle them for the subset of cases
7063 in which we are not using $at). */
7064 gas_assert (offset_expr
.X_op
== O_symbol
);
7065 expr1
.X_add_number
= offset_expr
.X_add_number
;
7066 offset_expr
.X_add_number
= 0;
7067 if (expr1
.X_add_number
< -0x8000
7068 || expr1
.X_add_number
>= 0x8000)
7069 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7070 gpdelay
= reg_needs_delay (mips_gp_register
);
7071 relax_start (offset_expr
.X_add_symbol
);
7072 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
7073 BFD_RELOC_MIPS_GOT_HI16
);
7074 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
7076 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7077 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
7080 macro_build (NULL
, "nop", "");
7081 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7082 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7084 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7085 tempreg
, BFD_RELOC_LO16
);
7089 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7090 tempreg
, tempreg
, breg
);
7091 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
7093 else if (mips_big_got
&& HAVE_NEWABI
)
7095 /* If this is a reference to an external symbol, we want
7096 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7097 add $tempreg,$tempreg,$gp
7098 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7099 <op> $treg,<ofst>($tempreg)
7100 Otherwise, for local symbols, we want:
7101 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7102 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7103 gas_assert (offset_expr
.X_op
== O_symbol
);
7104 expr1
.X_add_number
= offset_expr
.X_add_number
;
7105 offset_expr
.X_add_number
= 0;
7106 if (expr1
.X_add_number
< -0x8000
7107 || expr1
.X_add_number
>= 0x8000)
7108 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7109 relax_start (offset_expr
.X_add_symbol
);
7110 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
7111 BFD_RELOC_MIPS_GOT_HI16
);
7112 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
7114 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7115 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
7117 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7118 tempreg
, tempreg
, breg
);
7119 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
7122 offset_expr
.X_add_number
= expr1
.X_add_number
;
7123 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7124 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7126 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7127 tempreg
, tempreg
, breg
);
7128 macro_build (&offset_expr
, s
, fmt
, treg
,
7129 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
7139 load_register (treg
, &imm_expr
, 0);
7143 load_register (treg
, &imm_expr
, 1);
7147 if (imm_expr
.X_op
== O_constant
)
7150 load_register (AT
, &imm_expr
, 0);
7151 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
7156 gas_assert (offset_expr
.X_op
== O_symbol
7157 && strcmp (segment_name (S_GET_SEGMENT
7158 (offset_expr
.X_add_symbol
)),
7160 && offset_expr
.X_add_number
== 0);
7161 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
7162 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
7167 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7168 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7169 order 32 bits of the value and the low order 32 bits are either
7170 zero or in OFFSET_EXPR. */
7171 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
7173 if (HAVE_64BIT_GPRS
)
7174 load_register (treg
, &imm_expr
, 1);
7179 if (target_big_endian
)
7191 load_register (hreg
, &imm_expr
, 0);
7194 if (offset_expr
.X_op
== O_absent
)
7195 move_register (lreg
, 0);
7198 gas_assert (offset_expr
.X_op
== O_constant
);
7199 load_register (lreg
, &offset_expr
, 0);
7206 /* We know that sym is in the .rdata section. First we get the
7207 upper 16 bits of the address. */
7208 if (mips_pic
== NO_PIC
)
7210 macro_build_lui (&offset_expr
, AT
);
7215 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7216 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7220 /* Now we load the register(s). */
7221 if (HAVE_64BIT_GPRS
)
7224 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7229 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7232 /* FIXME: How in the world do we deal with the possible
7234 offset_expr
.X_add_number
+= 4;
7235 macro_build (&offset_expr
, "lw", "t,o(b)",
7236 treg
+ 1, BFD_RELOC_LO16
, AT
);
7242 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7243 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7244 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7245 the value and the low order 32 bits are either zero or in
7247 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
7250 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
7251 if (HAVE_64BIT_FPRS
)
7253 gas_assert (HAVE_64BIT_GPRS
);
7254 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
7258 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
7259 if (offset_expr
.X_op
== O_absent
)
7260 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
7263 gas_assert (offset_expr
.X_op
== O_constant
);
7264 load_register (AT
, &offset_expr
, 0);
7265 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
7271 gas_assert (offset_expr
.X_op
== O_symbol
7272 && offset_expr
.X_add_number
== 0);
7273 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
7274 if (strcmp (s
, ".lit8") == 0)
7276 if (mips_opts
.isa
!= ISA_MIPS1
)
7278 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
7279 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
7282 breg
= mips_gp_register
;
7283 r
= BFD_RELOC_MIPS_LITERAL
;
7288 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
7290 if (mips_pic
!= NO_PIC
)
7291 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7292 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7295 /* FIXME: This won't work for a 64 bit address. */
7296 macro_build_lui (&offset_expr
, AT
);
7299 if (mips_opts
.isa
!= ISA_MIPS1
)
7301 macro_build (&offset_expr
, "ldc1", "T,o(b)",
7302 treg
, BFD_RELOC_LO16
, AT
);
7311 /* Even on a big endian machine $fn comes before $fn+1. We have
7312 to adjust when loading from memory. */
7315 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7316 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7317 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
7318 /* FIXME: A possible overflow which I don't know how to deal
7320 offset_expr
.X_add_number
+= 4;
7321 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7322 target_big_endian
? treg
: treg
+ 1, r
, breg
);
7326 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7327 /* Even on a big endian machine $fn comes before $fn+1. We have
7328 to adjust when storing to memory. */
7329 macro_build (&offset_expr
, "swc1", "T,o(b)",
7330 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7331 offset_expr
.X_add_number
+= 4;
7332 macro_build (&offset_expr
, "swc1", "T,o(b)",
7333 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7338 * The MIPS assembler seems to check for X_add_number not
7339 * being double aligned and generating:
7342 * addiu at,at,%lo(foo+1)
7345 * But, the resulting address is the same after relocation so why
7346 * generate the extra instruction?
7348 /* Itbl support may require additional care here. */
7350 if (mips_opts
.isa
!= ISA_MIPS1
)
7361 if (mips_opts
.isa
!= ISA_MIPS1
)
7369 /* Itbl support may require additional care here. */
7374 if (HAVE_64BIT_GPRS
)
7385 if (HAVE_64BIT_GPRS
)
7395 if (offset_expr
.X_op
!= O_symbol
7396 && offset_expr
.X_op
!= O_constant
)
7398 as_bad (_("Expression too complex"));
7399 offset_expr
.X_op
= O_constant
;
7402 if (HAVE_32BIT_ADDRESSES
7403 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7407 sprintf_vma (value
, offset_expr
.X_add_number
);
7408 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7411 /* Even on a big endian machine $fn comes before $fn+1. We have
7412 to adjust when loading from memory. We set coproc if we must
7413 load $fn+1 first. */
7414 /* Itbl support may require additional care here. */
7415 if (!target_big_endian
)
7418 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
7420 /* If this is a reference to a GP relative symbol, we want
7421 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7422 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7423 If we have a base register, we use this
7425 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7426 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7427 If this is not a GP relative symbol, we want
7428 lui $at,<sym> (BFD_RELOC_HI16_S)
7429 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7430 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7431 If there is a base register, we add it to $at after the
7432 lui instruction. If there is a constant, we always use
7434 if (offset_expr
.X_op
== O_symbol
7435 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7436 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7438 relax_start (offset_expr
.X_add_symbol
);
7441 tempreg
= mips_gp_register
;
7445 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7446 AT
, breg
, mips_gp_register
);
7451 /* Itbl support may require additional care here. */
7452 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7453 BFD_RELOC_GPREL16
, tempreg
);
7454 offset_expr
.X_add_number
+= 4;
7456 /* Set mips_optimize to 2 to avoid inserting an
7458 hold_mips_optimize
= mips_optimize
;
7460 /* Itbl support may require additional care here. */
7461 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7462 BFD_RELOC_GPREL16
, tempreg
);
7463 mips_optimize
= hold_mips_optimize
;
7467 offset_expr
.X_add_number
-= 4;
7470 macro_build_lui (&offset_expr
, AT
);
7472 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7473 /* Itbl support may require additional care here. */
7474 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7475 BFD_RELOC_LO16
, AT
);
7476 /* FIXME: How do we handle overflow here? */
7477 offset_expr
.X_add_number
+= 4;
7478 /* Itbl support may require additional care here. */
7479 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7480 BFD_RELOC_LO16
, AT
);
7481 if (mips_relax
.sequence
)
7484 else if (!mips_big_got
)
7486 /* If this is a reference to an external symbol, we want
7487 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7492 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7494 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7495 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7496 If there is a base register we add it to $at before the
7497 lwc1 instructions. If there is a constant we include it
7498 in the lwc1 instructions. */
7500 expr1
.X_add_number
= offset_expr
.X_add_number
;
7501 if (expr1
.X_add_number
< -0x8000
7502 || expr1
.X_add_number
>= 0x8000 - 4)
7503 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7504 load_got_offset (AT
, &offset_expr
);
7507 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7509 /* Set mips_optimize to 2 to avoid inserting an undesired
7511 hold_mips_optimize
= mips_optimize
;
7514 /* Itbl support may require additional care here. */
7515 relax_start (offset_expr
.X_add_symbol
);
7516 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7517 BFD_RELOC_LO16
, AT
);
7518 expr1
.X_add_number
+= 4;
7519 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7520 BFD_RELOC_LO16
, AT
);
7522 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7523 BFD_RELOC_LO16
, AT
);
7524 offset_expr
.X_add_number
+= 4;
7525 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7526 BFD_RELOC_LO16
, AT
);
7529 mips_optimize
= hold_mips_optimize
;
7531 else if (mips_big_got
)
7535 /* If this is a reference to an external symbol, we want
7536 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7538 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7543 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7545 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7546 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7547 If there is a base register we add it to $at before the
7548 lwc1 instructions. If there is a constant we include it
7549 in the lwc1 instructions. */
7551 expr1
.X_add_number
= offset_expr
.X_add_number
;
7552 offset_expr
.X_add_number
= 0;
7553 if (expr1
.X_add_number
< -0x8000
7554 || expr1
.X_add_number
>= 0x8000 - 4)
7555 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7556 gpdelay
= reg_needs_delay (mips_gp_register
);
7557 relax_start (offset_expr
.X_add_symbol
);
7558 macro_build (&offset_expr
, "lui", "t,u",
7559 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7560 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7561 AT
, AT
, mips_gp_register
);
7562 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7563 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7566 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7567 /* Itbl support may require additional care here. */
7568 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7569 BFD_RELOC_LO16
, AT
);
7570 expr1
.X_add_number
+= 4;
7572 /* Set mips_optimize to 2 to avoid inserting an undesired
7574 hold_mips_optimize
= mips_optimize
;
7576 /* Itbl support may require additional care here. */
7577 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7578 BFD_RELOC_LO16
, AT
);
7579 mips_optimize
= hold_mips_optimize
;
7580 expr1
.X_add_number
-= 4;
7583 offset_expr
.X_add_number
= expr1
.X_add_number
;
7585 macro_build (NULL
, "nop", "");
7586 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7587 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7590 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7591 /* Itbl support may require additional care here. */
7592 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7593 BFD_RELOC_LO16
, AT
);
7594 offset_expr
.X_add_number
+= 4;
7596 /* Set mips_optimize to 2 to avoid inserting an undesired
7598 hold_mips_optimize
= mips_optimize
;
7600 /* Itbl support may require additional care here. */
7601 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7602 BFD_RELOC_LO16
, AT
);
7603 mips_optimize
= hold_mips_optimize
;
7612 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
7615 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
7617 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
7618 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7620 if (!HAVE_64BIT_GPRS
)
7622 offset_expr
.X_add_number
+= 4;
7623 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
7624 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7629 /* New code added to support COPZ instructions.
7630 This code builds table entries out of the macros in mip_opcodes.
7631 R4000 uses interlocks to handle coproc delays.
7632 Other chips (like the R3000) require nops to be inserted for delays.
7634 FIXME: Currently, we require that the user handle delays.
7635 In order to fill delay slots for non-interlocked chips,
7636 we must have a way to specify delays based on the coprocessor.
7637 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7638 What are the side-effects of the cop instruction?
7639 What cache support might we have and what are its effects?
7640 Both coprocessor & memory require delays. how long???
7641 What registers are read/set/modified?
7643 If an itbl is provided to interpret cop instructions,
7644 this knowledge can be encoded in the itbl spec. */
7658 if (NO_ISA_COP (mips_opts
.arch
)
7659 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7661 as_bad (_("opcode not supported on this processor: %s"),
7662 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7666 /* For now we just do C (same as Cz). The parameter will be
7667 stored in insn_opcode by mips_ip. */
7668 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7672 move_register (dreg
, sreg
);
7678 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7679 macro_build (NULL
, "mflo", "d", dreg
);
7685 /* The MIPS assembler some times generates shifts and adds. I'm
7686 not trying to be that fancy. GCC should do this for us
7689 load_register (AT
, &imm_expr
, dbl
);
7690 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7691 macro_build (NULL
, "mflo", "d", dreg
);
7707 load_register (AT
, &imm_expr
, dbl
);
7708 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7709 macro_build (NULL
, "mflo", "d", dreg
);
7710 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7711 macro_build (NULL
, "mfhi", "d", AT
);
7713 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7716 expr1
.X_add_number
= 8;
7717 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7718 macro_build (NULL
, "nop", "");
7719 macro_build (NULL
, "break", "c", 6);
7722 macro_build (NULL
, "mflo", "d", dreg
);
7738 load_register (AT
, &imm_expr
, dbl
);
7739 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7740 sreg
, imm
? AT
: treg
);
7741 macro_build (NULL
, "mfhi", "d", AT
);
7742 macro_build (NULL
, "mflo", "d", dreg
);
7744 macro_build (NULL
, "tne", "s,t,q", AT
, ZERO
, 6);
7747 expr1
.X_add_number
= 8;
7748 macro_build (&expr1
, "beq", "s,t,p", AT
, ZERO
);
7749 macro_build (NULL
, "nop", "");
7750 macro_build (NULL
, "break", "c", 6);
7756 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7767 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7768 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7772 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
7773 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7774 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7775 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7779 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7790 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7791 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7795 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
7796 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7797 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7798 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7807 if (imm_expr
.X_op
!= O_constant
)
7808 as_bad (_("Improper rotate count"));
7809 rot
= imm_expr
.X_add_number
& 0x3f;
7810 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7812 rot
= (64 - rot
) & 0x3f;
7814 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7816 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7821 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7824 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7825 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7828 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7829 macro_build (NULL
, rr
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7830 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7838 if (imm_expr
.X_op
!= O_constant
)
7839 as_bad (_("Improper rotate count"));
7840 rot
= imm_expr
.X_add_number
& 0x1f;
7841 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7843 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7848 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7852 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7853 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7854 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7859 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7861 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7865 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
7866 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7867 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7868 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7872 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7874 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7878 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
7879 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7880 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7881 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7890 if (imm_expr
.X_op
!= O_constant
)
7891 as_bad (_("Improper rotate count"));
7892 rot
= imm_expr
.X_add_number
& 0x3f;
7893 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7896 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7898 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7903 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7906 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7907 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7910 macro_build (NULL
, rr
, "d,w,<", AT
, sreg
, rot
);
7911 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7912 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7920 if (imm_expr
.X_op
!= O_constant
)
7921 as_bad (_("Improper rotate count"));
7922 rot
= imm_expr
.X_add_number
& 0x1f;
7923 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7925 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7930 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7934 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7935 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7936 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7942 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7944 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7947 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7948 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7953 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7955 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7960 as_warn (_("Instruction %s: result is always false"),
7962 move_register (dreg
, 0);
7965 if (CPU_HAS_SEQ (mips_opts
.arch
)
7966 && -512 <= imm_expr
.X_add_number
7967 && imm_expr
.X_add_number
< 512)
7969 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7970 (int) imm_expr
.X_add_number
);
7973 if (imm_expr
.X_op
== O_constant
7974 && imm_expr
.X_add_number
>= 0
7975 && imm_expr
.X_add_number
< 0x10000)
7977 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7979 else if (imm_expr
.X_op
== O_constant
7980 && imm_expr
.X_add_number
> -0x8000
7981 && imm_expr
.X_add_number
< 0)
7983 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7984 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7985 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7987 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7990 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7991 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7996 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7997 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
8000 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
8003 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
8009 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
8010 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
8013 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
8015 if (imm_expr
.X_op
== O_constant
8016 && imm_expr
.X_add_number
>= -0x8000
8017 && imm_expr
.X_add_number
< 0x8000)
8019 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
8020 dreg
, sreg
, BFD_RELOC_LO16
);
8024 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8025 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
8029 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
8032 case M_SGT
: /* sreg > treg <==> treg < sreg */
8038 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
8041 case M_SGT_I
: /* sreg > I <==> I < sreg */
8048 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8049 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
8052 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8058 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
8059 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
8062 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8069 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8070 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
8071 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
8075 if (imm_expr
.X_op
== O_constant
8076 && imm_expr
.X_add_number
>= -0x8000
8077 && imm_expr
.X_add_number
< 0x8000)
8079 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
8083 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8084 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
8088 if (imm_expr
.X_op
== O_constant
8089 && imm_expr
.X_add_number
>= -0x8000
8090 && imm_expr
.X_add_number
< 0x8000)
8092 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
8097 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8098 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
8103 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
8105 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
8108 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
8109 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
8114 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8116 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
8121 as_warn (_("Instruction %s: result is always true"),
8123 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
8124 dreg
, 0, BFD_RELOC_LO16
);
8127 if (CPU_HAS_SEQ (mips_opts
.arch
)
8128 && -512 <= imm_expr
.X_add_number
8129 && imm_expr
.X_add_number
< 512)
8131 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
8132 (int) imm_expr
.X_add_number
);
8135 if (imm_expr
.X_op
== O_constant
8136 && imm_expr
.X_add_number
>= 0
8137 && imm_expr
.X_add_number
< 0x10000)
8139 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
8141 else if (imm_expr
.X_op
== O_constant
8142 && imm_expr
.X_add_number
> -0x8000
8143 && imm_expr
.X_add_number
< 0)
8145 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8146 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
8147 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
8149 else if (CPU_HAS_SEQ (mips_opts
.arch
))
8152 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8153 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
8158 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8159 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
8162 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
8168 if (imm_expr
.X_op
== O_constant
8169 && imm_expr
.X_add_number
> -0x8000
8170 && imm_expr
.X_add_number
<= 0x8000)
8172 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8173 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
8174 dreg
, sreg
, BFD_RELOC_LO16
);
8178 load_register (AT
, &imm_expr
, dbl
);
8179 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
8185 if (imm_expr
.X_op
== O_constant
8186 && imm_expr
.X_add_number
> -0x8000
8187 && imm_expr
.X_add_number
<= 0x8000)
8189 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8190 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
8191 dreg
, sreg
, BFD_RELOC_LO16
);
8195 load_register (AT
, &imm_expr
, dbl
);
8196 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
8218 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8219 macro_build (NULL
, s
, "s,t", sreg
, AT
);
8224 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8226 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
8227 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
8230 * Is the double cfc1 instruction a bug in the mips assembler;
8231 * or is there a reason for it?
8234 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
8235 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
8236 macro_build (NULL
, "nop", "");
8237 expr1
.X_add_number
= 3;
8238 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
8239 expr1
.X_add_number
= 2;
8240 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
8241 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
8242 macro_build (NULL
, "nop", "");
8243 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
8245 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
8246 macro_build (NULL
, "nop", "");
8257 if (offset_expr
.X_add_number
>= 0x7fff)
8258 as_bad (_("Operand overflow"));
8259 if (!target_big_endian
)
8260 ++offset_expr
.X_add_number
;
8261 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8262 if (!target_big_endian
)
8263 --offset_expr
.X_add_number
;
8265 ++offset_expr
.X_add_number
;
8266 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8267 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
8268 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8281 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8282 as_bad (_("Operand overflow"));
8290 if (!target_big_endian
)
8291 offset_expr
.X_add_number
+= off
;
8292 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8293 if (!target_big_endian
)
8294 offset_expr
.X_add_number
-= off
;
8296 offset_expr
.X_add_number
+= off
;
8297 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8299 /* If necessary, move the result in tempreg to the final destination. */
8300 if (treg
== tempreg
)
8302 /* Protect second load's delay slot. */
8304 move_register (treg
, tempreg
);
8318 load_address (AT
, &offset_expr
, &used_at
);
8320 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8321 if (!target_big_endian
)
8322 expr1
.X_add_number
= off
;
8324 expr1
.X_add_number
= 0;
8325 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8326 if (!target_big_endian
)
8327 expr1
.X_add_number
= 0;
8329 expr1
.X_add_number
= off
;
8330 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8336 load_address (AT
, &offset_expr
, &used_at
);
8338 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8339 if (target_big_endian
)
8340 expr1
.X_add_number
= 0;
8341 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
8342 treg
, BFD_RELOC_LO16
, AT
);
8343 if (target_big_endian
)
8344 expr1
.X_add_number
= 1;
8346 expr1
.X_add_number
= 0;
8347 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8348 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8349 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8354 if (offset_expr
.X_add_number
>= 0x7fff)
8355 as_bad (_("Operand overflow"));
8356 if (target_big_endian
)
8357 ++offset_expr
.X_add_number
;
8358 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8359 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
8360 if (target_big_endian
)
8361 --offset_expr
.X_add_number
;
8363 ++offset_expr
.X_add_number
;
8364 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8377 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8378 as_bad (_("Operand overflow"));
8379 if (!target_big_endian
)
8380 offset_expr
.X_add_number
+= off
;
8381 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8382 if (!target_big_endian
)
8383 offset_expr
.X_add_number
-= off
;
8385 offset_expr
.X_add_number
+= off
;
8386 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8400 load_address (AT
, &offset_expr
, &used_at
);
8402 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8403 if (!target_big_endian
)
8404 expr1
.X_add_number
= off
;
8406 expr1
.X_add_number
= 0;
8407 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8408 if (!target_big_endian
)
8409 expr1
.X_add_number
= 0;
8411 expr1
.X_add_number
= off
;
8412 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8417 load_address (AT
, &offset_expr
, &used_at
);
8419 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8420 if (!target_big_endian
)
8421 expr1
.X_add_number
= 0;
8422 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8423 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8424 if (!target_big_endian
)
8425 expr1
.X_add_number
= 1;
8427 expr1
.X_add_number
= 0;
8428 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8429 if (!target_big_endian
)
8430 expr1
.X_add_number
= 0;
8432 expr1
.X_add_number
= 1;
8433 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8434 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8435 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8439 /* FIXME: Check if this is one of the itbl macros, since they
8440 are added dynamically. */
8441 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8444 if (!mips_opts
.at
&& used_at
)
8445 as_bad (_("Macro used $at after \".set noat\""));
8448 /* Implement macros in mips16 mode. */
8451 mips16_macro (struct mips_cl_insn
*ip
)
8454 int xreg
, yreg
, zreg
, tmp
;
8457 const char *s
, *s2
, *s3
;
8459 mask
= ip
->insn_mo
->mask
;
8461 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8462 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8463 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8465 expr1
.X_op
= O_constant
;
8466 expr1
.X_op_symbol
= NULL
;
8467 expr1
.X_add_symbol
= NULL
;
8468 expr1
.X_add_number
= 1;
8488 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8489 expr1
.X_add_number
= 2;
8490 macro_build (&expr1
, "bnez", "x,p", yreg
);
8491 macro_build (NULL
, "break", "6", 7);
8493 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8494 since that causes an overflow. We should do that as well,
8495 but I don't see how to do the comparisons without a temporary
8498 macro_build (NULL
, s
, "x", zreg
);
8518 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8519 expr1
.X_add_number
= 2;
8520 macro_build (&expr1
, "bnez", "x,p", yreg
);
8521 macro_build (NULL
, "break", "6", 7);
8523 macro_build (NULL
, s2
, "x", zreg
);
8529 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8530 macro_build (NULL
, "mflo", "x", zreg
);
8538 if (imm_expr
.X_op
!= O_constant
)
8539 as_bad (_("Unsupported large constant"));
8540 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8541 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8545 if (imm_expr
.X_op
!= O_constant
)
8546 as_bad (_("Unsupported large constant"));
8547 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8548 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8552 if (imm_expr
.X_op
!= O_constant
)
8553 as_bad (_("Unsupported large constant"));
8554 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8555 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8577 goto do_reverse_branch
;
8581 goto do_reverse_branch
;
8593 goto do_reverse_branch
;
8604 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8605 macro_build (&offset_expr
, s2
, "p");
8632 goto do_addone_branch_i
;
8637 goto do_addone_branch_i
;
8652 goto do_addone_branch_i
;
8659 if (imm_expr
.X_op
!= O_constant
)
8660 as_bad (_("Unsupported large constant"));
8661 ++imm_expr
.X_add_number
;
8664 macro_build (&imm_expr
, s
, s3
, xreg
);
8665 macro_build (&offset_expr
, s2
, "p");
8669 expr1
.X_add_number
= 0;
8670 macro_build (&expr1
, "slti", "x,8", yreg
);
8672 move_register (xreg
, yreg
);
8673 expr1
.X_add_number
= 2;
8674 macro_build (&expr1
, "bteqz", "p");
8675 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8679 /* For consistency checking, verify that all bits are specified either
8680 by the match/mask part of the instruction definition, or by the
8683 validate_mips_insn (const struct mips_opcode
*opc
)
8685 const char *p
= opc
->args
;
8687 unsigned long used_bits
= opc
->mask
;
8689 if ((used_bits
& opc
->match
) != opc
->match
)
8691 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8692 opc
->name
, opc
->args
);
8695 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8705 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8706 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8707 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8708 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8709 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8710 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8711 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8712 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8713 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8714 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8715 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8716 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8717 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8719 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8720 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8721 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8722 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8723 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8724 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8725 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8726 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8727 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8728 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8729 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
8730 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
8731 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
8732 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
8733 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
8736 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8737 c
, opc
->name
, opc
->args
);
8741 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8742 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8744 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8745 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8746 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8747 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8749 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8750 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8752 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8753 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8755 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8756 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8757 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8758 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8759 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8760 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8761 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8762 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8763 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8764 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8765 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8766 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8767 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8768 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8769 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8770 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8771 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8773 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8774 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8775 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8776 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8778 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8779 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8780 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8781 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8782 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8783 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8784 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8785 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8786 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8789 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8790 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8791 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8792 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8793 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8796 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8797 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8798 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8799 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8800 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8801 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8802 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8803 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8804 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8805 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8806 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8807 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8808 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8809 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8810 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8811 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8812 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8813 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8815 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8816 c
, opc
->name
, opc
->args
);
8820 if (used_bits
!= 0xffffffff)
8822 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8823 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8829 /* UDI immediates. */
8837 static const struct mips_immed mips_immed
[] = {
8838 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8839 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8840 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8841 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8845 /* Check whether an odd floating-point register is allowed. */
8847 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8849 const char *s
= insn
->name
;
8851 if (insn
->pinfo
== INSN_MACRO
)
8852 /* Let a macro pass, we'll catch it later when it is expanded. */
8855 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8857 /* Allow odd registers for single-precision ops. */
8858 switch (insn
->pinfo
& (FP_S
| FP_D
))
8862 return 1; /* both single precision - ok */
8864 return 0; /* both double precision - fail */
8869 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8870 s
= strchr (insn
->name
, '.');
8872 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8873 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8876 /* Single-precision coprocessor loads and moves are OK too. */
8877 if ((insn
->pinfo
& FP_S
)
8878 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8879 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8885 /* This routine assembles an instruction into its binary format. As a
8886 side effect, it sets one of the global variables imm_reloc or
8887 offset_reloc to the type of relocation to do if one of the operands
8888 is an address expression. */
8891 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8896 struct mips_opcode
*insn
;
8899 unsigned int lastregno
;
8900 unsigned int lastpos
= 0;
8901 unsigned int limlo
, limhi
;
8904 offsetT min_range
, max_range
;
8910 /* If the instruction contains a '.', we first try to match an instruction
8911 including the '.'. Then we try again without the '.'. */
8913 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8916 /* If we stopped on whitespace, then replace the whitespace with null for
8917 the call to hash_find. Save the character we replaced just in case we
8918 have to re-parse the instruction. */
8925 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8927 /* If we didn't find the instruction in the opcode table, try again, but
8928 this time with just the instruction up to, but not including the
8932 /* Restore the character we overwrite above (if any). */
8936 /* Scan up to the first '.' or whitespace. */
8938 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8942 /* If we did not find a '.', then we can quit now. */
8945 insn_error
= _("Unrecognized opcode");
8949 /* Lookup the instruction in the hash table. */
8951 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8953 insn_error
= _("Unrecognized opcode");
8963 gas_assert (strcmp (insn
->name
, str
) == 0);
8965 ok
= is_opcode_valid (insn
);
8968 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8969 && strcmp (insn
->name
, insn
[1].name
) == 0)
8978 static char buf
[100];
8980 _("opcode not supported on this processor: %s (%s)"),
8981 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8982 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8991 create_insn (ip
, insn
);
8994 lastregno
= 0xffffffff;
8995 for (args
= insn
->args
;; ++args
)
8999 s
+= strspn (s
, " \t");
9003 case '\0': /* end of args */
9008 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
9009 my_getExpression (&imm_expr
, s
);
9010 check_absolute_expr (ip
, &imm_expr
);
9011 if ((unsigned long) imm_expr
.X_add_number
!= 1
9012 && (unsigned long) imm_expr
.X_add_number
!= 3)
9014 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
9015 (unsigned long) imm_expr
.X_add_number
);
9017 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
9018 imm_expr
.X_op
= O_absent
;
9022 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
9023 my_getExpression (&imm_expr
, s
);
9024 check_absolute_expr (ip
, &imm_expr
);
9025 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
9027 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9028 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
9030 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
9031 imm_expr
.X_op
= O_absent
;
9035 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
9036 my_getExpression (&imm_expr
, s
);
9037 check_absolute_expr (ip
, &imm_expr
);
9038 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
9040 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9041 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
9043 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
9044 imm_expr
.X_op
= O_absent
;
9048 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9049 my_getExpression (&imm_expr
, s
);
9050 check_absolute_expr (ip
, &imm_expr
);
9051 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
9053 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9054 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
9056 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
9057 imm_expr
.X_op
= O_absent
;
9061 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9062 my_getExpression (&imm_expr
, s
);
9063 check_absolute_expr (ip
, &imm_expr
);
9064 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
9066 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9067 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
9069 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
9070 imm_expr
.X_op
= O_absent
;
9074 case '7': /* Four DSP accumulators in bits 11,12. */
9075 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
9076 s
[3] >= '0' && s
[3] <= '3')
9080 INSERT_OPERAND (DSPACC
, *ip
, regno
);
9084 as_bad (_("Invalid dsp acc register"));
9087 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9088 my_getExpression (&imm_expr
, s
);
9089 check_absolute_expr (ip
, &imm_expr
);
9090 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
9092 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9094 (unsigned long) imm_expr
.X_add_number
);
9096 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
9097 imm_expr
.X_op
= O_absent
;
9101 case '9': /* Four DSP accumulators in bits 21,22. */
9102 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
9103 s
[3] >= '0' && s
[3] <= '3')
9107 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
9111 as_bad (_("Invalid dsp acc register"));
9114 case '0': /* DSP 6-bit signed immediate in bit 20. */
9115 my_getExpression (&imm_expr
, s
);
9116 check_absolute_expr (ip
, &imm_expr
);
9117 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
9118 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
9119 if (imm_expr
.X_add_number
< min_range
||
9120 imm_expr
.X_add_number
> max_range
)
9122 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9123 (long) min_range
, (long) max_range
,
9124 (long) imm_expr
.X_add_number
);
9126 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
9127 imm_expr
.X_op
= O_absent
;
9131 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9132 my_getExpression (&imm_expr
, s
);
9133 check_absolute_expr (ip
, &imm_expr
);
9134 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
9136 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9138 (unsigned long) imm_expr
.X_add_number
);
9140 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
9141 imm_expr
.X_op
= O_absent
;
9145 case ':': /* DSP 7-bit signed immediate in bit 19. */
9146 my_getExpression (&imm_expr
, s
);
9147 check_absolute_expr (ip
, &imm_expr
);
9148 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
9149 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
9150 if (imm_expr
.X_add_number
< min_range
||
9151 imm_expr
.X_add_number
> max_range
)
9153 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9154 (long) min_range
, (long) max_range
,
9155 (long) imm_expr
.X_add_number
);
9157 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
9158 imm_expr
.X_op
= O_absent
;
9162 case '@': /* DSP 10-bit signed immediate in bit 16. */
9163 my_getExpression (&imm_expr
, s
);
9164 check_absolute_expr (ip
, &imm_expr
);
9165 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
9166 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
9167 if (imm_expr
.X_add_number
< min_range
||
9168 imm_expr
.X_add_number
> max_range
)
9170 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9171 (long) min_range
, (long) max_range
,
9172 (long) imm_expr
.X_add_number
);
9174 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
9175 imm_expr
.X_op
= O_absent
;
9179 case '!': /* MT usermode flag bit. */
9180 my_getExpression (&imm_expr
, s
);
9181 check_absolute_expr (ip
, &imm_expr
);
9182 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
9183 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9184 (unsigned long) imm_expr
.X_add_number
);
9185 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
9186 imm_expr
.X_op
= O_absent
;
9190 case '$': /* MT load high flag bit. */
9191 my_getExpression (&imm_expr
, s
);
9192 check_absolute_expr (ip
, &imm_expr
);
9193 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
9194 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9195 (unsigned long) imm_expr
.X_add_number
);
9196 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
9197 imm_expr
.X_op
= O_absent
;
9201 case '*': /* Four DSP accumulators in bits 18,19. */
9202 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
9203 s
[3] >= '0' && s
[3] <= '3')
9207 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
9211 as_bad (_("Invalid dsp/smartmips acc register"));
9214 case '&': /* Four DSP accumulators in bits 13,14. */
9215 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
9216 s
[3] >= '0' && s
[3] <= '3')
9220 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
9224 as_bad (_("Invalid dsp/smartmips acc register"));
9236 INSERT_OPERAND (RS
, *ip
, lastregno
);
9240 INSERT_OPERAND (RT
, *ip
, lastregno
);
9244 INSERT_OPERAND (FT
, *ip
, lastregno
);
9248 INSERT_OPERAND (FS
, *ip
, lastregno
);
9254 /* Handle optional base register.
9255 Either the base register is omitted or
9256 we must have a left paren. */
9257 /* This is dependent on the next operand specifier
9258 is a base register specification. */
9259 gas_assert (args
[1] == 'b');
9263 case ')': /* These must match exactly. */
9270 case '+': /* Opcode extension character. */
9273 case '1': /* UDI immediates. */
9278 const struct mips_immed
*imm
= mips_immed
;
9280 while (imm
->type
&& imm
->type
!= *args
)
9284 my_getExpression (&imm_expr
, s
);
9285 check_absolute_expr (ip
, &imm_expr
);
9286 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
9288 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9289 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
9290 (unsigned long) imm_expr
.X_add_number
,
9291 (unsigned long) imm_expr
.X_add_number
);
9292 imm_expr
.X_add_number
&= imm
->mask
;
9294 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
9296 imm_expr
.X_op
= O_absent
;
9301 case 'A': /* ins/ext position, becomes LSB. */
9310 my_getExpression (&imm_expr
, s
);
9311 check_absolute_expr (ip
, &imm_expr
);
9312 if ((unsigned long) imm_expr
.X_add_number
< limlo
9313 || (unsigned long) imm_expr
.X_add_number
> limhi
)
9315 as_bad (_("Improper position (%lu)"),
9316 (unsigned long) imm_expr
.X_add_number
);
9317 imm_expr
.X_add_number
= limlo
;
9319 lastpos
= imm_expr
.X_add_number
;
9320 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9321 imm_expr
.X_op
= O_absent
;
9325 case 'B': /* ins size, becomes MSB. */
9334 my_getExpression (&imm_expr
, s
);
9335 check_absolute_expr (ip
, &imm_expr
);
9336 /* Check for negative input so that small negative numbers
9337 will not succeed incorrectly. The checks against
9338 (pos+size) transitively check "size" itself,
9339 assuming that "pos" is reasonable. */
9340 if ((long) imm_expr
.X_add_number
< 0
9341 || ((unsigned long) imm_expr
.X_add_number
9343 || ((unsigned long) imm_expr
.X_add_number
9346 as_bad (_("Improper insert size (%lu, position %lu)"),
9347 (unsigned long) imm_expr
.X_add_number
,
9348 (unsigned long) lastpos
);
9349 imm_expr
.X_add_number
= limlo
- lastpos
;
9351 INSERT_OPERAND (INSMSB
, *ip
,
9352 lastpos
+ imm_expr
.X_add_number
- 1);
9353 imm_expr
.X_op
= O_absent
;
9357 case 'C': /* ext size, becomes MSBD. */
9370 my_getExpression (&imm_expr
, s
);
9371 check_absolute_expr (ip
, &imm_expr
);
9372 /* Check for negative input so that small negative numbers
9373 will not succeed incorrectly. The checks against
9374 (pos+size) transitively check "size" itself,
9375 assuming that "pos" is reasonable. */
9376 if ((long) imm_expr
.X_add_number
< 0
9377 || ((unsigned long) imm_expr
.X_add_number
9379 || ((unsigned long) imm_expr
.X_add_number
9382 as_bad (_("Improper extract size (%lu, position %lu)"),
9383 (unsigned long) imm_expr
.X_add_number
,
9384 (unsigned long) lastpos
);
9385 imm_expr
.X_add_number
= limlo
- lastpos
;
9387 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9388 imm_expr
.X_op
= O_absent
;
9393 /* +D is for disassembly only; never match. */
9397 /* "+I" is like "I", except that imm2_expr is used. */
9398 my_getExpression (&imm2_expr
, s
);
9399 if (imm2_expr
.X_op
!= O_big
9400 && imm2_expr
.X_op
!= O_constant
)
9401 insn_error
= _("absolute expression required");
9402 if (HAVE_32BIT_GPRS
)
9403 normalize_constant_expr (&imm2_expr
);
9407 case 'T': /* Coprocessor register. */
9408 /* +T is for disassembly only; never match. */
9411 case 't': /* Coprocessor register number. */
9412 if (s
[0] == '$' && ISDIGIT (s
[1]))
9422 while (ISDIGIT (*s
));
9424 as_bad (_("Invalid register number (%d)"), regno
);
9427 INSERT_OPERAND (RT
, *ip
, regno
);
9432 as_bad (_("Invalid coprocessor 0 register number"));
9436 /* bbit[01] and bbit[01]32 bit index. Give error if index
9437 is not in the valid range. */
9438 my_getExpression (&imm_expr
, s
);
9439 check_absolute_expr (ip
, &imm_expr
);
9440 if ((unsigned) imm_expr
.X_add_number
> 31)
9442 as_bad (_("Improper bit index (%lu)"),
9443 (unsigned long) imm_expr
.X_add_number
);
9444 imm_expr
.X_add_number
= 0;
9446 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9447 imm_expr
.X_op
= O_absent
;
9452 /* bbit[01] bit index when bbit is used but we generate
9453 bbit[01]32 because the index is over 32. Move to the
9454 next candidate if index is not in the valid range. */
9455 my_getExpression (&imm_expr
, s
);
9456 check_absolute_expr (ip
, &imm_expr
);
9457 if ((unsigned) imm_expr
.X_add_number
< 32
9458 || (unsigned) imm_expr
.X_add_number
> 63)
9460 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9461 imm_expr
.X_op
= O_absent
;
9466 /* cins, cins32, exts and exts32 position field. Give error
9467 if it's not in the valid range. */
9468 my_getExpression (&imm_expr
, s
);
9469 check_absolute_expr (ip
, &imm_expr
);
9470 if ((unsigned) imm_expr
.X_add_number
> 31)
9472 as_bad (_("Improper position (%lu)"),
9473 (unsigned long) imm_expr
.X_add_number
);
9474 imm_expr
.X_add_number
= 0;
9476 /* Make the pos explicit to simplify +S. */
9477 lastpos
= imm_expr
.X_add_number
+ 32;
9478 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9479 imm_expr
.X_op
= O_absent
;
9484 /* cins, cins32, exts and exts32 position field. Move to
9485 the next candidate if it's not in the valid range. */
9486 my_getExpression (&imm_expr
, s
);
9487 check_absolute_expr (ip
, &imm_expr
);
9488 if ((unsigned) imm_expr
.X_add_number
< 32
9489 || (unsigned) imm_expr
.X_add_number
> 63)
9491 lastpos
= imm_expr
.X_add_number
;
9492 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9493 imm_expr
.X_op
= O_absent
;
9498 /* cins and exts length-minus-one field. */
9499 my_getExpression (&imm_expr
, s
);
9500 check_absolute_expr (ip
, &imm_expr
);
9501 if ((unsigned long) imm_expr
.X_add_number
> 31)
9503 as_bad (_("Improper size (%lu)"),
9504 (unsigned long) imm_expr
.X_add_number
);
9505 imm_expr
.X_add_number
= 0;
9507 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9508 imm_expr
.X_op
= O_absent
;
9513 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9514 length-minus-one field. */
9515 my_getExpression (&imm_expr
, s
);
9516 check_absolute_expr (ip
, &imm_expr
);
9517 if ((long) imm_expr
.X_add_number
< 0
9518 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9520 as_bad (_("Improper size (%lu)"),
9521 (unsigned long) imm_expr
.X_add_number
);
9522 imm_expr
.X_add_number
= 0;
9524 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9525 imm_expr
.X_op
= O_absent
;
9530 /* seqi/snei immediate field. */
9531 my_getExpression (&imm_expr
, s
);
9532 check_absolute_expr (ip
, &imm_expr
);
9533 if ((long) imm_expr
.X_add_number
< -512
9534 || (long) imm_expr
.X_add_number
>= 512)
9536 as_bad (_("Improper immediate (%ld)"),
9537 (long) imm_expr
.X_add_number
);
9538 imm_expr
.X_add_number
= 0;
9540 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9541 imm_expr
.X_op
= O_absent
;
9545 case 'a': /* 8-bit signed offset in bit 6 */
9546 my_getExpression (&imm_expr
, s
);
9547 check_absolute_expr (ip
, &imm_expr
);
9548 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
9549 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
9550 if (imm_expr
.X_add_number
< min_range
9551 || imm_expr
.X_add_number
> max_range
)
9553 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9554 (long) min_range
, (long) max_range
,
9555 (long) imm_expr
.X_add_number
);
9557 INSERT_OPERAND (OFFSET_A
, *ip
, imm_expr
.X_add_number
);
9558 imm_expr
.X_op
= O_absent
;
9562 case 'b': /* 8-bit signed offset in bit 3 */
9563 my_getExpression (&imm_expr
, s
);
9564 check_absolute_expr (ip
, &imm_expr
);
9565 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
9566 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
9567 if (imm_expr
.X_add_number
< min_range
9568 || imm_expr
.X_add_number
> max_range
)
9570 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9571 (long) min_range
, (long) max_range
,
9572 (long) imm_expr
.X_add_number
);
9574 INSERT_OPERAND (OFFSET_B
, *ip
, imm_expr
.X_add_number
);
9575 imm_expr
.X_op
= O_absent
;
9579 case 'c': /* 9-bit signed offset in bit 6 */
9580 my_getExpression (&imm_expr
, s
);
9581 check_absolute_expr (ip
, &imm_expr
);
9582 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
9583 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
9584 /* We check the offset range before adjusted. */
9587 if (imm_expr
.X_add_number
< min_range
9588 || imm_expr
.X_add_number
> max_range
)
9590 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9591 (long) min_range
, (long) max_range
,
9592 (long) imm_expr
.X_add_number
);
9594 if (imm_expr
.X_add_number
& 0xf)
9596 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9597 (long) imm_expr
.X_add_number
);
9599 /* Right shift 4 bits to adjust the offset operand. */
9600 INSERT_OPERAND (OFFSET_C
, *ip
, imm_expr
.X_add_number
>> 4);
9601 imm_expr
.X_op
= O_absent
;
9606 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
9608 if (regno
== AT
&& mips_opts
.at
)
9610 if (mips_opts
.at
== ATREG
)
9611 as_warn (_("used $at without \".set noat\""));
9613 as_warn (_("used $%u with \".set at=$%u\""),
9614 regno
, mips_opts
.at
);
9616 INSERT_OPERAND (RZ
, *ip
, regno
);
9620 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
9622 INSERT_OPERAND (FZ
, *ip
, regno
);
9626 as_bad (_("Internal error: bad mips opcode "
9627 "(unknown extension operand type `+%c'): %s %s"),
9628 *args
, insn
->name
, insn
->args
);
9629 /* Further processing is fruitless. */
9634 case '<': /* must be at least one digit */
9636 * According to the manual, if the shift amount is greater
9637 * than 31 or less than 0, then the shift amount should be
9638 * mod 32. In reality the mips assembler issues an error.
9639 * We issue a warning and mask out all but the low 5 bits.
9641 my_getExpression (&imm_expr
, s
);
9642 check_absolute_expr (ip
, &imm_expr
);
9643 if ((unsigned long) imm_expr
.X_add_number
> 31)
9644 as_warn (_("Improper shift amount (%lu)"),
9645 (unsigned long) imm_expr
.X_add_number
);
9646 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9647 imm_expr
.X_op
= O_absent
;
9651 case '>': /* shift amount minus 32 */
9652 my_getExpression (&imm_expr
, s
);
9653 check_absolute_expr (ip
, &imm_expr
);
9654 if ((unsigned long) imm_expr
.X_add_number
< 32
9655 || (unsigned long) imm_expr
.X_add_number
> 63)
9657 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9658 imm_expr
.X_op
= O_absent
;
9662 case 'k': /* CACHE code. */
9663 case 'h': /* PREFX code. */
9664 case '1': /* SYNC type. */
9665 my_getExpression (&imm_expr
, s
);
9666 check_absolute_expr (ip
, &imm_expr
);
9667 if ((unsigned long) imm_expr
.X_add_number
> 31)
9668 as_warn (_("Invalid value for `%s' (%lu)"),
9670 (unsigned long) imm_expr
.X_add_number
);
9673 if (mips_fix_cn63xxp1
&& strcmp ("pref", insn
->name
) == 0)
9674 switch (imm_expr
.X_add_number
)
9683 case 31: /* These are ok. */
9686 default: /* The rest must be changed to 28. */
9687 imm_expr
.X_add_number
= 28;
9690 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9692 else if (*args
== 'h')
9693 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9695 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9696 imm_expr
.X_op
= O_absent
;
9700 case 'c': /* BREAK code. */
9701 my_getExpression (&imm_expr
, s
);
9702 check_absolute_expr (ip
, &imm_expr
);
9703 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9704 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9706 (unsigned long) imm_expr
.X_add_number
);
9707 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9708 imm_expr
.X_op
= O_absent
;
9712 case 'q': /* Lower BREAK code. */
9713 my_getExpression (&imm_expr
, s
);
9714 check_absolute_expr (ip
, &imm_expr
);
9715 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9716 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9718 (unsigned long) imm_expr
.X_add_number
);
9719 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9720 imm_expr
.X_op
= O_absent
;
9724 case 'B': /* 20-bit SYSCALL/BREAK code. */
9725 my_getExpression (&imm_expr
, s
);
9726 check_absolute_expr (ip
, &imm_expr
);
9727 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9728 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9730 (unsigned long) imm_expr
.X_add_number
);
9731 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9732 imm_expr
.X_op
= O_absent
;
9736 case 'C': /* Coprocessor code. */
9737 my_getExpression (&imm_expr
, s
);
9738 check_absolute_expr (ip
, &imm_expr
);
9739 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9741 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9742 (unsigned long) imm_expr
.X_add_number
);
9743 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9745 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9746 imm_expr
.X_op
= O_absent
;
9750 case 'J': /* 19-bit WAIT code. */
9751 my_getExpression (&imm_expr
, s
);
9752 check_absolute_expr (ip
, &imm_expr
);
9753 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9755 as_warn (_("Illegal 19-bit code (%lu)"),
9756 (unsigned long) imm_expr
.X_add_number
);
9757 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9759 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9760 imm_expr
.X_op
= O_absent
;
9764 case 'P': /* Performance register. */
9765 my_getExpression (&imm_expr
, s
);
9766 check_absolute_expr (ip
, &imm_expr
);
9767 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9768 as_warn (_("Invalid performance register (%lu)"),
9769 (unsigned long) imm_expr
.X_add_number
);
9770 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9771 imm_expr
.X_op
= O_absent
;
9775 case 'G': /* Coprocessor destination register. */
9776 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9777 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9779 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9780 INSERT_OPERAND (RD
, *ip
, regno
);
9789 case 'b': /* Base register. */
9790 case 'd': /* Destination register. */
9791 case 's': /* Source register. */
9792 case 't': /* Target register. */
9793 case 'r': /* Both target and source. */
9794 case 'v': /* Both dest and source. */
9795 case 'w': /* Both dest and target. */
9796 case 'E': /* Coprocessor target register. */
9797 case 'K': /* RDHWR destination register. */
9798 case 'x': /* Ignore register name. */
9799 case 'z': /* Must be zero register. */
9800 case 'U': /* Destination register (CLO/CLZ). */
9801 case 'g': /* Coprocessor destination register. */
9803 if (*args
== 'E' || *args
== 'K')
9804 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9807 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9808 if (regno
== AT
&& mips_opts
.at
)
9810 if (mips_opts
.at
== ATREG
)
9811 as_warn (_("Used $at without \".set noat\""));
9813 as_warn (_("Used $%u with \".set at=$%u\""),
9814 regno
, mips_opts
.at
);
9824 if (c
== 'r' || c
== 'v' || c
== 'w')
9831 /* 'z' only matches $0. */
9832 if (c
== 'z' && regno
!= 0)
9835 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
9837 if (regno
== lastregno
)
9840 = _("Source and destination must be different");
9843 if (regno
== 31 && lastregno
== 0xffffffff)
9846 = _("A destination register must be supplied");
9850 /* Now that we have assembled one operand, we use the args
9851 string to figure out where it goes in the instruction. */
9858 INSERT_OPERAND (RS
, *ip
, regno
);
9863 INSERT_OPERAND (RD
, *ip
, regno
);
9866 INSERT_OPERAND (RD
, *ip
, regno
);
9867 INSERT_OPERAND (RT
, *ip
, regno
);
9872 INSERT_OPERAND (RT
, *ip
, regno
);
9875 /* This case exists because on the r3000 trunc
9876 expands into a macro which requires a gp
9877 register. On the r6000 or r4000 it is
9878 assembled into a single instruction which
9879 ignores the register. Thus the insn version
9880 is MIPS_ISA2 and uses 'x', and the macro
9881 version is MIPS_ISA1 and uses 't'. */
9884 /* This case is for the div instruction, which
9885 acts differently if the destination argument
9886 is $0. This only matches $0, and is checked
9887 outside the switch. */
9897 INSERT_OPERAND (RS
, *ip
, lastregno
);
9900 INSERT_OPERAND (RT
, *ip
, lastregno
);
9905 case 'O': /* MDMX alignment immediate constant. */
9906 my_getExpression (&imm_expr
, s
);
9907 check_absolute_expr (ip
, &imm_expr
);
9908 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9909 as_warn (_("Improper align amount (%ld), using low bits"),
9910 (long) imm_expr
.X_add_number
);
9911 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9912 imm_expr
.X_op
= O_absent
;
9916 case 'Q': /* MDMX vector, element sel, or const. */
9919 /* MDMX Immediate. */
9920 my_getExpression (&imm_expr
, s
);
9921 check_absolute_expr (ip
, &imm_expr
);
9922 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9923 as_warn (_("Invalid MDMX Immediate (%ld)"),
9924 (long) imm_expr
.X_add_number
);
9925 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9926 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9927 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9929 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9930 imm_expr
.X_op
= O_absent
;
9934 /* Not MDMX Immediate. Fall through. */
9935 case 'X': /* MDMX destination register. */
9936 case 'Y': /* MDMX source register. */
9937 case 'Z': /* MDMX target register. */
9939 case 'D': /* Floating point destination register. */
9940 case 'S': /* Floating point source register. */
9941 case 'T': /* Floating point target register. */
9942 case 'R': /* Floating point source register. */
9947 || (mips_opts
.ase_mdmx
9948 && (ip
->insn_mo
->pinfo
& FP_D
)
9949 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9950 | INSN_COPROC_MEMORY_DELAY
9951 | INSN_LOAD_COPROC_DELAY
9952 | INSN_LOAD_MEMORY_DELAY
9953 | INSN_STORE_MEMORY
))))
9956 if (reg_lookup (&s
, rtype
, ®no
))
9958 if ((regno
& 1) != 0
9960 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9961 as_warn (_("Float register should be even, was %d"),
9969 if (c
== 'V' || c
== 'W')
9980 INSERT_OPERAND (FD
, *ip
, regno
);
9985 INSERT_OPERAND (FS
, *ip
, regno
);
9988 /* This is like 'Z', but also needs to fix the MDMX
9989 vector/scalar select bits. Note that the
9990 scalar immediate case is handled above. */
9993 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9994 int max_el
= (is_qh
? 3 : 7);
9996 my_getExpression(&imm_expr
, s
);
9997 check_absolute_expr (ip
, &imm_expr
);
9999 if (imm_expr
.X_add_number
> max_el
)
10000 as_bad (_("Bad element selector %ld"),
10001 (long) imm_expr
.X_add_number
);
10002 imm_expr
.X_add_number
&= max_el
;
10003 ip
->insn_opcode
|= (imm_expr
.X_add_number
10006 imm_expr
.X_op
= O_absent
;
10008 as_warn (_("Expecting ']' found '%s'"), s
);
10014 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
10015 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
10018 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
10021 /* Fall through. */
10025 INSERT_OPERAND (FT
, *ip
, regno
);
10028 INSERT_OPERAND (FR
, *ip
, regno
);
10038 INSERT_OPERAND (FS
, *ip
, lastregno
);
10041 INSERT_OPERAND (FT
, *ip
, lastregno
);
10047 my_getExpression (&imm_expr
, s
);
10048 if (imm_expr
.X_op
!= O_big
10049 && imm_expr
.X_op
!= O_constant
)
10050 insn_error
= _("absolute expression required");
10051 if (HAVE_32BIT_GPRS
)
10052 normalize_constant_expr (&imm_expr
);
10057 my_getExpression (&offset_expr
, s
);
10058 normalize_address_expr (&offset_expr
);
10059 *imm_reloc
= BFD_RELOC_32
;
10072 unsigned char temp
[8];
10074 unsigned int length
;
10079 /* These only appear as the last operand in an
10080 instruction, and every instruction that accepts
10081 them in any variant accepts them in all variants.
10082 This means we don't have to worry about backing out
10083 any changes if the instruction does not match.
10085 The difference between them is the size of the
10086 floating point constant and where it goes. For 'F'
10087 and 'L' the constant is 64 bits; for 'f' and 'l' it
10088 is 32 bits. Where the constant is placed is based
10089 on how the MIPS assembler does things:
10092 f -- immediate value
10095 The .lit4 and .lit8 sections are only used if
10096 permitted by the -G argument.
10098 The code below needs to know whether the target register
10099 is 32 or 64 bits wide. It relies on the fact 'f' and
10100 'F' are used with GPR-based instructions and 'l' and
10101 'L' are used with FPR-based instructions. */
10103 f64
= *args
== 'F' || *args
== 'L';
10104 using_gprs
= *args
== 'F' || *args
== 'f';
10106 save_in
= input_line_pointer
;
10107 input_line_pointer
= s
;
10108 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
10110 s
= input_line_pointer
;
10111 input_line_pointer
= save_in
;
10112 if (err
!= NULL
&& *err
!= '\0')
10114 as_bad (_("Bad floating point constant: %s"), err
);
10115 memset (temp
, '\0', sizeof temp
);
10116 length
= f64
? 8 : 4;
10119 gas_assert (length
== (unsigned) (f64
? 8 : 4));
10123 && (g_switch_value
< 4
10124 || (temp
[0] == 0 && temp
[1] == 0)
10125 || (temp
[2] == 0 && temp
[3] == 0))))
10127 imm_expr
.X_op
= O_constant
;
10128 if (!target_big_endian
)
10129 imm_expr
.X_add_number
= bfd_getl32 (temp
);
10131 imm_expr
.X_add_number
= bfd_getb32 (temp
);
10133 else if (length
> 4
10134 && !mips_disable_float_construction
10135 /* Constants can only be constructed in GPRs and
10136 copied to FPRs if the GPRs are at least as wide
10137 as the FPRs. Force the constant into memory if
10138 we are using 64-bit FPRs but the GPRs are only
10141 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
10142 && ((temp
[0] == 0 && temp
[1] == 0)
10143 || (temp
[2] == 0 && temp
[3] == 0))
10144 && ((temp
[4] == 0 && temp
[5] == 0)
10145 || (temp
[6] == 0 && temp
[7] == 0)))
10147 /* The value is simple enough to load with a couple of
10148 instructions. If using 32-bit registers, set
10149 imm_expr to the high order 32 bits and offset_expr to
10150 the low order 32 bits. Otherwise, set imm_expr to
10151 the entire 64 bit constant. */
10152 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
10154 imm_expr
.X_op
= O_constant
;
10155 offset_expr
.X_op
= O_constant
;
10156 if (!target_big_endian
)
10158 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
10159 offset_expr
.X_add_number
= bfd_getl32 (temp
);
10163 imm_expr
.X_add_number
= bfd_getb32 (temp
);
10164 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
10166 if (offset_expr
.X_add_number
== 0)
10167 offset_expr
.X_op
= O_absent
;
10169 else if (sizeof (imm_expr
.X_add_number
) > 4)
10171 imm_expr
.X_op
= O_constant
;
10172 if (!target_big_endian
)
10173 imm_expr
.X_add_number
= bfd_getl64 (temp
);
10175 imm_expr
.X_add_number
= bfd_getb64 (temp
);
10179 imm_expr
.X_op
= O_big
;
10180 imm_expr
.X_add_number
= 4;
10181 if (!target_big_endian
)
10183 generic_bignum
[0] = bfd_getl16 (temp
);
10184 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
10185 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
10186 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
10190 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
10191 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
10192 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
10193 generic_bignum
[3] = bfd_getb16 (temp
);
10199 const char *newname
;
10202 /* Switch to the right section. */
10204 subseg
= now_subseg
;
10207 default: /* unused default case avoids warnings. */
10209 newname
= RDATA_SECTION_NAME
;
10210 if (g_switch_value
>= 8)
10214 newname
= RDATA_SECTION_NAME
;
10217 gas_assert (g_switch_value
>= 4);
10221 new_seg
= subseg_new (newname
, (subsegT
) 0);
10223 bfd_set_section_flags (stdoutput
, new_seg
,
10228 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
10229 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
10230 record_alignment (new_seg
, 4);
10232 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
10233 if (seg
== now_seg
)
10234 as_bad (_("Can't use floating point insn in this section"));
10236 /* Set the argument to the current address in the
10238 offset_expr
.X_op
= O_symbol
;
10239 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
10240 offset_expr
.X_add_number
= 0;
10242 /* Put the floating point number into the section. */
10243 p
= frag_more ((int) length
);
10244 memcpy (p
, temp
, length
);
10246 /* Switch back to the original section. */
10247 subseg_set (seg
, subseg
);
10252 case 'i': /* 16-bit unsigned immediate. */
10253 case 'j': /* 16-bit signed immediate. */
10254 *imm_reloc
= BFD_RELOC_LO16
;
10255 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
10258 offsetT minval
, maxval
;
10260 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
10261 && strcmp (insn
->name
, insn
[1].name
) == 0);
10263 /* If the expression was written as an unsigned number,
10264 only treat it as signed if there are no more
10268 && sizeof (imm_expr
.X_add_number
) <= 4
10269 && imm_expr
.X_op
== O_constant
10270 && imm_expr
.X_add_number
< 0
10271 && imm_expr
.X_unsigned
10272 && HAVE_64BIT_GPRS
)
10275 /* For compatibility with older assemblers, we accept
10276 0x8000-0xffff as signed 16-bit numbers when only
10277 signed numbers are allowed. */
10279 minval
= 0, maxval
= 0xffff;
10281 minval
= -0x8000, maxval
= 0x7fff;
10283 minval
= -0x8000, maxval
= 0xffff;
10285 if (imm_expr
.X_op
!= O_constant
10286 || imm_expr
.X_add_number
< minval
10287 || imm_expr
.X_add_number
> maxval
)
10291 if (imm_expr
.X_op
== O_constant
10292 || imm_expr
.X_op
== O_big
)
10293 as_bad (_("Expression out of range"));
10299 case 'o': /* 16-bit offset. */
10300 offset_reloc
[0] = BFD_RELOC_LO16
;
10301 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10302 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10304 /* Check whether there is only a single bracketed expression
10305 left. If so, it must be the base register and the
10306 constant must be zero. */
10307 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
10309 offset_expr
.X_op
= O_constant
;
10310 offset_expr
.X_add_number
= 0;
10314 /* If this value won't fit into a 16 bit offset, then go
10315 find a macro that will generate the 32 bit offset
10317 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
10318 && (offset_expr
.X_op
!= O_constant
10319 || offset_expr
.X_add_number
>= 0x8000
10320 || offset_expr
.X_add_number
< -0x8000))
10326 case 'p': /* PC-relative offset. */
10327 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
10328 my_getExpression (&offset_expr
, s
);
10332 case 'u': /* Upper 16 bits. */
10333 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
10334 && imm_expr
.X_op
== O_constant
10335 && (imm_expr
.X_add_number
< 0
10336 || imm_expr
.X_add_number
>= 0x10000))
10337 as_bad (_("lui expression (%lu) not in range 0..65535"),
10338 (unsigned long) imm_expr
.X_add_number
);
10342 case 'a': /* 26-bit address. */
10343 my_getExpression (&offset_expr
, s
);
10345 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
10348 case 'N': /* 3-bit branch condition code. */
10349 case 'M': /* 3-bit compare condition code. */
10351 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
10352 rtype
|= RTYPE_FCC
;
10353 if (!reg_lookup (&s
, rtype
, ®no
))
10355 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
10356 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
10357 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
10358 && (regno
& 1) != 0)
10359 as_warn (_("Condition code register should be even for %s, "
10362 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
10363 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
10364 && (regno
& 3) != 0)
10365 as_warn (_("Condition code register should be 0 or 4 for %s, "
10369 INSERT_OPERAND (BCC
, *ip
, regno
);
10371 INSERT_OPERAND (CCC
, *ip
, regno
);
10375 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
10386 while (ISDIGIT (*s
));
10389 c
= 8; /* Invalid sel value. */
10392 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10393 ip
->insn_opcode
|= c
;
10397 /* Must be at least one digit. */
10398 my_getExpression (&imm_expr
, s
);
10399 check_absolute_expr (ip
, &imm_expr
);
10401 if ((unsigned long) imm_expr
.X_add_number
10402 > (unsigned long) OP_MASK_VECBYTE
)
10404 as_bad (_("bad byte vector index (%ld)"),
10405 (long) imm_expr
.X_add_number
);
10406 imm_expr
.X_add_number
= 0;
10409 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
10410 imm_expr
.X_op
= O_absent
;
10415 my_getExpression (&imm_expr
, s
);
10416 check_absolute_expr (ip
, &imm_expr
);
10418 if ((unsigned long) imm_expr
.X_add_number
10419 > (unsigned long) OP_MASK_VECALIGN
)
10421 as_bad (_("bad byte vector index (%ld)"),
10422 (long) imm_expr
.X_add_number
);
10423 imm_expr
.X_add_number
= 0;
10426 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
10427 imm_expr
.X_op
= O_absent
;
10432 as_bad (_("Bad char = '%c'\n"), *args
);
10437 /* Args don't match. */
10438 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
10439 !strcmp (insn
->name
, insn
[1].name
))
10443 insn_error
= _("Illegal operands");
10447 *(--argsStart
) = save_c
;
10448 insn_error
= _("Illegal operands");
10453 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10455 /* This routine assembles an instruction into its binary format when
10456 assembling for the mips16. As a side effect, it sets one of the
10457 global variables imm_reloc or offset_reloc to the type of
10458 relocation to do if one of the operands is an address expression.
10459 It also sets mips16_small and mips16_ext if the user explicitly
10460 requested a small or extended instruction. */
10463 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
10467 struct mips_opcode
*insn
;
10469 unsigned int regno
;
10470 unsigned int lastregno
= 0;
10476 mips16_small
= FALSE
;
10477 mips16_ext
= FALSE
;
10479 for (s
= str
; ISLOWER (*s
); ++s
)
10491 if (s
[1] == 't' && s
[2] == ' ')
10494 mips16_small
= TRUE
;
10498 else if (s
[1] == 'e' && s
[2] == ' ')
10505 /* Fall through. */
10507 insn_error
= _("unknown opcode");
10511 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10512 mips16_small
= TRUE
;
10514 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10516 insn_error
= _("unrecognized opcode");
10525 gas_assert (strcmp (insn
->name
, str
) == 0);
10527 ok
= is_opcode_valid_16 (insn
);
10530 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10531 && strcmp (insn
->name
, insn
[1].name
) == 0)
10540 static char buf
[100];
10542 _("opcode not supported on this processor: %s (%s)"),
10543 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10544 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10551 create_insn (ip
, insn
);
10552 imm_expr
.X_op
= O_absent
;
10553 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10554 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10555 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10556 imm2_expr
.X_op
= O_absent
;
10557 offset_expr
.X_op
= O_absent
;
10558 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10559 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10560 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10561 for (args
= insn
->args
; 1; ++args
)
10568 /* In this switch statement we call break if we did not find
10569 a match, continue if we did find a match, or return if we
10578 /* Stuff the immediate value in now, if we can. */
10579 if (imm_expr
.X_op
== O_constant
10580 && *imm_reloc
> BFD_RELOC_UNUSED
10581 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
10582 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
10583 && insn
->pinfo
!= INSN_MACRO
)
10587 switch (*offset_reloc
)
10589 case BFD_RELOC_MIPS16_HI16_S
:
10590 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10593 case BFD_RELOC_MIPS16_HI16
:
10594 tmp
= imm_expr
.X_add_number
>> 16;
10597 case BFD_RELOC_MIPS16_LO16
:
10598 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10602 case BFD_RELOC_UNUSED
:
10603 tmp
= imm_expr
.X_add_number
;
10609 *offset_reloc
= BFD_RELOC_UNUSED
;
10611 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10612 tmp
, TRUE
, mips16_small
,
10613 mips16_ext
, &ip
->insn_opcode
,
10614 &ip
->use_extend
, &ip
->extend
);
10615 imm_expr
.X_op
= O_absent
;
10616 *imm_reloc
= BFD_RELOC_UNUSED
;
10630 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10633 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10649 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10651 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10655 /* Fall through. */
10666 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10668 if (c
== 'v' || c
== 'w')
10671 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10673 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10684 if (c
== 'v' || c
== 'w')
10686 regno
= mips16_to_32_reg_map
[lastregno
];
10700 regno
= mips32_to_16_reg_map
[regno
];
10705 regno
= ILLEGAL_REG
;
10710 regno
= ILLEGAL_REG
;
10715 regno
= ILLEGAL_REG
;
10720 if (regno
== AT
&& mips_opts
.at
)
10722 if (mips_opts
.at
== ATREG
)
10723 as_warn (_("used $at without \".set noat\""));
10725 as_warn (_("used $%u with \".set at=$%u\""),
10726 regno
, mips_opts
.at
);
10734 if (regno
== ILLEGAL_REG
)
10741 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10745 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10748 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10751 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10757 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10760 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10761 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10771 if (strncmp (s
, "$pc", 3) == 0)
10788 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10791 if (imm_expr
.X_op
!= O_constant
)
10794 ip
->use_extend
= TRUE
;
10799 /* We need to relax this instruction. */
10800 *offset_reloc
= *imm_reloc
;
10801 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10806 *imm_reloc
= BFD_RELOC_UNUSED
;
10807 /* Fall through. */
10814 my_getExpression (&imm_expr
, s
);
10815 if (imm_expr
.X_op
== O_register
)
10817 /* What we thought was an expression turned out to
10820 if (s
[0] == '(' && args
[1] == '(')
10822 /* It looks like the expression was omitted
10823 before a register indirection, which means
10824 that the expression is implicitly zero. We
10825 still set up imm_expr, so that we handle
10826 explicit extensions correctly. */
10827 imm_expr
.X_op
= O_constant
;
10828 imm_expr
.X_add_number
= 0;
10829 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10836 /* We need to relax this instruction. */
10837 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10846 /* We use offset_reloc rather than imm_reloc for the PC
10847 relative operands. This lets macros with both
10848 immediate and address operands work correctly. */
10849 my_getExpression (&offset_expr
, s
);
10851 if (offset_expr
.X_op
== O_register
)
10854 /* We need to relax this instruction. */
10855 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10859 case '6': /* break code */
10860 my_getExpression (&imm_expr
, s
);
10861 check_absolute_expr (ip
, &imm_expr
);
10862 if ((unsigned long) imm_expr
.X_add_number
> 63)
10863 as_warn (_("Invalid value for `%s' (%lu)"),
10865 (unsigned long) imm_expr
.X_add_number
);
10866 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10867 imm_expr
.X_op
= O_absent
;
10871 case 'a': /* 26 bit address */
10872 my_getExpression (&offset_expr
, s
);
10874 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10875 ip
->insn_opcode
<<= 16;
10878 case 'l': /* register list for entry macro */
10879 case 'L': /* register list for exit macro */
10889 unsigned int freg
, reg1
, reg2
;
10891 while (*s
== ' ' || *s
== ',')
10893 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10895 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10899 as_bad (_("can't parse register list"));
10909 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10910 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10912 as_bad (_("invalid register list"));
10916 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10918 mask
&= ~ (7 << 3);
10921 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10923 mask
&= ~ (7 << 3);
10926 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10927 mask
|= (reg2
- 3) << 3;
10928 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10929 mask
|= (reg2
- 15) << 1;
10930 else if (reg1
== RA
&& reg2
== RA
)
10934 as_bad (_("invalid register list"));
10938 /* The mask is filled in in the opcode table for the
10939 benefit of the disassembler. We remove it before
10940 applying the actual mask. */
10941 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10942 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10946 case 'm': /* Register list for save insn. */
10947 case 'M': /* Register list for restore insn. */
10950 int framesz
= 0, seen_framesz
= 0;
10951 int nargs
= 0, statics
= 0, sregs
= 0;
10955 unsigned int reg1
, reg2
;
10957 SKIP_SPACE_TABS (s
);
10960 SKIP_SPACE_TABS (s
);
10962 my_getExpression (&imm_expr
, s
);
10963 if (imm_expr
.X_op
== O_constant
)
10965 /* Handle the frame size. */
10968 as_bad (_("more than one frame size in list"));
10972 framesz
= imm_expr
.X_add_number
;
10973 imm_expr
.X_op
= O_absent
;
10978 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10980 as_bad (_("can't parse register list"));
10992 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10995 as_bad (_("can't parse register list"));
11000 while (reg1
<= reg2
)
11002 if (reg1
>= 4 && reg1
<= 7)
11006 nargs
|= 1 << (reg1
- 4);
11008 /* statics $a0-$a3 */
11009 statics
|= 1 << (reg1
- 4);
11011 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
11014 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
11016 else if (reg1
== 31)
11018 /* Add $ra to insn. */
11023 as_bad (_("unexpected register in list"));
11031 /* Encode args/statics combination. */
11032 if (nargs
& statics
)
11033 as_bad (_("arg/static registers overlap"));
11034 else if (nargs
== 0xf)
11035 /* All $a0-$a3 are args. */
11036 opcode
|= MIPS16_ALL_ARGS
<< 16;
11037 else if (statics
== 0xf)
11038 /* All $a0-$a3 are statics. */
11039 opcode
|= MIPS16_ALL_STATICS
<< 16;
11042 int narg
= 0, nstat
= 0;
11044 /* Count arg registers. */
11045 while (nargs
& 0x1)
11051 as_bad (_("invalid arg register list"));
11053 /* Count static registers. */
11054 while (statics
& 0x8)
11056 statics
= (statics
<< 1) & 0xf;
11060 as_bad (_("invalid static register list"));
11062 /* Encode args/statics. */
11063 opcode
|= ((narg
<< 2) | nstat
) << 16;
11066 /* Encode $s0/$s1. */
11067 if (sregs
& (1 << 0)) /* $s0 */
11069 if (sregs
& (1 << 1)) /* $s1 */
11075 /* Count regs $s2-$s8. */
11083 as_bad (_("invalid static register list"));
11084 /* Encode $s2-$s8. */
11085 opcode
|= nsreg
<< 24;
11088 /* Encode frame size. */
11090 as_bad (_("missing frame size"));
11091 else if ((framesz
& 7) != 0 || framesz
< 0
11092 || framesz
> 0xff * 8)
11093 as_bad (_("invalid frame size"));
11094 else if (framesz
!= 128 || (opcode
>> 16) != 0)
11097 opcode
|= (((framesz
& 0xf0) << 16)
11098 | (framesz
& 0x0f));
11101 /* Finally build the instruction. */
11102 if ((opcode
>> 16) != 0 || framesz
== 0)
11104 ip
->use_extend
= TRUE
;
11105 ip
->extend
= opcode
>> 16;
11107 ip
->insn_opcode
|= opcode
& 0x7f;
11111 case 'e': /* extend code */
11112 my_getExpression (&imm_expr
, s
);
11113 check_absolute_expr (ip
, &imm_expr
);
11114 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
11116 as_warn (_("Invalid value for `%s' (%lu)"),
11118 (unsigned long) imm_expr
.X_add_number
);
11119 imm_expr
.X_add_number
&= 0x7ff;
11121 ip
->insn_opcode
|= imm_expr
.X_add_number
;
11122 imm_expr
.X_op
= O_absent
;
11132 /* Args don't match. */
11133 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
11134 strcmp (insn
->name
, insn
[1].name
) == 0)
11141 insn_error
= _("illegal operands");
11147 /* This structure holds information we know about a mips16 immediate
11150 struct mips16_immed_operand
11152 /* The type code used in the argument string in the opcode table. */
11154 /* The number of bits in the short form of the opcode. */
11156 /* The number of bits in the extended form of the opcode. */
11158 /* The amount by which the short form is shifted when it is used;
11159 for example, the sw instruction has a shift count of 2. */
11161 /* The amount by which the short form is shifted when it is stored
11162 into the instruction code. */
11164 /* Non-zero if the short form is unsigned. */
11166 /* Non-zero if the extended form is unsigned. */
11168 /* Non-zero if the value is PC relative. */
11172 /* The mips16 immediate operand types. */
11174 static const struct mips16_immed_operand mips16_immed_operands
[] =
11176 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
11177 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
11178 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
11179 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
11180 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
11181 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
11182 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
11183 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
11184 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
11185 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
11186 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
11187 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
11188 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
11189 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
11190 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
11191 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
11192 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
11193 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
11194 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
11195 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
11196 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
11199 #define MIPS16_NUM_IMMED \
11200 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11202 /* Handle a mips16 instruction with an immediate value. This or's the
11203 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11204 whether an extended value is needed; if one is needed, it sets
11205 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11206 If SMALL is true, an unextended opcode was explicitly requested.
11207 If EXT is true, an extended opcode was explicitly requested. If
11208 WARN is true, warn if EXT does not match reality. */
11211 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
11212 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
11213 unsigned long *insn
, bfd_boolean
*use_extend
,
11214 unsigned short *extend
)
11216 const struct mips16_immed_operand
*op
;
11217 int mintiny
, maxtiny
;
11218 bfd_boolean needext
;
11220 op
= mips16_immed_operands
;
11221 while (op
->type
!= type
)
11224 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11229 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11232 maxtiny
= 1 << op
->nbits
;
11237 maxtiny
= (1 << op
->nbits
) - 1;
11242 mintiny
= - (1 << (op
->nbits
- 1));
11243 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11246 /* Branch offsets have an implicit 0 in the lowest bit. */
11247 if (type
== 'p' || type
== 'q')
11250 if ((val
& ((1 << op
->shift
) - 1)) != 0
11251 || val
< (mintiny
<< op
->shift
)
11252 || val
> (maxtiny
<< op
->shift
))
11257 if (warn
&& ext
&& ! needext
)
11258 as_warn_where (file
, line
,
11259 _("extended operand requested but not required"));
11260 if (small
&& needext
)
11261 as_bad_where (file
, line
, _("invalid unextended operand value"));
11263 if (small
|| (! ext
&& ! needext
))
11267 *use_extend
= FALSE
;
11268 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
11269 insnval
<<= op
->op_shift
;
11274 long minext
, maxext
;
11280 maxext
= (1 << op
->extbits
) - 1;
11284 minext
= - (1 << (op
->extbits
- 1));
11285 maxext
= (1 << (op
->extbits
- 1)) - 1;
11287 if (val
< minext
|| val
> maxext
)
11288 as_bad_where (file
, line
,
11289 _("operand value out of range for instruction"));
11291 *use_extend
= TRUE
;
11292 if (op
->extbits
== 16)
11294 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
11297 else if (op
->extbits
== 15)
11299 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
11304 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
11308 *extend
= (unsigned short) extval
;
11313 struct percent_op_match
11316 bfd_reloc_code_real_type reloc
;
11319 static const struct percent_op_match mips_percent_op
[] =
11321 {"%lo", BFD_RELOC_LO16
},
11323 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
11324 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
11325 {"%call16", BFD_RELOC_MIPS_CALL16
},
11326 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
11327 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
11328 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
11329 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
11330 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
11331 {"%got", BFD_RELOC_MIPS_GOT16
},
11332 {"%gp_rel", BFD_RELOC_GPREL16
},
11333 {"%half", BFD_RELOC_16
},
11334 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
11335 {"%higher", BFD_RELOC_MIPS_HIGHER
},
11336 {"%neg", BFD_RELOC_MIPS_SUB
},
11337 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
11338 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
11339 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
11340 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
11341 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
11342 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
11343 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
11345 {"%hi", BFD_RELOC_HI16_S
}
11348 static const struct percent_op_match mips16_percent_op
[] =
11350 {"%lo", BFD_RELOC_MIPS16_LO16
},
11351 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
11352 {"%got", BFD_RELOC_MIPS16_GOT16
},
11353 {"%call16", BFD_RELOC_MIPS16_CALL16
},
11354 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
11358 /* Return true if *STR points to a relocation operator. When returning true,
11359 move *STR over the operator and store its relocation code in *RELOC.
11360 Leave both *STR and *RELOC alone when returning false. */
11363 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
11365 const struct percent_op_match
*percent_op
;
11368 if (mips_opts
.mips16
)
11370 percent_op
= mips16_percent_op
;
11371 limit
= ARRAY_SIZE (mips16_percent_op
);
11375 percent_op
= mips_percent_op
;
11376 limit
= ARRAY_SIZE (mips_percent_op
);
11379 for (i
= 0; i
< limit
; i
++)
11380 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
11382 int len
= strlen (percent_op
[i
].str
);
11384 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
11387 *str
+= strlen (percent_op
[i
].str
);
11388 *reloc
= percent_op
[i
].reloc
;
11390 /* Check whether the output BFD supports this relocation.
11391 If not, issue an error and fall back on something safe. */
11392 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
11394 as_bad (_("relocation %s isn't supported by the current ABI"),
11395 percent_op
[i
].str
);
11396 *reloc
= BFD_RELOC_UNUSED
;
11404 /* Parse string STR as a 16-bit relocatable operand. Store the
11405 expression in *EP and the relocations in the array starting
11406 at RELOC. Return the number of relocation operators used.
11408 On exit, EXPR_END points to the first character after the expression. */
11411 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
11414 bfd_reloc_code_real_type reversed_reloc
[3];
11415 size_t reloc_index
, i
;
11416 int crux_depth
, str_depth
;
11419 /* Search for the start of the main expression, recoding relocations
11420 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11421 of the main expression and with CRUX_DEPTH containing the number
11422 of open brackets at that point. */
11429 crux_depth
= str_depth
;
11431 /* Skip over whitespace and brackets, keeping count of the number
11433 while (*str
== ' ' || *str
== '\t' || *str
== '(')
11438 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
11439 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
11441 my_getExpression (ep
, crux
);
11444 /* Match every open bracket. */
11445 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
11449 if (crux_depth
> 0)
11450 as_bad (_("unclosed '('"));
11454 if (reloc_index
!= 0)
11456 prev_reloc_op_frag
= frag_now
;
11457 for (i
= 0; i
< reloc_index
; i
++)
11458 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
11461 return reloc_index
;
11465 my_getExpression (expressionS
*ep
, char *str
)
11469 save_in
= input_line_pointer
;
11470 input_line_pointer
= str
;
11472 expr_end
= input_line_pointer
;
11473 input_line_pointer
= save_in
;
11477 md_atof (int type
, char *litP
, int *sizeP
)
11479 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11483 md_number_to_chars (char *buf
, valueT val
, int n
)
11485 if (target_big_endian
)
11486 number_to_chars_bigendian (buf
, val
, n
);
11488 number_to_chars_littleendian (buf
, val
, n
);
11492 static int support_64bit_objects(void)
11494 const char **list
, **l
;
11497 list
= bfd_target_list ();
11498 for (l
= list
; *l
!= NULL
; l
++)
11499 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
11500 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
11502 yes
= (*l
!= NULL
);
11506 #endif /* OBJ_ELF */
11508 const char *md_shortopts
= "O::g::G:";
11512 OPTION_MARCH
= OPTION_MD_BASE
,
11534 OPTION_NO_SMARTMIPS
,
11537 OPTION_COMPAT_ARCH_BASE
,
11546 OPTION_M7000_HILO_FIX
,
11547 OPTION_MNO_7000_HILO_FIX
,
11550 OPTION_FIX_LOONGSON2F_JUMP
,
11551 OPTION_NO_FIX_LOONGSON2F_JUMP
,
11552 OPTION_FIX_LOONGSON2F_NOP
,
11553 OPTION_NO_FIX_LOONGSON2F_NOP
,
11555 OPTION_NO_FIX_VR4120
,
11557 OPTION_NO_FIX_VR4130
,
11558 OPTION_FIX_CN63XXP1
,
11559 OPTION_NO_FIX_CN63XXP1
,
11566 OPTION_CONSTRUCT_FLOATS
,
11567 OPTION_NO_CONSTRUCT_FLOATS
,
11570 OPTION_RELAX_BRANCH
,
11571 OPTION_NO_RELAX_BRANCH
,
11578 OPTION_SINGLE_FLOAT
,
11579 OPTION_DOUBLE_FLOAT
,
11582 OPTION_CALL_SHARED
,
11583 OPTION_CALL_NONPIC
,
11593 OPTION_MVXWORKS_PIC
,
11594 #endif /* OBJ_ELF */
11598 struct option md_longopts
[] =
11600 /* Options which specify architecture. */
11601 {"march", required_argument
, NULL
, OPTION_MARCH
},
11602 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11603 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11604 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11605 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11606 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11607 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11608 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11609 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11610 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11611 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11612 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11614 /* Options which specify Application Specific Extensions (ASEs). */
11615 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11616 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11617 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11618 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11619 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11620 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11621 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11622 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11623 {"mmt", no_argument
, NULL
, OPTION_MT
},
11624 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11625 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11626 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11627 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11628 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11630 /* Old-style architecture options. Don't add more of these. */
11631 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11632 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11633 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11634 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11635 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11636 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11637 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11638 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11640 /* Options which enable bug fixes. */
11641 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11642 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11643 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11644 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
11645 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
11646 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
11647 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
11648 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11649 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11650 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11651 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11652 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
11653 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
11654 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
11655 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
11657 /* Miscellaneous options. */
11658 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11659 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11660 {"break", no_argument
, NULL
, OPTION_BREAK
},
11661 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11662 {"EB", no_argument
, NULL
, OPTION_EB
},
11663 {"EL", no_argument
, NULL
, OPTION_EL
},
11664 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11665 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11666 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11667 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11668 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11669 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11670 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11671 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11672 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11673 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11674 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11675 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11676 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11677 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11678 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11679 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11681 /* Strictly speaking this next option is ELF specific,
11682 but we allow it for other ports as well in order to
11683 make testing easier. */
11684 {"32", no_argument
, NULL
, OPTION_32
},
11686 /* ELF-specific options. */
11688 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11689 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11690 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
11691 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11692 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11693 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11694 {"n32", no_argument
, NULL
, OPTION_N32
},
11695 {"64", no_argument
, NULL
, OPTION_64
},
11696 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11697 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11698 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11699 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11700 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11701 #endif /* OBJ_ELF */
11703 {NULL
, no_argument
, NULL
, 0}
11705 size_t md_longopts_size
= sizeof (md_longopts
);
11707 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11708 NEW_VALUE. Warn if another value was already specified. Note:
11709 we have to defer parsing the -march and -mtune arguments in order
11710 to handle 'from-abi' correctly, since the ABI might be specified
11711 in a later argument. */
11714 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11716 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11717 as_warn (_("A different %s was already specified, is now %s"),
11718 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11721 *string_ptr
= new_value
;
11725 md_parse_option (int c
, char *arg
)
11729 case OPTION_CONSTRUCT_FLOATS
:
11730 mips_disable_float_construction
= 0;
11733 case OPTION_NO_CONSTRUCT_FLOATS
:
11734 mips_disable_float_construction
= 1;
11746 target_big_endian
= 1;
11750 target_big_endian
= 0;
11756 else if (arg
[0] == '0')
11758 else if (arg
[0] == '1')
11768 mips_debug
= atoi (arg
);
11772 file_mips_isa
= ISA_MIPS1
;
11776 file_mips_isa
= ISA_MIPS2
;
11780 file_mips_isa
= ISA_MIPS3
;
11784 file_mips_isa
= ISA_MIPS4
;
11788 file_mips_isa
= ISA_MIPS5
;
11791 case OPTION_MIPS32
:
11792 file_mips_isa
= ISA_MIPS32
;
11795 case OPTION_MIPS32R2
:
11796 file_mips_isa
= ISA_MIPS32R2
;
11799 case OPTION_MIPS64R2
:
11800 file_mips_isa
= ISA_MIPS64R2
;
11803 case OPTION_MIPS64
:
11804 file_mips_isa
= ISA_MIPS64
;
11808 mips_set_option_string (&mips_tune_string
, arg
);
11812 mips_set_option_string (&mips_arch_string
, arg
);
11816 mips_set_option_string (&mips_arch_string
, "4650");
11817 mips_set_option_string (&mips_tune_string
, "4650");
11820 case OPTION_NO_M4650
:
11824 mips_set_option_string (&mips_arch_string
, "4010");
11825 mips_set_option_string (&mips_tune_string
, "4010");
11828 case OPTION_NO_M4010
:
11832 mips_set_option_string (&mips_arch_string
, "4100");
11833 mips_set_option_string (&mips_tune_string
, "4100");
11836 case OPTION_NO_M4100
:
11840 mips_set_option_string (&mips_arch_string
, "3900");
11841 mips_set_option_string (&mips_tune_string
, "3900");
11844 case OPTION_NO_M3900
:
11848 mips_opts
.ase_mdmx
= 1;
11851 case OPTION_NO_MDMX
:
11852 mips_opts
.ase_mdmx
= 0;
11856 mips_opts
.ase_dsp
= 1;
11857 mips_opts
.ase_dspr2
= 0;
11860 case OPTION_NO_DSP
:
11861 mips_opts
.ase_dsp
= 0;
11862 mips_opts
.ase_dspr2
= 0;
11866 mips_opts
.ase_dspr2
= 1;
11867 mips_opts
.ase_dsp
= 1;
11870 case OPTION_NO_DSPR2
:
11871 mips_opts
.ase_dspr2
= 0;
11872 mips_opts
.ase_dsp
= 0;
11876 mips_opts
.ase_mt
= 1;
11880 mips_opts
.ase_mt
= 0;
11883 case OPTION_MIPS16
:
11884 mips_opts
.mips16
= 1;
11885 mips_no_prev_insn ();
11888 case OPTION_NO_MIPS16
:
11889 mips_opts
.mips16
= 0;
11890 mips_no_prev_insn ();
11893 case OPTION_MIPS3D
:
11894 mips_opts
.ase_mips3d
= 1;
11897 case OPTION_NO_MIPS3D
:
11898 mips_opts
.ase_mips3d
= 0;
11901 case OPTION_SMARTMIPS
:
11902 mips_opts
.ase_smartmips
= 1;
11905 case OPTION_NO_SMARTMIPS
:
11906 mips_opts
.ase_smartmips
= 0;
11909 case OPTION_FIX_24K
:
11913 case OPTION_NO_FIX_24K
:
11917 case OPTION_FIX_LOONGSON2F_JUMP
:
11918 mips_fix_loongson2f_jump
= TRUE
;
11921 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
11922 mips_fix_loongson2f_jump
= FALSE
;
11925 case OPTION_FIX_LOONGSON2F_NOP
:
11926 mips_fix_loongson2f_nop
= TRUE
;
11929 case OPTION_NO_FIX_LOONGSON2F_NOP
:
11930 mips_fix_loongson2f_nop
= FALSE
;
11933 case OPTION_FIX_VR4120
:
11934 mips_fix_vr4120
= 1;
11937 case OPTION_NO_FIX_VR4120
:
11938 mips_fix_vr4120
= 0;
11941 case OPTION_FIX_VR4130
:
11942 mips_fix_vr4130
= 1;
11945 case OPTION_NO_FIX_VR4130
:
11946 mips_fix_vr4130
= 0;
11949 case OPTION_FIX_CN63XXP1
:
11950 mips_fix_cn63xxp1
= TRUE
;
11953 case OPTION_NO_FIX_CN63XXP1
:
11954 mips_fix_cn63xxp1
= FALSE
;
11957 case OPTION_RELAX_BRANCH
:
11958 mips_relax_branch
= 1;
11961 case OPTION_NO_RELAX_BRANCH
:
11962 mips_relax_branch
= 0;
11965 case OPTION_MSHARED
:
11966 mips_in_shared
= TRUE
;
11969 case OPTION_MNO_SHARED
:
11970 mips_in_shared
= FALSE
;
11973 case OPTION_MSYM32
:
11974 mips_opts
.sym32
= TRUE
;
11977 case OPTION_MNO_SYM32
:
11978 mips_opts
.sym32
= FALSE
;
11982 /* When generating ELF code, we permit -KPIC and -call_shared to
11983 select SVR4_PIC, and -non_shared to select no PIC. This is
11984 intended to be compatible with Irix 5. */
11985 case OPTION_CALL_SHARED
:
11988 as_bad (_("-call_shared is supported only for ELF format"));
11991 mips_pic
= SVR4_PIC
;
11992 mips_abicalls
= TRUE
;
11995 case OPTION_CALL_NONPIC
:
11998 as_bad (_("-call_nonpic is supported only for ELF format"));
12002 mips_abicalls
= TRUE
;
12005 case OPTION_NON_SHARED
:
12008 as_bad (_("-non_shared is supported only for ELF format"));
12012 mips_abicalls
= FALSE
;
12015 /* The -xgot option tells the assembler to use 32 bit offsets
12016 when accessing the got in SVR4_PIC mode. It is for Irix
12021 #endif /* OBJ_ELF */
12024 g_switch_value
= atoi (arg
);
12028 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
12032 mips_abi
= O32_ABI
;
12033 /* We silently ignore -32 for non-ELF targets. This greatly
12034 simplifies the construction of the MIPS GAS test cases. */
12041 as_bad (_("-n32 is supported for ELF format only"));
12044 mips_abi
= N32_ABI
;
12050 as_bad (_("-64 is supported for ELF format only"));
12053 mips_abi
= N64_ABI
;
12054 if (!support_64bit_objects())
12055 as_fatal (_("No compiled in support for 64 bit object file format"));
12057 #endif /* OBJ_ELF */
12060 file_mips_gp32
= 1;
12064 file_mips_gp32
= 0;
12068 file_mips_fp32
= 1;
12072 file_mips_fp32
= 0;
12075 case OPTION_SINGLE_FLOAT
:
12076 file_mips_single_float
= 1;
12079 case OPTION_DOUBLE_FLOAT
:
12080 file_mips_single_float
= 0;
12083 case OPTION_SOFT_FLOAT
:
12084 file_mips_soft_float
= 1;
12087 case OPTION_HARD_FLOAT
:
12088 file_mips_soft_float
= 0;
12095 as_bad (_("-mabi is supported for ELF format only"));
12098 if (strcmp (arg
, "32") == 0)
12099 mips_abi
= O32_ABI
;
12100 else if (strcmp (arg
, "o64") == 0)
12101 mips_abi
= O64_ABI
;
12102 else if (strcmp (arg
, "n32") == 0)
12103 mips_abi
= N32_ABI
;
12104 else if (strcmp (arg
, "64") == 0)
12106 mips_abi
= N64_ABI
;
12107 if (! support_64bit_objects())
12108 as_fatal (_("No compiled in support for 64 bit object file "
12111 else if (strcmp (arg
, "eabi") == 0)
12112 mips_abi
= EABI_ABI
;
12115 as_fatal (_("invalid abi -mabi=%s"), arg
);
12119 #endif /* OBJ_ELF */
12121 case OPTION_M7000_HILO_FIX
:
12122 mips_7000_hilo_fix
= TRUE
;
12125 case OPTION_MNO_7000_HILO_FIX
:
12126 mips_7000_hilo_fix
= FALSE
;
12130 case OPTION_MDEBUG
:
12131 mips_flag_mdebug
= TRUE
;
12134 case OPTION_NO_MDEBUG
:
12135 mips_flag_mdebug
= FALSE
;
12139 mips_flag_pdr
= TRUE
;
12142 case OPTION_NO_PDR
:
12143 mips_flag_pdr
= FALSE
;
12146 case OPTION_MVXWORKS_PIC
:
12147 mips_pic
= VXWORKS_PIC
;
12149 #endif /* OBJ_ELF */
12155 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
12160 /* Set up globals to generate code for the ISA or processor
12161 described by INFO. */
12164 mips_set_architecture (const struct mips_cpu_info
*info
)
12168 file_mips_arch
= info
->cpu
;
12169 mips_opts
.arch
= info
->cpu
;
12170 mips_opts
.isa
= info
->isa
;
12175 /* Likewise for tuning. */
12178 mips_set_tune (const struct mips_cpu_info
*info
)
12181 mips_tune
= info
->cpu
;
12186 mips_after_parse_args (void)
12188 const struct mips_cpu_info
*arch_info
= 0;
12189 const struct mips_cpu_info
*tune_info
= 0;
12191 /* GP relative stuff not working for PE */
12192 if (strncmp (TARGET_OS
, "pe", 2) == 0)
12194 if (g_switch_seen
&& g_switch_value
!= 0)
12195 as_bad (_("-G not supported in this configuration."));
12196 g_switch_value
= 0;
12199 if (mips_abi
== NO_ABI
)
12200 mips_abi
= MIPS_DEFAULT_ABI
;
12202 /* The following code determines the architecture and register size.
12203 Similar code was added to GCC 3.3 (see override_options() in
12204 config/mips/mips.c). The GAS and GCC code should be kept in sync
12205 as much as possible. */
12207 if (mips_arch_string
!= 0)
12208 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
12210 if (file_mips_isa
!= ISA_UNKNOWN
)
12212 /* Handle -mipsN. At this point, file_mips_isa contains the
12213 ISA level specified by -mipsN, while arch_info->isa contains
12214 the -march selection (if any). */
12215 if (arch_info
!= 0)
12217 /* -march takes precedence over -mipsN, since it is more descriptive.
12218 There's no harm in specifying both as long as the ISA levels
12220 if (file_mips_isa
!= arch_info
->isa
)
12221 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12222 mips_cpu_info_from_isa (file_mips_isa
)->name
,
12223 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
12226 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
12229 if (arch_info
== 0)
12230 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
12232 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
12233 as_bad (_("-march=%s is not compatible with the selected ABI"),
12236 mips_set_architecture (arch_info
);
12238 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12239 if (mips_tune_string
!= 0)
12240 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
12242 if (tune_info
== 0)
12243 mips_set_tune (arch_info
);
12245 mips_set_tune (tune_info
);
12247 if (file_mips_gp32
>= 0)
12249 /* The user specified the size of the integer registers. Make sure
12250 it agrees with the ABI and ISA. */
12251 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12252 as_bad (_("-mgp64 used with a 32-bit processor"));
12253 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
12254 as_bad (_("-mgp32 used with a 64-bit ABI"));
12255 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
12256 as_bad (_("-mgp64 used with a 32-bit ABI"));
12260 /* Infer the integer register size from the ABI and processor.
12261 Restrict ourselves to 32-bit registers if that's all the
12262 processor has, or if the ABI cannot handle 64-bit registers. */
12263 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
12264 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
12267 switch (file_mips_fp32
)
12271 /* No user specified float register size.
12272 ??? GAS treats single-float processors as though they had 64-bit
12273 float registers (although it complains when double-precision
12274 instructions are used). As things stand, saying they have 32-bit
12275 registers would lead to spurious "register must be even" messages.
12276 So here we assume float registers are never smaller than the
12278 if (file_mips_gp32
== 0)
12279 /* 64-bit integer registers implies 64-bit float registers. */
12280 file_mips_fp32
= 0;
12281 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
12282 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12283 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12284 file_mips_fp32
= 0;
12286 /* 32-bit float registers. */
12287 file_mips_fp32
= 1;
12290 /* The user specified the size of the float registers. Check if it
12291 agrees with the ABI and ISA. */
12293 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12294 as_bad (_("-mfp64 used with a 32-bit fpu"));
12295 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
12296 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
12297 as_warn (_("-mfp64 used with a 32-bit ABI"));
12300 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
12301 as_warn (_("-mfp32 used with a 64-bit ABI"));
12305 /* End of GCC-shared inference code. */
12307 /* This flag is set when we have a 64-bit capable CPU but use only
12308 32-bit wide registers. Note that EABI does not use it. */
12309 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
12310 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
12311 || mips_abi
== O32_ABI
))
12312 mips_32bitmode
= 1;
12314 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
12315 as_bad (_("trap exception not supported at ISA 1"));
12317 /* If the selected architecture includes support for ASEs, enable
12318 generation of code for them. */
12319 if (mips_opts
.mips16
== -1)
12320 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
12321 if (mips_opts
.ase_mips3d
== -1)
12322 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
12323 && file_mips_fp32
== 0) ? 1 : 0;
12324 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
12325 as_bad (_("-mfp32 used with -mips3d"));
12327 if (mips_opts
.ase_mdmx
== -1)
12328 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
12329 && file_mips_fp32
== 0) ? 1 : 0;
12330 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
12331 as_bad (_("-mfp32 used with -mdmx"));
12333 if (mips_opts
.ase_smartmips
== -1)
12334 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
12335 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
12336 as_warn (_("%s ISA does not support SmartMIPS"),
12337 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12339 if (mips_opts
.ase_dsp
== -1)
12340 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12341 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
12342 as_warn (_("%s ISA does not support DSP ASE"),
12343 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12345 if (mips_opts
.ase_dspr2
== -1)
12347 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
12348 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12350 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
12351 as_warn (_("%s ISA does not support DSP R2 ASE"),
12352 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12354 if (mips_opts
.ase_mt
== -1)
12355 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
12356 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
12357 as_warn (_("%s ISA does not support MT ASE"),
12358 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12360 file_mips_isa
= mips_opts
.isa
;
12361 file_ase_mips3d
= mips_opts
.ase_mips3d
;
12362 file_ase_mdmx
= mips_opts
.ase_mdmx
;
12363 file_ase_smartmips
= mips_opts
.ase_smartmips
;
12364 file_ase_dsp
= mips_opts
.ase_dsp
;
12365 file_ase_dspr2
= mips_opts
.ase_dspr2
;
12366 file_ase_mt
= mips_opts
.ase_mt
;
12367 mips_opts
.gp32
= file_mips_gp32
;
12368 mips_opts
.fp32
= file_mips_fp32
;
12369 mips_opts
.soft_float
= file_mips_soft_float
;
12370 mips_opts
.single_float
= file_mips_single_float
;
12372 if (mips_flag_mdebug
< 0)
12374 #ifdef OBJ_MAYBE_ECOFF
12375 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
12376 mips_flag_mdebug
= 1;
12378 #endif /* OBJ_MAYBE_ECOFF */
12379 mips_flag_mdebug
= 0;
12384 mips_init_after_args (void)
12386 /* initialize opcodes */
12387 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
12388 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
12392 md_pcrel_from (fixS
*fixP
)
12394 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12395 switch (fixP
->fx_r_type
)
12397 case BFD_RELOC_16_PCREL_S2
:
12398 case BFD_RELOC_MIPS_JMP
:
12399 /* Return the address of the delay slot. */
12402 /* We have no relocation type for PC relative MIPS16 instructions. */
12403 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
12404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12405 _("PC relative MIPS16 instruction references a different section"));
12410 /* This is called before the symbol table is processed. In order to
12411 work with gcc when using mips-tfile, we must keep all local labels.
12412 However, in other cases, we want to discard them. If we were
12413 called with -g, but we didn't see any debugging information, it may
12414 mean that gcc is smuggling debugging information through to
12415 mips-tfile, in which case we must generate all local labels. */
12418 mips_frob_file_before_adjust (void)
12420 #ifndef NO_ECOFF_DEBUGGING
12421 if (ECOFF_DEBUGGING
12423 && ! ecoff_debugging_seen
)
12424 flag_keep_locals
= 1;
12428 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12429 the corresponding LO16 reloc. This is called before md_apply_fix and
12430 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12431 relocation operators.
12433 For our purposes, a %lo() expression matches a %got() or %hi()
12436 (a) it refers to the same symbol; and
12437 (b) the offset applied in the %lo() expression is no lower than
12438 the offset applied in the %got() or %hi().
12440 (b) allows us to cope with code like:
12443 lh $4,%lo(foo+2)($4)
12445 ...which is legal on RELA targets, and has a well-defined behaviour
12446 if the user knows that adding 2 to "foo" will not induce a carry to
12449 When several %lo()s match a particular %got() or %hi(), we use the
12450 following rules to distinguish them:
12452 (1) %lo()s with smaller offsets are a better match than %lo()s with
12455 (2) %lo()s with no matching %got() or %hi() are better than those
12456 that already have a matching %got() or %hi().
12458 (3) later %lo()s are better than earlier %lo()s.
12460 These rules are applied in order.
12462 (1) means, among other things, that %lo()s with identical offsets are
12463 chosen if they exist.
12465 (2) means that we won't associate several high-part relocations with
12466 the same low-part relocation unless there's no alternative. Having
12467 several high parts for the same low part is a GNU extension; this rule
12468 allows careful users to avoid it.
12470 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12471 with the last high-part relocation being at the front of the list.
12472 It therefore makes sense to choose the last matching low-part
12473 relocation, all other things being equal. It's also easier
12474 to code that way. */
12477 mips_frob_file (void)
12479 struct mips_hi_fixup
*l
;
12480 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
12482 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
12484 segment_info_type
*seginfo
;
12485 bfd_boolean matched_lo_p
;
12486 fixS
**hi_pos
, **lo_pos
, **pos
;
12488 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
12490 /* If a GOT16 relocation turns out to be against a global symbol,
12491 there isn't supposed to be a matching LO. */
12492 if (got16_reloc_p (l
->fixp
->fx_r_type
)
12493 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
12496 /* Check quickly whether the next fixup happens to be a matching %lo. */
12497 if (fixup_has_matching_lo_p (l
->fixp
))
12500 seginfo
= seg_info (l
->seg
);
12502 /* Set HI_POS to the position of this relocation in the chain.
12503 Set LO_POS to the position of the chosen low-part relocation.
12504 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12505 relocation that matches an immediately-preceding high-part
12509 matched_lo_p
= FALSE
;
12510 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
12512 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
12514 if (*pos
== l
->fixp
)
12517 if ((*pos
)->fx_r_type
== looking_for_rtype
12518 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
12519 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
12521 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
12523 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
12526 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
12527 && fixup_has_matching_lo_p (*pos
));
12530 /* If we found a match, remove the high-part relocation from its
12531 current position and insert it before the low-part relocation.
12532 Make the offsets match so that fixup_has_matching_lo_p()
12535 We don't warn about unmatched high-part relocations since some
12536 versions of gcc have been known to emit dead "lui ...%hi(...)"
12538 if (lo_pos
!= NULL
)
12540 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12541 if (l
->fixp
->fx_next
!= *lo_pos
)
12543 *hi_pos
= l
->fixp
->fx_next
;
12544 l
->fixp
->fx_next
= *lo_pos
;
12551 /* We may have combined relocations without symbols in the N32/N64 ABI.
12552 We have to prevent gas from dropping them. */
12555 mips_force_relocation (fixS
*fixp
)
12557 if (generic_force_reloc (fixp
))
12561 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12562 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12563 || hi16_reloc_p (fixp
->fx_r_type
)
12564 || lo16_reloc_p (fixp
->fx_r_type
)))
12570 /* Apply a fixup to the object file. */
12573 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12577 reloc_howto_type
*howto
;
12579 /* We ignore generic BFD relocations we don't know about. */
12580 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12584 gas_assert (fixP
->fx_size
== 4
12585 || fixP
->fx_r_type
== BFD_RELOC_16
12586 || fixP
->fx_r_type
== BFD_RELOC_64
12587 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12588 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12589 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12590 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12591 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12593 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12595 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12597 /* Don't treat parts of a composite relocation as done. There are two
12600 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12601 should nevertheless be emitted if the first part is.
12603 (2) In normal usage, composite relocations are never assembly-time
12604 constants. The easiest way of dealing with the pathological
12605 exceptions is to generate a relocation against STN_UNDEF and
12606 leave everything up to the linker. */
12607 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12610 switch (fixP
->fx_r_type
)
12612 case BFD_RELOC_MIPS_TLS_GD
:
12613 case BFD_RELOC_MIPS_TLS_LDM
:
12614 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12615 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12616 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12617 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12618 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12619 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12620 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12621 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12624 case BFD_RELOC_MIPS_JMP
:
12625 case BFD_RELOC_MIPS_SHIFT5
:
12626 case BFD_RELOC_MIPS_SHIFT6
:
12627 case BFD_RELOC_MIPS_GOT_DISP
:
12628 case BFD_RELOC_MIPS_GOT_PAGE
:
12629 case BFD_RELOC_MIPS_GOT_OFST
:
12630 case BFD_RELOC_MIPS_SUB
:
12631 case BFD_RELOC_MIPS_INSERT_A
:
12632 case BFD_RELOC_MIPS_INSERT_B
:
12633 case BFD_RELOC_MIPS_DELETE
:
12634 case BFD_RELOC_MIPS_HIGHEST
:
12635 case BFD_RELOC_MIPS_HIGHER
:
12636 case BFD_RELOC_MIPS_SCN_DISP
:
12637 case BFD_RELOC_MIPS_REL16
:
12638 case BFD_RELOC_MIPS_RELGOT
:
12639 case BFD_RELOC_MIPS_JALR
:
12640 case BFD_RELOC_HI16
:
12641 case BFD_RELOC_HI16_S
:
12642 case BFD_RELOC_GPREL16
:
12643 case BFD_RELOC_MIPS_LITERAL
:
12644 case BFD_RELOC_MIPS_CALL16
:
12645 case BFD_RELOC_MIPS_GOT16
:
12646 case BFD_RELOC_GPREL32
:
12647 case BFD_RELOC_MIPS_GOT_HI16
:
12648 case BFD_RELOC_MIPS_GOT_LO16
:
12649 case BFD_RELOC_MIPS_CALL_HI16
:
12650 case BFD_RELOC_MIPS_CALL_LO16
:
12651 case BFD_RELOC_MIPS16_GPREL
:
12652 case BFD_RELOC_MIPS16_GOT16
:
12653 case BFD_RELOC_MIPS16_CALL16
:
12654 case BFD_RELOC_MIPS16_HI16
:
12655 case BFD_RELOC_MIPS16_HI16_S
:
12656 case BFD_RELOC_MIPS16_JMP
:
12657 /* Nothing needed to do. The value comes from the reloc entry. */
12661 /* This is handled like BFD_RELOC_32, but we output a sign
12662 extended value if we are only 32 bits. */
12665 if (8 <= sizeof (valueT
))
12666 md_number_to_chars ((char *) buf
, *valP
, 8);
12671 if ((*valP
& 0x80000000) != 0)
12675 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12677 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12683 case BFD_RELOC_RVA
:
12686 /* If we are deleting this reloc entry, we must fill in the
12687 value now. This can happen if we have a .word which is not
12688 resolved when it appears but is later defined. */
12690 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12693 case BFD_RELOC_LO16
:
12694 case BFD_RELOC_MIPS16_LO16
:
12695 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12696 may be safe to remove, but if so it's not obvious. */
12697 /* When handling an embedded PIC switch statement, we can wind
12698 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12701 if (*valP
+ 0x8000 > 0xffff)
12702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12703 _("relocation overflow"));
12704 if (target_big_endian
)
12706 md_number_to_chars ((char *) buf
, *valP
, 2);
12710 case BFD_RELOC_16_PCREL_S2
:
12711 if ((*valP
& 0x3) != 0)
12712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12713 _("Branch to misaligned address (%lx)"), (long) *valP
);
12715 /* We need to save the bits in the instruction since fixup_segment()
12716 might be deleting the relocation entry (i.e., a branch within
12717 the current segment). */
12718 if (! fixP
->fx_done
)
12721 /* Update old instruction data. */
12722 if (target_big_endian
)
12723 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12725 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12727 if (*valP
+ 0x20000 <= 0x3ffff)
12729 insn
|= (*valP
>> 2) & 0xffff;
12730 md_number_to_chars ((char *) buf
, insn
, 4);
12732 else if (mips_pic
== NO_PIC
12734 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12735 && (fixP
->fx_frag
->fr_address
12736 < text_section
->vma
+ bfd_get_section_size (text_section
))
12737 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12738 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12739 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12741 /* The branch offset is too large. If this is an
12742 unconditional branch, and we are not generating PIC code,
12743 we can convert it to an absolute jump instruction. */
12744 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12745 insn
= 0x0c000000; /* jal */
12747 insn
= 0x08000000; /* j */
12748 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12750 fixP
->fx_addsy
= section_symbol (text_section
);
12751 *valP
+= md_pcrel_from (fixP
);
12752 md_number_to_chars ((char *) buf
, insn
, 4);
12756 /* If we got here, we have branch-relaxation disabled,
12757 and there's nothing we can do to fix this instruction
12758 without turning it into a longer sequence. */
12759 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12760 _("Branch out of range"));
12764 case BFD_RELOC_VTABLE_INHERIT
:
12767 && !S_IS_DEFINED (fixP
->fx_addsy
)
12768 && !S_IS_WEAK (fixP
->fx_addsy
))
12769 S_SET_WEAK (fixP
->fx_addsy
);
12772 case BFD_RELOC_VTABLE_ENTRY
:
12780 /* Remember value for tc_gen_reloc. */
12781 fixP
->fx_addnumber
= *valP
;
12791 name
= input_line_pointer
;
12792 c
= get_symbol_end ();
12793 p
= (symbolS
*) symbol_find_or_make (name
);
12794 *input_line_pointer
= c
;
12798 /* Align the current frag to a given power of two. If a particular
12799 fill byte should be used, FILL points to an integer that contains
12800 that byte, otherwise FILL is null.
12802 The MIPS assembler also automatically adjusts any preceding
12806 mips_align (int to
, int *fill
, symbolS
*label
)
12808 mips_emit_delays ();
12809 mips_record_mips16_mode ();
12810 if (fill
== NULL
&& subseg_text_p (now_seg
))
12811 frag_align_code (to
, 0);
12813 frag_align (to
, fill
? *fill
: 0, 0);
12814 record_alignment (now_seg
, to
);
12817 gas_assert (S_GET_SEGMENT (label
) == now_seg
);
12818 symbol_set_frag (label
, frag_now
);
12819 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12823 /* Align to a given power of two. .align 0 turns off the automatic
12824 alignment used by the data creating pseudo-ops. */
12827 s_align (int x ATTRIBUTE_UNUSED
)
12829 int temp
, fill_value
, *fill_ptr
;
12830 long max_alignment
= 28;
12832 /* o Note that the assembler pulls down any immediately preceding label
12833 to the aligned address.
12834 o It's not documented but auto alignment is reinstated by
12835 a .align pseudo instruction.
12836 o Note also that after auto alignment is turned off the mips assembler
12837 issues an error on attempt to assemble an improperly aligned data item.
12840 temp
= get_absolute_expression ();
12841 if (temp
> max_alignment
)
12842 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12845 as_warn (_("Alignment negative: 0 assumed."));
12848 if (*input_line_pointer
== ',')
12850 ++input_line_pointer
;
12851 fill_value
= get_absolute_expression ();
12852 fill_ptr
= &fill_value
;
12858 segment_info_type
*si
= seg_info (now_seg
);
12859 struct insn_label_list
*l
= si
->label_list
;
12860 /* Auto alignment should be switched on by next section change. */
12862 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12869 demand_empty_rest_of_line ();
12873 s_change_sec (int sec
)
12878 /* The ELF backend needs to know that we are changing sections, so
12879 that .previous works correctly. We could do something like check
12880 for an obj_section_change_hook macro, but that might be confusing
12881 as it would not be appropriate to use it in the section changing
12882 functions in read.c, since obj-elf.c intercepts those. FIXME:
12883 This should be cleaner, somehow. */
12885 obj_elf_section_change_hook ();
12888 mips_emit_delays ();
12899 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12900 demand_empty_rest_of_line ();
12904 seg
= subseg_new (RDATA_SECTION_NAME
,
12905 (subsegT
) get_absolute_expression ());
12908 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12909 | SEC_READONLY
| SEC_RELOC
12911 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12912 record_alignment (seg
, 4);
12914 demand_empty_rest_of_line ();
12918 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12921 bfd_set_section_flags (stdoutput
, seg
,
12922 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12923 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12924 record_alignment (seg
, 4);
12926 demand_empty_rest_of_line ();
12930 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
12933 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
12934 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12935 record_alignment (seg
, 4);
12937 demand_empty_rest_of_line ();
12945 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12948 char *section_name
;
12953 int section_entry_size
;
12954 int section_alignment
;
12959 section_name
= input_line_pointer
;
12960 c
= get_symbol_end ();
12962 next_c
= *(input_line_pointer
+ 1);
12964 /* Do we have .section Name<,"flags">? */
12965 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12967 /* just after name is now '\0'. */
12968 *input_line_pointer
= c
;
12969 input_line_pointer
= section_name
;
12970 obj_elf_section (ignore
);
12973 input_line_pointer
++;
12975 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12977 section_type
= get_absolute_expression ();
12980 if (*input_line_pointer
++ == ',')
12981 section_flag
= get_absolute_expression ();
12984 if (*input_line_pointer
++ == ',')
12985 section_entry_size
= get_absolute_expression ();
12987 section_entry_size
= 0;
12988 if (*input_line_pointer
++ == ',')
12989 section_alignment
= get_absolute_expression ();
12991 section_alignment
= 0;
12992 /* FIXME: really ignore? */
12993 (void) section_alignment
;
12995 section_name
= xstrdup (section_name
);
12997 /* When using the generic form of .section (as implemented by obj-elf.c),
12998 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12999 traditionally had to fall back on the more common @progbits instead.
13001 There's nothing really harmful in this, since bfd will correct
13002 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
13003 means that, for backwards compatibility, the special_section entries
13004 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
13006 Even so, we shouldn't force users of the MIPS .section syntax to
13007 incorrectly label the sections as SHT_PROGBITS. The best compromise
13008 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
13009 generic type-checking code. */
13010 if (section_type
== SHT_MIPS_DWARF
)
13011 section_type
= SHT_PROGBITS
;
13013 obj_elf_change_section (section_name
, section_type
, section_flag
,
13014 section_entry_size
, 0, 0, 0);
13016 if (now_seg
->name
!= section_name
)
13017 free (section_name
);
13018 #endif /* OBJ_ELF */
13022 mips_enable_auto_align (void)
13028 s_cons (int log_size
)
13030 segment_info_type
*si
= seg_info (now_seg
);
13031 struct insn_label_list
*l
= si
->label_list
;
13034 label
= l
!= NULL
? l
->label
: NULL
;
13035 mips_emit_delays ();
13036 if (log_size
> 0 && auto_align
)
13037 mips_align (log_size
, 0, label
);
13038 cons (1 << log_size
);
13039 mips_clear_insn_labels ();
13043 s_float_cons (int type
)
13045 segment_info_type
*si
= seg_info (now_seg
);
13046 struct insn_label_list
*l
= si
->label_list
;
13049 label
= l
!= NULL
? l
->label
: NULL
;
13051 mips_emit_delays ();
13056 mips_align (3, 0, label
);
13058 mips_align (2, 0, label
);
13062 mips_clear_insn_labels ();
13065 /* Handle .globl. We need to override it because on Irix 5 you are
13068 where foo is an undefined symbol, to mean that foo should be
13069 considered to be the address of a function. */
13072 s_mips_globl (int x ATTRIBUTE_UNUSED
)
13081 name
= input_line_pointer
;
13082 c
= get_symbol_end ();
13083 symbolP
= symbol_find_or_make (name
);
13084 S_SET_EXTERNAL (symbolP
);
13086 *input_line_pointer
= c
;
13087 SKIP_WHITESPACE ();
13089 /* On Irix 5, every global symbol that is not explicitly labelled as
13090 being a function is apparently labelled as being an object. */
13093 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
13094 && (*input_line_pointer
!= ','))
13099 secname
= input_line_pointer
;
13100 c
= get_symbol_end ();
13101 sec
= bfd_get_section_by_name (stdoutput
, secname
);
13103 as_bad (_("%s: no such section"), secname
);
13104 *input_line_pointer
= c
;
13106 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
13107 flag
= BSF_FUNCTION
;
13110 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
13112 c
= *input_line_pointer
;
13115 input_line_pointer
++;
13116 SKIP_WHITESPACE ();
13117 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
13123 demand_empty_rest_of_line ();
13127 s_option (int x ATTRIBUTE_UNUSED
)
13132 opt
= input_line_pointer
;
13133 c
= get_symbol_end ();
13137 /* FIXME: What does this mean? */
13139 else if (strncmp (opt
, "pic", 3) == 0)
13143 i
= atoi (opt
+ 3);
13148 mips_pic
= SVR4_PIC
;
13149 mips_abicalls
= TRUE
;
13152 as_bad (_(".option pic%d not supported"), i
);
13154 if (mips_pic
== SVR4_PIC
)
13156 if (g_switch_seen
&& g_switch_value
!= 0)
13157 as_warn (_("-G may not be used with SVR4 PIC code"));
13158 g_switch_value
= 0;
13159 bfd_set_gp_size (stdoutput
, 0);
13163 as_warn (_("Unrecognized option \"%s\""), opt
);
13165 *input_line_pointer
= c
;
13166 demand_empty_rest_of_line ();
13169 /* This structure is used to hold a stack of .set values. */
13171 struct mips_option_stack
13173 struct mips_option_stack
*next
;
13174 struct mips_set_options options
;
13177 static struct mips_option_stack
*mips_opts_stack
;
13179 /* Handle the .set pseudo-op. */
13182 s_mipsset (int x ATTRIBUTE_UNUSED
)
13184 char *name
= input_line_pointer
, ch
;
13186 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13187 ++input_line_pointer
;
13188 ch
= *input_line_pointer
;
13189 *input_line_pointer
= '\0';
13191 if (strcmp (name
, "reorder") == 0)
13193 if (mips_opts
.noreorder
)
13196 else if (strcmp (name
, "noreorder") == 0)
13198 if (!mips_opts
.noreorder
)
13199 start_noreorder ();
13201 else if (strncmp (name
, "at=", 3) == 0)
13203 char *s
= name
+ 3;
13205 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
13206 as_bad (_("Unrecognized register name `%s'"), s
);
13208 else if (strcmp (name
, "at") == 0)
13210 mips_opts
.at
= ATREG
;
13212 else if (strcmp (name
, "noat") == 0)
13214 mips_opts
.at
= ZERO
;
13216 else if (strcmp (name
, "macro") == 0)
13218 mips_opts
.warn_about_macros
= 0;
13220 else if (strcmp (name
, "nomacro") == 0)
13222 if (mips_opts
.noreorder
== 0)
13223 as_bad (_("`noreorder' must be set before `nomacro'"));
13224 mips_opts
.warn_about_macros
= 1;
13226 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
13228 mips_opts
.nomove
= 0;
13230 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
13232 mips_opts
.nomove
= 1;
13234 else if (strcmp (name
, "bopt") == 0)
13236 mips_opts
.nobopt
= 0;
13238 else if (strcmp (name
, "nobopt") == 0)
13240 mips_opts
.nobopt
= 1;
13242 else if (strcmp (name
, "gp=default") == 0)
13243 mips_opts
.gp32
= file_mips_gp32
;
13244 else if (strcmp (name
, "gp=32") == 0)
13245 mips_opts
.gp32
= 1;
13246 else if (strcmp (name
, "gp=64") == 0)
13248 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13249 as_warn (_("%s isa does not support 64-bit registers"),
13250 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13251 mips_opts
.gp32
= 0;
13253 else if (strcmp (name
, "fp=default") == 0)
13254 mips_opts
.fp32
= file_mips_fp32
;
13255 else if (strcmp (name
, "fp=32") == 0)
13256 mips_opts
.fp32
= 1;
13257 else if (strcmp (name
, "fp=64") == 0)
13259 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13260 as_warn (_("%s isa does not support 64-bit floating point registers"),
13261 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13262 mips_opts
.fp32
= 0;
13264 else if (strcmp (name
, "softfloat") == 0)
13265 mips_opts
.soft_float
= 1;
13266 else if (strcmp (name
, "hardfloat") == 0)
13267 mips_opts
.soft_float
= 0;
13268 else if (strcmp (name
, "singlefloat") == 0)
13269 mips_opts
.single_float
= 1;
13270 else if (strcmp (name
, "doublefloat") == 0)
13271 mips_opts
.single_float
= 0;
13272 else if (strcmp (name
, "mips16") == 0
13273 || strcmp (name
, "MIPS-16") == 0)
13274 mips_opts
.mips16
= 1;
13275 else if (strcmp (name
, "nomips16") == 0
13276 || strcmp (name
, "noMIPS-16") == 0)
13277 mips_opts
.mips16
= 0;
13278 else if (strcmp (name
, "smartmips") == 0)
13280 if (!ISA_SUPPORTS_SMARTMIPS
)
13281 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13282 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13283 mips_opts
.ase_smartmips
= 1;
13285 else if (strcmp (name
, "nosmartmips") == 0)
13286 mips_opts
.ase_smartmips
= 0;
13287 else if (strcmp (name
, "mips3d") == 0)
13288 mips_opts
.ase_mips3d
= 1;
13289 else if (strcmp (name
, "nomips3d") == 0)
13290 mips_opts
.ase_mips3d
= 0;
13291 else if (strcmp (name
, "mdmx") == 0)
13292 mips_opts
.ase_mdmx
= 1;
13293 else if (strcmp (name
, "nomdmx") == 0)
13294 mips_opts
.ase_mdmx
= 0;
13295 else if (strcmp (name
, "dsp") == 0)
13297 if (!ISA_SUPPORTS_DSP_ASE
)
13298 as_warn (_("%s ISA does not support DSP ASE"),
13299 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13300 mips_opts
.ase_dsp
= 1;
13301 mips_opts
.ase_dspr2
= 0;
13303 else if (strcmp (name
, "nodsp") == 0)
13305 mips_opts
.ase_dsp
= 0;
13306 mips_opts
.ase_dspr2
= 0;
13308 else if (strcmp (name
, "dspr2") == 0)
13310 if (!ISA_SUPPORTS_DSPR2_ASE
)
13311 as_warn (_("%s ISA does not support DSP R2 ASE"),
13312 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13313 mips_opts
.ase_dspr2
= 1;
13314 mips_opts
.ase_dsp
= 1;
13316 else if (strcmp (name
, "nodspr2") == 0)
13318 mips_opts
.ase_dspr2
= 0;
13319 mips_opts
.ase_dsp
= 0;
13321 else if (strcmp (name
, "mt") == 0)
13323 if (!ISA_SUPPORTS_MT_ASE
)
13324 as_warn (_("%s ISA does not support MT ASE"),
13325 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13326 mips_opts
.ase_mt
= 1;
13328 else if (strcmp (name
, "nomt") == 0)
13329 mips_opts
.ase_mt
= 0;
13330 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
13334 /* Permit the user to change the ISA and architecture on the fly.
13335 Needless to say, misuse can cause serious problems. */
13336 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
13339 mips_opts
.isa
= file_mips_isa
;
13340 mips_opts
.arch
= file_mips_arch
;
13342 else if (strncmp (name
, "arch=", 5) == 0)
13344 const struct mips_cpu_info
*p
;
13346 p
= mips_parse_cpu("internal use", name
+ 5);
13348 as_bad (_("unknown architecture %s"), name
+ 5);
13351 mips_opts
.arch
= p
->cpu
;
13352 mips_opts
.isa
= p
->isa
;
13355 else if (strncmp (name
, "mips", 4) == 0)
13357 const struct mips_cpu_info
*p
;
13359 p
= mips_parse_cpu("internal use", name
);
13361 as_bad (_("unknown ISA level %s"), name
+ 4);
13364 mips_opts
.arch
= p
->cpu
;
13365 mips_opts
.isa
= p
->isa
;
13369 as_bad (_("unknown ISA or architecture %s"), name
);
13371 switch (mips_opts
.isa
)
13379 mips_opts
.gp32
= 1;
13380 mips_opts
.fp32
= 1;
13387 mips_opts
.gp32
= 0;
13388 mips_opts
.fp32
= 0;
13391 as_bad (_("unknown ISA level %s"), name
+ 4);
13396 mips_opts
.gp32
= file_mips_gp32
;
13397 mips_opts
.fp32
= file_mips_fp32
;
13400 else if (strcmp (name
, "autoextend") == 0)
13401 mips_opts
.noautoextend
= 0;
13402 else if (strcmp (name
, "noautoextend") == 0)
13403 mips_opts
.noautoextend
= 1;
13404 else if (strcmp (name
, "push") == 0)
13406 struct mips_option_stack
*s
;
13408 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
13409 s
->next
= mips_opts_stack
;
13410 s
->options
= mips_opts
;
13411 mips_opts_stack
= s
;
13413 else if (strcmp (name
, "pop") == 0)
13415 struct mips_option_stack
*s
;
13417 s
= mips_opts_stack
;
13419 as_bad (_(".set pop with no .set push"));
13422 /* If we're changing the reorder mode we need to handle
13423 delay slots correctly. */
13424 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
13425 start_noreorder ();
13426 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
13429 mips_opts
= s
->options
;
13430 mips_opts_stack
= s
->next
;
13434 else if (strcmp (name
, "sym32") == 0)
13435 mips_opts
.sym32
= TRUE
;
13436 else if (strcmp (name
, "nosym32") == 0)
13437 mips_opts
.sym32
= FALSE
;
13438 else if (strchr (name
, ','))
13440 /* Generic ".set" directive; use the generic handler. */
13441 *input_line_pointer
= ch
;
13442 input_line_pointer
= name
;
13448 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
13450 *input_line_pointer
= ch
;
13451 demand_empty_rest_of_line ();
13454 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13455 .option pic2. It means to generate SVR4 PIC calls. */
13458 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
13460 mips_pic
= SVR4_PIC
;
13461 mips_abicalls
= TRUE
;
13463 if (g_switch_seen
&& g_switch_value
!= 0)
13464 as_warn (_("-G may not be used with SVR4 PIC code"));
13465 g_switch_value
= 0;
13467 bfd_set_gp_size (stdoutput
, 0);
13468 demand_empty_rest_of_line ();
13471 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13472 PIC code. It sets the $gp register for the function based on the
13473 function address, which is in the register named in the argument.
13474 This uses a relocation against _gp_disp, which is handled specially
13475 by the linker. The result is:
13476 lui $gp,%hi(_gp_disp)
13477 addiu $gp,$gp,%lo(_gp_disp)
13478 addu $gp,$gp,.cpload argument
13479 The .cpload argument is normally $25 == $t9.
13481 The -mno-shared option changes this to:
13482 lui $gp,%hi(__gnu_local_gp)
13483 addiu $gp,$gp,%lo(__gnu_local_gp)
13484 and the argument is ignored. This saves an instruction, but the
13485 resulting code is not position independent; it uses an absolute
13486 address for __gnu_local_gp. Thus code assembled with -mno-shared
13487 can go into an ordinary executable, but not into a shared library. */
13490 s_cpload (int ignore ATTRIBUTE_UNUSED
)
13496 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13497 .cpload is ignored. */
13498 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13504 /* .cpload should be in a .set noreorder section. */
13505 if (mips_opts
.noreorder
== 0)
13506 as_warn (_(".cpload not in noreorder section"));
13508 reg
= tc_get_register (0);
13510 /* If we need to produce a 64-bit address, we are better off using
13511 the default instruction sequence. */
13512 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
13514 ex
.X_op
= O_symbol
;
13515 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
13517 ex
.X_op_symbol
= NULL
;
13518 ex
.X_add_number
= 0;
13520 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13521 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13524 macro_build_lui (&ex
, mips_gp_register
);
13525 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13526 mips_gp_register
, BFD_RELOC_LO16
);
13528 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
13529 mips_gp_register
, reg
);
13532 demand_empty_rest_of_line ();
13535 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13536 .cpsetup $reg1, offset|$reg2, label
13538 If offset is given, this results in:
13539 sd $gp, offset($sp)
13540 lui $gp, %hi(%neg(%gp_rel(label)))
13541 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13542 daddu $gp, $gp, $reg1
13544 If $reg2 is given, this results in:
13545 daddu $reg2, $gp, $0
13546 lui $gp, %hi(%neg(%gp_rel(label)))
13547 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13548 daddu $gp, $gp, $reg1
13549 $reg1 is normally $25 == $t9.
13551 The -mno-shared option replaces the last three instructions with
13553 addiu $gp,$gp,%lo(_gp) */
13556 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13558 expressionS ex_off
;
13559 expressionS ex_sym
;
13562 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13563 We also need NewABI support. */
13564 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13570 reg1
= tc_get_register (0);
13571 SKIP_WHITESPACE ();
13572 if (*input_line_pointer
!= ',')
13574 as_bad (_("missing argument separator ',' for .cpsetup"));
13578 ++input_line_pointer
;
13579 SKIP_WHITESPACE ();
13580 if (*input_line_pointer
== '$')
13582 mips_cpreturn_register
= tc_get_register (0);
13583 mips_cpreturn_offset
= -1;
13587 mips_cpreturn_offset
= get_absolute_expression ();
13588 mips_cpreturn_register
= -1;
13590 SKIP_WHITESPACE ();
13591 if (*input_line_pointer
!= ',')
13593 as_bad (_("missing argument separator ',' for .cpsetup"));
13597 ++input_line_pointer
;
13598 SKIP_WHITESPACE ();
13599 expression (&ex_sym
);
13602 if (mips_cpreturn_register
== -1)
13604 ex_off
.X_op
= O_constant
;
13605 ex_off
.X_add_symbol
= NULL
;
13606 ex_off
.X_op_symbol
= NULL
;
13607 ex_off
.X_add_number
= mips_cpreturn_offset
;
13609 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13610 BFD_RELOC_LO16
, SP
);
13613 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13614 mips_gp_register
, 0);
13616 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13618 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13619 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13622 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13623 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13624 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13626 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13627 mips_gp_register
, reg1
);
13633 ex
.X_op
= O_symbol
;
13634 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13635 ex
.X_op_symbol
= NULL
;
13636 ex
.X_add_number
= 0;
13638 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13639 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13641 macro_build_lui (&ex
, mips_gp_register
);
13642 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13643 mips_gp_register
, BFD_RELOC_LO16
);
13648 demand_empty_rest_of_line ();
13652 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13654 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13655 .cplocal is ignored. */
13656 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13662 mips_gp_register
= tc_get_register (0);
13663 demand_empty_rest_of_line ();
13666 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13667 offset from $sp. The offset is remembered, and after making a PIC
13668 call $gp is restored from that location. */
13671 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13675 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13676 .cprestore is ignored. */
13677 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13683 mips_cprestore_offset
= get_absolute_expression ();
13684 mips_cprestore_valid
= 1;
13686 ex
.X_op
= O_constant
;
13687 ex
.X_add_symbol
= NULL
;
13688 ex
.X_op_symbol
= NULL
;
13689 ex
.X_add_number
= mips_cprestore_offset
;
13692 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13693 SP
, HAVE_64BIT_ADDRESSES
);
13696 demand_empty_rest_of_line ();
13699 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13700 was given in the preceding .cpsetup, it results in:
13701 ld $gp, offset($sp)
13703 If a register $reg2 was given there, it results in:
13704 daddu $gp, $reg2, $0 */
13707 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13711 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13712 We also need NewABI support. */
13713 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13720 if (mips_cpreturn_register
== -1)
13722 ex
.X_op
= O_constant
;
13723 ex
.X_add_symbol
= NULL
;
13724 ex
.X_op_symbol
= NULL
;
13725 ex
.X_add_number
= mips_cpreturn_offset
;
13727 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13730 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13731 mips_cpreturn_register
, 0);
13734 demand_empty_rest_of_line ();
13737 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13738 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13739 use in DWARF debug information. */
13742 s_dtprel_internal (size_t bytes
)
13749 if (ex
.X_op
!= O_symbol
)
13751 as_bad (_("Unsupported use of %s"), (bytes
== 8
13754 ignore_rest_of_line ();
13757 p
= frag_more (bytes
);
13758 md_number_to_chars (p
, 0, bytes
);
13759 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13761 ? BFD_RELOC_MIPS_TLS_DTPREL64
13762 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13764 demand_empty_rest_of_line ();
13767 /* Handle .dtprelword. */
13770 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13772 s_dtprel_internal (4);
13775 /* Handle .dtpreldword. */
13778 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13780 s_dtprel_internal (8);
13783 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13784 code. It sets the offset to use in gp_rel relocations. */
13787 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13789 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13790 We also need NewABI support. */
13791 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13797 mips_gprel_offset
= get_absolute_expression ();
13799 demand_empty_rest_of_line ();
13802 /* Handle the .gpword pseudo-op. This is used when generating PIC
13803 code. It generates a 32 bit GP relative reloc. */
13806 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13808 segment_info_type
*si
;
13809 struct insn_label_list
*l
;
13814 /* When not generating PIC code, this is treated as .word. */
13815 if (mips_pic
!= SVR4_PIC
)
13821 si
= seg_info (now_seg
);
13822 l
= si
->label_list
;
13823 label
= l
!= NULL
? l
->label
: NULL
;
13824 mips_emit_delays ();
13826 mips_align (2, 0, label
);
13829 mips_clear_insn_labels ();
13831 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13833 as_bad (_("Unsupported use of .gpword"));
13834 ignore_rest_of_line ();
13838 md_number_to_chars (p
, 0, 4);
13839 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13840 BFD_RELOC_GPREL32
);
13842 demand_empty_rest_of_line ();
13846 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13848 segment_info_type
*si
;
13849 struct insn_label_list
*l
;
13854 /* When not generating PIC code, this is treated as .dword. */
13855 if (mips_pic
!= SVR4_PIC
)
13861 si
= seg_info (now_seg
);
13862 l
= si
->label_list
;
13863 label
= l
!= NULL
? l
->label
: NULL
;
13864 mips_emit_delays ();
13866 mips_align (3, 0, label
);
13869 mips_clear_insn_labels ();
13871 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13873 as_bad (_("Unsupported use of .gpdword"));
13874 ignore_rest_of_line ();
13878 md_number_to_chars (p
, 0, 8);
13879 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13880 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13882 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13883 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13884 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13886 demand_empty_rest_of_line ();
13889 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13890 tables in SVR4 PIC code. */
13893 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13897 /* This is ignored when not generating SVR4 PIC code. */
13898 if (mips_pic
!= SVR4_PIC
)
13904 /* Add $gp to the register named as an argument. */
13906 reg
= tc_get_register (0);
13907 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13910 demand_empty_rest_of_line ();
13913 /* Handle the .insn pseudo-op. This marks instruction labels in
13914 mips16 mode. This permits the linker to handle them specially,
13915 such as generating jalx instructions when needed. We also make
13916 them odd for the duration of the assembly, in order to generate the
13917 right sort of code. We will make them even in the adjust_symtab
13918 routine, while leaving them marked. This is convenient for the
13919 debugger and the disassembler. The linker knows to make them odd
13923 s_insn (int ignore ATTRIBUTE_UNUSED
)
13925 mips16_mark_labels ();
13927 demand_empty_rest_of_line ();
13930 /* Handle a .stabn directive. We need these in order to mark a label
13931 as being a mips16 text label correctly. Sometimes the compiler
13932 will emit a label, followed by a .stabn, and then switch sections.
13933 If the label and .stabn are in mips16 mode, then the label is
13934 really a mips16 text label. */
13937 s_mips_stab (int type
)
13940 mips16_mark_labels ();
13945 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13948 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13955 name
= input_line_pointer
;
13956 c
= get_symbol_end ();
13957 symbolP
= symbol_find_or_make (name
);
13958 S_SET_WEAK (symbolP
);
13959 *input_line_pointer
= c
;
13961 SKIP_WHITESPACE ();
13963 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13965 if (S_IS_DEFINED (symbolP
))
13967 as_bad (_("ignoring attempt to redefine symbol %s"),
13968 S_GET_NAME (symbolP
));
13969 ignore_rest_of_line ();
13973 if (*input_line_pointer
== ',')
13975 ++input_line_pointer
;
13976 SKIP_WHITESPACE ();
13980 if (exp
.X_op
!= O_symbol
)
13982 as_bad (_("bad .weakext directive"));
13983 ignore_rest_of_line ();
13986 symbol_set_value_expression (symbolP
, &exp
);
13989 demand_empty_rest_of_line ();
13992 /* Parse a register string into a number. Called from the ECOFF code
13993 to parse .frame. The argument is non-zero if this is the frame
13994 register, so that we can record it in mips_frame_reg. */
13997 tc_get_register (int frame
)
14001 SKIP_WHITESPACE ();
14002 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
14006 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
14007 mips_frame_reg_valid
= 1;
14008 mips_cprestore_valid
= 0;
14014 md_section_align (asection
*seg
, valueT addr
)
14016 int align
= bfd_get_section_alignment (stdoutput
, seg
);
14020 /* We don't need to align ELF sections to the full alignment.
14021 However, Irix 5 may prefer that we align them at least to a 16
14022 byte boundary. We don't bother to align the sections if we
14023 are targeted for an embedded system. */
14024 if (strncmp (TARGET_OS
, "elf", 3) == 0)
14030 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
14033 /* Utility routine, called from above as well. If called while the
14034 input file is still being read, it's only an approximation. (For
14035 example, a symbol may later become defined which appeared to be
14036 undefined earlier.) */
14039 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
14044 if (g_switch_value
> 0)
14046 const char *symname
;
14049 /* Find out whether this symbol can be referenced off the $gp
14050 register. It can be if it is smaller than the -G size or if
14051 it is in the .sdata or .sbss section. Certain symbols can
14052 not be referenced off the $gp, although it appears as though
14054 symname
= S_GET_NAME (sym
);
14055 if (symname
!= (const char *) NULL
14056 && (strcmp (symname
, "eprol") == 0
14057 || strcmp (symname
, "etext") == 0
14058 || strcmp (symname
, "_gp") == 0
14059 || strcmp (symname
, "edata") == 0
14060 || strcmp (symname
, "_fbss") == 0
14061 || strcmp (symname
, "_fdata") == 0
14062 || strcmp (symname
, "_ftext") == 0
14063 || strcmp (symname
, "end") == 0
14064 || strcmp (symname
, "_gp_disp") == 0))
14066 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
14068 #ifndef NO_ECOFF_DEBUGGING
14069 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
14070 && (symbol_get_obj (sym
)->ecoff_extern_size
14071 <= g_switch_value
))
14073 /* We must defer this decision until after the whole
14074 file has been read, since there might be a .extern
14075 after the first use of this symbol. */
14076 || (before_relaxing
14077 #ifndef NO_ECOFF_DEBUGGING
14078 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
14080 && S_GET_VALUE (sym
) == 0)
14081 || (S_GET_VALUE (sym
) != 0
14082 && S_GET_VALUE (sym
) <= g_switch_value
)))
14086 const char *segname
;
14088 segname
= segment_name (S_GET_SEGMENT (sym
));
14089 gas_assert (strcmp (segname
, ".lit8") != 0
14090 && strcmp (segname
, ".lit4") != 0);
14091 change
= (strcmp (segname
, ".sdata") != 0
14092 && strcmp (segname
, ".sbss") != 0
14093 && strncmp (segname
, ".sdata.", 7) != 0
14094 && strncmp (segname
, ".sbss.", 6) != 0
14095 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
14096 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
14101 /* We are not optimizing for the $gp register. */
14106 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14109 pic_need_relax (symbolS
*sym
, asection
*segtype
)
14113 /* Handle the case of a symbol equated to another symbol. */
14114 while (symbol_equated_reloc_p (sym
))
14118 /* It's possible to get a loop here in a badly written program. */
14119 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
14125 if (symbol_section_p (sym
))
14128 symsec
= S_GET_SEGMENT (sym
);
14130 /* This must duplicate the test in adjust_reloc_syms. */
14131 return (symsec
!= &bfd_und_section
14132 && symsec
!= &bfd_abs_section
14133 && !bfd_is_com_section (symsec
)
14134 && !s_is_linkonce (sym
, segtype
)
14136 /* A global or weak symbol is treated as external. */
14137 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
14143 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14144 extended opcode. SEC is the section the frag is in. */
14147 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
14150 const struct mips16_immed_operand
*op
;
14152 int mintiny
, maxtiny
;
14156 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
14158 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
14161 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14162 op
= mips16_immed_operands
;
14163 while (op
->type
!= type
)
14166 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14171 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14174 maxtiny
= 1 << op
->nbits
;
14179 maxtiny
= (1 << op
->nbits
) - 1;
14184 mintiny
= - (1 << (op
->nbits
- 1));
14185 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14188 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
14189 val
= S_GET_VALUE (fragp
->fr_symbol
);
14190 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
14196 /* We won't have the section when we are called from
14197 mips_relax_frag. However, we will always have been called
14198 from md_estimate_size_before_relax first. If this is a
14199 branch to a different section, we mark it as such. If SEC is
14200 NULL, and the frag is not marked, then it must be a branch to
14201 the same section. */
14204 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
14209 /* Must have been called from md_estimate_size_before_relax. */
14212 fragp
->fr_subtype
=
14213 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14215 /* FIXME: We should support this, and let the linker
14216 catch branches and loads that are out of range. */
14217 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
14218 _("unsupported PC relative reference to different section"));
14222 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
14223 /* Assume non-extended on the first relaxation pass.
14224 The address we have calculated will be bogus if this is
14225 a forward branch to another frag, as the forward frag
14226 will have fr_address == 0. */
14230 /* In this case, we know for sure that the symbol fragment is in
14231 the same section. If the relax_marker of the symbol fragment
14232 differs from the relax_marker of this fragment, we have not
14233 yet adjusted the symbol fragment fr_address. We want to add
14234 in STRETCH in order to get a better estimate of the address.
14235 This particularly matters because of the shift bits. */
14237 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
14241 /* Adjust stretch for any alignment frag. Note that if have
14242 been expanding the earlier code, the symbol may be
14243 defined in what appears to be an earlier frag. FIXME:
14244 This doesn't handle the fr_subtype field, which specifies
14245 a maximum number of bytes to skip when doing an
14247 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
14249 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
14252 stretch
= - ((- stretch
)
14253 & ~ ((1 << (int) f
->fr_offset
) - 1));
14255 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
14264 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14266 /* The base address rules are complicated. The base address of
14267 a branch is the following instruction. The base address of a
14268 PC relative load or add is the instruction itself, but if it
14269 is in a delay slot (in which case it can not be extended) use
14270 the address of the instruction whose delay slot it is in. */
14271 if (type
== 'p' || type
== 'q')
14275 /* If we are currently assuming that this frag should be
14276 extended, then, the current address is two bytes
14278 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14281 /* Ignore the low bit in the target, since it will be set
14282 for a text label. */
14283 if ((val
& 1) != 0)
14286 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14288 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14291 val
-= addr
& ~ ((1 << op
->shift
) - 1);
14293 /* Branch offsets have an implicit 0 in the lowest bit. */
14294 if (type
== 'p' || type
== 'q')
14297 /* If any of the shifted bits are set, we must use an extended
14298 opcode. If the address depends on the size of this
14299 instruction, this can lead to a loop, so we arrange to always
14300 use an extended opcode. We only check this when we are in
14301 the main relaxation loop, when SEC is NULL. */
14302 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
14304 fragp
->fr_subtype
=
14305 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14309 /* If we are about to mark a frag as extended because the value
14310 is precisely maxtiny + 1, then there is a chance of an
14311 infinite loop as in the following code:
14316 In this case when the la is extended, foo is 0x3fc bytes
14317 away, so the la can be shrunk, but then foo is 0x400 away, so
14318 the la must be extended. To avoid this loop, we mark the
14319 frag as extended if it was small, and is about to become
14320 extended with a value of maxtiny + 1. */
14321 if (val
== ((maxtiny
+ 1) << op
->shift
)
14322 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
14325 fragp
->fr_subtype
=
14326 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14330 else if (symsec
!= absolute_section
&& sec
!= NULL
)
14331 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
14333 if ((val
& ((1 << op
->shift
) - 1)) != 0
14334 || val
< (mintiny
<< op
->shift
)
14335 || val
> (maxtiny
<< op
->shift
))
14341 /* Compute the length of a branch sequence, and adjust the
14342 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14343 worst-case length is computed, with UPDATE being used to indicate
14344 whether an unconditional (-1), branch-likely (+1) or regular (0)
14345 branch is to be computed. */
14347 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
14349 bfd_boolean toofar
;
14353 && S_IS_DEFINED (fragp
->fr_symbol
)
14354 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
14359 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
14361 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
14365 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
14368 /* If the symbol is not defined or it's in a different segment,
14369 assume the user knows what's going on and emit a short
14375 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14377 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
14378 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
14379 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
14380 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
14386 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
14389 if (mips_pic
!= NO_PIC
)
14391 /* Additional space for PIC loading of target address. */
14393 if (mips_opts
.isa
== ISA_MIPS1
)
14394 /* Additional space for $at-stabilizing nop. */
14398 /* If branch is conditional. */
14399 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
14406 /* Estimate the size of a frag before relaxing. Unless this is the
14407 mips16, we are not really relaxing here, and the final size is
14408 encoded in the subtype information. For the mips16, we have to
14409 decide whether we are using an extended opcode or not. */
14412 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
14416 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14419 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
14421 return fragp
->fr_var
;
14424 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14425 /* We don't want to modify the EXTENDED bit here; it might get us
14426 into infinite loops. We change it only in mips_relax_frag(). */
14427 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
14429 if (mips_pic
== NO_PIC
)
14430 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
14431 else if (mips_pic
== SVR4_PIC
)
14432 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
14433 else if (mips_pic
== VXWORKS_PIC
)
14434 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14441 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
14442 return -RELAX_FIRST (fragp
->fr_subtype
);
14445 return -RELAX_SECOND (fragp
->fr_subtype
);
14448 /* This is called to see whether a reloc against a defined symbol
14449 should be converted into a reloc against a section. */
14452 mips_fix_adjustable (fixS
*fixp
)
14454 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14455 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14458 if (fixp
->fx_addsy
== NULL
)
14461 /* If symbol SYM is in a mergeable section, relocations of the form
14462 SYM + 0 can usually be made section-relative. The mergeable data
14463 is then identified by the section offset rather than by the symbol.
14465 However, if we're generating REL LO16 relocations, the offset is split
14466 between the LO16 and parterning high part relocation. The linker will
14467 need to recalculate the complete offset in order to correctly identify
14470 The linker has traditionally not looked for the parterning high part
14471 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14472 placed anywhere. Rather than break backwards compatibility by changing
14473 this, it seems better not to force the issue, and instead keep the
14474 original symbol. This will work with either linker behavior. */
14475 if ((lo16_reloc_p (fixp
->fx_r_type
)
14476 || reloc_needs_lo_p (fixp
->fx_r_type
))
14477 && HAVE_IN_PLACE_ADDENDS
14478 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
14481 /* There is no place to store an in-place offset for JALR relocations.
14482 Likewise an in-range offset of PC-relative relocations may overflow
14483 the in-place relocatable field if recalculated against the start
14484 address of the symbol's containing section. */
14485 if (HAVE_IN_PLACE_ADDENDS
14486 && (fixp
->fx_pcrel
|| fixp
->fx_r_type
== BFD_RELOC_MIPS_JALR
))
14490 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14491 to a floating-point stub. The same is true for non-R_MIPS16_26
14492 relocations against MIPS16 functions; in this case, the stub becomes
14493 the function's canonical address.
14495 Floating-point stubs are stored in unique .mips16.call.* or
14496 .mips16.fn.* sections. If a stub T for function F is in section S,
14497 the first relocation in section S must be against F; this is how the
14498 linker determines the target function. All relocations that might
14499 resolve to T must also be against F. We therefore have the following
14500 restrictions, which are given in an intentionally-redundant way:
14502 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14505 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14506 if that stub might be used.
14508 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14511 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14512 that stub might be used.
14514 There is a further restriction:
14516 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14517 on targets with in-place addends; the relocation field cannot
14518 encode the low bit.
14520 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14521 against a MIPS16 symbol.
14523 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14524 relocation against some symbol R, no relocation against R may be
14525 reduced. (Note that this deals with (2) as well as (1) because
14526 relocations against global symbols will never be reduced on ELF
14527 targets.) This approach is a little simpler than trying to detect
14528 stub sections, and gives the "all or nothing" per-symbol consistency
14529 that we have for MIPS16 symbols. */
14531 && fixp
->fx_subsy
== NULL
14532 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
14533 || *symbol_get_tc (fixp
->fx_addsy
)))
14540 /* Translate internal representation of relocation info to BFD target
14544 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14546 static arelent
*retval
[4];
14548 bfd_reloc_code_real_type code
;
14550 memset (retval
, 0, sizeof(retval
));
14551 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
14552 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14553 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14554 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14556 if (fixp
->fx_pcrel
)
14558 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14560 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14561 Relocations want only the symbol offset. */
14562 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14565 /* A gruesome hack which is a result of the gruesome gas
14566 reloc handling. What's worse, for COFF (as opposed to
14567 ECOFF), we might need yet another copy of reloc->address.
14568 See bfd_install_relocation. */
14569 reloc
->addend
+= reloc
->address
;
14573 reloc
->addend
= fixp
->fx_addnumber
;
14575 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14576 entry to be used in the relocation's section offset. */
14577 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14579 reloc
->address
= reloc
->addend
;
14583 code
= fixp
->fx_r_type
;
14585 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14586 if (reloc
->howto
== NULL
)
14588 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14589 _("Can not represent %s relocation in this object file format"),
14590 bfd_get_reloc_code_name (code
));
14597 /* Relax a machine dependent frag. This returns the amount by which
14598 the current size of the frag should change. */
14601 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14603 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14605 offsetT old_var
= fragp
->fr_var
;
14607 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14609 return fragp
->fr_var
- old_var
;
14612 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14615 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14617 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14619 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14624 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14626 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14633 /* Convert a machine dependent frag. */
14636 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14638 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14641 unsigned long insn
;
14645 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14647 if (target_big_endian
)
14648 insn
= bfd_getb32 (buf
);
14650 insn
= bfd_getl32 (buf
);
14652 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14654 /* We generate a fixup instead of applying it right now
14655 because, if there are linker relaxations, we're going to
14656 need the relocations. */
14657 exp
.X_op
= O_symbol
;
14658 exp
.X_add_symbol
= fragp
->fr_symbol
;
14659 exp
.X_add_number
= fragp
->fr_offset
;
14661 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14662 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14663 fixp
->fx_file
= fragp
->fr_file
;
14664 fixp
->fx_line
= fragp
->fr_line
;
14666 md_number_to_chars ((char *) buf
, insn
, 4);
14673 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14674 _("Relaxed out-of-range branch into a jump"));
14676 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14679 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14681 /* Reverse the branch. */
14682 switch ((insn
>> 28) & 0xf)
14685 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14686 have the condition reversed by tweaking a single
14687 bit, and their opcodes all have 0x4???????. */
14688 gas_assert ((insn
& 0xf1000000) == 0x41000000);
14689 insn
^= 0x00010000;
14693 /* bltz 0x04000000 bgez 0x04010000
14694 bltzal 0x04100000 bgezal 0x04110000 */
14695 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
14696 insn
^= 0x00010000;
14700 /* beq 0x10000000 bne 0x14000000
14701 blez 0x18000000 bgtz 0x1c000000 */
14702 insn
^= 0x04000000;
14710 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14712 /* Clear the and-link bit. */
14713 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
14715 /* bltzal 0x04100000 bgezal 0x04110000
14716 bltzall 0x04120000 bgezall 0x04130000 */
14717 insn
&= ~0x00100000;
14720 /* Branch over the branch (if the branch was likely) or the
14721 full jump (not likely case). Compute the offset from the
14722 current instruction to branch to. */
14723 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14727 /* How many bytes in instructions we've already emitted? */
14728 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14729 /* How many bytes in instructions from here to the end? */
14730 i
= fragp
->fr_var
- i
;
14732 /* Convert to instruction count. */
14734 /* Branch counts from the next instruction. */
14737 /* Branch over the jump. */
14738 md_number_to_chars ((char *) buf
, insn
, 4);
14742 md_number_to_chars ((char *) buf
, 0, 4);
14745 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14747 /* beql $0, $0, 2f */
14749 /* Compute the PC offset from the current instruction to
14750 the end of the variable frag. */
14751 /* How many bytes in instructions we've already emitted? */
14752 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14753 /* How many bytes in instructions from here to the end? */
14754 i
= fragp
->fr_var
- i
;
14755 /* Convert to instruction count. */
14757 /* Don't decrement i, because we want to branch over the
14761 md_number_to_chars ((char *) buf
, insn
, 4);
14764 md_number_to_chars ((char *) buf
, 0, 4);
14769 if (mips_pic
== NO_PIC
)
14772 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14773 ? 0x0c000000 : 0x08000000);
14774 exp
.X_op
= O_symbol
;
14775 exp
.X_add_symbol
= fragp
->fr_symbol
;
14776 exp
.X_add_number
= fragp
->fr_offset
;
14778 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14779 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14780 fixp
->fx_file
= fragp
->fr_file
;
14781 fixp
->fx_line
= fragp
->fr_line
;
14783 md_number_to_chars ((char *) buf
, insn
, 4);
14788 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
14790 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14791 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
14792 insn
|= at
<< OP_SH_RT
;
14793 exp
.X_op
= O_symbol
;
14794 exp
.X_add_symbol
= fragp
->fr_symbol
;
14795 exp
.X_add_number
= fragp
->fr_offset
;
14797 if (fragp
->fr_offset
)
14799 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14800 exp
.X_add_number
= 0;
14803 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14804 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14805 fixp
->fx_file
= fragp
->fr_file
;
14806 fixp
->fx_line
= fragp
->fr_line
;
14808 md_number_to_chars ((char *) buf
, insn
, 4);
14811 if (mips_opts
.isa
== ISA_MIPS1
)
14814 md_number_to_chars ((char *) buf
, 0, 4);
14818 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14819 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
14820 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
14822 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14823 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14824 fixp
->fx_file
= fragp
->fr_file
;
14825 fixp
->fx_line
= fragp
->fr_line
;
14827 md_number_to_chars ((char *) buf
, insn
, 4);
14831 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14835 insn
|= at
<< OP_SH_RS
;
14837 md_number_to_chars ((char *) buf
, insn
, 4);
14842 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
14843 + fragp
->fr_fix
+ fragp
->fr_var
);
14845 fragp
->fr_fix
+= fragp
->fr_var
;
14850 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14853 const struct mips16_immed_operand
*op
;
14854 bfd_boolean small
, ext
;
14857 unsigned long insn
;
14858 bfd_boolean use_extend
;
14859 unsigned short extend
;
14861 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14862 op
= mips16_immed_operands
;
14863 while (op
->type
!= type
)
14866 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14877 val
= resolve_symbol_value (fragp
->fr_symbol
);
14882 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14884 /* The rules for the base address of a PC relative reloc are
14885 complicated; see mips16_extended_frag. */
14886 if (type
== 'p' || type
== 'q')
14891 /* Ignore the low bit in the target, since it will be
14892 set for a text label. */
14893 if ((val
& 1) != 0)
14896 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14898 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14901 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14904 /* Make sure the section winds up with the alignment we have
14907 record_alignment (asec
, op
->shift
);
14911 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14912 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14913 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14914 _("extended instruction in delay slot"));
14916 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14918 if (target_big_endian
)
14919 insn
= bfd_getb16 (buf
);
14921 insn
= bfd_getl16 (buf
);
14923 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14924 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14925 small
, ext
, &insn
, &use_extend
, &extend
);
14929 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14930 fragp
->fr_fix
+= 2;
14934 md_number_to_chars ((char *) buf
, insn
, 2);
14935 fragp
->fr_fix
+= 2;
14943 first
= RELAX_FIRST (fragp
->fr_subtype
);
14944 second
= RELAX_SECOND (fragp
->fr_subtype
);
14945 fixp
= (fixS
*) fragp
->fr_opcode
;
14947 /* Possibly emit a warning if we've chosen the longer option. */
14948 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14949 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14951 const char *msg
= macro_warning (fragp
->fr_subtype
);
14953 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
14956 /* Go through all the fixups for the first sequence. Disable them
14957 (by marking them as done) if we're going to use the second
14958 sequence instead. */
14960 && fixp
->fx_frag
== fragp
14961 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14963 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14965 fixp
= fixp
->fx_next
;
14968 /* Go through the fixups for the second sequence. Disable them if
14969 we're going to use the first sequence, otherwise adjust their
14970 addresses to account for the relaxation. */
14971 while (fixp
&& fixp
->fx_frag
== fragp
)
14973 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14974 fixp
->fx_where
-= first
;
14977 fixp
= fixp
->fx_next
;
14980 /* Now modify the frag contents. */
14981 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14985 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14986 memmove (start
, start
+ first
, second
);
14987 fragp
->fr_fix
-= first
;
14990 fragp
->fr_fix
-= second
;
14996 /* This function is called after the relocs have been generated.
14997 We've been storing mips16 text labels as odd. Here we convert them
14998 back to even for the convenience of the debugger. */
15001 mips_frob_file_after_relocs (void)
15004 unsigned int count
, i
;
15009 syms
= bfd_get_outsymbols (stdoutput
);
15010 count
= bfd_get_symcount (stdoutput
);
15011 for (i
= 0; i
< count
; i
++, syms
++)
15013 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
15014 && ((*syms
)->value
& 1) != 0)
15016 (*syms
)->value
&= ~1;
15017 /* If the symbol has an odd size, it was probably computed
15018 incorrectly, so adjust that as well. */
15019 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
15020 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
15027 /* This function is called whenever a label is defined, including fake
15028 labels instantiated off the dot special symbol. It is used when
15029 handling branch delays; if a branch has a label, we assume we cannot
15030 move it. This also bumps the value of the symbol by 1 in compressed
15034 mips_record_label (symbolS
*sym
)
15036 segment_info_type
*si
= seg_info (now_seg
);
15037 struct insn_label_list
*l
;
15039 if (free_insn_labels
== NULL
)
15040 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
15043 l
= free_insn_labels
;
15044 free_insn_labels
= l
->next
;
15048 l
->next
= si
->label_list
;
15049 si
->label_list
= l
;
15052 /* This function is called as tc_frob_label() whenever a label is defined
15053 and adds a DWARF-2 record we only want for true labels. */
15056 mips_define_label (symbolS
*sym
)
15058 mips_record_label (sym
);
15060 dwarf2_emit_label (sym
);
15064 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15066 /* Some special processing for a MIPS ELF file. */
15069 mips_elf_final_processing (void)
15071 /* Write out the register information. */
15072 if (mips_abi
!= N64_ABI
)
15076 s
.ri_gprmask
= mips_gprmask
;
15077 s
.ri_cprmask
[0] = mips_cprmask
[0];
15078 s
.ri_cprmask
[1] = mips_cprmask
[1];
15079 s
.ri_cprmask
[2] = mips_cprmask
[2];
15080 s
.ri_cprmask
[3] = mips_cprmask
[3];
15081 /* The gp_value field is set by the MIPS ELF backend. */
15083 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
15084 ((Elf32_External_RegInfo
*)
15085 mips_regmask_frag
));
15089 Elf64_Internal_RegInfo s
;
15091 s
.ri_gprmask
= mips_gprmask
;
15093 s
.ri_cprmask
[0] = mips_cprmask
[0];
15094 s
.ri_cprmask
[1] = mips_cprmask
[1];
15095 s
.ri_cprmask
[2] = mips_cprmask
[2];
15096 s
.ri_cprmask
[3] = mips_cprmask
[3];
15097 /* The gp_value field is set by the MIPS ELF backend. */
15099 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
15100 ((Elf64_External_RegInfo
*)
15101 mips_regmask_frag
));
15104 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15105 sort of BFD interface for this. */
15106 if (mips_any_noreorder
)
15107 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
15108 if (mips_pic
!= NO_PIC
)
15110 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
15111 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
15114 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
15116 /* Set MIPS ELF flags for ASEs. */
15117 /* We may need to define a new flag for DSP ASE, and set this flag when
15118 file_ase_dsp is true. */
15119 /* Same for DSP R2. */
15120 /* We may need to define a new flag for MT ASE, and set this flag when
15121 file_ase_mt is true. */
15122 if (file_ase_mips16
)
15123 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
15124 #if 0 /* XXX FIXME */
15125 if (file_ase_mips3d
)
15126 elf_elfheader (stdoutput
)->e_flags
|= ???;
15129 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
15131 /* Set the MIPS ELF ABI flags. */
15132 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
15133 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
15134 else if (mips_abi
== O64_ABI
)
15135 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
15136 else if (mips_abi
== EABI_ABI
)
15138 if (!file_mips_gp32
)
15139 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
15141 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
15143 else if (mips_abi
== N32_ABI
)
15144 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
15146 /* Nothing to do for N64_ABI. */
15148 if (mips_32bitmode
)
15149 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
15151 #if 0 /* XXX FIXME */
15152 /* 32 bit code with 64 bit FP registers. */
15153 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
15154 elf_elfheader (stdoutput
)->e_flags
|= ???;
15158 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15160 typedef struct proc
{
15162 symbolS
*func_end_sym
;
15163 unsigned long reg_mask
;
15164 unsigned long reg_offset
;
15165 unsigned long fpreg_mask
;
15166 unsigned long fpreg_offset
;
15167 unsigned long frame_offset
;
15168 unsigned long frame_reg
;
15169 unsigned long pc_reg
;
15172 static procS cur_proc
;
15173 static procS
*cur_proc_ptr
;
15174 static int numprocs
;
15176 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15180 mips_nop_opcode (void)
15182 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
15185 /* Fill in an rs_align_code fragment. This only needs to do something
15186 for MIPS16 code, where 0 is not a nop. */
15189 mips_handle_align (fragS
*fragp
)
15192 int bytes
, size
, excess
;
15195 if (fragp
->fr_type
!= rs_align_code
)
15198 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
15201 opcode
= mips16_nop_insn
.insn_opcode
;
15206 opcode
= nop_insn
.insn_opcode
;
15210 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
15211 excess
= bytes
% size
;
15214 /* If we're not inserting a whole number of instructions,
15215 pad the end of the fixed part of the frag with zeros. */
15216 memset (p
, 0, excess
);
15218 fragp
->fr_fix
+= excess
;
15221 md_number_to_chars (p
, opcode
, size
);
15222 fragp
->fr_var
= size
;
15226 md_obj_begin (void)
15233 /* Check for premature end, nesting errors, etc. */
15235 as_warn (_("missing .end at end of assembly"));
15244 if (*input_line_pointer
== '-')
15246 ++input_line_pointer
;
15249 if (!ISDIGIT (*input_line_pointer
))
15250 as_bad (_("expected simple number"));
15251 if (input_line_pointer
[0] == '0')
15253 if (input_line_pointer
[1] == 'x')
15255 input_line_pointer
+= 2;
15256 while (ISXDIGIT (*input_line_pointer
))
15259 val
|= hex_value (*input_line_pointer
++);
15261 return negative
? -val
: val
;
15265 ++input_line_pointer
;
15266 while (ISDIGIT (*input_line_pointer
))
15269 val
|= *input_line_pointer
++ - '0';
15271 return negative
? -val
: val
;
15274 if (!ISDIGIT (*input_line_pointer
))
15276 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15277 *input_line_pointer
, *input_line_pointer
);
15278 as_warn (_("invalid number"));
15281 while (ISDIGIT (*input_line_pointer
))
15284 val
+= *input_line_pointer
++ - '0';
15286 return negative
? -val
: val
;
15289 /* The .file directive; just like the usual .file directive, but there
15290 is an initial number which is the ECOFF file index. In the non-ECOFF
15291 case .file implies DWARF-2. */
15294 s_mips_file (int x ATTRIBUTE_UNUSED
)
15296 static int first_file_directive
= 0;
15298 if (ECOFF_DEBUGGING
)
15307 filename
= dwarf2_directive_file (0);
15309 /* Versions of GCC up to 3.1 start files with a ".file"
15310 directive even for stabs output. Make sure that this
15311 ".file" is handled. Note that you need a version of GCC
15312 after 3.1 in order to support DWARF-2 on MIPS. */
15313 if (filename
!= NULL
&& ! first_file_directive
)
15315 (void) new_logical_line (filename
, -1);
15316 s_app_file_string (filename
, 0);
15318 first_file_directive
= 1;
15322 /* The .loc directive, implying DWARF-2. */
15325 s_mips_loc (int x ATTRIBUTE_UNUSED
)
15327 if (!ECOFF_DEBUGGING
)
15328 dwarf2_directive_loc (0);
15331 /* The .end directive. */
15334 s_mips_end (int x ATTRIBUTE_UNUSED
)
15338 /* Following functions need their own .frame and .cprestore directives. */
15339 mips_frame_reg_valid
= 0;
15340 mips_cprestore_valid
= 0;
15342 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15345 demand_empty_rest_of_line ();
15350 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15351 as_warn (_(".end not in text section"));
15355 as_warn (_(".end directive without a preceding .ent directive."));
15356 demand_empty_rest_of_line ();
15362 gas_assert (S_GET_NAME (p
));
15363 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
15364 as_warn (_(".end symbol does not match .ent symbol."));
15366 if (debug_type
== DEBUG_STABS
)
15367 stabs_generate_asm_endfunc (S_GET_NAME (p
),
15371 as_warn (_(".end directive missing or unknown symbol"));
15374 /* Create an expression to calculate the size of the function. */
15375 if (p
&& cur_proc_ptr
)
15377 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
15378 expressionS
*exp
= xmalloc (sizeof (expressionS
));
15381 exp
->X_op
= O_subtract
;
15382 exp
->X_add_symbol
= symbol_temp_new_now ();
15383 exp
->X_op_symbol
= p
;
15384 exp
->X_add_number
= 0;
15386 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
15389 /* Generate a .pdr section. */
15390 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
15392 segT saved_seg
= now_seg
;
15393 subsegT saved_subseg
= now_subseg
;
15397 #ifdef md_flush_pending_output
15398 md_flush_pending_output ();
15401 gas_assert (pdr_seg
);
15402 subseg_set (pdr_seg
, 0);
15404 /* Write the symbol. */
15405 exp
.X_op
= O_symbol
;
15406 exp
.X_add_symbol
= p
;
15407 exp
.X_add_number
= 0;
15408 emit_expr (&exp
, 4);
15410 fragp
= frag_more (7 * 4);
15412 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
15413 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
15414 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
15415 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
15416 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
15417 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
15418 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
15420 subseg_set (saved_seg
, saved_subseg
);
15422 #endif /* OBJ_ELF */
15424 cur_proc_ptr
= NULL
;
15427 /* The .aent and .ent directives. */
15430 s_mips_ent (int aent
)
15434 symbolP
= get_symbol ();
15435 if (*input_line_pointer
== ',')
15436 ++input_line_pointer
;
15437 SKIP_WHITESPACE ();
15438 if (ISDIGIT (*input_line_pointer
)
15439 || *input_line_pointer
== '-')
15442 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15443 as_warn (_(".ent or .aent not in text section."));
15445 if (!aent
&& cur_proc_ptr
)
15446 as_warn (_("missing .end"));
15450 /* This function needs its own .frame and .cprestore directives. */
15451 mips_frame_reg_valid
= 0;
15452 mips_cprestore_valid
= 0;
15454 cur_proc_ptr
= &cur_proc
;
15455 memset (cur_proc_ptr
, '\0', sizeof (procS
));
15457 cur_proc_ptr
->func_sym
= symbolP
;
15461 if (debug_type
== DEBUG_STABS
)
15462 stabs_generate_asm_func (S_GET_NAME (symbolP
),
15463 S_GET_NAME (symbolP
));
15466 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
15468 demand_empty_rest_of_line ();
15471 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15472 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15473 s_mips_frame is used so that we can set the PDR information correctly.
15474 We can't use the ecoff routines because they make reference to the ecoff
15475 symbol table (in the mdebug section). */
15478 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
15481 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15485 if (cur_proc_ptr
== (procS
*) NULL
)
15487 as_warn (_(".frame outside of .ent"));
15488 demand_empty_rest_of_line ();
15492 cur_proc_ptr
->frame_reg
= tc_get_register (1);
15494 SKIP_WHITESPACE ();
15495 if (*input_line_pointer
++ != ','
15496 || get_absolute_expression_and_terminator (&val
) != ',')
15498 as_warn (_("Bad .frame directive"));
15499 --input_line_pointer
;
15500 demand_empty_rest_of_line ();
15504 cur_proc_ptr
->frame_offset
= val
;
15505 cur_proc_ptr
->pc_reg
= tc_get_register (0);
15507 demand_empty_rest_of_line ();
15510 #endif /* OBJ_ELF */
15514 /* The .fmask and .mask directives. If the mdebug section is present
15515 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15516 embedded targets, s_mips_mask is used so that we can set the PDR
15517 information correctly. We can't use the ecoff routines because they
15518 make reference to the ecoff symbol table (in the mdebug section). */
15521 s_mips_mask (int reg_type
)
15524 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15528 if (cur_proc_ptr
== (procS
*) NULL
)
15530 as_warn (_(".mask/.fmask outside of .ent"));
15531 demand_empty_rest_of_line ();
15535 if (get_absolute_expression_and_terminator (&mask
) != ',')
15537 as_warn (_("Bad .mask/.fmask directive"));
15538 --input_line_pointer
;
15539 demand_empty_rest_of_line ();
15543 off
= get_absolute_expression ();
15545 if (reg_type
== 'F')
15547 cur_proc_ptr
->fpreg_mask
= mask
;
15548 cur_proc_ptr
->fpreg_offset
= off
;
15552 cur_proc_ptr
->reg_mask
= mask
;
15553 cur_proc_ptr
->reg_offset
= off
;
15556 demand_empty_rest_of_line ();
15559 #endif /* OBJ_ELF */
15560 s_ignore (reg_type
);
15563 /* A table describing all the processors gas knows about. Names are
15564 matched in the order listed.
15566 To ease comparison, please keep this table in the same order as
15567 gcc's mips_cpu_info_table[]. */
15568 static const struct mips_cpu_info mips_cpu_info_table
[] =
15570 /* Entries for generic ISAs */
15571 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
15572 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
15573 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
15574 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
15575 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
15576 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15577 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15578 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15579 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15582 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15583 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15584 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15587 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15590 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15591 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15592 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15593 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15594 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15595 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15596 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15597 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15598 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15599 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15600 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15601 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15602 /* ST Microelectronics Loongson 2E and 2F cores */
15603 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15604 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15607 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15608 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15609 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15610 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
15611 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
15612 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15613 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15614 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15615 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15616 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15617 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15618 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15619 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15620 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15621 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15624 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15625 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15626 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15627 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15629 /* MIPS 32 Release 2 */
15630 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15631 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15632 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15633 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15634 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15635 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15636 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15637 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15638 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15639 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15640 /* Deprecated forms of the above. */
15641 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15642 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15643 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15644 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15645 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15646 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15647 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15648 /* Deprecated forms of the above. */
15649 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15650 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15651 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15652 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15653 ISA_MIPS32R2
, CPU_MIPS32R2
},
15654 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15655 ISA_MIPS32R2
, CPU_MIPS32R2
},
15656 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15657 ISA_MIPS32R2
, CPU_MIPS32R2
},
15658 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15659 ISA_MIPS32R2
, CPU_MIPS32R2
},
15660 /* Deprecated forms of the above. */
15661 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15662 ISA_MIPS32R2
, CPU_MIPS32R2
},
15663 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15664 ISA_MIPS32R2
, CPU_MIPS32R2
},
15665 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15666 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15667 ISA_MIPS32R2
, CPU_MIPS32R2
},
15668 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15669 ISA_MIPS32R2
, CPU_MIPS32R2
},
15670 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15671 ISA_MIPS32R2
, CPU_MIPS32R2
},
15672 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15673 ISA_MIPS32R2
, CPU_MIPS32R2
},
15674 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15675 ISA_MIPS32R2
, CPU_MIPS32R2
},
15676 /* Deprecated forms of the above. */
15677 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15678 ISA_MIPS32R2
, CPU_MIPS32R2
},
15679 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15680 ISA_MIPS32R2
, CPU_MIPS32R2
},
15681 /* 1004K cores are multiprocessor versions of the 34K. */
15682 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15683 ISA_MIPS32R2
, CPU_MIPS32R2
},
15684 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15685 ISA_MIPS32R2
, CPU_MIPS32R2
},
15686 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15687 ISA_MIPS32R2
, CPU_MIPS32R2
},
15688 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15689 ISA_MIPS32R2
, CPU_MIPS32R2
},
15692 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15693 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15694 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15695 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15697 /* Broadcom SB-1 CPU core */
15698 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15699 ISA_MIPS64
, CPU_SB1
},
15700 /* Broadcom SB-1A CPU core */
15701 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15702 ISA_MIPS64
, CPU_SB1
},
15704 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
15706 /* MIPS 64 Release 2 */
15708 /* Cavium Networks Octeon CPU core */
15709 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15712 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
15719 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15720 with a final "000" replaced by "k". Ignore case.
15722 Note: this function is shared between GCC and GAS. */
15725 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15727 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15728 given
++, canonical
++;
15730 return ((*given
== 0 && *canonical
== 0)
15731 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15735 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15736 CPU name. We've traditionally allowed a lot of variation here.
15738 Note: this function is shared between GCC and GAS. */
15741 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15743 /* First see if the name matches exactly, or with a final "000"
15744 turned into "k". */
15745 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15748 /* If not, try comparing based on numerical designation alone.
15749 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15750 if (TOLOWER (*given
) == 'r')
15752 if (!ISDIGIT (*given
))
15755 /* Skip over some well-known prefixes in the canonical name,
15756 hoping to find a number there too. */
15757 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15759 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15761 else if (TOLOWER (canonical
[0]) == 'r')
15764 return mips_strict_matching_cpu_name_p (canonical
, given
);
15768 /* Parse an option that takes the name of a processor as its argument.
15769 OPTION is the name of the option and CPU_STRING is the argument.
15770 Return the corresponding processor enumeration if the CPU_STRING is
15771 recognized, otherwise report an error and return null.
15773 A similar function exists in GCC. */
15775 static const struct mips_cpu_info
*
15776 mips_parse_cpu (const char *option
, const char *cpu_string
)
15778 const struct mips_cpu_info
*p
;
15780 /* 'from-abi' selects the most compatible architecture for the given
15781 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15782 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15783 version. Look first at the -mgp options, if given, otherwise base
15784 the choice on MIPS_DEFAULT_64BIT.
15786 Treat NO_ABI like the EABIs. One reason to do this is that the
15787 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15788 architecture. This code picks MIPS I for 'mips' and MIPS III for
15789 'mips64', just as we did in the days before 'from-abi'. */
15790 if (strcasecmp (cpu_string
, "from-abi") == 0)
15792 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15793 return mips_cpu_info_from_isa (ISA_MIPS1
);
15795 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15796 return mips_cpu_info_from_isa (ISA_MIPS3
);
15798 if (file_mips_gp32
>= 0)
15799 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15801 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15806 /* 'default' has traditionally been a no-op. Probably not very useful. */
15807 if (strcasecmp (cpu_string
, "default") == 0)
15810 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15811 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15814 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
15818 /* Return the canonical processor information for ISA (a member of the
15819 ISA_MIPS* enumeration). */
15821 static const struct mips_cpu_info
*
15822 mips_cpu_info_from_isa (int isa
)
15826 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15827 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15828 && isa
== mips_cpu_info_table
[i
].isa
)
15829 return (&mips_cpu_info_table
[i
]);
15834 static const struct mips_cpu_info
*
15835 mips_cpu_info_from_arch (int arch
)
15839 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15840 if (arch
== mips_cpu_info_table
[i
].cpu
)
15841 return (&mips_cpu_info_table
[i
]);
15847 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15851 fprintf (stream
, "%24s", "");
15856 fprintf (stream
, ", ");
15860 if (*col_p
+ strlen (string
) > 72)
15862 fprintf (stream
, "\n%24s", "");
15866 fprintf (stream
, "%s", string
);
15867 *col_p
+= strlen (string
);
15873 md_show_usage (FILE *stream
)
15878 fprintf (stream
, _("\
15880 -EB generate big endian output\n\
15881 -EL generate little endian output\n\
15882 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15883 -G NUM allow referencing objects up to NUM bytes\n\
15884 implicitly with the gp register [default 8]\n"));
15885 fprintf (stream
, _("\
15886 -mips1 generate MIPS ISA I instructions\n\
15887 -mips2 generate MIPS ISA II instructions\n\
15888 -mips3 generate MIPS ISA III instructions\n\
15889 -mips4 generate MIPS ISA IV instructions\n\
15890 -mips5 generate MIPS ISA V instructions\n\
15891 -mips32 generate MIPS32 ISA instructions\n\
15892 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15893 -mips64 generate MIPS64 ISA instructions\n\
15894 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15895 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15899 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15900 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15901 show (stream
, "from-abi", &column
, &first
);
15902 fputc ('\n', stream
);
15904 fprintf (stream
, _("\
15905 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15906 -no-mCPU don't generate code specific to CPU.\n\
15907 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15911 show (stream
, "3900", &column
, &first
);
15912 show (stream
, "4010", &column
, &first
);
15913 show (stream
, "4100", &column
, &first
);
15914 show (stream
, "4650", &column
, &first
);
15915 fputc ('\n', stream
);
15917 fprintf (stream
, _("\
15918 -mips16 generate mips16 instructions\n\
15919 -no-mips16 do not generate mips16 instructions\n"));
15920 fprintf (stream
, _("\
15921 -msmartmips generate smartmips instructions\n\
15922 -mno-smartmips do not generate smartmips instructions\n"));
15923 fprintf (stream
, _("\
15924 -mdsp generate DSP instructions\n\
15925 -mno-dsp do not generate DSP instructions\n"));
15926 fprintf (stream
, _("\
15927 -mdspr2 generate DSP R2 instructions\n\
15928 -mno-dspr2 do not generate DSP R2 instructions\n"));
15929 fprintf (stream
, _("\
15930 -mmt generate MT instructions\n\
15931 -mno-mt do not generate MT instructions\n"));
15932 fprintf (stream
, _("\
15933 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15934 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15935 -mfix-vr4120 work around certain VR4120 errata\n\
15936 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15937 -mfix-24k insert a nop after ERET and DERET instructions\n\
15938 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15939 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15940 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15941 -msym32 assume all symbols have 32-bit values\n\
15942 -O0 remove unneeded NOPs, do not swap branches\n\
15943 -O remove unneeded NOPs and swap branches\n\
15944 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15945 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15946 fprintf (stream
, _("\
15947 -mhard-float allow floating-point instructions\n\
15948 -msoft-float do not allow floating-point instructions\n\
15949 -msingle-float only allow 32-bit floating-point operations\n\
15950 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15951 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15954 fprintf (stream
, _("\
15955 -KPIC, -call_shared generate SVR4 position independent code\n\
15956 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15957 -mvxworks-pic generate VxWorks position independent code\n\
15958 -non_shared do not generate code that can operate with DSOs\n\
15959 -xgot assume a 32 bit GOT\n\
15960 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15961 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15962 position dependent (non shared) code\n\
15963 -mabi=ABI create ABI conformant object file for:\n"));
15967 show (stream
, "32", &column
, &first
);
15968 show (stream
, "o64", &column
, &first
);
15969 show (stream
, "n32", &column
, &first
);
15970 show (stream
, "64", &column
, &first
);
15971 show (stream
, "eabi", &column
, &first
);
15973 fputc ('\n', stream
);
15975 fprintf (stream
, _("\
15976 -32 create o32 ABI object file (default)\n\
15977 -n32 create n32 ABI object file\n\
15978 -64 create 64 ABI object file\n"));
15984 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
15986 if (HAVE_64BIT_SYMBOLS
)
15987 return dwarf2_format_64bit_irix
;
15989 return dwarf2_format_32bit
;
15994 mips_dwarf2_addr_size (void)
15996 if (HAVE_64BIT_OBJECTS
)
16002 /* Standard calling conventions leave the CFA at SP on entry. */
16004 mips_cfi_frame_initial_instructions (void)
16006 cfi_add_CFA_def_cfa_register (SP
);
16010 tc_mips_regname_to_dw2regnum (char *regname
)
16012 unsigned int regnum
= -1;
16015 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))