opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* Intel L1OM support required */
  96   CpuL1OM,
  97   /* Xsave/xrstor New Instructions support required */
  98   CpuXsave,
  99   /* Xsaveopt New Instructions support required */
 100   CpuXsaveopt,
 101   /* AES support required */
 102   CpuAES,
 103   /* PCLMUL support required */
 104   CpuPCLMUL,
 105   /* FMA support required */
 106   CpuFMA,
 107   /* FMA4 support required */
 108   CpuFMA4,
 109   /* XOP support required */
 110   CpuXOP,
 111   /* LWP support required */
 112   CpuLWP,
 113   /* BMI support required */
 114   CpuBMI,
 115   /* TBM support required */
 116   CpuTBM,
 117   /* MOVBE Instruction support required */
 118   CpuMovbe,
 119   /* EPT Instructions required */
 120   CpuEPT,
 121   /* RDTSCP Instruction support required */
 122   CpuRdtscp,
 123   /* FSGSBASE Instructions required */
 124   CpuFSGSBase,
 125   /* RDRND Instructions required */
 126   CpuRdRnd,
 127   /* F16C Instructions required */
 128   CpuF16C,
 129   /* 64bit support available, used by -march= in assembler.  */
 130   CpuLM,
 131   /* 64bit support required  */
 132   Cpu64,
 133   /* Not supported in the 64bit mode  */
 134   CpuNo64,
 135   /* The last bitfield in i386_cpu_flags.  */
 136   CpuMax = CpuNo64
 137 };
 138
 139 #define CpuNumOfUints \
 140   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 141 #define CpuNumOfBits \
 142   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 143
 144 /* If you get a compiler error for zero width of the unused field,
 145    comment it out.  */
 146 #define CpuUnused       (CpuMax + 1)
 147
 148 /* We can check if an instruction is available with array instead
 149    of bitfield. */
 150 typedef union i386_cpu_flags
 151 {
 152   struct
 153     {
 154       unsigned int cpui186:1;
 155       unsigned int cpui286:1;
 156       unsigned int cpui386:1;
 157       unsigned int cpui486:1;
 158       unsigned int cpui586:1;
 159       unsigned int cpui686:1;
 160       unsigned int cpuclflush:1;
 161       unsigned int cpunop:1;
 162       unsigned int cpusyscall:1;
 163       unsigned int cpu8087:1;
 164       unsigned int cpu287:1;
 165       unsigned int cpu387:1;
 166       unsigned int cpu687:1;
 167       unsigned int cpufisttp:1;
 168       unsigned int cpummx:1;
 169       unsigned int cpusse:1;
 170       unsigned int cpusse2:1;
 171       unsigned int cpua3dnow:1;
 172       unsigned int cpua3dnowa:1;
 173       unsigned int cpusse3:1;
 174       unsigned int cpupadlock:1;
 175       unsigned int cpusvme:1;
 176       unsigned int cpuvmx:1;
 177       unsigned int cpusmx:1;
 178       unsigned int cpussse3:1;
 179       unsigned int cpusse4a:1;
 180       unsigned int cpuabm:1;
 181       unsigned int cpusse4_1:1;
 182       unsigned int cpusse4_2:1;
 183       unsigned int cpuavx:1;
 184       unsigned int cpul1om:1;
 185       unsigned int cpuxsave:1;
 186       unsigned int cpuxsaveopt:1;
 187       unsigned int cpuaes:1;
 188       unsigned int cpupclmul:1;
 189       unsigned int cpufma:1;
 190       unsigned int cpufma4:1;
 191       unsigned int cpuxop:1;
 192       unsigned int cpulwp:1;
 193       unsigned int cpubmi:1;
 194       unsigned int cputbm:1;
 195       unsigned int cpumovbe:1;
 196       unsigned int cpuept:1;
 197       unsigned int cpurdtscp:1;
 198       unsigned int cpufsgsbase:1;
 199       unsigned int cpurdrnd:1;
 200       unsigned int cpuf16c:1;
 201       unsigned int cpulm:1;
 202       unsigned int cpu64:1;
 203       unsigned int cpuno64:1;
 204 #ifdef CpuUnused
 205       unsigned int unused:(CpuNumOfBits - CpuUnused);
 206 #endif
 207     } bitfield;
 208   unsigned int array[CpuNumOfUints];
 209 } i386_cpu_flags;
 210
 211 /* Position of opcode_modifier bits.  */
 212
 213 enum
 214 {
 215   /* has direction bit. */
 216   D = 0,
 217   /* set if operands can be words or dwords encoded the canonical way */
 218   W,
 219   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 220      operand in encoding.  */
 221   S,
 222   /* insn has a modrm byte. */
 223   Modrm,
 224   /* register is in low 3 bits of opcode */
 225   ShortForm,
 226   /* special case for jump insns.  */
 227   Jump,
 228   /* call and jump */
 229   JumpDword,
 230   /* loop and jecxz */
 231   JumpByte,
 232   /* special case for intersegment leaps/calls */
 233   JumpInterSegment,
 234   /* FP insn memory format bit, sized by 0x4 */
 235   FloatMF,
 236   /* src/dest swap for floats. */
 237   FloatR,
 238   /* has float insn direction bit. */
 239   FloatD,
 240   /* needs size prefix if in 32-bit mode */
 241   Size16,
 242   /* needs size prefix if in 16-bit mode */
 243   Size32,
 244   /* needs size prefix if in 64-bit mode */
 245   Size64,
 246   /* check register size.  */
 247   CheckRegSize,
 248   /* instruction ignores operand size prefix and in Intel mode ignores
 249      mnemonic size suffix check.  */
 250   IgnoreSize,
 251   /* default insn size depends on mode */
 252   DefaultSize,
 253   /* b suffix on instruction illegal */
 254   No_bSuf,
 255   /* w suffix on instruction illegal */
 256   No_wSuf,
 257   /* l suffix on instruction illegal */
 258   No_lSuf,
 259   /* s suffix on instruction illegal */
 260   No_sSuf,
 261   /* q suffix on instruction illegal */
 262   No_qSuf,
 263   /* long double suffix on instruction illegal */
 264   No_ldSuf,
 265   /* instruction needs FWAIT */
 266   FWait,
 267   /* quick test for string instructions */
 268   IsString,
 269   /* quick test for lockable instructions */
 270   IsLockable,
 271   /* fake an extra reg operand for clr, imul and special register
 272      processing for some instructions.  */
 273   RegKludge,
 274   /* The first operand must be xmm0 */
 275   FirstXmm0,
 276   /* An implicit xmm0 as the first operand */
 277   Implicit1stXmm0,
 278   /* Convert to DWORD */
 279   ToDword,
 280   /* Convert to QWORD */
 281   ToQword,
 282   /* Address prefix changes operand 0 */
 283   AddrPrefixOp0,
 284   /* opcode is a prefix */
 285   IsPrefix,
 286   /* instruction has extension in 8 bit imm */
 287   ImmExt,
 288   /* instruction don't need Rex64 prefix.  */
 289   NoRex64,
 290   /* instruction require Rex64 prefix.  */
 291   Rex64,
 292   /* deprecated fp insn, gets a warning */
 293   Ugh,
 294   /* insn has VEX prefix:
 295         1: 128bit VEX prefix.
 296         2: 256bit VEX prefix.
 297         3: Scalar VEX prefix.
 298    */
 299 #define VEX128          1
 300 #define VEX256          2
 301 #define VEXScalar       3
 302   Vex,
 303   /* How to encode VEX.vvvv:
 304      0: VEX.vvvv must be 1111b.
 305      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 306         the content of source registers will be preserved.
 307         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 308         where the content of first source register will be overwritten
 309         by the result.
 310         For assembler, there are no difference between VEX.NDS and
 311         VEX.DDS.
 312      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
 313      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 314         of the operands can access a memory location.
 315    */
 316 #define VEXXDS  1
 317 #define VEXNDD  2
 318 #define VEXLWP  3
 319   VexVVVV,
 320   /* How the VEX.W bit is used:
 321      0: Set by the REX.W bit.
 322      1: VEX.W0.  Should always be 0.
 323      2: VEX.W1.  Should always be 1.
 324    */
 325 #define VEXW0   1
 326 #define VEXW1   2
 327   VexW,
 328   /* VEX opcode prefix:
 329      0: VEX 0x0F opcode prefix.
 330      1: VEX 0x0F38 opcode prefix.
 331      2: VEX 0x0F3A opcode prefix
 332      3: XOP 0x08 opcode prefix.
 333      4: XOP 0x09 opcode prefix
 334      5: XOP 0x0A opcode prefix.
 335    */
 336 #define VEX0F           0
 337 #define VEX0F38         1
 338 #define VEX0F3A         2
 339 #define XOP08           3
 340 #define XOP09           4
 341 #define XOP0A           5
 342   VexOpcode,
 343   /* number of VEX source operands:
 344      0: <= 2 source operands.
 345      1: 2 XOP source operands.
 346      2: 3 source operands.
 347    */
 348 #define XOP2SOURCES     1
 349 #define VEX3SOURCES     2
 350   VexSources,
 351   /* instruction has VEX 8 bit imm */
 352   VexImmExt,
 353   /* SSE to AVX support required */
 354   SSE2AVX,
 355   /* No AVX equivalent */
 356   NoAVX,
 357   /* Compatible with old (<= 2.8.1) versions of gcc  */
 358   OldGcc,
 359   /* AT&T mnemonic.  */
 360   ATTMnemonic,
 361   /* AT&T syntax.  */
 362   ATTSyntax,
 363   /* Intel syntax.  */
 364   IntelSyntax,
 365   /* The last bitfield in i386_opcode_modifier.  */
 366   Opcode_Modifier_Max
 367 };
 368
 369 typedef struct i386_opcode_modifier
 370 {
 371   unsigned int d:1;
 372   unsigned int w:1;
 373   unsigned int s:1;
 374   unsigned int modrm:1;
 375   unsigned int shortform:1;
 376   unsigned int jump:1;
 377   unsigned int jumpdword:1;
 378   unsigned int jumpbyte:1;
 379   unsigned int jumpintersegment:1;
 380   unsigned int floatmf:1;
 381   unsigned int floatr:1;
 382   unsigned int floatd:1;
 383   unsigned int size16:1;
 384   unsigned int size32:1;
 385   unsigned int size64:1;
 386   unsigned int checkregsize:1;
 387   unsigned int ignoresize:1;
 388   unsigned int defaultsize:1;
 389   unsigned int no_bsuf:1;
 390   unsigned int no_wsuf:1;
 391   unsigned int no_lsuf:1;
 392   unsigned int no_ssuf:1;
 393   unsigned int no_qsuf:1;
 394   unsigned int no_ldsuf:1;
 395   unsigned int fwait:1;
 396   unsigned int isstring:1;
 397   unsigned int islockable:1;
 398   unsigned int regkludge:1;
 399   unsigned int firstxmm0:1;
 400   unsigned int implicit1stxmm0:1;
 401   unsigned int todword:1;
 402   unsigned int toqword:1;
 403   unsigned int addrprefixop0:1;
 404   unsigned int isprefix:1;
 405   unsigned int immext:1;
 406   unsigned int norex64:1;
 407   unsigned int rex64:1;
 408   unsigned int ugh:1;
 409   unsigned int vex:2;
 410   unsigned int vexvvvv:2;
 411   unsigned int vexw:2;
 412   unsigned int vexopcode:3;
 413   unsigned int vexsources:2;
 414   unsigned int veximmext:1;
 415   unsigned int sse2avx:1;
 416   unsigned int noavx:1;
 417   unsigned int oldgcc:1;
 418   unsigned int attmnemonic:1;
 419   unsigned int attsyntax:1;
 420   unsigned int intelsyntax:1;
 421 } i386_opcode_modifier;
 422
 423 /* Position of operand_type bits.  */
 424
 425 enum
 426 {
 427   /* 8bit register */
 428   Reg8 = 0,
 429   /* 16bit register */
 430   Reg16,
 431   /* 32bit register */
 432   Reg32,
 433   /* 64bit register */
 434   Reg64,
 435   /* Floating pointer stack register */
 436   FloatReg,
 437   /* MMX register */
 438   RegMMX,
 439   /* SSE register */
 440   RegXMM,
 441   /* AVX registers */
 442   RegYMM,
 443   /* Control register */
 444   Control,
 445   /* Debug register */
 446   Debug,
 447   /* Test register */
 448   Test,
 449   /* 2 bit segment register */
 450   SReg2,
 451   /* 3 bit segment register */
 452   SReg3,
 453   /* 1 bit immediate */
 454   Imm1,
 455   /* 8 bit immediate */
 456   Imm8,
 457   /* 8 bit immediate sign extended */
 458   Imm8S,
 459   /* 16 bit immediate */
 460   Imm16,
 461   /* 32 bit immediate */
 462   Imm32,
 463   /* 32 bit immediate sign extended */
 464   Imm32S,
 465   /* 64 bit immediate */
 466   Imm64,
 467   /* 8bit/16bit/32bit displacements are used in different ways,
 468      depending on the instruction.  For jumps, they specify the
 469      size of the PC relative displacement, for instructions with
 470      memory operand, they specify the size of the offset relative
 471      to the base register, and for instructions with memory offset
 472      such as `mov 1234,%al' they specify the size of the offset
 473      relative to the segment base.  */
 474   /* 8 bit displacement */
 475   Disp8,
 476   /* 16 bit displacement */
 477   Disp16,
 478   /* 32 bit displacement */
 479   Disp32,
 480   /* 32 bit signed displacement */
 481   Disp32S,
 482   /* 64 bit displacement */
 483   Disp64,
 484   /* Accumulator %al/%ax/%eax/%rax */
 485   Acc,
 486   /* Floating pointer top stack register %st(0) */
 487   FloatAcc,
 488   /* Register which can be used for base or index in memory operand.  */
 489   BaseIndex,
 490   /* Register to hold in/out port addr = dx */
 491   InOutPortReg,
 492   /* Register to hold shift count = cl */
 493   ShiftCount,
 494   /* Absolute address for jump.  */
 495   JumpAbsolute,
 496   /* String insn operand with fixed es segment */
 497   EsSeg,
 498   /* RegMem is for instructions with a modrm byte where the register
 499      destination operand should be encoded in the mod and regmem fields.
 500      Normally, it will be encoded in the reg field. We add a RegMem
 501      flag to the destination register operand to indicate that it should
 502      be encoded in the regmem field.  */
 503   RegMem,
 504   /* Memory.  */
 505   Mem,
 506   /* BYTE memory. */
 507   Byte,
 508   /* WORD memory. 2 byte */
 509   Word,
 510   /* DWORD memory. 4 byte */
 511   Dword,
 512   /* FWORD memory. 6 byte */
 513   Fword,
 514   /* QWORD memory. 8 byte */
 515   Qword,
 516   /* TBYTE memory. 10 byte */
 517   Tbyte,
 518   /* XMMWORD memory. */
 519   Xmmword,
 520   /* YMMWORD memory. */
 521   Ymmword,
 522   /* Unspecified memory size.  */
 523   Unspecified,
 524   /* Any memory size.  */
 525   Anysize,
 526
 527   /* Vector 4 bit immediate.  */
 528   Vec_Imm4,
 529
 530   /* The last bitfield in i386_operand_type.  */
 531   OTMax
 532 };
 533
 534 #define OTNumOfUints \
 535   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 536 #define OTNumOfBits \
 537   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 538
 539 /* If you get a compiler error for zero width of the unused field,
 540    comment it out.  */
 541 #define OTUnused                (OTMax + 1)
 542
 543 typedef union i386_operand_type
 544 {
 545   struct
 546     {
 547       unsigned int reg8:1;
 548       unsigned int reg16:1;
 549       unsigned int reg32:1;
 550       unsigned int reg64:1;
 551       unsigned int floatreg:1;
 552       unsigned int regmmx:1;
 553       unsigned int regxmm:1;
 554       unsigned int regymm:1;
 555       unsigned int control:1;
 556       unsigned int debug:1;
 557       unsigned int test:1;
 558       unsigned int sreg2:1;
 559       unsigned int sreg3:1;
 560       unsigned int imm1:1;
 561       unsigned int imm8:1;
 562       unsigned int imm8s:1;
 563       unsigned int imm16:1;
 564       unsigned int imm32:1;
 565       unsigned int imm32s:1;
 566       unsigned int imm64:1;
 567       unsigned int disp8:1;
 568       unsigned int disp16:1;
 569       unsigned int disp32:1;
 570       unsigned int disp32s:1;
 571       unsigned int disp64:1;
 572       unsigned int acc:1;
 573       unsigned int floatacc:1;
 574       unsigned int baseindex:1;
 575       unsigned int inoutportreg:1;
 576       unsigned int shiftcount:1;
 577       unsigned int jumpabsolute:1;
 578       unsigned int esseg:1;
 579       unsigned int regmem:1;
 580       unsigned int mem:1;
 581       unsigned int byte:1;
 582       unsigned int word:1;
 583       unsigned int dword:1;
 584       unsigned int fword:1;
 585       unsigned int qword:1;
 586       unsigned int tbyte:1;
 587       unsigned int xmmword:1;
 588       unsigned int ymmword:1;
 589       unsigned int unspecified:1;
 590       unsigned int anysize:1;
 591       unsigned int vec_imm4:1;
 592 #ifdef OTUnused
 593       unsigned int unused:(OTNumOfBits - OTUnused);
 594 #endif
 595     } bitfield;
 596   unsigned int array[OTNumOfUints];
 597 } i386_operand_type;
 598
 599 typedef struct insn_template
 600 {
 601   /* instruction name sans width suffix ("mov" for movl insns) */
 602   char *name;
 603
 604   /* how many operands */
 605   unsigned int operands;
 606
 607   /* base_opcode is the fundamental opcode byte without optional
 608      prefix(es).  */
 609   unsigned int base_opcode;
 610 #define Opcode_D        0x2 /* Direction bit:
 611                                set if Reg --> Regmem;
 612                                unset if Regmem --> Reg. */
 613 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 614 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 615
 616   /* extension_opcode is the 3 bit extension for group <n> insns.
 617      This field is also used to store the 8-bit opcode suffix for the
 618      AMD 3DNow! instructions.
 619      If this template has no extension opcode (the usual case) use None
 620      Instructions */
 621   unsigned int extension_opcode;
 622 #define None 0xffff             /* If no extension_opcode is possible.  */
 623
 624   /* Opcode length.  */
 625   unsigned char opcode_length;
 626
 627   /* cpu feature flags */
 628   i386_cpu_flags cpu_flags;
 629
 630   /* the bits in opcode_modifier are used to generate the final opcode from
 631      the base_opcode.  These bits also are used to detect alternate forms of
 632      the same instruction */
 633   i386_opcode_modifier opcode_modifier;
 634
 635   /* operand_types[i] describes the type of operand i.  This is made
 636      by OR'ing together all of the possible type masks.  (e.g.
 637      'operand_types[i] = Reg|Imm' specifies that operand i can be
 638      either a register or an immediate operand.  */
 639   i386_operand_type operand_types[MAX_OPERANDS];
 640 }
 641 insn_template;
 642
 643 extern const insn_template i386_optab[];
 644
 645 /* these are for register name --> number & type hash lookup */
 646 typedef struct
 647 {
 648   char *reg_name;
 649   i386_operand_type reg_type;
 650   unsigned char reg_flags;
 651 #define RegRex      0x1  /* Extended register.  */
 652 #define RegRex64    0x2  /* Extended 8 bit register.  */
 653   unsigned char reg_num;
 654 #define RegRip  ((unsigned char ) ~0)
 655 #define RegEip  (RegRip - 1)
 656 /* EIZ and RIZ are fake index registers.  */
 657 #define RegEiz  (RegEip - 1)
 658 #define RegRiz  (RegEiz - 1)
 659 /* FLAT is a fake segment register (Intel mode).  */
 660 #define RegFlat     ((unsigned char) ~0)
 661   signed char dw2_regnum[2];
 662 #define Dw2Inval (-1)
 663 }
 664 reg_entry;
 665
 666 /* Entries in i386_regtab.  */
 667 #define REGNAM_AL 1
 668 #define REGNAM_AX 25
 669 #define REGNAM_EAX 41
 670
 671 extern const reg_entry i386_regtab[];
 672 extern const unsigned int i386_regtab_size;
 673
 674 typedef struct
 675 {
 676   char *seg_name;
 677   unsigned int seg_prefix;
 678 }
 679 seg_entry;
 680
 681 extern const seg_entry cs;
 682 extern const seg_entry ds;
 683 extern const seg_entry ss;
 684 extern const seg_entry es;
 685 extern const seg_entry fs;
 686 extern const seg_entry gs;