opcodes/openrisc-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
   8
   9 This file is part of the GNU Binutils and GDB, the GNU debugger.
  10
  11 This program is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 2, or (at your option)
  14 any later version.
  15
  16 This program is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with this program; if not, write to the Free Software Foundation, Inc.,
  23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  24
  25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  26    Keep that in mind.  */
  27
  28 #include "sysdep.h"
  29 #include <stdio.h>
  30 #include "ansidecl.h"
  31 #include "dis-asm.h"
  32 #include "bfd.h"
  33 #include "symcat.h"
  34 #include "openrisc-desc.h"
  35 #include "openrisc-opc.h"
  36 #include "opintl.h"
  37
  38 /* Default text to print if an instruction isn't recognized.  */
  39 #define UNKNOWN_INSN_MSG _("*unknown*")
  40
  41 static void print_normal
  42      PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
  43 static void print_address
  44      PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
  45 static void print_keyword
  46      PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
  47 static void print_insn_normal
  48      PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
  49               bfd_vma, int));
  50 static int print_insn
  51      PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
  52 static int default_print_insn
  53      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  54 static int read_insn
  55      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
  56               CGEN_EXTRACT_INFO *, unsigned long *));
  57 \f
  58 /* -- disassembler routines inserted here */
  59
  60
  61 void openrisc_cgen_print_operand
  62   PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
  63            void const *, bfd_vma, int));
  64
  65 /* Main entry point for printing operands.
  66    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
  67    of dis-asm.h on cgen.h.
  68
  69    This function is basically just a big switch statement.  Earlier versions
  70    used tables to look up the function to use, but
  71    - if the table contains both assembler and disassembler functions then
  72      the disassembler contains much of the assembler and vice-versa,
  73    - there's a lot of inlining possibilities as things grow,
  74    - using a switch statement avoids the function call overhead.
  75
  76    This function could be moved into `print_insn_normal', but keeping it
  77    separate makes clear the interface between `print_insn_normal' and each of
  78    the handlers.  */
  79
  80 void
  81 openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
  82      CGEN_CPU_DESC cd;
  83      int opindex;
  84      PTR xinfo;
  85      CGEN_FIELDS *fields;
  86      void const *attrs ATTRIBUTE_UNUSED;
  87      bfd_vma pc;
  88      int length;
  89 {
  90  disassemble_info *info = (disassemble_info *) xinfo;
  91
  92   switch (opindex)
  93     {
  94     case OPENRISC_OPERAND_ABS_26 :
  95       print_address (cd, info, fields->f_abs26, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
  96       break;
  97     case OPENRISC_OPERAND_DISP_26 :
  98       print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
  99       break;
 100     case OPENRISC_OPERAND_HI16 :
 101       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 102       break;
 103     case OPENRISC_OPERAND_LO16 :
 104       print_normal (cd, info, fields->f_lo16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 105       break;
 106     case OPENRISC_OPERAND_OP_F_23 :
 107       print_normal (cd, info, fields->f_op4, 0, pc, length);
 108       break;
 109     case OPENRISC_OPERAND_OP_F_3 :
 110       print_normal (cd, info, fields->f_op5, 0, pc, length);
 111       break;
 112     case OPENRISC_OPERAND_RA :
 113       print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0);
 114       break;
 115     case OPENRISC_OPERAND_RB :
 116       print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0);
 117       break;
 118     case OPENRISC_OPERAND_RD :
 119       print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0);
 120       break;
 121     case OPENRISC_OPERAND_SIMM_16 :
 122       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 123       break;
 124     case OPENRISC_OPERAND_UI16NC :
 125       print_normal (cd, info, fields->f_i16nc, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 126       break;
 127     case OPENRISC_OPERAND_UIMM_16 :
 128       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
 129       break;
 130     case OPENRISC_OPERAND_UIMM_5 :
 131       print_normal (cd, info, fields->f_uimm5, 0, pc, length);
 132       break;
 133
 134     default :
 135       /* xgettext:c-format */
 136       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 137                opindex);
 138     abort ();
 139   }
 140 }
 141
 142 cgen_print_fn * const openrisc_cgen_print_handlers[] =
 143 {
 144   print_insn_normal,
 145 };
 146
 147
 148 void
 149 openrisc_cgen_init_dis (cd)
 150      CGEN_CPU_DESC cd;
 151 {
 152   openrisc_cgen_init_opcode_table (cd);
 153   openrisc_cgen_init_ibld_table (cd);
 154   cd->print_handlers = & openrisc_cgen_print_handlers[0];
 155   cd->print_operand = openrisc_cgen_print_operand;
 156 }
 157
 158 \f
 159 /* Default print handler.  */
 160
 161 static void
 162 print_normal (cd, dis_info, value, attrs, pc, length)
 163      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 164      PTR dis_info;
 165      long value;
 166      unsigned int attrs;
 167      bfd_vma pc ATTRIBUTE_UNUSED;
 168      int length ATTRIBUTE_UNUSED;
 169 {
 170   disassemble_info *info = (disassemble_info *) dis_info;
 171
 172 #ifdef CGEN_PRINT_NORMAL
 173   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 174 #endif
 175
 176   /* Print the operand as directed by the attributes.  */
 177   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 178     ; /* nothing to do */
 179   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 180     (*info->fprintf_func) (info->stream, "%ld", value);
 181   else
 182     (*info->fprintf_func) (info->stream, "0x%lx", value);
 183 }
 184
 185 /* Default address handler.  */
 186
 187 static void
 188 print_address (cd, dis_info, value, attrs, pc, length)
 189      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 190      PTR dis_info;
 191      bfd_vma value;
 192      unsigned int attrs;
 193      bfd_vma pc ATTRIBUTE_UNUSED;
 194      int length ATTRIBUTE_UNUSED;
 195 {
 196   disassemble_info *info = (disassemble_info *) dis_info;
 197
 198 #ifdef CGEN_PRINT_ADDRESS
 199   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 200 #endif
 201
 202   /* Print the operand as directed by the attributes.  */
 203   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 204     ; /* nothing to do */
 205   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 206     (*info->print_address_func) (value, info);
 207   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 208     (*info->print_address_func) (value, info);
 209   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 210     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 211   else
 212     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 213 }
 214
 215 /* Keyword print handler.  */
 216
 217 static void
 218 print_keyword (cd, dis_info, keyword_table, value, attrs)
 219      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 220      PTR dis_info;
 221      CGEN_KEYWORD *keyword_table;
 222      long value;
 223      unsigned int attrs ATTRIBUTE_UNUSED;
 224 {
 225   disassemble_info *info = (disassemble_info *) dis_info;
 226   const CGEN_KEYWORD_ENTRY *ke;
 227
 228   ke = cgen_keyword_lookup_value (keyword_table, value);
 229   if (ke != NULL)
 230     (*info->fprintf_func) (info->stream, "%s", ke->name);
 231   else
 232     (*info->fprintf_func) (info->stream, "???");
 233 }
 234 \f
 235 /* Default insn printer.
 236
 237    DIS_INFO is defined as `PTR' so the disassembler needn't know anything
 238    about disassemble_info.  */
 239
 240 static void
 241 print_insn_normal (cd, dis_info, insn, fields, pc, length)
 242      CGEN_CPU_DESC cd;
 243      PTR dis_info;
 244      const CGEN_INSN *insn;
 245      CGEN_FIELDS *fields;
 246      bfd_vma pc;
 247      int length;
 248 {
 249   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 250   disassemble_info *info = (disassemble_info *) dis_info;
 251   const CGEN_SYNTAX_CHAR_TYPE *syn;
 252
 253   CGEN_INIT_PRINT (cd);
 254
 255   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 256     {
 257       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 258         {
 259           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 260           continue;
 261         }
 262       if (CGEN_SYNTAX_CHAR_P (*syn))
 263         {
 264           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 265           continue;
 266         }
 267
 268       /* We have an operand.  */
 269       openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 270                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 271     }
 272 }
 273 \f
 274 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 275    the extract info.
 276    Returns 0 if all is well, non-zero otherwise.  */
 277
 278 static int
 279 read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
 280      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 281      bfd_vma pc;
 282      disassemble_info *info;
 283      char *buf;
 284      int buflen;
 285      CGEN_EXTRACT_INFO *ex_info;
 286      unsigned long *insn_value;
 287 {
 288   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 289   if (status != 0)
 290     {
 291       (*info->memory_error_func) (status, pc, info);
 292       return -1;
 293     }
 294
 295   ex_info->dis_info = info;
 296   ex_info->valid = (1 << buflen) - 1;
 297   ex_info->insn_bytes = buf;
 298
 299   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 300   return 0;
 301 }
 302
 303 /* Utility to print an insn.
 304    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 305    The result is the size of the insn in bytes or zero for an unknown insn
 306    or -1 if an error occurs fetching data (memory_error_func will have
 307    been called).  */
 308
 309 static int
 310 print_insn (cd, pc, info, buf, buflen)
 311      CGEN_CPU_DESC cd;
 312      bfd_vma pc;
 313      disassemble_info *info;
 314      char *buf;
 315      unsigned int buflen;
 316 {
 317   CGEN_INSN_INT insn_value;
 318   const CGEN_INSN_LIST *insn_list;
 319   CGEN_EXTRACT_INFO ex_info;
 320   int basesize;
 321
 322   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 323   basesize = cd->base_insn_bitsize < buflen * 8 ?
 324                                      cd->base_insn_bitsize : buflen * 8;
 325   insn_value = cgen_get_insn_value (cd, buf, basesize);
 326
 327
 328   /* Fill in ex_info fields like read_insn would.  Don't actually call
 329      read_insn, since the incoming buffer is already read (and possibly
 330      modified a la m32r).  */
 331   ex_info.valid = (1 << buflen) - 1;
 332   ex_info.dis_info = info;
 333   ex_info.insn_bytes = buf;
 334
 335   /* The instructions are stored in hash lists.
 336      Pick the first one and keep trying until we find the right one.  */
 337
 338   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 339   while (insn_list != NULL)
 340     {
 341       const CGEN_INSN *insn = insn_list->insn;
 342       CGEN_FIELDS fields;
 343       int length;
 344       unsigned long insn_value_cropped;
 345
 346 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 347       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 348       /* Supported by this cpu?  */
 349       if (! openrisc_cgen_insn_supported (cd, insn))
 350         {
 351           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 352           continue;
 353         }
 354 #endif
 355
 356       /* Basic bit mask must be correct.  */
 357       /* ??? May wish to allow target to defer this check until the extract
 358          handler.  */
 359
 360       /* Base size may exceed this instruction's size.  Extract the
 361          relevant part from the buffer. */
 362       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 363           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 364         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 365                                            info->endian == BFD_ENDIAN_BIG);
 366       else
 367         insn_value_cropped = insn_value;
 368
 369       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 370           == CGEN_INSN_BASE_VALUE (insn))
 371         {
 372           /* Printing is handled in two passes.  The first pass parses the
 373              machine insn and extracts the fields.  The second pass prints
 374              them.  */
 375
 376           /* Make sure the entire insn is loaded into insn_value, if it
 377              can fit.  */
 378           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 379               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 380             {
 381               unsigned long full_insn_value;
 382               int rc = read_insn (cd, pc, info, buf,
 383                                   CGEN_INSN_BITSIZE (insn) / 8,
 384                                   & ex_info, & full_insn_value);
 385               if (rc != 0)
 386                 return rc;
 387               length = CGEN_EXTRACT_FN (cd, insn)
 388                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 389             }
 390           else
 391             length = CGEN_EXTRACT_FN (cd, insn)
 392               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 393
 394           /* length < 0 -> error */
 395           if (length < 0)
 396             return length;
 397           if (length > 0)
 398             {
 399               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 400               /* length is in bits, result is in bytes */
 401               return length / 8;
 402             }
 403         }
 404
 405       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 406     }
 407
 408   return 0;
 409 }
 410
 411 /* Default value for CGEN_PRINT_INSN.
 412    The result is the size of the insn in bytes or zero for an unknown insn
 413    or -1 if an error occured fetching bytes.  */
 414
 415 #ifndef CGEN_PRINT_INSN
 416 #define CGEN_PRINT_INSN default_print_insn
 417 #endif
 418
 419 static int
 420 default_print_insn (cd, pc, info)
 421      CGEN_CPU_DESC cd;
 422      bfd_vma pc;
 423      disassemble_info *info;
 424 {
 425   char buf[CGEN_MAX_INSN_SIZE];
 426   int buflen;
 427   int status;
 428
 429   /* Attempt to read the base part of the insn.  */
 430   buflen = cd->base_insn_bitsize / 8;
 431   status = (*info->read_memory_func) (pc, buf, buflen, info);
 432
 433   /* Try again with the minimum part, if min < base.  */
 434   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 435     {
 436       buflen = cd->min_insn_bitsize / 8;
 437       status = (*info->read_memory_func) (pc, buf, buflen, info);
 438     }
 439
 440   if (status != 0)
 441     {
 442       (*info->memory_error_func) (status, pc, info);
 443       return -1;
 444     }
 445
 446   return print_insn (cd, pc, info, buf, buflen);
 447 }
 448
 449 /* Main entry point.
 450    Print one instruction from PC on INFO->STREAM.
 451    Return the size of the instruction (in bytes).  */
 452
 453 typedef struct cpu_desc_list {
 454   struct cpu_desc_list *next;
 455   int isa;
 456   int mach;
 457   int endian;
 458   CGEN_CPU_DESC cd;
 459 } cpu_desc_list;
 460
 461 int
 462 print_insn_openrisc (pc, info)
 463      bfd_vma pc;
 464      disassemble_info *info;
 465 {
 466   static cpu_desc_list *cd_list = 0;
 467   cpu_desc_list *cl = 0;
 468   static CGEN_CPU_DESC cd = 0;
 469   static int prev_isa;
 470   static int prev_mach;
 471   static int prev_endian;
 472   int length;
 473   int isa,mach;
 474   int endian = (info->endian == BFD_ENDIAN_BIG
 475                 ? CGEN_ENDIAN_BIG
 476                 : CGEN_ENDIAN_LITTLE);
 477   enum bfd_architecture arch;
 478
 479   /* ??? gdb will set mach but leave the architecture as "unknown" */
 480 #ifndef CGEN_BFD_ARCH
 481 #define CGEN_BFD_ARCH bfd_arch_openrisc
 482 #endif
 483   arch = info->arch;
 484   if (arch == bfd_arch_unknown)
 485     arch = CGEN_BFD_ARCH;
 486
 487   /* There's no standard way to compute the machine or isa number
 488      so we leave it to the target.  */
 489 #ifdef CGEN_COMPUTE_MACH
 490   mach = CGEN_COMPUTE_MACH (info);
 491 #else
 492   mach = info->mach;
 493 #endif
 494
 495 #ifdef CGEN_COMPUTE_ISA
 496   isa = CGEN_COMPUTE_ISA (info);
 497 #else
 498   isa = info->insn_sets;
 499 #endif
 500
 501   /* If we've switched cpu's, try to find a handle we've used before */
 502   if (cd
 503       && (isa != prev_isa
 504           || mach != prev_mach
 505           || endian != prev_endian))
 506     {
 507       cd = 0;
 508       for (cl = cd_list; cl; cl = cl->next)
 509         {
 510           if (cl->isa == isa &&
 511               cl->mach == mach &&
 512               cl->endian == endian)
 513             {
 514               cd = cl->cd;
 515               break;
 516             }
 517         }
 518     }
 519
 520   /* If we haven't initialized yet, initialize the opcode table.  */
 521   if (! cd)
 522     {
 523       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 524       const char *mach_name;
 525
 526       if (!arch_type)
 527         abort ();
 528       mach_name = arch_type->printable_name;
 529
 530       prev_isa = isa;
 531       prev_mach = mach;
 532       prev_endian = endian;
 533       cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 534                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 535                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 536                                  CGEN_CPU_OPEN_END);
 537       if (!cd)
 538         abort ();
 539
 540       /* save this away for future reference */
 541       cl = xmalloc (sizeof (struct cpu_desc_list));
 542       cl->cd = cd;
 543       cl->isa = isa;
 544       cl->mach = mach;
 545       cl->endian = endian;
 546       cl->next = cd_list;
 547       cd_list = cl;
 548
 549       openrisc_cgen_init_dis (cd);
 550     }
 551
 552   /* We try to have as much common code as possible.
 553      But at this point some targets need to take over.  */
 554   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 555      but if not possible try to move this hook elsewhere rather than
 556      have two hooks.  */
 557   length = CGEN_PRINT_INSN (cd, pc, info);
 558   if (length > 0)
 559     return length;
 560   if (length < 0)
 561     return -1;
 562
 563   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 564   return cd->default_insn_bitsize / 8;
 565 }