1 2004-07-09 Andreas Schwab <schwab@suse.de>
3 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
5 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
7 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
8 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
9 (crx-dis.lo): New target.
10 (crx-opc.lo): Likewise.
11 * Makefile.in: Regenerate.
12 * configure.in: Handle bfd_crx_arch.
13 * configure: Regenerate.
14 * crx-dis.c: New file.
15 * crx-opc.c: New file.
16 * disassemble.c (ARCH_crx): Define.
17 (disassembler): Handle ARCH_crx.
19 2004-06-29 James E Wilson <wilson@specifixinc.com>
21 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
22 * ia64-asmtab.c: Regnerate.
24 2004-06-28 Alan Modra <amodra@bigpond.net.au>
26 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
27 (extract_fxm): Don't test dialect.
28 (XFXFXM_MASK): Include the power4 bit.
30 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
32 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
34 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
35 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
37 2004-06-26 Alan Modra <amodra@bigpond.net.au>
39 * ppc-opc.c (BH, XLBH_MASK): Define.
40 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
42 2004-06-24 Alan Modra <amodra@bigpond.net.au>
44 * i386-dis.c (x_mode): Comment.
45 (two_source_ops): File scope.
46 (float_mem): Correct fisttpll and fistpll.
47 (float_mem_mode): New table.
49 (OP_E): Correct intel mode PTR output.
50 (ptr_reg): Use open_char and close_char.
51 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
52 operands. Set two_source_ops.
54 2004-06-15 Alan Modra <amodra@bigpond.net.au>
56 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
59 2004-06-08 Jakub Jelinek <jakub@redhat.com>
61 * ia64-gen.c (in_iclass): Handle more postinc st
63 * ia64-asmtab.c: Rebuilt.
65 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
67 * s390-opc.txt: Correct architecture mask for some opcodes.
68 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
69 in the esa mode as well.
71 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
73 * sh-dis.c (target_arch): Make unsigned.
74 (print_insn_sh): Replace (most of) switch with a call to
75 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
76 * sh-opc.h: Redefine architecture flags values.
77 Add sh3-nommu architecture.
78 Reorganise <arch>_up macros so they make more visual sense.
79 (SH_MERGE_ARCH_SET): Define new macro.
80 (SH_VALID_BASE_ARCH_SET): Likewise.
81 (SH_VALID_MMU_ARCH_SET): Likewise.
82 (SH_VALID_CO_ARCH_SET): Likewise.
83 (SH_VALID_ARCH_SET): Likewise.
84 (SH_MERGE_ARCH_SET_VALID): Likewise.
85 (SH_ARCH_SET_HAS_FPU): Likewise.
86 (SH_ARCH_SET_HAS_DSP): Likewise.
87 (SH_ARCH_UNKNOWN_ARCH): Likewise.
88 (sh_get_arch_from_bfd_mach): Add prototype.
89 (sh_get_arch_up_from_bfd_mach): Likewise.
90 (sh_get_bfd_mach_from_arch_set): Likewise.
91 (sh_merge_bfd_arc): Likewise.
93 2004-05-24 Peter Barada <peter@the-baradas.com>
95 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
96 into new match_insn_m68k function. Loop over canidate
97 matches and select first that completely matches.
98 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
99 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
100 to verify addressing for MAC/EMAC.
101 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
102 reigster halves since 'fpu' and 'spl' look misleading.
103 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
104 * m68k-opc.c: Rearragne mac/emac cases to use longest for
105 first, tighten up match masks.
106 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
107 'size' from special case code in print_insn_m68k to
108 determine decode size of insns.
110 2004-05-19 Alan Modra <amodra@bigpond.net.au>
112 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
113 well as when -mpower4.
115 2004-05-13 Nick Clifton <nickc@redhat.com>
117 * po/fr.po: Updated French translation.
119 2004-05-05 Peter Barada <peter@the-baradas.com>
121 * m68k-dis.c(print_insn_m68k): Add new chips, use core
122 variants in arch_mask. Only set m68881/68851 for 68k chips.
123 * m68k-op.c: Switch from ColdFire chips to core variants.
125 2004-05-05 Alan Modra <amodra@bigpond.net.au>
128 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
130 2004-04-29 Ben Elliston <bje@au.ibm.com>
132 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
133 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
135 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
137 * sh-dis.c (print_insn_sh): Print the value in constant pool
138 as a symbol if it looks like a symbol.
140 2004-04-22 Peter Barada <peter@the-baradas.com>
142 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
143 appropriate ColdFire architectures.
144 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
146 Add EMAC instructions, fix MAC instructions. Remove
147 macmw/macml/msacmw/msacml instructions since mask addressing now
150 2004-04-20 Jakub Jelinek <jakub@redhat.com>
152 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
153 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
154 suffix. Use fmov*x macros, create all 3 fpsize variants in one
155 macro. Adjust all users.
157 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
159 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
162 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
164 * m32r-asm.c: Regenerate.
166 2004-03-29 Stan Shebs <shebs@apple.com>
168 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
171 2004-03-19 Alan Modra <amodra@bigpond.net.au>
173 * aclocal.m4: Regenerate.
174 * config.in: Regenerate.
175 * configure: Regenerate.
176 * po/POTFILES.in: Regenerate.
177 * po/opcodes.pot: Regenerate.
179 2004-03-16 Alan Modra <amodra@bigpond.net.au>
181 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
183 * ppc-opc.c (RA0): Define.
184 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
185 (RAOPT): Rename from RAO. Update all uses.
186 (powerpc_opcodes): Use RA0 as appropriate.
188 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
190 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
192 2004-03-15 Alan Modra <amodra@bigpond.net.au>
194 * sparc-dis.c (print_insn_sparc): Update getword prototype.
196 2004-03-12 Michal Ludvig <mludvig@suse.cz>
198 * i386-dis.c (GRPPLOCK): Delete.
199 (grps): Delete GRPPLOCK entry.
201 2004-03-12 Alan Modra <amodra@bigpond.net.au>
203 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
205 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
207 (dis386): Use NOP_Fixup on "nop".
208 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
209 (twobyte_has_modrm): Set for 0xa7.
210 (padlock_table): Delete. Move to..
211 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
213 (print_insn): Revert PADLOCK_SPECIAL code.
214 (OP_E): Delete sfence, lfence, mfence checks.
216 2004-03-12 Jakub Jelinek <jakub@redhat.com>
218 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
219 (INVLPG_Fixup): New function.
220 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
222 2004-03-12 Michal Ludvig <mludvig@suse.cz>
224 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
225 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
226 (padlock_table): New struct with PadLock instructions.
227 (print_insn): Handle PADLOCK_SPECIAL.
229 2004-03-12 Alan Modra <amodra@bigpond.net.au>
231 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
232 (OP_E): Twiddle clflush to sfence here.
234 2004-03-08 Nick Clifton <nickc@redhat.com>
236 * po/de.po: Updated German translation.
238 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
240 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
241 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
242 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
245 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
247 * frv-asm.c: Regenerate.
248 * frv-desc.c: Regenerate.
249 * frv-desc.h: Regenerate.
250 * frv-dis.c: Regenerate.
251 * frv-ibld.c: Regenerate.
252 * frv-opc.c: Regenerate.
253 * frv-opc.h: Regenerate.
255 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
257 * frv-desc.c, frv-opc.c: Regenerate.
259 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
261 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
263 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
265 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
266 Also correct mistake in the comment.
268 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
270 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
271 ensure that double registers have even numbers.
272 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
273 that reserved instruction 0xfffd does not decode the same
275 * sh-opc.h: Add REG_N_D nibble type and use it whereever
276 REG_N refers to a double register.
277 Add REG_N_B01 nibble type and use it instead of REG_NM
279 Adjust the bit patterns in a few comments.
281 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
283 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
285 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
287 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
289 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
291 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
293 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
295 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
296 mtivor32, mtivor33, mtivor34.
298 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
300 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
302 2004-02-10 Petko Manolov <petkan@nucleusys.com>
304 * arm-opc.h Maverick accumulator register opcode fixes.
306 2004-02-13 Ben Elliston <bje@wasabisystems.com>
308 * m32r-dis.c: Regenerate.
310 2004-01-27 Michael Snyder <msnyder@redhat.com>
312 * sh-opc.h (sh_table): "fsrra", not "fssra".
314 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
316 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
319 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
321 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
323 2004-01-19 Alan Modra <amodra@bigpond.net.au>
325 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
326 1. Don't print scale factor on AT&T mode when index missing.
328 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
330 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
331 when loaded into XR registers.
333 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
335 * frv-desc.h: Regenerate.
336 * frv-desc.c: Regenerate.
337 * frv-opc.c: Regenerate.
339 2004-01-13 Michael Snyder <msnyder@redhat.com>
341 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
343 2004-01-09 Paul Brook <paul@codesourcery.com>
345 * arm-opc.h (arm_opcodes): Move generic mcrr after known
348 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
350 * Makefile.am (libopcodes_la_DEPENDENCIES)
351 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
352 comment about the problem.
353 * Makefile.in: Regenerate.
355 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
357 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
358 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
359 cut&paste errors in shifting/truncating numerical operands.
360 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
361 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
362 (parse_uslo16): Likewise.
363 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
364 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
365 (parse_s12): Likewise.
366 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
367 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
368 (parse_uslo16): Likewise.
369 (parse_uhi16): Parse gothi and gotfuncdeschi.
370 (parse_d12): Parse got12 and gotfuncdesc12.
371 (parse_s12): Likewise.
373 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
375 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
376 instruction which looks similar to an 'rla' instruction.
378 For older changes see ChangeLog-0203
384 version-control: never