opcodes/m10300-opc.c

   1 /* Assemble Matsushita MN10300 instructions.
   2    Copyright (C) 1996, 1997 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18 /* This file is formatted at > 80 columns.  Attempting to read it on a
  19    screeen with less than 80 columns will be difficult.  */
  20 #include "ansidecl.h"
  21 #include "opcode/mn10300.h"
  22
  23 \f
  24 const struct mn10300_operand mn10300_operands[] = {
  25 #define UNUSED  0
  26   {0, 0, 0},
  27
  28 /* dn register in the first register operand position.  */
  29 #define DN0      (UNUSED+1)
  30   {2, 0, MN10300_OPERAND_DREG},
  31
  32 /* dn register in the second register operand position.  */
  33 #define DN1      (DN0+1)
  34   {2, 2, MN10300_OPERAND_DREG},
  35
  36 /* dn register in the third register operand position.  */
  37 #define DN2      (DN1+1)
  38   {2, 4, MN10300_OPERAND_DREG},
  39
  40 /* dm register in the first register operand position.  */
  41 #define DM0      (DN2+1)
  42   {2, 0, MN10300_OPERAND_DREG},
  43
  44 /* dm register in the second register operand position.  */
  45 #define DM1      (DM0+1)
  46   {2, 2, MN10300_OPERAND_DREG},
  47
  48 /* dm register in the third register operand position.  */
  49 #define DM2      (DM1+1)
  50   {2, 4, MN10300_OPERAND_DREG},
  51
  52 /* an register in the first register operand position.  */
  53 #define AN0      (DM2+1)
  54   {2, 0, MN10300_OPERAND_AREG},
  55
  56 /* an register in the second register operand position.  */
  57 #define AN1      (AN0+1)
  58   {2, 2, MN10300_OPERAND_AREG},
  59
  60 /* an register in the third register operand position.  */
  61 #define AN2      (AN1+1)
  62   {2, 4, MN10300_OPERAND_AREG},
  63
  64 /* am register in the first register operand position.  */
  65 #define AM0      (AN2+1)
  66   {2, 0, MN10300_OPERAND_AREG},
  67
  68 /* am register in the second register operand position.  */
  69 #define AM1      (AM0+1)
  70   {2, 2, MN10300_OPERAND_AREG},
  71
  72 /* am register in the third register operand position.  */
  73 #define AM2      (AM1+1)
  74   {2, 4, MN10300_OPERAND_AREG},
  75
  76 /* 8 bit unsigned immediate which may promote to a 16bit
  77    unsigned immediate.  */
  78 #define IMM8    (AM2+1)
  79   {8, 0, MN10300_OPERAND_PROMOTE},
  80
  81 /* 16 bit unsigned immediate which may promote to a 32bit
  82    unsigned immediate.  */
  83 #define IMM16    (IMM8+1)
  84   {16, 0, MN10300_OPERAND_PROMOTE},
  85
  86 /* 16 bit pc-relative immediate which may promote to a 16bit
  87    pc-relative immediate.  */
  88 #define IMM16_PCREL    (IMM16+1)
  89   {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
  90
  91 /* 16bit unsigned dispacement in a memory operation which
  92    may promote to a 32bit displacement.  */
  93 #define IMM16_MEM    (IMM16_PCREL+1)
  94   {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
  95
  96 /* 32bit immediate, high 16 bits in the main instruction
  97    word, 16bits in the extension word.
  98
  99    The "bits" field indicates how many bits are in the
 100    main instruction word for MN10300_OPERAND_SPLIT!  */
 101 #define IMM32    (IMM16_MEM+1)
 102   {16, 0, MN10300_OPERAND_SPLIT},
 103
 104 /* 32bit pc-relative offset.  */
 105 #define IMM32_PCREL    (IMM32+1)
 106   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
 107
 108 /* 32bit memory offset.  */
 109 #define IMM32_MEM    (IMM32_PCREL+1)
 110   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
 111
 112 /* 32bit immediate, high 16 bits in the main instruction
 113    word, 16bits in the extension word, low 16bits are left
 114    shifted 8 places.
 115
 116    The "bits" field indicates how many bits are in the
 117    main instruction word for MN10300_OPERAND_SPLIT!  */
 118 #define IMM32_LOWSHIFT8    (IMM32_MEM+1)
 119   {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
 120
 121 /* 32bit immediate, high 24 bits in the main instruction
 122    word, 8 in the extension word.
 123
 124    The "bits" field indicates how many bits are in the
 125    main instruction word for MN10300_OPERAND_SPLIT!  */
 126 #define IMM32_HIGH24    (IMM32_LOWSHIFT8+1)
 127   {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
 128
 129 /* 32bit immediate, high 24 bits in the main instruction
 130    word, 8 in the extension word, low 8 bits are left
 131    shifted 16 places.
 132
 133    The "bits" field indicates how many bits are in the
 134    main instruction word for MN10300_OPERAND_SPLIT!  */
 135 #define IMM32_HIGH24_LOWSHIFT16    (IMM32_HIGH24+1)
 136   {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
 137
 138 /* Stack pointer.  */
 139 #define SP    (IMM32_HIGH24_LOWSHIFT16+1)
 140   {8, 0, MN10300_OPERAND_SP},
 141
 142 /* Processor status word.  */
 143 #define PSW    (SP+1)
 144   {0, 0, MN10300_OPERAND_PSW},
 145
 146 /* MDR register.  */
 147 #define MDR    (PSW+1)
 148   {0, 0, MN10300_OPERAND_MDR},
 149
 150 /* Index register.  */
 151 #define DI (MDR+1)
 152   {2, 2, MN10300_OPERAND_DREG},
 153
 154 /* 8 bit signed displacement, may promote to 16bit signed dispacement.  */
 155 #define SD8    (DI+1)
 156   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 157
 158 /* 16 bit signed displacement, may promote to 32bit dispacement.  */
 159 #define SD16    (SD8+1)
 160   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 161
 162 /* 8 bit signed displacement that can not promote.  */
 163 #define SD8N    (SD16+1)
 164   {8, 0, MN10300_OPERAND_SIGNED},
 165
 166 /* 8 bit pc-relative displacement.  */
 167 #define SD8N_PCREL    (SD8N+1)
 168   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
 169
 170 /* 8 bit signed displacement shifted left 8 bits in the instruction.  */
 171 #define SD8N_SHIFT8    (SD8N_PCREL+1)
 172   {8, 8, MN10300_OPERAND_SIGNED},
 173
 174 /* 8 bit signed immediate which may promote to 16bit signed immediate.  */
 175 #define SIMM8    (SD8N_SHIFT8+1)
 176   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 177
 178 /* 16 bit signed immediate which may promote to 32bit  immediate.  */
 179 #define SIMM16    (SIMM8+1)
 180   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 181
 182 /* Either an open paren or close paren.  */
 183 #define PAREN   (SIMM16+1)
 184   {0, 0, MN10300_OPERAND_PAREN},
 185
 186 /* dn register that appears in the first and second register positions.  */
 187 #define DN01     (PAREN+1)
 188   {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
 189
 190 /* an register that appears in the first and second register positions.  */
 191 #define AN01     (DN01+1)
 192   {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
 193
 194 /* 16bit pc-relative displacement which may promote to 32bit pc-relative
 195    displacement.  */
 196 #define D16_SHIFT (AN01+1)
 197   {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
 198
 199 /* 8 bit immediate found in the extension word.  */
 200 #define IMM8E    (D16_SHIFT+1)
 201   {8, 0, MN10300_OPERAND_EXTENDED},
 202
 203 /* Register list found in the extension word shifted 8 bits left.  */
 204 #define REGSE_SHIFT8    (IMM8E+1)
 205   {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
 206
 207 /* Register list shifted 8 bits left.  */
 208 #define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
 209   {8, 8, MN10300_OPERAND_REG_LIST},
 210
 211 /* Reigster list.  */
 212 #define REGS    (REGS_SHIFT8+1)
 213   {8, 0, MN10300_OPERAND_REG_LIST},
 214
 215
 216 } ;
 217
 218 #define MEM(ADDR) PAREN, ADDR, PAREN
 219 #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
 220 #define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
 221 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
 222 \f
 223 /* The opcode table.
 224
 225    The format of the opcode table is:
 226
 227    NAME         OPCODE          MASK    MATCH_MASK, FORMAT, PROCESSOR   { OPERANDS }
 228
 229    NAME is the name of the instruction.
 230    OPCODE is the instruction opcode.
 231    MASK is the opcode mask; this is used to tell the disassembler
 232      which bits in the actual opcode must match OPCODE.
 233    OPERANDS is the list of operands.
 234
 235    The disassembler reads the table in order and prints the first
 236    instruction which matches, so this table is sorted to put more
 237    specific instructions before more general instructions.  It is also
 238    sorted by major opcode.  */
 239
 240 const struct mn10300_opcode mn10300_opcodes[] = {
 241 { "mov",        0x8000,      0xf000,      0,    FMT_S1, 0,      {SIMM8, DN01}},
 242 { "mov",        0x80,        0xf0,        0x3,  FMT_S0, 0,      {DM1, DN0}},
 243 { "mov",        0xf1e0,      0xfff0,      0,    FMT_D0, 0,      {DM1, AN0}},
 244 { "mov",        0xf1d0,      0xfff0,      0,    FMT_D0, 0,      {AM1, DN0}},
 245 { "mov",        0x9000,      0xf000,      0,    FMT_S1, 0,      {IMM8, AN01}},
 246 { "mov",        0x90,        0xf0,        0x3,  FMT_S0, 0,      {AM1, AN0}},
 247 { "mov",        0x3c,        0xfc,        0,    FMT_S0, 0,      {SP, AN0}},
 248 { "mov",        0xf2f0,      0xfff3,      0,    FMT_D0, 0,      {AM1, SP}},
 249 { "mov",        0xf2e4,      0xfffc,      0,    FMT_D0, 0,      {PSW, DN0}},
 250 { "mov",        0xf2f3,      0xfff3,      0,    FMT_D0, 0,      {DM1, PSW}},
 251 { "mov",        0xf2e0,      0xfffc,      0,    FMT_D0, 0,      {MDR, DN0}},
 252 { "mov",        0xf2f2,      0xfff3,      0,    FMT_D0, 0,      {DM1, MDR}},
 253 { "mov",        0x70,        0xf0,        0,    FMT_S0, 0,      {MEM(AM0), DN1}},
 254 { "mov",        0x5800,      0xfcff,      0,    FMT_S1, 0,      {MEM(SP), DN0}},
 255 { "mov",        0x300000,    0xfc0000,    0,    FMT_S2, 0,      {MEM(IMM16_MEM), DN0}},
 256 { "mov",        0xf000,      0xfff0,      0,    FMT_D0, 0,      {MEM(AM0), AN1}},
 257 { "mov",        0x5c00,      0xfcff,      0,    FMT_S1, 0,      {MEM(SP), AN0}},
 258 { "mov",        0xfaa00000,  0xfffc0000,  0,    FMT_D2, 0,      {MEM(IMM16_MEM), AN0}},
 259 { "mov",        0x60,        0xf0,        0,    FMT_S0, 0,      {DM1, MEM(AN0)}},
 260 { "mov",        0x4200,      0xf3ff,      0,    FMT_S1, 0,      {DM1, MEM(SP)}},
 261 { "mov",        0x010000,    0xf30000,    0,    FMT_S2, 0,      {DM1, MEM(IMM16_MEM)}},
 262 { "mov",        0xf010,      0xfff0,      0,    FMT_D0, 0,      {AM1, MEM(AN0)}},
 263 { "mov",        0x4300,      0xf3ff,      0,    FMT_S1, 0,      {AM1, MEM(SP)}},
 264 { "mov",        0xfa800000,  0xfff30000,  0,    FMT_D2, 0,      {AM1, MEM(IMM16_MEM)}},
 265 { "mov",        0x5c00,      0xfc00,      0,    FMT_S1, 0,      {MEM2(IMM8, SP), AN0}},
 266 { "mov",        0xf80000,    0xfff000,    0,    FMT_D1, 0,      {MEM2(SD8, AM0), DN1}},
 267 { "mov",        0xfa000000,  0xfff00000,  0,    FMT_D2, 0,      {MEM2(SD16, AM0), DN1}},
 268 { "mov",        0x5800,      0xfc00,      0,    FMT_S1, 0,      {MEM2(IMM8, SP), DN0}},
 269 { "mov",        0xfab40000,  0xfffc0000,  0,    FMT_D2, 0,      {MEM2(IMM16, SP), DN0}},
 270 { "mov",        0xf300,      0xffc0,      0,    FMT_D0, 0,      {MEM2(DI, AM0), DN2}},
 271 { "mov",        0xf82000,    0xfff000,    0,    FMT_D1, 0,      {MEM2(SD8,AM0), AN1}},
 272 { "mov",        0xfa200000,  0xfff00000,  0,    FMT_D2, 0,      {MEM2(SD16, AM0), AN1}},
 273 { "mov",        0xfab00000,  0xfffc0000,  0,    FMT_D2, 0,      {MEM2(IMM16, SP), AN0}},
 274 { "mov",        0xf380,      0xffc0,      0,    FMT_D0, 0,      {MEM2(DI, AM0), AN2}},
 275 { "mov",        0x4300,      0xf300,      0,    FMT_S1, 0,      {AM1, MEM2(IMM8, SP)}},
 276 { "mov",        0xf81000,    0xfff000,    0,    FMT_D1, 0,      {DM1, MEM2(SD8, AN0)}},
 277 { "mov",        0xfa100000,  0xfff00000,  0,    FMT_D2, 0,      {DM1, MEM2(SD16, AN0)}},
 278 { "mov",        0x4200,      0xf300,      0,    FMT_S1, 0,      {DM1, MEM2(IMM8, SP)}},
 279 { "mov",        0xfa910000,  0xfff30000,  0,    FMT_D2, 0,      {DM1, MEM2(IMM16, SP)}},
 280 { "mov",        0xf340,      0xffc0,      0,    FMT_D0, 0,      {DM2, MEM2(DI, AN0)}},
 281 { "mov",        0xf83000,    0xfff000,    0,    FMT_D1, 0,      {AM1, MEM2(SD8, AN0)}},
 282 { "mov",        0xfa300000,  0xfff00000,  0,    FMT_D2, 0,      {AM1, MEM2(SD16, AN0)}},
 283 { "mov",        0xfa900000,  0xfff30000,  0,    FMT_D2, 0,      {AM1, MEM2(IMM16, SP)}},
 284 { "mov",        0xf3c0,      0xffc0,      0,    FMT_D0, 0,      {AM2, MEM2(DI, AN0)}},
 285
 286 /* These must come after most of the other move instructions to avoid matching
 287    a symbolic name with IMMxx operands.  Ugh.  */
 288 { "mov",        0x2c0000,    0xfc0000,    0,    FMT_S2, 0,      {SIMM16, DN0}},
 289 { "mov",        0xfccc0000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 290 { "mov",        0x240000,    0xfc0000,    0,    FMT_S2, 0,      {IMM16, AN0}},
 291 { "mov",        0xfcdc0000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, AN0}},
 292 { "mov",        0xfca40000,  0xfffc0000,  0,    FMT_D4, 0,      {MEM(IMM32_MEM), DN0}},
 293 { "mov",        0xfca00000,  0xfffc0000,  0,    FMT_D4, 0,      {MEM(IMM32_MEM), AN0}},
 294 { "mov",        0xfc810000,  0xfff30000,  0,    FMT_D4, 0,      {DM1, MEM(IMM32_MEM)}},
 295 { "mov",        0xfc800000,  0xfff30000,  0,    FMT_D4, 0,      {AM1, MEM(IMM32_MEM)}},
 296 { "mov",        0xfc000000,  0xfff00000,  0,    FMT_D4, 0,      {MEM2(IMM32,AM0), DN1}},
 297 { "mov",        0xfcb40000,  0xfffc0000,  0,    FMT_D4, 0,      {MEM2(IMM32, SP), DN0}},
 298 { "mov",        0xfc200000,  0xfff00000,  0,    FMT_D4, 0,      {MEM2(IMM32,AM0), AN1}},
 299 { "mov",        0xfcb00000,  0xfffc0000,  0,    FMT_D4, 0,      {MEM2(IMM32, SP), AN0}},
 300 { "mov",        0xfc100000,  0xfff00000,  0,    FMT_D4, 0,      {DM1, MEM2(IMM32,AN0)}},
 301 { "mov",        0xfc910000,  0xfff30000,  0,    FMT_D4, 0,      {DM1, MEM2(IMM32, SP)}},
 302 { "mov",        0xfc300000,  0xfff00000,  0,    FMT_D4, 0,      {AM1, MEM2(IMM32,AN0)}},
 303 { "mov",        0xfc900000,  0xfff30000,  0,    FMT_D4, 0,      {AM1, MEM2(IMM32, SP)}},
 304 /* These non-promoting variants need to come after all the other memory
 305    moves.  */
 306 { "mov",        0xf8f000,    0xfffc00,    0,    FMT_D1, AM30,   {MEM2(SD8N, AM0), SP}},
 307 { "mov",        0xf8f400,    0xfffc00,    0,    FMT_D1, AM30,   {SP, MEM2(SD8N, AN0)}},
 308
 309
 310
 311 { "movbu",      0xf040,      0xfff0,      0,    FMT_D0, 0,      {MEM(AM0), DN1}},
 312 { "movbu",      0xf84000,    0xfff000,    0,    FMT_D1, 0,      {MEM2(SD8, AM0), DN1}},
 313 { "movbu",      0xfa400000,  0xfff00000,  0,    FMT_D2, 0,      {MEM2(SD16, AM0), DN1}},
 314 { "movbu",      0xf8b800,    0xfffcff,    0,    FMT_D1, 0,      {MEM(SP), DN0}},
 315 { "movbu",      0xf8b800,    0xfffc00,    0,    FMT_D1, 0,      {MEM2(IMM8, SP), DN0}},
 316 { "movbu",      0xfab80000,  0xfffc0000,  0,    FMT_D2, 0,      {MEM2(IMM16, SP), DN0}},
 317 { "movbu",      0xf400,      0xffc0,      0,    FMT_D0, 0,      {MEM2(DI, AM0), DN2}},
 318 { "movbu",      0x340000,    0xfc0000,    0,    FMT_S2, 0,      {MEM(IMM16_MEM), DN0}},
 319 { "movbu",      0xf050,      0xfff0,      0,    FMT_D0, 0,      {DM1, MEM(AN0)}},
 320 { "movbu",      0xf85000,    0xfff000,    0,    FMT_D1, 0,      {DM1, MEM2(SD8, AN0)}},
 321 { "movbu",      0xfa500000,  0xfff00000,  0,    FMT_D2, 0,      {DM1, MEM2(SD16, AN0)}},
 322 { "movbu",      0xf89200,    0xfff3ff,    0,    FMT_D1, 0,      {DM1, MEM(SP)}},
 323 { "movbu",      0xf89200,    0xfff300,    0,    FMT_D1, 0,      {DM1, MEM2(IMM8, SP)}},
 324 { "movbu",      0xfa920000,  0xfff30000,  0,    FMT_D2, 0,      {DM1, MEM2(IMM16, SP)}},
 325 { "movbu",      0xf440,      0xffc0,      0,    FMT_D0, 0,      {DM2, MEM2(DI, AN0)}},
 326 { "movbu",      0x020000,    0xf30000,    0,    FMT_S2, 0,      {DM1, MEM(IMM16_MEM)}},
 327 { "movbu",      0xfc400000,  0xfff00000,  0,    FMT_D4, 0,      {MEM2(IMM32,AM0), DN1}},
 328 { "movbu",      0xfcb80000,  0xfffc0000,  0,    FMT_D4, 0,      {MEM2(IMM32, SP), DN0}},
 329 { "movbu",      0xfca80000,  0xfffc0000,  0,    FMT_D4, 0,      {MEM(IMM32_MEM), DN0}},
 330 { "movbu",      0xfc500000,  0xfff00000,  0,    FMT_D4, 0,      {DM1, MEM2(IMM32,AN0)}},
 331 { "movbu",      0xfc920000,  0xfff30000,  0,    FMT_D4, 0,      {DM1, MEM2(IMM32, SP)}},
 332 { "movbu",      0xfc820000,  0xfff30000,  0,    FMT_D4, 0,      {DM1, MEM(IMM32_MEM)}},
 333
 334 { "movhu",      0xf060,      0xfff0,      0,    FMT_D0, 0,      {MEM(AM0), DN1}},
 335 { "movhu",      0xf86000,    0xfff000,    0,    FMT_D1, 0,      {MEM2(SD8, AM0), DN1}},
 336 { "movhu",      0xfa600000,  0xfff00000,  0,    FMT_D2, 0,      {MEM2(SD16, AM0), DN1}},
 337 { "movhu",      0xf8bc00,    0xfffcff,    0,    FMT_D1, 0,      {MEM(SP), DN0}},
 338 { "movhu",      0xf8bc00,    0xfffc00,    0,    FMT_D1, 0,      {MEM2(IMM8, SP), DN0}},
 339 { "movhu",      0xfabc0000,  0xfffc0000,  0,    FMT_D2, 0,      {MEM2(IMM16, SP), DN0}},
 340 { "movhu",      0xf480,      0xffc0,      0,    FMT_D0, 0,      {MEM2(DI, AM0), DN2}},
 341 { "movhu",      0x380000,    0xfc0000,    0,    FMT_S2, 0,      {MEM(IMM16_MEM), DN0}},
 342 { "movhu",      0xf070,      0xfff0,      0,    FMT_D0, 0,      {DM1, MEM(AN0)}},
 343 { "movhu",      0xf87000,    0xfff000,    0,    FMT_D1, 0,      {DM1, MEM2(SD8, AN0)}},
 344 { "movhu",      0xfa700000,  0xfff00000,  0,    FMT_D2, 0,      {DM1, MEM2(SD16, AN0)}},
 345 { "movhu",      0xf89300,    0xfff3ff,    0,    FMT_D1, 0,      {DM1, MEM(SP)}},
 346 { "movhu",      0xf89300,    0xfff300,    0,    FMT_D1, 0,      {DM1, MEM2(IMM8, SP)}},
 347 { "movhu",      0xfa930000,  0xfff30000,  0,    FMT_D2, 0,      {DM1, MEM2(IMM16, SP)}},
 348 { "movhu",      0xf4c0,      0xffc0,      0,    FMT_D0, 0,      {DM2, MEM2(DI, AN0)}},
 349 { "movhu",      0x030000,    0xf30000,    0,    FMT_S2, 0,      {DM1, MEM(IMM16_MEM)}},
 350 { "movhu",      0xfc600000,  0xfff00000,  0,    FMT_D4, 0,      {MEM2(IMM32,AM0), DN1}},
 351 { "movhu",      0xfcbc0000,  0xfffc0000,  0,    FMT_D4, 0,      {MEM2(IMM32, SP), DN0}},
 352 { "movhu",      0xfcac0000,  0xfffc0000,  0,    FMT_D4, 0,      {MEM(IMM32_MEM), DN0}},
 353 { "movhu",      0xfc700000,  0xfff00000,  0,    FMT_D4, 0,      {DM1, MEM2(IMM32,AN0)}},
 354 { "movhu",      0xfc930000,  0xfff30000,  0,    FMT_D4, 0,      {DM1, MEM2(IMM32, SP)}},
 355 { "movhu",      0xfc830000,  0xfff30000,  0,    FMT_D4, 0,      {DM1, MEM(IMM32_MEM)}},
 356
 357 { "ext",        0xf2d0,      0xfffc,      0,    FMT_D0, 0,      {DN0}},
 358
 359 { "extb",       0x10,        0xfc,        0,    FMT_S0, 0,      {DN0}},
 360
 361 { "extbu",      0x14,        0xfc,        0,    FMT_S0, 0,      {DN0}},
 362
 363 { "exth",       0x18,        0xfc,        0,    FMT_S0, 0,      {DN0}},
 364
 365 { "exthu",      0x1c,        0xfc,        0,    FMT_S0, 0,      {DN0}},
 366
 367 { "movm",       0xce00,      0xff00,      0,    FMT_S1, 0,      {MEM(SP), REGS}},
 368 { "movm",       0xcf00,      0xff00,      0,    FMT_S1, 0,      {REGS, MEM(SP)}},
 369
 370 { "clr",        0x00,        0xf3,        0,    FMT_S0, 0,      {DN1}},
 371
 372 { "add",        0xe0,        0xf0,        0,    FMT_S0, 0,      {DM1, DN0}},
 373 { "add",        0xf160,      0xfff0,      0,    FMT_D0, 0,      {DM1, AN0}},
 374 { "add",        0xf150,      0xfff0,      0,    FMT_D0, 0,      {AM1, DN0}},
 375 { "add",        0xf170,      0xfff0,      0,    FMT_D0, 0,      {AM1, AN0}},
 376 { "add",        0x2800,      0xfc00,      0,    FMT_S1, 0,      {SIMM8, DN0}},
 377 { "add",        0xfac00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 378 { "add",        0x2000,      0xfc00,      0,    FMT_S1, 0,      {SIMM8, AN0}},
 379 { "add",        0xfad00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, AN0}},
 380 { "add",        0xf8fe00,    0xffff00,    0,    FMT_D1, 0,      {SIMM8, SP}},
 381 { "add",        0xfafe0000,  0xffff0000,  0,    FMT_D2, 0,      {SIMM16, SP}},
 382 { "add",        0xfcc00000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 383 { "add",        0xfcd00000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, AN0}},
 384 { "add",        0xfcfe0000,  0xffff0000,  0,    FMT_D4, 0,      {IMM32, SP}},
 385
 386 { "addc",       0xf140,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 387
 388 { "sub",        0xf100,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 389 { "sub",        0xf120,      0xfff0,      0,    FMT_D0, 0,      {DM1, AN0}},
 390 { "sub",        0xf110,      0xfff0,      0,    FMT_D0, 0,      {AM1, DN0}},
 391 { "sub",        0xf130,      0xfff0,      0,    FMT_D0, 0,      {AM1, AN0}},
 392 { "sub",        0xfcc40000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 393 { "sub",        0xfcd40000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, AN0}},
 394
 395 { "subc",       0xf180,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 396
 397 { "mul",        0xf240,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 398
 399 { "mulu",       0xf250,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 400
 401 { "div",        0xf260,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 402
 403 { "divu",       0xf270,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 404
 405 { "inc",        0x40,        0xf3,        0,    FMT_S0, 0,      {DN1}},
 406 { "inc",        0x41,        0xf3,        0,    FMT_S0, 0,      {AN1}},
 407
 408 { "inc4",       0x50,        0xfc,        0,    FMT_S0, 0,      {AN0}},
 409
 410 { "cmp",        0xa000,      0xf000,      0,    FMT_S1, 0,      {SIMM8, DN01}},
 411 { "cmp",        0xa0,        0xf0,        0x3,  FMT_S0, 0,      {DM1, DN0}},
 412 { "cmp",        0xf1a0,      0xfff0,      0,    FMT_D0, 0,      {DM1, AN0}},
 413 { "cmp",        0xf190,      0xfff0,      0,    FMT_D0, 0,      {AM1, DN0}},
 414 { "cmp",        0xb000,      0xf000,      0,    FMT_S1, 0,      {IMM8, AN01}},
 415 { "cmp",        0xb0,        0xf0,        0x3,  FMT_S0, 0,      {AM1, AN0}},
 416 { "cmp",        0xfac80000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 417 { "cmp",        0xfad80000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, AN0}},
 418 { "cmp",        0xfcc80000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 419 { "cmp",        0xfcd80000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, AN0}},
 420
 421 { "and",        0xf200,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 422 { "and",        0xf8e000,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 423 { "and",        0xfae00000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 424 { "and",        0xfafc0000,  0xffff0000,  0,    FMT_D2, 0,      {IMM16, PSW}},
 425 { "and",        0xfce00000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 426
 427 { "or",         0xf210,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 428 { "or",         0xf8e400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 429 { "or",         0xfae40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 430 { "or",         0xfafd0000,  0xffff0000,  0,    FMT_D2, 0,      {IMM16, PSW}},
 431 { "or",         0xfce40000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 432
 433 { "xor",        0xf220,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 434 { "xor",        0xfae80000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 435 { "xor",        0xfce80000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 436
 437 { "not",        0xf230,      0xfffc,      0,    FMT_D0, 0,      {DN0}},
 438
 439 { "btst",       0xf8ec00,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 440 { "btst",       0xfaec0000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 441 { "btst",       0xfcec0000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 442 { "btst",       0xfe020000,  0xffff0000,  0,    FMT_D5, 0,      {IMM8E, MEM(IMM32_LOWSHIFT8)}},
 443 { "btst",       0xfaf80000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
 444
 445 { "bset",       0xf080,      0xfff0,      0,    FMT_D0, 0,      {DM1, MEM(AN0)}},
 446 { "bset",       0xfe000000,  0xffff0000,  0,    FMT_D5, 0,      {IMM8E, MEM(IMM32_LOWSHIFT8)}},
 447 { "bset",       0xfaf00000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
 448
 449 { "bclr",       0xf090,      0xfff0,      0,    FMT_D0, 0,      {DM1, MEM(AN0)}},
 450 { "bclr",       0xfe010000,  0xffff0000,  0,    FMT_D5, 0,      {IMM8E, MEM(IMM32_LOWSHIFT8)}},
 451 { "bclr",       0xfaf40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
 452
 453 { "asr",        0xf2b0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 454 { "asr",        0xf8c800,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 455 { "asr",        0xf8c801,    0xfffcff,    0,    FMT_D1, 0,      {DN0}},
 456
 457 { "lsr",        0xf2a0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 458 { "lsr",        0xf8c400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 459 { "lsr",        0xf8c401,    0xfffcff,    0,    FMT_D1, 0,      {DN0}},
 460
 461 { "asl",        0xf290,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 462 { "asl",        0xf8c000,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 463 { "asl",        0xf8c001,    0xfffcff,    0,    FMT_D1, 0,      {DN0}},
 464
 465 { "asl2",       0x54,        0xfc,        0,    FMT_S0, 0,      {DN0}},
 466
 467 { "ror",        0xf284,      0xfffc,      0,    FMT_D0, 0,      {DN0}},
 468
 469 { "rol",        0xf280,      0xfffc,      0,    FMT_D0, 0,      {DN0}},
 470
 471 { "beq",        0xc800,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 472 { "bne",        0xc900,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 473 { "bgt",        0xc100,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 474 { "bge",        0xc200,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 475 { "ble",        0xc300,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 476 { "blt",        0xc000,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 477 { "bhi",        0xc500,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 478 { "bcc",        0xc600,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 479 { "bls",        0xc700,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 480 { "bcs",        0xc400,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 481 { "bvc",        0xf8e800,    0xffff00,    0,    FMT_D1, 0,      {SD8N_PCREL}},
 482 { "bvs",        0xf8e900,    0xffff00,    0,    FMT_D1, 0,      {SD8N_PCREL}},
 483 { "bnc",        0xf8ea00,    0xffff00,    0,    FMT_D1, 0,      {SD8N_PCREL}},
 484 { "bns",        0xf8eb00,    0xffff00,    0,    FMT_D1, 0,      {SD8N_PCREL}},
 485 { "bra",        0xca00,      0xff00,      0,    FMT_S1, 0,      {SD8N_PCREL}},
 486
 487 { "leq",        0xd8,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 488 { "lne",        0xd9,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 489 { "lgt",        0xd1,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 490 { "lge",        0xd2,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 491 { "lle",        0xd3,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 492 { "llt",        0xd0,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 493 { "lhi",        0xd5,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 494 { "lcc",        0xd6,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 495 { "lls",        0xd7,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 496 { "lcs",        0xd4,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 497 { "lra",        0xda,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 498 { "setlb",      0xdb,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 499
 500 { "jmp",        0xf0f4,      0xfffc,      0,    FMT_D0, 0,      {PAREN,AN0,PAREN}},
 501 { "jmp",        0xcc0000,    0xff0000,    0,    FMT_S2, 0,      {IMM16_PCREL}},
 502 { "jmp",        0xdc000000,  0xff000000,  0,    FMT_S4, 0,      {IMM32_HIGH24}},
 503 { "call",       0xcd000000,  0xff000000,  0,    FMT_S4, 0,      {D16_SHIFT,REGS,IMM8E}},
 504 { "call",       0xdd000000,  0xff000000,  0,    FMT_S6, 0,      {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
 505 { "calls",      0xf0f0,      0xfffc,      0,    FMT_D0, 0,      {PAREN,AN0,PAREN}},
 506 { "calls",      0xfaff0000,  0xffff0000,  0,    FMT_D2, 0,      {IMM16_PCREL}},
 507 { "calls",      0xfcff0000,  0xffff0000,  0,    FMT_D4, 0,      {IMM32_PCREL}},
 508
 509 { "ret",        0xdf0000,    0xff0000,    0,    FMT_S2, 0,      {REGS_SHIFT8, IMM8}},
 510 { "retf",       0xde0000,    0xff0000,    0,    FMT_S2, 0,      {REGS_SHIFT8, IMM8}},
 511 { "rets",       0xf0fc,      0xffff,      0,    FMT_D0, 0,      {UNUSED}},
 512 { "rti",        0xf0fd,      0xffff,      0,    FMT_D0, 0,      {UNUSED}},
 513 { "trap",       0xf0fe,      0xffff,      0,    FMT_D0, 0,      {UNUSED}},
 514 { "rtm",        0xf0ff,      0xffff,      0,    FMT_D0, 0,      {UNUSED}},
 515 { "nop",        0xcb,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 516
 517 /* UDF instructions.  */
 518 { "udf00",      0xf600,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 519 { "udf00",      0xf90000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 520 { "udf00",      0xfb000000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 521 { "udf00",      0xfd000000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 522 { "udf01",      0xf610,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 523 { "udf01",      0xf91000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 524 { "udf01",      0xfb100000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 525 { "udf01",      0xfd100000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 526 { "udf02",      0xf620,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 527 { "udf02",      0xf92000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 528 { "udf02",      0xfb200000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 529 { "udf02",      0xfd200000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 530 { "udf03",      0xf630,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 531 { "udf03",      0xf93000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 532 { "udf03",      0xfb300000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 533 { "udf03",      0xfd300000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 534 { "udf04",      0xf640,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 535 { "udf04",      0xf94000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 536 { "udf04",      0xfb400000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 537 { "udf04",      0xfd400000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 538 { "udf05",      0xf650,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 539 { "udf05",      0xf95000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 540 { "udf05",      0xfb500000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 541 { "udf05",      0xfd500000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 542 { "udf06",      0xf660,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 543 { "udf06",      0xf96000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 544 { "udf06",      0xfb600000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 545 { "udf06",      0xfd600000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 546 { "udf07",      0xf670,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 547 { "udf07",      0xf97000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 548 { "udf07",      0xfb700000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 549 { "udf07",      0xfd700000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 550 { "udf08",      0xf680,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 551 { "udf08",      0xf98000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 552 { "udf08",      0xfb800000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 553 { "udf08",      0xfd800000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 554 { "udf09",      0xf690,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 555 { "udf09",      0xf99000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 556 { "udf09",      0xfb900000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 557 { "udf09",      0xfd900000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 558 { "udf10",      0xf6a0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 559 { "udf10",      0xf9a000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 560 { "udf10",      0xfba00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 561 { "udf10",      0xfda00000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 562 { "udf11",      0xf6b0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 563 { "udf11",      0xf9b000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 564 { "udf11",      0xfbb00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 565 { "udf11",      0xfdb00000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 566 { "udf12",      0xf6c0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 567 { "udf12",      0xf9c000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 568 { "udf12",      0xfbc00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 569 { "udf12",      0xfdc00000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 570 { "udf13",      0xf6d0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 571 { "udf13",      0xf9d000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 572 { "udf13",      0xfbd00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 573 { "udf13",      0xfdd00000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 574 { "udf14",      0xf6e0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 575 { "udf14",      0xf9e000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 576 { "udf14",      0xfbe00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 577 { "udf14",      0xfde00000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 578 { "udf15",      0xf6f0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 579 { "udf15",      0xf9f000,    0xfffc00,    0,    FMT_D1, 0,      {SIMM8, DN0}},
 580 { "udf15",      0xfbf00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
 581 { "udf15",      0xfdf00000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 582 { "udf20",      0xf500,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 583 { "udf21",      0xf510,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 584 { "udf22",      0xf520,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 585 { "udf23",      0xf530,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 586 { "udf24",      0xf540,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 587 { "udf25",      0xf550,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 588 { "udf26",      0xf560,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 589 { "udf27",      0xf570,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 590 { "udf28",      0xf580,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 591 { "udf29",      0xf590,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 592 { "udf30",      0xf5a0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 593 { "udf31",      0xf5b0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 594 { "udf32",      0xf5c0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 595 { "udf33",      0xf5d0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 596 { "udf34",      0xf5e0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 597 { "udf35",      0xf5f0,      0xfff0,      0,    FMT_D0, 0,      {DM1, DN0}},
 598 { "udfu00",     0xf90400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 599 { "udfu00",     0xfb040000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 600 { "udfu00",     0xfd040000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 601 { "udfu01",     0xf91400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 602 { "udfu01",     0xfb140000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 603 { "udfu01",     0xfd140000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 604 { "udfu02",     0xf92400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 605 { "udfu02",     0xfb240000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 606 { "udfu02",     0xfd240000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 607 { "udfu03",     0xf93400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 608 { "udfu03",     0xfb340000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 609 { "udfu03",     0xfd340000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 610 { "udfu04",     0xf94400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 611 { "udfu04",     0xfb440000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 612 { "udfu04",     0xfd440000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 613 { "udfu05",     0xf95400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 614 { "udfu05",     0xfb540000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 615 { "udfu05",     0xfd540000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 616 { "udfu06",     0xf96400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 617 { "udfu06",     0xfb640000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 618 { "udfu06",     0xfd640000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 619 { "udfu07",     0xf97400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 620 { "udfu07",     0xfb740000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 621 { "udfu07",     0xfd740000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 622 { "udfu08",     0xf98400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 623 { "udfu08",     0xfb840000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 624 { "udfu08",     0xfd840000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 625 { "udfu09",     0xf99400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 626 { "udfu09",     0xfb940000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 627 { "udfu09",     0xfd940000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 628 { "udfu10",     0xf9a400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 629 { "udfu10",     0xfba40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 630 { "udfu10",     0xfda40000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 631 { "udfu11",     0xf9b400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 632 { "udfu11",     0xfbb40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 633 { "udfu11",     0xfdb40000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 634 { "udfu12",     0xf9c400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 635 { "udfu12",     0xfbc40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 636 { "udfu12",     0xfdc40000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 637 { "udfu13",     0xf9d400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 638 { "udfu13",     0xfbd40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 639 { "udfu13",     0xfdd40000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 640 { "udfu14",     0xf9e400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 641 { "udfu14",     0xfbe40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 642 { "udfu14",     0xfde40000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 643 { "udfu15",     0xf9f400,    0xfffc00,    0,    FMT_D1, 0,      {IMM8, DN0}},
 644 { "udfu15",     0xfbf40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
 645 { "udfu15",     0xfdf40000,  0xfffc0000,  0,    FMT_D4, 0,      {IMM32, DN0}},
 646
 647 { "putx",       0xf500,      0xfff0,      0,    FMT_D0, AM30,   {DN01}},
 648 { "getx",       0xf6f0,      0xfff0,      0,    FMT_D0, AM30,   {DN01}},
 649 { "mulq",       0xf600,      0xfff0,      0,    FMT_D0, AM30,   {DM1, DN0}},
 650 { "mulq",       0xf90000,    0xfffc00,    0,    FMT_D1, AM30,   {SIMM8, DN0}},
 651 { "mulq",       0xfb000000,  0xfffc0000,  0,    FMT_D2, AM30,   {SIMM16, DN0}},
 652 { "mulq",       0xfd000000,  0xfffc0000,  0,    FMT_D4, AM30,   {IMM32, DN0}},
 653 { "mulqu",      0xf610,      0xfff0,      0,    FMT_D0, AM30,   {DM1, DN0}},
 654 { "mulqu",      0xf91400,    0xfffc00,    0,    FMT_D1, AM30,   {SIMM8, DN0}},
 655 { "mulqu",      0xfb140000,  0xfffc0000,  0,    FMT_D2, AM30,   {SIMM16, DN0}},
 656 { "mulqu",      0xfd140000,  0xfffc0000,  0,    FMT_D4, AM30,   {IMM32, DN0}},
 657 { "sat16",      0xf640,      0xfff0,      0,    FMT_D0, AM30,   {DM1, DN0}},
 658
 659 { "sat24",      0xf650,      0xfff0,      0,    FMT_D0, AM30,   {DM1, DN0}},
 660
 661 { "bsch",       0xf670,      0xfff0,      0,    FMT_D0, AM30,   {DM1, DN0}},
 662
 663 /* Extension.  We need some instruction to trigger "emulated syscalls"
 664    for our simulator.  */
 665 { "syscall",    0xf0c0,      0xffff,      0,    FMT_D0, 0,      {UNUSED}},
 666
 667 /* Extension.  When talking to the simulator, gdb requires some instruction
 668    that will trigger a "breakpoint" (really just an instruction that isn't
 669    otherwise used by the tools.  This instruction must be the same size
 670    as the smallest instruction on the target machine.  In the case of the
 671    mn10x00 the "break" instruction must be one byte.  0xff is available on
 672    both mn10x00 architectures.  */
 673 { "break",      0xff,        0xff,        0,    FMT_S0, 0,      {UNUSED}},
 674
 675
 676 { 0, 0, 0, 0, 0, 0, {0}},
 677
 678 } ;
 679
 680 const int mn10300_num_opcodes =
 681   sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
 682
 683 \f