bfd/
[binutils.git] / opcodes / d30v-dis.c
blob2a2916eeccc46a674f1012b9f8e59e521e4a7065
1 /* Disassemble D30V instructions.
2 Copyright 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
17 MA 02110-1301, USA. */
19 #include <stdio.h>
20 #include "sysdep.h"
21 #include "opcode/d30v.h"
22 #include "dis-asm.h"
23 #include "opintl.h"
25 #define PC_MASK 0xFFFFFFFF
27 /* Return 0 if lookup fails,
28 1 if found and only one form,
29 2 if found and there are short and long forms. */
31 static int
32 lookup_opcode (struct d30v_insn *insn, long num, int is_long)
34 int i = 0, index;
35 struct d30v_format *f;
36 struct d30v_opcode *op = (struct d30v_opcode *) d30v_opcode_table;
37 int op1 = (num >> 25) & 0x7;
38 int op2 = (num >> 20) & 0x1f;
39 int mod = (num >> 18) & 0x3;
41 /* Find the opcode. */
44 if ((op->op1 == op1) && (op->op2 == op2))
45 break;
46 op++;
48 while (op->name);
50 if (!op || !op->name)
51 return 0;
53 while (op->op1 == op1 && op->op2 == op2)
55 /* Scan through all the formats for the opcode. */
56 index = op->format[i++];
59 f = (struct d30v_format *) &d30v_format_table[index];
60 while (f->form == index)
62 if ((!is_long || f->form >= LONG) && (f->modifier == mod))
64 insn->form = f;
65 break;
67 f++;
69 if (insn->form)
70 break;
72 while ((index = op->format[i++]) != 0);
73 if (insn->form)
74 break;
75 op++;
76 i = 0;
78 if (insn->form == NULL)
79 return 0;
81 insn->op = op;
82 insn->ecc = (num >> 28) & 0x7;
83 if (op->format[1])
84 return 2;
85 else
86 return 1;
89 static int
90 extract_value (long long num, struct d30v_operand *oper, int is_long)
92 int val;
93 int shift = 12 - oper->position;
94 int mask = (0xFFFFFFFF >> (32 - oper->bits));
96 if (is_long)
98 if (oper->bits == 32)
99 /* Piece together 32-bit constant. */
100 val = ((num & 0x3FFFF)
101 | ((num & 0xFF00000) >> 2)
102 | ((num & 0x3F00000000LL) >> 6));
103 else
104 val = (num >> (32 + shift)) & mask;
106 else
107 val = (num >> shift) & mask;
109 if (oper->flags & OPERAND_SHIFT)
110 val <<= 3;
112 return val;
115 static void
116 print_insn (struct disassemble_info *info,
117 bfd_vma memaddr,
118 long long num,
119 struct d30v_insn *insn,
120 int is_long,
121 int show_ext)
123 int val, opnum, need_comma = 0;
124 struct d30v_operand *oper;
125 int i, match, opind = 0, need_paren = 0, found_control = 0;
127 (*info->fprintf_func) (info->stream, "%s", insn->op->name);
129 /* Check for CMP or CMPU. */
130 if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME)
132 opind++;
133 val =
134 extract_value (num,
135 (struct d30v_operand *) &d30v_operand_table[insn->form->operands[0]],
136 is_long);
137 (*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]);
140 /* Add in ".s" or ".l". */
141 if (show_ext == 2)
143 if (is_long)
144 (*info->fprintf_func) (info->stream, ".l");
145 else
146 (*info->fprintf_func) (info->stream, ".s");
149 if (insn->ecc)
150 (*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]);
152 (*info->fprintf_func) (info->stream, "\t");
154 while ((opnum = insn->form->operands[opind++]) != 0)
156 int bits;
158 oper = (struct d30v_operand *) &d30v_operand_table[opnum];
159 bits = oper->bits;
160 if (oper->flags & OPERAND_SHIFT)
161 bits += 3;
163 if (need_comma
164 && oper->flags != OPERAND_PLUS
165 && oper->flags != OPERAND_MINUS)
167 need_comma = 0;
168 (*info->fprintf_func) (info->stream, ", ");
171 if (oper->flags == OPERAND_ATMINUS)
173 (*info->fprintf_func) (info->stream, "@-");
174 continue;
176 if (oper->flags == OPERAND_MINUS)
178 (*info->fprintf_func) (info->stream, "-");
179 continue;
181 if (oper->flags == OPERAND_PLUS)
183 (*info->fprintf_func) (info->stream, "+");
184 continue;
186 if (oper->flags == OPERAND_ATSIGN)
188 (*info->fprintf_func) (info->stream, "@");
189 continue;
191 if (oper->flags == OPERAND_ATPAR)
193 (*info->fprintf_func) (info->stream, "@(");
194 need_paren = 1;
195 continue;
198 if (oper->flags == OPERAND_SPECIAL)
199 continue;
201 val = extract_value (num, oper, is_long);
203 if (oper->flags & OPERAND_REG)
205 match = 0;
206 if (oper->flags & OPERAND_CONTROL)
208 struct d30v_operand *oper3 =
209 (struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]];
210 int id = extract_value (num, oper3, is_long);
212 found_control = 1;
213 switch (id)
215 case 0:
216 val |= OPERAND_CONTROL;
217 break;
218 case 1:
219 case 2:
220 val = OPERAND_CONTROL + MAX_CONTROL_REG + id;
221 break;
222 case 3:
223 val |= OPERAND_FLAG;
224 break;
225 default:
226 fprintf (stderr, "illegal id (%d)\n", id);
229 else if (oper->flags & OPERAND_ACC)
230 val |= OPERAND_ACC;
231 else if (oper->flags & OPERAND_FLAG)
232 val |= OPERAND_FLAG;
233 for (i = 0; i < reg_name_cnt (); i++)
235 if (val == pre_defined_registers[i].value)
237 if (pre_defined_registers[i].pname)
238 (*info->fprintf_func)
239 (info->stream, "%s", pre_defined_registers[i].pname);
240 else
241 (*info->fprintf_func)
242 (info->stream, "%s", pre_defined_registers[i].name);
243 match = 1;
244 break;
247 if (match == 0)
249 /* This would only get executed if a register was not in
250 the register table. */
251 (*info->fprintf_func)
252 (info->stream, _("<unknown register %d>"), val & 0x3F);
255 /* repeati has a relocation, but its first argument is a plain
256 immediate. OTOH instructions like djsri have a pc-relative
257 delay target, but an absolute jump target. Therefore, a test
258 of insn->op->reloc_flag is not specific enough; we must test
259 if the actual operand we are handling now is pc-relative. */
260 else if (oper->flags & OPERAND_PCREL)
262 int neg = 0;
264 /* IMM6S3 is unsigned. */
265 if (oper->flags & OPERAND_SIGNED || bits == 32)
267 long max;
268 max = (1 << (bits - 1));
269 if (val & max)
271 if (bits == 32)
272 val = -val;
273 else
274 val = -val & ((1 << bits) - 1);
275 neg = 1;
278 if (neg)
280 (*info->fprintf_func) (info->stream, "-%x\t(", val);
281 (*info->print_address_func) ((memaddr - val) & PC_MASK, info);
282 (*info->fprintf_func) (info->stream, ")");
284 else
286 (*info->fprintf_func) (info->stream, "%x\t(", val);
287 (*info->print_address_func) ((memaddr + val) & PC_MASK, info);
288 (*info->fprintf_func) (info->stream, ")");
291 else if (insn->op->reloc_flag == RELOC_ABS)
293 (*info->print_address_func) (val, info);
295 else
297 if (oper->flags & OPERAND_SIGNED)
299 int max = (1 << (bits - 1));
301 if (val & max)
303 val = -val;
304 if (bits < 32)
305 val &= ((1 << bits) - 1);
306 (*info->fprintf_func) (info->stream, "-");
309 (*info->fprintf_func) (info->stream, "0x%x", val);
311 /* If there is another operand, then write a comma and space. */
312 if (insn->form->operands[opind] && !(found_control && opind == 2))
313 need_comma = 1;
315 if (need_paren)
316 (*info->fprintf_func) (info->stream, ")");
320 print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
322 int status, result;
323 bfd_byte buffer[12];
324 unsigned long in1, in2;
325 struct d30v_insn insn;
326 long long num;
328 insn.form = NULL;
330 info->bytes_per_line = 8;
331 info->bytes_per_chunk = 4;
332 info->display_endian = BFD_ENDIAN_BIG;
334 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
335 if (status != 0)
337 (*info->memory_error_func) (status, memaddr, info);
338 return -1;
340 in1 = bfd_getb32 (buffer);
342 status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
343 if (status != 0)
345 info->bytes_per_line = 8;
346 if (!(result = lookup_opcode (&insn, in1, 0)))
347 (*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
348 else
349 print_insn (info, memaddr, (long long) in1, &insn, 0, result);
350 return 4;
352 in2 = bfd_getb32 (buffer);
354 if (in1 & in2 & FM01)
356 /* LONG instruction. */
357 if (!(result = lookup_opcode (&insn, in1, 1)))
359 (*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2);
360 return 8;
362 num = (long long) in1 << 32 | in2;
363 print_insn (info, memaddr, num, &insn, 1, result);
365 else
367 num = in1;
368 if (!(result = lookup_opcode (&insn, in1, 0)))
369 (*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
370 else
371 print_insn (info, memaddr, num, &insn, 0, result);
373 switch (((in1 >> 31) << 1) | (in2 >> 31))
375 case 0:
376 (*info->fprintf_func) (info->stream, "\t||\t");
377 break;
378 case 1:
379 (*info->fprintf_func) (info->stream, "\t->\t");
380 break;
381 case 2:
382 (*info->fprintf_func) (info->stream, "\t<-\t");
383 default:
384 break;
387 insn.form = NULL;
388 num = in2;
389 if (!(result = lookup_opcode (&insn, in2, 0)))
390 (*info->fprintf_func) (info->stream, ".long\t0x%lx", in2);
391 else
392 print_insn (info, memaddr, num, &insn, 0, result);
394 return 8;