1 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
3 * score-dis.c (print_insn): Correct the error code to print
4 correct PCE instruction disassembly.
6 2006-10-26 Ben Elliston <bje@au.ibm.com>
7 Anton Blanchard <anton@samba.org>
8 Peter Bergner <bergner@vnet.ibm.com>
10 * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
11 AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
13 (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
14 "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
15 Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
16 "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
17 "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
18 "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
19 "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
20 "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
21 "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
22 "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
23 "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
24 "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
25 "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
26 "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
27 "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
28 "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
29 "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
30 "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
31 "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
32 "diexq" and "diexq." opcodes.
34 2006-10-26 Daniel Jacobowitz <dan@codesourcery.com>
36 * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
38 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
39 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
40 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
41 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
42 Alan Modra <amodra@bigpond.net.au>
44 * spu-dis.c: New file.
45 * spu-opc.c: New file.
46 * configure.in: Add SPU support.
47 * disassemble.c: Likewise.
48 * Makefile.am: Likewise. Run "make dep-am".
49 * Makefile.in: Regenerate.
50 * configure: Regenerate.
51 * po/POTFILES.in: Regenerate.
53 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
55 * ppc-opc.c (CELL): New define.
56 (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx,
57 cell specific instructions. Add {st,l}x{r,l}{,l} cell specific
59 * ppc-dis.c (powerpc_dialect): Handle cell.
61 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
63 * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
64 amdfam10 architecture.
66 (print_insn): Disallow REP prefix for POPCNT.
68 2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
70 * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
73 2006-10-18 Dave Brolley <brolley@redhat.com>
75 * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
76 * configure: Regenerated.
78 2006-09-29 Alan Modra <amodra@bigpond.net.au>
80 * po/POTFILES.in: Regenerate.
82 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
83 Joseph Myers <joseph@codesourcery.com>
84 Ian Lance Taylor <ian@wasabisystems.com>
85 Ben Elliston <bje@wasabisystems.com>
87 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
88 only be used with the default multiply-add operation, so if N is
89 set, don't bother printing X. Add new iwmmxt instructions.
90 (IWMMXT_INSN_COUNT): Update.
91 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
93 (print_insn_coprocessor): Check for iWMMXt2. Handle format
96 2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
99 * i386-dis.c (prefix_user_table): Fix the second operand of
100 maskmovdqu instruction to allow only %xmm register instead of
101 both %xmm register and memory.
103 2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
106 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
109 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
111 * score-dis.c: New file.
112 * score-opc.h: New file.
113 * Makefile.am: Add Score files.
114 * Makefile.in: Regenerate.
115 * configure.in: Add support for Score target.
116 * configure: Regenerate.
117 * disassemble.c: Add support for Score target.
119 2006-09-16 Nick Clifton <nickc@redhat.com>
120 Pedro Alves <pedro_alves@portugalmail.pt>
122 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
123 macros defined in bfd.h.
124 * cris-dis.c: Likewise.
125 * h8300-dis.c: Likewise.
126 * i386-dis.c: Likewise.
127 * ia64-gen.c: Likewise.
128 * mips-dis: Likewise.
130 2006-09-04 Paul Brook <paul@codesourcery.com>
132 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
134 2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
136 * i386-dis.c (three_byte_table): Expand to 256 elements.
138 2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
141 * i386-dis.c (MXC,EMC): Define.
142 (OP_MXC): New function to handle cvt* (convert instructions) between
143 %xmm and %mm register correctly.
145 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
146 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
149 2006-07-29 Richard Sandiford <richard@codesourcery.com>
151 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
154 2006-07-19 Paul Brook <paul@codesourcery.com>
156 * armd-dis.c (arm_opcodes): Fix rbit opcode.
158 2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
160 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
161 "sldt", "str" and "smsw".
163 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
166 * i386-dis.c (GRP11_C6): NEW.
167 (GRP11_C7): Likewise.
174 (GRPPADLCK1): Likewise.
175 (GRPPADLCK2): Likewise.
176 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
178 (grps): Add entries for GRP11_C6 and GRP11_C7.
180 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
181 Michael Meissner <michael.meissner@amd.com>
183 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
184 support for amdfam10 SSE4a/ABM instructions. Modify all
185 initializer macros to have additional arguments. Disallow REP
186 prefix for non-string instructions.
189 2006-07-05 Julian Brown <julian@codesourcery.com>
191 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
193 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
195 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
196 (twobyte_has_modrm): Set 1 for 0x1f.
198 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
200 * i386-dis.c (NOP_Fixup): Removed.
202 (NOP_Fixup2): Likewise.
203 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
205 2006-06-12 Julian Brown <julian@codesourcery.com>
207 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
210 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>
212 * i386.c (GRP10): Renamed to ...
214 (GRP11): Renamed to ...
216 (GRP12): Renamed to ...
218 (GRP13): Renamed to ...
220 (GRP14): Renamed to ...
222 (dis386_twobyte): Updated.
225 2006-06-09 Nick Clifton <nickc@redhat.com>
227 * po/fi.po: Updated Finnish translation.
229 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
231 * po/Make-in (pdf, ps): New dummy targets.
233 2006-06-06 Paul Brook <paul@codesourcery.com>
235 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
237 (neon_opcodes): Add conditional execution specifiers.
238 (thumb_opcodes): Ditto.
239 (thumb32_opcodes): Ditto.
240 (arm_conditional): Change 0xe to "al" and add "" to end.
241 (ifthen_state, ifthen_next_state, ifthen_address): New.
242 (IFTHEN_COND): Define.
243 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
244 (print_insn_arm): Change %c to use new values of arm_conditional.
245 (print_insn_thumb16): Print thumb conditions. Add %I.
246 (print_insn_thumb32): Print thumb conditions.
247 (find_ifthen_state): New function.
248 (print_insn): Track IT block state.
250 2006-06-06 Ben Elliston <bje@au.ibm.com>
251 Anton Blanchard <anton@samba.org>
252 Peter Bergner <bergner@vnet.ibm.com>
254 * ppc-dis.c (powerpc_dialect): Handle power6 option.
255 (print_ppc_disassembler_options): Mention power6.
257 2006-06-06 Thiemo Seufer <ths@mips.com>
258 Chao-ying Fu <fu@mips.com>
260 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
261 * mips-opc.c: Add DSP64 instructions.
263 2006-06-06 Alan Modra <amodra@bigpond.net.au>
265 * m68hc11-dis.c (print_insn): Warning fix.
267 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
269 * po/Make-in (top_builddir): Define.
271 2006-06-05 Alan Modra <amodra@bigpond.net.au>
273 * Makefile.am: Run "make dep-am".
274 * Makefile.in: Regenerate.
275 * config.in: Regenerate.
277 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
279 * Makefile.am (INCLUDES): Use @INCINTL@.
280 * acinclude.m4: Include new gettext macros.
281 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
282 Remove local code for po/Makefile.
283 * Makefile.in, aclocal.m4, configure: Regenerated.
285 2006-05-30 Nick Clifton <nickc@redhat.com>
287 * po/es.po: Updated Spanish translation.
289 2006-05-25 Richard Sandiford <richard@codesourcery.com>
291 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
292 and fmovem entries. Put register list entries before immediate
293 mask entries. Use "l" rather than "L" in the fmovem entries.
294 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
296 (m68k_scan_mask): New function, split out from...
297 (print_insn_m68k): ...here. If no architecture has been set,
298 first try printing an m680x0 instruction, then try a Coldfire one.
300 2006-05-24 Nick Clifton <nickc@redhat.com>
302 * po/ga.po: Updated Irish translation.
304 2006-05-22 Nick Clifton <nickc@redhat.com>
306 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
308 2006-05-22 Nick Clifton <nickc@redhat.com>
310 * po/nl.po: Updated translation.
312 2006-05-18 Alan Modra <amodra@bigpond.net.au>
314 * avr-dis.c: Formatting fix.
316 2006-05-14 Thiemo Seufer <ths@mips.com>
318 * mips16-opc.c (I1, I32, I64): New shortcut defines.
319 (mips16_opcodes): Change membership of instructions to their
322 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
324 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
326 2006-05-05 Julian Brown <julian@codesourcery.com>
328 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
331 2006-05-05 Thiemo Seufer <ths@mips.com>
332 David Ung <davidu@mips.com>
334 * mips-opc.c: Add macro for cache instruction.
336 2006-05-04 Thiemo Seufer <ths@mips.com>
337 Nigel Stephens <nigel@mips.com>
338 David Ung <davidu@mips.com>
340 * mips-dis.c (mips_arch_choices): Add smartmips instruction
341 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
342 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
344 * mips-opc.c: fix random typos in comments.
345 (INSN_SMARTMIPS): New defines.
346 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
347 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
348 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
349 FP_S and FP_D flags to denote single and double register
350 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
351 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
352 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
353 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
355 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
357 2006-05-03 Thiemo Seufer <ths@mips.com>
359 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
361 2006-05-02 Thiemo Seufer <ths@mips.com>
362 Nigel Stephens <nigel@mips.com>
363 David Ung <davidu@mips.com>
365 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
366 (print_mips16_insn_arg): Force mips16 to odd addresses.
368 2006-04-30 Thiemo Seufer <ths@mips.com>
369 David Ung <davidu@mips.com>
371 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
373 * mips-dis.c (print_insn_args): Adds udi argument handling.
375 2006-04-28 James E Wilson <wilson@specifix.com>
377 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
380 2006-04-28 Thiemo Seufer <ths@mips.com>
381 David Ung <davidu@mips.com>
382 Nigel Stephens <nigel@mips.com>
384 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
387 2006-04-28 Thiemo Seufer <ths@mips.com>
388 Nigel Stephens <nigel@mips.com>
389 David Ung <davidu@mips.com>
391 * mips-dis.c (print_insn_args): Add mips_opcode argument.
392 (print_insn_mips): Adjust print_insn_args call.
394 2006-04-28 Thiemo Seufer <ths@mips.com>
395 Nigel Stephens <nigel@mips.com>
397 * mips-dis.c (print_insn_args): Print $fcc only for FP
398 instructions, use $cc elsewise.
400 2006-04-28 Thiemo Seufer <ths@mips.com>
401 Nigel Stephens <nigel@mips.com>
403 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
404 Map MIPS16 registers to O32 names.
405 (print_mips16_insn_arg): Use mips16_reg_names.
407 2006-04-26 Julian Brown <julian@codesourcery.com>
409 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
412 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
413 Julian Brown <julian@codesourcery.com>
415 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
416 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
417 Add unified load/store instruction names.
418 (neon_opcode_table): New.
419 (arm_opcodes): Expand meaning of %<bitfield>['`?].
420 (arm_decode_bitfield): New.
421 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
422 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
423 (print_insn_neon): New.
424 (print_insn_arm): Adjust print_insn_coprocessor call. Call
425 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
426 (print_insn_thumb32): Likewise.
428 2006-04-19 Alan Modra <amodra@bigpond.net.au>
430 * Makefile.am: Run "make dep-am".
431 * Makefile.in: Regenerate.
433 2006-04-19 Alan Modra <amodra@bigpond.net.au>
435 * avr-dis.c (avr_operand): Warning fix.
437 * configure: Regenerate.
439 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
441 * po/POTFILES.in: Regenerated.
443 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
446 * avr-dis.c (avr_operand): Arrange for a comment to appear before
447 the symolic form of an address, so that the output of objdump -d
450 2006-04-10 DJ Delorie <dj@redhat.com>
452 * m32c-asm.c: Regenerate.
454 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
456 * Makefile.am: Add install-html target.
457 * Makefile.in: Regenerate.
459 2006-04-06 Nick Clifton <nickc@redhat.com>
461 * po/vi/po: Updated Vietnamese translation.
463 2006-03-31 Paul Koning <ni1d@arrl.net>
465 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
467 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
469 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
470 logic to identify halfword shifts.
472 2006-03-16 Paul Brook <paul@codesourcery.com>
474 * arm-dis.c (arm_opcodes): Rename swi to svc.
475 (thumb_opcodes): Ditto.
477 2006-03-13 DJ Delorie <dj@redhat.com>
479 * m32c-asm.c: Regenerate.
480 * m32c-desc.c: Likewise.
481 * m32c-desc.h: Likewise.
482 * m32c-dis.c: Likewise.
483 * m32c-ibld.c: Likewise.
484 * m32c-opc.c: Likewise.
485 * m32c-opc.h: Likewise.
487 2006-03-10 DJ Delorie <dj@redhat.com>
489 * m32c-desc.c: Regenerate with mul.l, mulu.l.
490 * m32c-opc.c: Likewise.
491 * m32c-opc.h: Likewise.
494 2006-03-09 Nick Clifton <nickc@redhat.com>
496 * po/sv.po: Updated Swedish translation.
498 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
501 * i386-dis.c (REP_Fixup): New function.
502 (AL): Remove duplicate.
507 (indirDXr): Likewise.
510 (dis386): Updated entries of ins, outs, movs, lods and stos.
512 2006-03-05 Nick Clifton <nickc@redhat.com>
514 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
515 signed 32-bit value into an unsigned 32-bit field when the host is
517 * fr30-ibld.c: Regenerate.
518 * frv-ibld.c: Regenerate.
519 * ip2k-ibld.c: Regenerate.
520 * iq2000-asm.c: Regenerate.
521 * iq2000-ibld.c: Regenerate.
522 * m32c-ibld.c: Regenerate.
523 * m32r-ibld.c: Regenerate.
524 * openrisc-ibld.c: Regenerate.
525 * xc16x-ibld.c: Regenerate.
526 * xstormy16-ibld.c: Regenerate.
528 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
530 * xc16x-asm.c: Regenerate.
531 * xc16x-dis.c: Regenerate.
533 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
535 * po/Make-in: Add html target.
537 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
539 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
540 Intel Merom New Instructions.
541 (THREE_BYTE_0): Likewise.
542 (THREE_BYTE_1): Likewise.
543 (three_byte_table): Likewise.
544 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
545 THREE_BYTE_1 for entry 0x3a.
546 (twobyte_has_modrm): Updated.
547 (twobyte_uses_SSE_prefix): Likewise.
548 (print_insn): Handle 3-byte opcodes used by Intel Merom New
551 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
553 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
554 (v9_hpriv_reg_names): New table.
555 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
556 New cases '$' and '%' for read/write hyperprivileged register.
557 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
558 window handling and rdhpr/wrhpr instructions.
560 2006-02-24 DJ Delorie <dj@redhat.com>
562 * m32c-desc.c: Regenerate with linker relaxation attributes.
563 * m32c-desc.h: Likewise.
564 * m32c-dis.c: Likewise.
565 * m32c-opc.c: Likewise.
567 2006-02-24 Paul Brook <paul@codesourcery.com>
569 * arm-dis.c (arm_opcodes): Add V7 instructions.
570 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
571 (print_arm_address): New function.
572 (print_insn_arm): Use it. Add 'P' and 'U' cases.
573 (psr_name): New function.
574 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
576 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
578 * ia64-opc-i.c (bXc): New.
580 (OpX2TaTbYaXcC): Likewise.
583 (ia64_opcodes_i): Add instructions for tf.
585 * ia64-opc.h (IMMU5b): New.
587 * ia64-asmtab.c: Regenerated.
589 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
591 * ia64-gen.c: Update copyright years.
592 * ia64-opc-b.c: Likewise.
594 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
596 * ia64-gen.c (lookup_regindex): Handle ".vm".
597 (print_dependency_table): Handle '\"'.
599 * ia64-ic.tbl: Updated from SDM 2.2.
600 * ia64-raw.tbl: Likewise.
601 * ia64-waw.tbl: Likewise.
602 * ia64-asmtab.c: Regenerated.
604 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
606 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
607 Anil Paranjape <anilp1@kpitcummins.com>
608 Shilin Shakti <shilins@kpitcummins.com>
610 * xc16x-desc.h: New file
611 * xc16x-desc.c: New file
612 * xc16x-opc.h: New file
613 * xc16x-opc.c: New file
614 * xc16x-ibld.c: New file
615 * xc16x-asm.c: New file
616 * xc16x-dis.c: New file
617 * Makefile.am: Entries for xc16x
618 * Makefile.in: Regenerate
619 * cofigure.in: Add xc16x target information.
620 * configure: Regenerate.
621 * disassemble.c: Add xc16x target information.
623 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
625 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
628 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
630 * i386-dis.c ('Z'): Add a new macro.
631 (dis386_twobyte): Use "movZ" for control register moves.
633 2006-02-10 Nick Clifton <nickc@redhat.com>
635 * iq2000-asm.c: Regenerate.
637 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
639 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
641 2006-01-26 David Ung <davidu@mips.com>
643 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
644 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
645 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
646 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
647 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
649 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
651 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
652 ld_d_r, pref_xd_cb): Use signed char to hold data to be
654 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
655 buffer overflows when disassembling instructions like
657 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
658 operand, if the offset is negative.
660 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
662 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
663 unsigned char to hold data to be disassembled.
665 2006-01-17 Andreas Schwab <schwab@suse.de>
668 * disassemble.c (disassemble_init_for_target): Set
669 disassembler_needs_relocs for bfd_arch_arm.
671 2006-01-16 Paul Brook <paul@codesourcery.com>
673 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
674 f?add?, and f?sub? instructions.
676 2006-01-16 Nick Clifton <nickc@redhat.com>
678 * po/zh_CN.po: New Chinese (simplified) translation.
679 * configure.in (ALL_LINGUAS): Add "zh_CH".
680 * configure: Regenerate.
682 2006-01-05 Paul Brook <paul@codesourcery.com>
684 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
686 2006-01-06 DJ Delorie <dj@redhat.com>
688 * m32c-desc.c: Regenerate.
689 * m32c-opc.c: Regenerate.
690 * m32c-opc.h: Regenerate.
692 2006-01-03 DJ Delorie <dj@redhat.com>
694 * cgen-ibld.in (extract_normal): Avoid memory range errors.
695 * m32c-ibld.c: Regenerated.
697 For older changes see ChangeLog-2005
703 version-control: never