Don't abort for invalid input, print an error message instead.
[binutils.git] / gas / config / tc-ia64.c
blobb9050951f969102055f0fb60ea561b39deb415e6
1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 TODO:
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
45 #include "as.h"
46 #include "dwarf2dbg.h"
47 #include "subsegs.h"
49 #include "opcode/ia64.h"
51 #include "elf/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
56 #define NUM_SLOTS 4
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
62 enum special_section
64 SPECIAL_SECTION_BSS = 0,
65 SPECIAL_SECTION_SBSS,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
73 enum reloc_func
75 FUNC_FPTR_RELATIVE,
76 FUNC_GP_RELATIVE,
77 FUNC_LT_RELATIVE,
78 FUNC_PC_RELATIVE,
79 FUNC_PLT_RELATIVE,
80 FUNC_SEC_RELATIVE,
81 FUNC_SEG_RELATIVE,
82 FUNC_LTV_RELATIVE,
83 FUNC_LT_FPTR_RELATIVE,
86 enum reg_symbol
88 REG_GR = 0,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
95 REG_CFM,
96 REG_PR,
97 REG_PR_ROT,
98 REG_PSR,
99 REG_PSR_L,
100 REG_PSR_UM,
101 /* The following are pseudo-registers for use by gas only. */
102 IND_CPUID,
103 IND_DBR,
104 IND_DTR,
105 IND_ITR,
106 IND_IBR,
107 IND_MEM,
108 IND_MSR,
109 IND_PKR,
110 IND_PMC,
111 IND_PMD,
112 IND_RR,
113 /* The following pseudo-registers are used for unwind directives only: */
114 REG_PSP,
115 REG_PRIUNAT,
116 REG_NUM
119 enum dynreg_type
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
124 DYNREG_NUM_TYPES
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
130 instruction. */
131 struct label_fix
133 struct label_fix *next;
134 struct symbol *sym;
137 extern int target_big_endian;
139 /* Characters which always start a comment. */
140 const char comment_chars[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars[] = "#";
145 /* Characters which may be used to separate multiple commands on a
146 single line. */
147 const char line_separator_chars[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
150 point number. */
151 const char EXP_CHARS[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
154 as in 0d1.0. */
155 const char FLT_CHARS[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts = "m:N:x::";
161 struct option md_longopts[] =
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
169 size_t md_longopts_size = sizeof (md_longopts);
171 static struct
173 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
174 struct hash_control *reg_hash; /* register name hash table */
175 struct hash_control *dynreg_hash; /* dynamic register hash table */
176 struct hash_control *const_hash; /* constant hash table */
177 struct hash_control *entry_hash; /* code entry hint hash table */
179 symbolS *regsym[REG_NUM];
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
184 expressionS qp;
186 unsigned int
187 manual_bundling : 1,
188 debug_dv: 1,
189 detect_dv: 1,
190 explicit_mode : 1, /* which mode we're in */
191 default_explicit_mode : 1, /* which mode is the default */
192 mode_explicitly_set : 1, /* was the current mode explicitly set? */
193 auto_align : 1;
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
198 int curr_slot;
199 int num_slots_in_use;
200 struct slot
202 unsigned int
203 end_of_insn_group : 1,
204 manual_bundling_on : 1,
205 manual_bundling_off : 1;
206 signed char user_template; /* user-selected template, if any */
207 unsigned char qp_regno; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
211 int num_fixups;
212 struct insn_fix
214 bfd_reloc_code_real_type code;
215 enum ia64_opnd opnd; /* type of operand in need of fix */
216 unsigned int is_pcrel : 1; /* is operand pc-relative? */
217 expressionS expr; /* the value to be inserted */
219 fixup[2]; /* at most two fixups per insn */
220 struct ia64_opcode *idesc;
221 struct label_fix *label_fixups;
222 struct label_fix *tag_fixups;
223 struct unw_rec_list *unwind_record; /* Unwind directive. */
224 expressionS opnd[6];
225 char *src_file;
226 unsigned int src_line;
227 struct dwarf2_line_info debug_line;
229 slot[NUM_SLOTS];
231 segT last_text_seg;
233 struct dynreg
235 struct dynreg *next; /* next dynamic register */
236 const char *name;
237 unsigned short base; /* the base register number */
238 unsigned short num_regs; /* # of registers in this set */
240 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
242 flagword flags; /* ELF-header flags */
244 struct mem_offset {
245 unsigned hint:1; /* is this hint currently valid? */
246 bfd_vma offset; /* mem.offset offset */
247 bfd_vma base; /* mem.offset base */
248 } mem_offset;
250 int path; /* number of alt. entry points seen */
251 const char **entry_labels; /* labels of all alternate paths in
252 the current DV-checking block. */
253 int maxpaths; /* size currently allocated for
254 entry_labels */
255 /* Support for hardware errata workarounds. */
257 /* Record data about the last three insn groups. */
258 struct group
260 /* B-step workaround.
261 For each predicate register, this is set if the corresponding insn
262 group conditionally sets this register with one of the affected
263 instructions. */
264 int p_reg_set[64];
265 /* B-step workaround.
266 For each general register, this is set if the corresponding insn
267 a) is conditional one one of the predicate registers for which
268 P_REG_SET is 1 in the corresponding entry of the previous group,
269 b) sets this general register with one of the affected
270 instructions. */
271 int g_reg_set_conditionally[128];
272 } last_groups[3];
273 int group_idx;
277 /* application registers: */
279 #define AR_K0 0
280 #define AR_K7 7
281 #define AR_RSC 16
282 #define AR_BSP 17
283 #define AR_BSPSTORE 18
284 #define AR_RNAT 19
285 #define AR_UNAT 36
286 #define AR_FPSR 40
287 #define AR_ITC 44
288 #define AR_PFS 64
289 #define AR_LC 65
291 static const struct
293 const char *name;
294 int regnum;
296 ar[] =
298 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
299 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
300 {"ar.rsc", 16}, {"ar.bsp", 17},
301 {"ar.bspstore", 18}, {"ar.rnat", 19},
302 {"ar.fcr", 21}, {"ar.eflag", 24},
303 {"ar.csd", 25}, {"ar.ssd", 26},
304 {"ar.cflg", 27}, {"ar.fsr", 28},
305 {"ar.fir", 29}, {"ar.fdr", 30},
306 {"ar.ccv", 32}, {"ar.unat", 36},
307 {"ar.fpsr", 40}, {"ar.itc", 44},
308 {"ar.pfs", 64}, {"ar.lc", 65},
309 {"ar.ec", 66},
312 #define CR_IPSR 16
313 #define CR_ISR 17
314 #define CR_IIP 19
315 #define CR_IFA 20
316 #define CR_ITIR 21
317 #define CR_IIPA 22
318 #define CR_IFS 23
319 #define CR_IIM 24
320 #define CR_IHA 25
321 #define CR_IVR 65
322 #define CR_TPR 66
323 #define CR_EOI 67
324 #define CR_IRR0 68
325 #define CR_IRR3 71
326 #define CR_LRR0 80
327 #define CR_LRR1 81
329 /* control registers: */
330 static const struct
332 const char *name;
333 int regnum;
335 cr[] =
337 {"cr.dcr", 0},
338 {"cr.itm", 1},
339 {"cr.iva", 2},
340 {"cr.pta", 8},
341 {"cr.gpta", 9},
342 {"cr.ipsr", 16},
343 {"cr.isr", 17},
344 {"cr.iip", 19},
345 {"cr.ifa", 20},
346 {"cr.itir", 21},
347 {"cr.iipa", 22},
348 {"cr.ifs", 23},
349 {"cr.iim", 24},
350 {"cr.iha", 25},
351 {"cr.lid", 64},
352 {"cr.ivr", 65},
353 {"cr.tpr", 66},
354 {"cr.eoi", 67},
355 {"cr.irr0", 68},
356 {"cr.irr1", 69},
357 {"cr.irr2", 70},
358 {"cr.irr3", 71},
359 {"cr.itv", 72},
360 {"cr.pmv", 73},
361 {"cr.cmcv", 74},
362 {"cr.lrr0", 80},
363 {"cr.lrr1", 81}
366 #define PSR_MFL 4
367 #define PSR_IC 13
368 #define PSR_DFL 18
369 #define PSR_CPL 32
371 static const struct const_desc
373 const char *name;
374 valueT value;
376 const_bits[] =
378 /* PSR constant masks: */
380 /* 0: reserved */
381 {"psr.be", ((valueT) 1) << 1},
382 {"psr.up", ((valueT) 1) << 2},
383 {"psr.ac", ((valueT) 1) << 3},
384 {"psr.mfl", ((valueT) 1) << 4},
385 {"psr.mfh", ((valueT) 1) << 5},
386 /* 6-12: reserved */
387 {"psr.ic", ((valueT) 1) << 13},
388 {"psr.i", ((valueT) 1) << 14},
389 {"psr.pk", ((valueT) 1) << 15},
390 /* 16: reserved */
391 {"psr.dt", ((valueT) 1) << 17},
392 {"psr.dfl", ((valueT) 1) << 18},
393 {"psr.dfh", ((valueT) 1) << 19},
394 {"psr.sp", ((valueT) 1) << 20},
395 {"psr.pp", ((valueT) 1) << 21},
396 {"psr.di", ((valueT) 1) << 22},
397 {"psr.si", ((valueT) 1) << 23},
398 {"psr.db", ((valueT) 1) << 24},
399 {"psr.lp", ((valueT) 1) << 25},
400 {"psr.tb", ((valueT) 1) << 26},
401 {"psr.rt", ((valueT) 1) << 27},
402 /* 28-31: reserved */
403 /* 32-33: cpl (current privilege level) */
404 {"psr.is", ((valueT) 1) << 34},
405 {"psr.mc", ((valueT) 1) << 35},
406 {"psr.it", ((valueT) 1) << 36},
407 {"psr.id", ((valueT) 1) << 37},
408 {"psr.da", ((valueT) 1) << 38},
409 {"psr.dd", ((valueT) 1) << 39},
410 {"psr.ss", ((valueT) 1) << 40},
411 /* 41-42: ri (restart instruction) */
412 {"psr.ed", ((valueT) 1) << 43},
413 {"psr.bn", ((valueT) 1) << 44},
416 /* indirect register-sets/memory: */
418 static const struct
420 const char *name;
421 int regnum;
423 indirect_reg[] =
425 { "CPUID", IND_CPUID },
426 { "cpuid", IND_CPUID },
427 { "dbr", IND_DBR },
428 { "dtr", IND_DTR },
429 { "itr", IND_ITR },
430 { "ibr", IND_IBR },
431 { "msr", IND_MSR },
432 { "pkr", IND_PKR },
433 { "pmc", IND_PMC },
434 { "pmd", IND_PMD },
435 { "rr", IND_RR },
438 /* Pseudo functions used to indicate relocation types (these functions
439 start with an at sign (@). */
440 static struct
442 const char *name;
443 enum pseudo_type
445 PSEUDO_FUNC_NONE,
446 PSEUDO_FUNC_RELOC,
447 PSEUDO_FUNC_CONST,
448 PSEUDO_FUNC_REG,
449 PSEUDO_FUNC_FLOAT
451 type;
452 union
454 unsigned long ival;
455 symbolS *sym;
459 pseudo_func[] =
461 /* reloc pseudo functions (these must come first!): */
462 { "fptr", PSEUDO_FUNC_RELOC, { 0 } },
463 { "gprel", PSEUDO_FUNC_RELOC, { 0 } },
464 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } },
465 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } },
466 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } },
467 { "secrel", PSEUDO_FUNC_RELOC, { 0 } },
468 { "segrel", PSEUDO_FUNC_RELOC, { 0 } },
469 { "ltv", PSEUDO_FUNC_RELOC, { 0 } },
470 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
472 /* mbtype4 constants: */
473 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
474 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
475 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
476 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
477 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
479 /* fclass constants: */
480 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
481 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
482 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
483 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
484 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
485 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
486 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
487 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
488 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
490 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
492 /* unwind-related constants: */
493 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
494 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
495 { "nt", PSEUDO_FUNC_CONST, { 2 } },
497 /* unwind-related registers: */
498 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
501 /* 41-bit nop opcodes (one per unit): */
502 static const bfd_vma nop[IA64_NUM_UNITS] =
504 0x0000000000LL, /* NIL => break 0 */
505 0x0008000000LL, /* I-unit nop */
506 0x0008000000LL, /* M-unit nop */
507 0x4000000000LL, /* B-unit nop */
508 0x0008000000LL, /* F-unit nop */
509 0x0008000000LL, /* L-"unit" nop */
510 0x0008000000LL, /* X-unit nop */
513 /* Can't be `const' as it's passed to input routines (which have the
514 habit of setting temporary sentinels. */
515 static char special_section_name[][20] =
517 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
518 {".IA_64.unwind"}, {".IA_64.unwind_info"}
521 /* The best template for a particular sequence of up to three
522 instructions: */
523 #define N IA64_NUM_TYPES
524 static unsigned char best_template[N][N][N];
525 #undef N
527 /* Resource dependencies currently in effect */
528 static struct rsrc {
529 int depind; /* dependency index */
530 const struct ia64_dependency *dependency; /* actual dependency */
531 unsigned specific:1, /* is this a specific bit/regno? */
532 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
533 int index; /* specific regno/bit within dependency */
534 int note; /* optional qualifying note (0 if none) */
535 #define STATE_NONE 0
536 #define STATE_STOP 1
537 #define STATE_SRLZ 2
538 int insn_srlz; /* current insn serialization state */
539 int data_srlz; /* current data serialization state */
540 int qp_regno; /* qualifying predicate for this usage */
541 char *file; /* what file marked this dependency */
542 unsigned int line; /* what line marked this dependency */
543 struct mem_offset mem_offset; /* optional memory offset hint */
544 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
545 int path; /* corresponding code entry index */
546 } *regdeps = NULL;
547 static int regdepslen = 0;
548 static int regdepstotlen = 0;
549 static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
550 static const char *dv_sem[] = { "none", "implied", "impliedf",
551 "data", "instr", "specific", "stop", "other" };
552 static const char *dv_cmp_type[] = { "none", "OR", "AND" };
554 /* Current state of PR mutexation */
555 static struct qpmutex {
556 valueT prmask;
557 int path;
558 } *qp_mutexes = NULL; /* QP mutex bitmasks */
559 static int qp_mutexeslen = 0;
560 static int qp_mutexestotlen = 0;
561 static valueT qp_safe_across_calls = 0;
563 /* Current state of PR implications */
564 static struct qp_imply {
565 unsigned p1:6;
566 unsigned p2:6;
567 unsigned p2_branched:1;
568 int path;
569 } *qp_implies = NULL;
570 static int qp_implieslen = 0;
571 static int qp_impliestotlen = 0;
573 /* Keep track of static GR values so that indirect register usage can
574 sometimes be tracked. */
575 static struct gr {
576 unsigned known:1;
577 int path;
578 valueT value;
579 } gr_values[128] = {{ 1, 0, 0 }};
581 /* These are the routines required to output the various types of
582 unwind records. */
584 /* A slot_number is a frag address plus the slot index (0-2). We use the
585 frag address here so that if there is a section switch in the middle of
586 a function, then instructions emitted to a different section are not
587 counted. Since there may be more than one frag for a function, this
588 means we also need to keep track of which frag this address belongs to
589 so we can compute inter-frag distances. This also nicely solves the
590 problem with nops emitted for align directives, which can't easily be
591 counted, but can easily be derived from frag sizes. */
593 typedef struct unw_rec_list {
594 unwind_record r;
595 unsigned long slot_number;
596 fragS *slot_frag;
597 struct unw_rec_list *next;
598 } unw_rec_list;
600 #define SLOT_NUM_NOT_SET (unsigned)-1
602 static struct
604 unsigned long next_slot_number;
605 fragS *next_slot_frag;
607 /* Maintain a list of unwind entries for the current function. */
608 unw_rec_list *list;
609 unw_rec_list *tail;
611 /* Any unwind entires that should be attached to the current slot
612 that an insn is being constructed for. */
613 unw_rec_list *current_entry;
615 /* These are used to create the unwind table entry for this function. */
616 symbolS *proc_start;
617 symbolS *proc_end;
618 symbolS *info; /* pointer to unwind info */
619 symbolS *personality_routine;
621 /* TRUE if processing unwind directives in a prologue region. */
622 int prologue;
623 int prologue_mask;
624 } unwind;
626 typedef void (*vbyte_func) PARAMS ((int, char *, char *));
628 /* Forward delarations: */
629 static int ar_is_in_integer_unit PARAMS ((int regnum));
630 static void set_section PARAMS ((char *name));
631 static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
632 unsigned int, unsigned int));
633 static void dot_radix PARAMS ((int));
634 static void dot_special_section PARAMS ((int));
635 static void dot_proc PARAMS ((int));
636 static void dot_fframe PARAMS ((int));
637 static void dot_vframe PARAMS ((int));
638 static void dot_vframesp PARAMS ((int));
639 static void dot_vframepsp PARAMS ((int));
640 static void dot_save PARAMS ((int));
641 static void dot_restore PARAMS ((int));
642 static void dot_restorereg PARAMS ((int));
643 static void dot_restorereg_p PARAMS ((int));
644 static void dot_handlerdata PARAMS ((int));
645 static void dot_unwentry PARAMS ((int));
646 static void dot_altrp PARAMS ((int));
647 static void dot_savemem PARAMS ((int));
648 static void dot_saveg PARAMS ((int));
649 static void dot_savef PARAMS ((int));
650 static void dot_saveb PARAMS ((int));
651 static void dot_savegf PARAMS ((int));
652 static void dot_spill PARAMS ((int));
653 static void dot_spillreg PARAMS ((int));
654 static void dot_spillmem PARAMS ((int));
655 static void dot_spillreg_p PARAMS ((int));
656 static void dot_spillmem_p PARAMS ((int));
657 static void dot_label_state PARAMS ((int));
658 static void dot_copy_state PARAMS ((int));
659 static void dot_unwabi PARAMS ((int));
660 static void dot_personality PARAMS ((int));
661 static void dot_body PARAMS ((int));
662 static void dot_prologue PARAMS ((int));
663 static void dot_endp PARAMS ((int));
664 static void dot_template PARAMS ((int));
665 static void dot_regstk PARAMS ((int));
666 static void dot_rot PARAMS ((int));
667 static void dot_byteorder PARAMS ((int));
668 static void dot_psr PARAMS ((int));
669 static void dot_alias PARAMS ((int));
670 static void dot_ln PARAMS ((int));
671 static char *parse_section_name PARAMS ((void));
672 static void dot_xdata PARAMS ((int));
673 static void stmt_float_cons PARAMS ((int));
674 static void stmt_cons_ua PARAMS ((int));
675 static void dot_xfloat_cons PARAMS ((int));
676 static void dot_xstringer PARAMS ((int));
677 static void dot_xdata_ua PARAMS ((int));
678 static void dot_xfloat_cons_ua PARAMS ((int));
679 static void print_prmask PARAMS ((valueT mask));
680 static void dot_pred_rel PARAMS ((int));
681 static void dot_reg_val PARAMS ((int));
682 static void dot_dv_mode PARAMS ((int));
683 static void dot_entry PARAMS ((int));
684 static void dot_mem_offset PARAMS ((int));
685 static void add_unwind_entry PARAMS((unw_rec_list *ptr));
686 static symbolS *declare_register PARAMS ((const char *name, int regnum));
687 static void declare_register_set PARAMS ((const char *, int, int));
688 static unsigned int operand_width PARAMS ((enum ia64_opnd));
689 static int operand_match PARAMS ((const struct ia64_opcode *idesc,
690 int index, expressionS *e));
691 static int parse_operand PARAMS ((expressionS *e));
692 static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
693 static void build_insn PARAMS ((struct slot *, bfd_vma *));
694 static void emit_one_bundle PARAMS ((void));
695 static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
696 static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
697 bfd_reloc_code_real_type r_type));
698 static void insn_group_break PARAMS ((int, int, int));
699 static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
700 struct rsrc *, int depind, int path));
701 static void add_qp_mutex PARAMS((valueT mask));
702 static void add_qp_imply PARAMS((int p1, int p2));
703 static void clear_qp_branch_flag PARAMS((valueT mask));
704 static void clear_qp_mutex PARAMS((valueT mask));
705 static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
706 static void clear_register_values PARAMS ((void));
707 static void print_dependency PARAMS ((const char *action, int depind));
708 static void instruction_serialization PARAMS ((void));
709 static void data_serialization PARAMS ((void));
710 static void remove_marked_resource PARAMS ((struct rsrc *));
711 static int is_conditional_branch PARAMS ((struct ia64_opcode *));
712 static int is_taken_branch PARAMS ((struct ia64_opcode *));
713 static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
714 static int depends_on PARAMS ((int, struct ia64_opcode *));
715 static int specify_resource PARAMS ((const struct ia64_dependency *,
716 struct ia64_opcode *, int, struct rsrc [], int, int));
717 static int check_dv PARAMS((struct ia64_opcode *idesc));
718 static void check_dependencies PARAMS((struct ia64_opcode *));
719 static void mark_resources PARAMS((struct ia64_opcode *));
720 static void update_dependencies PARAMS((struct ia64_opcode *));
721 static void note_register_values PARAMS((struct ia64_opcode *));
722 static int qp_mutex PARAMS ((int, int, int));
723 static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
724 static void output_vbyte_mem PARAMS ((int, char *, char *));
725 static void count_output PARAMS ((int, char *, char *));
726 static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
727 static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
728 static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
729 static void output_P1_format PARAMS ((vbyte_func, int));
730 static void output_P2_format PARAMS ((vbyte_func, int, int));
731 static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
732 static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
733 static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
734 static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
735 static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
736 static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
737 static void output_P9_format PARAMS ((vbyte_func, int, int));
738 static void output_P10_format PARAMS ((vbyte_func, int, int));
739 static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
740 static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
741 static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
742 static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
743 static char format_ab_reg PARAMS ((int, int));
744 static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
745 unsigned long));
746 static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
747 static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
748 unsigned long));
749 static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
750 static void free_list_records PARAMS ((unw_rec_list *));
751 static unw_rec_list *output_prologue PARAMS ((void));
752 static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
753 static unw_rec_list *output_body PARAMS ((void));
754 static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
755 static unw_rec_list *output_mem_stack_v PARAMS ((void));
756 static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
757 static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
758 static unw_rec_list *output_rp_when PARAMS ((void));
759 static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
760 static unw_rec_list *output_rp_br PARAMS ((unsigned int));
761 static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
762 static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
763 static unw_rec_list *output_pfs_when PARAMS ((void));
764 static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
765 static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
766 static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
767 static unw_rec_list *output_preds_when PARAMS ((void));
768 static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
769 static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
770 static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
771 static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
772 static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
773 static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
774 static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
775 static unw_rec_list *output_br_mem PARAMS ((unsigned int));
776 static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
777 static unw_rec_list *output_spill_base PARAMS ((unsigned int));
778 static unw_rec_list *output_unat_when PARAMS ((void));
779 static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
780 static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
781 static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
782 static unw_rec_list *output_lc_when PARAMS ((void));
783 static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
784 static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
785 static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
786 static unw_rec_list *output_fpsr_when PARAMS ((void));
787 static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
788 static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
789 static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
790 static unw_rec_list *output_priunat_when_gr PARAMS ((void));
791 static unw_rec_list *output_priunat_when_mem PARAMS ((void));
792 static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
793 static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
794 static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
795 static unw_rec_list *output_bsp_when PARAMS ((void));
796 static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
797 static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
798 static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
799 static unw_rec_list *output_bspstore_when PARAMS ((void));
800 static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
801 static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
802 static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
803 static unw_rec_list *output_rnat_when PARAMS ((void));
804 static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
805 static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
806 static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
807 static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
808 static unw_rec_list *output_epilogue PARAMS ((unsigned long));
809 static unw_rec_list *output_label_state PARAMS ((unsigned long));
810 static unw_rec_list *output_copy_state PARAMS ((unsigned long));
811 static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
812 static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
813 static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
814 unsigned int));
815 static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
816 unsigned int));
817 static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
818 unsigned int));
819 static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
820 unsigned int, unsigned int));
821 static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
822 static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
823 static int calc_record_size PARAMS ((unw_rec_list *));
824 static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
825 static int count_bits PARAMS ((unsigned long));
826 static unsigned long slot_index PARAMS ((unsigned long, fragS *,
827 unsigned long, fragS *));
828 static void fixup_unw_records PARAMS ((unw_rec_list *));
829 static int output_unw_records PARAMS ((unw_rec_list *, void **));
830 static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
831 static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
832 static int generate_unwind_image PARAMS ((void));
834 /* Determine if application register REGNUM resides in the integer
835 unit (as opposed to the memory unit). */
836 static int
837 ar_is_in_integer_unit (reg)
838 int reg;
840 reg -= REG_AR;
842 return (reg == 64 /* pfs */
843 || reg == 65 /* lc */
844 || reg == 66 /* ec */
845 /* ??? ias accepts and puts these in the integer unit. */
846 || (reg >= 112 && reg <= 127));
849 /* Switch to section NAME and create section if necessary. It's
850 rather ugly that we have to manipulate input_line_pointer but I
851 don't see any other way to accomplish the same thing without
852 changing obj-elf.c (which may be the Right Thing, in the end). */
853 static void
854 set_section (name)
855 char *name;
857 char *saved_input_line_pointer;
859 saved_input_line_pointer = input_line_pointer;
860 input_line_pointer = name;
861 obj_elf_section (0);
862 input_line_pointer = saved_input_line_pointer;
865 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
867 flagword
868 ia64_elf_section_flags (flags, attr, type)
869 flagword flags;
870 int attr, type ATTRIBUTE_UNUSED;
872 if (attr & SHF_IA_64_SHORT)
873 flags |= SEC_SMALL_DATA;
874 return flags;
877 static unsigned int
878 set_regstack (ins, locs, outs, rots)
879 unsigned int ins, locs, outs, rots;
881 /* Size of frame. */
882 unsigned int sof;
884 sof = ins + locs + outs;
885 if (sof > 96)
887 as_bad ("Size of frame exceeds maximum of 96 registers");
888 return 0;
890 if (rots > sof)
892 as_warn ("Size of rotating registers exceeds frame size");
893 return 0;
895 md.in.base = REG_GR + 32;
896 md.loc.base = md.in.base + ins;
897 md.out.base = md.loc.base + locs;
899 md.in.num_regs = ins;
900 md.loc.num_regs = locs;
901 md.out.num_regs = outs;
902 md.rot.num_regs = rots;
903 return sof;
906 void
907 ia64_flush_insns ()
909 struct label_fix *lfix;
910 segT saved_seg;
911 subsegT saved_subseg;
912 unw_rec_list *ptr;
914 if (!md.last_text_seg)
915 return;
917 saved_seg = now_seg;
918 saved_subseg = now_subseg;
920 subseg_set (md.last_text_seg, 0);
922 while (md.num_slots_in_use > 0)
923 emit_one_bundle (); /* force out queued instructions */
925 /* In case there are labels following the last instruction, resolve
926 those now: */
927 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
929 S_SET_VALUE (lfix->sym, frag_now_fix ());
930 symbol_set_frag (lfix->sym, frag_now);
932 CURR_SLOT.label_fixups = 0;
933 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
935 S_SET_VALUE (lfix->sym, frag_now_fix ());
936 symbol_set_frag (lfix->sym, frag_now);
938 CURR_SLOT.tag_fixups = 0;
940 /* In case there are unwind directives following the last instruction,
941 resolve those now. We only handle body and prologue directives here.
942 Give an error for others. */
943 for (ptr = unwind.current_entry; ptr; ptr = ptr->next)
945 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
946 || ptr->r.type == body)
948 ptr->slot_number = (unsigned long) frag_more (0);
949 ptr->slot_frag = frag_now;
951 else
952 as_bad (_("Unwind directive not followed by an instruction."));
954 unwind.current_entry = NULL;
956 subseg_set (saved_seg, saved_subseg);
958 if (md.qp.X_op == O_register)
959 as_bad ("qualifying predicate not followed by instruction");
962 void
963 ia64_do_align (nbytes)
964 int nbytes;
966 char *saved_input_line_pointer = input_line_pointer;
968 input_line_pointer = "";
969 s_align_bytes (nbytes);
970 input_line_pointer = saved_input_line_pointer;
973 void
974 ia64_cons_align (nbytes)
975 int nbytes;
977 if (md.auto_align)
979 char *saved_input_line_pointer = input_line_pointer;
980 input_line_pointer = "";
981 s_align_bytes (nbytes);
982 input_line_pointer = saved_input_line_pointer;
986 /* Output COUNT bytes to a memory location. */
987 static unsigned char *vbyte_mem_ptr = NULL;
989 void
990 output_vbyte_mem (count, ptr, comment)
991 int count;
992 char *ptr;
993 char *comment ATTRIBUTE_UNUSED;
995 int x;
996 if (vbyte_mem_ptr == NULL)
997 abort ();
999 if (count == 0)
1000 return;
1001 for (x = 0; x < count; x++)
1002 *(vbyte_mem_ptr++) = ptr[x];
1005 /* Count the number of bytes required for records. */
1006 static int vbyte_count = 0;
1007 void
1008 count_output (count, ptr, comment)
1009 int count;
1010 char *ptr ATTRIBUTE_UNUSED;
1011 char *comment ATTRIBUTE_UNUSED;
1013 vbyte_count += count;
1016 static void
1017 output_R1_format (f, rtype, rlen)
1018 vbyte_func f;
1019 unw_record_type rtype;
1020 int rlen;
1022 int r = 0;
1023 char byte;
1024 if (rlen > 0x1f)
1026 output_R3_format (f, rtype, rlen);
1027 return;
1030 if (rtype == body)
1031 r = 1;
1032 else if (rtype != prologue)
1033 as_bad ("record type is not valid");
1035 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
1036 (*f) (1, &byte, NULL);
1039 static void
1040 output_R2_format (f, mask, grsave, rlen)
1041 vbyte_func f;
1042 int mask, grsave;
1043 unsigned long rlen;
1045 char bytes[20];
1046 int count = 2;
1047 mask = (mask & 0x0f);
1048 grsave = (grsave & 0x7f);
1050 bytes[0] = (UNW_R2 | (mask >> 1));
1051 bytes[1] = (((mask & 0x01) << 7) | grsave);
1052 count += output_leb128 (bytes + 2, rlen, 0);
1053 (*f) (count, bytes, NULL);
1056 static void
1057 output_R3_format (f, rtype, rlen)
1058 vbyte_func f;
1059 unw_record_type rtype;
1060 unsigned long rlen;
1062 int r = 0, count;
1063 char bytes[20];
1064 if (rlen <= 0x1f)
1066 output_R1_format (f, rtype, rlen);
1067 return;
1070 if (rtype == body)
1071 r = 1;
1072 else if (rtype != prologue)
1073 as_bad ("record type is not valid");
1074 bytes[0] = (UNW_R3 | r);
1075 count = output_leb128 (bytes + 1, rlen, 0);
1076 (*f) (count + 1, bytes, NULL);
1079 static void
1080 output_P1_format (f, brmask)
1081 vbyte_func f;
1082 int brmask;
1084 char byte;
1085 byte = UNW_P1 | (brmask & 0x1f);
1086 (*f) (1, &byte, NULL);
1089 static void
1090 output_P2_format (f, brmask, gr)
1091 vbyte_func f;
1092 int brmask;
1093 int gr;
1095 char bytes[2];
1096 brmask = (brmask & 0x1f);
1097 bytes[0] = UNW_P2 | (brmask >> 1);
1098 bytes[1] = (((brmask & 1) << 7) | gr);
1099 (*f) (2, bytes, NULL);
1102 static void
1103 output_P3_format (f, rtype, reg)
1104 vbyte_func f;
1105 unw_record_type rtype;
1106 int reg;
1108 char bytes[2];
1109 int r = 0;
1110 reg = (reg & 0x7f);
1111 switch (rtype)
1113 case psp_gr:
1114 r = 0;
1115 break;
1116 case rp_gr:
1117 r = 1;
1118 break;
1119 case pfs_gr:
1120 r = 2;
1121 break;
1122 case preds_gr:
1123 r = 3;
1124 break;
1125 case unat_gr:
1126 r = 4;
1127 break;
1128 case lc_gr:
1129 r = 5;
1130 break;
1131 case rp_br:
1132 r = 6;
1133 break;
1134 case rnat_gr:
1135 r = 7;
1136 break;
1137 case bsp_gr:
1138 r = 8;
1139 break;
1140 case bspstore_gr:
1141 r = 9;
1142 break;
1143 case fpsr_gr:
1144 r = 10;
1145 break;
1146 case priunat_gr:
1147 r = 11;
1148 break;
1149 default:
1150 as_bad ("Invalid record type for P3 format.");
1152 bytes[0] = (UNW_P3 | (r >> 1));
1153 bytes[1] = (((r & 1) << 7) | reg);
1154 (*f) (2, bytes, NULL);
1157 static void
1158 output_P4_format (f, imask, imask_size)
1159 vbyte_func f;
1160 unsigned char *imask;
1161 unsigned long imask_size;
1163 imask[0] = UNW_P4;
1164 (*f) (imask_size, imask, NULL);
1167 static void
1168 output_P5_format (f, grmask, frmask)
1169 vbyte_func f;
1170 int grmask;
1171 unsigned long frmask;
1173 char bytes[4];
1174 grmask = (grmask & 0x0f);
1176 bytes[0] = UNW_P5;
1177 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1178 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1179 bytes[3] = (frmask & 0x000000ff);
1180 (*f) (4, bytes, NULL);
1183 static void
1184 output_P6_format (f, rtype, rmask)
1185 vbyte_func f;
1186 unw_record_type rtype;
1187 int rmask;
1189 char byte;
1190 int r = 0;
1192 if (rtype == gr_mem)
1193 r = 1;
1194 else if (rtype != fr_mem)
1195 as_bad ("Invalid record type for format P6");
1196 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1197 (*f) (1, &byte, NULL);
1200 static void
1201 output_P7_format (f, rtype, w1, w2)
1202 vbyte_func f;
1203 unw_record_type rtype;
1204 unsigned long w1;
1205 unsigned long w2;
1207 char bytes[20];
1208 int count = 1;
1209 int r = 0;
1210 count += output_leb128 (bytes + 1, w1, 0);
1211 switch (rtype)
1213 case mem_stack_f:
1214 r = 0;
1215 count += output_leb128 (bytes + count, w2 >> 4, 0);
1216 break;
1217 case mem_stack_v:
1218 r = 1;
1219 break;
1220 case spill_base:
1221 r = 2;
1222 break;
1223 case psp_sprel:
1224 r = 3;
1225 break;
1226 case rp_when:
1227 r = 4;
1228 break;
1229 case rp_psprel:
1230 r = 5;
1231 break;
1232 case pfs_when:
1233 r = 6;
1234 break;
1235 case pfs_psprel:
1236 r = 7;
1237 break;
1238 case preds_when:
1239 r = 8;
1240 break;
1241 case preds_psprel:
1242 r = 9;
1243 break;
1244 case lc_when:
1245 r = 10;
1246 break;
1247 case lc_psprel:
1248 r = 11;
1249 break;
1250 case unat_when:
1251 r = 12;
1252 break;
1253 case unat_psprel:
1254 r = 13;
1255 break;
1256 case fpsr_when:
1257 r = 14;
1258 break;
1259 case fpsr_psprel:
1260 r = 15;
1261 break;
1262 default:
1263 break;
1265 bytes[0] = (UNW_P7 | r);
1266 (*f) (count, bytes, NULL);
1269 static void
1270 output_P8_format (f, rtype, t)
1271 vbyte_func f;
1272 unw_record_type rtype;
1273 unsigned long t;
1275 char bytes[20];
1276 int r = 0;
1277 int count = 2;
1278 bytes[0] = UNW_P8;
1279 switch (rtype)
1281 case rp_sprel:
1282 r = 1;
1283 break;
1284 case pfs_sprel:
1285 r = 2;
1286 break;
1287 case preds_sprel:
1288 r = 3;
1289 break;
1290 case lc_sprel:
1291 r = 4;
1292 break;
1293 case unat_sprel:
1294 r = 5;
1295 break;
1296 case fpsr_sprel:
1297 r = 6;
1298 break;
1299 case bsp_when:
1300 r = 7;
1301 break;
1302 case bsp_psprel:
1303 r = 8;
1304 break;
1305 case bsp_sprel:
1306 r = 9;
1307 break;
1308 case bspstore_when:
1309 r = 10;
1310 break;
1311 case bspstore_psprel:
1312 r = 11;
1313 break;
1314 case bspstore_sprel:
1315 r = 12;
1316 break;
1317 case rnat_when:
1318 r = 13;
1319 break;
1320 case rnat_psprel:
1321 r = 14;
1322 break;
1323 case rnat_sprel:
1324 r = 15;
1325 break;
1326 case priunat_when_gr:
1327 r = 16;
1328 break;
1329 case priunat_psprel:
1330 r = 17;
1331 break;
1332 case priunat_sprel:
1333 r = 18;
1334 break;
1335 case priunat_when_mem:
1336 r = 19;
1337 break;
1338 default:
1339 break;
1341 bytes[1] = r;
1342 count += output_leb128 (bytes + 2, t, 0);
1343 (*f) (count, bytes, NULL);
1346 static void
1347 output_P9_format (f, grmask, gr)
1348 vbyte_func f;
1349 int grmask;
1350 int gr;
1352 char bytes[3];
1353 bytes[0] = UNW_P9;
1354 bytes[1] = (grmask & 0x0f);
1355 bytes[2] = (gr & 0x7f);
1356 (*f) (3, bytes, NULL);
1359 static void
1360 output_P10_format (f, abi, context)
1361 vbyte_func f;
1362 int abi;
1363 int context;
1365 char bytes[3];
1366 bytes[0] = UNW_P10;
1367 bytes[1] = (abi & 0xff);
1368 bytes[2] = (context & 0xff);
1369 (*f) (3, bytes, NULL);
1372 static void
1373 output_B1_format (f, rtype, label)
1374 vbyte_func f;
1375 unw_record_type rtype;
1376 unsigned long label;
1378 char byte;
1379 int r = 0;
1380 if (label > 0x1f)
1382 output_B4_format (f, rtype, label);
1383 return;
1385 if (rtype == copy_state)
1386 r = 1;
1387 else if (rtype != label_state)
1388 as_bad ("Invalid record type for format B1");
1390 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1391 (*f) (1, &byte, NULL);
1394 static void
1395 output_B2_format (f, ecount, t)
1396 vbyte_func f;
1397 unsigned long ecount;
1398 unsigned long t;
1400 char bytes[20];
1401 int count = 1;
1402 if (ecount > 0x1f)
1404 output_B3_format (f, ecount, t);
1405 return;
1407 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1408 count += output_leb128 (bytes + 1, t, 0);
1409 (*f) (count, bytes, NULL);
1412 static void
1413 output_B3_format (f, ecount, t)
1414 vbyte_func f;
1415 unsigned long ecount;
1416 unsigned long t;
1418 char bytes[20];
1419 int count = 1;
1420 if (ecount <= 0x1f)
1422 output_B2_format (f, ecount, t);
1423 return;
1425 bytes[0] = UNW_B3;
1426 count += output_leb128 (bytes + 1, t, 0);
1427 count += output_leb128 (bytes + count, ecount, 0);
1428 (*f) (count, bytes, NULL);
1431 static void
1432 output_B4_format (f, rtype, label)
1433 vbyte_func f;
1434 unw_record_type rtype;
1435 unsigned long label;
1437 char bytes[20];
1438 int r = 0;
1439 int count = 1;
1440 if (label <= 0x1f)
1442 output_B1_format (f, rtype, label);
1443 return;
1446 if (rtype == copy_state)
1447 r = 1;
1448 else if (rtype != label_state)
1449 as_bad ("Invalid record type for format B1");
1451 bytes[0] = (UNW_B4 | (r << 3));
1452 count += output_leb128 (bytes + 1, label, 0);
1453 (*f) (count, bytes, NULL);
1456 static char
1457 format_ab_reg (ab, reg)
1458 int ab;
1459 int reg;
1461 int ret;
1462 ab = (ab & 3);
1463 reg = (reg & 0x1f);
1464 ret = (ab << 5) | reg;
1465 return ret;
1468 static void
1469 output_X1_format (f, rtype, ab, reg, t, w1)
1470 vbyte_func f;
1471 unw_record_type rtype;
1472 int ab, reg;
1473 unsigned long t;
1474 unsigned long w1;
1476 char bytes[20];
1477 int r = 0;
1478 int count = 2;
1479 bytes[0] = UNW_X1;
1481 if (rtype == spill_sprel)
1482 r = 1;
1483 else if (rtype != spill_psprel)
1484 as_bad ("Invalid record type for format X1");
1485 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
1486 count += output_leb128 (bytes + 2, t, 0);
1487 count += output_leb128 (bytes + count, w1, 0);
1488 (*f) (count, bytes, NULL);
1491 static void
1492 output_X2_format (f, ab, reg, x, y, treg, t)
1493 vbyte_func f;
1494 int ab, reg;
1495 int x, y, treg;
1496 unsigned long t;
1498 char bytes[20];
1499 int count = 3;
1500 bytes[0] = UNW_X2;
1501 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1502 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1503 count += output_leb128 (bytes + 3, t, 0);
1504 (*f) (count, bytes, NULL);
1507 static void
1508 output_X3_format (f, rtype, qp, ab, reg, t, w1)
1509 vbyte_func f;
1510 unw_record_type rtype;
1511 int qp;
1512 int ab, reg;
1513 unsigned long t;
1514 unsigned long w1;
1516 char bytes[20];
1517 int r = 0;
1518 int count = 3;
1519 bytes[0] = UNW_X3;
1521 if (rtype == spill_sprel_p)
1522 r = 1;
1523 else if (rtype != spill_psprel_p)
1524 as_bad ("Invalid record type for format X3");
1525 bytes[1] = ((r << 7) | (qp & 0x3f));
1526 bytes[2] = format_ab_reg (ab, reg);
1527 count += output_leb128 (bytes + 3, t, 0);
1528 count += output_leb128 (bytes + count, w1, 0);
1529 (*f) (count, bytes, NULL);
1532 static void
1533 output_X4_format (f, qp, ab, reg, x, y, treg, t)
1534 vbyte_func f;
1535 int qp;
1536 int ab, reg;
1537 int x, y, treg;
1538 unsigned long t;
1540 char bytes[20];
1541 int count = 4;
1542 bytes[0] = UNW_X4;
1543 bytes[1] = (qp & 0x3f);
1544 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1545 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1546 count += output_leb128 (bytes + 4, t, 0);
1547 (*f) (count, bytes, NULL);
1550 /* This function allocates a record list structure, and initializes fields. */
1552 static unw_rec_list *
1553 alloc_record (unw_record_type t)
1555 unw_rec_list *ptr;
1556 ptr = xmalloc (sizeof (*ptr));
1557 ptr->next = NULL;
1558 ptr->slot_number = SLOT_NUM_NOT_SET;
1559 ptr->r.type = t;
1560 return ptr;
1563 /* This function frees an entire list of record structures. */
1565 void
1566 free_list_records (unw_rec_list *first)
1568 unw_rec_list *ptr;
1569 for (ptr = first; ptr != NULL;)
1571 unw_rec_list *tmp = ptr;
1573 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1574 && tmp->r.record.r.mask.i)
1575 free (tmp->r.record.r.mask.i);
1577 ptr = ptr->next;
1578 free (tmp);
1582 static unw_rec_list *
1583 output_prologue ()
1585 unw_rec_list *ptr = alloc_record (prologue);
1586 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1587 return ptr;
1590 static unw_rec_list *
1591 output_prologue_gr (saved_mask, reg)
1592 unsigned int saved_mask;
1593 unsigned int reg;
1595 unw_rec_list *ptr = alloc_record (prologue_gr);
1596 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1597 ptr->r.record.r.grmask = saved_mask;
1598 ptr->r.record.r.grsave = reg;
1599 return ptr;
1602 static unw_rec_list *
1603 output_body ()
1605 unw_rec_list *ptr = alloc_record (body);
1606 return ptr;
1609 static unw_rec_list *
1610 output_mem_stack_f (size)
1611 unsigned int size;
1613 unw_rec_list *ptr = alloc_record (mem_stack_f);
1614 ptr->r.record.p.size = size;
1615 return ptr;
1618 static unw_rec_list *
1619 output_mem_stack_v ()
1621 unw_rec_list *ptr = alloc_record (mem_stack_v);
1622 return ptr;
1625 static unw_rec_list *
1626 output_psp_gr (gr)
1627 unsigned int gr;
1629 unw_rec_list *ptr = alloc_record (psp_gr);
1630 ptr->r.record.p.gr = gr;
1631 return ptr;
1634 static unw_rec_list *
1635 output_psp_sprel (offset)
1636 unsigned int offset;
1638 unw_rec_list *ptr = alloc_record (psp_sprel);
1639 ptr->r.record.p.spoff = offset / 4;
1640 return ptr;
1643 static unw_rec_list *
1644 output_rp_when ()
1646 unw_rec_list *ptr = alloc_record (rp_when);
1647 return ptr;
1650 static unw_rec_list *
1651 output_rp_gr (gr)
1652 unsigned int gr;
1654 unw_rec_list *ptr = alloc_record (rp_gr);
1655 ptr->r.record.p.gr = gr;
1656 return ptr;
1659 static unw_rec_list *
1660 output_rp_br (br)
1661 unsigned int br;
1663 unw_rec_list *ptr = alloc_record (rp_br);
1664 ptr->r.record.p.br = br;
1665 return ptr;
1668 static unw_rec_list *
1669 output_rp_psprel (offset)
1670 unsigned int offset;
1672 unw_rec_list *ptr = alloc_record (rp_psprel);
1673 ptr->r.record.p.pspoff = offset / 4;
1674 return ptr;
1677 static unw_rec_list *
1678 output_rp_sprel (offset)
1679 unsigned int offset;
1681 unw_rec_list *ptr = alloc_record (rp_sprel);
1682 ptr->r.record.p.spoff = offset / 4;
1683 return ptr;
1686 static unw_rec_list *
1687 output_pfs_when ()
1689 unw_rec_list *ptr = alloc_record (pfs_when);
1690 return ptr;
1693 static unw_rec_list *
1694 output_pfs_gr (gr)
1695 unsigned int gr;
1697 unw_rec_list *ptr = alloc_record (pfs_gr);
1698 ptr->r.record.p.gr = gr;
1699 return ptr;
1702 static unw_rec_list *
1703 output_pfs_psprel (offset)
1704 unsigned int offset;
1706 unw_rec_list *ptr = alloc_record (pfs_psprel);
1707 ptr->r.record.p.pspoff = offset / 4;
1708 return ptr;
1711 static unw_rec_list *
1712 output_pfs_sprel (offset)
1713 unsigned int offset;
1715 unw_rec_list *ptr = alloc_record (pfs_sprel);
1716 ptr->r.record.p.spoff = offset / 4;
1717 return ptr;
1720 static unw_rec_list *
1721 output_preds_when ()
1723 unw_rec_list *ptr = alloc_record (preds_when);
1724 return ptr;
1727 static unw_rec_list *
1728 output_preds_gr (gr)
1729 unsigned int gr;
1731 unw_rec_list *ptr = alloc_record (preds_gr);
1732 ptr->r.record.p.gr = gr;
1733 return ptr;
1736 static unw_rec_list *
1737 output_preds_psprel (offset)
1738 unsigned int offset;
1740 unw_rec_list *ptr = alloc_record (preds_psprel);
1741 ptr->r.record.p.pspoff = offset / 4;
1742 return ptr;
1745 static unw_rec_list *
1746 output_preds_sprel (offset)
1747 unsigned int offset;
1749 unw_rec_list *ptr = alloc_record (preds_sprel);
1750 ptr->r.record.p.spoff = offset / 4;
1751 return ptr;
1754 static unw_rec_list *
1755 output_fr_mem (mask)
1756 unsigned int mask;
1758 unw_rec_list *ptr = alloc_record (fr_mem);
1759 ptr->r.record.p.rmask = mask;
1760 return ptr;
1763 static unw_rec_list *
1764 output_frgr_mem (gr_mask, fr_mask)
1765 unsigned int gr_mask;
1766 unsigned int fr_mask;
1768 unw_rec_list *ptr = alloc_record (frgr_mem);
1769 ptr->r.record.p.grmask = gr_mask;
1770 ptr->r.record.p.frmask = fr_mask;
1771 return ptr;
1774 static unw_rec_list *
1775 output_gr_gr (mask, reg)
1776 unsigned int mask;
1777 unsigned int reg;
1779 unw_rec_list *ptr = alloc_record (gr_gr);
1780 ptr->r.record.p.grmask = mask;
1781 ptr->r.record.p.gr = reg;
1782 return ptr;
1785 static unw_rec_list *
1786 output_gr_mem (mask)
1787 unsigned int mask;
1789 unw_rec_list *ptr = alloc_record (gr_mem);
1790 ptr->r.record.p.rmask = mask;
1791 return ptr;
1794 static unw_rec_list *
1795 output_br_mem (unsigned int mask)
1797 unw_rec_list *ptr = alloc_record (br_mem);
1798 ptr->r.record.p.brmask = mask;
1799 return ptr;
1802 static unw_rec_list *
1803 output_br_gr (save_mask, reg)
1804 unsigned int save_mask;
1805 unsigned int reg;
1807 unw_rec_list *ptr = alloc_record (br_gr);
1808 ptr->r.record.p.brmask = save_mask;
1809 ptr->r.record.p.gr = reg;
1810 return ptr;
1813 static unw_rec_list *
1814 output_spill_base (offset)
1815 unsigned int offset;
1817 unw_rec_list *ptr = alloc_record (spill_base);
1818 ptr->r.record.p.pspoff = offset / 4;
1819 return ptr;
1822 static unw_rec_list *
1823 output_unat_when ()
1825 unw_rec_list *ptr = alloc_record (unat_when);
1826 return ptr;
1829 static unw_rec_list *
1830 output_unat_gr (gr)
1831 unsigned int gr;
1833 unw_rec_list *ptr = alloc_record (unat_gr);
1834 ptr->r.record.p.gr = gr;
1835 return ptr;
1838 static unw_rec_list *
1839 output_unat_psprel (offset)
1840 unsigned int offset;
1842 unw_rec_list *ptr = alloc_record (unat_psprel);
1843 ptr->r.record.p.pspoff = offset / 4;
1844 return ptr;
1847 static unw_rec_list *
1848 output_unat_sprel (offset)
1849 unsigned int offset;
1851 unw_rec_list *ptr = alloc_record (unat_sprel);
1852 ptr->r.record.p.spoff = offset / 4;
1853 return ptr;
1856 static unw_rec_list *
1857 output_lc_when ()
1859 unw_rec_list *ptr = alloc_record (lc_when);
1860 return ptr;
1863 static unw_rec_list *
1864 output_lc_gr (gr)
1865 unsigned int gr;
1867 unw_rec_list *ptr = alloc_record (lc_gr);
1868 ptr->r.record.p.gr = gr;
1869 return ptr;
1872 static unw_rec_list *
1873 output_lc_psprel (offset)
1874 unsigned int offset;
1876 unw_rec_list *ptr = alloc_record (lc_psprel);
1877 ptr->r.record.p.pspoff = offset / 4;
1878 return ptr;
1881 static unw_rec_list *
1882 output_lc_sprel (offset)
1883 unsigned int offset;
1885 unw_rec_list *ptr = alloc_record (lc_sprel);
1886 ptr->r.record.p.spoff = offset / 4;
1887 return ptr;
1890 static unw_rec_list *
1891 output_fpsr_when ()
1893 unw_rec_list *ptr = alloc_record (fpsr_when);
1894 return ptr;
1897 static unw_rec_list *
1898 output_fpsr_gr (gr)
1899 unsigned int gr;
1901 unw_rec_list *ptr = alloc_record (fpsr_gr);
1902 ptr->r.record.p.gr = gr;
1903 return ptr;
1906 static unw_rec_list *
1907 output_fpsr_psprel (offset)
1908 unsigned int offset;
1910 unw_rec_list *ptr = alloc_record (fpsr_psprel);
1911 ptr->r.record.p.pspoff = offset / 4;
1912 return ptr;
1915 static unw_rec_list *
1916 output_fpsr_sprel (offset)
1917 unsigned int offset;
1919 unw_rec_list *ptr = alloc_record (fpsr_sprel);
1920 ptr->r.record.p.spoff = offset / 4;
1921 return ptr;
1924 static unw_rec_list *
1925 output_priunat_when_gr ()
1927 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1928 return ptr;
1931 static unw_rec_list *
1932 output_priunat_when_mem ()
1934 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1935 return ptr;
1938 static unw_rec_list *
1939 output_priunat_gr (gr)
1940 unsigned int gr;
1942 unw_rec_list *ptr = alloc_record (priunat_gr);
1943 ptr->r.record.p.gr = gr;
1944 return ptr;
1947 static unw_rec_list *
1948 output_priunat_psprel (offset)
1949 unsigned int offset;
1951 unw_rec_list *ptr = alloc_record (priunat_psprel);
1952 ptr->r.record.p.pspoff = offset / 4;
1953 return ptr;
1956 static unw_rec_list *
1957 output_priunat_sprel (offset)
1958 unsigned int offset;
1960 unw_rec_list *ptr = alloc_record (priunat_sprel);
1961 ptr->r.record.p.spoff = offset / 4;
1962 return ptr;
1965 static unw_rec_list *
1966 output_bsp_when ()
1968 unw_rec_list *ptr = alloc_record (bsp_when);
1969 return ptr;
1972 static unw_rec_list *
1973 output_bsp_gr (gr)
1974 unsigned int gr;
1976 unw_rec_list *ptr = alloc_record (bsp_gr);
1977 ptr->r.record.p.gr = gr;
1978 return ptr;
1981 static unw_rec_list *
1982 output_bsp_psprel (offset)
1983 unsigned int offset;
1985 unw_rec_list *ptr = alloc_record (bsp_psprel);
1986 ptr->r.record.p.pspoff = offset / 4;
1987 return ptr;
1990 static unw_rec_list *
1991 output_bsp_sprel (offset)
1992 unsigned int offset;
1994 unw_rec_list *ptr = alloc_record (bsp_sprel);
1995 ptr->r.record.p.spoff = offset / 4;
1996 return ptr;
1999 static unw_rec_list *
2000 output_bspstore_when ()
2002 unw_rec_list *ptr = alloc_record (bspstore_when);
2003 return ptr;
2006 static unw_rec_list *
2007 output_bspstore_gr (gr)
2008 unsigned int gr;
2010 unw_rec_list *ptr = alloc_record (bspstore_gr);
2011 ptr->r.record.p.gr = gr;
2012 return ptr;
2015 static unw_rec_list *
2016 output_bspstore_psprel (offset)
2017 unsigned int offset;
2019 unw_rec_list *ptr = alloc_record (bspstore_psprel);
2020 ptr->r.record.p.pspoff = offset / 4;
2021 return ptr;
2024 static unw_rec_list *
2025 output_bspstore_sprel (offset)
2026 unsigned int offset;
2028 unw_rec_list *ptr = alloc_record (bspstore_sprel);
2029 ptr->r.record.p.spoff = offset / 4;
2030 return ptr;
2033 static unw_rec_list *
2034 output_rnat_when ()
2036 unw_rec_list *ptr = alloc_record (rnat_when);
2037 return ptr;
2040 static unw_rec_list *
2041 output_rnat_gr (gr)
2042 unsigned int gr;
2044 unw_rec_list *ptr = alloc_record (rnat_gr);
2045 ptr->r.record.p.gr = gr;
2046 return ptr;
2049 static unw_rec_list *
2050 output_rnat_psprel (offset)
2051 unsigned int offset;
2053 unw_rec_list *ptr = alloc_record (rnat_psprel);
2054 ptr->r.record.p.pspoff = offset / 4;
2055 return ptr;
2058 static unw_rec_list *
2059 output_rnat_sprel (offset)
2060 unsigned int offset;
2062 unw_rec_list *ptr = alloc_record (rnat_sprel);
2063 ptr->r.record.p.spoff = offset / 4;
2064 return ptr;
2067 static unw_rec_list *
2068 output_unwabi (abi, context)
2069 unsigned long abi;
2070 unsigned long context;
2072 unw_rec_list *ptr = alloc_record (unwabi);
2073 ptr->r.record.p.abi = abi;
2074 ptr->r.record.p.context = context;
2075 return ptr;
2078 static unw_rec_list *
2079 output_epilogue (unsigned long ecount)
2081 unw_rec_list *ptr = alloc_record (epilogue);
2082 ptr->r.record.b.ecount = ecount;
2083 return ptr;
2086 static unw_rec_list *
2087 output_label_state (unsigned long label)
2089 unw_rec_list *ptr = alloc_record (label_state);
2090 ptr->r.record.b.label = label;
2091 return ptr;
2094 static unw_rec_list *
2095 output_copy_state (unsigned long label)
2097 unw_rec_list *ptr = alloc_record (copy_state);
2098 ptr->r.record.b.label = label;
2099 return ptr;
2102 static unw_rec_list *
2103 output_spill_psprel (ab, reg, offset)
2104 unsigned int ab;
2105 unsigned int reg;
2106 unsigned int offset;
2108 unw_rec_list *ptr = alloc_record (spill_psprel);
2109 ptr->r.record.x.ab = ab;
2110 ptr->r.record.x.reg = reg;
2111 ptr->r.record.x.pspoff = offset / 4;
2112 return ptr;
2115 static unw_rec_list *
2116 output_spill_sprel (ab, reg, offset)
2117 unsigned int ab;
2118 unsigned int reg;
2119 unsigned int offset;
2121 unw_rec_list *ptr = alloc_record (spill_sprel);
2122 ptr->r.record.x.ab = ab;
2123 ptr->r.record.x.reg = reg;
2124 ptr->r.record.x.spoff = offset / 4;
2125 return ptr;
2128 static unw_rec_list *
2129 output_spill_psprel_p (ab, reg, offset, predicate)
2130 unsigned int ab;
2131 unsigned int reg;
2132 unsigned int offset;
2133 unsigned int predicate;
2135 unw_rec_list *ptr = alloc_record (spill_psprel_p);
2136 ptr->r.record.x.ab = ab;
2137 ptr->r.record.x.reg = reg;
2138 ptr->r.record.x.pspoff = offset / 4;
2139 ptr->r.record.x.qp = predicate;
2140 return ptr;
2143 static unw_rec_list *
2144 output_spill_sprel_p (ab, reg, offset, predicate)
2145 unsigned int ab;
2146 unsigned int reg;
2147 unsigned int offset;
2148 unsigned int predicate;
2150 unw_rec_list *ptr = alloc_record (spill_sprel_p);
2151 ptr->r.record.x.ab = ab;
2152 ptr->r.record.x.reg = reg;
2153 ptr->r.record.x.spoff = offset / 4;
2154 ptr->r.record.x.qp = predicate;
2155 return ptr;
2158 static unw_rec_list *
2159 output_spill_reg (ab, reg, targ_reg, xy)
2160 unsigned int ab;
2161 unsigned int reg;
2162 unsigned int targ_reg;
2163 unsigned int xy;
2165 unw_rec_list *ptr = alloc_record (spill_reg);
2166 ptr->r.record.x.ab = ab;
2167 ptr->r.record.x.reg = reg;
2168 ptr->r.record.x.treg = targ_reg;
2169 ptr->r.record.x.xy = xy;
2170 return ptr;
2173 static unw_rec_list *
2174 output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2175 unsigned int ab;
2176 unsigned int reg;
2177 unsigned int targ_reg;
2178 unsigned int xy;
2179 unsigned int predicate;
2181 unw_rec_list *ptr = alloc_record (spill_reg_p);
2182 ptr->r.record.x.ab = ab;
2183 ptr->r.record.x.reg = reg;
2184 ptr->r.record.x.treg = targ_reg;
2185 ptr->r.record.x.xy = xy;
2186 ptr->r.record.x.qp = predicate;
2187 return ptr;
2190 /* Given a unw_rec_list process the correct format with the
2191 specified function. */
2193 static void
2194 process_one_record (ptr, f)
2195 unw_rec_list *ptr;
2196 vbyte_func f;
2198 unsigned long fr_mask, gr_mask;
2200 switch (ptr->r.type)
2202 case gr_mem:
2203 case fr_mem:
2204 case br_mem:
2205 case frgr_mem:
2206 /* These are taken care of by prologue/prologue_gr. */
2207 break;
2209 case prologue_gr:
2210 case prologue:
2211 if (ptr->r.type == prologue_gr)
2212 output_R2_format (f, ptr->r.record.r.grmask,
2213 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2214 else
2215 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2217 /* Output descriptor(s) for union of register spills (if any). */
2218 gr_mask = ptr->r.record.r.mask.gr_mem;
2219 fr_mask = ptr->r.record.r.mask.fr_mem;
2220 if (fr_mask)
2222 if ((fr_mask & ~0xfUL) == 0)
2223 output_P6_format (f, fr_mem, fr_mask);
2224 else
2226 output_P5_format (f, gr_mask, fr_mask);
2227 gr_mask = 0;
2230 if (gr_mask)
2231 output_P6_format (f, gr_mem, gr_mask);
2232 if (ptr->r.record.r.mask.br_mem)
2233 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2235 /* output imask descriptor if necessary: */
2236 if (ptr->r.record.r.mask.i)
2237 output_P4_format (f, ptr->r.record.r.mask.i,
2238 ptr->r.record.r.imask_size);
2239 break;
2241 case body:
2242 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2243 break;
2244 case mem_stack_f:
2245 case mem_stack_v:
2246 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2247 ptr->r.record.p.size);
2248 break;
2249 case psp_gr:
2250 case rp_gr:
2251 case pfs_gr:
2252 case preds_gr:
2253 case unat_gr:
2254 case lc_gr:
2255 case fpsr_gr:
2256 case priunat_gr:
2257 case bsp_gr:
2258 case bspstore_gr:
2259 case rnat_gr:
2260 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2261 break;
2262 case rp_br:
2263 output_P3_format (f, rp_br, ptr->r.record.p.br);
2264 break;
2265 case psp_sprel:
2266 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2267 break;
2268 case rp_when:
2269 case pfs_when:
2270 case preds_when:
2271 case unat_when:
2272 case lc_when:
2273 case fpsr_when:
2274 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2275 break;
2276 case rp_psprel:
2277 case pfs_psprel:
2278 case preds_psprel:
2279 case unat_psprel:
2280 case lc_psprel:
2281 case fpsr_psprel:
2282 case spill_base:
2283 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2284 break;
2285 case rp_sprel:
2286 case pfs_sprel:
2287 case preds_sprel:
2288 case unat_sprel:
2289 case lc_sprel:
2290 case fpsr_sprel:
2291 case priunat_sprel:
2292 case bsp_sprel:
2293 case bspstore_sprel:
2294 case rnat_sprel:
2295 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2296 break;
2297 case gr_gr:
2298 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2299 break;
2300 case br_gr:
2301 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2302 break;
2303 case spill_mask:
2304 as_bad ("spill_mask record unimplemented.");
2305 break;
2306 case priunat_when_gr:
2307 case priunat_when_mem:
2308 case bsp_when:
2309 case bspstore_when:
2310 case rnat_when:
2311 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2312 break;
2313 case priunat_psprel:
2314 case bsp_psprel:
2315 case bspstore_psprel:
2316 case rnat_psprel:
2317 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2318 break;
2319 case unwabi:
2320 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2321 break;
2322 case epilogue:
2323 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2324 break;
2325 case label_state:
2326 case copy_state:
2327 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2328 break;
2329 case spill_psprel:
2330 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2331 ptr->r.record.x.reg, ptr->r.record.x.t,
2332 ptr->r.record.x.pspoff);
2333 break;
2334 case spill_sprel:
2335 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2336 ptr->r.record.x.reg, ptr->r.record.x.t,
2337 ptr->r.record.x.spoff);
2338 break;
2339 case spill_reg:
2340 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2341 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2342 ptr->r.record.x.treg, ptr->r.record.x.t);
2343 break;
2344 case spill_psprel_p:
2345 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2346 ptr->r.record.x.ab, ptr->r.record.x.reg,
2347 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2348 break;
2349 case spill_sprel_p:
2350 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2351 ptr->r.record.x.ab, ptr->r.record.x.reg,
2352 ptr->r.record.x.t, ptr->r.record.x.spoff);
2353 break;
2354 case spill_reg_p:
2355 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2356 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2357 ptr->r.record.x.xy, ptr->r.record.x.treg,
2358 ptr->r.record.x.t);
2359 break;
2360 default:
2361 as_bad ("record_type_not_valid");
2362 break;
2366 /* Given a unw_rec_list list, process all the records with
2367 the specified function. */
2368 static void
2369 process_unw_records (list, f)
2370 unw_rec_list *list;
2371 vbyte_func f;
2373 unw_rec_list *ptr;
2374 for (ptr = list; ptr; ptr = ptr->next)
2375 process_one_record (ptr, f);
2378 /* Determine the size of a record list in bytes. */
2379 static int
2380 calc_record_size (list)
2381 unw_rec_list *list;
2383 vbyte_count = 0;
2384 process_unw_records (list, count_output);
2385 return vbyte_count;
2388 /* Update IMASK bitmask to reflect the fact that one or more registers
2389 of type TYPE are saved starting at instruction with index T. If N
2390 bits are set in REGMASK, it is assumed that instructions T through
2391 T+N-1 save these registers.
2393 TYPE values:
2394 0: no save
2395 1: instruction saves next fp reg
2396 2: instruction saves next general reg
2397 3: instruction saves next branch reg */
2398 static void
2399 set_imask (region, regmask, t, type)
2400 unw_rec_list *region;
2401 unsigned long regmask;
2402 unsigned long t;
2403 unsigned int type;
2405 unsigned char *imask;
2406 unsigned long imask_size;
2407 unsigned int i;
2408 int pos;
2410 imask = region->r.record.r.mask.i;
2411 imask_size = region->r.record.r.imask_size;
2412 if (!imask)
2414 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
2415 imask = xmalloc (imask_size);
2416 memset (imask, 0, imask_size);
2418 region->r.record.r.imask_size = imask_size;
2419 region->r.record.r.mask.i = imask;
2422 i = (t / 4) + 1;
2423 pos = 2 * (3 - t % 4);
2424 while (regmask)
2426 if (i >= imask_size)
2428 as_bad ("Ignoring attempt to spill beyond end of region");
2429 return;
2432 imask[i] |= (type & 0x3) << pos;
2434 regmask &= (regmask - 1);
2435 pos -= 2;
2436 if (pos < 0)
2438 pos = 0;
2439 ++i;
2444 static int
2445 count_bits (unsigned long mask)
2447 int n = 0;
2449 while (mask)
2451 mask &= mask - 1;
2452 ++n;
2454 return n;
2457 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2458 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2459 containing FIRST_ADDR. */
2461 unsigned long
2462 slot_index (slot_addr, slot_frag, first_addr, first_frag)
2463 unsigned long slot_addr;
2464 fragS *slot_frag;
2465 unsigned long first_addr;
2466 fragS *first_frag;
2468 unsigned long index = 0;
2470 /* First time we are called, the initial address and frag are invalid. */
2471 if (first_addr == 0)
2472 return 0;
2474 /* If the two addresses are in different frags, then we need to add in
2475 the remaining size of this frag, and then the entire size of intermediate
2476 frags. */
2477 while (slot_frag != first_frag)
2479 unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
2481 /* Add in the full size of the frag converted to instruction slots. */
2482 index += 3 * (first_frag->fr_fix >> 4);
2483 /* Subtract away the initial part before first_addr. */
2484 index -= (3 * ((first_addr >> 4) - (start_addr >> 4))
2485 + ((first_addr & 0x3) - (start_addr & 0x3)));
2487 /* Move to the beginning of the next frag. */
2488 first_frag = first_frag->fr_next;
2489 first_addr = (unsigned long) &first_frag->fr_literal;
2492 /* Add in the used part of the last frag. */
2493 index += (3 * ((slot_addr >> 4) - (first_addr >> 4))
2494 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2495 return index;
2498 /* Given a complete record list, process any records which have
2499 unresolved fields, (ie length counts for a prologue). After
2500 this has been run, all neccessary information should be available
2501 within each record to generate an image. */
2503 static void
2504 fixup_unw_records (list)
2505 unw_rec_list *list;
2507 unw_rec_list *ptr, *region = 0;
2508 unsigned long first_addr = 0, rlen = 0, t;
2509 fragS *first_frag = 0;
2511 for (ptr = list; ptr; ptr = ptr->next)
2513 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2514 as_bad (" Insn slot not set in unwind record.");
2515 t = slot_index (ptr->slot_number, ptr->slot_frag,
2516 first_addr, first_frag);
2517 switch (ptr->r.type)
2519 case prologue:
2520 case prologue_gr:
2521 case body:
2523 unw_rec_list *last;
2524 int size, dir_len = 0;
2525 unsigned long last_addr;
2526 fragS *last_frag;
2528 first_addr = ptr->slot_number;
2529 first_frag = ptr->slot_frag;
2530 ptr->slot_number = 0;
2531 /* Find either the next body/prologue start, or the end of
2532 the list, and determine the size of the region. */
2533 last_addr = unwind.next_slot_number;
2534 last_frag = unwind.next_slot_frag;
2535 for (last = ptr->next; last != NULL; last = last->next)
2536 if (last->r.type == prologue || last->r.type == prologue_gr
2537 || last->r.type == body)
2539 last_addr = last->slot_number;
2540 last_frag = last->slot_frag;
2541 break;
2543 else if (!last->next)
2545 /* In the absence of an explicit .body directive,
2546 the prologue ends after the last instruction
2547 covered by an unwind directive. */
2548 if (ptr->r.type != body)
2550 last_addr = last->slot_number;
2551 last_frag = last->slot_frag;
2552 switch (last->r.type)
2554 case frgr_mem:
2555 dir_len = (count_bits (last->r.record.p.frmask)
2556 + count_bits (last->r.record.p.grmask));
2557 break;
2558 case fr_mem:
2559 case gr_mem:
2560 dir_len += count_bits (last->r.record.p.rmask);
2561 break;
2562 case br_mem:
2563 case br_gr:
2564 dir_len += count_bits (last->r.record.p.brmask);
2565 break;
2566 case gr_gr:
2567 dir_len += count_bits (last->r.record.p.grmask);
2568 break;
2569 default:
2570 dir_len = 1;
2571 break;
2574 break;
2576 size = (slot_index (last_addr, last_frag, first_addr, first_frag)
2577 + dir_len);
2578 rlen = ptr->r.record.r.rlen = size;
2579 region = ptr;
2580 break;
2582 case epilogue:
2583 ptr->r.record.b.t = rlen - 1 - t;
2584 break;
2586 case mem_stack_f:
2587 case mem_stack_v:
2588 case rp_when:
2589 case pfs_when:
2590 case preds_when:
2591 case unat_when:
2592 case lc_when:
2593 case fpsr_when:
2594 case priunat_when_gr:
2595 case priunat_when_mem:
2596 case bsp_when:
2597 case bspstore_when:
2598 case rnat_when:
2599 ptr->r.record.p.t = t;
2600 break;
2602 case spill_reg:
2603 case spill_sprel:
2604 case spill_psprel:
2605 case spill_reg_p:
2606 case spill_sprel_p:
2607 case spill_psprel_p:
2608 ptr->r.record.x.t = t;
2609 break;
2611 case frgr_mem:
2612 if (!region)
2614 as_bad ("frgr_mem record before region record!\n");
2615 return;
2617 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2618 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2619 set_imask (region, ptr->r.record.p.frmask, t, 1);
2620 set_imask (region, ptr->r.record.p.grmask, t, 2);
2621 break;
2622 case fr_mem:
2623 if (!region)
2625 as_bad ("fr_mem record before region record!\n");
2626 return;
2628 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2629 set_imask (region, ptr->r.record.p.rmask, t, 1);
2630 break;
2631 case gr_mem:
2632 if (!region)
2634 as_bad ("gr_mem record before region record!\n");
2635 return;
2637 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2638 set_imask (region, ptr->r.record.p.rmask, t, 2);
2639 break;
2640 case br_mem:
2641 if (!region)
2643 as_bad ("br_mem record before region record!\n");
2644 return;
2646 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2647 set_imask (region, ptr->r.record.p.brmask, t, 3);
2648 break;
2650 case gr_gr:
2651 if (!region)
2653 as_bad ("gr_gr record before region record!\n");
2654 return;
2656 set_imask (region, ptr->r.record.p.grmask, t, 2);
2657 break;
2658 case br_gr:
2659 if (!region)
2661 as_bad ("br_gr record before region record!\n");
2662 return;
2664 set_imask (region, ptr->r.record.p.brmask, t, 3);
2665 break;
2667 default:
2668 break;
2673 /* Generate an unwind image from a record list. Returns the number of
2674 bytes in the resulting image. The memory image itselof is returned
2675 in the 'ptr' parameter. */
2676 static int
2677 output_unw_records (list, ptr)
2678 unw_rec_list *list;
2679 void **ptr;
2681 int size, x, extra = 0;
2682 unsigned char *mem;
2684 fixup_unw_records (list);
2685 size = calc_record_size (list);
2687 /* pad to 8 byte boundry. */
2688 x = size % 8;
2689 if (x != 0)
2690 extra = 8 - x;
2691 /* Add 8 for the header + 8 more bytes for the personality offset. */
2692 mem = xmalloc (size + extra + 16);
2694 vbyte_mem_ptr = mem + 8;
2695 /* Clear the padding area and personality. */
2696 memset (mem + 8 + size, 0 , extra + 8);
2697 /* Initialize the header area. */
2698 md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */
2699 | (unwind.personality_routine
2700 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2701 : 0)
2702 | ((size + extra) / 8)), /* length (dwords) */
2705 process_unw_records (list, output_vbyte_mem);
2707 *ptr = mem;
2708 return size + extra + 16;
2711 static int
2712 convert_expr_to_ab_reg (e, ab, regp)
2713 expressionS *e;
2714 unsigned int *ab;
2715 unsigned int *regp;
2717 unsigned int reg;
2719 if (e->X_op != O_register)
2720 return 0;
2722 reg = e->X_add_number;
2723 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7))
2725 *ab = 0;
2726 *regp = reg - REG_GR;
2728 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5))
2729 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31)))
2731 *ab = 1;
2732 *regp = reg - REG_FR;
2734 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5))
2736 *ab = 2;
2737 *regp = reg - REG_BR;
2739 else
2741 *ab = 3;
2742 switch (reg)
2744 case REG_PR: *regp = 0; break;
2745 case REG_PSP: *regp = 1; break;
2746 case REG_PRIUNAT: *regp = 2; break;
2747 case REG_BR + 0: *regp = 3; break;
2748 case REG_AR + AR_BSP: *regp = 4; break;
2749 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2750 case REG_AR + AR_RNAT: *regp = 6; break;
2751 case REG_AR + AR_UNAT: *regp = 7; break;
2752 case REG_AR + AR_FPSR: *regp = 8; break;
2753 case REG_AR + AR_PFS: *regp = 9; break;
2754 case REG_AR + AR_LC: *regp = 10; break;
2756 default:
2757 return 0;
2760 return 1;
2763 static int
2764 convert_expr_to_xy_reg (e, xy, regp)
2765 expressionS *e;
2766 unsigned int *xy;
2767 unsigned int *regp;
2769 unsigned int reg;
2771 if (e->X_op != O_register)
2772 return 0;
2774 reg = e->X_add_number;
2776 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127))
2778 *xy = 0;
2779 *regp = reg - REG_GR;
2781 else if (reg >= REG_FR && reg <= (REG_FR + 127))
2783 *xy = 1;
2784 *regp = reg - REG_FR;
2786 else if (reg >= REG_BR && reg <= (REG_BR + 7))
2788 *xy = 2;
2789 *regp = reg - REG_BR;
2791 else
2792 return -1;
2793 return 1;
2796 static void
2797 dot_radix (dummy)
2798 int dummy ATTRIBUTE_UNUSED;
2800 int radix;
2802 SKIP_WHITESPACE ();
2803 radix = *input_line_pointer++;
2805 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2807 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2808 ignore_rest_of_line ();
2809 return;
2813 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2814 static void
2815 dot_special_section (which)
2816 int which;
2818 set_section ((char *) special_section_name[which]);
2821 static void
2822 add_unwind_entry (ptr)
2823 unw_rec_list *ptr;
2825 if (unwind.tail)
2826 unwind.tail->next = ptr;
2827 else
2828 unwind.list = ptr;
2829 unwind.tail = ptr;
2831 /* The current entry can in fact be a chain of unwind entries. */
2832 if (unwind.current_entry == NULL)
2833 unwind.current_entry = ptr;
2836 static void
2837 dot_fframe (dummy)
2838 int dummy ATTRIBUTE_UNUSED;
2840 expressionS e;
2842 parse_operand (&e);
2844 if (e.X_op != O_constant)
2845 as_bad ("Operand to .fframe must be a constant");
2846 else
2847 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2850 static void
2851 dot_vframe (dummy)
2852 int dummy ATTRIBUTE_UNUSED;
2854 expressionS e;
2855 unsigned reg;
2857 parse_operand (&e);
2858 reg = e.X_add_number - REG_GR;
2859 if (e.X_op == O_register && reg < 128)
2861 add_unwind_entry (output_mem_stack_v ());
2862 if (! (unwind.prologue_mask & 2))
2863 add_unwind_entry (output_psp_gr (reg));
2865 else
2866 as_bad ("First operand to .vframe must be a general register");
2869 static void
2870 dot_vframesp (dummy)
2871 int dummy ATTRIBUTE_UNUSED;
2873 expressionS e;
2875 parse_operand (&e);
2876 if (e.X_op == O_constant)
2878 add_unwind_entry (output_mem_stack_v ());
2879 add_unwind_entry (output_psp_sprel (e.X_add_number));
2881 else
2882 as_bad ("First operand to .vframesp must be a general register");
2885 static void
2886 dot_vframepsp (dummy)
2887 int dummy ATTRIBUTE_UNUSED;
2889 expressionS e;
2891 parse_operand (&e);
2892 if (e.X_op == O_constant)
2894 add_unwind_entry (output_mem_stack_v ());
2895 add_unwind_entry (output_psp_sprel (e.X_add_number));
2897 else
2898 as_bad ("First operand to .vframepsp must be a general register");
2901 static void
2902 dot_save (dummy)
2903 int dummy ATTRIBUTE_UNUSED;
2905 expressionS e1, e2;
2906 int sep;
2907 int reg1, reg2;
2909 sep = parse_operand (&e1);
2910 if (sep != ',')
2911 as_bad ("No second operand to .save");
2912 sep = parse_operand (&e2);
2914 reg1 = e1.X_add_number;
2915 reg2 = e2.X_add_number - REG_GR;
2917 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2918 if (e1.X_op == O_register)
2920 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
2922 switch (reg1)
2924 case REG_AR + AR_BSP:
2925 add_unwind_entry (output_bsp_when ());
2926 add_unwind_entry (output_bsp_gr (reg2));
2927 break;
2928 case REG_AR + AR_BSPSTORE:
2929 add_unwind_entry (output_bspstore_when ());
2930 add_unwind_entry (output_bspstore_gr (reg2));
2931 break;
2932 case REG_AR + AR_RNAT:
2933 add_unwind_entry (output_rnat_when ());
2934 add_unwind_entry (output_rnat_gr (reg2));
2935 break;
2936 case REG_AR + AR_UNAT:
2937 add_unwind_entry (output_unat_when ());
2938 add_unwind_entry (output_unat_gr (reg2));
2939 break;
2940 case REG_AR + AR_FPSR:
2941 add_unwind_entry (output_fpsr_when ());
2942 add_unwind_entry (output_fpsr_gr (reg2));
2943 break;
2944 case REG_AR + AR_PFS:
2945 add_unwind_entry (output_pfs_when ());
2946 if (! (unwind.prologue_mask & 4))
2947 add_unwind_entry (output_pfs_gr (reg2));
2948 break;
2949 case REG_AR + AR_LC:
2950 add_unwind_entry (output_lc_when ());
2951 add_unwind_entry (output_lc_gr (reg2));
2952 break;
2953 case REG_BR:
2954 add_unwind_entry (output_rp_when ());
2955 if (! (unwind.prologue_mask & 8))
2956 add_unwind_entry (output_rp_gr (reg2));
2957 break;
2958 case REG_PR:
2959 add_unwind_entry (output_preds_when ());
2960 if (! (unwind.prologue_mask & 1))
2961 add_unwind_entry (output_preds_gr (reg2));
2962 break;
2963 case REG_PRIUNAT:
2964 add_unwind_entry (output_priunat_when_gr ());
2965 add_unwind_entry (output_priunat_gr (reg2));
2966 break;
2967 default:
2968 as_bad ("First operand not a valid register");
2971 else
2972 as_bad (" Second operand not a valid register");
2974 else
2975 as_bad ("First operand not a register");
2978 static void
2979 dot_restore (dummy)
2980 int dummy ATTRIBUTE_UNUSED;
2982 expressionS e1, e2;
2983 unsigned long ecount = 0;
2984 int sep;
2986 sep = parse_operand (&e1);
2987 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
2989 as_bad ("First operand to .restore must be stack pointer (sp)");
2990 return;
2993 if (sep == ',')
2995 parse_operand (&e2);
2996 if (e1.X_op != O_constant)
2998 as_bad ("Second operand to .restore must be constant");
2999 return;
3001 ecount = e1.X_op;
3003 add_unwind_entry (output_epilogue (ecount));
3006 static void
3007 dot_restorereg (dummy)
3008 int dummy ATTRIBUTE_UNUSED;
3010 unsigned int ab, reg;
3011 expressionS e;
3013 parse_operand (&e);
3015 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
3017 as_bad ("First operand to .restorereg must be a preserved register");
3018 return;
3020 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
3023 static void
3024 dot_restorereg_p (dummy)
3025 int dummy ATTRIBUTE_UNUSED;
3027 unsigned int qp, ab, reg;
3028 expressionS e1, e2;
3029 int sep;
3031 sep = parse_operand (&e1);
3032 if (sep != ',')
3034 as_bad ("No second operand to .restorereg.p");
3035 return;
3038 parse_operand (&e2);
3040 qp = e1.X_add_number - REG_P;
3041 if (e1.X_op != O_register || qp > 63)
3043 as_bad ("First operand to .restorereg.p must be a predicate");
3044 return;
3047 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3049 as_bad ("Second operand to .restorereg.p must be a preserved register");
3050 return;
3052 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
3055 static int
3056 generate_unwind_image ()
3058 int size;
3059 unsigned char *unw_rec;
3061 /* Force out pending instructions, to make sure all unwind records have
3062 a valid slot_number field. */
3063 ia64_flush_insns ();
3065 /* Generate the unwind record. */
3066 size = output_unw_records (unwind.list, (void **) &unw_rec);
3067 if (size % 8 != 0)
3068 as_bad ("Unwind record is not a multiple of 8 bytes.");
3070 /* If there are unwind records, switch sections, and output the info. */
3071 if (size != 0)
3073 unsigned char *where;
3074 expressionS exp;
3075 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
3077 /* Make sure the section has 8 byte alignment. */
3078 record_alignment (now_seg, 3);
3080 /* Set expression which points to start of unwind descriptor area. */
3081 unwind.info = expr_build_dot ();
3083 where = (unsigned char *) frag_more (size);
3085 /* Issue a label for this address, and keep track of it to put it
3086 in the unwind section. */
3088 /* Copy the information from the unwind record into this section. The
3089 data is already in the correct byte order. */
3090 memcpy (where, unw_rec, size);
3091 /* Add the personality address to the image. */
3092 if (unwind.personality_routine != 0)
3094 exp.X_op = O_symbol;
3095 exp.X_add_symbol = unwind.personality_routine;
3096 exp.X_add_number = 0;
3097 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
3098 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
3099 unwind.personality_routine = 0;
3101 obj_elf_previous (0);
3104 free_list_records (unwind.list);
3105 unwind.list = unwind.tail = unwind.current_entry = NULL;
3107 return size;
3110 static void
3111 dot_handlerdata (dummy)
3112 int dummy ATTRIBUTE_UNUSED;
3114 generate_unwind_image ();
3115 demand_empty_rest_of_line ();
3118 static void
3119 dot_unwentry (dummy)
3120 int dummy ATTRIBUTE_UNUSED;
3122 demand_empty_rest_of_line ();
3125 static void
3126 dot_altrp (dummy)
3127 int dummy ATTRIBUTE_UNUSED;
3129 expressionS e;
3130 unsigned reg;
3132 parse_operand (&e);
3133 reg = e.X_add_number - REG_BR;
3134 if (e.X_op == O_register && reg < 8)
3135 add_unwind_entry (output_rp_br (reg));
3136 else
3137 as_bad ("First operand not a valid branch register");
3140 static void
3141 dot_savemem (psprel)
3142 int psprel;
3144 expressionS e1, e2;
3145 int sep;
3146 int reg1, val;
3148 sep = parse_operand (&e1);
3149 if (sep != ',')
3150 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
3151 sep = parse_operand (&e2);
3153 reg1 = e1.X_add_number;
3154 val = e2.X_add_number;
3156 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3157 if (e1.X_op == O_register)
3159 if (e2.X_op == O_constant)
3161 switch (reg1)
3163 case REG_AR + AR_BSP:
3164 add_unwind_entry (output_bsp_when ());
3165 add_unwind_entry ((psprel
3166 ? output_bsp_psprel
3167 : output_bsp_sprel) (val));
3168 break;
3169 case REG_AR + AR_BSPSTORE:
3170 add_unwind_entry (output_bspstore_when ());
3171 add_unwind_entry ((psprel
3172 ? output_bspstore_psprel
3173 : output_bspstore_sprel) (val));
3174 break;
3175 case REG_AR + AR_RNAT:
3176 add_unwind_entry (output_rnat_when ());
3177 add_unwind_entry ((psprel
3178 ? output_rnat_psprel
3179 : output_rnat_sprel) (val));
3180 break;
3181 case REG_AR + AR_UNAT:
3182 add_unwind_entry (output_unat_when ());
3183 add_unwind_entry ((psprel
3184 ? output_unat_psprel
3185 : output_unat_sprel) (val));
3186 break;
3187 case REG_AR + AR_FPSR:
3188 add_unwind_entry (output_fpsr_when ());
3189 add_unwind_entry ((psprel
3190 ? output_fpsr_psprel
3191 : output_fpsr_sprel) (val));
3192 break;
3193 case REG_AR + AR_PFS:
3194 add_unwind_entry (output_pfs_when ());
3195 add_unwind_entry ((psprel
3196 ? output_pfs_psprel
3197 : output_pfs_sprel) (val));
3198 break;
3199 case REG_AR + AR_LC:
3200 add_unwind_entry (output_lc_when ());
3201 add_unwind_entry ((psprel
3202 ? output_lc_psprel
3203 : output_lc_sprel) (val));
3204 break;
3205 case REG_BR:
3206 add_unwind_entry (output_rp_when ());
3207 add_unwind_entry ((psprel
3208 ? output_rp_psprel
3209 : output_rp_sprel) (val));
3210 break;
3211 case REG_PR:
3212 add_unwind_entry (output_preds_when ());
3213 add_unwind_entry ((psprel
3214 ? output_preds_psprel
3215 : output_preds_sprel) (val));
3216 break;
3217 case REG_PRIUNAT:
3218 add_unwind_entry (output_priunat_when_mem ());
3219 add_unwind_entry ((psprel
3220 ? output_priunat_psprel
3221 : output_priunat_sprel) (val));
3222 break;
3223 default:
3224 as_bad ("First operand not a valid register");
3227 else
3228 as_bad (" Second operand not a valid constant");
3230 else
3231 as_bad ("First operand not a register");
3234 static void
3235 dot_saveg (dummy)
3236 int dummy ATTRIBUTE_UNUSED;
3238 expressionS e1, e2;
3239 int sep;
3240 sep = parse_operand (&e1);
3241 if (sep == ',')
3242 parse_operand (&e2);
3244 if (e1.X_op != O_constant)
3245 as_bad ("First operand to .save.g must be a constant.");
3246 else
3248 int grmask = e1.X_add_number;
3249 if (sep != ',')
3250 add_unwind_entry (output_gr_mem (grmask));
3251 else
3253 int reg = e2.X_add_number - REG_GR;
3254 if (e2.X_op == O_register && reg >= 0 && reg < 128)
3255 add_unwind_entry (output_gr_gr (grmask, reg));
3256 else
3257 as_bad ("Second operand is an invalid register.");
3262 static void
3263 dot_savef (dummy)
3264 int dummy ATTRIBUTE_UNUSED;
3266 expressionS e1;
3267 int sep;
3268 sep = parse_operand (&e1);
3270 if (e1.X_op != O_constant)
3271 as_bad ("Operand to .save.f must be a constant.");
3272 else
3273 add_unwind_entry (output_fr_mem (e1.X_add_number));
3276 static void
3277 dot_saveb (dummy)
3278 int dummy ATTRIBUTE_UNUSED;
3280 expressionS e1, e2;
3281 unsigned int reg;
3282 unsigned char sep;
3283 int brmask;
3285 sep = parse_operand (&e1);
3286 if (e1.X_op != O_constant)
3288 as_bad ("First operand to .save.b must be a constant.");
3289 return;
3291 brmask = e1.X_add_number;
3293 if (sep == ',')
3295 sep = parse_operand (&e2);
3296 reg = e2.X_add_number - REG_GR;
3297 if (e2.X_op != O_register || reg > 127)
3299 as_bad ("Second operand to .save.b must be a general register.");
3300 return;
3302 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3304 else
3305 add_unwind_entry (output_br_mem (brmask));
3307 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3308 ignore_rest_of_line ();
3311 static void
3312 dot_savegf (dummy)
3313 int dummy ATTRIBUTE_UNUSED;
3315 expressionS e1, e2;
3316 int sep;
3317 sep = parse_operand (&e1);
3318 if (sep == ',')
3319 parse_operand (&e2);
3321 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3322 as_bad ("Both operands of .save.gf must be constants.");
3323 else
3325 int grmask = e1.X_add_number;
3326 int frmask = e2.X_add_number;
3327 add_unwind_entry (output_frgr_mem (grmask, frmask));
3331 static void
3332 dot_spill (dummy)
3333 int dummy ATTRIBUTE_UNUSED;
3335 expressionS e;
3336 unsigned char sep;
3338 sep = parse_operand (&e);
3339 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3340 ignore_rest_of_line ();
3342 if (e.X_op != O_constant)
3343 as_bad ("Operand to .spill must be a constant");
3344 else
3345 add_unwind_entry (output_spill_base (e.X_add_number));
3348 static void
3349 dot_spillreg (dummy)
3350 int dummy ATTRIBUTE_UNUSED;
3352 int sep, ab, xy, reg, treg;
3353 expressionS e1, e2;
3355 sep = parse_operand (&e1);
3356 if (sep != ',')
3358 as_bad ("No second operand to .spillreg");
3359 return;
3362 parse_operand (&e2);
3364 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3366 as_bad ("First operand to .spillreg must be a preserved register");
3367 return;
3370 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3372 as_bad ("Second operand to .spillreg must be a register");
3373 return;
3376 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3379 static void
3380 dot_spillmem (psprel)
3381 int psprel;
3383 expressionS e1, e2;
3384 int sep, ab, reg;
3386 sep = parse_operand (&e1);
3387 if (sep != ',')
3389 as_bad ("Second operand missing");
3390 return;
3393 parse_operand (&e2);
3395 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3397 as_bad ("First operand to .spill%s must be a preserved register",
3398 psprel ? "psp" : "sp");
3399 return;
3402 if (e2.X_op != O_constant)
3404 as_bad ("Second operand to .spill%s must be a constant",
3405 psprel ? "psp" : "sp");
3406 return;
3409 if (psprel)
3410 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3411 else
3412 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3415 static void
3416 dot_spillreg_p (dummy)
3417 int dummy ATTRIBUTE_UNUSED;
3419 int sep, ab, xy, reg, treg;
3420 expressionS e1, e2, e3;
3421 unsigned int qp;
3423 sep = parse_operand (&e1);
3424 if (sep != ',')
3426 as_bad ("No second and third operand to .spillreg.p");
3427 return;
3430 sep = parse_operand (&e2);
3431 if (sep != ',')
3433 as_bad ("No third operand to .spillreg.p");
3434 return;
3437 parse_operand (&e3);
3439 qp = e1.X_add_number - REG_P;
3441 if (e1.X_op != O_register || qp > 63)
3443 as_bad ("First operand to .spillreg.p must be a predicate");
3444 return;
3447 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3449 as_bad ("Second operand to .spillreg.p must be a preserved register");
3450 return;
3453 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3455 as_bad ("Third operand to .spillreg.p must be a register");
3456 return;
3459 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3462 static void
3463 dot_spillmem_p (psprel)
3464 int psprel;
3466 expressionS e1, e2, e3;
3467 int sep, ab, reg;
3468 unsigned int qp;
3470 sep = parse_operand (&e1);
3471 if (sep != ',')
3473 as_bad ("Second operand missing");
3474 return;
3477 parse_operand (&e2);
3478 if (sep != ',')
3480 as_bad ("Second operand missing");
3481 return;
3484 parse_operand (&e3);
3486 qp = e1.X_add_number - REG_P;
3487 if (e1.X_op != O_register || qp > 63)
3489 as_bad ("First operand to .spill%s_p must be a predicate",
3490 psprel ? "psp" : "sp");
3491 return;
3494 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3496 as_bad ("Second operand to .spill%s_p must be a preserved register",
3497 psprel ? "psp" : "sp");
3498 return;
3501 if (e3.X_op != O_constant)
3503 as_bad ("Third operand to .spill%s_p must be a constant",
3504 psprel ? "psp" : "sp");
3505 return;
3508 if (psprel)
3509 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3510 else
3511 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3514 static void
3515 dot_label_state (dummy)
3516 int dummy ATTRIBUTE_UNUSED;
3518 expressionS e;
3520 parse_operand (&e);
3521 if (e.X_op != O_constant)
3523 as_bad ("Operand to .label_state must be a constant");
3524 return;
3526 add_unwind_entry (output_label_state (e.X_add_number));
3529 static void
3530 dot_copy_state (dummy)
3531 int dummy ATTRIBUTE_UNUSED;
3533 expressionS e;
3535 parse_operand (&e);
3536 if (e.X_op != O_constant)
3538 as_bad ("Operand to .copy_state must be a constant");
3539 return;
3541 add_unwind_entry (output_copy_state (e.X_add_number));
3544 static void
3545 dot_unwabi (dummy)
3546 int dummy ATTRIBUTE_UNUSED;
3548 expressionS e1, e2;
3549 unsigned char sep;
3551 sep = parse_operand (&e1);
3552 if (sep != ',')
3554 as_bad ("Second operand to .unwabi missing");
3555 return;
3557 sep = parse_operand (&e2);
3558 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3559 ignore_rest_of_line ();
3561 if (e1.X_op != O_constant)
3563 as_bad ("First operand to .unwabi must be a constant");
3564 return;
3567 if (e2.X_op != O_constant)
3569 as_bad ("Second operand to .unwabi must be a constant");
3570 return;
3573 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
3576 static void
3577 dot_personality (dummy)
3578 int dummy ATTRIBUTE_UNUSED;
3580 char *name, *p, c;
3581 SKIP_WHITESPACE ();
3582 name = input_line_pointer;
3583 c = get_symbol_end ();
3584 p = input_line_pointer;
3585 unwind.personality_routine = symbol_find_or_make (name);
3586 *p = c;
3587 SKIP_WHITESPACE ();
3588 demand_empty_rest_of_line ();
3591 static void
3592 dot_proc (dummy)
3593 int dummy ATTRIBUTE_UNUSED;
3595 char *name, *p, c;
3596 symbolS *sym;
3598 unwind.proc_start = expr_build_dot ();
3599 /* Parse names of main and alternate entry points and mark them as
3600 function symbols: */
3601 while (1)
3603 SKIP_WHITESPACE ();
3604 name = input_line_pointer;
3605 c = get_symbol_end ();
3606 p = input_line_pointer;
3607 sym = symbol_find_or_make (name);
3608 if (unwind.proc_start == 0)
3610 unwind.proc_start = sym;
3612 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3613 *p = c;
3614 SKIP_WHITESPACE ();
3615 if (*input_line_pointer != ',')
3616 break;
3617 ++input_line_pointer;
3619 demand_empty_rest_of_line ();
3620 ia64_do_align (16);
3622 unwind.list = unwind.tail = unwind.current_entry = NULL;
3623 unwind.personality_routine = 0;
3626 static void
3627 dot_body (dummy)
3628 int dummy ATTRIBUTE_UNUSED;
3630 unwind.prologue = 0;
3631 unwind.prologue_mask = 0;
3633 add_unwind_entry (output_body ());
3634 demand_empty_rest_of_line ();
3637 static void
3638 dot_prologue (dummy)
3639 int dummy ATTRIBUTE_UNUSED;
3641 unsigned char sep;
3642 int mask = 0, grsave = 0;
3644 if (!is_it_end_of_statement ())
3646 expressionS e1, e2;
3647 sep = parse_operand (&e1);
3648 if (sep != ',')
3649 as_bad ("No second operand to .prologue");
3650 sep = parse_operand (&e2);
3651 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3652 ignore_rest_of_line ();
3654 if (e1.X_op == O_constant)
3656 mask = e1.X_add_number;
3658 if (e2.X_op == O_constant)
3659 grsave = e2.X_add_number;
3660 else if (e2.X_op == O_register
3661 && (grsave = e2.X_add_number - REG_GR) < 128)
3663 else
3664 as_bad ("Second operand not a constant or general register");
3666 add_unwind_entry (output_prologue_gr (mask, grsave));
3668 else
3669 as_bad ("First operand not a constant");
3671 else
3672 add_unwind_entry (output_prologue ());
3674 unwind.prologue = 1;
3675 unwind.prologue_mask = mask;
3678 static void
3679 dot_endp (dummy)
3680 int dummy ATTRIBUTE_UNUSED;
3682 expressionS e;
3683 unsigned char *ptr;
3684 int bytes_per_address;
3685 long where;
3686 segT saved_seg;
3687 subsegT saved_subseg;
3689 saved_seg = now_seg;
3690 saved_subseg = now_subseg;
3692 expression (&e);
3693 demand_empty_rest_of_line ();
3695 insn_group_break (1, 0, 0);
3697 /* If there was a .handlerdata, we haven't generated an image yet. */
3698 if (unwind.info == 0)
3700 generate_unwind_image ();
3703 subseg_set (md.last_text_seg, 0);
3704 unwind.proc_end = expr_build_dot ();
3706 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
3708 /* Make sure the section has 8 byte alignment. */
3709 record_alignment (now_seg, 3);
3711 ptr = frag_more (24);
3712 where = frag_now_fix () - 24;
3713 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
3715 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3716 e.X_op = O_pseudo_fixup;
3717 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3718 e.X_add_number = 0;
3719 e.X_add_symbol = unwind.proc_start;
3720 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
3722 e.X_op = O_pseudo_fixup;
3723 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3724 e.X_add_number = 0;
3725 e.X_add_symbol = unwind.proc_end;
3726 ia64_cons_fix_new (frag_now, where + bytes_per_address, bytes_per_address, &e);
3728 if (unwind.info != 0)
3730 e.X_op = O_pseudo_fixup;
3731 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3732 e.X_add_number = 0;
3733 e.X_add_symbol = unwind.info;
3734 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), bytes_per_address, &e);
3736 else
3737 md_number_to_chars (ptr + (bytes_per_address * 2), 0, bytes_per_address);
3739 subseg_set (saved_seg, saved_subseg);
3740 unwind.proc_start = unwind.proc_end = unwind.info = 0;
3743 static void
3744 dot_template (template)
3745 int template;
3747 CURR_SLOT.user_template = template;
3750 static void
3751 dot_regstk (dummy)
3752 int dummy ATTRIBUTE_UNUSED;
3754 int ins, locs, outs, rots;
3756 if (is_it_end_of_statement ())
3757 ins = locs = outs = rots = 0;
3758 else
3760 ins = get_absolute_expression ();
3761 if (*input_line_pointer++ != ',')
3762 goto err;
3763 locs = get_absolute_expression ();
3764 if (*input_line_pointer++ != ',')
3765 goto err;
3766 outs = get_absolute_expression ();
3767 if (*input_line_pointer++ != ',')
3768 goto err;
3769 rots = get_absolute_expression ();
3771 set_regstack (ins, locs, outs, rots);
3772 return;
3774 err:
3775 as_bad ("Comma expected");
3776 ignore_rest_of_line ();
3779 static void
3780 dot_rot (type)
3781 int type;
3783 unsigned num_regs, num_alloced = 0;
3784 struct dynreg **drpp, *dr;
3785 int ch, base_reg = 0;
3786 char *name, *start;
3787 size_t len;
3789 switch (type)
3791 case DYNREG_GR: base_reg = REG_GR + 32; break;
3792 case DYNREG_FR: base_reg = REG_FR + 32; break;
3793 case DYNREG_PR: base_reg = REG_P + 16; break;
3794 default: break;
3797 /* First, remove existing names from hash table. */
3798 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3800 hash_delete (md.dynreg_hash, dr->name);
3801 dr->num_regs = 0;
3804 drpp = &md.dynreg[type];
3805 while (1)
3807 start = input_line_pointer;
3808 ch = get_symbol_end ();
3809 *input_line_pointer = ch;
3810 len = (input_line_pointer - start);
3812 SKIP_WHITESPACE ();
3813 if (*input_line_pointer != '[')
3815 as_bad ("Expected '['");
3816 goto err;
3818 ++input_line_pointer; /* skip '[' */
3820 num_regs = get_absolute_expression ();
3822 if (*input_line_pointer++ != ']')
3824 as_bad ("Expected ']'");
3825 goto err;
3827 SKIP_WHITESPACE ();
3829 num_alloced += num_regs;
3830 switch (type)
3832 case DYNREG_GR:
3833 if (num_alloced > md.rot.num_regs)
3835 as_bad ("Used more than the declared %d rotating registers",
3836 md.rot.num_regs);
3837 goto err;
3839 break;
3840 case DYNREG_FR:
3841 if (num_alloced > 96)
3843 as_bad ("Used more than the available 96 rotating registers");
3844 goto err;
3846 break;
3847 case DYNREG_PR:
3848 if (num_alloced > 48)
3850 as_bad ("Used more than the available 48 rotating registers");
3851 goto err;
3853 break;
3855 default:
3856 break;
3859 name = obstack_alloc (&notes, len + 1);
3860 memcpy (name, start, len);
3861 name[len] = '\0';
3863 if (!*drpp)
3865 *drpp = obstack_alloc (&notes, sizeof (*dr));
3866 memset (*drpp, 0, sizeof (*dr));
3869 dr = *drpp;
3870 dr->name = name;
3871 dr->num_regs = num_regs;
3872 dr->base = base_reg;
3873 drpp = &dr->next;
3874 base_reg += num_regs;
3876 if (hash_insert (md.dynreg_hash, name, dr))
3878 as_bad ("Attempt to redefine register set `%s'", name);
3879 goto err;
3882 if (*input_line_pointer != ',')
3883 break;
3884 ++input_line_pointer; /* skip comma */
3885 SKIP_WHITESPACE ();
3887 demand_empty_rest_of_line ();
3888 return;
3890 err:
3891 ignore_rest_of_line ();
3894 static void
3895 dot_byteorder (byteorder)
3896 int byteorder;
3898 target_big_endian = byteorder;
3901 static void
3902 dot_psr (dummy)
3903 int dummy ATTRIBUTE_UNUSED;
3905 char *option;
3906 int ch;
3908 while (1)
3910 option = input_line_pointer;
3911 ch = get_symbol_end ();
3912 if (strcmp (option, "lsb") == 0)
3913 md.flags &= ~EF_IA_64_BE;
3914 else if (strcmp (option, "msb") == 0)
3915 md.flags |= EF_IA_64_BE;
3916 else if (strcmp (option, "abi32") == 0)
3917 md.flags &= ~EF_IA_64_ABI64;
3918 else if (strcmp (option, "abi64") == 0)
3919 md.flags |= EF_IA_64_ABI64;
3920 else
3921 as_bad ("Unknown psr option `%s'", option);
3922 *input_line_pointer = ch;
3924 SKIP_WHITESPACE ();
3925 if (*input_line_pointer != ',')
3926 break;
3928 ++input_line_pointer;
3929 SKIP_WHITESPACE ();
3931 demand_empty_rest_of_line ();
3934 static void
3935 dot_alias (dummy)
3936 int dummy ATTRIBUTE_UNUSED;
3938 as_bad (".alias not implemented yet");
3941 static void
3942 dot_ln (dummy)
3943 int dummy ATTRIBUTE_UNUSED;
3945 new_logical_line (0, get_absolute_expression ());
3946 demand_empty_rest_of_line ();
3949 static char *
3950 parse_section_name ()
3952 char *name;
3953 int len;
3955 SKIP_WHITESPACE ();
3956 if (*input_line_pointer != '"')
3958 as_bad ("Missing section name");
3959 ignore_rest_of_line ();
3960 return 0;
3962 name = demand_copy_C_string (&len);
3963 if (!name)
3965 ignore_rest_of_line ();
3966 return 0;
3968 SKIP_WHITESPACE ();
3969 if (*input_line_pointer != ',')
3971 as_bad ("Comma expected after section name");
3972 ignore_rest_of_line ();
3973 return 0;
3975 ++input_line_pointer; /* skip comma */
3976 return name;
3979 static void
3980 dot_xdata (size)
3981 int size;
3983 char *name = parse_section_name ();
3984 if (!name)
3985 return;
3987 set_section (name);
3988 cons (size);
3989 obj_elf_previous (0);
3992 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3994 static void
3995 stmt_float_cons (kind)
3996 int kind;
3998 size_t size;
4000 switch (kind)
4002 case 'd': size = 8; break;
4003 case 'x': size = 10; break;
4005 case 'f':
4006 default:
4007 size = 4;
4008 break;
4010 ia64_do_align (size);
4011 float_cons (kind);
4014 static void
4015 stmt_cons_ua (size)
4016 int size;
4018 int saved_auto_align = md.auto_align;
4020 md.auto_align = 0;
4021 cons (size);
4022 md.auto_align = saved_auto_align;
4025 static void
4026 dot_xfloat_cons (kind)
4027 int kind;
4029 char *name = parse_section_name ();
4030 if (!name)
4031 return;
4033 set_section (name);
4034 stmt_float_cons (kind);
4035 obj_elf_previous (0);
4038 static void
4039 dot_xstringer (zero)
4040 int zero;
4042 char *name = parse_section_name ();
4043 if (!name)
4044 return;
4046 set_section (name);
4047 stringer (zero);
4048 obj_elf_previous (0);
4051 static void
4052 dot_xdata_ua (size)
4053 int size;
4055 int saved_auto_align = md.auto_align;
4056 char *name = parse_section_name ();
4057 if (!name)
4058 return;
4060 set_section (name);
4061 md.auto_align = 0;
4062 cons (size);
4063 md.auto_align = saved_auto_align;
4064 obj_elf_previous (0);
4067 static void
4068 dot_xfloat_cons_ua (kind)
4069 int kind;
4071 int saved_auto_align = md.auto_align;
4072 char *name = parse_section_name ();
4073 if (!name)
4074 return;
4076 set_section (name);
4077 md.auto_align = 0;
4078 stmt_float_cons (kind);
4079 md.auto_align = saved_auto_align;
4080 obj_elf_previous (0);
4083 /* .reg.val <regname>,value */
4085 static void
4086 dot_reg_val (dummy)
4087 int dummy ATTRIBUTE_UNUSED;
4089 expressionS reg;
4091 expression (&reg);
4092 if (reg.X_op != O_register)
4094 as_bad (_("Register name expected"));
4095 ignore_rest_of_line ();
4097 else if (*input_line_pointer++ != ',')
4099 as_bad (_("Comma expected"));
4100 ignore_rest_of_line ();
4102 else
4104 valueT value = get_absolute_expression ();
4105 int regno = reg.X_add_number;
4106 if (regno < REG_GR || regno > REG_GR + 128)
4107 as_warn (_("Register value annotation ignored"));
4108 else
4110 gr_values[regno - REG_GR].known = 1;
4111 gr_values[regno - REG_GR].value = value;
4112 gr_values[regno - REG_GR].path = md.path;
4115 demand_empty_rest_of_line ();
4118 /* select dv checking mode
4119 .auto
4120 .explicit
4121 .default
4123 A stop is inserted when changing modes
4126 static void
4127 dot_dv_mode (type)
4128 int type;
4130 if (md.manual_bundling)
4131 as_warn (_("Directive invalid within a bundle"));
4133 if (type == 'E' || type == 'A')
4134 md.mode_explicitly_set = 0;
4135 else
4136 md.mode_explicitly_set = 1;
4138 md.detect_dv = 1;
4139 switch (type)
4141 case 'A':
4142 case 'a':
4143 if (md.explicit_mode)
4144 insn_group_break (1, 0, 0);
4145 md.explicit_mode = 0;
4146 break;
4147 case 'E':
4148 case 'e':
4149 if (!md.explicit_mode)
4150 insn_group_break (1, 0, 0);
4151 md.explicit_mode = 1;
4152 break;
4153 default:
4154 case 'd':
4155 if (md.explicit_mode != md.default_explicit_mode)
4156 insn_group_break (1, 0, 0);
4157 md.explicit_mode = md.default_explicit_mode;
4158 md.mode_explicitly_set = 0;
4159 break;
4163 static void
4164 print_prmask (mask)
4165 valueT mask;
4167 int regno;
4168 char *comma = "";
4169 for (regno = 0; regno < 64; regno++)
4171 if (mask & ((valueT) 1 << regno))
4173 fprintf (stderr, "%s p%d", comma, regno);
4174 comma = ",";
4180 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4181 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4182 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4183 .pred.safe_across_calls p1 [, p2 [,...]]
4186 static void
4187 dot_pred_rel (type)
4188 int type;
4190 valueT mask = 0;
4191 int count = 0;
4192 int p1 = -1, p2 = -1;
4194 if (type == 0)
4196 if (*input_line_pointer != '"')
4198 as_bad (_("Missing predicate relation type"));
4199 ignore_rest_of_line ();
4200 return;
4202 else
4204 int len;
4205 char *form = demand_copy_C_string (&len);
4206 if (strcmp (form, "mutex") == 0)
4207 type = 'm';
4208 else if (strcmp (form, "clear") == 0)
4209 type = 'c';
4210 else if (strcmp (form, "imply") == 0)
4211 type = 'i';
4212 else
4214 as_bad (_("Unrecognized predicate relation type"));
4215 ignore_rest_of_line ();
4216 return;
4219 if (*input_line_pointer == ',')
4220 ++input_line_pointer;
4221 SKIP_WHITESPACE ();
4224 SKIP_WHITESPACE ();
4225 while (1)
4227 valueT bit = 1;
4228 int regno;
4230 if (toupper (*input_line_pointer) != 'P'
4231 || (regno = atoi (++input_line_pointer)) < 0
4232 || regno > 63)
4234 as_bad (_("Predicate register expected"));
4235 ignore_rest_of_line ();
4236 return;
4238 while (isdigit (*input_line_pointer))
4239 ++input_line_pointer;
4240 if (p1 == -1)
4241 p1 = regno;
4242 else if (p2 == -1)
4243 p2 = regno;
4244 bit <<= regno;
4245 if (mask & bit)
4246 as_warn (_("Duplicate predicate register ignored"));
4247 mask |= bit;
4248 count++;
4249 /* See if it's a range. */
4250 if (*input_line_pointer == '-')
4252 valueT stop = 1;
4253 ++input_line_pointer;
4255 if (toupper (*input_line_pointer) != 'P'
4256 || (regno = atoi (++input_line_pointer)) < 0
4257 || regno > 63)
4259 as_bad (_("Predicate register expected"));
4260 ignore_rest_of_line ();
4261 return;
4263 while (isdigit (*input_line_pointer))
4264 ++input_line_pointer;
4265 stop <<= regno;
4266 if (bit >= stop)
4268 as_bad (_("Bad register range"));
4269 ignore_rest_of_line ();
4270 return;
4272 while (bit < stop)
4274 bit <<= 1;
4275 mask |= bit;
4276 count++;
4278 SKIP_WHITESPACE ();
4280 if (*input_line_pointer != ',')
4281 break;
4282 ++input_line_pointer;
4283 SKIP_WHITESPACE ();
4286 switch (type)
4288 case 'c':
4289 if (count == 0)
4290 mask = ~(valueT) 0;
4291 clear_qp_mutex (mask);
4292 clear_qp_implies (mask, (valueT) 0);
4293 break;
4294 case 'i':
4295 if (count != 2 || p1 == -1 || p2 == -1)
4296 as_bad (_("Predicate source and target required"));
4297 else if (p1 == 0 || p2 == 0)
4298 as_bad (_("Use of p0 is not valid in this context"));
4299 else
4300 add_qp_imply (p1, p2);
4301 break;
4302 case 'm':
4303 if (count < 2)
4305 as_bad (_("At least two PR arguments expected"));
4306 break;
4308 else if (mask & 1)
4310 as_bad (_("Use of p0 is not valid in this context"));
4311 break;
4313 add_qp_mutex (mask);
4314 break;
4315 case 's':
4316 /* note that we don't override any existing relations */
4317 if (count == 0)
4319 as_bad (_("At least one PR argument expected"));
4320 break;
4322 if (md.debug_dv)
4324 fprintf (stderr, "Safe across calls: ");
4325 print_prmask (mask);
4326 fprintf (stderr, "\n");
4328 qp_safe_across_calls = mask;
4329 break;
4331 demand_empty_rest_of_line ();
4334 /* .entry label [, label [, ...]]
4335 Hint to DV code that the given labels are to be considered entry points.
4336 Otherwise, only global labels are considered entry points. */
4338 static void
4339 dot_entry (dummy)
4340 int dummy ATTRIBUTE_UNUSED;
4342 const char *err;
4343 char *name;
4344 int c;
4345 symbolS *symbolP;
4349 name = input_line_pointer;
4350 c = get_symbol_end ();
4351 symbolP = symbol_find_or_make (name);
4353 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4354 if (err)
4355 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4356 name, err);
4358 *input_line_pointer = c;
4359 SKIP_WHITESPACE ();
4360 c = *input_line_pointer;
4361 if (c == ',')
4363 input_line_pointer++;
4364 SKIP_WHITESPACE ();
4365 if (*input_line_pointer == '\n')
4366 c = '\n';
4369 while (c == ',');
4371 demand_empty_rest_of_line ();
4374 /* .mem.offset offset, base
4375 "base" is used to distinguish between offsets from a different base. */
4377 static void
4378 dot_mem_offset (dummy)
4379 int dummy ATTRIBUTE_UNUSED;
4381 md.mem_offset.hint = 1;
4382 md.mem_offset.offset = get_absolute_expression ();
4383 if (*input_line_pointer != ',')
4385 as_bad (_("Comma expected"));
4386 ignore_rest_of_line ();
4387 return;
4389 ++input_line_pointer;
4390 md.mem_offset.base = get_absolute_expression ();
4391 demand_empty_rest_of_line ();
4394 /* ia64-specific pseudo-ops: */
4395 const pseudo_typeS md_pseudo_table[] =
4397 { "radix", dot_radix, 0 },
4398 { "lcomm", s_lcomm_bytes, 1 },
4399 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4400 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4401 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4402 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4403 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4404 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4405 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4406 { "proc", dot_proc, 0 },
4407 { "body", dot_body, 0 },
4408 { "prologue", dot_prologue, 0 },
4409 { "endp", dot_endp, 0 },
4410 { "file", dwarf2_directive_file, 0 },
4411 { "loc", dwarf2_directive_loc, 0 },
4413 { "fframe", dot_fframe, 0 },
4414 { "vframe", dot_vframe, 0 },
4415 { "vframesp", dot_vframesp, 0 },
4416 { "vframepsp", dot_vframepsp, 0 },
4417 { "save", dot_save, 0 },
4418 { "restore", dot_restore, 0 },
4419 { "restorereg", dot_restorereg, 0 },
4420 { "restorereg.p", dot_restorereg_p, 0 },
4421 { "handlerdata", dot_handlerdata, 0 },
4422 { "unwentry", dot_unwentry, 0 },
4423 { "altrp", dot_altrp, 0 },
4424 { "savesp", dot_savemem, 0 },
4425 { "savepsp", dot_savemem, 1 },
4426 { "save.g", dot_saveg, 0 },
4427 { "save.f", dot_savef, 0 },
4428 { "save.b", dot_saveb, 0 },
4429 { "save.gf", dot_savegf, 0 },
4430 { "spill", dot_spill, 0 },
4431 { "spillreg", dot_spillreg, 0 },
4432 { "spillsp", dot_spillmem, 0 },
4433 { "spillpsp", dot_spillmem, 1 },
4434 { "spillreg.p", dot_spillreg_p, 0 },
4435 { "spillsp.p", dot_spillmem_p, 0 },
4436 { "spillpsp.p", dot_spillmem_p, 1 },
4437 { "label_state", dot_label_state, 0 },
4438 { "copy_state", dot_copy_state, 0 },
4439 { "unwabi", dot_unwabi, 0 },
4440 { "personality", dot_personality, 0 },
4441 #if 0
4442 { "estate", dot_estate, 0 },
4443 #endif
4444 { "mii", dot_template, 0x0 },
4445 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4446 { "mlx", dot_template, 0x2 },
4447 { "mmi", dot_template, 0x4 },
4448 { "mfi", dot_template, 0x6 },
4449 { "mmf", dot_template, 0x7 },
4450 { "mib", dot_template, 0x8 },
4451 { "mbb", dot_template, 0x9 },
4452 { "bbb", dot_template, 0xb },
4453 { "mmb", dot_template, 0xc },
4454 { "mfb", dot_template, 0xe },
4455 #if 0
4456 { "lb", dot_scope, 0 },
4457 { "le", dot_scope, 1 },
4458 #endif
4459 { "align", s_align_bytes, 0 },
4460 { "regstk", dot_regstk, 0 },
4461 { "rotr", dot_rot, DYNREG_GR },
4462 { "rotf", dot_rot, DYNREG_FR },
4463 { "rotp", dot_rot, DYNREG_PR },
4464 { "lsb", dot_byteorder, 0 },
4465 { "msb", dot_byteorder, 1 },
4466 { "psr", dot_psr, 0 },
4467 { "alias", dot_alias, 0 },
4468 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4470 { "xdata1", dot_xdata, 1 },
4471 { "xdata2", dot_xdata, 2 },
4472 { "xdata4", dot_xdata, 4 },
4473 { "xdata8", dot_xdata, 8 },
4474 { "xreal4", dot_xfloat_cons, 'f' },
4475 { "xreal8", dot_xfloat_cons, 'd' },
4476 { "xreal10", dot_xfloat_cons, 'x' },
4477 { "xstring", dot_xstringer, 0 },
4478 { "xstringz", dot_xstringer, 1 },
4480 /* unaligned versions: */
4481 { "xdata2.ua", dot_xdata_ua, 2 },
4482 { "xdata4.ua", dot_xdata_ua, 4 },
4483 { "xdata8.ua", dot_xdata_ua, 8 },
4484 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4485 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4486 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4488 /* annotations/DV checking support */
4489 { "entry", dot_entry, 0 },
4490 { "mem.offset", dot_mem_offset, 0 },
4491 { "pred.rel", dot_pred_rel, 0 },
4492 { "pred.rel.clear", dot_pred_rel, 'c' },
4493 { "pred.rel.imply", dot_pred_rel, 'i' },
4494 { "pred.rel.mutex", dot_pred_rel, 'm' },
4495 { "pred.safe_across_calls", dot_pred_rel, 's' },
4496 { "reg.val", dot_reg_val, 0 },
4497 { "auto", dot_dv_mode, 'a' },
4498 { "explicit", dot_dv_mode, 'e' },
4499 { "default", dot_dv_mode, 'd' },
4501 { NULL, 0, 0 }
4504 static const struct pseudo_opcode
4506 const char *name;
4507 void (*handler) (int);
4508 int arg;
4510 pseudo_opcode[] =
4512 /* these are more like pseudo-ops, but don't start with a dot */
4513 { "data1", cons, 1 },
4514 { "data2", cons, 2 },
4515 { "data4", cons, 4 },
4516 { "data8", cons, 8 },
4517 { "real4", stmt_float_cons, 'f' },
4518 { "real8", stmt_float_cons, 'd' },
4519 { "real10", stmt_float_cons, 'x' },
4520 { "string", stringer, 0 },
4521 { "stringz", stringer, 1 },
4523 /* unaligned versions: */
4524 { "data2.ua", stmt_cons_ua, 2 },
4525 { "data4.ua", stmt_cons_ua, 4 },
4526 { "data8.ua", stmt_cons_ua, 8 },
4527 { "real4.ua", float_cons, 'f' },
4528 { "real8.ua", float_cons, 'd' },
4529 { "real10.ua", float_cons, 'x' },
4532 /* Declare a register by creating a symbol for it and entering it in
4533 the symbol table. */
4535 static symbolS *
4536 declare_register (name, regnum)
4537 const char *name;
4538 int regnum;
4540 const char *err;
4541 symbolS *sym;
4543 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4545 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4546 if (err)
4547 as_fatal ("Inserting \"%s\" into register table failed: %s",
4548 name, err);
4550 return sym;
4553 static void
4554 declare_register_set (prefix, num_regs, base_regnum)
4555 const char *prefix;
4556 int num_regs;
4557 int base_regnum;
4559 char name[8];
4560 int i;
4562 for (i = 0; i < num_regs; ++i)
4564 sprintf (name, "%s%u", prefix, i);
4565 declare_register (name, base_regnum + i);
4569 static unsigned int
4570 operand_width (opnd)
4571 enum ia64_opnd opnd;
4573 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4574 unsigned int bits = 0;
4575 int i;
4577 bits = 0;
4578 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4579 bits += odesc->field[i].bits;
4581 return bits;
4584 static int
4585 operand_match (idesc, index, e)
4586 const struct ia64_opcode *idesc;
4587 int index;
4588 expressionS *e;
4590 enum ia64_opnd opnd = idesc->operands[index];
4591 int bits, relocatable = 0;
4592 struct insn_fix *fix;
4593 bfd_signed_vma val;
4595 switch (opnd)
4597 /* constants: */
4599 case IA64_OPND_AR_CCV:
4600 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4601 return 1;
4602 break;
4604 case IA64_OPND_AR_PFS:
4605 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4606 return 1;
4607 break;
4609 case IA64_OPND_GR0:
4610 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4611 return 1;
4612 break;
4614 case IA64_OPND_IP:
4615 if (e->X_op == O_register && e->X_add_number == REG_IP)
4616 return 1;
4617 break;
4619 case IA64_OPND_PR:
4620 if (e->X_op == O_register && e->X_add_number == REG_PR)
4621 return 1;
4622 break;
4624 case IA64_OPND_PR_ROT:
4625 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4626 return 1;
4627 break;
4629 case IA64_OPND_PSR:
4630 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4631 return 1;
4632 break;
4634 case IA64_OPND_PSR_L:
4635 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4636 return 1;
4637 break;
4639 case IA64_OPND_PSR_UM:
4640 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4641 return 1;
4642 break;
4644 case IA64_OPND_C1:
4645 if (e->X_op == O_constant && e->X_add_number == 1)
4646 return 1;
4647 break;
4649 case IA64_OPND_C8:
4650 if (e->X_op == O_constant && e->X_add_number == 8)
4651 return 1;
4652 break;
4654 case IA64_OPND_C16:
4655 if (e->X_op == O_constant && e->X_add_number == 16)
4656 return 1;
4657 break;
4659 /* register operands: */
4661 case IA64_OPND_AR3:
4662 if (e->X_op == O_register && e->X_add_number >= REG_AR
4663 && e->X_add_number < REG_AR + 128)
4664 return 1;
4665 break;
4667 case IA64_OPND_B1:
4668 case IA64_OPND_B2:
4669 if (e->X_op == O_register && e->X_add_number >= REG_BR
4670 && e->X_add_number < REG_BR + 8)
4671 return 1;
4672 break;
4674 case IA64_OPND_CR3:
4675 if (e->X_op == O_register && e->X_add_number >= REG_CR
4676 && e->X_add_number < REG_CR + 128)
4677 return 1;
4678 break;
4680 case IA64_OPND_F1:
4681 case IA64_OPND_F2:
4682 case IA64_OPND_F3:
4683 case IA64_OPND_F4:
4684 if (e->X_op == O_register && e->X_add_number >= REG_FR
4685 && e->X_add_number < REG_FR + 128)
4686 return 1;
4687 break;
4689 case IA64_OPND_P1:
4690 case IA64_OPND_P2:
4691 if (e->X_op == O_register && e->X_add_number >= REG_P
4692 && e->X_add_number < REG_P + 64)
4693 return 1;
4694 break;
4696 case IA64_OPND_R1:
4697 case IA64_OPND_R2:
4698 case IA64_OPND_R3:
4699 if (e->X_op == O_register && e->X_add_number >= REG_GR
4700 && e->X_add_number < REG_GR + 128)
4701 return 1;
4702 break;
4704 case IA64_OPND_R3_2:
4705 if (e->X_op == O_register && e->X_add_number >= REG_GR
4706 && e->X_add_number < REG_GR + 4)
4707 return 1;
4708 break;
4710 /* indirect operands: */
4711 case IA64_OPND_CPUID_R3:
4712 case IA64_OPND_DBR_R3:
4713 case IA64_OPND_DTR_R3:
4714 case IA64_OPND_ITR_R3:
4715 case IA64_OPND_IBR_R3:
4716 case IA64_OPND_MSR_R3:
4717 case IA64_OPND_PKR_R3:
4718 case IA64_OPND_PMC_R3:
4719 case IA64_OPND_PMD_R3:
4720 case IA64_OPND_RR_R3:
4721 if (e->X_op == O_index && e->X_op_symbol
4722 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4723 == opnd - IA64_OPND_CPUID_R3))
4724 return 1;
4725 break;
4727 case IA64_OPND_MR3:
4728 if (e->X_op == O_index && !e->X_op_symbol)
4729 return 1;
4730 break;
4732 /* immediate operands: */
4733 case IA64_OPND_CNT2a:
4734 case IA64_OPND_LEN4:
4735 case IA64_OPND_LEN6:
4736 bits = operand_width (idesc->operands[index]);
4737 if (e->X_op == O_constant
4738 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4739 return 1;
4740 break;
4742 case IA64_OPND_CNT2b:
4743 if (e->X_op == O_constant
4744 && (bfd_vma) (e->X_add_number - 1) < 3)
4745 return 1;
4746 break;
4748 case IA64_OPND_CNT2c:
4749 val = e->X_add_number;
4750 if (e->X_op == O_constant
4751 && (val == 0 || val == 7 || val == 15 || val == 16))
4752 return 1;
4753 break;
4755 case IA64_OPND_SOR:
4756 /* SOR must be an integer multiple of 8 */
4757 if (e->X_add_number & 0x7)
4758 break;
4759 case IA64_OPND_SOF:
4760 case IA64_OPND_SOL:
4761 if (e->X_op == O_constant &&
4762 (bfd_vma) e->X_add_number <= 96)
4763 return 1;
4764 break;
4766 case IA64_OPND_IMMU62:
4767 if (e->X_op == O_constant)
4769 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
4770 return 1;
4772 else
4774 /* FIXME -- need 62-bit relocation type */
4775 as_bad (_("62-bit relocation not yet implemented"));
4777 break;
4779 case IA64_OPND_IMMU64:
4780 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4781 || e->X_op == O_subtract)
4783 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4784 fix->code = BFD_RELOC_IA64_IMM64;
4785 if (e->X_op != O_subtract)
4787 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4788 if (e->X_op == O_pseudo_fixup)
4789 e->X_op = O_symbol;
4792 fix->opnd = idesc->operands[index];
4793 fix->expr = *e;
4794 fix->is_pcrel = 0;
4795 ++CURR_SLOT.num_fixups;
4796 return 1;
4798 else if (e->X_op == O_constant)
4799 return 1;
4800 break;
4802 case IA64_OPND_CCNT5:
4803 case IA64_OPND_CNT5:
4804 case IA64_OPND_CNT6:
4805 case IA64_OPND_CPOS6a:
4806 case IA64_OPND_CPOS6b:
4807 case IA64_OPND_CPOS6c:
4808 case IA64_OPND_IMMU2:
4809 case IA64_OPND_IMMU7a:
4810 case IA64_OPND_IMMU7b:
4811 case IA64_OPND_IMMU21:
4812 case IA64_OPND_IMMU24:
4813 case IA64_OPND_MBTYPE4:
4814 case IA64_OPND_MHTYPE8:
4815 case IA64_OPND_POS6:
4816 bits = operand_width (idesc->operands[index]);
4817 if (e->X_op == O_constant
4818 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4819 return 1;
4820 break;
4822 case IA64_OPND_IMMU9:
4823 bits = operand_width (idesc->operands[index]);
4824 if (e->X_op == O_constant
4825 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4827 int lobits = e->X_add_number & 0x3;
4828 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
4829 e->X_add_number |= (bfd_vma) 0x3;
4830 return 1;
4832 break;
4834 case IA64_OPND_IMM44:
4835 /* least 16 bits must be zero */
4836 if ((e->X_add_number & 0xffff) != 0)
4837 as_warn (_("lower 16 bits of mask ignored"));
4839 if (e->X_op == O_constant
4840 && ((e->X_add_number >= 0
4841 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44))
4842 || (e->X_add_number < 0
4843 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44))))
4845 /* sign-extend */
4846 if (e->X_add_number >= 0
4847 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
4849 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
4851 return 1;
4853 break;
4855 case IA64_OPND_IMM17:
4856 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4857 if (e->X_op == O_constant
4858 && ((e->X_add_number >= 0
4859 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17))
4860 || (e->X_add_number < 0
4861 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17))))
4863 /* sign-extend */
4864 if (e->X_add_number >= 0
4865 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
4867 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
4869 return 1;
4871 break;
4873 case IA64_OPND_IMM14:
4874 case IA64_OPND_IMM22:
4875 relocatable = 1;
4876 case IA64_OPND_IMM1:
4877 case IA64_OPND_IMM8:
4878 case IA64_OPND_IMM8U4:
4879 case IA64_OPND_IMM8M1:
4880 case IA64_OPND_IMM8M1U4:
4881 case IA64_OPND_IMM8M1U8:
4882 case IA64_OPND_IMM9a:
4883 case IA64_OPND_IMM9b:
4884 bits = operand_width (idesc->operands[index]);
4885 if (relocatable && (e->X_op == O_symbol
4886 || e->X_op == O_subtract
4887 || e->X_op == O_pseudo_fixup))
4889 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4891 if (idesc->operands[index] == IA64_OPND_IMM14)
4892 fix->code = BFD_RELOC_IA64_IMM14;
4893 else
4894 fix->code = BFD_RELOC_IA64_IMM22;
4896 if (e->X_op != O_subtract)
4898 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4899 if (e->X_op == O_pseudo_fixup)
4900 e->X_op = O_symbol;
4903 fix->opnd = idesc->operands[index];
4904 fix->expr = *e;
4905 fix->is_pcrel = 0;
4906 ++CURR_SLOT.num_fixups;
4907 return 1;
4909 else if (e->X_op != O_constant
4910 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
4911 return 0;
4913 if (opnd == IA64_OPND_IMM8M1U4)
4915 /* Zero is not valid for unsigned compares that take an adjusted
4916 constant immediate range. */
4917 if (e->X_add_number == 0)
4918 return 0;
4920 /* Sign-extend 32-bit unsigned numbers, so that the following range
4921 checks will work. */
4922 val = e->X_add_number;
4923 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4924 && ((val & ((bfd_vma) 1 << 31)) != 0))
4925 val = ((val << 32) >> 32);
4927 /* Check for 0x100000000. This is valid because
4928 0x100000000-1 is the same as ((uint32_t) -1). */
4929 if (val == ((bfd_signed_vma) 1 << 32))
4930 return 1;
4932 val = val - 1;
4934 else if (opnd == IA64_OPND_IMM8M1U8)
4936 /* Zero is not valid for unsigned compares that take an adjusted
4937 constant immediate range. */
4938 if (e->X_add_number == 0)
4939 return 0;
4941 /* Check for 0x10000000000000000. */
4942 if (e->X_op == O_big)
4944 if (generic_bignum[0] == 0
4945 && generic_bignum[1] == 0
4946 && generic_bignum[2] == 0
4947 && generic_bignum[3] == 0
4948 && generic_bignum[4] == 1)
4949 return 1;
4950 else
4951 return 0;
4953 else
4954 val = e->X_add_number - 1;
4956 else if (opnd == IA64_OPND_IMM8M1)
4957 val = e->X_add_number - 1;
4958 else if (opnd == IA64_OPND_IMM8U4)
4960 /* Sign-extend 32-bit unsigned numbers, so that the following range
4961 checks will work. */
4962 val = e->X_add_number;
4963 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4964 && ((val & ((bfd_vma) 1 << 31)) != 0))
4965 val = ((val << 32) >> 32);
4967 else
4968 val = e->X_add_number;
4970 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1)))
4971 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1))))
4972 return 1;
4973 break;
4975 case IA64_OPND_INC3:
4976 /* +/- 1, 4, 8, 16 */
4977 val = e->X_add_number;
4978 if (val < 0)
4979 val = -val;
4980 if (e->X_op == O_constant
4981 && (val == 1 || val == 4 || val == 8 || val == 16))
4982 return 1;
4983 break;
4985 case IA64_OPND_TGT25:
4986 case IA64_OPND_TGT25b:
4987 case IA64_OPND_TGT25c:
4988 case IA64_OPND_TGT64:
4989 if (e->X_op == O_symbol)
4991 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4992 if (opnd == IA64_OPND_TGT25)
4993 fix->code = BFD_RELOC_IA64_PCREL21F;
4994 else if (opnd == IA64_OPND_TGT25b)
4995 fix->code = BFD_RELOC_IA64_PCREL21M;
4996 else if (opnd == IA64_OPND_TGT25c)
4997 fix->code = BFD_RELOC_IA64_PCREL21B;
4998 else if (opnd == IA64_OPND_TGT64)
4999 fix->code = BFD_RELOC_IA64_PCREL60B;
5000 else
5001 abort ();
5003 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5004 fix->opnd = idesc->operands[index];
5005 fix->expr = *e;
5006 fix->is_pcrel = 1;
5007 ++CURR_SLOT.num_fixups;
5008 return 1;
5010 case IA64_OPND_TAG13:
5011 case IA64_OPND_TAG13b:
5012 switch (e->X_op)
5014 case O_constant:
5015 return 1;
5017 case O_symbol:
5018 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5019 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
5020 fix->opnd = idesc->operands[index];
5021 fix->expr = *e;
5022 fix->is_pcrel = 1;
5023 ++CURR_SLOT.num_fixups;
5024 return 1;
5026 default:
5027 break;
5029 break;
5031 default:
5032 break;
5034 return 0;
5037 static int
5038 parse_operand (e)
5039 expressionS *e;
5041 int sep = '\0';
5043 memset (e, 0, sizeof (*e));
5044 e->X_op = O_absent;
5045 SKIP_WHITESPACE ();
5046 if (*input_line_pointer != '}')
5047 expression (e);
5048 sep = *input_line_pointer++;
5050 if (sep == '}')
5052 if (!md.manual_bundling)
5053 as_warn ("Found '}' when manual bundling is off");
5054 else
5055 CURR_SLOT.manual_bundling_off = 1;
5056 md.manual_bundling = 0;
5057 sep = '\0';
5059 return sep;
5062 /* Returns the next entry in the opcode table that matches the one in
5063 IDESC, and frees the entry in IDESC. If no matching entry is
5064 found, NULL is returned instead. */
5066 static struct ia64_opcode *
5067 get_next_opcode (struct ia64_opcode *idesc)
5069 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
5070 ia64_free_opcode (idesc);
5071 return next;
5074 /* Parse the operands for the opcode and find the opcode variant that
5075 matches the specified operands, or NULL if no match is possible. */
5077 static struct ia64_opcode *
5078 parse_operands (idesc)
5079 struct ia64_opcode *idesc;
5081 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
5082 int sep = 0;
5083 enum ia64_opnd expected_operand = IA64_OPND_NIL;
5084 char mnemonic[129];
5085 char *first_arg = 0, *end, *saved_input_pointer;
5086 unsigned int sof;
5088 assert (strlen (idesc->name) <= 128);
5090 strcpy (mnemonic, idesc->name);
5091 if (idesc->operands[2] == IA64_OPND_SOF)
5093 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5094 can't parse the first operand until we have parsed the
5095 remaining operands of the "alloc" instruction. */
5096 SKIP_WHITESPACE ();
5097 first_arg = input_line_pointer;
5098 end = strchr (input_line_pointer, '=');
5099 if (!end)
5101 as_bad ("Expected separator `='");
5102 return 0;
5104 input_line_pointer = end + 1;
5105 ++i;
5106 ++num_outputs;
5109 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5111 sep = parse_operand (CURR_SLOT.opnd + i);
5112 if (CURR_SLOT.opnd[i].X_op == O_absent)
5113 break;
5115 ++num_operands;
5117 if (sep != '=' && sep != ',')
5118 break;
5120 if (sep == '=')
5122 if (num_outputs > 0)
5123 as_bad ("Duplicate equal sign (=) in instruction");
5124 else
5125 num_outputs = i + 1;
5128 if (sep != '\0')
5130 as_bad ("Illegal operand separator `%c'", sep);
5131 return 0;
5134 if (idesc->operands[2] == IA64_OPND_SOF)
5136 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5137 know (strcmp (idesc->name, "alloc") == 0);
5138 if (num_operands == 5 /* first_arg not included in this count! */
5139 && CURR_SLOT.opnd[2].X_op == O_constant
5140 && CURR_SLOT.opnd[3].X_op == O_constant
5141 && CURR_SLOT.opnd[4].X_op == O_constant
5142 && CURR_SLOT.opnd[5].X_op == O_constant)
5144 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5145 CURR_SLOT.opnd[3].X_add_number,
5146 CURR_SLOT.opnd[4].X_add_number,
5147 CURR_SLOT.opnd[5].X_add_number);
5149 /* now we can parse the first arg: */
5150 saved_input_pointer = input_line_pointer;
5151 input_line_pointer = first_arg;
5152 sep = parse_operand (CURR_SLOT.opnd + 0);
5153 if (sep != '=')
5154 --num_outputs; /* force error */
5155 input_line_pointer = saved_input_pointer;
5157 CURR_SLOT.opnd[2].X_add_number = sof;
5158 CURR_SLOT.opnd[3].X_add_number
5159 = sof - CURR_SLOT.opnd[4].X_add_number;
5160 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5164 highest_unmatched_operand = 0;
5165 expected_operand = idesc->operands[0];
5166 for (; idesc; idesc = get_next_opcode (idesc))
5168 if (num_outputs != idesc->num_outputs)
5169 continue; /* mismatch in # of outputs */
5171 CURR_SLOT.num_fixups = 0;
5172 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5173 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
5174 break;
5176 if (i != num_operands)
5178 if (i > highest_unmatched_operand)
5180 highest_unmatched_operand = i;
5181 expected_operand = idesc->operands[i];
5183 continue;
5186 if (num_operands < NELEMS (idesc->operands)
5187 && idesc->operands[num_operands])
5188 continue; /* mismatch in number of arguments */
5190 break;
5192 if (!idesc)
5194 if (expected_operand)
5195 as_bad ("Operand %u of `%s' should be %s",
5196 highest_unmatched_operand + 1, mnemonic,
5197 elf64_ia64_operands[expected_operand].desc);
5198 else
5199 as_bad ("Operand mismatch");
5200 return 0;
5202 return idesc;
5205 /* Keep track of state necessary to determine whether a NOP is necessary
5206 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5207 detect a case where additional NOPs may be necessary. */
5208 static int
5209 errata_nop_necessary_p (slot, insn_unit)
5210 struct slot *slot;
5211 enum ia64_unit insn_unit;
5213 int i;
5214 struct group *this_group = md.last_groups + md.group_idx;
5215 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3;
5216 struct ia64_opcode *idesc = slot->idesc;
5218 /* Test whether this could be the first insn in a problematic sequence. */
5219 if (insn_unit == IA64_UNIT_F)
5221 for (i = 0; i < idesc->num_outputs; i++)
5222 if (idesc->operands[i] == IA64_OPND_P1
5223 || idesc->operands[i] == IA64_OPND_P2)
5225 int regno = slot->opnd[i].X_add_number - REG_P;
5226 /* Ignore invalid operands; they generate errors elsewhere. */
5227 if (regno >= 64)
5228 return 0;
5229 this_group->p_reg_set[regno] = 1;
5233 /* Test whether this could be the second insn in a problematic sequence. */
5234 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0
5235 && prev_group->p_reg_set[slot->qp_regno])
5237 for (i = 0; i < idesc->num_outputs; i++)
5238 if (idesc->operands[i] == IA64_OPND_R1
5239 || idesc->operands[i] == IA64_OPND_R2
5240 || idesc->operands[i] == IA64_OPND_R3)
5242 int regno = slot->opnd[i].X_add_number - REG_GR;
5243 /* Ignore invalid operands; they generate errors elsewhere. */
5244 if (regno >= 128)
5245 return 0;
5246 if (strncmp (idesc->name, "add", 3) != 0
5247 && strncmp (idesc->name, "sub", 3) != 0
5248 && strncmp (idesc->name, "shladd", 6) != 0
5249 && (idesc->flags & IA64_OPCODE_POSTINC) == 0)
5250 this_group->g_reg_set_conditionally[regno] = 1;
5254 /* Test whether this could be the third insn in a problematic sequence. */
5255 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++)
5257 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5258 idesc->operands[i] == IA64_OPND_R3
5259 /* For mov indirect. */
5260 || idesc->operands[i] == IA64_OPND_RR_R3
5261 || idesc->operands[i] == IA64_OPND_DBR_R3
5262 || idesc->operands[i] == IA64_OPND_IBR_R3
5263 || idesc->operands[i] == IA64_OPND_PKR_R3
5264 || idesc->operands[i] == IA64_OPND_PMC_R3
5265 || idesc->operands[i] == IA64_OPND_PMD_R3
5266 || idesc->operands[i] == IA64_OPND_MSR_R3
5267 || idesc->operands[i] == IA64_OPND_CPUID_R3
5268 /* For itr. */
5269 || idesc->operands[i] == IA64_OPND_ITR_R3
5270 || idesc->operands[i] == IA64_OPND_DTR_R3
5271 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5272 || idesc->operands[i] == IA64_OPND_MR3)
5274 int regno = slot->opnd[i].X_add_number - REG_GR;
5275 /* Ignore invalid operands; they generate errors elsewhere. */
5276 if (regno >= 128)
5277 return 0;
5278 if (idesc->operands[i] == IA64_OPND_R3)
5280 if (strcmp (idesc->name, "fc") != 0
5281 && strcmp (idesc->name, "tak") != 0
5282 && strcmp (idesc->name, "thash") != 0
5283 && strcmp (idesc->name, "tpa") != 0
5284 && strcmp (idesc->name, "ttag") != 0
5285 && strncmp (idesc->name, "ptr", 3) != 0
5286 && strncmp (idesc->name, "ptc", 3) != 0
5287 && strncmp (idesc->name, "probe", 5) != 0)
5288 return 0;
5290 if (prev_group->g_reg_set_conditionally[regno])
5291 return 1;
5294 return 0;
5297 static void
5298 build_insn (slot, insnp)
5299 struct slot *slot;
5300 bfd_vma *insnp;
5302 const struct ia64_operand *odesc, *o2desc;
5303 struct ia64_opcode *idesc = slot->idesc;
5304 bfd_signed_vma insn, val;
5305 const char *err;
5306 int i;
5308 insn = idesc->opcode | slot->qp_regno;
5310 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5312 if (slot->opnd[i].X_op == O_register
5313 || slot->opnd[i].X_op == O_constant
5314 || slot->opnd[i].X_op == O_index)
5315 val = slot->opnd[i].X_add_number;
5316 else if (slot->opnd[i].X_op == O_big)
5318 /* This must be the value 0x10000000000000000. */
5319 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5320 val = 0;
5322 else
5323 val = 0;
5325 switch (idesc->operands[i])
5327 case IA64_OPND_IMMU64:
5328 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5329 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5330 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5331 | (((val >> 63) & 0x1) << 36));
5332 continue;
5334 case IA64_OPND_IMMU62:
5335 val &= 0x3fffffffffffffffULL;
5336 if (val != slot->opnd[i].X_add_number)
5337 as_warn (_("Value truncated to 62 bits"));
5338 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5339 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
5340 continue;
5342 case IA64_OPND_TGT64:
5343 val >>= 4;
5344 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5345 insn |= ((((val >> 59) & 0x1) << 36)
5346 | (((val >> 0) & 0xfffff) << 13));
5347 continue;
5349 case IA64_OPND_AR3:
5350 val -= REG_AR;
5351 break;
5353 case IA64_OPND_B1:
5354 case IA64_OPND_B2:
5355 val -= REG_BR;
5356 break;
5358 case IA64_OPND_CR3:
5359 val -= REG_CR;
5360 break;
5362 case IA64_OPND_F1:
5363 case IA64_OPND_F2:
5364 case IA64_OPND_F3:
5365 case IA64_OPND_F4:
5366 val -= REG_FR;
5367 break;
5369 case IA64_OPND_P1:
5370 case IA64_OPND_P2:
5371 val -= REG_P;
5372 break;
5374 case IA64_OPND_R1:
5375 case IA64_OPND_R2:
5376 case IA64_OPND_R3:
5377 case IA64_OPND_R3_2:
5378 case IA64_OPND_CPUID_R3:
5379 case IA64_OPND_DBR_R3:
5380 case IA64_OPND_DTR_R3:
5381 case IA64_OPND_ITR_R3:
5382 case IA64_OPND_IBR_R3:
5383 case IA64_OPND_MR3:
5384 case IA64_OPND_MSR_R3:
5385 case IA64_OPND_PKR_R3:
5386 case IA64_OPND_PMC_R3:
5387 case IA64_OPND_PMD_R3:
5388 case IA64_OPND_RR_R3:
5389 val -= REG_GR;
5390 break;
5392 default:
5393 break;
5396 odesc = elf64_ia64_operands + idesc->operands[i];
5397 err = (*odesc->insert) (odesc, val, &insn);
5398 if (err)
5399 as_bad_where (slot->src_file, slot->src_line,
5400 "Bad operand value: %s", err);
5401 if (idesc->flags & IA64_OPCODE_PSEUDO)
5403 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5404 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5406 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5407 (*o2desc->insert) (o2desc, val, &insn);
5409 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5410 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5411 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
5413 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5414 (*o2desc->insert) (o2desc, 64 - val, &insn);
5418 *insnp = insn;
5421 static void
5422 emit_one_bundle ()
5424 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5425 unsigned int manual_bundling = 0;
5426 enum ia64_unit required_unit, insn_unit = 0;
5427 enum ia64_insn_type type[3], insn_type;
5428 unsigned int template, orig_template;
5429 bfd_vma insn[3] = { -1, -1, -1 };
5430 struct ia64_opcode *idesc;
5431 int end_of_insn_group = 0, user_template = -1;
5432 int n, i, j, first, curr;
5433 unw_rec_list *ptr;
5434 bfd_vma t0 = 0, t1 = 0;
5435 struct label_fix *lfix;
5436 struct insn_fix *ifix;
5437 char mnemonic[16];
5438 fixS *fix;
5439 char *f;
5441 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5442 know (first >= 0 & first < NUM_SLOTS);
5443 n = MIN (3, md.num_slots_in_use);
5445 /* Determine template: user user_template if specified, best match
5446 otherwise: */
5448 if (md.slot[first].user_template >= 0)
5449 user_template = template = md.slot[first].user_template;
5450 else
5452 /* Auto select appropriate template. */
5453 memset (type, 0, sizeof (type));
5454 curr = first;
5455 for (i = 0; i < n; ++i)
5457 if (md.slot[curr].label_fixups && i != 0)
5458 break;
5459 type[i] = md.slot[curr].idesc->type;
5460 curr = (curr + 1) % NUM_SLOTS;
5462 template = best_template[type[0]][type[1]][type[2]];
5465 /* initialize instructions with appropriate nops: */
5466 for (i = 0; i < 3; ++i)
5467 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5469 f = frag_more (16);
5471 /* now fill in slots with as many insns as possible: */
5472 curr = first;
5473 idesc = md.slot[curr].idesc;
5474 end_of_insn_group = 0;
5475 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5477 /* Set the slot number for prologue/body records now as those
5478 refer to the current point, not the point after the
5479 instruction has been issued: */
5480 /* Don't try to delete prologue/body records here, as that will cause
5481 them to also be deleted from the master list of unwind records. */
5482 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5483 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5484 || ptr->r.type == body)
5486 ptr->slot_number = (unsigned long) f + i;
5487 ptr->slot_frag = frag_now;
5490 if (idesc->flags & IA64_OPCODE_SLOT2)
5492 if (manual_bundling && i != 2)
5493 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5494 "`%s' must be last in bundle", idesc->name);
5495 else
5496 i = 2;
5498 if (idesc->flags & IA64_OPCODE_LAST)
5500 int required_slot;
5501 unsigned int required_template;
5503 /* If we need a stop bit after an M slot, our only choice is
5504 template 5 (M;;MI). If we need a stop bit after a B
5505 slot, our only choice is to place it at the end of the
5506 bundle, because the only available templates are MIB,
5507 MBB, BBB, MMB, and MFB. We don't handle anything other
5508 than M and B slots because these are the only kind of
5509 instructions that can have the IA64_OPCODE_LAST bit set. */
5510 required_template = template;
5511 switch (idesc->type)
5513 case IA64_TYPE_M:
5514 required_slot = 0;
5515 required_template = 5;
5516 break;
5518 case IA64_TYPE_B:
5519 required_slot = 2;
5520 break;
5522 default:
5523 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5524 "Internal error: don't know how to force %s to end"
5525 "of instruction group", idesc->name);
5526 required_slot = i;
5527 break;
5529 if (manual_bundling && i != required_slot)
5530 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5531 "`%s' must be last in instruction group",
5532 idesc->name);
5533 if (required_slot < i)
5534 /* Can't fit this instruction. */
5535 break;
5537 i = required_slot;
5538 if (required_template != template)
5540 /* If we switch the template, we need to reset the NOPs
5541 after slot i. The slot-types of the instructions ahead
5542 of i never change, so we don't need to worry about
5543 changing NOPs in front of this slot. */
5544 for (j = i; j < 3; ++j)
5545 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5547 template = required_template;
5549 if (curr != first && md.slot[curr].label_fixups)
5551 if (manual_bundling_on)
5552 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5553 "Label must be first in a bundle");
5554 /* This insn must go into the first slot of a bundle. */
5555 break;
5558 manual_bundling_on = md.slot[curr].manual_bundling_on;
5559 manual_bundling_off = md.slot[curr].manual_bundling_off;
5561 if (manual_bundling_on)
5563 if (curr == first)
5564 manual_bundling = 1;
5565 else
5566 break; /* need to start a new bundle */
5569 if (end_of_insn_group && md.num_slots_in_use >= 1)
5571 /* We need an instruction group boundary in the middle of a
5572 bundle. See if we can switch to an other template with
5573 an appropriate boundary. */
5575 orig_template = template;
5576 if (i == 1 && (user_template == 4
5577 || (user_template < 0
5578 && (ia64_templ_desc[template].exec_unit[0]
5579 == IA64_UNIT_M))))
5581 template = 5;
5582 end_of_insn_group = 0;
5584 else if (i == 2 && (user_template == 0
5585 || (user_template < 0
5586 && (ia64_templ_desc[template].exec_unit[1]
5587 == IA64_UNIT_I)))
5588 /* This test makes sure we don't switch the template if
5589 the next instruction is one that needs to be first in
5590 an instruction group. Since all those instructions are
5591 in the M group, there is no way such an instruction can
5592 fit in this bundle even if we switch the template. The
5593 reason we have to check for this is that otherwise we
5594 may end up generating "MI;;I M.." which has the deadly
5595 effect that the second M instruction is no longer the
5596 first in the bundle! --davidm 99/12/16 */
5597 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5599 template = 1;
5600 end_of_insn_group = 0;
5602 else if (curr != first)
5603 /* can't fit this insn */
5604 break;
5606 if (template != orig_template)
5607 /* if we switch the template, we need to reset the NOPs
5608 after slot i. The slot-types of the instructions ahead
5609 of i never change, so we don't need to worry about
5610 changing NOPs in front of this slot. */
5611 for (j = i; j < 3; ++j)
5612 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5614 required_unit = ia64_templ_desc[template].exec_unit[i];
5616 /* resolve dynamic opcodes such as "break" and "nop": */
5617 if (idesc->type == IA64_TYPE_DYN)
5619 if ((strcmp (idesc->name, "nop") == 0)
5620 || (strcmp (idesc->name, "break") == 0))
5621 insn_unit = required_unit;
5622 else if (strcmp (idesc->name, "chk.s") == 0)
5624 insn_unit = IA64_UNIT_M;
5625 if (required_unit == IA64_UNIT_I)
5626 insn_unit = IA64_UNIT_I;
5628 else
5629 as_fatal ("emit_one_bundle: unexpected dynamic op");
5631 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
5632 ia64_free_opcode (idesc);
5633 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5634 #if 0
5635 know (!idesc->next); /* no resolved dynamic ops have collisions */
5636 #endif
5638 else
5640 insn_type = idesc->type;
5641 insn_unit = IA64_UNIT_NIL;
5642 switch (insn_type)
5644 case IA64_TYPE_A:
5645 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5646 insn_unit = required_unit;
5647 break;
5648 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
5649 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5650 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5651 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5652 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5653 default: break;
5657 if (insn_unit != required_unit)
5659 if (required_unit == IA64_UNIT_L
5660 && insn_unit == IA64_UNIT_I
5661 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5663 /* we got ourselves an MLX template but the current
5664 instruction isn't an X-unit, or an I-unit instruction
5665 that can go into the X slot of an MLX template. Duh. */
5666 if (md.num_slots_in_use >= NUM_SLOTS)
5668 as_bad_where (md.slot[curr].src_file,
5669 md.slot[curr].src_line,
5670 "`%s' can't go in X slot of "
5671 "MLX template", idesc->name);
5672 /* drop this insn so we don't livelock: */
5673 --md.num_slots_in_use;
5675 break;
5677 continue; /* try next slot */
5681 bfd_vma addr;
5683 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
5684 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5687 if (errata_nop_necessary_p (md.slot + curr, insn_unit))
5688 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
5690 build_insn (md.slot + curr, insn + i);
5692 /* Set slot counts for non prologue/body unwind records. */
5693 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5694 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
5695 && ptr->r.type != body)
5697 ptr->slot_number = (unsigned long) f + i;
5698 ptr->slot_frag = frag_now;
5700 md.slot[curr].unwind_record = NULL;
5702 if (required_unit == IA64_UNIT_L)
5704 know (i == 1);
5705 /* skip one slot for long/X-unit instructions */
5706 ++i;
5708 --md.num_slots_in_use;
5710 /* now is a good time to fix up the labels for this insn: */
5711 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5713 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5714 symbol_set_frag (lfix->sym, frag_now);
5716 /* and fix up the tags also. */
5717 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
5719 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
5720 symbol_set_frag (lfix->sym, frag_now);
5723 for (j = 0; j < md.slot[curr].num_fixups; ++j)
5725 ifix = md.slot[curr].fixup + j;
5726 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8,
5727 &ifix->expr, ifix->is_pcrel, ifix->code);
5728 fix->tc_fix_data.opnd = ifix->opnd;
5729 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
5730 fix->fx_file = md.slot[curr].src_file;
5731 fix->fx_line = md.slot[curr].src_line;
5734 end_of_insn_group = md.slot[curr].end_of_insn_group;
5736 if (end_of_insn_group)
5738 md.group_idx = (md.group_idx + 1) % 3;
5739 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]);
5742 /* clear slot: */
5743 ia64_free_opcode (md.slot[curr].idesc);
5744 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
5745 md.slot[curr].user_template = -1;
5747 if (manual_bundling_off)
5749 manual_bundling = 0;
5750 break;
5752 curr = (curr + 1) % NUM_SLOTS;
5753 idesc = md.slot[curr].idesc;
5755 if (manual_bundling)
5757 if (md.num_slots_in_use > 0)
5758 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5759 "`%s' does not fit into %s template",
5760 idesc->name, ia64_templ_desc[template].name);
5761 else
5762 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5763 "Missing '}' at end of file");
5765 know (md.num_slots_in_use < NUM_SLOTS);
5767 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
5768 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
5770 number_to_chars_littleendian (f + 0, t0, 8);
5771 number_to_chars_littleendian (f + 8, t1, 8);
5773 unwind.next_slot_number = (unsigned long) f + 16;
5774 unwind.next_slot_frag = frag_now;
5778 md_parse_option (c, arg)
5779 int c;
5780 char *arg;
5782 switch (c)
5784 /* Switches from the Intel assembler. */
5785 case 'm':
5786 if (strcmp (arg, "ilp64") == 0
5787 || strcmp (arg, "lp64") == 0
5788 || strcmp (arg, "p64") == 0)
5790 md.flags |= EF_IA_64_ABI64;
5792 else if (strcmp (arg, "ilp32") == 0)
5794 md.flags &= ~EF_IA_64_ABI64;
5796 else if (strcmp (arg, "le") == 0)
5798 md.flags &= ~EF_IA_64_BE;
5800 else if (strcmp (arg, "be") == 0)
5802 md.flags |= EF_IA_64_BE;
5804 else
5805 return 0;
5806 break;
5808 case 'N':
5809 if (strcmp (arg, "so") == 0)
5811 /* Suppress signon message. */
5813 else if (strcmp (arg, "pi") == 0)
5815 /* Reject privileged instructions. FIXME */
5817 else if (strcmp (arg, "us") == 0)
5819 /* Allow union of signed and unsigned range. FIXME */
5821 else if (strcmp (arg, "close_fcalls") == 0)
5823 /* Do not resolve global function calls. */
5825 else
5826 return 0;
5827 break;
5829 case 'C':
5830 /* temp[="prefix"] Insert temporary labels into the object file
5831 symbol table prefixed by "prefix".
5832 Default prefix is ":temp:".
5834 break;
5836 case 'a':
5837 /* ??? Conflicts with gas' listing option. */
5838 /* indirect=<tgt> Assume unannotated indirect branches behavior
5839 according to <tgt> --
5840 exit: branch out from the current context (default)
5841 labels: all labels in context may be branch targets
5843 break;
5845 case 'x':
5846 /* -X conflicts with an ignored option, use -x instead */
5847 md.detect_dv = 1;
5848 if (!arg || strcmp (arg, "explicit") == 0)
5850 /* set default mode to explicit */
5851 md.default_explicit_mode = 1;
5852 break;
5854 else if (strcmp (arg, "auto") == 0)
5856 md.default_explicit_mode = 0;
5858 else if (strcmp (arg, "debug") == 0)
5860 md.debug_dv = 1;
5862 else if (strcmp (arg, "debugx") == 0)
5864 md.default_explicit_mode = 1;
5865 md.debug_dv = 1;
5867 else
5869 as_bad (_("Unrecognized option '-x%s'"), arg);
5871 break;
5873 case 'S':
5874 /* nops Print nops statistics. */
5875 break;
5877 /* GNU specific switches for gcc. */
5878 case OPTION_MCONSTANT_GP:
5879 md.flags |= EF_IA_64_CONS_GP;
5880 break;
5882 case OPTION_MAUTO_PIC:
5883 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
5884 break;
5886 default:
5887 return 0;
5890 return 1;
5893 void
5894 md_show_usage (stream)
5895 FILE *stream;
5897 fputs (_("\
5898 IA-64 options:\n\
5899 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
5900 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
5901 -x | -xexplicit turn on dependency violation checking (default)\n\
5902 -xauto automagically remove dependency violations\n\
5903 -xdebug debug dependency violation checker\n"),
5904 stream);
5907 /* Return true if TYPE fits in TEMPL at SLOT. */
5909 static int
5910 match (int templ, int type, int slot)
5912 enum ia64_unit unit;
5913 int result;
5915 unit = ia64_templ_desc[templ].exec_unit[slot];
5916 switch (type)
5918 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
5919 case IA64_TYPE_A:
5920 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
5921 break;
5922 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
5923 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
5924 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
5925 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
5926 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
5927 default: result = 0; break;
5929 return result;
5932 /* Add a bit of extra goodness if a nop of type F or B would fit
5933 in TEMPL at SLOT. */
5935 static inline int
5936 extra_goodness (int templ, int slot)
5938 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
5939 return 2;
5940 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
5941 return 1;
5942 return 0;
5945 /* This function is called once, at assembler startup time. It sets
5946 up all the tables, etc. that the MD part of the assembler will need
5947 that can be determined before arguments are parsed. */
5948 void
5949 md_begin ()
5951 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
5952 const char *err;
5953 char name[8];
5955 md.auto_align = 1;
5956 md.explicit_mode = md.default_explicit_mode;
5958 bfd_set_section_alignment (stdoutput, text_section, 4);
5960 target_big_endian = TARGET_BYTES_BIG_ENDIAN;
5961 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
5962 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
5963 &zero_address_frag);
5965 pseudo_func[FUNC_GP_RELATIVE].u.sym =
5966 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
5967 &zero_address_frag);
5969 pseudo_func[FUNC_LT_RELATIVE].u.sym =
5970 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
5971 &zero_address_frag);
5973 pseudo_func[FUNC_PC_RELATIVE].u.sym =
5974 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
5975 &zero_address_frag);
5977 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
5978 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
5979 &zero_address_frag);
5981 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
5982 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
5983 &zero_address_frag);
5985 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
5986 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
5987 &zero_address_frag);
5989 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
5990 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
5991 &zero_address_frag);
5993 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
5994 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
5995 &zero_address_frag);
5997 /* Compute the table of best templates. We compute goodness as a
5998 base 4 value, in which each match counts for 3, each F counts
5999 for 2, each B counts for 1. This should maximize the number of
6000 F and B nops in the chosen bundles, which is good because these
6001 pipelines are least likely to be overcommitted. */
6002 for (i = 0; i < IA64_NUM_TYPES; ++i)
6003 for (j = 0; j < IA64_NUM_TYPES; ++j)
6004 for (k = 0; k < IA64_NUM_TYPES; ++k)
6006 best = 0;
6007 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
6009 goodness = 0;
6010 if (match (t, i, 0))
6012 if (match (t, j, 1))
6014 if (match (t, k, 2))
6015 goodness = 3 + 3 + 3;
6016 else
6017 goodness = 3 + 3 + extra_goodness (t, 2);
6019 else if (match (t, j, 2))
6020 goodness = 3 + 3 + extra_goodness (t, 1);
6021 else
6023 goodness = 3;
6024 goodness += extra_goodness (t, 1);
6025 goodness += extra_goodness (t, 2);
6028 else if (match (t, i, 1))
6030 if (match (t, j, 2))
6031 goodness = 3 + 3;
6032 else
6033 goodness = 3 + extra_goodness (t, 2);
6035 else if (match (t, i, 2))
6036 goodness = 3 + extra_goodness (t, 1);
6038 if (goodness > best)
6040 best = goodness;
6041 best_template[i][j][k] = t;
6046 for (i = 0; i < NUM_SLOTS; ++i)
6047 md.slot[i].user_template = -1;
6049 md.pseudo_hash = hash_new ();
6050 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
6052 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
6053 (void *) (pseudo_opcode + i));
6054 if (err)
6055 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6056 pseudo_opcode[i].name, err);
6059 md.reg_hash = hash_new ();
6060 md.dynreg_hash = hash_new ();
6061 md.const_hash = hash_new ();
6062 md.entry_hash = hash_new ();
6064 /* general registers: */
6066 total = 128;
6067 for (i = 0; i < total; ++i)
6069 sprintf (name, "r%d", i - REG_GR);
6070 md.regsym[i] = declare_register (name, i);
6073 /* floating point registers: */
6074 total += 128;
6075 for (; i < total; ++i)
6077 sprintf (name, "f%d", i - REG_FR);
6078 md.regsym[i] = declare_register (name, i);
6081 /* application registers: */
6082 total += 128;
6083 ar_base = i;
6084 for (; i < total; ++i)
6086 sprintf (name, "ar%d", i - REG_AR);
6087 md.regsym[i] = declare_register (name, i);
6090 /* control registers: */
6091 total += 128;
6092 cr_base = i;
6093 for (; i < total; ++i)
6095 sprintf (name, "cr%d", i - REG_CR);
6096 md.regsym[i] = declare_register (name, i);
6099 /* predicate registers: */
6100 total += 64;
6101 for (; i < total; ++i)
6103 sprintf (name, "p%d", i - REG_P);
6104 md.regsym[i] = declare_register (name, i);
6107 /* branch registers: */
6108 total += 8;
6109 for (; i < total; ++i)
6111 sprintf (name, "b%d", i - REG_BR);
6112 md.regsym[i] = declare_register (name, i);
6115 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
6116 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
6117 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
6118 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
6119 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
6120 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
6121 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
6123 for (i = 0; i < NELEMS (indirect_reg); ++i)
6125 regnum = indirect_reg[i].regnum;
6126 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
6129 /* define synonyms for application registers: */
6130 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
6131 md.regsym[i] = declare_register (ar[i - REG_AR].name,
6132 REG_AR + ar[i - REG_AR].regnum);
6134 /* define synonyms for control registers: */
6135 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
6136 md.regsym[i] = declare_register (cr[i - REG_CR].name,
6137 REG_CR + cr[i - REG_CR].regnum);
6139 declare_register ("gp", REG_GR + 1);
6140 declare_register ("sp", REG_GR + 12);
6141 declare_register ("rp", REG_BR + 0);
6143 /* pseudo-registers used to specify unwind info: */
6144 declare_register ("psp", REG_PSP);
6146 declare_register_set ("ret", 4, REG_GR + 8);
6147 declare_register_set ("farg", 8, REG_FR + 8);
6148 declare_register_set ("fret", 8, REG_FR + 8);
6150 for (i = 0; i < NELEMS (const_bits); ++i)
6152 err = hash_insert (md.const_hash, const_bits[i].name,
6153 (PTR) (const_bits + i));
6154 if (err)
6155 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6156 name, err);
6159 /* Set the architecture and machine depending on defaults and command line
6160 options. */
6161 if (md.flags & EF_IA_64_ABI64)
6162 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
6163 else
6164 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
6166 if (! ok)
6167 as_warn (_("Could not set architecture and machine"));
6169 md.mem_offset.hint = 0;
6170 md.path = 0;
6171 md.maxpaths = 0;
6172 md.entry_labels = NULL;
6175 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6176 because that is called after md_parse_option which is where we do the
6177 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6178 default endianness. */
6180 void
6181 ia64_init (argc, argv)
6182 int argc ATTRIBUTE_UNUSED;
6183 char **argv ATTRIBUTE_UNUSED;
6185 md.flags = EF_IA_64_ABI64;
6186 if (TARGET_BYTES_BIG_ENDIAN)
6187 md.flags |= EF_IA_64_BE;
6190 /* Return a string for the target object file format. */
6192 const char *
6193 ia64_target_format ()
6195 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6197 if (md.flags & EF_IA_64_BE)
6199 if (md.flags & EF_IA_64_ABI64)
6200 return "elf64-ia64-big";
6201 else
6202 return "elf32-ia64-big";
6204 else
6206 if (md.flags & EF_IA_64_ABI64)
6207 return "elf64-ia64-little";
6208 else
6209 return "elf32-ia64-little";
6212 else
6213 return "unknown-format";
6216 void
6217 ia64_end_of_source ()
6219 /* terminate insn group upon reaching end of file: */
6220 insn_group_break (1, 0, 0);
6222 /* emits slots we haven't written yet: */
6223 ia64_flush_insns ();
6225 bfd_set_private_flags (stdoutput, md.flags);
6227 md.mem_offset.hint = 0;
6230 void
6231 ia64_start_line ()
6233 if (md.qp.X_op == O_register)
6234 as_bad ("qualifying predicate not followed by instruction");
6235 md.qp.X_op = O_absent;
6237 if (ignore_input ())
6238 return;
6240 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
6242 if (md.detect_dv && !md.explicit_mode)
6243 as_warn (_("Explicit stops are ignored in auto mode"));
6244 else
6245 insn_group_break (1, 0, 0);
6249 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6250 labels. */
6251 static int defining_tag = 0;
6254 ia64_unrecognized_line (ch)
6255 int ch;
6257 switch (ch)
6259 case '(':
6260 expression (&md.qp);
6261 if (*input_line_pointer++ != ')')
6263 as_bad ("Expected ')'");
6264 return 0;
6266 if (md.qp.X_op != O_register)
6268 as_bad ("Qualifying predicate expected");
6269 return 0;
6271 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6273 as_bad ("Predicate register expected");
6274 return 0;
6276 return 1;
6278 case '{':
6279 if (md.manual_bundling)
6280 as_warn ("Found '{' when manual bundling is already turned on");
6281 else
6282 CURR_SLOT.manual_bundling_on = 1;
6283 md.manual_bundling = 1;
6285 /* Bundling is only acceptable in explicit mode
6286 or when in default automatic mode. */
6287 if (md.detect_dv && !md.explicit_mode)
6289 if (!md.mode_explicitly_set
6290 && !md.default_explicit_mode)
6291 dot_dv_mode ('E');
6292 else
6293 as_warn (_("Found '{' after explicit switch to automatic mode"));
6295 return 1;
6297 case '}':
6298 if (!md.manual_bundling)
6299 as_warn ("Found '}' when manual bundling is off");
6300 else
6301 PREV_SLOT.manual_bundling_off = 1;
6302 md.manual_bundling = 0;
6304 /* switch back to automatic mode, if applicable */
6305 if (md.detect_dv
6306 && md.explicit_mode
6307 && !md.mode_explicitly_set
6308 && !md.default_explicit_mode)
6309 dot_dv_mode ('A');
6311 /* Allow '{' to follow on the same line. We also allow ";;", but that
6312 happens automatically because ';' is an end of line marker. */
6313 SKIP_WHITESPACE ();
6314 if (input_line_pointer[0] == '{')
6316 input_line_pointer++;
6317 return ia64_unrecognized_line ('{');
6320 demand_empty_rest_of_line ();
6321 return 1;
6323 case '[':
6325 char *s;
6326 char c;
6327 symbolS *tag;
6329 if (md.qp.X_op == O_register)
6331 as_bad ("Tag must come before qualifying predicate.");
6332 return 0;
6334 s = input_line_pointer;
6335 c = get_symbol_end ();
6336 if (c != ':')
6338 /* Put ':' back for error messages' sake. */
6339 *input_line_pointer++ = ':';
6340 as_bad ("Expected ':'");
6341 return 0;
6343 defining_tag = 1;
6344 tag = colon (s);
6345 defining_tag = 0;
6346 /* Put ':' back for error messages' sake. */
6347 *input_line_pointer++ = ':';
6348 if (*input_line_pointer++ != ']')
6350 as_bad ("Expected ']'");
6351 return 0;
6353 if (! tag)
6355 as_bad ("Tag name expected");
6356 return 0;
6358 return 1;
6361 default:
6362 break;
6365 /* Not a valid line. */
6366 return 0;
6369 void
6370 ia64_frob_label (sym)
6371 struct symbol *sym;
6373 struct label_fix *fix;
6375 /* Tags need special handling since they are not bundle breaks like
6376 labels. */
6377 if (defining_tag)
6379 fix = obstack_alloc (&notes, sizeof (*fix));
6380 fix->sym = sym;
6381 fix->next = CURR_SLOT.tag_fixups;
6382 CURR_SLOT.tag_fixups = fix;
6384 return;
6387 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6389 md.last_text_seg = now_seg;
6390 fix = obstack_alloc (&notes, sizeof (*fix));
6391 fix->sym = sym;
6392 fix->next = CURR_SLOT.label_fixups;
6393 CURR_SLOT.label_fixups = fix;
6395 /* Keep track of how many code entry points we've seen. */
6396 if (md.path == md.maxpaths)
6398 md.maxpaths += 20;
6399 md.entry_labels = (const char **)
6400 xrealloc ((void *) md.entry_labels,
6401 md.maxpaths * sizeof (char *));
6403 md.entry_labels[md.path++] = S_GET_NAME (sym);
6407 void
6408 ia64_flush_pending_output ()
6410 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6412 /* ??? This causes many unnecessary stop bits to be emitted.
6413 Unfortunately, it isn't clear if it is safe to remove this. */
6414 insn_group_break (1, 0, 0);
6415 ia64_flush_insns ();
6419 /* Do ia64-specific expression optimization. All that's done here is
6420 to transform index expressions that are either due to the indexing
6421 of rotating registers or due to the indexing of indirect register
6422 sets. */
6424 ia64_optimize_expr (l, op, r)
6425 expressionS *l;
6426 operatorT op;
6427 expressionS *r;
6429 unsigned num_regs;
6431 if (op == O_index)
6433 if (l->X_op == O_register && r->X_op == O_constant)
6435 num_regs = (l->X_add_number >> 16);
6436 if ((unsigned) r->X_add_number >= num_regs)
6438 if (!num_regs)
6439 as_bad ("No current frame");
6440 else
6441 as_bad ("Index out of range 0..%u", num_regs - 1);
6442 r->X_add_number = 0;
6444 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6445 return 1;
6447 else if (l->X_op == O_register && r->X_op == O_register)
6449 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6450 || l->X_add_number == IND_MEM)
6452 as_bad ("Indirect register set name expected");
6453 l->X_add_number = IND_CPUID;
6455 l->X_op = O_index;
6456 l->X_op_symbol = md.regsym[l->X_add_number];
6457 l->X_add_number = r->X_add_number;
6458 return 1;
6461 return 0;
6465 ia64_parse_name (name, e)
6466 char *name;
6467 expressionS *e;
6469 struct const_desc *cdesc;
6470 struct dynreg *dr = 0;
6471 unsigned int regnum;
6472 struct symbol *sym;
6473 char *end;
6475 /* first see if NAME is a known register name: */
6476 sym = hash_find (md.reg_hash, name);
6477 if (sym)
6479 e->X_op = O_register;
6480 e->X_add_number = S_GET_VALUE (sym);
6481 return 1;
6484 cdesc = hash_find (md.const_hash, name);
6485 if (cdesc)
6487 e->X_op = O_constant;
6488 e->X_add_number = cdesc->value;
6489 return 1;
6492 /* check for inN, locN, or outN: */
6493 switch (name[0])
6495 case 'i':
6496 if (name[1] == 'n' && isdigit (name[2]))
6498 dr = &md.in;
6499 name += 2;
6501 break;
6503 case 'l':
6504 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6506 dr = &md.loc;
6507 name += 3;
6509 break;
6511 case 'o':
6512 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6514 dr = &md.out;
6515 name += 3;
6517 break;
6519 default:
6520 break;
6523 if (dr)
6525 /* The name is inN, locN, or outN; parse the register number. */
6526 regnum = strtoul (name, &end, 10);
6527 if (end > name && *end == '\0')
6529 if ((unsigned) regnum >= dr->num_regs)
6531 if (!dr->num_regs)
6532 as_bad ("No current frame");
6533 else
6534 as_bad ("Register number out of range 0..%u",
6535 dr->num_regs - 1);
6536 regnum = 0;
6538 e->X_op = O_register;
6539 e->X_add_number = dr->base + regnum;
6540 return 1;
6544 if ((dr = hash_find (md.dynreg_hash, name)))
6546 /* We've got ourselves the name of a rotating register set.
6547 Store the base register number in the low 16 bits of
6548 X_add_number and the size of the register set in the top 16
6549 bits. */
6550 e->X_op = O_register;
6551 e->X_add_number = dr->base | (dr->num_regs << 16);
6552 return 1;
6554 return 0;
6557 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6559 char *
6560 ia64_canonicalize_symbol_name (name)
6561 char *name;
6563 size_t len = strlen (name);
6564 if (len > 1 && name[len - 1] == '#')
6565 name[len - 1] = '\0';
6566 return name;
6569 static int
6570 is_conditional_branch (idesc)
6571 struct ia64_opcode *idesc;
6573 return (strncmp (idesc->name, "br", 2) == 0
6574 && (strcmp (idesc->name, "br") == 0
6575 || strncmp (idesc->name, "br.cond", 7) == 0
6576 || strncmp (idesc->name, "br.call", 7) == 0
6577 || strncmp (idesc->name, "br.ret", 6) == 0
6578 || strcmp (idesc->name, "brl") == 0
6579 || strncmp (idesc->name, "brl.cond", 7) == 0
6580 || strncmp (idesc->name, "brl.call", 7) == 0
6581 || strncmp (idesc->name, "brl.ret", 6) == 0));
6584 /* Return whether the given opcode is a taken branch. If there's any doubt,
6585 returns zero. */
6587 static int
6588 is_taken_branch (idesc)
6589 struct ia64_opcode *idesc;
6591 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
6592 || strncmp (idesc->name, "br.ia", 5) == 0);
6595 /* Return whether the given opcode is an interruption or rfi. If there's any
6596 doubt, returns zero. */
6598 static int
6599 is_interruption_or_rfi (idesc)
6600 struct ia64_opcode *idesc;
6602 if (strcmp (idesc->name, "rfi") == 0)
6603 return 1;
6604 return 0;
6607 /* Returns the index of the given dependency in the opcode's list of chks, or
6608 -1 if there is no dependency. */
6610 static int
6611 depends_on (depind, idesc)
6612 int depind;
6613 struct ia64_opcode *idesc;
6615 int i;
6616 const struct ia64_opcode_dependency *dep = idesc->dependencies;
6617 for (i = 0; i < dep->nchks; i++)
6619 if (depind == DEP (dep->chks[i]))
6620 return i;
6622 return -1;
6625 /* Determine a set of specific resources used for a particular resource
6626 class. Returns the number of specific resources identified For those
6627 cases which are not determinable statically, the resource returned is
6628 marked nonspecific.
6630 Meanings of value in 'NOTE':
6631 1) only read/write when the register number is explicitly encoded in the
6632 insn.
6633 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6634 accesses CFM when qualifying predicate is in the rotating region.
6635 3) general register value is used to specify an indirect register; not
6636 determinable statically.
6637 4) only read the given resource when bits 7:0 of the indirect index
6638 register value does not match the register number of the resource; not
6639 determinable statically.
6640 5) all rules are implementation specific.
6641 6) only when both the index specified by the reader and the index specified
6642 by the writer have the same value in bits 63:61; not determinable
6643 statically.
6644 7) only access the specified resource when the corresponding mask bit is
6646 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6647 only read when these insns reference FR2-31
6648 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6649 written when these insns write FR32-127
6650 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6651 instruction
6652 11) The target predicates are written independently of PR[qp], but source
6653 registers are only read if PR[qp] is true. Since the state of PR[qp]
6654 cannot statically be determined, all source registers are marked used.
6655 12) This insn only reads the specified predicate register when that
6656 register is the PR[qp].
6657 13) This reference to ld-c only applies to teh GR whose value is loaded
6658 with data returned from memory, not the post-incremented address register.
6659 14) The RSE resource includes the implementation-specific RSE internal
6660 state resources. At least one (and possibly more) of these resources are
6661 read by each instruction listed in IC:rse-readers. At least one (and
6662 possibly more) of these resources are written by each insn listed in
6663 IC:rse-writers.
6664 15+16) Represents reserved instructions, which the assembler does not
6665 generate.
6667 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6668 this code; there are no dependency violations based on memory access.
6671 #define MAX_SPECS 256
6672 #define DV_CHK 1
6673 #define DV_REG 0
6675 static int
6676 specify_resource (dep, idesc, type, specs, note, path)
6677 const struct ia64_dependency *dep;
6678 struct ia64_opcode *idesc;
6679 int type; /* is this a DV chk or a DV reg? */
6680 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
6681 int note; /* resource note for this insn's usage */
6682 int path; /* which execution path to examine */
6684 int count = 0;
6685 int i;
6686 int rsrc_write = 0;
6687 struct rsrc tmpl;
6689 if (dep->mode == IA64_DV_WAW
6690 || (dep->mode == IA64_DV_RAW && type == DV_REG)
6691 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
6692 rsrc_write = 1;
6694 /* template for any resources we identify */
6695 tmpl.dependency = dep;
6696 tmpl.note = note;
6697 tmpl.insn_srlz = tmpl.data_srlz = 0;
6698 tmpl.qp_regno = CURR_SLOT.qp_regno;
6699 tmpl.link_to_qp_branch = 1;
6700 tmpl.mem_offset.hint = 0;
6701 tmpl.specific = 1;
6702 tmpl.index = 0;
6703 tmpl.cmp_type = CMP_NONE;
6705 #define UNHANDLED \
6706 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6707 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6708 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6710 /* we don't need to track these */
6711 if (dep->semantics == IA64_DVS_NONE)
6712 return 0;
6714 switch (dep->specifier)
6716 case IA64_RS_AR_K:
6717 if (note == 1)
6719 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6721 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6722 if (regno >= 0 && regno <= 7)
6724 specs[count] = tmpl;
6725 specs[count++].index = regno;
6729 else if (note == 0)
6731 for (i = 0; i < 8; i++)
6733 specs[count] = tmpl;
6734 specs[count++].index = i;
6737 else
6739 UNHANDLED;
6741 break;
6743 case IA64_RS_AR_UNAT:
6744 /* This is a mov =AR or mov AR= instruction. */
6745 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6747 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6748 if (regno == AR_UNAT)
6750 specs[count++] = tmpl;
6753 else
6755 /* This is a spill/fill, or other instruction that modifies the
6756 unat register. */
6758 /* Unless we can determine the specific bits used, mark the whole
6759 thing; bits 8:3 of the memory address indicate the bit used in
6760 UNAT. The .mem.offset hint may be used to eliminate a small
6761 subset of conflicts. */
6762 specs[count] = tmpl;
6763 if (md.mem_offset.hint)
6765 if (md.debug_dv)
6766 fprintf (stderr, " Using hint for spill/fill\n");
6767 /* The index isn't actually used, just set it to something
6768 approximating the bit index. */
6769 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
6770 specs[count].mem_offset.hint = 1;
6771 specs[count].mem_offset.offset = md.mem_offset.offset;
6772 specs[count++].mem_offset.base = md.mem_offset.base;
6774 else
6776 specs[count++].specific = 0;
6779 break;
6781 case IA64_RS_AR:
6782 if (note == 1)
6784 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6786 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6787 if ((regno >= 8 && regno <= 15)
6788 || (regno >= 20 && regno <= 23)
6789 || (regno >= 31 && regno <= 39)
6790 || (regno >= 41 && regno <= 47)
6791 || (regno >= 67 && regno <= 111))
6793 specs[count] = tmpl;
6794 specs[count++].index = regno;
6798 else
6800 UNHANDLED;
6802 break;
6804 case IA64_RS_ARb:
6805 if (note == 1)
6807 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6809 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6810 if ((regno >= 48 && regno <= 63)
6811 || (regno >= 112 && regno <= 127))
6813 specs[count] = tmpl;
6814 specs[count++].index = regno;
6818 else if (note == 0)
6820 for (i = 48; i < 64; i++)
6822 specs[count] = tmpl;
6823 specs[count++].index = i;
6825 for (i = 112; i < 128; i++)
6827 specs[count] = tmpl;
6828 specs[count++].index = i;
6831 else
6833 UNHANDLED;
6835 break;
6837 case IA64_RS_BR:
6838 if (note != 1)
6840 UNHANDLED;
6842 else
6844 if (rsrc_write)
6846 for (i = 0; i < idesc->num_outputs; i++)
6847 if (idesc->operands[i] == IA64_OPND_B1
6848 || idesc->operands[i] == IA64_OPND_B2)
6850 specs[count] = tmpl;
6851 specs[count++].index =
6852 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6855 else
6857 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++)
6858 if (idesc->operands[i] == IA64_OPND_B1
6859 || idesc->operands[i] == IA64_OPND_B2)
6861 specs[count] = tmpl;
6862 specs[count++].index =
6863 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6867 break;
6869 case IA64_RS_CPUID: /* four or more registers */
6870 if (note == 3)
6872 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
6874 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6875 if (regno >= 0 && regno < NELEMS (gr_values)
6876 && KNOWN (regno))
6878 specs[count] = tmpl;
6879 specs[count++].index = gr_values[regno].value & 0xFF;
6881 else
6883 specs[count] = tmpl;
6884 specs[count++].specific = 0;
6888 else
6890 UNHANDLED;
6892 break;
6894 case IA64_RS_DBR: /* four or more registers */
6895 if (note == 3)
6897 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
6899 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6900 if (regno >= 0 && regno < NELEMS (gr_values)
6901 && KNOWN (regno))
6903 specs[count] = tmpl;
6904 specs[count++].index = gr_values[regno].value & 0xFF;
6906 else
6908 specs[count] = tmpl;
6909 specs[count++].specific = 0;
6913 else if (note == 0 && !rsrc_write)
6915 specs[count] = tmpl;
6916 specs[count++].specific = 0;
6918 else
6920 UNHANDLED;
6922 break;
6924 case IA64_RS_IBR: /* four or more registers */
6925 if (note == 3)
6927 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
6929 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6930 if (regno >= 0 && regno < NELEMS (gr_values)
6931 && KNOWN (regno))
6933 specs[count] = tmpl;
6934 specs[count++].index = gr_values[regno].value & 0xFF;
6936 else
6938 specs[count] = tmpl;
6939 specs[count++].specific = 0;
6943 else
6945 UNHANDLED;
6947 break;
6949 case IA64_RS_MSR:
6950 if (note == 5)
6952 /* These are implementation specific. Force all references to
6953 conflict with all other references. */
6954 specs[count] = tmpl;
6955 specs[count++].specific = 0;
6957 else
6959 UNHANDLED;
6961 break;
6963 case IA64_RS_PKR: /* 16 or more registers */
6964 if (note == 3 || note == 4)
6966 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
6968 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6969 if (regno >= 0 && regno < NELEMS (gr_values)
6970 && KNOWN (regno))
6972 if (note == 3)
6974 specs[count] = tmpl;
6975 specs[count++].index = gr_values[regno].value & 0xFF;
6977 else
6978 for (i = 0; i < NELEMS (gr_values); i++)
6980 /* Uses all registers *except* the one in R3. */
6981 if ((unsigned)i != (gr_values[regno].value & 0xFF))
6983 specs[count] = tmpl;
6984 specs[count++].index = i;
6988 else
6990 specs[count] = tmpl;
6991 specs[count++].specific = 0;
6995 else if (note == 0)
6997 /* probe et al. */
6998 specs[count] = tmpl;
6999 specs[count++].specific = 0;
7001 break;
7003 case IA64_RS_PMC: /* four or more registers */
7004 if (note == 3)
7006 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
7007 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
7010 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
7011 ? 1 : !rsrc_write);
7012 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
7013 if (regno >= 0 && regno < NELEMS (gr_values)
7014 && KNOWN (regno))
7016 specs[count] = tmpl;
7017 specs[count++].index = gr_values[regno].value & 0xFF;
7019 else
7021 specs[count] = tmpl;
7022 specs[count++].specific = 0;
7026 else
7028 UNHANDLED;
7030 break;
7032 case IA64_RS_PMD: /* four or more registers */
7033 if (note == 3)
7035 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
7037 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7038 if (regno >= 0 && regno < NELEMS (gr_values)
7039 && KNOWN (regno))
7041 specs[count] = tmpl;
7042 specs[count++].index = gr_values[regno].value & 0xFF;
7044 else
7046 specs[count] = tmpl;
7047 specs[count++].specific = 0;
7051 else
7053 UNHANDLED;
7055 break;
7057 case IA64_RS_RR: /* eight registers */
7058 if (note == 6)
7060 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
7062 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7063 if (regno >= 0 && regno < NELEMS (gr_values)
7064 && KNOWN (regno))
7066 specs[count] = tmpl;
7067 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
7069 else
7071 specs[count] = tmpl;
7072 specs[count++].specific = 0;
7076 else if (note == 0 && !rsrc_write)
7078 specs[count] = tmpl;
7079 specs[count++].specific = 0;
7081 else
7083 UNHANDLED;
7085 break;
7087 case IA64_RS_CR_IRR:
7088 if (note == 0)
7090 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7091 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
7092 if (rsrc_write
7093 && idesc->operands[1] == IA64_OPND_CR3
7094 && regno == CR_IVR)
7096 for (i = 0; i < 4; i++)
7098 specs[count] = tmpl;
7099 specs[count++].index = CR_IRR0 + i;
7103 else if (note == 1)
7105 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7106 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7107 && regno >= CR_IRR0
7108 && regno <= CR_IRR3)
7110 specs[count] = tmpl;
7111 specs[count++].index = regno;
7114 else
7116 UNHANDLED;
7118 break;
7120 case IA64_RS_CR_LRR:
7121 if (note != 1)
7123 UNHANDLED;
7125 else
7127 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7128 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7129 && (regno == CR_LRR0 || regno == CR_LRR1))
7131 specs[count] = tmpl;
7132 specs[count++].index = regno;
7135 break;
7137 case IA64_RS_CR:
7138 if (note == 1)
7140 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7142 specs[count] = tmpl;
7143 specs[count++].index =
7144 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7147 else
7149 UNHANDLED;
7151 break;
7153 case IA64_RS_FR:
7154 case IA64_RS_FRb:
7155 if (note != 1)
7157 UNHANDLED;
7159 else if (rsrc_write)
7161 if (dep->specifier == IA64_RS_FRb
7162 && idesc->operands[0] == IA64_OPND_F1)
7164 specs[count] = tmpl;
7165 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
7168 else
7170 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
7172 if (idesc->operands[i] == IA64_OPND_F2
7173 || idesc->operands[i] == IA64_OPND_F3
7174 || idesc->operands[i] == IA64_OPND_F4)
7176 specs[count] = tmpl;
7177 specs[count++].index =
7178 CURR_SLOT.opnd[i].X_add_number - REG_FR;
7182 break;
7184 case IA64_RS_GR:
7185 if (note == 13)
7187 /* This reference applies only to the GR whose value is loaded with
7188 data returned from memory. */
7189 specs[count] = tmpl;
7190 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7192 else if (note == 1)
7194 if (rsrc_write)
7196 for (i = 0; i < idesc->num_outputs; i++)
7197 if (idesc->operands[i] == IA64_OPND_R1
7198 || idesc->operands[i] == IA64_OPND_R2
7199 || idesc->operands[i] == IA64_OPND_R3)
7201 specs[count] = tmpl;
7202 specs[count++].index =
7203 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7205 if (idesc->flags & IA64_OPCODE_POSTINC)
7206 for (i = 0; i < NELEMS (idesc->operands); i++)
7207 if (idesc->operands[i] == IA64_OPND_MR3)
7209 specs[count] = tmpl;
7210 specs[count++].index =
7211 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7214 else
7216 /* Look for anything that reads a GR. */
7217 for (i = 0; i < NELEMS (idesc->operands); i++)
7219 if (idesc->operands[i] == IA64_OPND_MR3
7220 || idesc->operands[i] == IA64_OPND_CPUID_R3
7221 || idesc->operands[i] == IA64_OPND_DBR_R3
7222 || idesc->operands[i] == IA64_OPND_IBR_R3
7223 || idesc->operands[i] == IA64_OPND_MSR_R3
7224 || idesc->operands[i] == IA64_OPND_PKR_R3
7225 || idesc->operands[i] == IA64_OPND_PMC_R3
7226 || idesc->operands[i] == IA64_OPND_PMD_R3
7227 || idesc->operands[i] == IA64_OPND_RR_R3
7228 || ((i >= idesc->num_outputs)
7229 && (idesc->operands[i] == IA64_OPND_R1
7230 || idesc->operands[i] == IA64_OPND_R2
7231 || idesc->operands[i] == IA64_OPND_R3
7232 /* addl source register. */
7233 || idesc->operands[i] == IA64_OPND_R3_2)))
7235 specs[count] = tmpl;
7236 specs[count++].index =
7237 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7242 else
7244 UNHANDLED;
7246 break;
7248 /* This is the same as IA64_RS_PRr, except that the register range is
7249 from 1 - 15, and there are no rotating register reads/writes here. */
7250 case IA64_RS_PR:
7251 if (note == 0)
7253 for (i = 1; i < 16; i++)
7255 specs[count] = tmpl;
7256 specs[count++].index = i;
7259 else if (note == 7)
7261 valueT mask = 0;
7262 /* Mark only those registers indicated by the mask. */
7263 if (rsrc_write)
7265 mask = CURR_SLOT.opnd[2].X_add_number;
7266 for (i = 1; i < 16; i++)
7267 if (mask & ((valueT) 1 << i))
7269 specs[count] = tmpl;
7270 specs[count++].index = i;
7273 else
7275 UNHANDLED;
7278 else if (note == 11) /* note 11 implies note 1 as well */
7280 if (rsrc_write)
7282 for (i = 0; i < idesc->num_outputs; i++)
7284 if (idesc->operands[i] == IA64_OPND_P1
7285 || idesc->operands[i] == IA64_OPND_P2)
7287 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7288 if (regno >= 1 && regno < 16)
7290 specs[count] = tmpl;
7291 specs[count++].index = regno;
7296 else
7298 UNHANDLED;
7301 else if (note == 12)
7303 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7305 specs[count] = tmpl;
7306 specs[count++].index = CURR_SLOT.qp_regno;
7309 else if (note == 1)
7311 if (rsrc_write)
7313 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7314 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7315 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7316 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7318 if ((idesc->operands[0] == IA64_OPND_P1
7319 || idesc->operands[0] == IA64_OPND_P2)
7320 && p1 >= 1 && p1 < 16)
7322 specs[count] = tmpl;
7323 specs[count].cmp_type =
7324 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7325 specs[count++].index = p1;
7327 if ((idesc->operands[1] == IA64_OPND_P1
7328 || idesc->operands[1] == IA64_OPND_P2)
7329 && p2 >= 1 && p2 < 16)
7331 specs[count] = tmpl;
7332 specs[count].cmp_type =
7333 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7334 specs[count++].index = p2;
7337 else
7339 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7341 specs[count] = tmpl;
7342 specs[count++].index = CURR_SLOT.qp_regno;
7344 if (idesc->operands[1] == IA64_OPND_PR)
7346 for (i = 1; i < 16; i++)
7348 specs[count] = tmpl;
7349 specs[count++].index = i;
7354 else
7356 UNHANDLED;
7358 break;
7360 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7361 simplified cases of this. */
7362 case IA64_RS_PRr:
7363 if (note == 0)
7365 for (i = 16; i < 63; i++)
7367 specs[count] = tmpl;
7368 specs[count++].index = i;
7371 else if (note == 7)
7373 valueT mask = 0;
7374 /* Mark only those registers indicated by the mask. */
7375 if (rsrc_write
7376 && idesc->operands[0] == IA64_OPND_PR)
7378 mask = CURR_SLOT.opnd[2].X_add_number;
7379 if (mask & ((valueT) 1<<16))
7380 for (i = 16; i < 63; i++)
7382 specs[count] = tmpl;
7383 specs[count++].index = i;
7386 else if (rsrc_write
7387 && idesc->operands[0] == IA64_OPND_PR_ROT)
7389 for (i = 16; i < 63; i++)
7391 specs[count] = tmpl;
7392 specs[count++].index = i;
7395 else
7397 UNHANDLED;
7400 else if (note == 11) /* note 11 implies note 1 as well */
7402 if (rsrc_write)
7404 for (i = 0; i < idesc->num_outputs; i++)
7406 if (idesc->operands[i] == IA64_OPND_P1
7407 || idesc->operands[i] == IA64_OPND_P2)
7409 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7410 if (regno >= 16 && regno < 63)
7412 specs[count] = tmpl;
7413 specs[count++].index = regno;
7418 else
7420 UNHANDLED;
7423 else if (note == 12)
7425 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
7427 specs[count] = tmpl;
7428 specs[count++].index = CURR_SLOT.qp_regno;
7431 else if (note == 1)
7433 if (rsrc_write)
7435 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7436 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7437 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7438 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7440 if ((idesc->operands[0] == IA64_OPND_P1
7441 || idesc->operands[0] == IA64_OPND_P2)
7442 && p1 >= 16 && p1 < 63)
7444 specs[count] = tmpl;
7445 specs[count].cmp_type =
7446 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7447 specs[count++].index = p1;
7449 if ((idesc->operands[1] == IA64_OPND_P1
7450 || idesc->operands[1] == IA64_OPND_P2)
7451 && p2 >= 16 && p2 < 63)
7453 specs[count] = tmpl;
7454 specs[count].cmp_type =
7455 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7456 specs[count++].index = p2;
7459 else
7461 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
7463 specs[count] = tmpl;
7464 specs[count++].index = CURR_SLOT.qp_regno;
7466 if (idesc->operands[1] == IA64_OPND_PR)
7468 for (i = 16; i < 63; i++)
7470 specs[count] = tmpl;
7471 specs[count++].index = i;
7476 else
7478 UNHANDLED;
7480 break;
7482 case IA64_RS_PSR:
7483 /* Verify that the instruction is using the PSR bit indicated in
7484 dep->regindex. */
7485 if (note == 0)
7487 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7489 if (dep->regindex < 6)
7491 specs[count++] = tmpl;
7494 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7496 if (dep->regindex < 32
7497 || dep->regindex == 35
7498 || dep->regindex == 36
7499 || (!rsrc_write && dep->regindex == PSR_CPL))
7501 specs[count++] = tmpl;
7504 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7506 if (dep->regindex < 32
7507 || dep->regindex == 35
7508 || dep->regindex == 36
7509 || (rsrc_write && dep->regindex == PSR_CPL))
7511 specs[count++] = tmpl;
7514 else
7516 /* Several PSR bits have very specific dependencies. */
7517 switch (dep->regindex)
7519 default:
7520 specs[count++] = tmpl;
7521 break;
7522 case PSR_IC:
7523 if (rsrc_write)
7525 specs[count++] = tmpl;
7527 else
7529 /* Only certain CR accesses use PSR.ic */
7530 if (idesc->operands[0] == IA64_OPND_CR3
7531 || idesc->operands[1] == IA64_OPND_CR3)
7533 int index =
7534 ((idesc->operands[0] == IA64_OPND_CR3)
7535 ? 0 : 1);
7536 int regno =
7537 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7539 switch (regno)
7541 default:
7542 break;
7543 case CR_ITIR:
7544 case CR_IFS:
7545 case CR_IIM:
7546 case CR_IIP:
7547 case CR_IPSR:
7548 case CR_ISR:
7549 case CR_IFA:
7550 case CR_IHA:
7551 case CR_IIPA:
7552 specs[count++] = tmpl;
7553 break;
7557 break;
7558 case PSR_CPL:
7559 if (rsrc_write)
7561 specs[count++] = tmpl;
7563 else
7565 /* Only some AR accesses use cpl */
7566 if (idesc->operands[0] == IA64_OPND_AR3
7567 || idesc->operands[1] == IA64_OPND_AR3)
7569 int index =
7570 ((idesc->operands[0] == IA64_OPND_AR3)
7571 ? 0 : 1);
7572 int regno =
7573 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7575 if (regno == AR_ITC
7576 || (index == 0
7577 && (regno == AR_ITC
7578 || regno == AR_RSC
7579 || (regno >= AR_K0
7580 && regno <= AR_K7))))
7582 specs[count++] = tmpl;
7585 else
7587 specs[count++] = tmpl;
7589 break;
7594 else if (note == 7)
7596 valueT mask = 0;
7597 if (idesc->operands[0] == IA64_OPND_IMMU24)
7599 mask = CURR_SLOT.opnd[0].X_add_number;
7601 else
7603 UNHANDLED;
7605 if (mask & ((valueT) 1 << dep->regindex))
7607 specs[count++] = tmpl;
7610 else if (note == 8)
7612 int min = dep->regindex == PSR_DFL ? 2 : 32;
7613 int max = dep->regindex == PSR_DFL ? 31 : 127;
7614 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7615 for (i = 0; i < NELEMS (idesc->operands); i++)
7617 if (idesc->operands[i] == IA64_OPND_F1
7618 || idesc->operands[i] == IA64_OPND_F2
7619 || idesc->operands[i] == IA64_OPND_F3
7620 || idesc->operands[i] == IA64_OPND_F4)
7622 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7623 if (reg >= min && reg <= max)
7625 specs[count++] = tmpl;
7630 else if (note == 9)
7632 int min = dep->regindex == PSR_MFL ? 2 : 32;
7633 int max = dep->regindex == PSR_MFL ? 31 : 127;
7634 /* mfh is read on writes to FR32-127; mfl is read on writes to
7635 FR2-31 */
7636 for (i = 0; i < idesc->num_outputs; i++)
7638 if (idesc->operands[i] == IA64_OPND_F1)
7640 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7641 if (reg >= min && reg <= max)
7643 specs[count++] = tmpl;
7648 else if (note == 10)
7650 for (i = 0; i < NELEMS (idesc->operands); i++)
7652 if (idesc->operands[i] == IA64_OPND_R1
7653 || idesc->operands[i] == IA64_OPND_R2
7654 || idesc->operands[i] == IA64_OPND_R3)
7656 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7657 if (regno >= 16 && regno <= 31)
7659 specs[count++] = tmpl;
7664 else
7666 UNHANDLED;
7668 break;
7670 case IA64_RS_AR_FPSR:
7671 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7673 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7674 if (regno == AR_FPSR)
7676 specs[count++] = tmpl;
7679 else
7681 specs[count++] = tmpl;
7683 break;
7685 case IA64_RS_ARX:
7686 /* Handle all AR[REG] resources */
7687 if (note == 0 || note == 1)
7689 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7690 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
7691 && regno == dep->regindex)
7693 specs[count++] = tmpl;
7695 /* other AR[REG] resources may be affected by AR accesses */
7696 else if (idesc->operands[0] == IA64_OPND_AR3)
7698 /* AR[] writes */
7699 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
7700 switch (dep->regindex)
7702 default:
7703 break;
7704 case AR_BSP:
7705 case AR_RNAT:
7706 if (regno == AR_BSPSTORE)
7708 specs[count++] = tmpl;
7710 case AR_RSC:
7711 if (!rsrc_write &&
7712 (regno == AR_BSPSTORE
7713 || regno == AR_RNAT))
7715 specs[count++] = tmpl;
7717 break;
7720 else if (idesc->operands[1] == IA64_OPND_AR3)
7722 /* AR[] reads */
7723 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
7724 switch (dep->regindex)
7726 default:
7727 break;
7728 case AR_RSC:
7729 if (regno == AR_BSPSTORE || regno == AR_RNAT)
7731 specs[count++] = tmpl;
7733 break;
7736 else
7738 specs[count++] = tmpl;
7741 else
7743 UNHANDLED;
7745 break;
7747 case IA64_RS_CRX:
7748 /* Handle all CR[REG] resources */
7749 if (note == 0 || note == 1)
7751 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7753 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7754 if (regno == dep->regindex)
7756 specs[count++] = tmpl;
7758 else if (!rsrc_write)
7760 /* Reads from CR[IVR] affect other resources. */
7761 if (regno == CR_IVR)
7763 if ((dep->regindex >= CR_IRR0
7764 && dep->regindex <= CR_IRR3)
7765 || dep->regindex == CR_TPR)
7767 specs[count++] = tmpl;
7772 else
7774 specs[count++] = tmpl;
7777 else
7779 UNHANDLED;
7781 break;
7783 case IA64_RS_INSERVICE:
7784 /* look for write of EOI (67) or read of IVR (65) */
7785 if ((idesc->operands[0] == IA64_OPND_CR3
7786 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
7787 || (idesc->operands[1] == IA64_OPND_CR3
7788 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
7790 specs[count++] = tmpl;
7792 break;
7794 case IA64_RS_GR0:
7795 if (note == 1)
7797 specs[count++] = tmpl;
7799 else
7801 UNHANDLED;
7803 break;
7805 case IA64_RS_CFM:
7806 if (note != 2)
7808 specs[count++] = tmpl;
7810 else
7812 /* Check if any of the registers accessed are in the rotating region.
7813 mov to/from pr accesses CFM only when qp_regno is in the rotating
7814 region */
7815 for (i = 0; i < NELEMS (idesc->operands); i++)
7817 if (idesc->operands[i] == IA64_OPND_R1
7818 || idesc->operands[i] == IA64_OPND_R2
7819 || idesc->operands[i] == IA64_OPND_R3)
7821 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7822 /* Assumes that md.rot.num_regs is always valid */
7823 if (md.rot.num_regs > 0
7824 && num > 31
7825 && num < 31 + md.rot.num_regs)
7827 specs[count] = tmpl;
7828 specs[count++].specific = 0;
7831 else if (idesc->operands[i] == IA64_OPND_F1
7832 || idesc->operands[i] == IA64_OPND_F2
7833 || idesc->operands[i] == IA64_OPND_F3
7834 || idesc->operands[i] == IA64_OPND_F4)
7836 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7837 if (num > 31)
7839 specs[count] = tmpl;
7840 specs[count++].specific = 0;
7843 else if (idesc->operands[i] == IA64_OPND_P1
7844 || idesc->operands[i] == IA64_OPND_P2)
7846 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
7847 if (num > 15)
7849 specs[count] = tmpl;
7850 specs[count++].specific = 0;
7854 if (CURR_SLOT.qp_regno > 15)
7856 specs[count] = tmpl;
7857 specs[count++].specific = 0;
7860 break;
7862 /* This is the same as IA64_RS_PRr, except simplified to account for
7863 the fact that there is only one register. */
7864 case IA64_RS_PR63:
7865 if (note == 0)
7867 specs[count++] = tmpl;
7869 else if (note == 7)
7871 valueT mask = 0;
7872 if (idesc->operands[2] == IA64_OPND_IMM17)
7873 mask = CURR_SLOT.opnd[2].X_add_number;
7874 if (mask & ((valueT) 1 << 63))
7875 specs[count++] = tmpl;
7877 else if (note == 11)
7879 if ((idesc->operands[0] == IA64_OPND_P1
7880 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
7881 || (idesc->operands[1] == IA64_OPND_P2
7882 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
7884 specs[count++] = tmpl;
7887 else if (note == 12)
7889 if (CURR_SLOT.qp_regno == 63)
7891 specs[count++] = tmpl;
7894 else if (note == 1)
7896 if (rsrc_write)
7898 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7899 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7900 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7901 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7903 if (p1 == 63
7904 && (idesc->operands[0] == IA64_OPND_P1
7905 || idesc->operands[0] == IA64_OPND_P2))
7907 specs[count] = tmpl;
7908 specs[count++].cmp_type =
7909 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7911 if (p2 == 63
7912 && (idesc->operands[1] == IA64_OPND_P1
7913 || idesc->operands[1] == IA64_OPND_P2))
7915 specs[count] = tmpl;
7916 specs[count++].cmp_type =
7917 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7920 else
7922 if (CURR_SLOT.qp_regno == 63)
7924 specs[count++] = tmpl;
7928 else
7930 UNHANDLED;
7932 break;
7934 case IA64_RS_RSE:
7935 /* FIXME we can identify some individual RSE written resources, but RSE
7936 read resources have not yet been completely identified, so for now
7937 treat RSE as a single resource */
7938 if (strncmp (idesc->name, "mov", 3) == 0)
7940 if (rsrc_write)
7942 if (idesc->operands[0] == IA64_OPND_AR3
7943 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
7945 specs[count] = tmpl;
7946 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7949 else
7951 if (idesc->operands[0] == IA64_OPND_AR3)
7953 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
7954 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
7956 specs[count++] = tmpl;
7959 else if (idesc->operands[1] == IA64_OPND_AR3)
7961 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
7962 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
7963 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
7965 specs[count++] = tmpl;
7970 else
7972 specs[count++] = tmpl;
7974 break;
7976 case IA64_RS_ANY:
7977 /* FIXME -- do any of these need to be non-specific? */
7978 specs[count++] = tmpl;
7979 break;
7981 default:
7982 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
7983 break;
7986 return count;
7989 /* Clear branch flags on marked resources. This breaks the link between the
7990 QP of the marking instruction and a subsequent branch on the same QP. */
7992 static void
7993 clear_qp_branch_flag (mask)
7994 valueT mask;
7996 int i;
7997 for (i = 0; i < regdepslen; i++)
7999 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
8000 if ((bit & mask) != 0)
8002 regdeps[i].link_to_qp_branch = 0;
8007 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8009 Any changes to a PR clears the mutex relations which include that PR. */
8011 static void
8012 clear_qp_mutex (mask)
8013 valueT mask;
8015 int i;
8017 i = 0;
8018 while (i < qp_mutexeslen)
8020 if ((qp_mutexes[i].prmask & mask) != 0)
8022 if (md.debug_dv)
8024 fprintf (stderr, " Clearing mutex relation");
8025 print_prmask (qp_mutexes[i].prmask);
8026 fprintf (stderr, "\n");
8028 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
8030 else
8031 ++i;
8035 /* Clear implies relations which contain PRs in the given masks.
8036 P1_MASK indicates the source of the implies relation, while P2_MASK
8037 indicates the implied PR. */
8039 static void
8040 clear_qp_implies (p1_mask, p2_mask)
8041 valueT p1_mask;
8042 valueT p2_mask;
8044 int i;
8046 i = 0;
8047 while (i < qp_implieslen)
8049 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
8050 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
8052 if (md.debug_dv)
8053 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
8054 qp_implies[i].p1, qp_implies[i].p2);
8055 qp_implies[i] = qp_implies[--qp_implieslen];
8057 else
8058 ++i;
8062 /* Add the PRs specified to the list of implied relations. */
8064 static void
8065 add_qp_imply (p1, p2)
8066 int p1, p2;
8068 valueT mask;
8069 valueT bit;
8070 int i;
8072 /* p0 is not meaningful here. */
8073 if (p1 == 0 || p2 == 0)
8074 abort ();
8076 if (p1 == p2)
8077 return;
8079 /* If it exists already, ignore it. */
8080 for (i = 0; i < qp_implieslen; i++)
8082 if (qp_implies[i].p1 == p1
8083 && qp_implies[i].p2 == p2
8084 && qp_implies[i].path == md.path
8085 && !qp_implies[i].p2_branched)
8086 return;
8089 if (qp_implieslen == qp_impliestotlen)
8091 qp_impliestotlen += 20;
8092 qp_implies = (struct qp_imply *)
8093 xrealloc ((void *) qp_implies,
8094 qp_impliestotlen * sizeof (struct qp_imply));
8096 if (md.debug_dv)
8097 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
8098 qp_implies[qp_implieslen].p1 = p1;
8099 qp_implies[qp_implieslen].p2 = p2;
8100 qp_implies[qp_implieslen].path = md.path;
8101 qp_implies[qp_implieslen++].p2_branched = 0;
8103 /* Add in the implied transitive relations; for everything that p2 implies,
8104 make p1 imply that, too; for everything that implies p1, make it imply p2
8105 as well. */
8106 for (i = 0; i < qp_implieslen; i++)
8108 if (qp_implies[i].p1 == p2)
8109 add_qp_imply (p1, qp_implies[i].p2);
8110 if (qp_implies[i].p2 == p1)
8111 add_qp_imply (qp_implies[i].p1, p2);
8113 /* Add in mutex relations implied by this implies relation; for each mutex
8114 relation containing p2, duplicate it and replace p2 with p1. */
8115 bit = (valueT) 1 << p1;
8116 mask = (valueT) 1 << p2;
8117 for (i = 0; i < qp_mutexeslen; i++)
8119 if (qp_mutexes[i].prmask & mask)
8120 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
8124 /* Add the PRs specified in the mask to the mutex list; this means that only
8125 one of the PRs can be true at any time. PR0 should never be included in
8126 the mask. */
8128 static void
8129 add_qp_mutex (mask)
8130 valueT mask;
8132 if (mask & 0x1)
8133 abort ();
8135 if (qp_mutexeslen == qp_mutexestotlen)
8137 qp_mutexestotlen += 20;
8138 qp_mutexes = (struct qpmutex *)
8139 xrealloc ((void *) qp_mutexes,
8140 qp_mutexestotlen * sizeof (struct qpmutex));
8142 if (md.debug_dv)
8144 fprintf (stderr, " Registering mutex on");
8145 print_prmask (mask);
8146 fprintf (stderr, "\n");
8148 qp_mutexes[qp_mutexeslen].path = md.path;
8149 qp_mutexes[qp_mutexeslen++].prmask = mask;
8152 static void
8153 clear_register_values ()
8155 int i;
8156 if (md.debug_dv)
8157 fprintf (stderr, " Clearing register values\n");
8158 for (i = 1; i < NELEMS (gr_values); i++)
8159 gr_values[i].known = 0;
8162 /* Keep track of register values/changes which affect DV tracking.
8164 optimization note: should add a flag to classes of insns where otherwise we
8165 have to examine a group of strings to identify them. */
8167 static void
8168 note_register_values (idesc)
8169 struct ia64_opcode *idesc;
8171 valueT qp_changemask = 0;
8172 int i;
8174 /* Invalidate values for registers being written to. */
8175 for (i = 0; i < idesc->num_outputs; i++)
8177 if (idesc->operands[i] == IA64_OPND_R1
8178 || idesc->operands[i] == IA64_OPND_R2
8179 || idesc->operands[i] == IA64_OPND_R3)
8181 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8182 if (regno > 0 && regno < NELEMS (gr_values))
8183 gr_values[regno].known = 0;
8185 else if (idesc->operands[i] == IA64_OPND_R3_2)
8187 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8188 if (regno > 0 && regno < 4)
8189 gr_values[regno].known = 0;
8191 else if (idesc->operands[i] == IA64_OPND_P1
8192 || idesc->operands[i] == IA64_OPND_P2)
8194 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
8195 qp_changemask |= (valueT) 1 << regno;
8197 else if (idesc->operands[i] == IA64_OPND_PR)
8199 if (idesc->operands[2] & (valueT) 0x10000)
8200 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
8201 else
8202 qp_changemask = idesc->operands[2];
8203 break;
8205 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
8207 if (idesc->operands[1] & ((valueT) 1 << 43))
8208 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
8209 else
8210 qp_changemask = idesc->operands[1];
8211 qp_changemask &= ~(valueT) 0xFFFF;
8212 break;
8216 /* Always clear qp branch flags on any PR change. */
8217 /* FIXME there may be exceptions for certain compares. */
8218 clear_qp_branch_flag (qp_changemask);
8220 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8221 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
8223 qp_changemask |= ~(valueT) 0xFFFF;
8224 if (strcmp (idesc->name, "clrrrb.pr") != 0)
8226 for (i = 32; i < 32 + md.rot.num_regs; i++)
8227 gr_values[i].known = 0;
8229 clear_qp_mutex (qp_changemask);
8230 clear_qp_implies (qp_changemask, qp_changemask);
8232 /* After a call, all register values are undefined, except those marked
8233 as "safe". */
8234 else if (strncmp (idesc->name, "br.call", 6) == 0
8235 || strncmp (idesc->name, "brl.call", 7) == 0)
8237 /* FIXME keep GR values which are marked as "safe_across_calls" */
8238 clear_register_values ();
8239 clear_qp_mutex (~qp_safe_across_calls);
8240 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
8241 clear_qp_branch_flag (~qp_safe_across_calls);
8243 else if (is_interruption_or_rfi (idesc)
8244 || is_taken_branch (idesc))
8246 clear_register_values ();
8247 clear_qp_mutex (~(valueT) 0);
8248 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
8250 /* Look for mutex and implies relations. */
8251 else if ((idesc->operands[0] == IA64_OPND_P1
8252 || idesc->operands[0] == IA64_OPND_P2)
8253 && (idesc->operands[1] == IA64_OPND_P1
8254 || idesc->operands[1] == IA64_OPND_P2))
8256 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8257 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8258 valueT p1mask = (valueT) 1 << p1;
8259 valueT p2mask = (valueT) 1 << p2;
8261 /* If one of the PRs is PR0, we can't really do anything. */
8262 if (p1 == 0 || p2 == 0)
8264 if (md.debug_dv)
8265 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8267 /* In general, clear mutexes and implies which include P1 or P2,
8268 with the following exceptions. */
8269 else if (strstr (idesc->name, ".or.andcm") != NULL)
8271 add_qp_mutex (p1mask | p2mask);
8272 clear_qp_implies (p2mask, p1mask);
8274 else if (strstr (idesc->name, ".and.orcm") != NULL)
8276 add_qp_mutex (p1mask | p2mask);
8277 clear_qp_implies (p1mask, p2mask);
8279 else if (strstr (idesc->name, ".and") != NULL)
8281 clear_qp_implies (0, p1mask | p2mask);
8283 else if (strstr (idesc->name, ".or") != NULL)
8285 clear_qp_mutex (p1mask | p2mask);
8286 clear_qp_implies (p1mask | p2mask, 0);
8288 else
8290 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
8291 if (strstr (idesc->name, ".unc") != NULL)
8293 add_qp_mutex (p1mask | p2mask);
8294 if (CURR_SLOT.qp_regno != 0)
8296 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8297 CURR_SLOT.qp_regno);
8298 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8299 CURR_SLOT.qp_regno);
8302 else if (CURR_SLOT.qp_regno == 0)
8304 add_qp_mutex (p1mask | p2mask);
8306 else
8308 clear_qp_mutex (p1mask | p2mask);
8312 /* Look for mov imm insns into GRs. */
8313 else if (idesc->operands[0] == IA64_OPND_R1
8314 && (idesc->operands[1] == IA64_OPND_IMM22
8315 || idesc->operands[1] == IA64_OPND_IMMU64)
8316 && (strcmp (idesc->name, "mov") == 0
8317 || strcmp (idesc->name, "movl") == 0))
8319 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
8320 if (regno > 0 && regno < NELEMS (gr_values))
8322 gr_values[regno].known = 1;
8323 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
8324 gr_values[regno].path = md.path;
8325 if (md.debug_dv)
8327 fprintf (stderr, " Know gr%d = ", regno);
8328 fprintf_vma (stderr, gr_values[regno].value);
8329 fputs ("\n", stderr);
8333 else
8335 clear_qp_mutex (qp_changemask);
8336 clear_qp_implies (qp_changemask, qp_changemask);
8340 /* Return whether the given predicate registers are currently mutex. */
8342 static int
8343 qp_mutex (p1, p2, path)
8344 int p1;
8345 int p2;
8346 int path;
8348 int i;
8349 valueT mask;
8351 if (p1 != p2)
8353 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
8354 for (i = 0; i < qp_mutexeslen; i++)
8356 if (qp_mutexes[i].path >= path
8357 && (qp_mutexes[i].prmask & mask) == mask)
8358 return 1;
8361 return 0;
8364 /* Return whether the given resource is in the given insn's list of chks
8365 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8366 conflict. */
8368 static int
8369 resources_match (rs, idesc, note, qp_regno, path)
8370 struct rsrc *rs;
8371 struct ia64_opcode *idesc;
8372 int note;
8373 int qp_regno;
8374 int path;
8376 struct rsrc specs[MAX_SPECS];
8377 int count;
8379 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8380 we don't need to check. One exception is note 11, which indicates that
8381 target predicates are written regardless of PR[qp]. */
8382 if (qp_mutex (rs->qp_regno, qp_regno, path)
8383 && note != 11)
8384 return 0;
8386 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
8387 while (count-- > 0)
8389 /* UNAT checking is a bit more specific than other resources */
8390 if (rs->dependency->specifier == IA64_RS_AR_UNAT
8391 && specs[count].mem_offset.hint
8392 && rs->mem_offset.hint)
8394 if (rs->mem_offset.base == specs[count].mem_offset.base)
8396 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
8397 ((specs[count].mem_offset.offset >> 3) & 0x3F))
8398 return 1;
8399 else
8400 continue;
8404 /* Skip apparent PR write conflicts where both writes are an AND or both
8405 writes are an OR. */
8406 if (rs->dependency->specifier == IA64_RS_PR
8407 || rs->dependency->specifier == IA64_RS_PRr
8408 || rs->dependency->specifier == IA64_RS_PR63)
8410 if (specs[count].cmp_type != CMP_NONE
8411 && specs[count].cmp_type == rs->cmp_type)
8413 if (md.debug_dv)
8414 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
8415 dv_mode[rs->dependency->mode],
8416 rs->dependency->specifier != IA64_RS_PR63 ?
8417 specs[count].index : 63);
8418 continue;
8420 if (md.debug_dv)
8421 fprintf (stderr,
8422 " %s on parallel compare conflict %s vs %s on PR%d\n",
8423 dv_mode[rs->dependency->mode],
8424 dv_cmp_type[rs->cmp_type],
8425 dv_cmp_type[specs[count].cmp_type],
8426 rs->dependency->specifier != IA64_RS_PR63 ?
8427 specs[count].index : 63);
8431 /* If either resource is not specific, conservatively assume a conflict
8433 if (!specs[count].specific || !rs->specific)
8434 return 2;
8435 else if (specs[count].index == rs->index)
8436 return 1;
8438 #if 0
8439 if (md.debug_dv)
8440 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
8441 #endif
8443 return 0;
8446 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8447 insert a stop to create the break. Update all resource dependencies
8448 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8449 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8450 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8451 instruction. */
8453 static void
8454 insn_group_break (insert_stop, qp_regno, save_current)
8455 int insert_stop;
8456 int qp_regno;
8457 int save_current;
8459 int i;
8461 if (insert_stop && md.num_slots_in_use > 0)
8462 PREV_SLOT.end_of_insn_group = 1;
8464 if (md.debug_dv)
8466 fprintf (stderr, " Insn group break%s",
8467 (insert_stop ? " (w/stop)" : ""));
8468 if (qp_regno != 0)
8469 fprintf (stderr, " effective for QP=%d", qp_regno);
8470 fprintf (stderr, "\n");
8473 i = 0;
8474 while (i < regdepslen)
8476 const struct ia64_dependency *dep = regdeps[i].dependency;
8478 if (qp_regno != 0
8479 && regdeps[i].qp_regno != qp_regno)
8481 ++i;
8482 continue;
8485 if (save_current
8486 && CURR_SLOT.src_file == regdeps[i].file
8487 && CURR_SLOT.src_line == regdeps[i].line)
8489 ++i;
8490 continue;
8493 /* clear dependencies which are automatically cleared by a stop, or
8494 those that have reached the appropriate state of insn serialization */
8495 if (dep->semantics == IA64_DVS_IMPLIED
8496 || dep->semantics == IA64_DVS_IMPLIEDF
8497 || regdeps[i].insn_srlz == STATE_SRLZ)
8499 print_dependency ("Removing", i);
8500 regdeps[i] = regdeps[--regdepslen];
8502 else
8504 if (dep->semantics == IA64_DVS_DATA
8505 || dep->semantics == IA64_DVS_INSTR
8506 || dep->semantics == IA64_DVS_SPECIFIC)
8508 if (regdeps[i].insn_srlz == STATE_NONE)
8509 regdeps[i].insn_srlz = STATE_STOP;
8510 if (regdeps[i].data_srlz == STATE_NONE)
8511 regdeps[i].data_srlz = STATE_STOP;
8513 ++i;
8518 /* Add the given resource usage spec to the list of active dependencies. */
8520 static void
8521 mark_resource (idesc, dep, spec, depind, path)
8522 struct ia64_opcode *idesc ATTRIBUTE_UNUSED;
8523 const struct ia64_dependency *dep ATTRIBUTE_UNUSED;
8524 struct rsrc *spec;
8525 int depind;
8526 int path;
8528 if (regdepslen == regdepstotlen)
8530 regdepstotlen += 20;
8531 regdeps = (struct rsrc *)
8532 xrealloc ((void *) regdeps,
8533 regdepstotlen * sizeof (struct rsrc));
8536 regdeps[regdepslen] = *spec;
8537 regdeps[regdepslen].depind = depind;
8538 regdeps[regdepslen].path = path;
8539 regdeps[regdepslen].file = CURR_SLOT.src_file;
8540 regdeps[regdepslen].line = CURR_SLOT.src_line;
8542 print_dependency ("Adding", regdepslen);
8544 ++regdepslen;
8547 static void
8548 print_dependency (action, depind)
8549 const char *action;
8550 int depind;
8552 if (md.debug_dv)
8554 fprintf (stderr, " %s %s '%s'",
8555 action, dv_mode[(regdeps[depind].dependency)->mode],
8556 (regdeps[depind].dependency)->name);
8557 if (regdeps[depind].specific && regdeps[depind].index != 0)
8558 fprintf (stderr, " (%d)", regdeps[depind].index);
8559 if (regdeps[depind].mem_offset.hint)
8561 fputs (" ", stderr);
8562 fprintf_vma (stderr, regdeps[depind].mem_offset.base);
8563 fputs ("+", stderr);
8564 fprintf_vma (stderr, regdeps[depind].mem_offset.offset);
8566 fprintf (stderr, "\n");
8570 static void
8571 instruction_serialization ()
8573 int i;
8574 if (md.debug_dv)
8575 fprintf (stderr, " Instruction serialization\n");
8576 for (i = 0; i < regdepslen; i++)
8577 if (regdeps[i].insn_srlz == STATE_STOP)
8578 regdeps[i].insn_srlz = STATE_SRLZ;
8581 static void
8582 data_serialization ()
8584 int i = 0;
8585 if (md.debug_dv)
8586 fprintf (stderr, " Data serialization\n");
8587 while (i < regdepslen)
8589 if (regdeps[i].data_srlz == STATE_STOP
8590 /* Note: as of 991210, all "other" dependencies are cleared by a
8591 data serialization. This might change with new tables */
8592 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8594 print_dependency ("Removing", i);
8595 regdeps[i] = regdeps[--regdepslen];
8597 else
8598 ++i;
8602 /* Insert stops and serializations as needed to avoid DVs. */
8604 static void
8605 remove_marked_resource (rs)
8606 struct rsrc *rs;
8608 switch (rs->dependency->semantics)
8610 case IA64_DVS_SPECIFIC:
8611 if (md.debug_dv)
8612 fprintf (stderr, "Implementation-specific, assume worst case...\n");
8613 /* ...fall through... */
8614 case IA64_DVS_INSTR:
8615 if (md.debug_dv)
8616 fprintf (stderr, "Inserting instr serialization\n");
8617 if (rs->insn_srlz < STATE_STOP)
8618 insn_group_break (1, 0, 0);
8619 if (rs->insn_srlz < STATE_SRLZ)
8621 int oldqp = CURR_SLOT.qp_regno;
8622 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8623 /* Manually jam a srlz.i insn into the stream */
8624 CURR_SLOT.qp_regno = 0;
8625 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8626 instruction_serialization ();
8627 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8628 if (++md.num_slots_in_use >= NUM_SLOTS)
8629 emit_one_bundle ();
8630 CURR_SLOT.qp_regno = oldqp;
8631 CURR_SLOT.idesc = oldidesc;
8633 insn_group_break (1, 0, 0);
8634 break;
8635 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
8636 "other" types of DV are eliminated
8637 by a data serialization */
8638 case IA64_DVS_DATA:
8639 if (md.debug_dv)
8640 fprintf (stderr, "Inserting data serialization\n");
8641 if (rs->data_srlz < STATE_STOP)
8642 insn_group_break (1, 0, 0);
8644 int oldqp = CURR_SLOT.qp_regno;
8645 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8646 /* Manually jam a srlz.d insn into the stream */
8647 CURR_SLOT.qp_regno = 0;
8648 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
8649 data_serialization ();
8650 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8651 if (++md.num_slots_in_use >= NUM_SLOTS)
8652 emit_one_bundle ();
8653 CURR_SLOT.qp_regno = oldqp;
8654 CURR_SLOT.idesc = oldidesc;
8656 break;
8657 case IA64_DVS_IMPLIED:
8658 case IA64_DVS_IMPLIEDF:
8659 if (md.debug_dv)
8660 fprintf (stderr, "Inserting stop\n");
8661 insn_group_break (1, 0, 0);
8662 break;
8663 default:
8664 break;
8668 /* Check the resources used by the given opcode against the current dependency
8669 list.
8671 The check is run once for each execution path encountered. In this case,
8672 a unique execution path is the sequence of instructions following a code
8673 entry point, e.g. the following has three execution paths, one starting
8674 at L0, one at L1, and one at L2.
8676 L0: nop
8677 L1: add
8678 L2: add
8679 br.ret
8682 static void
8683 check_dependencies (idesc)
8684 struct ia64_opcode *idesc;
8686 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8687 int path;
8688 int i;
8690 /* Note that the number of marked resources may change within the
8691 loop if in auto mode. */
8692 i = 0;
8693 while (i < regdepslen)
8695 struct rsrc *rs = &regdeps[i];
8696 const struct ia64_dependency *dep = rs->dependency;
8697 int chkind;
8698 int note;
8699 int start_over = 0;
8701 if (dep->semantics == IA64_DVS_NONE
8702 || (chkind = depends_on (rs->depind, idesc)) == -1)
8704 ++i;
8705 continue;
8708 note = NOTE (opdeps->chks[chkind]);
8710 /* Check this resource against each execution path seen thus far. */
8711 for (path = 0; path <= md.path; path++)
8713 int matchtype;
8715 /* If the dependency wasn't on the path being checked, ignore it. */
8716 if (rs->path < path)
8717 continue;
8719 /* If the QP for this insn implies a QP which has branched, don't
8720 bother checking. Ed. NOTE: I don't think this check is terribly
8721 useful; what's the point of generating code which will only be
8722 reached if its QP is zero?
8723 This code was specifically inserted to handle the following code,
8724 based on notes from Intel's DV checking code, where p1 implies p2.
8726 mov r4 = 2
8727 (p2) br.cond L
8728 (p1) mov r4 = 7
8730 if (CURR_SLOT.qp_regno != 0)
8732 int skip = 0;
8733 int implies;
8734 for (implies = 0; implies < qp_implieslen; implies++)
8736 if (qp_implies[implies].path >= path
8737 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
8738 && qp_implies[implies].p2_branched)
8740 skip = 1;
8741 break;
8744 if (skip)
8745 continue;
8748 if ((matchtype = resources_match (rs, idesc, note,
8749 CURR_SLOT.qp_regno, path)) != 0)
8751 char msg[1024];
8752 char pathmsg[256] = "";
8753 char indexmsg[256] = "";
8754 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
8756 if (path != 0)
8757 sprintf (pathmsg, " when entry is at label '%s'",
8758 md.entry_labels[path - 1]);
8759 if (rs->specific && rs->index != 0)
8760 sprintf (indexmsg, ", specific resource number is %d",
8761 rs->index);
8762 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8763 idesc->name,
8764 (certain ? "violates" : "may violate"),
8765 dv_mode[dep->mode], dep->name,
8766 dv_sem[dep->semantics],
8767 pathmsg, indexmsg);
8769 if (md.explicit_mode)
8771 as_warn ("%s", msg);
8772 if (path < md.path)
8773 as_warn (_("Only the first path encountering the conflict "
8774 "is reported"));
8775 as_warn_where (rs->file, rs->line,
8776 _("This is the location of the "
8777 "conflicting usage"));
8778 /* Don't bother checking other paths, to avoid duplicating
8779 the same warning */
8780 break;
8782 else
8784 if (md.debug_dv)
8785 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
8787 remove_marked_resource (rs);
8789 /* since the set of dependencies has changed, start over */
8790 /* FIXME -- since we're removing dvs as we go, we
8791 probably don't really need to start over... */
8792 start_over = 1;
8793 break;
8797 if (start_over)
8798 i = 0;
8799 else
8800 ++i;
8804 /* Register new dependencies based on the given opcode. */
8806 static void
8807 mark_resources (idesc)
8808 struct ia64_opcode *idesc;
8810 int i;
8811 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8812 int add_only_qp_reads = 0;
8814 /* A conditional branch only uses its resources if it is taken; if it is
8815 taken, we stop following that path. The other branch types effectively
8816 *always* write their resources. If it's not taken, register only QP
8817 reads. */
8818 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
8820 add_only_qp_reads = 1;
8823 if (md.debug_dv)
8824 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
8826 for (i = 0; i < opdeps->nregs; i++)
8828 const struct ia64_dependency *dep;
8829 struct rsrc specs[MAX_SPECS];
8830 int note;
8831 int path;
8832 int count;
8834 dep = ia64_find_dependency (opdeps->regs[i]);
8835 note = NOTE (opdeps->regs[i]);
8837 if (add_only_qp_reads
8838 && !(dep->mode == IA64_DV_WAR
8839 && (dep->specifier == IA64_RS_PR
8840 || dep->specifier == IA64_RS_PRr
8841 || dep->specifier == IA64_RS_PR63)))
8842 continue;
8844 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
8846 #if 0
8847 if (md.debug_dv && !count)
8848 fprintf (stderr, " No %s %s usage found (path %d)\n",
8849 dv_mode[dep->mode], dep->name, md.path);
8850 #endif
8852 while (count-- > 0)
8854 mark_resource (idesc, dep, &specs[count],
8855 DEP (opdeps->regs[i]), md.path);
8858 /* The execution path may affect register values, which may in turn
8859 affect which indirect-access resources are accessed. */
8860 switch (dep->specifier)
8862 default:
8863 break;
8864 case IA64_RS_CPUID:
8865 case IA64_RS_DBR:
8866 case IA64_RS_IBR:
8867 case IA64_RS_MSR:
8868 case IA64_RS_PKR:
8869 case IA64_RS_PMC:
8870 case IA64_RS_PMD:
8871 case IA64_RS_RR:
8872 for (path = 0; path < md.path; path++)
8874 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
8875 while (count-- > 0)
8876 mark_resource (idesc, dep, &specs[count],
8877 DEP (opdeps->regs[i]), path);
8879 break;
8884 /* Remove dependencies when they no longer apply. */
8886 static void
8887 update_dependencies (idesc)
8888 struct ia64_opcode *idesc;
8890 int i;
8892 if (strcmp (idesc->name, "srlz.i") == 0)
8894 instruction_serialization ();
8896 else if (strcmp (idesc->name, "srlz.d") == 0)
8898 data_serialization ();
8900 else if (is_interruption_or_rfi (idesc)
8901 || is_taken_branch (idesc))
8903 /* Although technically the taken branch doesn't clear dependencies
8904 which require a srlz.[id], we don't follow the branch; the next
8905 instruction is assumed to start with a clean slate. */
8906 regdepslen = 0;
8907 md.path = 0;
8909 else if (is_conditional_branch (idesc)
8910 && CURR_SLOT.qp_regno != 0)
8912 int is_call = strstr (idesc->name, ".call") != NULL;
8914 for (i = 0; i < qp_implieslen; i++)
8916 /* If the conditional branch's predicate is implied by the predicate
8917 in an existing dependency, remove that dependency. */
8918 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
8920 int depind = 0;
8921 /* Note that this implied predicate takes a branch so that if
8922 a later insn generates a DV but its predicate implies this
8923 one, we can avoid the false DV warning. */
8924 qp_implies[i].p2_branched = 1;
8925 while (depind < regdepslen)
8927 if (regdeps[depind].qp_regno == qp_implies[i].p1)
8929 print_dependency ("Removing", depind);
8930 regdeps[depind] = regdeps[--regdepslen];
8932 else
8933 ++depind;
8937 /* Any marked resources which have this same predicate should be
8938 cleared, provided that the QP hasn't been modified between the
8939 marking instruction and the branch. */
8940 if (is_call)
8942 insn_group_break (0, CURR_SLOT.qp_regno, 1);
8944 else
8946 i = 0;
8947 while (i < regdepslen)
8949 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
8950 && regdeps[i].link_to_qp_branch
8951 && (regdeps[i].file != CURR_SLOT.src_file
8952 || regdeps[i].line != CURR_SLOT.src_line))
8954 /* Treat like a taken branch */
8955 print_dependency ("Removing", i);
8956 regdeps[i] = regdeps[--regdepslen];
8958 else
8959 ++i;
8965 /* Examine the current instruction for dependency violations. */
8967 static int
8968 check_dv (idesc)
8969 struct ia64_opcode *idesc;
8971 if (md.debug_dv)
8973 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
8974 idesc->name, CURR_SLOT.src_line,
8975 idesc->dependencies->nchks,
8976 idesc->dependencies->nregs);
8979 /* Look through the list of currently marked resources; if the current
8980 instruction has the dependency in its chks list which uses that resource,
8981 check against the specific resources used. */
8982 check_dependencies (idesc);
8984 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8985 then add them to the list of marked resources. */
8986 mark_resources (idesc);
8988 /* There are several types of dependency semantics, and each has its own
8989 requirements for being cleared
8991 Instruction serialization (insns separated by interruption, rfi, or
8992 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8994 Data serialization (instruction serialization, or writer + srlz.d +
8995 reader, where writer and srlz.d are in separate groups) clears
8996 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8997 always be the case).
8999 Instruction group break (groups separated by stop, taken branch,
9000 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9002 update_dependencies (idesc);
9004 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9005 warning. Keep track of as many as possible that are useful. */
9006 note_register_values (idesc);
9008 /* We don't need or want this anymore. */
9009 md.mem_offset.hint = 0;
9011 return 0;
9014 /* Translate one line of assembly. Pseudo ops and labels do not show
9015 here. */
9016 void
9017 md_assemble (str)
9018 char *str;
9020 char *saved_input_line_pointer, *mnemonic;
9021 const struct pseudo_opcode *pdesc;
9022 struct ia64_opcode *idesc;
9023 unsigned char qp_regno;
9024 unsigned int flags;
9025 int ch;
9027 saved_input_line_pointer = input_line_pointer;
9028 input_line_pointer = str;
9030 /* extract the opcode (mnemonic): */
9032 mnemonic = input_line_pointer;
9033 ch = get_symbol_end ();
9034 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
9035 if (pdesc)
9037 *input_line_pointer = ch;
9038 (*pdesc->handler) (pdesc->arg);
9039 goto done;
9042 /* Find the instruction descriptor matching the arguments. */
9044 idesc = ia64_find_opcode (mnemonic);
9045 *input_line_pointer = ch;
9046 if (!idesc)
9048 as_bad ("Unknown opcode `%s'", mnemonic);
9049 goto done;
9052 idesc = parse_operands (idesc);
9053 if (!idesc)
9054 goto done;
9056 /* Handle the dynamic ops we can handle now: */
9057 if (idesc->type == IA64_TYPE_DYN)
9059 if (strcmp (idesc->name, "add") == 0)
9061 if (CURR_SLOT.opnd[2].X_op == O_register
9062 && CURR_SLOT.opnd[2].X_add_number < 4)
9063 mnemonic = "addl";
9064 else
9065 mnemonic = "adds";
9066 ia64_free_opcode (idesc);
9067 idesc = ia64_find_opcode (mnemonic);
9068 #if 0
9069 know (!idesc->next);
9070 #endif
9072 else if (strcmp (idesc->name, "mov") == 0)
9074 enum ia64_opnd opnd1, opnd2;
9075 int rop;
9077 opnd1 = idesc->operands[0];
9078 opnd2 = idesc->operands[1];
9079 if (opnd1 == IA64_OPND_AR3)
9080 rop = 0;
9081 else if (opnd2 == IA64_OPND_AR3)
9082 rop = 1;
9083 else
9084 abort ();
9085 if (CURR_SLOT.opnd[rop].X_op == O_register
9086 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
9087 mnemonic = "mov.i";
9088 else
9089 mnemonic = "mov.m";
9090 ia64_free_opcode (idesc);
9091 idesc = ia64_find_opcode (mnemonic);
9092 while (idesc != NULL
9093 && (idesc->operands[0] != opnd1
9094 || idesc->operands[1] != opnd2))
9095 idesc = get_next_opcode (idesc);
9099 qp_regno = 0;
9100 if (md.qp.X_op == O_register)
9102 qp_regno = md.qp.X_add_number - REG_P;
9103 md.qp.X_op = O_absent;
9106 flags = idesc->flags;
9108 if ((flags & IA64_OPCODE_FIRST) != 0)
9109 insn_group_break (1, 0, 0);
9111 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
9113 as_bad ("`%s' cannot be predicated", idesc->name);
9114 goto done;
9117 /* Build the instruction. */
9118 CURR_SLOT.qp_regno = qp_regno;
9119 CURR_SLOT.idesc = idesc;
9120 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
9121 dwarf2_where (&CURR_SLOT.debug_line);
9123 /* Add unwind entry, if there is one. */
9124 if (unwind.current_entry)
9126 CURR_SLOT.unwind_record = unwind.current_entry;
9127 unwind.current_entry = NULL;
9130 /* Check for dependency violations. */
9131 if (md.detect_dv)
9132 check_dv (idesc);
9134 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9135 if (++md.num_slots_in_use >= NUM_SLOTS)
9136 emit_one_bundle ();
9138 if ((flags & IA64_OPCODE_LAST) != 0)
9139 insn_group_break (1, 0, 0);
9141 md.last_text_seg = now_seg;
9143 done:
9144 input_line_pointer = saved_input_line_pointer;
9147 /* Called when symbol NAME cannot be found in the symbol table.
9148 Should be used for dynamic valued symbols only. */
9150 symbolS *
9151 md_undefined_symbol (name)
9152 char *name ATTRIBUTE_UNUSED;
9154 return 0;
9157 /* Called for any expression that can not be recognized. When the
9158 function is called, `input_line_pointer' will point to the start of
9159 the expression. */
9161 void
9162 md_operand (e)
9163 expressionS *e;
9165 enum pseudo_type pseudo_type;
9166 const char *name;
9167 size_t len;
9168 int ch, i;
9170 switch (*input_line_pointer)
9172 case '@':
9173 /* Find what relocation pseudo-function we're dealing with. */
9174 pseudo_type = 0;
9175 ch = *++input_line_pointer;
9176 for (i = 0; i < NELEMS (pseudo_func); ++i)
9177 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
9179 len = strlen (pseudo_func[i].name);
9180 if (strncmp (pseudo_func[i].name + 1,
9181 input_line_pointer + 1, len - 1) == 0
9182 && !is_part_of_name (input_line_pointer[len]))
9184 input_line_pointer += len;
9185 pseudo_type = pseudo_func[i].type;
9186 break;
9189 switch (pseudo_type)
9191 case PSEUDO_FUNC_RELOC:
9192 SKIP_WHITESPACE ();
9193 if (*input_line_pointer != '(')
9195 as_bad ("Expected '('");
9196 goto err;
9198 /* Skip '('. */
9199 ++input_line_pointer;
9200 expression (e);
9201 if (*input_line_pointer++ != ')')
9203 as_bad ("Missing ')'");
9204 goto err;
9206 if (e->X_op != O_symbol)
9208 if (e->X_op != O_pseudo_fixup)
9210 as_bad ("Not a symbolic expression");
9211 goto err;
9213 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
9214 && i == FUNC_LT_RELATIVE)
9215 i = FUNC_LT_FPTR_RELATIVE;
9216 else
9218 as_bad ("Illegal combination of relocation functions");
9219 goto err;
9222 /* Make sure gas doesn't get rid of local symbols that are used
9223 in relocs. */
9224 e->X_op = O_pseudo_fixup;
9225 e->X_op_symbol = pseudo_func[i].u.sym;
9226 break;
9228 case PSEUDO_FUNC_CONST:
9229 e->X_op = O_constant;
9230 e->X_add_number = pseudo_func[i].u.ival;
9231 break;
9233 case PSEUDO_FUNC_REG:
9234 e->X_op = O_register;
9235 e->X_add_number = pseudo_func[i].u.ival;
9236 break;
9238 default:
9239 name = input_line_pointer - 1;
9240 get_symbol_end ();
9241 as_bad ("Unknown pseudo function `%s'", name);
9242 goto err;
9244 break;
9246 case '[':
9247 ++input_line_pointer;
9248 expression (e);
9249 if (*input_line_pointer != ']')
9251 as_bad ("Closing bracket misssing");
9252 goto err;
9254 else
9256 if (e->X_op != O_register)
9257 as_bad ("Register expected as index");
9259 ++input_line_pointer;
9260 e->X_op = O_index;
9262 break;
9264 default:
9265 break;
9267 return;
9269 err:
9270 ignore_rest_of_line ();
9273 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9274 a section symbol plus some offset. For relocs involving @fptr(),
9275 directives we don't want such adjustments since we need to have the
9276 original symbol's name in the reloc. */
9278 ia64_fix_adjustable (fix)
9279 fixS *fix;
9281 /* Prevent all adjustments to global symbols */
9282 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9283 return 0;
9285 switch (fix->fx_r_type)
9287 case BFD_RELOC_IA64_FPTR64I:
9288 case BFD_RELOC_IA64_FPTR32MSB:
9289 case BFD_RELOC_IA64_FPTR32LSB:
9290 case BFD_RELOC_IA64_FPTR64MSB:
9291 case BFD_RELOC_IA64_FPTR64LSB:
9292 case BFD_RELOC_IA64_LTOFF_FPTR22:
9293 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9294 return 0;
9295 default:
9296 break;
9299 return 1;
9303 ia64_force_relocation (fix)
9304 fixS *fix;
9306 switch (fix->fx_r_type)
9308 case BFD_RELOC_IA64_FPTR64I:
9309 case BFD_RELOC_IA64_FPTR32MSB:
9310 case BFD_RELOC_IA64_FPTR32LSB:
9311 case BFD_RELOC_IA64_FPTR64MSB:
9312 case BFD_RELOC_IA64_FPTR64LSB:
9314 case BFD_RELOC_IA64_LTOFF22:
9315 case BFD_RELOC_IA64_LTOFF64I:
9316 case BFD_RELOC_IA64_LTOFF_FPTR22:
9317 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9318 case BFD_RELOC_IA64_PLTOFF22:
9319 case BFD_RELOC_IA64_PLTOFF64I:
9320 case BFD_RELOC_IA64_PLTOFF64MSB:
9321 case BFD_RELOC_IA64_PLTOFF64LSB:
9322 return 1;
9324 default:
9325 return 0;
9327 return 0;
9330 /* Decide from what point a pc-relative relocation is relative to,
9331 relative to the pc-relative fixup. Er, relatively speaking. */
9332 long
9333 ia64_pcrel_from_section (fix, sec)
9334 fixS *fix;
9335 segT sec;
9337 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
9339 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
9340 off &= ~0xfUL;
9342 return off;
9345 /* This is called whenever some data item (not an instruction) needs a
9346 fixup. We pick the right reloc code depending on the byteorder
9347 currently in effect. */
9348 void
9349 ia64_cons_fix_new (f, where, nbytes, exp)
9350 fragS *f;
9351 int where;
9352 int nbytes;
9353 expressionS *exp;
9355 bfd_reloc_code_real_type code;
9356 fixS *fix;
9358 switch (nbytes)
9360 /* There are no reloc for 8 and 16 bit quantities, but we allow
9361 them here since they will work fine as long as the expression
9362 is fully defined at the end of the pass over the source file. */
9363 case 1: code = BFD_RELOC_8; break;
9364 case 2: code = BFD_RELOC_16; break;
9365 case 4:
9366 if (target_big_endian)
9367 code = BFD_RELOC_IA64_DIR32MSB;
9368 else
9369 code = BFD_RELOC_IA64_DIR32LSB;
9370 break;
9372 case 8:
9373 if (target_big_endian)
9374 code = BFD_RELOC_IA64_DIR64MSB;
9375 else
9376 code = BFD_RELOC_IA64_DIR64LSB;
9377 break;
9379 default:
9380 as_bad ("Unsupported fixup size %d", nbytes);
9381 ignore_rest_of_line ();
9382 return;
9384 if (exp->X_op == O_pseudo_fixup)
9386 /* ??? */
9387 exp->X_op = O_symbol;
9388 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
9390 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
9391 /* We need to store the byte order in effect in case we're going
9392 to fix an 8 or 16 bit relocation (for which there no real
9393 relocs available). See md_apply_fix(). */
9394 fix->tc_fix_data.bigendian = target_big_endian;
9397 /* Return the actual relocation we wish to associate with the pseudo
9398 reloc described by SYM and R_TYPE. SYM should be one of the
9399 symbols in the pseudo_func array, or NULL. */
9401 static bfd_reloc_code_real_type
9402 ia64_gen_real_reloc_type (sym, r_type)
9403 struct symbol *sym;
9404 bfd_reloc_code_real_type r_type;
9406 bfd_reloc_code_real_type new = 0;
9408 if (sym == NULL)
9410 return r_type;
9413 switch (S_GET_VALUE (sym))
9415 case FUNC_FPTR_RELATIVE:
9416 switch (r_type)
9418 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
9419 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
9420 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
9421 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
9422 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
9423 default: break;
9425 break;
9427 case FUNC_GP_RELATIVE:
9428 switch (r_type)
9430 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
9431 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
9432 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
9433 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
9434 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
9435 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
9436 default: break;
9438 break;
9440 case FUNC_LT_RELATIVE:
9441 switch (r_type)
9443 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
9444 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
9445 default: break;
9447 break;
9449 case FUNC_PC_RELATIVE:
9450 switch (r_type)
9452 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
9453 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
9454 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
9455 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
9456 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
9457 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
9458 default: break;
9460 break;
9462 case FUNC_PLT_RELATIVE:
9463 switch (r_type)
9465 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
9466 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
9467 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
9468 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
9469 default: break;
9471 break;
9473 case FUNC_SEC_RELATIVE:
9474 switch (r_type)
9476 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
9477 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
9478 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
9479 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
9480 default: break;
9482 break;
9484 case FUNC_SEG_RELATIVE:
9485 switch (r_type)
9487 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
9488 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
9489 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
9490 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
9491 default: break;
9493 break;
9495 case FUNC_LTV_RELATIVE:
9496 switch (r_type)
9498 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
9499 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
9500 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
9501 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
9502 default: break;
9504 break;
9506 case FUNC_LT_FPTR_RELATIVE:
9507 switch (r_type)
9509 case BFD_RELOC_IA64_IMM22:
9510 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9511 case BFD_RELOC_IA64_IMM64:
9512 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9513 default:
9514 break;
9516 break;
9517 default:
9518 abort ();
9520 /* Hmmmm. Should this ever occur? */
9521 if (new)
9522 return new;
9523 else
9524 return r_type;
9527 /* Here is where generate the appropriate reloc for pseudo relocation
9528 functions. */
9529 void
9530 ia64_validate_fix (fix)
9531 fixS *fix;
9533 switch (fix->fx_r_type)
9535 case BFD_RELOC_IA64_FPTR64I:
9536 case BFD_RELOC_IA64_FPTR32MSB:
9537 case BFD_RELOC_IA64_FPTR64LSB:
9538 case BFD_RELOC_IA64_LTOFF_FPTR22:
9539 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9540 if (fix->fx_offset != 0)
9541 as_bad_where (fix->fx_file, fix->fx_line,
9542 "No addend allowed in @fptr() relocation");
9543 break;
9544 default:
9545 break;
9548 return;
9551 static void
9552 fix_insn (fix, odesc, value)
9553 fixS *fix;
9554 const struct ia64_operand *odesc;
9555 valueT value;
9557 bfd_vma insn[3], t0, t1, control_bits;
9558 const char *err;
9559 char *fixpos;
9560 long slot;
9562 slot = fix->fx_where & 0x3;
9563 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9565 /* Bundles are always in little-endian byte order */
9566 t0 = bfd_getl64 (fixpos);
9567 t1 = bfd_getl64 (fixpos + 8);
9568 control_bits = t0 & 0x1f;
9569 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9570 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9571 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9573 err = NULL;
9574 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
9576 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9577 insn[2] |= (((value & 0x7f) << 13)
9578 | (((value >> 7) & 0x1ff) << 27)
9579 | (((value >> 16) & 0x1f) << 22)
9580 | (((value >> 21) & 0x1) << 21)
9581 | (((value >> 63) & 0x1) << 36));
9583 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9585 if (value & ~0x3fffffffffffffffULL)
9586 err = "integer operand out of range";
9587 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9588 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9590 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9592 value >>= 4;
9593 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9594 insn[2] |= ((((value >> 59) & 0x1) << 36)
9595 | (((value >> 0) & 0xfffff) << 13));
9597 else
9598 err = (*odesc->insert) (odesc, value, insn + slot);
9600 if (err)
9601 as_bad_where (fix->fx_file, fix->fx_line, err);
9603 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9604 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
9605 number_to_chars_littleendian (fixpos + 0, t0, 8);
9606 number_to_chars_littleendian (fixpos + 8, t1, 8);
9609 /* Attempt to simplify or even eliminate a fixup. The return value is
9610 ignored; perhaps it was once meaningful, but now it is historical.
9611 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9613 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9614 (if possible). */
9616 md_apply_fix3 (fix, valuep, seg)
9617 fixS *fix;
9618 valueT *valuep;
9619 segT seg ATTRIBUTE_UNUSED;
9621 char *fixpos;
9622 valueT value = *valuep;
9623 int adjust = 0;
9625 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9627 if (fix->fx_pcrel)
9629 switch (fix->fx_r_type)
9631 case BFD_RELOC_IA64_DIR32MSB:
9632 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9633 adjust = 1;
9634 break;
9636 case BFD_RELOC_IA64_DIR32LSB:
9637 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9638 adjust = 1;
9639 break;
9641 case BFD_RELOC_IA64_DIR64MSB:
9642 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
9643 adjust = 1;
9644 break;
9646 case BFD_RELOC_IA64_DIR64LSB:
9647 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
9648 adjust = 1;
9649 break;
9651 default:
9652 break;
9655 if (fix->fx_addsy)
9657 switch (fix->fx_r_type)
9659 case 0:
9660 as_bad_where (fix->fx_file, fix->fx_line,
9661 "%s must have a constant value",
9662 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
9663 break;
9665 default:
9666 break;
9669 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9670 work. There should be a better way to handle this. */
9671 if (adjust)
9672 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
9674 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
9676 if (fix->tc_fix_data.bigendian)
9677 number_to_chars_bigendian (fixpos, value, fix->fx_size);
9678 else
9679 number_to_chars_littleendian (fixpos, value, fix->fx_size);
9680 fix->fx_done = 1;
9681 return 1;
9683 else
9685 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
9686 fix->fx_done = 1;
9687 return 1;
9689 return 1;
9692 /* Generate the BFD reloc to be stuck in the object file from the
9693 fixup used internally in the assembler. */
9695 arelent *
9696 tc_gen_reloc (sec, fixp)
9697 asection *sec ATTRIBUTE_UNUSED;
9698 fixS *fixp;
9700 arelent *reloc;
9702 reloc = xmalloc (sizeof (*reloc));
9703 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9704 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9705 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9706 reloc->addend = fixp->fx_offset;
9707 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
9709 if (!reloc->howto)
9711 as_bad_where (fixp->fx_file, fixp->fx_line,
9712 "Cannot represent %s relocation in object file",
9713 bfd_get_reloc_code_name (fixp->fx_r_type));
9715 return reloc;
9718 /* Turn a string in input_line_pointer into a floating point constant
9719 of type TYPE, and store the appropriate bytes in *LIT. The number
9720 of LITTLENUMS emitted is stored in *SIZE. An error message is
9721 returned, or NULL on OK. */
9723 #define MAX_LITTLENUMS 5
9725 char *
9726 md_atof (type, lit, size)
9727 int type;
9728 char *lit;
9729 int *size;
9731 LITTLENUM_TYPE words[MAX_LITTLENUMS];
9732 LITTLENUM_TYPE *word;
9733 char *t;
9734 int prec;
9736 switch (type)
9738 /* IEEE floats */
9739 case 'f':
9740 case 'F':
9741 case 's':
9742 case 'S':
9743 prec = 2;
9744 break;
9746 case 'd':
9747 case 'D':
9748 case 'r':
9749 case 'R':
9750 prec = 4;
9751 break;
9753 case 'x':
9754 case 'X':
9755 case 'p':
9756 case 'P':
9757 prec = 5;
9758 break;
9760 default:
9761 *size = 0;
9762 return "Bad call to MD_ATOF()";
9764 t = atof_ieee (input_line_pointer, type, words);
9765 if (t)
9766 input_line_pointer = t;
9767 *size = prec * sizeof (LITTLENUM_TYPE);
9769 for (word = words + prec - 1; prec--;)
9771 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
9772 lit += sizeof (LITTLENUM_TYPE);
9774 return 0;
9777 /* Round up a section's size to the appropriate boundary. */
9778 valueT
9779 md_section_align (seg, size)
9780 segT seg;
9781 valueT size;
9783 int align = bfd_get_section_alignment (stdoutput, seg);
9784 valueT mask = ((valueT) 1 << align) - 1;
9786 return (size + mask) & ~mask;
9789 /* Handle ia64 specific semantics of the align directive. */
9791 void
9792 ia64_md_do_align (n, fill, len, max)
9793 int n;
9794 const char *fill;
9795 int len ATTRIBUTE_UNUSED;
9796 int max;
9798 if (subseg_text_p (now_seg))
9799 ia64_flush_insns ();
9802 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9803 of an rs_align_code fragment. */
9805 void
9806 ia64_handle_align (fragp)
9807 fragS *fragp;
9809 /* Use mfi bundle of nops with no stop bits. */
9810 static const unsigned char be_nop[]
9811 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9812 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9813 static const unsigned char le_nop[]
9814 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9815 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9817 int bytes;
9818 char *p;
9820 if (fragp->fr_type != rs_align_code)
9821 return;
9823 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
9824 p = fragp->fr_literal + fragp->fr_fix;
9826 /* Make sure we are on a 16-byte boundary, in case someone has been
9827 putting data into a text section. */
9828 if (bytes & 15)
9830 int fix = bytes & 15;
9831 memset (p, 0, fix);
9832 p += fix;
9833 bytes -= fix;
9834 fragp->fr_fix += fix;
9837 memcpy (p, (target_big_endian ? be_nop : le_nop), 16);
9838 fragp->fr_var = 16;