opcodes/fr30-desc.h

   1 /* CPU data header for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef FR30_CPU_H
  26 #define FR30_CPU_H
  27
  28 #define CGEN_ARCH fr30
  29
  30 /* Given symbol S, return fr30_cgen_<S>.  */
  31 #define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_FR30BF
  35
  36 #define CGEN_INSN_LSB0_P 0
  37
  38 /* Maximum size of any insn (in bytes).  */
  39 #define CGEN_MAX_INSN_SIZE 6
  40
  41 #define CGEN_INT_INSN_P 0
  42
  43 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  44
  45 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  46    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  47    we can't hash on everything up to the space.  */
  48 #define CGEN_MNEMONIC_OPERANDS
  49 /* Maximum number of operands any insn or macro-insn has.  */
  50 #define CGEN_MAX_INSN_OPERANDS 16
  51
  52 /* Maximum number of fields in an instruction.  */
  53 #define CGEN_MAX_IFMT_OPERANDS 7
  54
  55 /* Enums.  */
  56
  57 /* Enum declaration for insn op1 enums.  */
  58 typedef enum insn_op1 {
  59   OP1_0, OP1_1, OP1_2, OP1_3
  60  , OP1_4, OP1_5, OP1_6, OP1_7
  61  , OP1_8, OP1_9, OP1_A, OP1_B
  62  , OP1_C, OP1_D, OP1_E, OP1_F
  63 } INSN_OP1;
  64
  65 /* Enum declaration for insn op2 enums.  */
  66 typedef enum insn_op2 {
  67   OP2_0, OP2_1, OP2_2, OP2_3
  68  , OP2_4, OP2_5, OP2_6, OP2_7
  69  , OP2_8, OP2_9, OP2_A, OP2_B
  70  , OP2_C, OP2_D, OP2_E, OP2_F
  71 } INSN_OP2;
  72
  73 /* Enum declaration for insn op3 enums.  */
  74 typedef enum insn_op3 {
  75   OP3_0, OP3_1, OP3_2, OP3_3
  76  , OP3_4, OP3_5, OP3_6, OP3_7
  77  , OP3_8, OP3_9, OP3_A, OP3_B
  78  , OP3_C, OP3_D, OP3_E, OP3_F
  79 } INSN_OP3;
  80
  81 /* Enum declaration for insn op4 enums.  */
  82 typedef enum insn_op4 {
  83   OP4_0
  84 } INSN_OP4;
  85
  86 /* Enum declaration for insn op5 enums.  */
  87 typedef enum insn_op5 {
  88   OP5_0, OP5_1
  89 } INSN_OP5;
  90
  91 /* Enum declaration for insn cc enums.  */
  92 typedef enum insn_cc {
  93   CC_RA, CC_NO, CC_EQ, CC_NE
  94  , CC_C, CC_NC, CC_N, CC_P
  95  , CC_V, CC_NV, CC_LT, CC_GE
  96  , CC_LE, CC_GT, CC_LS, CC_HI
  97 } INSN_CC;
  98
  99 /* Enum declaration for .  */
 100 typedef enum gr_names {
 101   H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
 102  , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
 103  , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
 104  , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
 105  , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15
 106 } GR_NAMES;
 107
 108 /* Enum declaration for .  */
 109 typedef enum cr_names {
 110   H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
 111  , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
 112  , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
 113  , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
 114 } CR_NAMES;
 115
 116 /* Enum declaration for .  */
 117 typedef enum dr_names {
 118   H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
 119  , H_DR_MDH, H_DR_MDL
 120 } DR_NAMES;
 121
 122 /* Attributes.  */
 123
 124 /* Enum declaration for machine type selection.  */
 125 typedef enum mach_attr {
 126   MACH_BASE, MACH_FR30, MACH_MAX
 127 } MACH_ATTR;
 128
 129 /* Enum declaration for instruction set selection.  */
 130 typedef enum isa_attr {
 131   ISA_FR30, ISA_MAX
 132 } ISA_ATTR;
 133
 134 /* Number of architecture variants.  */
 135 #define MAX_ISAS  1
 136 #define MAX_MACHS ((int) MACH_MAX)
 137
 138 /* Ifield support.  */
 139
 140 extern const struct cgen_ifld fr30_cgen_ifld_table[];
 141
 142 /* Ifield attribute indices.  */
 143
 144 /* Enum declaration for cgen_ifld attrs.  */
 145 typedef enum cgen_ifld_attr {
 146   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 147  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 148  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 149 } CGEN_IFLD_ATTR;
 150
 151 /* Number of non-boolean elements in cgen_ifld_attr.  */
 152 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 153
 154 /* Enum declaration for fr30 ifield types.  */
 155 typedef enum ifield_type {
 156   FR30_F_NIL, FR30_F_OP1, FR30_F_OP2, FR30_F_OP3
 157  , FR30_F_OP4, FR30_F_OP5, FR30_F_CC, FR30_F_CCC
 158  , FR30_F_RJ, FR30_F_RI, FR30_F_RS1, FR30_F_RS2
 159  , FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ, FR30_F_CRI
 160  , FR30_F_U4, FR30_F_U4C, FR30_F_I4, FR30_F_M4
 161  , FR30_F_U8, FR30_F_I8, FR30_F_I20_4, FR30_F_I20_16
 162  , FR30_F_I20, FR30_F_I32, FR30_F_UDISP6, FR30_F_DISP8
 163  , FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10, FR30_F_U10
 164  , FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9, FR30_F_DIR10
 165  , FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST, FR30_F_REGLIST_HI_LD
 166  , FR30_F_REGLIST_LOW_LD, FR30_F_MAX
 167 } IFIELD_TYPE;
 168
 169 #define MAX_IFLD ((int) FR30_F_MAX)
 170
 171 /* Hardware attribute indices.  */
 172
 173 /* Enum declaration for cgen_hw attrs.  */
 174 typedef enum cgen_hw_attr {
 175   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 176  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 177 } CGEN_HW_ATTR;
 178
 179 /* Number of non-boolean elements in cgen_hw_attr.  */
 180 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 181
 182 /* Enum declaration for fr30 hardware types.  */
 183 typedef enum cgen_hw_type {
 184   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 185  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
 186  , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
 187  , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
 188  , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
 189  , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
 190  , HW_H_ILM, HW_MAX
 191 } CGEN_HW_TYPE;
 192
 193 #define MAX_HW ((int) HW_MAX)
 194
 195 /* Operand attribute indices.  */
 196
 197 /* Enum declaration for cgen_operand attrs.  */
 198 typedef enum cgen_operand_attr {
 199   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 200  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 201  , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
 202  , CGEN_OPERAND_END_NBOOLS
 203 } CGEN_OPERAND_ATTR;
 204
 205 /* Number of non-boolean elements in cgen_operand_attr.  */
 206 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 207
 208 /* Enum declaration for fr30 operand types.  */
 209 typedef enum cgen_operand_type {
 210   FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
 211  , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
 212  , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
 213  , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
 214  , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
 215  , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
 216  , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
 217  , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
 218  , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
 219  , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
 220  , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
 221  , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
 222  , FR30_OPERAND_ILM, FR30_OPERAND_MAX
 223 } CGEN_OPERAND_TYPE;
 224
 225 /* Number of operands types.  */
 226 #define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
 227
 228 /* Maximum number of operands referenced by any insn.  */
 229 #define MAX_OPERAND_INSTANCES 8
 230
 231 /* Insn attribute indices.  */
 232
 233 /* Enum declaration for cgen_insn attrs.  */
 234 typedef enum cgen_insn_attr {
 235   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 236  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
 237  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
 238  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 239 } CGEN_INSN_ATTR;
 240
 241 /* Number of non-boolean elements in cgen_insn_attr.  */
 242 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 243
 244 /* cgen.h uses things we just defined.  */
 245 #include "opcode/cgen.h"
 246
 247 /* Attributes.  */
 248 extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[];
 249 extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[];
 250 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
 251 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
 252
 253 /* Hardware decls.  */
 254
 255 extern CGEN_KEYWORD fr30_cgen_opval_gr_names;
 256 extern CGEN_KEYWORD fr30_cgen_opval_cr_names;
 257 extern CGEN_KEYWORD fr30_cgen_opval_dr_names;
 258 extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
 259 extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
 260 extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
 261 extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
 262
 263
 264
 265
 266 #endif /* FR30_CPU_H */