1 2010-12-30 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (print_insn): Support bfd_mach_x64_32 and
4 bfd_mach_x64_32_intel_syntax.
6 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
8 * mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
9 (mips_builtin_opcodes): Add loongson3a specific instructions.
10 * mips-dis.c (print_insn_args): Handle the new arguments +a|b|c|z|Z.
12 2010-12-11 Mingming Sun <mingm.sun@gmail.com>
14 * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
15 fixed point instructions.
17 2010-12-09 Mike Frysinger <vapier@gentoo.org>
19 * .gitignore: New file.
21 2010-11-25 Alan Modra <amodra@gmail.com>
26 * po/zh_CN.po: Update.
28 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
30 * mips-dis.c (mips_arch_choices): Add loongson3a.
31 * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
32 (mips_builtin_opcodes): Modify some instructions' membership from
35 2010-11-10 Nick Clifton <nickc@redhat.com>
37 * po/fi.po: Updated Finnish translation.
39 2010-11-05 Tristan Gingold <gingold@adacore.com>
41 * po/opcodes.pot: Regenerate
43 2010-10-28 Maciej W. Rozycki <macro@codesourcery.com>
45 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
47 2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
49 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
51 2010-10-25 Chao-ying Fu <fu@mips.com>
53 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
55 2010-10-25 Nathan Sidwell <nathan@codesourcery.com>
57 * tic6x-dis.c: Add attribution.
59 2010-10-22 Alan Modra <amodra@gmail.com>
61 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
62 * Makefile.in: Regenerate.
64 2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
66 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
67 macros before their corresponding MIPS III hardware instructions.
69 2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
71 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
73 * i386-init.h: Regenerated.
75 2010-10-15 Mike Frysinger <vapier@gentoo.org>
77 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
79 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
81 * i386-opc.tbl: Remove CheckRegSize from movq.
82 * i386-tbl.h: Regenerated.
84 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
86 * i386-opc.tbl: Remove CheckRegSize from instructions with
87 0, 1 or fixed operands.
88 * i386-tbl.h: Regenerated.
90 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-gen.c (opcode_modifiers): Add CheckRegSize.
94 * i386-opc.h (CheckRegSize): New.
95 (i386_opcode_modifier): Add checkregsize.
97 * i386-opc.tbl: Add CheckRegSize to instructions which
98 require register size check.
99 * i386-tbl.h: Regenerated.
101 2010-10-12 Andreas Schwab <schwab@linux-m68k.org>
103 * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
105 2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
107 * s390-opc.c: Make the instruction masks for the load/store on
108 condition instructions to cover the condition code mask as well.
109 * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
111 2010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
112 Jiang Jilin <freephp@gmail.com>
114 * Makefile.am (libopcodes_a_SOURCES): New as empty.
115 * Makefile.in: Regenerate.
117 2010-10-09 Matt Rice <ratmice@gmail.com>
119 * fr30-desc.h: Regenerate.
120 * frv-desc.h: Regenerate.
121 * ip2k-desc.h: Regenerate.
122 * iq2000-desc.h: Regenerate.
123 * lm32-desc.h: Regenerate.
124 * m32c-desc.h: Regenerate.
125 * m32r-desc.h: Regenerate.
126 * mep-desc.h: Regenerate.
127 * mep-opc.c: Regenerate.
128 * mt-desc.h: Regenerate.
129 * openrisc-desc.h: Regenerate.
130 * xc16x-desc.h: Regenerate.
131 * xstormy16-desc.h: Regenerate.
133 2010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
135 Fix build with -DDEBUG=7
136 * frv-opc.c: Regenerate.
137 * or32-dis.c (DEBUG): Don't redefine.
138 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
139 Adapt DEBUG code to some type changes throughout.
140 * or32-opc.c (or32_extract): Likewise.
142 2010-10-07 Bernd Schmidt <bernds@codesourcery.com>
144 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
145 in SPKERNEL instructions.
147 2010-10-02 H.J. Lu <hongjiu.lu@intel.com>
150 * i386-dis.c (RMAL): Remove duplicate.
152 2010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
154 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
155 to parse all 6 parameters.
157 2010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
159 * s390-mkopc.c (main): Change description array size to 80.
160 Add maximum length of 79 to description parsing.
162 2010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
164 * configure: Regenerate.
166 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
168 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
169 (main): Recognize the new CPU string.
170 * s390-opc.c: Add new instruction formats and masks.
171 * s390-opc.txt: Add new z196 instructions.
173 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
175 * s390-dis.c (print_insn_s390): Pick instruction with most
177 * s390-opc.c: Add unused bits to the insn mask.
178 * s390-opc.txt: Reorder some instructions to prefer more recent
181 2010-09-27 Tejas Belagod <tejas.belagod@arm.com>
183 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
184 correction to unaligned PCs while printing comment.
186 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
188 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
189 (thumb32_opcodes): Likewise.
190 (banked_regname): New function.
191 (print_insn_arm): Add Virtualization Extensions support.
192 (print_insn_thumb32): Likewise.
194 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
196 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
199 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
201 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
202 (thumb32_opcodes): Likewise.
204 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
206 * arm-dis.c (arm_opcodes): Add support for pldw.
207 (thumb32_opcodes): Likewise.
209 2010-09-22 Robin Getz <robin.getz@analog.com>
211 * bfin-dis.c (fmtconst): Cast address to 32bits.
213 2010-09-22 Mike Frysinger <vapier@gentoo.org>
215 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
217 2010-09-22 Robin Getz <robin.getz@analog.com>
219 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
220 Reject P6/P7 to TESTSET.
221 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
223 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
224 P/D fields match all the time.
225 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
226 are 0 for accumulator compares.
227 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
228 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
229 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
230 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
231 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
232 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
234 (decode_dagMODim_0): Verify br field for IREG ops.
235 (decode_LDST_0): Reject preg load into same preg.
236 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
237 (print_insn_bfin): Likewise.
239 2010-09-22 Mike Frysinger <vapier@gentoo.org>
241 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
243 2010-09-22 Robin Getz <robin.getz@analog.com>
245 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
247 2010-09-22 Mike Frysinger <vapier@gentoo.org>
249 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
251 2010-09-22 Robin Getz <robin.getz@analog.com>
253 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
254 register values greater than 8.
255 (IS_RESERVEDREG, allreg, mostreg): New helpers.
256 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
257 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
258 (decode_CC2dreg_0): Check valid CC register number.
260 2010-09-22 Robin Getz <robin.getz@analog.com>
262 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
264 2010-09-22 Robin Getz <robin.getz@analog.com>
266 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
267 (reg_names): Likewise.
268 (decode_statbits): Likewise; while reformatting to make manageable.
270 2010-09-22 Mike Frysinger <vapier@gentoo.org>
272 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
273 (decode_pseudoOChar_0): New function.
274 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
276 2010-09-22 Robin Getz <robin.getz@analog.com>
278 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
279 LSHIFT instead of SHIFT.
281 2010-09-22 Mike Frysinger <vapier@gentoo.org>
283 * bfin-dis.c (constant_formats): Constify the whole structure.
284 (fmtconst): Add const to return value.
285 (reg_names): Mark const.
286 (decode_multfunc): Mark s0/s1 as const.
287 (decode_macfunc): Mark a/sop as const.
289 2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
291 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
293 2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
295 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
296 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
298 2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
300 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
303 2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
306 * i386-dis.c (sIv): New.
307 (dis386): Replace Iq with sIv on "pushT".
308 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
309 (x86_64_table): Replace {T|}/{P|} with P.
310 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
311 (OP_sI): Update v_mode. Remove w_mode.
313 2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
315 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
318 2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
320 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
323 2010-08-06 Quentin Neill <quentin.neill@amd.com>
325 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
326 to processor flags for PENTIUMPRO processors and later.
327 * i386-opc.h (enum): Add CpuNop.
328 (i386_cpu_flags): Add cpunop bit.
329 * i386-opc.tbl: Change nop cpu_flags.
330 * i386-init.h: Regenerated.
331 * i386-tbl.h: Likewise.
333 2010-08-06 Quentin Neill <quentin.neill@amd.com>
335 * i386-opc.h (enum): Fix typos in comments.
337 2010-08-06 Alan Modra <amodra@gmail.com>
339 * disassemble.c: Formatting.
340 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
342 2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
344 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
345 * i386-tbl.h: Regenerated.
347 2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
349 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
351 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
352 * i386-tbl.h: Regenerated.
354 2010-07-29 DJ Delorie <dj@redhat.com>
356 * rx-decode.opc (SRR): New.
357 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
358 r0,r0) and NOP3 (max r0,r0) special cases.
359 * rx-decode.c: Regenerate.
361 2010-07-28 H.J. Lu <hongjiu.lu@intel.com>
363 * i386-dis.c: Add 0F to VEX opcode enums.
365 2010-07-27 DJ Delorie <dj@redhat.com>
367 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
368 (rx_decode_opcode): Likewise.
369 * rx-decode.c: Regenerate.
371 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
372 Ina Pandit <ina.pandit@kpitcummins.com>
374 * v850-dis.c (v850_sreg_names): Updated structure for system
376 (float_cc_names): new structure for condition codes.
377 (print_value): Update the function that prints value.
378 (get_operand_value): New function to get the operand value.
379 (disassemble): Updated to handle the disassembly of instructions.
380 (print_insn_v850): Updated function to print instruction for different
382 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
383 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
384 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
385 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
386 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
387 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
388 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
389 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
390 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
391 (v850_operands): Update with the relocation name. Also update
392 the instructions with specific set of processors.
394 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
396 * arm-dis.c (print_insn_arm): Add cases for printing more
398 (print_insn_thumb32): Likewise.
400 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
402 * mips-dis.c (print_insn_mips): Correct branch instruction type
405 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
407 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
408 type and delay slot determination.
409 (print_insn_mips16): Extend branch instruction type and delay
410 slot determination to cover all instructions.
411 * mips16-opc.c (BR): Remove macro.
412 (UBR, CBR): New macros.
413 (mips16_opcodes): Update branch annotation for "b", "beqz",
414 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
417 2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
419 AVX Programming Reference (June, 2010)
420 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
421 * i386-opc.tbl: Likewise.
422 * i386-tbl.h: Regenerated.
424 2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
426 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
428 2010-07-03 Andreas Schwab <schwab@linux-m68k.org>
430 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
431 ppc_cpu_t before inverting.
432 (ppc_parse_cpu): Likewise.
433 (print_insn_powerpc): Likewise.
435 2010-07-03 Alan Modra <amodra@gmail.com>
437 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
438 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
439 (PPC64, MFDEC2): Update.
440 (NON32, NO371): Define.
441 (powerpc_opcode): Update to not use old opcode flags, and avoid
444 2010-07-03 DJ Delorie <dj@delorie.com>
446 * m32c-ibld.c: Regenerate.
448 2010-07-03 Alan Modra <amodra@gmail.com>
450 * ppc-opc.c (PWR2COM): Define.
451 (PPCPWR2): Add PPC_OPCODE_COMMON.
452 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
453 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
456 2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
458 AVX Programming Reference (June, 2010)
459 * i386-dis.c (PREFIX_0FAE_REG_0): New.
460 (PREFIX_0FAE_REG_1): Likewise.
461 (PREFIX_0FAE_REG_2): Likewise.
462 (PREFIX_0FAE_REG_3): Likewise.
463 (PREFIX_VEX_3813): Likewise.
464 (PREFIX_VEX_3A1D): Likewise.
465 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
466 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
468 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
469 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
470 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
472 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
473 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
474 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
476 * i386-opc.h (CpuXsaveopt): New.
477 (CpuFSGSBase): Likewise.
478 (CpuRdRnd): Likewise.
480 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
483 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
484 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
485 * i386-init.h: Regenerated.
486 * i386-tbl.h: Likewise.
488 2010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
490 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
493 2010-06-29 Alan Modra <amodra@gmail.com>
495 * maxq-dis.c: Delete file.
496 * Makefile.am: Remove references to maxq.
497 * configure.in: Likewise.
498 * disassemble.c: Likewise.
499 * Makefile.in: Regenerate.
500 * configure: Regenerate.
501 * po/POTFILES.in: Regenerate.
503 2010-06-29 Alan Modra <amodra@gmail.com>
505 * mep-dis.c: Regenerate.
507 2010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
509 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
511 2010-06-27 Alan Modra <amodra@gmail.com>
513 * arc-dis.c (arc_sprintf): Delete set but unused variables.
514 (decodeInstr): Likewise.
515 * dlx-dis.c (print_insn_dlx): Likewise.
516 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
517 * maxq-dis.c (check_move, print_insn): Likewise.
518 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
519 * msp430-dis.c (msp430_branchinstr): Likewise.
520 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
521 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
522 * sparc-dis.c (print_insn_sparc): Likewise.
523 * fr30-asm.c: Regenerate.
524 * frv-asm.c: Regenerate.
525 * ip2k-asm.c: Regenerate.
526 * iq2000-asm.c: Regenerate.
527 * lm32-asm.c: Regenerate.
528 * m32c-asm.c: Regenerate.
529 * m32r-asm.c: Regenerate.
530 * mep-asm.c: Regenerate.
531 * mt-asm.c: Regenerate.
532 * openrisc-asm.c: Regenerate.
533 * xc16x-asm.c: Regenerate.
534 * xstormy16-asm.c: Regenerate.
536 2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
539 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
541 2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
544 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
546 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
548 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
549 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
550 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
551 touch floating point regs and are enabled by COM, PPC or PPCCOM.
552 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
553 Treat lwsync as msync on e500.
555 2010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
557 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
559 2010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
561 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
562 constants is the same on 32-bit and 64-bit hosts.
564 2010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
566 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
567 .short directives so that they can be reassembled.
569 2010-05-26 Catherine Moore <clm@codesourcery.com>
570 David Ung <davidu@mips.com>
572 * mips-opc.c: Change membership to I1 for instructions ssnop and
575 2010-05-26 H.J. Lu <hongjiu.lu@intel.com>
577 * i386-dis.c (sib): New.
579 (print_insn): Call get_sib.
580 OP_E_memory): Use sib.
582 2010-05-26 Catherine Moore <clm@codesoourcery.com>
584 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
585 * mips-opc.c (I16): Remove.
586 (mips_builtin_op): Reclassify jalx.
588 2010-05-19 Alan Modra <amodra@gmail.com>
590 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
591 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
593 2010-05-13 Alan Modra <amodra@gmail.com>
595 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
597 2010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
599 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
601 (print_insn_thumb16): Add support for new %W format.
603 2010-05-07 Tristan Gingold <gingold@adacore.com>
605 * Makefile.in: Regenerate with automake 1.11.1.
608 2010-05-05 Nick Clifton <nickc@redhat.com>
610 * po/es.po: Updated Spanish translation.
612 2010-04-22 Nick Clifton <nickc@redhat.com>
614 * po/opcodes.pot: Updated by the Translation project.
615 * po/vi.po: Updated Vietnamese translation.
617 2010-04-16 H.J. Lu <hongjiu.lu@intel.com>
619 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
622 2010-04-09 Nick Clifton <nickc@redhat.com>
624 * i386-dis.c (print_insn): Remove unused variable op.
625 (OP_sI): Remove unused variable mask.
627 2010-04-07 Alan Modra <amodra@gmail.com>
629 * configure: Regenerate.
631 2010-04-06 Peter Bergner <bergner@vnet.ibm.com>
633 * ppc-opc.c (RBOPT): New define.
634 ("dccci"): Enable for PPCA2. Make operands optional.
635 ("iccci"): Likewise. Do not deprecate for PPC476.
637 2010-04-02 Masaki Muranaka <monaka@monami-software.com>
639 * cr16-opc.c (cr16_instruction): Fix typo in comment.
641 2010-03-25 Joseph Myers <joseph@codesourcery.com>
643 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
644 * Makefile.in: Regenerate.
645 * configure.in (bfd_tic6x_arch): New.
646 * configure: Regenerate.
647 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
648 (disassembler): Handle TI C6X.
651 2010-03-24 Mike Frysinger <vapier@gentoo.org>
653 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
655 2010-03-23 Joseph Myers <joseph@codesourcery.com>
657 * dis-buf.c (buffer_read_memory): Give error for reading just
658 before the start of memory.
660 2010-03-22 Sebastian Pop <sebastian.pop@amd.com>
661 Quentin Neill <quentin.neill@amd.com>
663 * i386-dis.c (OP_LWP_I): Removed.
664 (reg_table): Do not use OP_LWP_I, use Iq.
665 (OP_LWPCB_E): Remove use of names16.
667 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
668 should not set the Vex.length bit.
669 * i386-tbl.h: Regenerated.
671 2010-02-25 Edmar Wienskoski <edmar@freescale.com>
673 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
675 2010-02-24 Nick Clifton <nickc@redhat.com>
678 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
679 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
680 (thumb32_opcodes): Likewise.
682 2010-02-15 Nick Clifton <nickc@redhat.com>
684 * po/vi.po: Updated Vietnamese translation.
686 2010-02-12 Doug Evans <dje@sebabeach.org>
688 * lm32-opinst.c: Regenerate.
690 2010-02-11 Doug Evans <dje@sebabeach.org>
692 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
693 (print_address): Delete CGEN_PRINT_ADDRESS.
694 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
695 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
696 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
697 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
699 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
700 * frv-desc.c, * frv-desc.h, * frv-opc.c,
701 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
702 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
703 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
704 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
705 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
706 * mep-desc.c, * mep-desc.h, * mep-opc.c,
707 * mt-desc.c, * mt-desc.h, * mt-opc.c,
708 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
709 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
710 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
712 2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
714 * i386-dis.c: Update copyright.
715 * i386-gen.c: Likewise.
716 * i386-opc.h: Likewise.
717 * i386-opc.tbl: Likewise.
719 2010-02-10 Quentin Neill <quentin.neill@amd.com>
720 Sebastian Pop <sebastian.pop@amd.com>
722 * i386-dis.c (OP_EX_VexImmW): Reintroduced
723 function to handle 5th imm8 operand.
724 (PREFIX_VEX_3A48): Added.
725 (PREFIX_VEX_3A49): Added.
726 (VEX_W_3A48_P_2): Added.
727 (VEX_W_3A49_P_2): Added.
728 (prefix table): Added entries for PREFIX_VEX_3A48
730 (vex table): Added entries for VEX_W_3A48_P_2 and
732 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
733 for Vec_Imm4 operands.
734 * i386-opc.h (enum): Added Vec_Imm4.
735 (i386_operand_type): Added vec_imm4.
736 * i386-opc.tbl: Add entries for vpermilp[ds].
737 * i386-init.h: Regenerated.
738 * i386-tbl.h: Regenerated.
740 2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
742 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
743 and "pwr7". Move "a2" into alphabetical order.
745 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
747 * ppc-dis.c (ppc_opts): Add titan entry.
748 * ppc-opc.c (TITAN, MULHW): Define.
749 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
751 2010-02-03 Quentin Neill <quentin.neill@amd.com>
753 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
755 * i386-init.h: Regenerated.
757 2010-02-03 Anthony Green <green@moxielogic.com>
759 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
760 0x0f, and make 0x00 an illegal instruction.
762 2010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
764 * opcodes/arm-dis.c (struct arm_private_data): New.
765 (print_insn_coprocessor, print_insn_arm): Update to use struct
767 (is_mapping_symbol, get_map_sym_type): New functions.
768 (get_sym_code_type): Check the symbol's section. Do not check
770 (print_insn): Default to disassembling ARM mode code. Check
771 for mapping symbols separately from other symbols. Use
772 struct arm_private_data.
774 2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
776 * i386-dis.c (EXVexWdqScalar): New.
777 (vex_scalar_w_dq_mode): Likewise.
778 (prefix_table): Update entries for PREFIX_VEX_3899,
779 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
780 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
781 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
782 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
783 (intel_operand_size): Handle vex_scalar_w_dq_mode.
786 2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
788 * i386-dis.c (XMScalar): New.
789 (EXdScalar): Likewise.
790 (EXqScalar): Likewise.
791 (EXqScalarS): Likewise.
792 (VexScalar): Likewise.
793 (EXdVexScalarS): Likewise.
794 (EXqVexScalarS): Likewise.
795 (XMVexScalar): Likewise.
796 (scalar_mode): Likewise.
797 (d_scalar_mode): Likewise.
798 (d_scalar_swap_mode): Likewise.
799 (q_scalar_mode): Likewise.
800 (q_scalar_swap_mode): Likewise.
801 (vex_scalar_mode): Likewise.
802 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
803 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
804 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
805 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
806 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
807 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
808 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
809 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
810 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
811 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
812 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
813 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
814 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
815 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
816 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
817 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
818 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
819 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
820 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
821 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
822 q_scalar_mode, q_scalar_swap_mode.
823 (OP_XMM): Handle scalar_mode.
824 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
825 and q_scalar_swap_mode.
826 (OP_VEX): Handle vex_scalar_mode.
828 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
830 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
832 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
834 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
836 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
838 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
840 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
842 * i386-dis.c (Bad_Opcode): New.
843 (bad_opcode): Likewise.
844 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
845 (dis386_twobyte): Likewise.
846 (reg_table): Likewise.
847 (prefix_table): Likewise.
848 (x86_64_table): Likewise.
849 (vex_len_table): Likewise.
850 (vex_w_table): Likewise.
851 (mod_table): Likewise.
852 (rm_table): Likewise.
853 (float_reg): Likewise.
854 (reg_table): Remove trailing "(bad)" entries.
855 (prefix_table): Likewise.
856 (x86_64_table): Likewise.
857 (vex_len_table): Likewise.
858 (vex_w_table): Likewise.
859 (mod_table): Likewise.
860 (rm_table): Likewise.
861 (get_valid_dis386): Handle bytemode 0.
863 2010-01-23 H.J. Lu <hongjiu.lu@intel.com>
865 * i386-opc.h (VEXScalar): New.
867 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
869 * i386-tbl.h: Regenerated.
871 2010-01-21 H.J. Lu <hongjiu.lu@intel.com>
873 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
875 * i386-opc.tbl: Add xsave64 and xrstor64.
876 * i386-tbl.h: Regenerated.
878 2010-01-20 Nick Clifton <nickc@redhat.com>
881 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
882 based post-indexed addressing.
884 2010-01-15 Sebastian Pop <sebastian.pop@amd.com>
886 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
887 * i386-tbl.h: Regenerated.
889 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
891 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
894 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
896 * i386-dis.c (names_mm): New.
897 (intel_names_mm): Likewise.
898 (att_names_mm): Likewise.
899 (names_xmm): Likewise.
900 (intel_names_xmm): Likewise.
901 (att_names_xmm): Likewise.
902 (names_ymm): Likewise.
903 (intel_names_ymm): Likewise.
904 (att_names_ymm): Likewise.
905 (print_insn): Set names_mm, names_xmm and names_ymm.
906 (OP_MMX): Use names_mm, names_xmm and names_ymm.
912 (XMM_Fixup): Likewise.
914 (OP_EX_VexReg): Likewise.
915 (OP_Vex_2src): Likewise.
916 (OP_Vex_2src_1): Likewise.
917 (OP_Vex_2src_2): Likewise.
918 (OP_REG_VexI4): Likewise.
920 2010-01-13 H.J. Lu <hongjiu.lu@intel.com>
922 * i386-dis.c (print_insn): Update comments.
924 2010-01-12 H.J. Lu <hongjiu.lu@intel.com>
926 * i386-dis.c (rex_original): Removed.
927 (ckprefix): Remove rex_original.
928 (print_insn): Update comments.
930 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
932 * Makefile.in: Regenerate.
933 * configure: Regenerate.
935 2010-01-07 Doug Evans <dje@sebabeach.org>
937 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
938 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
939 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
940 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
941 * xstormy16-ibld.c: Regenerate.
943 2010-01-06 Quentin Neill <quentin.neill@amd.com>
945 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
946 * i386-init.h: Regenerated.
948 2010-01-06 Daniel Gutson <dgutson@codesourcery.com>
950 * arm-dis.c (print_insn): Fixed search for next symbol and data
951 dumping condition, and the initial mapping symbol state.
953 2010-01-05 Doug Evans <dje@sebabeach.org>
955 * cgen-ibld.in: #include "cgen/basic-modes.h".
956 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
957 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
958 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
959 * xstormy16-ibld.c: Regenerate.
961 2010-01-04 Nick Clifton <nickc@redhat.com>
964 * arm-dis.c (print_insn_coprocessor): Initialise value.
966 2010-01-04 Edmar Wienskoski <edmar@freescale.com>
968 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
970 2010-01-02 Doug Evans <dje@sebabeach.org>
972 * cgen-asm.in: Update copyright year.
973 * cgen-dis.in: Update copyright year.
974 * cgen-ibld.in: Update copyright year.
975 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
976 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
977 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
978 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
979 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
980 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
981 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
982 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
983 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
984 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
985 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
986 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
987 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
988 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
989 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
990 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
991 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
992 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
993 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
994 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
995 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
997 For older changes see ChangeLog-2009
1003 version-control: never