opcodes/m32r-desc.c

   1 /* CPU data for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <ctype.h>
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include "ansidecl.h"
  30 #include "bfd.h"
  31 #include "symcat.h"
  32 #include "m32r-desc.h"
  33 #include "m32r-opc.h"
  34 #include "opintl.h"
  35 #include "libiberty.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] =
  47 {
  48   { "base", MACH_BASE },
  49   { "m32r", MACH_M32R },
  50   { "m32rx", MACH_M32RX },
  51   { "max", MACH_MAX },
  52   { 0, 0 }
  53 };
  54
  55 static const CGEN_ATTR_ENTRY ISA_attr[] =
  56 {
  57   { "m32r", ISA_M32R },
  58   { "max", ISA_MAX },
  59   { 0, 0 }
  60 };
  61
  62 static const CGEN_ATTR_ENTRY PIPE_attr[] =
  63 {
  64   { "NONE", PIPE_NONE },
  65   { "O", PIPE_O },
  66   { "S", PIPE_S },
  67   { "OS", PIPE_OS },
  68   { 0, 0 }
  69 };
  70
  71 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
  72 {
  73   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  74   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  75   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  76   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  77   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  78   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  79   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  80   { "RELOC", &bool_attr[0], &bool_attr[0] },
  81   { 0, 0, 0 }
  82 };
  83
  84 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
  85 {
  86   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  87   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  88   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  89   { "PC", &bool_attr[0], &bool_attr[0] },
  90   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  91   { 0, 0, 0 }
  92 };
  93
  94 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
  95 {
  96   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  97   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  98   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  99   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 100   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 101   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 102   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 103   { "RELAX", &bool_attr[0], &bool_attr[0] },
 104   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 105   { "RELOC", &bool_attr[0], &bool_attr[0] },
 106   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 107   { 0, 0, 0 }
 108 };
 109
 110 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 111 {
 112   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 113   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
 114   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 115   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 116   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 117   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 118   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 119   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 120   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 121   { "RELAX", &bool_attr[0], &bool_attr[0] },
 122   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 123   { "PBB", &bool_attr[0], &bool_attr[0] },
 124   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
 125   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
 126   { 0, 0, 0 }
 127 };
 128
 129 /* Instruction set variants.  */
 130
 131 static const CGEN_ISA m32r_cgen_isa_table[] = {
 132   { "m32r", 32, 32, 16, 32 },
 133   { 0, 0, 0, 0, 0 }
 134 };
 135
 136 /* Machine variants.  */
 137
 138 static const CGEN_MACH m32r_cgen_mach_table[] = {
 139   { "m32r", "m32r", MACH_M32R },
 140   { "m32rx", "m32rx", MACH_M32RX },
 141   { 0, 0, 0 }
 142 };
 143
 144 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
 145 {
 146   { "fp", 13, {0, {0}}, 0, 0 },
 147   { "lr", 14, {0, {0}}, 0, 0 },
 148   { "sp", 15, {0, {0}}, 0, 0 },
 149   { "r0", 0, {0, {0}}, 0, 0 },
 150   { "r1", 1, {0, {0}}, 0, 0 },
 151   { "r2", 2, {0, {0}}, 0, 0 },
 152   { "r3", 3, {0, {0}}, 0, 0 },
 153   { "r4", 4, {0, {0}}, 0, 0 },
 154   { "r5", 5, {0, {0}}, 0, 0 },
 155   { "r6", 6, {0, {0}}, 0, 0 },
 156   { "r7", 7, {0, {0}}, 0, 0 },
 157   { "r8", 8, {0, {0}}, 0, 0 },
 158   { "r9", 9, {0, {0}}, 0, 0 },
 159   { "r10", 10, {0, {0}}, 0, 0 },
 160   { "r11", 11, {0, {0}}, 0, 0 },
 161   { "r12", 12, {0, {0}}, 0, 0 },
 162   { "r13", 13, {0, {0}}, 0, 0 },
 163   { "r14", 14, {0, {0}}, 0, 0 },
 164   { "r15", 15, {0, {0}}, 0, 0 }
 165 };
 166
 167 CGEN_KEYWORD m32r_cgen_opval_gr_names =
 168 {
 169   & m32r_cgen_opval_gr_names_entries[0],
 170   19,
 171   0, 0, 0, 0
 172 };
 173
 174 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 175 {
 176   { "psw", 0, {0, {0}}, 0, 0 },
 177   { "cbr", 1, {0, {0}}, 0, 0 },
 178   { "spi", 2, {0, {0}}, 0, 0 },
 179   { "spu", 3, {0, {0}}, 0, 0 },
 180   { "bpc", 6, {0, {0}}, 0, 0 },
 181   { "bbpsw", 8, {0, {0}}, 0, 0 },
 182   { "bbpc", 14, {0, {0}}, 0, 0 },
 183   { "cr0", 0, {0, {0}}, 0, 0 },
 184   { "cr1", 1, {0, {0}}, 0, 0 },
 185   { "cr2", 2, {0, {0}}, 0, 0 },
 186   { "cr3", 3, {0, {0}}, 0, 0 },
 187   { "cr4", 4, {0, {0}}, 0, 0 },
 188   { "cr5", 5, {0, {0}}, 0, 0 },
 189   { "cr6", 6, {0, {0}}, 0, 0 },
 190   { "cr7", 7, {0, {0}}, 0, 0 },
 191   { "cr8", 8, {0, {0}}, 0, 0 },
 192   { "cr9", 9, {0, {0}}, 0, 0 },
 193   { "cr10", 10, {0, {0}}, 0, 0 },
 194   { "cr11", 11, {0, {0}}, 0, 0 },
 195   { "cr12", 12, {0, {0}}, 0, 0 },
 196   { "cr13", 13, {0, {0}}, 0, 0 },
 197   { "cr14", 14, {0, {0}}, 0, 0 },
 198   { "cr15", 15, {0, {0}}, 0, 0 }
 199 };
 200
 201 CGEN_KEYWORD m32r_cgen_opval_cr_names =
 202 {
 203   & m32r_cgen_opval_cr_names_entries[0],
 204   23,
 205   0, 0, 0, 0
 206 };
 207
 208 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 209 {
 210   { "a0", 0, {0, {0}}, 0, 0 },
 211   { "a1", 1, {0, {0}}, 0, 0 }
 212 };
 213
 214 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 215 {
 216   & m32r_cgen_opval_h_accums_entries[0],
 217   2,
 218   0, 0, 0, 0
 219 };
 220
 221
 222
 223 /* The hardware table.  */
 224
 225 #define A(a) (1 << CONCAT2 (CGEN_HW_,a))
 226
 227 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
 228 {
 229   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 230   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 231   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 232   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 233   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 234   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
 235   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 236   { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 237   { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 238   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
 239   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
 240   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 241   { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
 242   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 243   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 244   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 245   { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 246   { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 247   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 248 };
 249
 250 #undef A
 251
 252 /* The instruction field table.  */
 253
 254 #define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))
 255
 256 const CGEN_IFLD m32r_cgen_ifld_table[] =
 257 {
 258   { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 259   { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 260   { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
 261   { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 262   { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 263   { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 264   { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 265   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 266   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
 267   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
 268   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 269   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
 270   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
 271   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 272   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 273   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 274   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 275   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 276   { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
 277   { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
 278   { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
 279   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
 280   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
 281   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
 282   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
 283   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
 284   { 0, 0, 0, 0, 0, 0, {0, {0}} }
 285 };
 286
 287 #undef A
 288
 289 /* The operand table.  */
 290
 291 #define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
 292 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
 293
 294 const CGEN_OPERAND m32r_cgen_operand_table[] =
 295 {
 296 /* pc: program counter */
 297   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
 298     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 299 /* sr: source register */
 300   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
 301     { 0, { (1<<MACH_BASE) } }  },
 302 /* dr: destination register */
 303   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
 304     { 0, { (1<<MACH_BASE) } }  },
 305 /* src1: source register 1 */
 306   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
 307     { 0, { (1<<MACH_BASE) } }  },
 308 /* src2: source register 2 */
 309   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
 310     { 0, { (1<<MACH_BASE) } }  },
 311 /* scr: source control register */
 312   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
 313     { 0, { (1<<MACH_BASE) } }  },
 314 /* dcr: destination control register */
 315   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
 316     { 0, { (1<<MACH_BASE) } }  },
 317 /* simm8: 8 bit signed immediate */
 318   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
 319     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 320 /* simm16: 16 bit signed immediate */
 321   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
 322     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 323 /* uimm4: 4 bit trap number */
 324   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
 325     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 326 /* uimm5: 5 bit shift count */
 327   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
 328     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 329 /* uimm16: 16 bit unsigned immediate */
 330   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
 331     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 332 /* imm1: 1 bit immediate */
 333   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
 334     { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
 335 /* accd: accumulator destination register */
 336   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
 337     { 0, { (1<<MACH_M32RX) } }  },
 338 /* accs: accumulator source register */
 339   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
 340     { 0, { (1<<MACH_M32RX) } }  },
 341 /* acc: accumulator reg (d) */
 342   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
 343     { 0, { (1<<MACH_M32RX) } }  },
 344 /* hash: # prefix */
 345   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
 346     { 0, { (1<<MACH_BASE) } }  },
 347 /* hi16: high 16 bit immediate, sign optional */
 348   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
 349     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 350 /* slo16: 16 bit signed immediate, for low() */
 351   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
 352     { 0, { (1<<MACH_BASE) } }  },
 353 /* ulo16: 16 bit unsigned immediate, for low() */
 354   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
 355     { 0, { (1<<MACH_BASE) } }  },
 356 /* uimm24: 24 bit address */
 357   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
 358     { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 359 /* disp8: 8 bit displacement */
 360   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
 361     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 362 /* disp16: 16 bit displacement */
 363   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
 364     { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 365 /* disp24: 24 bit displacement */
 366   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
 367     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 368 /* condbit: condition bit */
 369   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
 370     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 371 /* accum: accumulator */
 372   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
 373     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 374   { 0, 0, 0, 0, 0, {0, {0}} }
 375 };
 376
 377 #undef A
 378
 379 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 380 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 381
 382 /* The instruction table.  */
 383
 384 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 385 {
 386   /* Special null first entry.
 387      A `num' value of zero is thus invalid.
 388      Also, the special `invalid' insn resides here.  */
 389   { 0, 0, 0, 0, {0, {0}} },
 390 /* add $dr,$sr */
 391   {
 392     M32R_INSN_ADD, "add", "add", 16,
 393     { 0, { (1<<MACH_BASE), PIPE_OS } }
 394   },
 395 /* add3 $dr,$sr,$hash$slo16 */
 396   {
 397     M32R_INSN_ADD3, "add3", "add3", 32,
 398     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 399   },
 400 /* and $dr,$sr */
 401   {
 402     M32R_INSN_AND, "and", "and", 16,
 403     { 0, { (1<<MACH_BASE), PIPE_OS } }
 404   },
 405 /* and3 $dr,$sr,$uimm16 */
 406   {
 407     M32R_INSN_AND3, "and3", "and3", 32,
 408     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 409   },
 410 /* or $dr,$sr */
 411   {
 412     M32R_INSN_OR, "or", "or", 16,
 413     { 0, { (1<<MACH_BASE), PIPE_OS } }
 414   },
 415 /* or3 $dr,$sr,$hash$ulo16 */
 416   {
 417     M32R_INSN_OR3, "or3", "or3", 32,
 418     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 419   },
 420 /* xor $dr,$sr */
 421   {
 422     M32R_INSN_XOR, "xor", "xor", 16,
 423     { 0, { (1<<MACH_BASE), PIPE_OS } }
 424   },
 425 /* xor3 $dr,$sr,$uimm16 */
 426   {
 427     M32R_INSN_XOR3, "xor3", "xor3", 32,
 428     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 429   },
 430 /* addi $dr,$simm8 */
 431   {
 432     M32R_INSN_ADDI, "addi", "addi", 16,
 433     { 0, { (1<<MACH_BASE), PIPE_OS } }
 434   },
 435 /* addv $dr,$sr */
 436   {
 437     M32R_INSN_ADDV, "addv", "addv", 16,
 438     { 0, { (1<<MACH_BASE), PIPE_OS } }
 439   },
 440 /* addv3 $dr,$sr,$simm16 */
 441   {
 442     M32R_INSN_ADDV3, "addv3", "addv3", 32,
 443     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 444   },
 445 /* addx $dr,$sr */
 446   {
 447     M32R_INSN_ADDX, "addx", "addx", 16,
 448     { 0, { (1<<MACH_BASE), PIPE_OS } }
 449   },
 450 /* bc.s $disp8 */
 451   {
 452     M32R_INSN_BC8, "bc8", "bc.s", 16,
 453     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
 454   },
 455 /* bc.l $disp24 */
 456   {
 457     M32R_INSN_BC24, "bc24", "bc.l", 32,
 458     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 459   },
 460 /* beq $src1,$src2,$disp16 */
 461   {
 462     M32R_INSN_BEQ, "beq", "beq", 32,
 463     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 464   },
 465 /* beqz $src2,$disp16 */
 466   {
 467     M32R_INSN_BEQZ, "beqz", "beqz", 32,
 468     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 469   },
 470 /* bgez $src2,$disp16 */
 471   {
 472     M32R_INSN_BGEZ, "bgez", "bgez", 32,
 473     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 474   },
 475 /* bgtz $src2,$disp16 */
 476   {
 477     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
 478     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 479   },
 480 /* blez $src2,$disp16 */
 481   {
 482     M32R_INSN_BLEZ, "blez", "blez", 32,
 483     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 484   },
 485 /* bltz $src2,$disp16 */
 486   {
 487     M32R_INSN_BLTZ, "bltz", "bltz", 32,
 488     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 489   },
 490 /* bnez $src2,$disp16 */
 491   {
 492     M32R_INSN_BNEZ, "bnez", "bnez", 32,
 493     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 494   },
 495 /* bl.s $disp8 */
 496   {
 497     M32R_INSN_BL8, "bl8", "bl.s", 16,
 498     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 499   },
 500 /* bl.l $disp24 */
 501   {
 502     M32R_INSN_BL24, "bl24", "bl.l", 32,
 503     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 504   },
 505 /* bcl.s $disp8 */
 506   {
 507     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
 508     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 509   },
 510 /* bcl.l $disp24 */
 511   {
 512     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
 513     { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
 514   },
 515 /* bnc.s $disp8 */
 516   {
 517     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
 518     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
 519   },
 520 /* bnc.l $disp24 */
 521   {
 522     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
 523     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 524   },
 525 /* bne $src1,$src2,$disp16 */
 526   {
 527     M32R_INSN_BNE, "bne", "bne", 32,
 528     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 529   },
 530 /* bra.s $disp8 */
 531   {
 532     M32R_INSN_BRA8, "bra8", "bra.s", 16,
 533     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 534   },
 535 /* bra.l $disp24 */
 536   {
 537     M32R_INSN_BRA24, "bra24", "bra.l", 32,
 538     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 539   },
 540 /* bncl.s $disp8 */
 541   {
 542     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
 543     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 544   },
 545 /* bncl.l $disp24 */
 546   {
 547     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
 548     { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
 549   },
 550 /* cmp $src1,$src2 */
 551   {
 552     M32R_INSN_CMP, "cmp", "cmp", 16,
 553     { 0, { (1<<MACH_BASE), PIPE_OS } }
 554   },
 555 /* cmpi $src2,$simm16 */
 556   {
 557     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
 558     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 559   },
 560 /* cmpu $src1,$src2 */
 561   {
 562     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
 563     { 0, { (1<<MACH_BASE), PIPE_OS } }
 564   },
 565 /* cmpui $src2,$simm16 */
 566   {
 567     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
 568     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 569   },
 570 /* cmpeq $src1,$src2 */
 571   {
 572     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
 573     { 0, { (1<<MACH_M32RX), PIPE_OS } }
 574   },
 575 /* cmpz $src2 */
 576   {
 577     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
 578     { 0, { (1<<MACH_M32RX), PIPE_OS } }
 579   },
 580 /* div $dr,$sr */
 581   {
 582     M32R_INSN_DIV, "div", "div", 32,
 583     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 584   },
 585 /* divu $dr,$sr */
 586   {
 587     M32R_INSN_DIVU, "divu", "divu", 32,
 588     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 589   },
 590 /* rem $dr,$sr */
 591   {
 592     M32R_INSN_REM, "rem", "rem", 32,
 593     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 594   },
 595 /* remu $dr,$sr */
 596   {
 597     M32R_INSN_REMU, "remu", "remu", 32,
 598     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 599   },
 600 /* divh $dr,$sr */
 601   {
 602     M32R_INSN_DIVH, "divh", "divh", 32,
 603     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
 604   },
 605 /* jc $sr */
 606   {
 607     M32R_INSN_JC, "jc", "jc", 16,
 608     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 609   },
 610 /* jnc $sr */
 611   {
 612     M32R_INSN_JNC, "jnc", "jnc", 16,
 613     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 614   },
 615 /* jl $sr */
 616   {
 617     M32R_INSN_JL, "jl", "jl", 16,
 618     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 619   },
 620 /* jmp $sr */
 621   {
 622     M32R_INSN_JMP, "jmp", "jmp", 16,
 623     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 624   },
 625 /* ld $dr,@$sr */
 626   {
 627     M32R_INSN_LD, "ld", "ld", 16,
 628     { 0, { (1<<MACH_BASE), PIPE_O } }
 629   },
 630 /* ld $dr,@($slo16,$sr) */
 631   {
 632     M32R_INSN_LD_D, "ld-d", "ld", 32,
 633     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 634   },
 635 /* ldb $dr,@$sr */
 636   {
 637     M32R_INSN_LDB, "ldb", "ldb", 16,
 638     { 0, { (1<<MACH_BASE), PIPE_O } }
 639   },
 640 /* ldb $dr,@($slo16,$sr) */
 641   {
 642     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
 643     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 644   },
 645 /* ldh $dr,@$sr */
 646   {
 647     M32R_INSN_LDH, "ldh", "ldh", 16,
 648     { 0, { (1<<MACH_BASE), PIPE_O } }
 649   },
 650 /* ldh $dr,@($slo16,$sr) */
 651   {
 652     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
 653     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 654   },
 655 /* ldub $dr,@$sr */
 656   {
 657     M32R_INSN_LDUB, "ldub", "ldub", 16,
 658     { 0, { (1<<MACH_BASE), PIPE_O } }
 659   },
 660 /* ldub $dr,@($slo16,$sr) */
 661   {
 662     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
 663     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 664   },
 665 /* lduh $dr,@$sr */
 666   {
 667     M32R_INSN_LDUH, "lduh", "lduh", 16,
 668     { 0, { (1<<MACH_BASE), PIPE_O } }
 669   },
 670 /* lduh $dr,@($slo16,$sr) */
 671   {
 672     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
 673     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 674   },
 675 /* ld $dr,@$sr+ */
 676   {
 677     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
 678     { 0, { (1<<MACH_BASE), PIPE_O } }
 679   },
 680 /* ld24 $dr,$uimm24 */
 681   {
 682     M32R_INSN_LD24, "ld24", "ld24", 32,
 683     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 684   },
 685 /* ldi8 $dr,$simm8 */
 686   {
 687     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
 688     { 0, { (1<<MACH_BASE), PIPE_OS } }
 689   },
 690 /* ldi16 $dr,$hash$slo16 */
 691   {
 692     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
 693     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 694   },
 695 /* lock $dr,@$sr */
 696   {
 697     M32R_INSN_LOCK, "lock", "lock", 16,
 698     { 0, { (1<<MACH_BASE), PIPE_O } }
 699   },
 700 /* machi $src1,$src2 */
 701   {
 702     M32R_INSN_MACHI, "machi", "machi", 16,
 703     { 0, { (1<<MACH_M32R), PIPE_S } }
 704   },
 705 /* machi $src1,$src2,$acc */
 706   {
 707     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
 708     { 0, { (1<<MACH_M32RX), PIPE_S } }
 709   },
 710 /* maclo $src1,$src2 */
 711   {
 712     M32R_INSN_MACLO, "maclo", "maclo", 16,
 713     { 0, { (1<<MACH_M32R), PIPE_S } }
 714   },
 715 /* maclo $src1,$src2,$acc */
 716   {
 717     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
 718     { 0, { (1<<MACH_M32RX), PIPE_S } }
 719   },
 720 /* macwhi $src1,$src2 */
 721   {
 722     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
 723     { 0, { (1<<MACH_M32R), PIPE_S } }
 724   },
 725 /* macwhi $src1,$src2,$acc */
 726   {
 727     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
 728     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 729   },
 730 /* macwlo $src1,$src2 */
 731   {
 732     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
 733     { 0, { (1<<MACH_M32R), PIPE_S } }
 734   },
 735 /* macwlo $src1,$src2,$acc */
 736   {
 737     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
 738     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 739   },
 740 /* mul $dr,$sr */
 741   {
 742     M32R_INSN_MUL, "mul", "mul", 16,
 743     { 0, { (1<<MACH_BASE), PIPE_S } }
 744   },
 745 /* mulhi $src1,$src2 */
 746   {
 747     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
 748     { 0, { (1<<MACH_M32R), PIPE_S } }
 749   },
 750 /* mulhi $src1,$src2,$acc */
 751   {
 752     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
 753     { 0, { (1<<MACH_M32RX), PIPE_S } }
 754   },
 755 /* mullo $src1,$src2 */
 756   {
 757     M32R_INSN_MULLO, "mullo", "mullo", 16,
 758     { 0, { (1<<MACH_M32R), PIPE_S } }
 759   },
 760 /* mullo $src1,$src2,$acc */
 761   {
 762     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
 763     { 0, { (1<<MACH_M32RX), PIPE_S } }
 764   },
 765 /* mulwhi $src1,$src2 */
 766   {
 767     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
 768     { 0, { (1<<MACH_M32R), PIPE_S } }
 769   },
 770 /* mulwhi $src1,$src2,$acc */
 771   {
 772     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
 773     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 774   },
 775 /* mulwlo $src1,$src2 */
 776   {
 777     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
 778     { 0, { (1<<MACH_M32R), PIPE_S } }
 779   },
 780 /* mulwlo $src1,$src2,$acc */
 781   {
 782     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
 783     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 784   },
 785 /* mv $dr,$sr */
 786   {
 787     M32R_INSN_MV, "mv", "mv", 16,
 788     { 0, { (1<<MACH_BASE), PIPE_OS } }
 789   },
 790 /* mvfachi $dr */
 791   {
 792     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
 793     { 0, { (1<<MACH_M32R), PIPE_S } }
 794   },
 795 /* mvfachi $dr,$accs */
 796   {
 797     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
 798     { 0, { (1<<MACH_M32RX), PIPE_S } }
 799   },
 800 /* mvfaclo $dr */
 801   {
 802     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
 803     { 0, { (1<<MACH_M32R), PIPE_S } }
 804   },
 805 /* mvfaclo $dr,$accs */
 806   {
 807     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
 808     { 0, { (1<<MACH_M32RX), PIPE_S } }
 809   },
 810 /* mvfacmi $dr */
 811   {
 812     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
 813     { 0, { (1<<MACH_M32R), PIPE_S } }
 814   },
 815 /* mvfacmi $dr,$accs */
 816   {
 817     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
 818     { 0, { (1<<MACH_M32RX), PIPE_S } }
 819   },
 820 /* mvfc $dr,$scr */
 821   {
 822     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
 823     { 0, { (1<<MACH_BASE), PIPE_O } }
 824   },
 825 /* mvtachi $src1 */
 826   {
 827     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
 828     { 0, { (1<<MACH_M32R), PIPE_S } }
 829   },
 830 /* mvtachi $src1,$accs */
 831   {
 832     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
 833     { 0, { (1<<MACH_M32RX), PIPE_S } }
 834   },
 835 /* mvtaclo $src1 */
 836   {
 837     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
 838     { 0, { (1<<MACH_M32R), PIPE_S } }
 839   },
 840 /* mvtaclo $src1,$accs */
 841   {
 842     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
 843     { 0, { (1<<MACH_M32RX), PIPE_S } }
 844   },
 845 /* mvtc $sr,$dcr */
 846   {
 847     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
 848     { 0, { (1<<MACH_BASE), PIPE_O } }
 849   },
 850 /* neg $dr,$sr */
 851   {
 852     M32R_INSN_NEG, "neg", "neg", 16,
 853     { 0, { (1<<MACH_BASE), PIPE_OS } }
 854   },
 855 /* nop */
 856   {
 857     M32R_INSN_NOP, "nop", "nop", 16,
 858     { 0, { (1<<MACH_BASE), PIPE_OS } }
 859   },
 860 /* not $dr,$sr */
 861   {
 862     M32R_INSN_NOT, "not", "not", 16,
 863     { 0, { (1<<MACH_BASE), PIPE_OS } }
 864   },
 865 /* rac */
 866   {
 867     M32R_INSN_RAC, "rac", "rac", 16,
 868     { 0, { (1<<MACH_M32R), PIPE_S } }
 869   },
 870 /* rac $accd,$accs,$imm1 */
 871   {
 872     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
 873     { 0, { (1<<MACH_M32RX), PIPE_S } }
 874   },
 875 /* rach */
 876   {
 877     M32R_INSN_RACH, "rach", "rach", 16,
 878     { 0, { (1<<MACH_M32R), PIPE_S } }
 879   },
 880 /* rach $accd,$accs,$imm1 */
 881   {
 882     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
 883     { 0, { (1<<MACH_M32RX), PIPE_S } }
 884   },
 885 /* rte */
 886   {
 887     M32R_INSN_RTE, "rte", "rte", 16,
 888     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 889   },
 890 /* seth $dr,$hash$hi16 */
 891   {
 892     M32R_INSN_SETH, "seth", "seth", 32,
 893     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 894   },
 895 /* sll $dr,$sr */
 896   {
 897     M32R_INSN_SLL, "sll", "sll", 16,
 898     { 0, { (1<<MACH_BASE), PIPE_O } }
 899   },
 900 /* sll3 $dr,$sr,$simm16 */
 901   {
 902     M32R_INSN_SLL3, "sll3", "sll3", 32,
 903     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 904   },
 905 /* slli $dr,$uimm5 */
 906   {
 907     M32R_INSN_SLLI, "slli", "slli", 16,
 908     { 0, { (1<<MACH_BASE), PIPE_O } }
 909   },
 910 /* sra $dr,$sr */
 911   {
 912     M32R_INSN_SRA, "sra", "sra", 16,
 913     { 0, { (1<<MACH_BASE), PIPE_O } }
 914   },
 915 /* sra3 $dr,$sr,$simm16 */
 916   {
 917     M32R_INSN_SRA3, "sra3", "sra3", 32,
 918     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 919   },
 920 /* srai $dr,$uimm5 */
 921   {
 922     M32R_INSN_SRAI, "srai", "srai", 16,
 923     { 0, { (1<<MACH_BASE), PIPE_O } }
 924   },
 925 /* srl $dr,$sr */
 926   {
 927     M32R_INSN_SRL, "srl", "srl", 16,
 928     { 0, { (1<<MACH_BASE), PIPE_O } }
 929   },
 930 /* srl3 $dr,$sr,$simm16 */
 931   {
 932     M32R_INSN_SRL3, "srl3", "srl3", 32,
 933     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 934   },
 935 /* srli $dr,$uimm5 */
 936   {
 937     M32R_INSN_SRLI, "srli", "srli", 16,
 938     { 0, { (1<<MACH_BASE), PIPE_O } }
 939   },
 940 /* st $src1,@$src2 */
 941   {
 942     M32R_INSN_ST, "st", "st", 16,
 943     { 0, { (1<<MACH_BASE), PIPE_O } }
 944   },
 945 /* st $src1,@($slo16,$src2) */
 946   {
 947     M32R_INSN_ST_D, "st-d", "st", 32,
 948     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 949   },
 950 /* stb $src1,@$src2 */
 951   {
 952     M32R_INSN_STB, "stb", "stb", 16,
 953     { 0, { (1<<MACH_BASE), PIPE_O } }
 954   },
 955 /* stb $src1,@($slo16,$src2) */
 956   {
 957     M32R_INSN_STB_D, "stb-d", "stb", 32,
 958     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 959   },
 960 /* sth $src1,@$src2 */
 961   {
 962     M32R_INSN_STH, "sth", "sth", 16,
 963     { 0, { (1<<MACH_BASE), PIPE_O } }
 964   },
 965 /* sth $src1,@($slo16,$src2) */
 966   {
 967     M32R_INSN_STH_D, "sth-d", "sth", 32,
 968     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 969   },
 970 /* st $src1,@+$src2 */
 971   {
 972     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
 973     { 0, { (1<<MACH_BASE), PIPE_O } }
 974   },
 975 /* st $src1,@-$src2 */
 976   {
 977     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
 978     { 0, { (1<<MACH_BASE), PIPE_O } }
 979   },
 980 /* sub $dr,$sr */
 981   {
 982     M32R_INSN_SUB, "sub", "sub", 16,
 983     { 0, { (1<<MACH_BASE), PIPE_OS } }
 984   },
 985 /* subv $dr,$sr */
 986   {
 987     M32R_INSN_SUBV, "subv", "subv", 16,
 988     { 0, { (1<<MACH_BASE), PIPE_OS } }
 989   },
 990 /* subx $dr,$sr */
 991   {
 992     M32R_INSN_SUBX, "subx", "subx", 16,
 993     { 0, { (1<<MACH_BASE), PIPE_OS } }
 994   },
 995 /* trap $uimm4 */
 996   {
 997     M32R_INSN_TRAP, "trap", "trap", 16,
 998     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 999   },
1000 /* unlock $src1,@$src2 */
1001   {
1002     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1003     { 0, { (1<<MACH_BASE), PIPE_O } }
1004   },
1005 /* satb $dr,$sr */
1006   {
1007     M32R_INSN_SATB, "satb", "satb", 32,
1008     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1009   },
1010 /* sath $dr,$sr */
1011   {
1012     M32R_INSN_SATH, "sath", "sath", 32,
1013     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1014   },
1015 /* sat $dr,$sr */
1016   {
1017     M32R_INSN_SAT, "sat", "sat", 32,
1018     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
1019   },
1020 /* pcmpbz $src2 */
1021   {
1022     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1023     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
1024   },
1025 /* sadd */
1026   {
1027     M32R_INSN_SADD, "sadd", "sadd", 16,
1028     { 0, { (1<<MACH_M32RX), PIPE_S } }
1029   },
1030 /* macwu1 $src1,$src2 */
1031   {
1032     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1033     { 0, { (1<<MACH_M32RX), PIPE_S } }
1034   },
1035 /* msblo $src1,$src2 */
1036   {
1037     M32R_INSN_MSBLO, "msblo", "msblo", 16,
1038     { 0, { (1<<MACH_M32RX), PIPE_S } }
1039   },
1040 /* mulwu1 $src1,$src2 */
1041   {
1042     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1043     { 0, { (1<<MACH_M32RX), PIPE_S } }
1044   },
1045 /* maclh1 $src1,$src2 */
1046   {
1047     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1048     { 0, { (1<<MACH_M32RX), PIPE_S } }
1049   },
1050 /* sc */
1051   {
1052     M32R_INSN_SC, "sc", "sc", 16,
1053     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1054   },
1055 /* snc */
1056   {
1057     M32R_INSN_SNC, "snc", "snc", 16,
1058     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1059   },
1060 };
1061
1062 #undef A
1063 #undef MNEM
1064 #undef OP
1065
1066 /* Initialize anything needed to be done once, before any cpu_open call.  */
1067
1068 static void
1069 init_tables ()
1070 {
1071 }
1072
1073 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
1074
1075 static const CGEN_MACH *
1076 lookup_mach_via_bfd_name (table, name)
1077      const CGEN_MACH *table;
1078      const char *name;
1079 {
1080   while (table->name)
1081     {
1082       if (strcmp (name, table->bfd_name) == 0)
1083         return table;
1084       ++table;
1085     }
1086   abort ();
1087 }
1088
1089 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1090
1091 static void
1092 build_hw_table (cd)
1093      CGEN_CPU_TABLE *cd;
1094 {
1095   int i;
1096   int machs = cd->machs;
1097   const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1098   /* MAX_HW is only an upper bound on the number of selected entries.
1099      However each entry is indexed by it's enum so there can be holes in
1100      the table.  */
1101   const CGEN_HW_ENTRY **selected =
1102     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1103
1104   cd->hw_table.init_entries = init;
1105   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1106   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1107   /* ??? For now we just use machs to determine which ones we want.  */
1108   for (i = 0; init[i].name != NULL; ++i)
1109     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1110         & machs)
1111       selected[init[i].type] = &init[i];
1112   cd->hw_table.entries = selected;
1113   cd->hw_table.num_entries = MAX_HW;
1114 }
1115
1116 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1117
1118 static void
1119 build_ifield_table (cd)
1120      CGEN_CPU_TABLE *cd;
1121 {
1122   cd->ifld_table = & m32r_cgen_ifld_table[0];
1123 }
1124
1125 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1126
1127 static void
1128 build_operand_table (cd)
1129      CGEN_CPU_TABLE *cd;
1130 {
1131   int i;
1132   int machs = cd->machs;
1133   const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1134   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1135      However each entry is indexed by it's enum so there can be holes in
1136      the table.  */
1137   const CGEN_OPERAND **selected =
1138     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1139
1140   cd->operand_table.init_entries = init;
1141   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1142   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1143   /* ??? For now we just use mach to determine which ones we want.  */
1144   for (i = 0; init[i].name != NULL; ++i)
1145     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1146         & machs)
1147       selected[init[i].type] = &init[i];
1148   cd->operand_table.entries = selected;
1149   cd->operand_table.num_entries = MAX_OPERANDS;
1150 }
1151
1152 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1153    ??? This could leave out insns not supported by the specified mach/isa,
1154    but that would cause errors like "foo only supported by bar" to become
1155    "unknown insn", so for now we include all insns and require the app to
1156    do the checking later.
1157    ??? On the other hand, parsing of such insns may require their hardware or
1158    operand elements to be in the table [which they mightn't be].  */
1159
1160 static void
1161 build_insn_table (cd)
1162      CGEN_CPU_TABLE *cd;
1163 {
1164   int i;
1165   const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1166   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1167
1168   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1169   for (i = 0; i < MAX_INSNS; ++i)
1170     insns[i].base = &ib[i];
1171   cd->insn_table.init_entries = insns;
1172   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1173   cd->insn_table.num_init_entries = MAX_INSNS;
1174 }
1175
1176 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
1177
1178 static void
1179 m32r_cgen_rebuild_tables (cd)
1180      CGEN_CPU_TABLE *cd;
1181 {
1182   int i,n_isas;
1183   unsigned int isas = cd->isas;
1184 #if 0
1185   unsigned int machs = cd->machs;
1186 #endif
1187
1188   cd->int_insn_p = CGEN_INT_INSN_P;
1189
1190   /* Data derived from the isa spec.  */
1191 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1192   cd->default_insn_bitsize = UNSET;
1193   cd->base_insn_bitsize = UNSET;
1194   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1195   cd->max_insn_bitsize = 0;
1196   for (i = 0; i < MAX_ISAS; ++i)
1197     if (((1 << i) & isas) != 0)
1198       {
1199         const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1200
1201         /* Default insn sizes of all selected isas must be equal or we set
1202            the result to 0, meaning "unknown".  */
1203         if (cd->default_insn_bitsize == UNSET)
1204           cd->default_insn_bitsize = isa->default_insn_bitsize;
1205         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1206           ; /* this is ok */
1207         else
1208           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1209
1210         /* Base insn sizes of all selected isas must be equal or we set
1211            the result to 0, meaning "unknown".  */
1212         if (cd->base_insn_bitsize == UNSET)
1213           cd->base_insn_bitsize = isa->base_insn_bitsize;
1214         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1215           ; /* this is ok */
1216         else
1217           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1218
1219         /* Set min,max insn sizes.  */
1220         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1221           cd->min_insn_bitsize = isa->min_insn_bitsize;
1222         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1223           cd->max_insn_bitsize = isa->max_insn_bitsize;
1224
1225         ++n_isas;
1226       }
1227
1228 #if 0 /* Does nothing?? */
1229   /* Data derived from the mach spec.  */
1230   for (i = 0; i < MAX_MACHS; ++i)
1231     if (((1 << i) & machs) != 0)
1232       {
1233         const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1234
1235         ++n_machs;
1236       }
1237 #endif
1238
1239   /* Determine which hw elements are used by MACH.  */
1240   build_hw_table (cd);
1241
1242   /* Build the ifield table.  */
1243   build_ifield_table (cd);
1244
1245   /* Determine which operands are used by MACH/ISA.  */
1246   build_operand_table (cd);
1247
1248   /* Build the instruction table.  */
1249   build_insn_table (cd);
1250 }
1251
1252 /* Initialize a cpu table and return a descriptor.
1253    It's much like opening a file, and must be the first function called.
1254    The arguments are a set of (type/value) pairs, terminated with
1255    CGEN_CPU_OPEN_END.
1256
1257    Currently supported values:
1258    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1259    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1260    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1261    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1262    CGEN_CPU_OPEN_END:     terminates arguments
1263
1264    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1265    precluded.
1266
1267    ??? We only support ISO C stdargs here, not K&R.
1268    Laziness, plus experiment to see if anything requires K&R - eventually
1269    K&R will no longer be supported - e.g. GDB is currently trying this.  */
1270
1271 CGEN_CPU_DESC
1272 m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1273 {
1274   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1275   static int init_p;
1276   unsigned int isas = 0;  /* 0 = "unspecified" */
1277   unsigned int machs = 0; /* 0 = "unspecified" */
1278   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1279   va_list ap;
1280
1281   if (! init_p)
1282     {
1283       init_tables ();
1284       init_p = 1;
1285     }
1286
1287   memset (cd, 0, sizeof (*cd));
1288
1289   va_start (ap, arg_type);
1290   while (arg_type != CGEN_CPU_OPEN_END)
1291     {
1292       switch (arg_type)
1293         {
1294         case CGEN_CPU_OPEN_ISAS :
1295           isas = va_arg (ap, unsigned int);
1296           break;
1297         case CGEN_CPU_OPEN_MACHS :
1298           machs = va_arg (ap, unsigned int);
1299           break;
1300         case CGEN_CPU_OPEN_BFDMACH :
1301           {
1302             const char *name = va_arg (ap, const char *);
1303             const CGEN_MACH *mach =
1304               lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1305
1306             machs |= mach->num << 1;
1307             break;
1308           }
1309         case CGEN_CPU_OPEN_ENDIAN :
1310           endian = va_arg (ap, enum cgen_endian);
1311           break;
1312         default :
1313           fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1314                    arg_type);
1315           abort (); /* ??? return NULL? */
1316         }
1317       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1318     }
1319   va_end (ap);
1320
1321   /* mach unspecified means "all" */
1322   if (machs == 0)
1323     machs = (1 << MAX_MACHS) - 1;
1324   /* base mach is always selected */
1325   machs |= 1;
1326   /* isa unspecified means "all" */
1327   if (isas == 0)
1328     isas = (1 << MAX_ISAS) - 1;
1329   if (endian == CGEN_ENDIAN_UNKNOWN)
1330     {
1331       /* ??? If target has only one, could have a default.  */
1332       fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1333       abort ();
1334     }
1335
1336   cd->isas = isas;
1337   cd->machs = machs;
1338   cd->endian = endian;
1339   /* FIXME: for the sparc case we can determine insn-endianness statically.
1340      The worry here is where both data and insn endian can be independently
1341      chosen, in which case this function will need another argument.
1342      Actually, will want to allow for more arguments in the future anyway.  */
1343   cd->insn_endian = endian;
1344
1345   /* Table (re)builder.  */
1346   cd->rebuild_tables = m32r_cgen_rebuild_tables;
1347   m32r_cgen_rebuild_tables (cd);
1348
1349   /* Default to not allowing signed overflow.  */
1350   cd->signed_overflow_ok_p = 0;
1351
1352   return (CGEN_CPU_DESC) cd;
1353 }
1354
1355 /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1356    MACH_NAME is the bfd name of the mach.  */
1357
1358 CGEN_CPU_DESC
1359 m32r_cgen_cpu_open_1 (mach_name, endian)
1360      const char *mach_name;
1361      enum cgen_endian endian;
1362 {
1363   return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1364                                CGEN_CPU_OPEN_ENDIAN, endian,
1365                                CGEN_CPU_OPEN_END);
1366 }
1367
1368 /* Close a cpu table.
1369    ??? This can live in a machine independent file, but there's currently
1370    no place to put this file (there's no libcgen).  libopcodes is the wrong
1371    place as some simulator ports use this but they don't use libopcodes.  */
1372
1373 void
1374 m32r_cgen_cpu_close (cd)
1375      CGEN_CPU_DESC cd;
1376 {
1377   if (cd->insn_table.init_entries)
1378     free ((CGEN_INSN *) cd->insn_table.init_entries);
1379   if (cd->hw_table.entries)
1380     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1381   free (cd);
1382 }
1383