1999-09-12 Donn Terry <donn@interix.com>
[binutils.git] / opcodes / fr30-desc.c
blob810f04b9dcc796d0f246e92db1e6c23353cba7b0
1 /* CPU data for fr30.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #include "sysdep.h"
26 #include <ctype.h>
27 #include <stdio.h>
28 #include <stdarg.h>
29 #include "ansidecl.h"
30 #include "bfd.h"
31 #include "symcat.h"
32 #include "fr30-desc.h"
33 #include "fr30-opc.h"
34 #include "opintl.h"
36 /* Attributes. */
38 static const CGEN_ATTR_ENTRY bool_attr[] =
40 { "#f", 0 },
41 { "#t", 1 },
42 { 0, 0 }
45 static const CGEN_ATTR_ENTRY MACH_attr[] =
47 { "base", MACH_BASE },
48 { "fr30", MACH_FR30 },
49 { "max", MACH_MAX },
50 { 0, 0 }
53 static const CGEN_ATTR_ENTRY ISA_attr[] =
55 { "fr30", ISA_FR30 },
56 { "max", ISA_MAX },
57 { 0, 0 }
60 const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
62 { "MACH", & MACH_attr[0] },
63 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
64 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
65 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
66 { "RESERVED", &bool_attr[0], &bool_attr[0] },
67 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
68 { "SIGNED", &bool_attr[0], &bool_attr[0] },
69 { 0, 0, 0 }
72 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
74 { "MACH", & MACH_attr[0] },
75 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
76 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
77 { "PC", &bool_attr[0], &bool_attr[0] },
78 { "PROFILE", &bool_attr[0], &bool_attr[0] },
79 { 0, 0, 0 }
82 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
84 { "MACH", & MACH_attr[0] },
85 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
86 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
87 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
88 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
89 { "SIGNED", &bool_attr[0], &bool_attr[0] },
90 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
91 { "RELAX", &bool_attr[0], &bool_attr[0] },
92 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
93 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
94 { 0, 0, 0 }
97 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
99 { "MACH", & MACH_attr[0] },
100 { "ALIAS", &bool_attr[0], &bool_attr[0] },
101 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
102 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
103 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
104 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
105 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
106 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
107 { "RELAX", &bool_attr[0], &bool_attr[0] },
108 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
109 { "PBB", &bool_attr[0], &bool_attr[0] },
110 { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
111 { 0, 0, 0 }
114 /* Instruction set variants. */
116 static const CGEN_ISA fr30_cgen_isa_table[] = {
117 { "fr30", 16, 16, 16, 48, },
118 { 0 }
121 /* Machine variants. */
123 static const CGEN_MACH fr30_cgen_mach_table[] = {
124 { "fr30", "fr30", MACH_FR30 },
125 { 0 }
128 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
130 { "r0", 0 },
131 { "r1", 1 },
132 { "r2", 2 },
133 { "r3", 3 },
134 { "r4", 4 },
135 { "r5", 5 },
136 { "r6", 6 },
137 { "r7", 7 },
138 { "r8", 8 },
139 { "r9", 9 },
140 { "r10", 10 },
141 { "r11", 11 },
142 { "r12", 12 },
143 { "r13", 13 },
144 { "r14", 14 },
145 { "r15", 15 },
146 { "ac", 13 },
147 { "fp", 14 },
148 { "sp", 15 }
151 CGEN_KEYWORD fr30_cgen_opval_gr_names =
153 & fr30_cgen_opval_gr_names_entries[0],
157 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
159 { "cr0", 0 },
160 { "cr1", 1 },
161 { "cr2", 2 },
162 { "cr3", 3 },
163 { "cr4", 4 },
164 { "cr5", 5 },
165 { "cr6", 6 },
166 { "cr7", 7 },
167 { "cr8", 8 },
168 { "cr9", 9 },
169 { "cr10", 10 },
170 { "cr11", 11 },
171 { "cr12", 12 },
172 { "cr13", 13 },
173 { "cr14", 14 },
174 { "cr15", 15 }
177 CGEN_KEYWORD fr30_cgen_opval_cr_names =
179 & fr30_cgen_opval_cr_names_entries[0],
183 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
185 { "tbr", 0 },
186 { "rp", 1 },
187 { "ssp", 2 },
188 { "usp", 3 },
189 { "mdh", 4 },
190 { "mdl", 5 }
193 CGEN_KEYWORD fr30_cgen_opval_dr_names =
195 & fr30_cgen_opval_dr_names_entries[0],
199 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
201 { "ps", 0 }
204 CGEN_KEYWORD fr30_cgen_opval_h_ps =
206 & fr30_cgen_opval_h_ps_entries[0],
210 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
212 { "r13", 0 }
215 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
217 & fr30_cgen_opval_h_r13_entries[0],
221 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
223 { "r14", 0 }
226 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
228 & fr30_cgen_opval_h_r14_entries[0],
232 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
234 { "r15", 0 }
237 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
239 & fr30_cgen_opval_h_r15_entries[0],
245 /* The hardware table. */
247 #define A(a) (1 << CONCAT2 (CGEN_HW_,a))
249 const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
251 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
252 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
253 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
254 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
255 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
256 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
257 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
258 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
259 { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
260 { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
261 { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
262 { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
263 { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
264 { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
265 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
266 { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
267 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
268 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
269 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
270 { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
271 { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
272 { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
273 { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
274 { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
275 { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
276 { 0 }
279 #undef A
281 /* The instruction field table. */
283 #define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))
285 const CGEN_IFLD fr30_cgen_ifld_table[] =
287 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
288 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } } },
289 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } },
290 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
291 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
292 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } } },
293 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } },
294 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } } },
295 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
296 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
297 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
298 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
299 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
300 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
301 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
302 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
303 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
304 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
305 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
306 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
307 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
308 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
309 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
310 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } } },
311 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
312 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
313 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
314 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
315 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
316 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
317 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
318 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
319 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
320 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
321 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
322 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
323 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
324 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
325 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
326 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
327 { 0 }
330 #undef A
332 /* The operand table. */
334 #define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
335 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
337 const CGEN_OPERAND fr30_cgen_operand_table[] =
339 /* pc: program counter */
340 { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
341 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
342 /* Ri: destination register */
343 { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
344 { 0, { (1<<MACH_BASE) } } },
345 /* Rj: source register */
346 { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
347 { 0, { (1<<MACH_BASE) } } },
348 /* Ric: target register coproc insn */
349 { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
350 { 0, { (1<<MACH_BASE) } } },
351 /* Rjc: source register coproc insn */
352 { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
353 { 0, { (1<<MACH_BASE) } } },
354 /* CRi: coprocessor register */
355 { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
356 { 0, { (1<<MACH_BASE) } } },
357 /* CRj: coprocessor register */
358 { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
359 { 0, { (1<<MACH_BASE) } } },
360 /* Rs1: dedicated register */
361 { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
362 { 0, { (1<<MACH_BASE) } } },
363 /* Rs2: dedicated register */
364 { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
365 { 0, { (1<<MACH_BASE) } } },
366 /* R13: General Register 13 */
367 { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
368 { 0, { (1<<MACH_BASE) } } },
369 /* R14: General Register 14 */
370 { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
371 { 0, { (1<<MACH_BASE) } } },
372 /* R15: General Register 15 */
373 { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
374 { 0, { (1<<MACH_BASE) } } },
375 /* ps: Program Status register */
376 { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
377 { 0, { (1<<MACH_BASE) } } },
378 /* u4: 4 bit unsigned immediate */
379 { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
380 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
381 /* u4c: 4 bit unsigned immediate */
382 { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
383 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
384 /* u8: 8 bit unsigned immediate */
385 { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
386 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
387 /* i8: 8 bit unsigned immediate */
388 { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
389 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
390 /* udisp6: 6 bit unsigned immediate */
391 { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
392 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
393 /* disp8: 8 bit signed immediate */
394 { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
395 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
396 /* disp9: 9 bit signed immediate */
397 { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
398 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
399 /* disp10: 10 bit signed immediate */
400 { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
401 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
402 /* s10: 10 bit signed immediate */
403 { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
404 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
405 /* u10: 10 bit unsigned immediate */
406 { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
407 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
408 /* i32: 32 bit immediate */
409 { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
410 { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } },
411 /* m4: 4 bit negative immediate */
412 { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
413 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
414 /* i20: 20 bit immediate */
415 { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
416 { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } },
417 /* dir8: 8 bit direct address */
418 { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
419 { 0, { (1<<MACH_BASE) } } },
420 /* dir9: 9 bit direct address */
421 { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
422 { 0, { (1<<MACH_BASE) } } },
423 /* dir10: 10 bit direct address */
424 { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
425 { 0, { (1<<MACH_BASE) } } },
426 /* label9: 9 bit pc relative address */
427 { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
428 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
429 /* label12: 12 bit pc relative address */
430 { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
431 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
432 /* reglist_low_ld: 8 bit low register mask for ldm */
433 { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
434 { 0, { (1<<MACH_BASE) } } },
435 /* reglist_hi_ld: 8 bit high register mask for ldm */
436 { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
437 { 0, { (1<<MACH_BASE) } } },
438 /* reglist_low_st: 8 bit low register mask for stm */
439 { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
440 { 0, { (1<<MACH_BASE) } } },
441 /* reglist_hi_st: 8 bit high register mask for stm */
442 { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
443 { 0, { (1<<MACH_BASE) } } },
444 /* cc: condition codes */
445 { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
446 { 0, { (1<<MACH_BASE) } } },
447 /* ccc: coprocessor calc */
448 { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
449 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
450 /* nbit: negative bit */
451 { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
452 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
453 /* vbit: overflow bit */
454 { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
455 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
456 /* zbit: zero bit */
457 { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
458 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
459 /* cbit: carry bit */
460 { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
461 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
462 /* ibit: interrupt bit */
463 { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
464 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
465 /* sbit: stack bit */
466 { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
467 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
468 /* tbit: trace trap bit */
469 { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
470 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
471 /* d0bit: division 0 bit */
472 { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
473 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
474 /* d1bit: division 1 bit */
475 { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
476 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
477 /* ccr: condition code bits */
478 { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
479 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
480 /* scr: system condition bits */
481 { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
482 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
483 /* ilm: interrupt level mask */
484 { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
485 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
486 { 0 }
489 #undef A
491 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
492 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
494 /* The instruction table. */
496 static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
498 /* Special null first entry.
499 A `num' value of zero is thus invalid.
500 Also, the special `invalid' insn resides here. */
501 { 0, 0, 0 },
502 /* add $Rj,$Ri */
504 FR30_INSN_ADD, "add", "add", 16,
505 { 0, { (1<<MACH_BASE) } }
507 /* add $u4,$Ri */
509 FR30_INSN_ADDI, "addi", "add", 16,
510 { 0, { (1<<MACH_BASE) } }
512 /* add2 $m4,$Ri */
514 FR30_INSN_ADD2, "add2", "add2", 16,
515 { 0, { (1<<MACH_BASE) } }
517 /* addc $Rj,$Ri */
519 FR30_INSN_ADDC, "addc", "addc", 16,
520 { 0, { (1<<MACH_BASE) } }
522 /* addn $Rj,$Ri */
524 FR30_INSN_ADDN, "addn", "addn", 16,
525 { 0, { (1<<MACH_BASE) } }
527 /* addn $u4,$Ri */
529 FR30_INSN_ADDNI, "addni", "addn", 16,
530 { 0, { (1<<MACH_BASE) } }
532 /* addn2 $m4,$Ri */
534 FR30_INSN_ADDN2, "addn2", "addn2", 16,
535 { 0, { (1<<MACH_BASE) } }
537 /* sub $Rj,$Ri */
539 FR30_INSN_SUB, "sub", "sub", 16,
540 { 0, { (1<<MACH_BASE) } }
542 /* subc $Rj,$Ri */
544 FR30_INSN_SUBC, "subc", "subc", 16,
545 { 0, { (1<<MACH_BASE) } }
547 /* subn $Rj,$Ri */
549 FR30_INSN_SUBN, "subn", "subn", 16,
550 { 0, { (1<<MACH_BASE) } }
552 /* cmp $Rj,$Ri */
554 FR30_INSN_CMP, "cmp", "cmp", 16,
555 { 0, { (1<<MACH_BASE) } }
557 /* cmp $u4,$Ri */
559 FR30_INSN_CMPI, "cmpi", "cmp", 16,
560 { 0, { (1<<MACH_BASE) } }
562 /* cmp2 $m4,$Ri */
564 FR30_INSN_CMP2, "cmp2", "cmp2", 16,
565 { 0, { (1<<MACH_BASE) } }
567 /* and $Rj,$Ri */
569 FR30_INSN_AND, "and", "and", 16,
570 { 0, { (1<<MACH_BASE) } }
572 /* or $Rj,$Ri */
574 FR30_INSN_OR, "or", "or", 16,
575 { 0, { (1<<MACH_BASE) } }
577 /* eor $Rj,$Ri */
579 FR30_INSN_EOR, "eor", "eor", 16,
580 { 0, { (1<<MACH_BASE) } }
582 /* and $Rj,@$Ri */
584 FR30_INSN_ANDM, "andm", "and", 16,
585 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
587 /* andh $Rj,@$Ri */
589 FR30_INSN_ANDH, "andh", "andh", 16,
590 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
592 /* andb $Rj,@$Ri */
594 FR30_INSN_ANDB, "andb", "andb", 16,
595 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
597 /* or $Rj,@$Ri */
599 FR30_INSN_ORM, "orm", "or", 16,
600 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
602 /* orh $Rj,@$Ri */
604 FR30_INSN_ORH, "orh", "orh", 16,
605 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
607 /* orb $Rj,@$Ri */
609 FR30_INSN_ORB, "orb", "orb", 16,
610 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
612 /* eor $Rj,@$Ri */
614 FR30_INSN_EORM, "eorm", "eor", 16,
615 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
617 /* eorh $Rj,@$Ri */
619 FR30_INSN_EORH, "eorh", "eorh", 16,
620 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
622 /* eorb $Rj,@$Ri */
624 FR30_INSN_EORB, "eorb", "eorb", 16,
625 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
627 /* bandl $u4,@$Ri */
629 FR30_INSN_BANDL, "bandl", "bandl", 16,
630 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
632 /* borl $u4,@$Ri */
634 FR30_INSN_BORL, "borl", "borl", 16,
635 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
637 /* beorl $u4,@$Ri */
639 FR30_INSN_BEORL, "beorl", "beorl", 16,
640 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
642 /* bandh $u4,@$Ri */
644 FR30_INSN_BANDH, "bandh", "bandh", 16,
645 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
647 /* borh $u4,@$Ri */
649 FR30_INSN_BORH, "borh", "borh", 16,
650 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
652 /* beorh $u4,@$Ri */
654 FR30_INSN_BEORH, "beorh", "beorh", 16,
655 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
657 /* btstl $u4,@$Ri */
659 FR30_INSN_BTSTL, "btstl", "btstl", 16,
660 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
662 /* btsth $u4,@$Ri */
664 FR30_INSN_BTSTH, "btsth", "btsth", 16,
665 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
667 /* mul $Rj,$Ri */
669 FR30_INSN_MUL, "mul", "mul", 16,
670 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
672 /* mulu $Rj,$Ri */
674 FR30_INSN_MULU, "mulu", "mulu", 16,
675 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
677 /* mulh $Rj,$Ri */
679 FR30_INSN_MULH, "mulh", "mulh", 16,
680 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
682 /* muluh $Rj,$Ri */
684 FR30_INSN_MULUH, "muluh", "muluh", 16,
685 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
687 /* div0s $Ri */
689 FR30_INSN_DIV0S, "div0s", "div0s", 16,
690 { 0, { (1<<MACH_BASE) } }
692 /* div0u $Ri */
694 FR30_INSN_DIV0U, "div0u", "div0u", 16,
695 { 0, { (1<<MACH_BASE) } }
697 /* div1 $Ri */
699 FR30_INSN_DIV1, "div1", "div1", 16,
700 { 0, { (1<<MACH_BASE) } }
702 /* div2 $Ri */
704 FR30_INSN_DIV2, "div2", "div2", 16,
705 { 0, { (1<<MACH_BASE) } }
707 /* div3 */
709 FR30_INSN_DIV3, "div3", "div3", 16,
710 { 0, { (1<<MACH_BASE) } }
712 /* div4s */
714 FR30_INSN_DIV4S, "div4s", "div4s", 16,
715 { 0, { (1<<MACH_BASE) } }
717 /* lsl $Rj,$Ri */
719 FR30_INSN_LSL, "lsl", "lsl", 16,
720 { 0, { (1<<MACH_BASE) } }
722 /* lsl $u4,$Ri */
724 FR30_INSN_LSLI, "lsli", "lsl", 16,
725 { 0, { (1<<MACH_BASE) } }
727 /* lsl2 $u4,$Ri */
729 FR30_INSN_LSL2, "lsl2", "lsl2", 16,
730 { 0, { (1<<MACH_BASE) } }
732 /* lsr $Rj,$Ri */
734 FR30_INSN_LSR, "lsr", "lsr", 16,
735 { 0, { (1<<MACH_BASE) } }
737 /* lsr $u4,$Ri */
739 FR30_INSN_LSRI, "lsri", "lsr", 16,
740 { 0, { (1<<MACH_BASE) } }
742 /* lsr2 $u4,$Ri */
744 FR30_INSN_LSR2, "lsr2", "lsr2", 16,
745 { 0, { (1<<MACH_BASE) } }
747 /* asr $Rj,$Ri */
749 FR30_INSN_ASR, "asr", "asr", 16,
750 { 0, { (1<<MACH_BASE) } }
752 /* asr $u4,$Ri */
754 FR30_INSN_ASRI, "asri", "asr", 16,
755 { 0, { (1<<MACH_BASE) } }
757 /* asr2 $u4,$Ri */
759 FR30_INSN_ASR2, "asr2", "asr2", 16,
760 { 0, { (1<<MACH_BASE) } }
762 /* ldi:8 $i8,$Ri */
764 FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
765 { 0, { (1<<MACH_BASE) } }
767 /* ldi:20 $i20,$Ri */
769 FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
770 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
772 /* ldi:32 $i32,$Ri */
774 FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
775 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
777 /* ld @$Rj,$Ri */
779 FR30_INSN_LD, "ld", "ld", 16,
780 { 0, { (1<<MACH_BASE) } }
782 /* lduh @$Rj,$Ri */
784 FR30_INSN_LDUH, "lduh", "lduh", 16,
785 { 0, { (1<<MACH_BASE) } }
787 /* ldub @$Rj,$Ri */
789 FR30_INSN_LDUB, "ldub", "ldub", 16,
790 { 0, { (1<<MACH_BASE) } }
792 /* ld @($R13,$Rj),$Ri */
794 FR30_INSN_LDR13, "ldr13", "ld", 16,
795 { 0, { (1<<MACH_BASE) } }
797 /* lduh @($R13,$Rj),$Ri */
799 FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
800 { 0, { (1<<MACH_BASE) } }
802 /* ldub @($R13,$Rj),$Ri */
804 FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
805 { 0, { (1<<MACH_BASE) } }
807 /* ld @($R14,$disp10),$Ri */
809 FR30_INSN_LDR14, "ldr14", "ld", 16,
810 { 0, { (1<<MACH_BASE) } }
812 /* lduh @($R14,$disp9),$Ri */
814 FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
815 { 0, { (1<<MACH_BASE) } }
817 /* ldub @($R14,$disp8),$Ri */
819 FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
820 { 0, { (1<<MACH_BASE) } }
822 /* ld @($R15,$udisp6),$Ri */
824 FR30_INSN_LDR15, "ldr15", "ld", 16,
825 { 0, { (1<<MACH_BASE) } }
827 /* ld @$R15+,$Ri */
829 FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
830 { 0, { (1<<MACH_BASE) } }
832 /* ld @$R15+,$Rs2 */
834 FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
835 { 0, { (1<<MACH_BASE) } }
837 /* ld @$R15+,$ps */
839 FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
840 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
842 /* st $Ri,@$Rj */
844 FR30_INSN_ST, "st", "st", 16,
845 { 0, { (1<<MACH_BASE) } }
847 /* sth $Ri,@$Rj */
849 FR30_INSN_STH, "sth", "sth", 16,
850 { 0, { (1<<MACH_BASE) } }
852 /* stb $Ri,@$Rj */
854 FR30_INSN_STB, "stb", "stb", 16,
855 { 0, { (1<<MACH_BASE) } }
857 /* st $Ri,@($R13,$Rj) */
859 FR30_INSN_STR13, "str13", "st", 16,
860 { 0, { (1<<MACH_BASE) } }
862 /* sth $Ri,@($R13,$Rj) */
864 FR30_INSN_STR13H, "str13h", "sth", 16,
865 { 0, { (1<<MACH_BASE) } }
867 /* stb $Ri,@($R13,$Rj) */
869 FR30_INSN_STR13B, "str13b", "stb", 16,
870 { 0, { (1<<MACH_BASE) } }
872 /* st $Ri,@($R14,$disp10) */
874 FR30_INSN_STR14, "str14", "st", 16,
875 { 0, { (1<<MACH_BASE) } }
877 /* sth $Ri,@($R14,$disp9) */
879 FR30_INSN_STR14H, "str14h", "sth", 16,
880 { 0, { (1<<MACH_BASE) } }
882 /* stb $Ri,@($R14,$disp8) */
884 FR30_INSN_STR14B, "str14b", "stb", 16,
885 { 0, { (1<<MACH_BASE) } }
887 /* st $Ri,@($R15,$udisp6) */
889 FR30_INSN_STR15, "str15", "st", 16,
890 { 0, { (1<<MACH_BASE) } }
892 /* st $Ri,@-$R15 */
894 FR30_INSN_STR15GR, "str15gr", "st", 16,
895 { 0, { (1<<MACH_BASE) } }
897 /* st $Rs2,@-$R15 */
899 FR30_INSN_STR15DR, "str15dr", "st", 16,
900 { 0, { (1<<MACH_BASE) } }
902 /* st $ps,@-$R15 */
904 FR30_INSN_STR15PS, "str15ps", "st", 16,
905 { 0, { (1<<MACH_BASE) } }
907 /* mov $Rj,$Ri */
909 FR30_INSN_MOV, "mov", "mov", 16,
910 { 0, { (1<<MACH_BASE) } }
912 /* mov $Rs1,$Ri */
914 FR30_INSN_MOVDR, "movdr", "mov", 16,
915 { 0, { (1<<MACH_BASE) } }
917 /* mov $ps,$Ri */
919 FR30_INSN_MOVPS, "movps", "mov", 16,
920 { 0, { (1<<MACH_BASE) } }
922 /* mov $Ri,$Rs1 */
924 FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
925 { 0, { (1<<MACH_BASE) } }
927 /* mov $Ri,$ps */
929 FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
930 { 0, { (1<<MACH_BASE) } }
932 /* jmp @$Ri */
934 FR30_INSN_JMP, "jmp", "jmp", 16,
935 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
937 /* jmp:d @$Ri */
939 FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
940 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
942 /* call @$Ri */
944 FR30_INSN_CALLR, "callr", "call", 16,
945 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
947 /* call:d @$Ri */
949 FR30_INSN_CALLRD, "callrd", "call:d", 16,
950 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
952 /* call $label12 */
954 FR30_INSN_CALL, "call", "call", 16,
955 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
957 /* call:d $label12 */
959 FR30_INSN_CALLD, "calld", "call:d", 16,
960 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
962 /* ret */
964 FR30_INSN_RET, "ret", "ret", 16,
965 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
967 /* ret:d */
969 FR30_INSN_RET_D, "ret:d", "ret:d", 16,
970 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
972 /* int $u8 */
974 FR30_INSN_INT, "int", "int", 16,
975 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
977 /* inte */
979 FR30_INSN_INTE, "inte", "inte", 16,
980 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
982 /* reti */
984 FR30_INSN_RETI, "reti", "reti", 16,
985 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
987 /* bra:d $label9 */
989 FR30_INSN_BRAD, "brad", "bra:d", 16,
990 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
992 /* bra $label9 */
994 FR30_INSN_BRA, "bra", "bra", 16,
995 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
997 /* bno:d $label9 */
999 FR30_INSN_BNOD, "bnod", "bno:d", 16,
1000 { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1002 /* bno $label9 */
1004 FR30_INSN_BNO, "bno", "bno", 16,
1005 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1007 /* beq:d $label9 */
1009 FR30_INSN_BEQD, "beqd", "beq:d", 16,
1010 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1012 /* beq $label9 */
1014 FR30_INSN_BEQ, "beq", "beq", 16,
1015 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1017 /* bne:d $label9 */
1019 FR30_INSN_BNED, "bned", "bne:d", 16,
1020 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1022 /* bne $label9 */
1024 FR30_INSN_BNE, "bne", "bne", 16,
1025 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1027 /* bc:d $label9 */
1029 FR30_INSN_BCD, "bcd", "bc:d", 16,
1030 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1032 /* bc $label9 */
1034 FR30_INSN_BC, "bc", "bc", 16,
1035 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1037 /* bnc:d $label9 */
1039 FR30_INSN_BNCD, "bncd", "bnc:d", 16,
1040 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1042 /* bnc $label9 */
1044 FR30_INSN_BNC, "bnc", "bnc", 16,
1045 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1047 /* bn:d $label9 */
1049 FR30_INSN_BND, "bnd", "bn:d", 16,
1050 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1052 /* bn $label9 */
1054 FR30_INSN_BN, "bn", "bn", 16,
1055 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1057 /* bp:d $label9 */
1059 FR30_INSN_BPD, "bpd", "bp:d", 16,
1060 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1062 /* bp $label9 */
1064 FR30_INSN_BP, "bp", "bp", 16,
1065 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1067 /* bv:d $label9 */
1069 FR30_INSN_BVD, "bvd", "bv:d", 16,
1070 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1072 /* bv $label9 */
1074 FR30_INSN_BV, "bv", "bv", 16,
1075 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1077 /* bnv:d $label9 */
1079 FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
1080 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1082 /* bnv $label9 */
1084 FR30_INSN_BNV, "bnv", "bnv", 16,
1085 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1087 /* blt:d $label9 */
1089 FR30_INSN_BLTD, "bltd", "blt:d", 16,
1090 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1092 /* blt $label9 */
1094 FR30_INSN_BLT, "blt", "blt", 16,
1095 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1097 /* bge:d $label9 */
1099 FR30_INSN_BGED, "bged", "bge:d", 16,
1100 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1102 /* bge $label9 */
1104 FR30_INSN_BGE, "bge", "bge", 16,
1105 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1107 /* ble:d $label9 */
1109 FR30_INSN_BLED, "bled", "ble:d", 16,
1110 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1112 /* ble $label9 */
1114 FR30_INSN_BLE, "ble", "ble", 16,
1115 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1117 /* bgt:d $label9 */
1119 FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
1120 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1122 /* bgt $label9 */
1124 FR30_INSN_BGT, "bgt", "bgt", 16,
1125 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1127 /* bls:d $label9 */
1129 FR30_INSN_BLSD, "blsd", "bls:d", 16,
1130 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1132 /* bls $label9 */
1134 FR30_INSN_BLS, "bls", "bls", 16,
1135 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1137 /* bhi:d $label9 */
1139 FR30_INSN_BHID, "bhid", "bhi:d", 16,
1140 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1142 /* bhi $label9 */
1144 FR30_INSN_BHI, "bhi", "bhi", 16,
1145 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1147 /* dmov $R13,@$dir10 */
1149 FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
1150 { 0, { (1<<MACH_BASE) } }
1152 /* dmovh $R13,@$dir9 */
1154 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
1155 { 0, { (1<<MACH_BASE) } }
1157 /* dmovb $R13,@$dir8 */
1159 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
1160 { 0, { (1<<MACH_BASE) } }
1162 /* dmov @$R13+,@$dir10 */
1164 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
1165 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1167 /* dmovh @$R13+,@$dir9 */
1169 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
1170 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1172 /* dmovb @$R13+,@$dir8 */
1174 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
1175 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1177 /* dmov @$R15+,@$dir10 */
1179 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
1180 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1182 /* dmov @$dir10,$R13 */
1184 FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
1185 { 0, { (1<<MACH_BASE) } }
1187 /* dmovh @$dir9,$R13 */
1189 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
1190 { 0, { (1<<MACH_BASE) } }
1192 /* dmovb @$dir8,$R13 */
1194 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
1195 { 0, { (1<<MACH_BASE) } }
1197 /* dmov @$dir10,@$R13+ */
1199 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
1200 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1202 /* dmovh @$dir9,@$R13+ */
1204 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
1205 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1207 /* dmovb @$dir8,@$R13+ */
1209 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
1210 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1212 /* dmov @$dir10,@-$R15 */
1214 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
1215 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1217 /* ldres @$Ri+,$u4 */
1219 FR30_INSN_LDRES, "ldres", "ldres", 16,
1220 { 0, { (1<<MACH_BASE) } }
1222 /* stres $u4,@$Ri+ */
1224 FR30_INSN_STRES, "stres", "stres", 16,
1225 { 0, { (1<<MACH_BASE) } }
1227 /* copop $u4c,$ccc,$CRj,$CRi */
1229 FR30_INSN_COPOP, "copop", "copop", 32,
1230 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1232 /* copld $u4c,$ccc,$Rjc,$CRi */
1234 FR30_INSN_COPLD, "copld", "copld", 32,
1235 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1237 /* copst $u4c,$ccc,$CRj,$Ric */
1239 FR30_INSN_COPST, "copst", "copst", 32,
1240 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1242 /* copsv $u4c,$ccc,$CRj,$Ric */
1244 FR30_INSN_COPSV, "copsv", "copsv", 32,
1245 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1247 /* nop */
1249 FR30_INSN_NOP, "nop", "nop", 16,
1250 { 0, { (1<<MACH_BASE) } }
1252 /* andccr $u8 */
1254 FR30_INSN_ANDCCR, "andccr", "andccr", 16,
1255 { 0, { (1<<MACH_BASE) } }
1257 /* orccr $u8 */
1259 FR30_INSN_ORCCR, "orccr", "orccr", 16,
1260 { 0, { (1<<MACH_BASE) } }
1262 /* stilm $u8 */
1264 FR30_INSN_STILM, "stilm", "stilm", 16,
1265 { 0, { (1<<MACH_BASE) } }
1267 /* addsp $s10 */
1269 FR30_INSN_ADDSP, "addsp", "addsp", 16,
1270 { 0, { (1<<MACH_BASE) } }
1272 /* extsb $Ri */
1274 FR30_INSN_EXTSB, "extsb", "extsb", 16,
1275 { 0, { (1<<MACH_BASE) } }
1277 /* extub $Ri */
1279 FR30_INSN_EXTUB, "extub", "extub", 16,
1280 { 0, { (1<<MACH_BASE) } }
1282 /* extsh $Ri */
1284 FR30_INSN_EXTSH, "extsh", "extsh", 16,
1285 { 0, { (1<<MACH_BASE) } }
1287 /* extuh $Ri */
1289 FR30_INSN_EXTUH, "extuh", "extuh", 16,
1290 { 0, { (1<<MACH_BASE) } }
1292 /* ldm0 ($reglist_low_ld) */
1294 FR30_INSN_LDM0, "ldm0", "ldm0", 16,
1295 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1297 /* ldm1 ($reglist_hi_ld) */
1299 FR30_INSN_LDM1, "ldm1", "ldm1", 16,
1300 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1302 /* stm0 ($reglist_low_st) */
1304 FR30_INSN_STM0, "stm0", "stm0", 16,
1305 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1307 /* stm1 ($reglist_hi_st) */
1309 FR30_INSN_STM1, "stm1", "stm1", 16,
1310 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1312 /* enter $u10 */
1314 FR30_INSN_ENTER, "enter", "enter", 16,
1315 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1317 /* leave */
1319 FR30_INSN_LEAVE, "leave", "leave", 16,
1320 { 0, { (1<<MACH_BASE) } }
1322 /* xchb @$Rj,$Ri */
1324 FR30_INSN_XCHB, "xchb", "xchb", 16,
1325 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1329 #undef A
1330 #undef MNEM
1331 #undef OP
1333 /* Initialize anything needed to be done once, before any cpu_open call. */
1335 static void
1336 init_tables ()
1340 /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name. */
1342 static const CGEN_MACH *
1343 lookup_mach_via_bfd_name (table, name)
1344 const CGEN_MACH *table;
1345 const char *name;
1347 while (table->name)
1349 if (strcmp (name, table->bfd_name) == 0)
1350 return table;
1351 ++table;
1353 abort ();
1356 /* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1358 static void
1359 build_hw_table (cd)
1360 CGEN_CPU_TABLE *cd;
1362 int i;
1363 int machs = cd->machs;
1364 const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
1365 /* MAX_HW is only an upper bound on the number of selected entries.
1366 However each entry is indexed by it's enum so there can be holes in
1367 the table. */
1368 const CGEN_HW_ENTRY **selected =
1369 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1371 cd->hw_table.init_entries = init;
1372 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1373 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1374 /* ??? For now we just use machs to determine which ones we want. */
1375 for (i = 0; init[i].name != NULL; ++i)
1376 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1377 & machs)
1378 selected[init[i].type] = &init[i];
1379 cd->hw_table.entries = selected;
1380 cd->hw_table.num_entries = MAX_HW;
1383 /* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1385 static void
1386 build_ifield_table (cd)
1387 CGEN_CPU_TABLE *cd;
1389 cd->ifld_table = & fr30_cgen_ifld_table[0];
1392 /* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1394 static void
1395 build_operand_table (cd)
1396 CGEN_CPU_TABLE *cd;
1398 int i;
1399 int machs = cd->machs;
1400 const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
1401 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1402 However each entry is indexed by it's enum so there can be holes in
1403 the table. */
1404 const CGEN_OPERAND **selected =
1405 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1407 cd->operand_table.init_entries = init;
1408 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1409 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1410 /* ??? For now we just use mach to determine which ones we want. */
1411 for (i = 0; init[i].name != NULL; ++i)
1412 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1413 & machs)
1414 selected[init[i].type] = &init[i];
1415 cd->operand_table.entries = selected;
1416 cd->operand_table.num_entries = MAX_OPERANDS;
1419 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.
1420 ??? This could leave out insns not supported by the specified mach/isa,
1421 but that would cause errors like "foo only supported by bar" to become
1422 "unknown insn", so for now we include all insns and require the app to
1423 do the checking later.
1424 ??? On the other hand, parsing of such insns may require their hardware or
1425 operand elements to be in the table [which they mightn't be]. */
1427 static void
1428 build_insn_table (cd)
1429 CGEN_CPU_TABLE *cd;
1431 int i;
1432 const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
1433 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1435 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1436 for (i = 0; i < MAX_INSNS; ++i)
1437 insns[i].base = &ib[i];
1438 cd->insn_table.init_entries = insns;
1439 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1440 cd->insn_table.num_init_entries = MAX_INSNS;
1443 /* Subroutine of fr30_cgen_cpu_open to rebuild the tables. */
1445 static void
1446 fr30_cgen_rebuild_tables (cd)
1447 CGEN_CPU_TABLE *cd;
1449 int i,n_isas,n_machs;
1450 unsigned int isas = cd->isas;
1451 unsigned int machs = cd->machs;
1453 cd->int_insn_p = CGEN_INT_INSN_P;
1455 /* Data derived from the isa spec. */
1456 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1457 cd->default_insn_bitsize = UNSET;
1458 cd->base_insn_bitsize = UNSET;
1459 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1460 cd->max_insn_bitsize = 0;
1461 for (i = 0; i < MAX_ISAS; ++i)
1462 if (((1 << i) & isas) != 0)
1464 const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
1466 /* Default insn sizes of all selected isas must be equal or we set
1467 the result to 0, meaning "unknown". */
1468 if (cd->default_insn_bitsize == UNSET)
1469 cd->default_insn_bitsize = isa->default_insn_bitsize;
1470 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1471 ; /* this is ok */
1472 else
1473 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1475 /* Base insn sizes of all selected isas must be equal or we set
1476 the result to 0, meaning "unknown". */
1477 if (cd->base_insn_bitsize == UNSET)
1478 cd->base_insn_bitsize = isa->base_insn_bitsize;
1479 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1480 ; /* this is ok */
1481 else
1482 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1484 /* Set min,max insn sizes. */
1485 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1486 cd->min_insn_bitsize = isa->min_insn_bitsize;
1487 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1488 cd->max_insn_bitsize = isa->max_insn_bitsize;
1490 ++n_isas;
1493 /* Data derived from the mach spec. */
1494 for (i = 0; i < MAX_MACHS; ++i)
1495 if (((1 << i) & machs) != 0)
1497 const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
1499 ++n_machs;
1502 /* Determine which hw elements are used by MACH. */
1503 build_hw_table (cd);
1505 /* Build the ifield table. */
1506 build_ifield_table (cd);
1508 /* Determine which operands are used by MACH/ISA. */
1509 build_operand_table (cd);
1511 /* Build the instruction table. */
1512 build_insn_table (cd);
1515 /* Initialize a cpu table and return a descriptor.
1516 It's much like opening a file, and must be the first function called.
1517 The arguments are a set of (type/value) pairs, terminated with
1518 CGEN_CPU_OPEN_END.
1520 Currently supported values:
1521 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1522 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1523 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1524 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1525 CGEN_CPU_OPEN_END: terminates arguments
1527 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1528 precluded.
1530 ??? We only support ISO C stdargs here, not K&R.
1531 Laziness, plus experiment to see if anything requires K&R - eventually
1532 K&R will no longer be supported - e.g. GDB is currently trying this. */
1534 CGEN_CPU_DESC
1535 fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1537 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1538 static int init_p;
1539 unsigned int isas = 0; /* 0 = "unspecified" */
1540 unsigned int machs = 0; /* 0 = "unspecified" */
1541 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1542 va_list ap;
1544 if (! init_p)
1546 init_tables ();
1547 init_p = 1;
1550 memset (cd, 0, sizeof (*cd));
1552 va_start (ap, arg_type);
1553 while (arg_type != CGEN_CPU_OPEN_END)
1555 switch (arg_type)
1557 case CGEN_CPU_OPEN_ISAS :
1558 isas = va_arg (ap, unsigned int);
1559 break;
1560 case CGEN_CPU_OPEN_MACHS :
1561 machs = va_arg (ap, unsigned int);
1562 break;
1563 case CGEN_CPU_OPEN_BFDMACH :
1565 const char *name = va_arg (ap, const char *);
1566 const CGEN_MACH *mach =
1567 lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
1569 machs |= mach->num << 1;
1570 break;
1572 case CGEN_CPU_OPEN_ENDIAN :
1573 endian = va_arg (ap, enum cgen_endian);
1574 break;
1575 default :
1576 fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
1577 arg_type);
1578 abort (); /* ??? return NULL? */
1580 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1582 va_end (ap);
1584 /* mach unspecified means "all" */
1585 if (machs == 0)
1586 machs = (1 << MAX_MACHS) - 1;
1587 /* base mach is always selected */
1588 machs |= 1;
1589 /* isa unspecified means "all" */
1590 if (isas == 0)
1591 isas = (1 << MAX_ISAS) - 1;
1592 if (endian == CGEN_ENDIAN_UNKNOWN)
1594 /* ??? If target has only one, could have a default. */
1595 fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
1596 abort ();
1599 cd->isas = isas;
1600 cd->machs = machs;
1601 cd->endian = endian;
1602 /* FIXME: for the sparc case we can determine insn-endianness statically.
1603 The worry here is where both data and insn endian can be independently
1604 chosen, in which case this function will need another argument.
1605 Actually, will want to allow for more arguments in the future anyway. */
1606 cd->insn_endian = endian;
1608 /* Table (re)builder. */
1609 cd->rebuild_tables = fr30_cgen_rebuild_tables;
1610 fr30_cgen_rebuild_tables (cd);
1612 return (CGEN_CPU_DESC) cd;
1615 /* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1616 MACH_NAME is the bfd name of the mach. */
1618 CGEN_CPU_DESC
1619 fr30_cgen_cpu_open_1 (mach_name, endian)
1620 const char *mach_name;
1621 enum cgen_endian endian;
1623 return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1624 CGEN_CPU_OPEN_ENDIAN, endian,
1625 CGEN_CPU_OPEN_END);
1628 /* Close a cpu table.
1629 ??? This can live in a machine independent file, but there's currently
1630 no place to put this file (there's no libcgen). libopcodes is the wrong
1631 place as some simulator ports use this but they don't use libopcodes. */
1633 void
1634 fr30_cgen_cpu_close (cd)
1635 CGEN_CPU_DESC cd;
1637 if (cd->insn_table.init_entries)
1638 free ((CGEN_INSN *) cd->insn_table.init_entries);
1639 if (cd->hw_table.entries)
1640 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1641 free (cd);