1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 1, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "opcode/mips.h"
26 /* Short hand so the lines aren't too long. */
28 #define LDD INSN_LOAD_MEMORY_DELAY
29 #define LCD INSN_LOAD_COPROC_DELAY
30 #define UBD INSN_UNCOND_BRANCH_DELAY
31 #define CBD INSN_COND_BRANCH_DELAY
32 #define COD INSN_COPROC_MOVE_DELAY
33 #define CLD INSN_COPROC_MEMORY_DELAY
34 #define CBL INSN_COND_BRANCH_LIKELY
35 #define TRAP INSN_TRAP
36 #define SM INSN_STORE_MEMORY
38 #define WR_d INSN_WRITE_GPR_D
39 #define WR_t INSN_WRITE_GPR_T
40 #define WR_31 INSN_WRITE_GPR_31
41 #define WR_D INSN_WRITE_FPR_D
42 #define WR_T INSN_WRITE_FPR_T
43 #define WR_S INSN_WRITE_FPR_S
44 #define RD_s INSN_READ_GPR_S
45 #define RD_b INSN_READ_GPR_S
46 #define RD_t INSN_READ_GPR_T
47 #define RD_S INSN_READ_FPR_S
48 #define RD_T INSN_READ_FPR_T
49 #define RD_R INSN_READ_FPR_R
50 #define WR_CC INSN_WRITE_COND_CODE
51 #define RD_CC INSN_READ_COND_CODE
52 #define RD_C0 INSN_COP
53 #define RD_C1 INSN_COP
54 #define RD_C2 INSN_COP
55 #define RD_C3 INSN_COP
56 #define WR_C0 INSN_COP
57 #define WR_C1 INSN_COP
58 #define WR_C2 INSN_COP
59 #define WR_C3 INSN_COP
61 #define WR_HI INSN_WRITE_HI
62 #define RD_HI INSN_READ_HI
63 #define MOD_HI WR_HI|RD_HI
65 #define WR_LO INSN_WRITE_LO
66 #define RD_LO INSN_READ_LO
67 #define MOD_LO WR_LO|RD_LO
69 #define WR_HILO WR_HI|WR_LO
70 #define RD_HILO RD_HI|RD_LO
71 #define MOD_HILO WR_HILO|RD_HILO
73 #define IS_M INSN_MULT
81 #define P4 INSN_MIPS32
100 /* The order of overloaded instructions matters. Label arguments and
101 register arguments look the same. Instructions that can have either
102 for arguments must apear in the correct order in this table for the
103 assembler to pick the right one. In other words, entries with
104 immediate operands must apear after the same instruction with
107 Many instructions are short hand for other instructions (i.e., The
108 jal <register> instruction is short for jalr <register>). */
110 const struct mips_opcode mips_builtin_opcodes
[] = {
111 /* These instructions appear first so that the disassembler will find
112 them first. The assemblers uses a hash table based on the
113 instruction name anyhow. */
114 /* name, args, match, mask, pinfo, membership */
115 {"nop", "", 0x00000000, 0xffffffff, 0, I1
},
116 {"li", "t,j", 0x24000000, 0xffe00000, WR_t
, I1
}, /* addiu */
117 {"li", "t,i", 0x34000000, 0xffe00000, WR_t
, I1
}, /* ori */
118 {"li", "t,I", 0, (int) M_LI
, INSN_MACRO
, I1
},
119 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d
|RD_s
, I1
|G6
},/* or */
120 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d
|RD_s
, I3
},/* daddu */
121 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d
|RD_s
, I1
},/* addu */
122 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d
|RD_s
, I1
},/* or */
123 {"b", "p", 0x10000000, 0xffff0000, UBD
, I1
},/* beq 0,0 */
124 {"b", "p", 0x04010000, 0xffff0000, UBD
, I1
},/* bgez 0 */
125 {"bal", "p", 0x04110000, 0xffff0000, UBD
|WR_31
, I1
},/* bgezal 0*/
127 {"abs", "d,v", 0, (int) M_ABS
, INSN_MACRO
, I1
},
128 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
129 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
130 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D
|RD_S
|FP_D
, I5
},
131 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
132 {"add", "t,r,I", 0, (int) M_ADD_I
, INSN_MACRO
, I1
},
133 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, I1
},
134 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I1
},
135 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
136 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t
|RD_s
, I1
},
137 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t
|RD_s
, I1
},
138 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
139 {"addu", "t,r,I", 0, (int) M_ADDU_I
, INSN_MACRO
, I1
},
140 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
141 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
142 {"and", "t,r,I", 0, (int) M_AND_I
, INSN_MACRO
, I1
},
143 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t
|RD_s
, I1
},
144 /* b is at the top of the table. */
145 /* bal is at the top of the table. */
146 {"bc0f", "p", 0x41000000, 0xffff0000, CBD
|RD_CC
, I1
},
147 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
148 {"bc1f", "p", 0x45000000, 0xffff0000, CBD
|RD_CC
|FP_S
, I1
|M1
},
149 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD
|RD_CC
|FP_S
, I4
|M1
},
150 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL
|RD_CC
|FP_S
, I2
|T3
|M1
},
151 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL
|RD_CC
|FP_S
, I4
|M1
},
152 {"bc2f", "p", 0x49000000, 0xffff0000, CBD
|RD_CC
, I1
},
153 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
154 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD
|RD_CC
, I1
},
155 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
156 {"bc0t", "p", 0x41010000, 0xffff0000, CBD
|RD_CC
, I1
},
157 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
158 {"bc1t", "p", 0x45010000, 0xffff0000, CBD
|RD_CC
|FP_S
, I1
},
159 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD
|RD_CC
|FP_S
, I4
|M1
},
160 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL
|RD_CC
|FP_S
, I2
|T3
},
161 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL
|RD_CC
|FP_S
, I4
|M1
},
162 {"bc2t", "p", 0x49010000, 0xffff0000, CBD
|RD_CC
, I1
},
163 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
164 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD
|RD_CC
, I1
},
165 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL
|RD_CC
, I2
|T3
},
166 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD
|RD_s
, I1
},
167 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
168 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD
|RD_s
|RD_t
, I1
},
169 {"beq", "s,I,p", 0, (int) M_BEQ_I
, INSN_MACRO
, I1
},
170 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL
|RD_s
|RD_t
, I2
|T3
},
171 {"beql", "s,I,p", 0, (int) M_BEQL_I
, INSN_MACRO
, I2
},
172 {"bge", "s,t,p", 0, (int) M_BGE
, INSN_MACRO
, I1
},
173 {"bge", "s,I,p", 0, (int) M_BGE_I
, INSN_MACRO
, I1
},
174 {"bgel", "s,t,p", 0, (int) M_BGEL
, INSN_MACRO
, I2
},
175 {"bgel", "s,I,p", 0, (int) M_BGEL_I
, INSN_MACRO
, I2
},
176 {"bgeu", "s,t,p", 0, (int) M_BGEU
, INSN_MACRO
, I1
},
177 {"bgeu", "s,I,p", 0, (int) M_BGEU_I
, INSN_MACRO
, I1
},
178 {"bgeul", "s,t,p", 0, (int) M_BGEUL
, INSN_MACRO
, I2
},
179 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I
, INSN_MACRO
, I2
},
180 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD
|RD_s
, I1
},
181 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
182 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD
|RD_s
|WR_31
, I1
},
183 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
184 {"bgt", "s,t,p", 0, (int) M_BGT
, INSN_MACRO
, I1
},
185 {"bgt", "s,I,p", 0, (int) M_BGT_I
, INSN_MACRO
, I1
},
186 {"bgtl", "s,t,p", 0, (int) M_BGTL
, INSN_MACRO
, I2
},
187 {"bgtl", "s,I,p", 0, (int) M_BGTL_I
, INSN_MACRO
, I2
},
188 {"bgtu", "s,t,p", 0, (int) M_BGTU
, INSN_MACRO
, I1
},
189 {"bgtu", "s,I,p", 0, (int) M_BGTU_I
, INSN_MACRO
, I1
},
190 {"bgtul", "s,t,p", 0, (int) M_BGTUL
, INSN_MACRO
, I2
},
191 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I
, INSN_MACRO
, I2
},
192 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD
|RD_s
, I1
},
193 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
194 {"ble", "s,t,p", 0, (int) M_BLE
, INSN_MACRO
, I1
},
195 {"ble", "s,I,p", 0, (int) M_BLE_I
, INSN_MACRO
, I1
},
196 {"blel", "s,t,p", 0, (int) M_BLEL
, INSN_MACRO
, I2
},
197 {"blel", "s,I,p", 0, (int) M_BLEL_I
, INSN_MACRO
, I2
},
198 {"bleu", "s,t,p", 0, (int) M_BLEU
, INSN_MACRO
, I1
},
199 {"bleu", "s,I,p", 0, (int) M_BLEU_I
, INSN_MACRO
, I1
},
200 {"bleul", "s,t,p", 0, (int) M_BLEUL
, INSN_MACRO
, I2
},
201 {"bleul", "s,I,p", 0, (int) M_BLEUL_I
, INSN_MACRO
, I2
},
202 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD
|RD_s
, I1
},
203 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
204 {"blt", "s,t,p", 0, (int) M_BLT
, INSN_MACRO
, I1
},
205 {"blt", "s,I,p", 0, (int) M_BLT_I
, INSN_MACRO
, I1
},
206 {"bltl", "s,t,p", 0, (int) M_BLTL
, INSN_MACRO
, I2
},
207 {"bltl", "s,I,p", 0, (int) M_BLTL_I
, INSN_MACRO
, I2
},
208 {"bltu", "s,t,p", 0, (int) M_BLTU
, INSN_MACRO
, I1
},
209 {"bltu", "s,I,p", 0, (int) M_BLTU_I
, INSN_MACRO
, I1
},
210 {"bltul", "s,t,p", 0, (int) M_BLTUL
, INSN_MACRO
, I2
},
211 {"bltul", "s,I,p", 0, (int) M_BLTUL_I
, INSN_MACRO
, I2
},
212 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD
|RD_s
, I1
},
213 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
214 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD
|RD_s
|WR_31
, I1
},
215 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
216 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD
|RD_s
, I1
},
217 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL
|RD_s
, I2
|T3
},
218 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD
|RD_s
|RD_t
, I1
},
219 {"bne", "s,I,p", 0, (int) M_BNE_I
, INSN_MACRO
, I1
},
220 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL
|RD_s
|RD_t
, I2
|T3
},
221 {"bnel", "s,I,p", 0, (int) M_BNEL_I
, INSN_MACRO
, I2
},
222 {"break", "", 0x0000000d, 0xffffffff, TRAP
, I1
},
223 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP
, I1
},
224 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP
, I1
},
225 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
226 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
227 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
228 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
229 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
230 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
231 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
232 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
233 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
234 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
235 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
236 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
237 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
238 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
239 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
240 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
241 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
242 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
243 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
244 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
245 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
246 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
247 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
248 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
249 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
250 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
251 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
252 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
253 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
254 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
255 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
256 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
257 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
258 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
259 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
260 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
261 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
262 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
263 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
264 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
265 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
266 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
267 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
268 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
269 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
270 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
271 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
272 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
273 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
274 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
275 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
276 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
277 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
278 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
279 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
280 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
281 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
282 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
283 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
284 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
285 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
286 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
287 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
288 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
289 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
290 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
291 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
292 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
293 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
294 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
295 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
296 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
297 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
298 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
299 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
300 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
301 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
302 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
303 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
304 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
305 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
306 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
307 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
308 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
309 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
310 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
311 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
312 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
313 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
314 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
315 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I1
},
316 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I4
|M1
},
317 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_S
, I1
},
318 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_S
, I4
|M1
},
319 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
320 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S
|RD_T
|WR_CC
|FP_D
, I5
},
321 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b
, I3
|T3
|M1
|P4
},
322 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
323 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
324 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
325 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
326 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD
|WR_t
|RD_C0
, I1
},
327 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD
|WR_t
|RD_C1
|FP_S
, I1
},
328 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD
|WR_t
|RD_C1
|FP_S
, I1
},
329 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD
|WR_t
|RD_C2
, I1
},
330 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD
|WR_t
|RD_C3
, I1
},
331 {"clo", "d,s", 0x70000021, 0xfc1f07ff, WR_d
|RD_s
, P4
},
332 {"clz", "d,s", 0x70000020, 0xfc1f07ff, WR_d
|RD_s
, P4
},
333 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD
|RD_t
|WR_CC
, I1
},
334 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD
|RD_t
|WR_CC
|FP_S
, I1
},
335 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD
|RD_t
|WR_CC
|FP_S
, I1
},
336 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD
|RD_t
|WR_CC
, I1
},
337 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD
|RD_t
|WR_CC
, I1
},
338 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
339 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D
|RD_S
|FP_D
|FP_S
, I1
},
340 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
341 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
342 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
343 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
344 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D
|RD_S
|FP_S
|FP_D
, I1
},
345 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
346 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D
|RD_S
|FP_S
|FP_D
, I5
},
347 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D
|RD_S
|FP_S
|FP_D
, I5
},
348 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
349 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
350 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
351 {"dabs", "d,v", 0, (int) M_DABS
, INSN_MACRO
, I3
},
352 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I3
},
353 {"dadd", "t,r,I", 0, (int) M_DADD_I
, INSN_MACRO
, I3
},
354 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t
|RD_s
, I3
},
355 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t
|RD_s
, I3
},
356 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I3
},
357 {"daddu", "t,r,I", 0, (int) M_DADDU_I
, INSN_MACRO
, I3
},
358 /* dctr and dctw are used on the r5000. */
359 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b
, I3
},
360 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b
, I3
},
361 {"deret", "", 0x4200001f, 0xffffffff, 0, G2
|M1
|P4
},
362 /* For ddiv, see the comments about div. */
363 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I3
},
364 {"ddiv", "d,v,t", 0, (int) M_DDIV_3
, INSN_MACRO
, I3
},
365 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I
, INSN_MACRO
, I3
},
366 /* For ddivu, see the comments about div. */
367 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I3
},
368 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3
, INSN_MACRO
, I3
},
369 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I
, INSN_MACRO
, I3
},
370 /* The MIPS assembler treats the div opcode with two operands as
371 though the first operand appeared twice (the first operand is both
372 a source and a destination). To get the div machine instruction,
373 you must use an explicit destination of $0. */
374 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I1
},
375 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I1
},
376 {"div", "d,v,t", 0, (int) M_DIV_3
, INSN_MACRO
, I1
},
377 {"div", "d,v,I", 0, (int) M_DIV_3I
, INSN_MACRO
, I1
},
378 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I1
},
379 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, I1
},
380 /* For divu, see the comments about div. */
381 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I1
},
382 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I1
},
383 {"divu", "d,v,t", 0, (int) M_DIVU_3
, INSN_MACRO
, I1
},
384 {"divu", "d,v,I", 0, (int) M_DIVU_3I
, INSN_MACRO
, I1
},
385 {"dla", "t,o(b)", 0x64000000, 0xfc000000, WR_t
|RD_s
, I3
}, /* daddiu */
386 {"dla", "t,A(b)", 0, (int) M_DLA_AB
, INSN_MACRO
, I3
},
387 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t
, I3
}, /* addiu */
388 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t
, I3
}, /* ori */
389 {"dli", "t,I", 0, (int) M_DLI
, INSN_MACRO
, I3
},
391 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s
|RD_t
|WR_LO
|RD_LO
, V1
},
392 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD
|WR_t
|RD_C0
, I3
},
393 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD
|RD_t
|WR_C0
|WR_CC
, I3
},
394 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD
|WR_t
|RD_S
|FP_S
, I3
},
395 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD
|RD_t
|WR_S
|FP_S
, I3
},
396 {"dmfc2", "t,S", 0x48200000, 0xffe007ff, LCD
|WR_t
|RD_S
|FP_S
, I3
},
397 {"dmtc2", "t,S", 0x48a00000, 0xffe007ff, COD
|RD_t
|WR_S
|FP_S
, I3
},
398 {"dmul", "d,v,t", 0, (int) M_DMUL
, INSN_MACRO
, I3
},
399 {"dmul", "d,v,I", 0, (int) M_DMUL_I
, INSN_MACRO
, I3
},
400 {"dmulo", "d,v,t", 0, (int) M_DMULO
, INSN_MACRO
, I3
},
401 {"dmulo", "d,v,I", 0, (int) M_DMULO_I
, INSN_MACRO
, I3
},
402 {"dmulou", "d,v,t", 0, (int) M_DMULOU
, INSN_MACRO
, I3
},
403 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I
, INSN_MACRO
, I3
},
404 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I3
},
405 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I3
},
406 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d
|RD_t
, I3
}, /* dsub 0 */
407 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d
|RD_t
, I3
}, /* dsubu 0*/
408 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I3
},
409 {"drem", "d,v,t", 3, (int) M_DREM_3
, INSN_MACRO
, I3
},
410 {"drem", "d,v,I", 3, (int) M_DREM_3I
, INSN_MACRO
, I3
},
411 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I3
},
412 {"dremu", "d,v,t", 3, (int) M_DREMU_3
, INSN_MACRO
, I3
},
413 {"dremu", "d,v,I", 3, (int) M_DREMU_3I
, INSN_MACRO
, I3
},
414 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
},
415 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d
|RD_t
, I3
},
416 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
}, /* dsllv */
417 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d
|RD_t
, I3
}, /* dsll32 */
418 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d
|RD_t
, I3
},
419 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
},
420 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d
|RD_t
, I3
},
421 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
}, /* dsrav */
422 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d
|RD_t
, I3
}, /* dsra32 */
423 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d
|RD_t
, I3
},
424 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
},
425 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d
|RD_t
, I3
},
426 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I3
}, /* dsrlv */
427 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d
|RD_t
, I3
}, /* dsrl32 */
428 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d
|RD_t
, I3
},
429 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I3
},
430 {"dsub", "d,v,I", 0, (int) M_DSUB_I
, INSN_MACRO
, I3
},
431 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I3
},
432 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I
, INSN_MACRO
, I3
},
433 {"eret", "", 0x42000018, 0xffffffff, 0, I3
|M1
|P4
},
434 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
435 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
436 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
437 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
438 {"flushi", "", 0xbc010000, 0xffffffff, 0, L1
},
439 {"flushd", "", 0xbc020000, 0xffffffff, 0, L1
},
440 {"flushid", "", 0xbc030000, 0xffffffff, 0, L1
},
441 {"hibernate","", 0x42000023, 0xffffffff, 0, V1
},
442 {"jr", "s", 0x00000008, 0xfc1fffff, UBD
|RD_s
, I1
},
443 {"j", "s", 0x00000008, 0xfc1fffff, UBD
|RD_s
, I1
}, /* jr */
444 /* SVR4 PIC code requires special handling for j, so it must be a
446 {"j", "a", 0, (int) M_J_A
, INSN_MACRO
, I1
},
447 /* This form of j is used by the disassembler and internally by the
448 assembler, but will never match user input (because the line above
449 will match first). */
450 {"j", "a", 0x08000000, 0xfc000000, UBD
, I1
},
451 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD
|RD_s
|WR_d
, I1
},
452 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD
|RD_s
|WR_d
, I1
},
453 /* SVR4 PIC code requires special handling for jal, so it must be a
455 {"jal", "d,s", 0, (int) M_JAL_2
, INSN_MACRO
, I1
},
456 {"jal", "s", 0, (int) M_JAL_1
, INSN_MACRO
, I1
},
457 {"jal", "a", 0, (int) M_JAL_A
, INSN_MACRO
, I1
},
458 /* This form of jal is used by the disassembler and internally by the
459 assembler, but will never match user input (because the line above
460 will match first). */
461 {"jal", "a", 0x0c000000, 0xfc000000, UBD
|WR_31
, I1
},
462 /* jalx really should only be avaliable if mips16 is available,
463 but for now make it I1. */
464 {"jalx", "a", 0x74000000, 0xfc000000, UBD
|WR_31
, I1
},
465 {"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t
|RD_s
, I1
}, /* addiu */
466 {"la", "t,A(b)", 0, (int) M_LA_AB
, INSN_MACRO
, I1
},
467 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
468 {"lb", "t,A(b)", 0, (int) M_LB_AB
, INSN_MACRO
, I1
},
469 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
470 {"lbu", "t,A(b)", 0, (int) M_LBU_AB
, INSN_MACRO
, I1
},
471 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t
|RD_b
, I3
},
472 {"ld", "t,o(b)", 0, (int) M_LD_OB
, INSN_MACRO
, I1
},
473 {"ld", "t,A(b)", 0, (int) M_LD_AB
, INSN_MACRO
, I1
},
474 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_D
, I2
},
475 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_D
, I2
},
476 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB
, INSN_MACRO
, I2
},
477 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB
, INSN_MACRO
, I2
},
478 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_D
, I2
}, /* ldc1 */
479 {"l.d", "T,o(b)", 0, (int) M_L_DOB
, INSN_MACRO
, I1
},
480 {"l.d", "T,A(b)", 0, (int) M_L_DAB
, INSN_MACRO
, I1
},
481 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I2
},
482 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB
, INSN_MACRO
, I2
},
483 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I2
},
484 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB
, INSN_MACRO
, I2
},
485 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD
|WR_t
|RD_b
, I3
},
486 {"ldl", "t,A(b)", 0, (int) M_LDL_AB
, INSN_MACRO
, I3
},
487 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD
|WR_t
|RD_b
, I3
},
488 {"ldr", "t,A(b)", 0, (int) M_LDR_AB
, INSN_MACRO
, I3
},
489 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD
|WR_D
|RD_t
|RD_b
, I4
},
490 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
491 {"lh", "t,A(b)", 0, (int) M_LH_AB
, INSN_MACRO
, I1
},
492 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
493 {"lhu", "t,A(b)", 0, (int) M_LHU_AB
, INSN_MACRO
, I1
},
494 /* li is at the start of the table. */
495 {"li.d", "t,F", 0, (int) M_LI_D
, INSN_MACRO
, I1
},
496 {"li.d", "T,L", 0, (int) M_LI_DD
, INSN_MACRO
, I1
},
497 {"li.s", "t,f", 0, (int) M_LI_S
, INSN_MACRO
, I1
},
498 {"li.s", "T,l", 0, (int) M_LI_SS
, INSN_MACRO
, I1
},
499 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD
|RD_b
|WR_t
, I2
},
500 {"ll", "t,A(b)", 0, (int) M_LL_AB
, INSN_MACRO
, I2
},
501 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD
|RD_b
|WR_t
, I3
},
502 {"lld", "t,A(b)", 0, (int) M_LLD_AB
, INSN_MACRO
, I3
},
503 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t
, I1
},
504 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD
|WR_D
|RD_t
|RD_b
, I5
},
505 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
506 {"lw", "t,A(b)", 0, (int) M_LW_AB
, INSN_MACRO
, I1
},
507 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I1
},
508 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB
, INSN_MACRO
, I1
},
509 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_S
, I1
},
510 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_S
, I1
},
511 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
, I1
},
512 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
, I1
},
513 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD
|RD_b
|WR_T
|FP_S
, I1
}, /* lwc1 */
514 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
, I1
},
515 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I1
},
516 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB
, INSN_MACRO
, I1
},
517 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD
|RD_b
|WR_CC
, I1
},
518 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB
, INSN_MACRO
, I1
},
519 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
520 {"lwl", "t,A(b)", 0, (int) M_LWL_AB
, INSN_MACRO
, I1
},
521 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD
|RD_b
|WR_t
, I2
}, /* same */
522 {"lcache", "t,A(b)", 0, (int) M_LWL_AB
, INSN_MACRO
, I2
}, /* as lwl */
523 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD
|RD_b
|WR_t
, I1
},
524 {"lwr", "t,A(b)", 0, (int) M_LWR_AB
, INSN_MACRO
, I1
},
525 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD
|RD_b
|WR_t
, I2
}, /* same */
526 {"flush", "t,A(b)", 0, (int) M_LWR_AB
, INSN_MACRO
, I2
}, /* as lwr */
527 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD
|RD_b
|WR_t
, I3
},
528 {"lwu", "t,A(b)", 0, (int) M_LWU_AB
, INSN_MACRO
, I3
},
529 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD
|WR_D
|RD_t
|RD_b
, I4
},
530 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|RD_HI
|RD_LO
, P3
|P4
},
531 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|RD_HI
|RD_LO
, P3
|P4
},
532 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I4
},
533 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, I4
},
534 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I5
},
535 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, L1
},
536 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|RD_HI
|RD_LO
, P4
},
537 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|IS_M
, G1
|M1
},
538 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s
|RD_t
|WR_HI
|WR_LO
|WR_d
|IS_M
, G1
},
539 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, L1
},
540 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|RD_HI
|RD_LO
, P4
},
541 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|IS_M
, G1
|M1
},
542 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s
|RD_t
|WR_HI
|WR_LO
|WR_d
|IS_M
, G1
},
543 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|RD_HI
|RD_LO
, V1
},
544 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD
|WR_t
|RD_C0
, I1
},
545 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD
|WR_t
|RD_C0
, P4
},
546 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD
|WR_t
|RD_S
|FP_S
, I1
},
547 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD
|WR_t
|RD_S
|FP_S
, I1
},
548 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD
|WR_t
|RD_C2
, I1
},
549 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD
|WR_t
|RD_C3
, I1
},
550 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d
|RD_HI
, I1
},
551 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d
|RD_LO
, I1
},
552 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
553 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
554 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D
|RD_S
|FP_D
, I5
},
555 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d
|RD_s
|RD_CC
|FP_D
|FP_S
, I4
|M1
},
556 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_D
, I4
|M1
},
557 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_S
, I4
|M1
},
558 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_D
, I5
},
559 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I4
|M1
|P4
},
560 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d
|RD_s
,L1
},
561 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_D
, I4
|M1
},
562 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_S
, I4
|M1
},
563 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d
|RD_s
|RD_CC
, I4
|M1
},
564 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_D
, I4
|M1
},
565 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_S
, I4
|M1
},
566 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D
|RD_S
|RD_CC
|FP_D
, I5
},
567 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I4
|M1
|P4
},
568 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d
|RD_s
,L1
},
569 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_D
, I4
|M1
},
570 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D
|RD_S
|RD_t
|FP_S
, I4
|M1
},
571 /* move is at the top of the table. */
572 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I4
},
573 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, I4
},
574 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I5
},
575 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
,L1
},
576 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|RD_HI
|RD_LO
, P4
},
577 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
,L1
},
578 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|RD_HI
|RD_LO
, P4
},
579 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD
|RD_t
|WR_C0
|WR_CC
, I1
},
580 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD
|RD_t
|WR_C0
|WR_CC
, P4
},
581 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD
|RD_t
|WR_S
|FP_S
, I1
},
582 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD
|RD_t
|WR_S
|FP_S
, I1
},
583 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD
|RD_t
|WR_C2
|WR_CC
, I1
},
584 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD
|RD_t
|WR_C3
|WR_CC
, I1
},
585 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s
|WR_HI
, I1
},
586 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s
|WR_LO
, I1
},
587 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I1
},
588 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, I1
},
589 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
590 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d
|RD_s
|RD_t
|WR_HI
|WR_LO
, P3
|P4
},
591 {"mul", "d,v,t", 0, (int) M_MUL
, INSN_MACRO
, I1
},
592 {"mul", "d,v,I", 0, (int) M_MUL_I
, INSN_MACRO
, I1
},
593 {"mulo", "d,v,t", 0, (int) M_MULO
, INSN_MACRO
, I1
},
594 {"mulo", "d,v,I", 0, (int) M_MULO_I
, INSN_MACRO
, I1
},
595 {"mulou", "d,v,t", 0, (int) M_MULOU
, INSN_MACRO
, I1
},
596 {"mulou", "d,v,I", 0, (int) M_MULOU_I
, INSN_MACRO
, I1
},
597 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|IS_M
, I1
},
598 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s
|RD_t
|WR_HI
|WR_LO
|WR_d
|IS_M
, G1
},
599 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|IS_M
, I1
},
600 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s
|RD_t
|WR_HI
|WR_LO
|WR_d
|IS_M
, G1
},
601 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d
|RD_t
, I1
}, /* sub 0 */
602 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d
|RD_t
, I1
}, /* subu 0 */
603 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D
|RD_S
|FP_D
, I1
},
604 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D
|RD_S
|FP_S
, I1
},
605 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D
|RD_S
|FP_D
,I5
},
606 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I4
},
607 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, I4
},
608 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I5
},
609 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I4
},
610 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_S
, I4
},
611 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R
|RD_S
|RD_T
|WR_D
|FP_D
, I5
},
612 /* nop is at the start of the table. */
613 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
614 {"nor", "t,r,I", 0, (int) M_NOR_I
, INSN_MACRO
, I1
},
615 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d
|RD_s
|RD_t
, I1
},/*nor d,s,0*/
616 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
617 {"or", "t,r,I", 0, (int) M_OR_I
, INSN_MACRO
, I1
},
618 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t
|RD_s
, I1
},
620 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
621 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
623 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b
, G3
|M1
|P4
},
624 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b
|RD_t
, I4
},
626 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
627 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
629 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D
|RD_S
|FP_D
, I4
},
630 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D
|RD_S
|FP_S
, I4
},
631 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I1
},
632 {"rem", "d,v,t", 0, (int) M_REM_3
, INSN_MACRO
, I1
},
633 {"rem", "d,v,I", 0, (int) M_REM_3I
, INSN_MACRO
, I1
},
634 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
, I1
},
635 {"remu", "d,v,t", 0, (int) M_REMU_3
, INSN_MACRO
, I1
},
636 {"remu", "d,v,I", 0, (int) M_REMU_3I
, INSN_MACRO
, I1
},
637 {"rfe", "", 0x42000010, 0xffffffff, 0, I1
|T3
},
638 {"rol", "d,v,t", 0, (int) M_ROL
, INSN_MACRO
, I1
},
639 {"rol", "d,v,I", 0, (int) M_ROL_I
, INSN_MACRO
, I1
},
640 {"ror", "d,v,t", 0, (int) M_ROR
, INSN_MACRO
, I1
},
641 {"ror", "d,v,I", 0, (int) M_ROR_I
, INSN_MACRO
, I1
},
642 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
643 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
644 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
645 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
646 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D
|RD_S
|FP_D
, I4
},
647 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D
|RD_S
|FP_S
, I4
},
648 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
649 {"sb", "t,A(b)", 0, (int) M_SB_AB
, INSN_MACRO
, I1
},
650 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM
|RD_t
|WR_t
|RD_b
, I2
},
651 {"sc", "t,A(b)", 0, (int) M_SC_AB
, INSN_MACRO
, I2
},
652 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM
|RD_t
|WR_t
|RD_b
, I3
},
653 {"scd", "t,A(b)", 0, (int) M_SCD_AB
, INSN_MACRO
, I3
},
654 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM
|RD_t
|RD_b
, I3
},
655 {"sd", "t,o(b)", 0, (int) M_SD_OB
, INSN_MACRO
, I1
},
656 {"sd", "t,A(b)", 0, (int) M_SD_AB
, INSN_MACRO
, I1
},
657 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP
, G2
|M1
},
658 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP
, G2
|M1
},
659 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP
, G2
|M1
},
660 {"sdbbp", "m", 0x7000003f, 0xfc00003f, TRAP
, P4
},
661 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_D
, I2
},
662 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_D
, I2
},
663 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB
, INSN_MACRO
, I2
},
664 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB
, INSN_MACRO
, I2
},
665 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM
|RD_C2
|RD_b
, I2
},
666 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB
, INSN_MACRO
, I2
},
667 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM
|RD_C3
|RD_b
, I2
},
668 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB
, INSN_MACRO
, I2
},
669 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_D
, I2
},
670 {"s.d", "T,o(b)", 0, (int) M_S_DOB
, INSN_MACRO
, I1
},
671 {"s.d", "T,A(b)", 0, (int) M_S_DAB
, INSN_MACRO
, I1
},
672 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM
|RD_t
|RD_b
, I3
},
673 {"sdl", "t,A(b)", 0, (int) M_SDL_AB
, INSN_MACRO
, I3
},
674 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM
|RD_t
|RD_b
, I3
},
675 {"sdr", "t,A(b)", 0, (int) M_SDR_AB
, INSN_MACRO
, I3
},
676 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM
|RD_S
|RD_t
|RD_b
, I4
},
677 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d
|RD_s
|RD_t
,L1
},
678 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d
|RD_s
|RD_t
,L1
},
679 {"seq", "d,v,t", 0, (int) M_SEQ
, INSN_MACRO
, I1
},
680 {"seq", "d,v,I", 0, (int) M_SEQ_I
, INSN_MACRO
, I1
},
681 {"sge", "d,v,t", 0, (int) M_SGE
, INSN_MACRO
, I1
},
682 {"sge", "d,v,I", 0, (int) M_SGE_I
, INSN_MACRO
, I1
},
683 {"sgeu", "d,v,t", 0, (int) M_SGEU
, INSN_MACRO
, I1
},
684 {"sgeu", "d,v,I", 0, (int) M_SGEU_I
, INSN_MACRO
, I1
},
685 {"sgt", "d,v,t", 0, (int) M_SGT
, INSN_MACRO
, I1
},
686 {"sgt", "d,v,I", 0, (int) M_SGT_I
, INSN_MACRO
, I1
},
687 {"sgtu", "d,v,t", 0, (int) M_SGTU
, INSN_MACRO
, I1
},
688 {"sgtu", "d,v,I", 0, (int) M_SGTU_I
, INSN_MACRO
, I1
},
689 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
690 {"sh", "t,A(b)", 0, (int) M_SH_AB
, INSN_MACRO
, I1
},
691 {"sle", "d,v,t", 0, (int) M_SLE
, INSN_MACRO
, I1
},
692 {"sle", "d,v,I", 0, (int) M_SLE_I
, INSN_MACRO
, I1
},
693 {"sleu", "d,v,t", 0, (int) M_SLEU
, INSN_MACRO
, I1
},
694 {"sleu", "d,v,I", 0, (int) M_SLEU_I
, INSN_MACRO
, I1
},
695 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
},
696 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
}, /* sllv */
697 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d
|RD_t
, I1
},
698 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
699 {"slt", "d,v,I", 0, (int) M_SLT_I
, INSN_MACRO
, I1
},
700 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t
|RD_s
, I1
},
701 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t
|RD_s
, I1
},
702 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
703 {"sltu", "d,v,I", 0, (int) M_SLTU_I
, INSN_MACRO
, I1
},
704 {"sne", "d,v,t", 0, (int) M_SNE
, INSN_MACRO
, I1
},
705 {"sne", "d,v,I", 0, (int) M_SNE_I
, INSN_MACRO
, I1
},
706 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
707 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
708 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
},
709 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
}, /* srav */
710 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d
|RD_t
, I1
},
711 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
},
712 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d
|RD_t
|RD_s
, I1
}, /* srlv */
713 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d
|RD_t
, I1
},
714 {"ssnop", "", 0x00000040, 0xffffffff, 0, M1
},
715 {"standby", "", 0x42000021, 0xffffffff, 0, V1
},
716 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
717 {"sub", "d,v,I", 0, (int) M_SUB_I
, INSN_MACRO
, I1
},
718 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I1
},
719 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_S
, I1
},
720 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D
|RD_S
|RD_T
|FP_D
, I5
},
721 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
722 {"subu", "d,v,I", 0, (int) M_SUBU_I
, INSN_MACRO
, I1
},
723 {"suspend", "", 0x42000022, 0xffffffff, 0, V1
},
724 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM
|RD_S
|RD_t
|RD_b
, I5
},
725 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
726 {"sw", "t,A(b)", 0, (int) M_SW_AB
, INSN_MACRO
, I1
},
727 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM
|RD_C0
|RD_b
, I1
},
728 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB
, INSN_MACRO
, I1
},
729 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_S
, I1
},
730 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_S
, I1
},
731 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
, I1
},
732 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
, I1
},
733 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM
|RD_T
|RD_b
|FP_S
, I1
}, /* swc1 */
734 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
, I1
},
735 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM
|RD_C2
|RD_b
, I1
},
736 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB
, INSN_MACRO
, I1
},
737 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM
|RD_C3
|RD_b
, I1
},
738 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB
, INSN_MACRO
, I1
},
739 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
740 {"swl", "t,A(b)", 0, (int) M_SWL_AB
, INSN_MACRO
, I1
},
741 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t
|RD_b
, I2
}, /* same */
742 {"scache", "t,A(b)", 0, (int) M_SWL_AB
, INSN_MACRO
, I2
}, /* as swl */
743 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM
|RD_t
|RD_b
, I1
},
744 {"swr", "t,A(b)", 0, (int) M_SWR_AB
, INSN_MACRO
, I1
},
745 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t
|RD_b
, I2
}, /* same */
746 {"invalidate", "t,A(b)",0, (int) M_SWR_AB
, INSN_MACRO
, I2
}, /* as swr */
747 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM
|RD_S
|RD_t
|RD_b
, I4
},
748 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC
, I2
|G1
},
749 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC
, I2
},
750 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC
, I2
},
751 {"syscall", "", 0x0000000c, 0xffffffff, TRAP
, I1
},
752 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP
, I1
},
753 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s
|TRAP
, I2
},
754 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
755 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
756 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* teqi */
757 {"teq", "s,I", 0, (int) M_TEQ_I
, INSN_MACRO
, I2
},
758 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s
|TRAP
, I2
},
759 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
760 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
761 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tgei */
762 {"tge", "s,I", 0, (int) M_TGE_I
, INSN_MACRO
, I2
},
763 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s
|TRAP
, I2
},
764 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
765 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
766 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tgeiu */
767 {"tgeu", "s,I", 0, (int) M_TGEU_I
, INSN_MACRO
, I2
},
768 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB
, I1
|M1
|P4
},
769 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB
, I1
|M1
|P4
},
770 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB
, I1
|M1
|P4
},
771 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB
, I1
|M1
|P4
},
772 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s
|TRAP
, I2
},
773 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
774 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
775 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tlti */
776 {"tlt", "s,I", 0, (int) M_TLT_I
, INSN_MACRO
, I2
},
777 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s
|TRAP
, I2
},
778 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
779 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
780 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tltiu */
781 {"tltu", "s,I", 0, (int) M_TLTU_I
, INSN_MACRO
, I2
},
782 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s
|TRAP
, I2
},
783 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s
|RD_t
|TRAP
, I2
},
784 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s
|RD_t
|TRAP
, I2
},
785 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s
|TRAP
, I2
}, /* tnei */
786 {"tne", "s,I", 0, (int) M_TNE_I
, INSN_MACRO
, I2
},
787 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D
|RD_S
|FP_D
, I3
},
788 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D
|RD_S
|FP_S
, I3
},
789 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
790 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D
|RD_S
|FP_D
, I2
},
791 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD
, INSN_MACRO
, I1
},
792 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
793 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D
|RD_S
|FP_S
, I2
},
794 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS
, INSN_MACRO
, I1
},
795 {"uld", "t,o(b)", 0, (int) M_ULD
, INSN_MACRO
, I3
},
796 {"uld", "t,A(b)", 0, (int) M_ULD_A
, INSN_MACRO
, I3
},
797 {"ulh", "t,o(b)", 0, (int) M_ULH
, INSN_MACRO
, I1
},
798 {"ulh", "t,A(b)", 0, (int) M_ULH_A
, INSN_MACRO
, I1
},
799 {"ulhu", "t,o(b)", 0, (int) M_ULHU
, INSN_MACRO
, I1
},
800 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A
, INSN_MACRO
, I1
},
801 {"ulw", "t,o(b)", 0, (int) M_ULW
, INSN_MACRO
, I1
},
802 {"ulw", "t,A(b)", 0, (int) M_ULW_A
, INSN_MACRO
, I1
},
803 {"usd", "t,o(b)", 0, (int) M_USD
, INSN_MACRO
, I3
},
804 {"usd", "t,A(b)", 0, (int) M_USD_A
, INSN_MACRO
, I3
},
805 {"ush", "t,o(b)", 0, (int) M_USH
, INSN_MACRO
, I1
},
806 {"ush", "t,A(b)", 0, (int) M_USH_A
, INSN_MACRO
, I1
},
807 {"usw", "t,o(b)", 0, (int) M_USW
, INSN_MACRO
, I1
},
808 {"usw", "t,A(b)", 0, (int) M_USW_A
, INSN_MACRO
, I1
},
809 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d
|RD_s
|RD_t
, I1
},
810 {"xor", "t,r,I", 0, (int) M_XOR_I
, INSN_MACRO
, I1
},
811 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t
|RD_s
, I1
},
812 {"wait", "", 0x42000020, 0xffffffff, TRAP
, I3
|M1
|P4
},
813 {"waiti", "", 0x42000020, 0xffffffff, TRAP
, L1
},
814 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM
|RD_b
, L1
},
815 /* No hazard protection on coprocessor instructions--they shouldn't
816 change the state of the processor and if they do it's up to the
817 user to put in nops as necessary. These are at the end so that the
818 disasembler recognizes more specific versions first. */
819 {"c0", "C", 0x42000000, 0xfe000000, 0, I1
},
820 {"c1", "C", 0x46000000, 0xfe000000, 0, I1
},
821 {"c2", "C", 0x4a000000, 0xfe000000, 0, I1
},
822 {"c3", "C", 0x4e000000, 0xfe000000, 0, I1
},
823 {"cop0", "C", 0, (int) M_COP0
, INSN_MACRO
, I1
},
824 {"cop1", "C", 0, (int) M_COP1
, INSN_MACRO
, I1
},
825 {"cop2", "C", 0, (int) M_COP2
, INSN_MACRO
, I1
},
826 {"cop3", "C", 0, (int) M_COP3
, INSN_MACRO
, I1
},
828 /* Conflicts with the 4650's "mul" instruction. Nobody's using the
829 4010 any more, so move this insn out of the way. If the object
830 format gave us more info, we could do this right. */
831 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t
|RD_s
,L1
},
834 #define MIPS_NUM_OPCODES \
835 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
836 const int bfd_mips_num_builtin_opcodes
= MIPS_NUM_OPCODES
;
838 /* const removed from the following to allow for dynamic extensions to the
839 * built-in instruction set. */
840 struct mips_opcode
*mips_opcodes
=
841 (struct mips_opcode
*) mips_builtin_opcodes
;
842 int bfd_mips_num_opcodes
= MIPS_NUM_OPCODES
;
843 #undef MIPS_NUM_OPCODES
