opcodes/m32r-ibld.c

   1 /* Instruction building/extraction support for m32r. -*- C -*-
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
   4 - the resultant file is machine generated, cgen-ibld.in isn't
   5
   6 Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  25    Keep that in mind.  */
  26
  27 #include "sysdep.h"
  28 #include <ctype.h>
  29 #include <stdio.h>
  30 #include "ansidecl.h"
  31 #include "dis-asm.h"
  32 #include "bfd.h"
  33 #include "symcat.h"
  34 #include "m32r-desc.h"
  35 #include "m32r-opc.h"
  36 #include "opintl.h"
  37
  38 #undef min
  39 #define min(a,b) ((a) < (b) ? (a) : (b))
  40 #undef max
  41 #define max(a,b) ((a) > (b) ? (a) : (b))
  42
  43 /* Used by the ifield rtx function.  */
  44 #define FLD(f) (fields->f)
  45
  46 static const char * insert_normal
  47      PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
  48               unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
  49 static const char * insert_insn_normal
  50      PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
  51               CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
  52
  53 static int extract_normal
  54      PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
  55               unsigned int, unsigned int, unsigned int, unsigned int,
  56               unsigned int, unsigned int, bfd_vma, long *));
  57 static int extract_insn_normal
  58      PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
  59               CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
  60 static void put_insn_int_value
  61      PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
  62
  63 \f
  64 /* Operand insertion.  */
  65
  66 #if ! CGEN_INT_INSN_P
  67
  68 /* Subroutine of insert_normal.  */
  69
  70 static CGEN_INLINE void
  71 insert_1 (cd, value, start, length, word_length, bufp)
  72      CGEN_CPU_DESC cd;
  73      unsigned long value;
  74      int start,length,word_length;
  75      unsigned char *bufp;
  76 {
  77   unsigned long x,mask;
  78   int shift;
  79   int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
  80
  81   switch (word_length)
  82     {
  83     case 8:
  84       x = *bufp;
  85       break;
  86     case 16:
  87       if (big_p)
  88         x = bfd_getb16 (bufp);
  89       else
  90         x = bfd_getl16 (bufp);
  91       break;
  92     case 24:
  93       /* ??? This may need reworking as these cases don't necessarily
  94          want the first byte and the last two bytes handled like this.  */
  95       if (big_p)
  96         x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
  97       else
  98         x = bfd_getl16 (bufp) | (bufp[2] << 16);
  99       break;
 100     case 32:
 101       if (big_p)
 102         x = bfd_getb32 (bufp);
 103       else
 104         x = bfd_getl32 (bufp);
 105       break;
 106     default :
 107       abort ();
 108     }
 109
 110   /* Written this way to avoid undefined behaviour.  */
 111   mask = (((1L << (length - 1)) - 1) << 1) | 1;
 112   if (CGEN_INSN_LSB0_P)
 113     shift = (start + 1) - length;
 114   else
 115     shift = (word_length - (start + length));
 116   x = (x & ~(mask << shift)) | ((value & mask) << shift);
 117
 118   switch (word_length)
 119     {
 120     case 8:
 121       *bufp = x;
 122       break;
 123     case 16:
 124       if (big_p)
 125         bfd_putb16 (x, bufp);
 126       else
 127         bfd_putl16 (x, bufp);
 128       break;
 129     case 24:
 130       /* ??? This may need reworking as these cases don't necessarily
 131          want the first byte and the last two bytes handled like this.  */
 132       if (big_p)
 133         {
 134           bufp[0] = x >> 16;
 135           bfd_putb16 (x, bufp + 1);
 136         }
 137       else
 138         {
 139           bfd_putl16 (x, bufp);
 140           bufp[2] = x >> 16;
 141         }
 142       break;
 143     case 32:
 144       if (big_p)
 145         bfd_putb32 (x, bufp);
 146       else
 147         bfd_putl32 (x, bufp);
 148       break;
 149     default :
 150       abort ();
 151     }
 152 }
 153
 154 #endif /* ! CGEN_INT_INSN_P */
 155
 156 /* Default insertion routine.
 157
 158    ATTRS is a mask of the boolean attributes.
 159    WORD_OFFSET is the offset in bits from the start of the insn of the value.
 160    WORD_LENGTH is the length of the word in bits in which the value resides.
 161    START is the starting bit number in the word, architecture origin.
 162    LENGTH is the length of VALUE in bits.
 163    TOTAL_LENGTH is the total length of the insn in bits.
 164
 165    The result is an error message or NULL if success.  */
 166
 167 /* ??? This duplicates functionality with bfd's howto table and
 168    bfd_install_relocation.  */
 169 /* ??? This doesn't handle bfd_vma's.  Create another function when
 170    necessary.  */
 171
 172 static const char *
 173 insert_normal (cd, value, attrs, word_offset, start, length, word_length,
 174                total_length, buffer)
 175      CGEN_CPU_DESC cd;
 176      long value;
 177      unsigned int attrs;
 178      unsigned int word_offset, start, length, word_length, total_length;
 179      CGEN_INSN_BYTES_PTR buffer;
 180 {
 181   static char errbuf[100];
 182   /* Written this way to avoid undefined behaviour.  */
 183   unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
 184
 185   /* If LENGTH is zero, this operand doesn't contribute to the value.  */
 186   if (length == 0)
 187     return NULL;
 188
 189 #if 0
 190   if (CGEN_INT_INSN_P
 191       && word_offset != 0)
 192     abort ();
 193 #endif
 194
 195   if (word_length > 32)
 196     abort ();
 197
 198   /* For architectures with insns smaller than the base-insn-bitsize,
 199      word_length may be too big.  */
 200   if (cd->min_insn_bitsize < cd->base_insn_bitsize)
 201     {
 202       if (word_offset == 0
 203           && word_length > total_length)
 204         word_length = total_length;
 205     }
 206
 207   /* Ensure VALUE will fit.  */
 208   if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
 209     {
 210       unsigned long maxval = mask;
 211
 212       if ((unsigned long) value > maxval)
 213         {
 214           /* xgettext:c-format */
 215           sprintf (errbuf,
 216                    _("operand out of range (%lu not between 0 and %lu)"),
 217                    value, maxval);
 218           return errbuf;
 219         }
 220     }
 221   else
 222     {
 223       if (! cgen_signed_overflow_ok_p (cd))
 224         {
 225           long minval = - (1L << (length - 1));
 226           long maxval =   (1L << (length - 1)) - 1;
 227
 228           if (value < minval || value > maxval)
 229             {
 230               sprintf
 231                 /* xgettext:c-format */
 232                 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
 233                  value, minval, maxval);
 234               return errbuf;
 235             }
 236         }
 237     }
 238
 239 #if CGEN_INT_INSN_P
 240
 241   {
 242     int shift;
 243
 244     if (CGEN_INSN_LSB0_P)
 245       shift = (word_offset + start + 1) - length;
 246     else
 247       shift = total_length - (word_offset + start + length);
 248     *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
 249   }
 250
 251 #else /* ! CGEN_INT_INSN_P */
 252
 253   {
 254     unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
 255
 256     insert_1 (cd, value, start, length, word_length, bufp);
 257   }
 258
 259 #endif /* ! CGEN_INT_INSN_P */
 260
 261   return NULL;
 262 }
 263
 264 /* Default insn builder (insert handler).
 265    The instruction is recorded in CGEN_INT_INSN_P byte order
 266    (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is
 267    recorded in host byte order, otherwise BUFFER is an array of bytes and the
 268    value is recorded in target byte order).
 269    The result is an error message or NULL if success.  */
 270
 271 static const char *
 272 insert_insn_normal (cd, insn, fields, buffer, pc)
 273      CGEN_CPU_DESC cd;
 274      const CGEN_INSN * insn;
 275      CGEN_FIELDS * fields;
 276      CGEN_INSN_BYTES_PTR buffer;
 277      bfd_vma pc;
 278 {
 279   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 280   unsigned long value;
 281   const unsigned char * syn;
 282
 283   CGEN_INIT_INSERT (cd);
 284   value = CGEN_INSN_BASE_VALUE (insn);
 285
 286   /* If we're recording insns as numbers (rather than a string of bytes),
 287      target byte order handling is deferred until later.  */
 288
 289 #if CGEN_INT_INSN_P
 290
 291   put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
 292                       CGEN_FIELDS_BITSIZE (fields), value);
 293
 294 #else
 295
 296   cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
 297                                         CGEN_FIELDS_BITSIZE (fields)),
 298                        value);
 299
 300 #endif /* ! CGEN_INT_INSN_P */
 301
 302   /* ??? It would be better to scan the format's fields.
 303      Still need to be able to insert a value based on the operand though;
 304      e.g. storing a branch displacement that got resolved later.
 305      Needs more thought first.  */
 306
 307   for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn)
 308     {
 309       const char *errmsg;
 310
 311       if (CGEN_SYNTAX_CHAR_P (* syn))
 312         continue;
 313
 314       errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
 315                                        fields, buffer, pc);
 316       if (errmsg)
 317         return errmsg;
 318     }
 319
 320   return NULL;
 321 }
 322
 323 /* Cover function to store an insn value into an integral insn.  Must go here
 324  because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 325
 326 static void
 327 put_insn_int_value (cd, buf, length, insn_length, value)
 328      CGEN_CPU_DESC cd;
 329      CGEN_INSN_BYTES_PTR buf;
 330      int length;
 331      int insn_length;
 332      CGEN_INSN_INT value;
 333 {
 334   /* For architectures with insns smaller than the base-insn-bitsize,
 335      length may be too big.  */
 336   if (length > insn_length)
 337     *buf = value;
 338   else
 339     {
 340       int shift = insn_length - length;
 341       /* Written this way to avoid undefined behaviour.  */
 342       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
 343       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
 344     }
 345 }
 346 \f
 347 /* Operand extraction.  */
 348
 349 #if ! CGEN_INT_INSN_P
 350
 351 /* Subroutine of extract_normal.
 352    Ensure sufficient bytes are cached in EX_INFO.
 353    OFFSET is the offset in bytes from the start of the insn of the value.
 354    BYTES is the length of the needed value.
 355    Returns 1 for success, 0 for failure.  */
 356
 357 static CGEN_INLINE int
 358 fill_cache (cd, ex_info, offset, bytes, pc)
 359      CGEN_CPU_DESC cd;
 360      CGEN_EXTRACT_INFO *ex_info;
 361      int offset, bytes;
 362      bfd_vma pc;
 363 {
 364   /* It's doubtful that the middle part has already been fetched so
 365      we don't optimize that case.  kiss.  */
 366   int mask;
 367   disassemble_info *info = (disassemble_info *) ex_info->dis_info;
 368
 369   /* First do a quick check.  */
 370   mask = (1 << bytes) - 1;
 371   if (((ex_info->valid >> offset) & mask) == mask)
 372     return 1;
 373
 374   /* Search for the first byte we need to read.  */
 375   for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
 376     if (! (mask & ex_info->valid))
 377       break;
 378
 379   if (bytes)
 380     {
 381       int status;
 382
 383       pc += offset;
 384       status = (*info->read_memory_func)
 385         (pc, ex_info->insn_bytes + offset, bytes, info);
 386
 387       if (status != 0)
 388         {
 389           (*info->memory_error_func) (status, pc, info);
 390           return 0;
 391         }
 392
 393       ex_info->valid |= ((1 << bytes) - 1) << offset;
 394     }
 395
 396   return 1;
 397 }
 398
 399 /* Subroutine of extract_normal.  */
 400
 401 static CGEN_INLINE long
 402 extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
 403      CGEN_CPU_DESC cd;
 404      CGEN_EXTRACT_INFO *ex_info;
 405      int start,length,word_length;
 406      unsigned char *bufp;
 407      bfd_vma pc;
 408 {
 409   unsigned long x,mask;
 410   int shift;
 411   int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
 412
 413   switch (word_length)
 414     {
 415     case 8:
 416       x = *bufp;
 417       break;
 418     case 16:
 419       if (big_p)
 420         x = bfd_getb16 (bufp);
 421       else
 422         x = bfd_getl16 (bufp);
 423       break;
 424     case 24:
 425       /* ??? This may need reworking as these cases don't necessarily
 426          want the first byte and the last two bytes handled like this.  */
 427       if (big_p)
 428         x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
 429       else
 430         x = bfd_getl16 (bufp) | (bufp[2] << 16);
 431       break;
 432     case 32:
 433       if (big_p)
 434         x = bfd_getb32 (bufp);
 435       else
 436         x = bfd_getl32 (bufp);
 437       break;
 438     default :
 439       abort ();
 440     }
 441
 442   /* Written this way to avoid undefined behaviour.  */
 443   mask = (((1L << (length - 1)) - 1) << 1) | 1;
 444   if (CGEN_INSN_LSB0_P)
 445     shift = (start + 1) - length;
 446   else
 447     shift = (word_length - (start + length));
 448   return (x >> shift) & mask;
 449 }
 450
 451 #endif /* ! CGEN_INT_INSN_P */
 452
 453 /* Default extraction routine.
 454
 455    INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
 456    or sometimes less for cases like the m32r where the base insn size is 32
 457    but some insns are 16 bits.
 458    ATTRS is a mask of the boolean attributes.  We only need `SIGNED',
 459    but for generality we take a bitmask of all of them.
 460    WORD_OFFSET is the offset in bits from the start of the insn of the value.
 461    WORD_LENGTH is the length of the word in bits in which the value resides.
 462    START is the starting bit number in the word, architecture origin.
 463    LENGTH is the length of VALUE in bits.
 464    TOTAL_LENGTH is the total length of the insn in bits.
 465
 466    Returns 1 for success, 0 for failure.  */
 467
 468 /* ??? The return code isn't properly used.  wip.  */
 469
 470 /* ??? This doesn't handle bfd_vma's.  Create another function when
 471    necessary.  */
 472
 473 static int
 474 extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
 475                 word_length, total_length, pc, valuep)
 476      CGEN_CPU_DESC cd;
 477 #if ! CGEN_INT_INSN_P
 478      CGEN_EXTRACT_INFO *ex_info;
 479 #else
 480      CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
 481 #endif
 482      CGEN_INSN_INT insn_value;
 483      unsigned int attrs;
 484      unsigned int word_offset, start, length, word_length, total_length;
 485 #if ! CGEN_INT_INSN_P
 486      bfd_vma pc;
 487 #else
 488      bfd_vma pc ATTRIBUTE_UNUSED;
 489 #endif
 490      long *valuep;
 491 {
 492   CGEN_INSN_INT value;
 493
 494   /* If LENGTH is zero, this operand doesn't contribute to the value
 495      so give it a standard value of zero.  */
 496   if (length == 0)
 497     {
 498       *valuep = 0;
 499       return 1;
 500     }
 501
 502 #if 0
 503   if (CGEN_INT_INSN_P
 504       && word_offset != 0)
 505     abort ();
 506 #endif
 507
 508   if (word_length > 32)
 509     abort ();
 510
 511   /* For architectures with insns smaller than the insn-base-bitsize,
 512      word_length may be too big.  */
 513   if (cd->min_insn_bitsize < cd->base_insn_bitsize)
 514     {
 515       if (word_offset == 0
 516           && word_length > total_length)
 517         word_length = total_length;
 518     }
 519
 520   /* Does the value reside in INSN_VALUE?  */
 521
 522   if (CGEN_INT_INSN_P || word_offset == 0)
 523     {
 524       /* Written this way to avoid undefined behaviour.  */
 525       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
 526
 527       if (CGEN_INSN_LSB0_P)
 528         value = insn_value >> ((word_offset + start + 1) - length);
 529       else
 530         value = insn_value >> (total_length - ( word_offset + start + length));
 531       value &= mask;
 532       /* sign extend? */
 533       if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
 534           && (value & (1L << (length - 1))))
 535         value |= ~mask;
 536     }
 537
 538 #if ! CGEN_INT_INSN_P
 539
 540   else
 541     {
 542       unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
 543
 544       if (word_length > 32)
 545         abort ();
 546
 547       if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
 548         return 0;
 549
 550       value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
 551     }
 552
 553 #endif /* ! CGEN_INT_INSN_P */
 554
 555   *valuep = value;
 556
 557   return 1;
 558 }
 559
 560 /* Default insn extractor.
 561
 562    INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
 563    The extracted fields are stored in FIELDS.
 564    EX_INFO is used to handle reading variable length insns.
 565    Return the length of the insn in bits, or 0 if no match,
 566    or -1 if an error occurs fetching data (memory_error_func will have
 567    been called).  */
 568
 569 static int
 570 extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
 571      CGEN_CPU_DESC cd;
 572      const CGEN_INSN *insn;
 573      CGEN_EXTRACT_INFO *ex_info;
 574      CGEN_INSN_INT insn_value;
 575      CGEN_FIELDS *fields;
 576      bfd_vma pc;
 577 {
 578   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 579   const unsigned char *syn;
 580
 581   CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
 582
 583   CGEN_INIT_EXTRACT (cd);
 584
 585   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 586     {
 587       int length;
 588
 589       if (CGEN_SYNTAX_CHAR_P (*syn))
 590         continue;
 591
 592       length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
 593                                         ex_info, insn_value, fields, pc);
 594       if (length <= 0)
 595         return length;
 596     }
 597
 598   /* We recognized and successfully extracted this insn.  */
 599   return CGEN_INSN_BITSIZE (insn);
 600 }
 601 \f
 602 /* machine generated code added here */
 603
 604 /* Main entry point for operand insertion.
 605
 606    This function is basically just a big switch statement.  Earlier versions
 607    used tables to look up the function to use, but
 608    - if the table contains both assembler and disassembler functions then
 609      the disassembler contains much of the assembler and vice-versa,
 610    - there's a lot of inlining possibilities as things grow,
 611    - using a switch statement avoids the function call overhead.
 612
 613    This function could be moved into `parse_insn_normal', but keeping it
 614    separate makes clear the interface between `parse_insn_normal' and each of
 615    the handlers.  It's also needed by GAS to insert operands that couldn't be
 616    resolved during parsing.
 617 */
 618
 619 const char *
 620 m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 621      CGEN_CPU_DESC cd;
 622      int opindex;
 623      CGEN_FIELDS * fields;
 624      CGEN_INSN_BYTES_PTR buffer;
 625      bfd_vma pc;
 626 {
 627   const char * errmsg = NULL;
 628   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
 629
 630   switch (opindex)
 631     {
 632     case M32R_OPERAND_ACC :
 633       errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
 634       break;
 635     case M32R_OPERAND_ACCD :
 636       errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
 637       break;
 638     case M32R_OPERAND_ACCS :
 639       errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
 640       break;
 641     case M32R_OPERAND_DCR :
 642       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
 643       break;
 644     case M32R_OPERAND_DISP16 :
 645       {
 646         long value = fields->f_disp16;
 647         value = ((int) (((value) - (pc))) >> (2));
 648         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
 649       }
 650       break;
 651     case M32R_OPERAND_DISP24 :
 652       {
 653         long value = fields->f_disp24;
 654         value = ((int) (((value) - (pc))) >> (2));
 655         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
 656       }
 657       break;
 658     case M32R_OPERAND_DISP8 :
 659       {
 660         long value = fields->f_disp8;
 661         value = ((int) (((value) - (((pc) & (-4))))) >> (2));
 662         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
 663       }
 664       break;
 665     case M32R_OPERAND_DR :
 666       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
 667       break;
 668     case M32R_OPERAND_HASH :
 669       break;
 670     case M32R_OPERAND_HI16 :
 671       errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
 672       break;
 673     case M32R_OPERAND_IMM1 :
 674       {
 675         long value = fields->f_imm1;
 676         value = ((value) - (1));
 677         errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
 678       }
 679       break;
 680     case M32R_OPERAND_SCR :
 681       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
 682       break;
 683     case M32R_OPERAND_SIMM16 :
 684       errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
 685       break;
 686     case M32R_OPERAND_SIMM8 :
 687       errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
 688       break;
 689     case M32R_OPERAND_SLO16 :
 690       errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
 691       break;
 692     case M32R_OPERAND_SR :
 693       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
 694       break;
 695     case M32R_OPERAND_SRC1 :
 696       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
 697       break;
 698     case M32R_OPERAND_SRC2 :
 699       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
 700       break;
 701     case M32R_OPERAND_UIMM16 :
 702       errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
 703       break;
 704     case M32R_OPERAND_UIMM24 :
 705       errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
 706       break;
 707     case M32R_OPERAND_UIMM4 :
 708       errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
 709       break;
 710     case M32R_OPERAND_UIMM5 :
 711       errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
 712       break;
 713     case M32R_OPERAND_ULO16 :
 714       errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
 715       break;
 716
 717     default :
 718       /* xgettext:c-format */
 719       fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
 720                opindex);
 721       abort ();
 722   }
 723
 724   return errmsg;
 725 }
 726
 727 /* Main entry point for operand extraction.
 728    The result is <= 0 for error, >0 for success.
 729    ??? Actual values aren't well defined right now.
 730
 731    This function is basically just a big switch statement.  Earlier versions
 732    used tables to look up the function to use, but
 733    - if the table contains both assembler and disassembler functions then
 734      the disassembler contains much of the assembler and vice-versa,
 735    - there's a lot of inlining possibilities as things grow,
 736    - using a switch statement avoids the function call overhead.
 737
 738    This function could be moved into `print_insn_normal', but keeping it
 739    separate makes clear the interface between `print_insn_normal' and each of
 740    the handlers.
 741 */
 742
 743 int
 744 m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
 745      CGEN_CPU_DESC cd;
 746      int opindex;
 747      CGEN_EXTRACT_INFO *ex_info;
 748      CGEN_INSN_INT insn_value;
 749      CGEN_FIELDS * fields;
 750      bfd_vma pc;
 751 {
 752   /* Assume success (for those operands that are nops).  */
 753   int length = 1;
 754   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
 755
 756   switch (opindex)
 757     {
 758     case M32R_OPERAND_ACC :
 759       length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
 760       break;
 761     case M32R_OPERAND_ACCD :
 762       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
 763       break;
 764     case M32R_OPERAND_ACCS :
 765       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
 766       break;
 767     case M32R_OPERAND_DCR :
 768       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
 769       break;
 770     case M32R_OPERAND_DISP16 :
 771       {
 772         long value;
 773         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
 774         value = ((((value) << (2))) + (pc));
 775         fields->f_disp16 = value;
 776       }
 777       break;
 778     case M32R_OPERAND_DISP24 :
 779       {
 780         long value;
 781         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
 782         value = ((((value) << (2))) + (pc));
 783         fields->f_disp24 = value;
 784       }
 785       break;
 786     case M32R_OPERAND_DISP8 :
 787       {
 788         long value;
 789         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
 790         value = ((((value) << (2))) + (((pc) & (-4))));
 791         fields->f_disp8 = value;
 792       }
 793       break;
 794     case M32R_OPERAND_DR :
 795       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
 796       break;
 797     case M32R_OPERAND_HASH :
 798       break;
 799     case M32R_OPERAND_HI16 :
 800       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
 801       break;
 802     case M32R_OPERAND_IMM1 :
 803       {
 804         long value;
 805         length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
 806         value = ((value) + (1));
 807         fields->f_imm1 = value;
 808       }
 809       break;
 810     case M32R_OPERAND_SCR :
 811       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
 812       break;
 813     case M32R_OPERAND_SIMM16 :
 814       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
 815       break;
 816     case M32R_OPERAND_SIMM8 :
 817       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
 818       break;
 819     case M32R_OPERAND_SLO16 :
 820       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
 821       break;
 822     case M32R_OPERAND_SR :
 823       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
 824       break;
 825     case M32R_OPERAND_SRC1 :
 826       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
 827       break;
 828     case M32R_OPERAND_SRC2 :
 829       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
 830       break;
 831     case M32R_OPERAND_UIMM16 :
 832       length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
 833       break;
 834     case M32R_OPERAND_UIMM24 :
 835       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
 836       break;
 837     case M32R_OPERAND_UIMM4 :
 838       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
 839       break;
 840     case M32R_OPERAND_UIMM5 :
 841       length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
 842       break;
 843     case M32R_OPERAND_ULO16 :
 844       length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
 845       break;
 846
 847     default :
 848       /* xgettext:c-format */
 849       fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
 850                opindex);
 851       abort ();
 852     }
 853
 854   return length;
 855 }
 856
 857 cgen_insert_fn * const m32r_cgen_insert_handlers[] =
 858 {
 859   insert_insn_normal,
 860 };
 861
 862 cgen_extract_fn * const m32r_cgen_extract_handlers[] =
 863 {
 864   extract_insn_normal,
 865 };
 866
 867 /* Getting values from cgen_fields is handled by a collection of functions.
 868    They are distinguished by the type of the VALUE argument they return.
 869    TODO: floating point, inlining support, remove cases where result type
 870    not appropriate.  */
 871
 872 int
 873 m32r_cgen_get_int_operand (cd, opindex, fields)
 874      CGEN_CPU_DESC cd;
 875      int opindex;
 876      const CGEN_FIELDS * fields;
 877 {
 878   int value;
 879
 880   switch (opindex)
 881     {
 882     case M32R_OPERAND_ACC :
 883       value = fields->f_acc;
 884       break;
 885     case M32R_OPERAND_ACCD :
 886       value = fields->f_accd;
 887       break;
 888     case M32R_OPERAND_ACCS :
 889       value = fields->f_accs;
 890       break;
 891     case M32R_OPERAND_DCR :
 892       value = fields->f_r1;
 893       break;
 894     case M32R_OPERAND_DISP16 :
 895       value = fields->f_disp16;
 896       break;
 897     case M32R_OPERAND_DISP24 :
 898       value = fields->f_disp24;
 899       break;
 900     case M32R_OPERAND_DISP8 :
 901       value = fields->f_disp8;
 902       break;
 903     case M32R_OPERAND_DR :
 904       value = fields->f_r1;
 905       break;
 906     case M32R_OPERAND_HASH :
 907       value = 0;
 908       break;
 909     case M32R_OPERAND_HI16 :
 910       value = fields->f_hi16;
 911       break;
 912     case M32R_OPERAND_IMM1 :
 913       value = fields->f_imm1;
 914       break;
 915     case M32R_OPERAND_SCR :
 916       value = fields->f_r2;
 917       break;
 918     case M32R_OPERAND_SIMM16 :
 919       value = fields->f_simm16;
 920       break;
 921     case M32R_OPERAND_SIMM8 :
 922       value = fields->f_simm8;
 923       break;
 924     case M32R_OPERAND_SLO16 :
 925       value = fields->f_simm16;
 926       break;
 927     case M32R_OPERAND_SR :
 928       value = fields->f_r2;
 929       break;
 930     case M32R_OPERAND_SRC1 :
 931       value = fields->f_r1;
 932       break;
 933     case M32R_OPERAND_SRC2 :
 934       value = fields->f_r2;
 935       break;
 936     case M32R_OPERAND_UIMM16 :
 937       value = fields->f_uimm16;
 938       break;
 939     case M32R_OPERAND_UIMM24 :
 940       value = fields->f_uimm24;
 941       break;
 942     case M32R_OPERAND_UIMM4 :
 943       value = fields->f_uimm4;
 944       break;
 945     case M32R_OPERAND_UIMM5 :
 946       value = fields->f_uimm5;
 947       break;
 948     case M32R_OPERAND_ULO16 :
 949       value = fields->f_uimm16;
 950       break;
 951
 952     default :
 953       /* xgettext:c-format */
 954       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
 955                        opindex);
 956       abort ();
 957   }
 958
 959   return value;
 960 }
 961
 962 bfd_vma
 963 m32r_cgen_get_vma_operand (cd, opindex, fields)
 964      CGEN_CPU_DESC cd;
 965      int opindex;
 966      const CGEN_FIELDS * fields;
 967 {
 968   bfd_vma value;
 969
 970   switch (opindex)
 971     {
 972     case M32R_OPERAND_ACC :
 973       value = fields->f_acc;
 974       break;
 975     case M32R_OPERAND_ACCD :
 976       value = fields->f_accd;
 977       break;
 978     case M32R_OPERAND_ACCS :
 979       value = fields->f_accs;
 980       break;
 981     case M32R_OPERAND_DCR :
 982       value = fields->f_r1;
 983       break;
 984     case M32R_OPERAND_DISP16 :
 985       value = fields->f_disp16;
 986       break;
 987     case M32R_OPERAND_DISP24 :
 988       value = fields->f_disp24;
 989       break;
 990     case M32R_OPERAND_DISP8 :
 991       value = fields->f_disp8;
 992       break;
 993     case M32R_OPERAND_DR :
 994       value = fields->f_r1;
 995       break;
 996     case M32R_OPERAND_HASH :
 997       value = 0;
 998       break;
 999     case M32R_OPERAND_HI16 :
1000       value = fields->f_hi16;
1001       break;
1002     case M32R_OPERAND_IMM1 :
1003       value = fields->f_imm1;
1004       break;
1005     case M32R_OPERAND_SCR :
1006       value = fields->f_r2;
1007       break;
1008     case M32R_OPERAND_SIMM16 :
1009       value = fields->f_simm16;
1010       break;
1011     case M32R_OPERAND_SIMM8 :
1012       value = fields->f_simm8;
1013       break;
1014     case M32R_OPERAND_SLO16 :
1015       value = fields->f_simm16;
1016       break;
1017     case M32R_OPERAND_SR :
1018       value = fields->f_r2;
1019       break;
1020     case M32R_OPERAND_SRC1 :
1021       value = fields->f_r1;
1022       break;
1023     case M32R_OPERAND_SRC2 :
1024       value = fields->f_r2;
1025       break;
1026     case M32R_OPERAND_UIMM16 :
1027       value = fields->f_uimm16;
1028       break;
1029     case M32R_OPERAND_UIMM24 :
1030       value = fields->f_uimm24;
1031       break;
1032     case M32R_OPERAND_UIMM4 :
1033       value = fields->f_uimm4;
1034       break;
1035     case M32R_OPERAND_UIMM5 :
1036       value = fields->f_uimm5;
1037       break;
1038     case M32R_OPERAND_ULO16 :
1039       value = fields->f_uimm16;
1040       break;
1041
1042     default :
1043       /* xgettext:c-format */
1044       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
1045                        opindex);
1046       abort ();
1047   }
1048
1049   return value;
1050 }
1051
1052 /* Stuffing values in cgen_fields is handled by a collection of functions.
1053    They are distinguished by the type of the VALUE argument they accept.
1054    TODO: floating point, inlining support, remove cases where argument type
1055    not appropriate.  */
1056
1057 void
1058 m32r_cgen_set_int_operand (cd, opindex, fields, value)
1059      CGEN_CPU_DESC cd;
1060      int opindex;
1061      CGEN_FIELDS * fields;
1062      int value;
1063 {
1064   switch (opindex)
1065     {
1066     case M32R_OPERAND_ACC :
1067       fields->f_acc = value;
1068       break;
1069     case M32R_OPERAND_ACCD :
1070       fields->f_accd = value;
1071       break;
1072     case M32R_OPERAND_ACCS :
1073       fields->f_accs = value;
1074       break;
1075     case M32R_OPERAND_DCR :
1076       fields->f_r1 = value;
1077       break;
1078     case M32R_OPERAND_DISP16 :
1079       fields->f_disp16 = value;
1080       break;
1081     case M32R_OPERAND_DISP24 :
1082       fields->f_disp24 = value;
1083       break;
1084     case M32R_OPERAND_DISP8 :
1085       fields->f_disp8 = value;
1086       break;
1087     case M32R_OPERAND_DR :
1088       fields->f_r1 = value;
1089       break;
1090     case M32R_OPERAND_HASH :
1091       break;
1092     case M32R_OPERAND_HI16 :
1093       fields->f_hi16 = value;
1094       break;
1095     case M32R_OPERAND_IMM1 :
1096       fields->f_imm1 = value;
1097       break;
1098     case M32R_OPERAND_SCR :
1099       fields->f_r2 = value;
1100       break;
1101     case M32R_OPERAND_SIMM16 :
1102       fields->f_simm16 = value;
1103       break;
1104     case M32R_OPERAND_SIMM8 :
1105       fields->f_simm8 = value;
1106       break;
1107     case M32R_OPERAND_SLO16 :
1108       fields->f_simm16 = value;
1109       break;
1110     case M32R_OPERAND_SR :
1111       fields->f_r2 = value;
1112       break;
1113     case M32R_OPERAND_SRC1 :
1114       fields->f_r1 = value;
1115       break;
1116     case M32R_OPERAND_SRC2 :
1117       fields->f_r2 = value;
1118       break;
1119     case M32R_OPERAND_UIMM16 :
1120       fields->f_uimm16 = value;
1121       break;
1122     case M32R_OPERAND_UIMM24 :
1123       fields->f_uimm24 = value;
1124       break;
1125     case M32R_OPERAND_UIMM4 :
1126       fields->f_uimm4 = value;
1127       break;
1128     case M32R_OPERAND_UIMM5 :
1129       fields->f_uimm5 = value;
1130       break;
1131     case M32R_OPERAND_ULO16 :
1132       fields->f_uimm16 = value;
1133       break;
1134
1135     default :
1136       /* xgettext:c-format */
1137       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
1138                        opindex);
1139       abort ();
1140   }
1141 }
1142
1143 void
1144 m32r_cgen_set_vma_operand (cd, opindex, fields, value)
1145      CGEN_CPU_DESC cd;
1146      int opindex;
1147      CGEN_FIELDS * fields;
1148      bfd_vma value;
1149 {
1150   switch (opindex)
1151     {
1152     case M32R_OPERAND_ACC :
1153       fields->f_acc = value;
1154       break;
1155     case M32R_OPERAND_ACCD :
1156       fields->f_accd = value;
1157       break;
1158     case M32R_OPERAND_ACCS :
1159       fields->f_accs = value;
1160       break;
1161     case M32R_OPERAND_DCR :
1162       fields->f_r1 = value;
1163       break;
1164     case M32R_OPERAND_DISP16 :
1165       fields->f_disp16 = value;
1166       break;
1167     case M32R_OPERAND_DISP24 :
1168       fields->f_disp24 = value;
1169       break;
1170     case M32R_OPERAND_DISP8 :
1171       fields->f_disp8 = value;
1172       break;
1173     case M32R_OPERAND_DR :
1174       fields->f_r1 = value;
1175       break;
1176     case M32R_OPERAND_HASH :
1177       break;
1178     case M32R_OPERAND_HI16 :
1179       fields->f_hi16 = value;
1180       break;
1181     case M32R_OPERAND_IMM1 :
1182       fields->f_imm1 = value;
1183       break;
1184     case M32R_OPERAND_SCR :
1185       fields->f_r2 = value;
1186       break;
1187     case M32R_OPERAND_SIMM16 :
1188       fields->f_simm16 = value;
1189       break;
1190     case M32R_OPERAND_SIMM8 :
1191       fields->f_simm8 = value;
1192       break;
1193     case M32R_OPERAND_SLO16 :
1194       fields->f_simm16 = value;
1195       break;
1196     case M32R_OPERAND_SR :
1197       fields->f_r2 = value;
1198       break;
1199     case M32R_OPERAND_SRC1 :
1200       fields->f_r1 = value;
1201       break;
1202     case M32R_OPERAND_SRC2 :
1203       fields->f_r2 = value;
1204       break;
1205     case M32R_OPERAND_UIMM16 :
1206       fields->f_uimm16 = value;
1207       break;
1208     case M32R_OPERAND_UIMM24 :
1209       fields->f_uimm24 = value;
1210       break;
1211     case M32R_OPERAND_UIMM4 :
1212       fields->f_uimm4 = value;
1213       break;
1214     case M32R_OPERAND_UIMM5 :
1215       fields->f_uimm5 = value;
1216       break;
1217     case M32R_OPERAND_ULO16 :
1218       fields->f_uimm16 = value;
1219       break;
1220
1221     default :
1222       /* xgettext:c-format */
1223       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1224                        opindex);
1225       abort ();
1226   }
1227 }
1228
1229 /* Function to call before using the instruction builder tables.  */
1230
1231 void
1232 m32r_cgen_init_ibld_table (cd)
1233      CGEN_CPU_DESC cd;
1234 {
1235   cd->insert_handlers = & m32r_cgen_insert_handlers[0];
1236   cd->extract_handlers = & m32r_cgen_extract_handlers[0];
1237
1238   cd->insert_operand = m32r_cgen_insert_operand;
1239   cd->extract_operand = m32r_cgen_extract_operand;
1240
1241   cd->get_int_operand = m32r_cgen_get_int_operand;
1242   cd->set_int_operand = m32r_cgen_set_int_operand;
1243   cd->get_vma_operand = m32r_cgen_get_vma_operand;
1244   cd->set_vma_operand = m32r_cgen_set_vma_operand;
1245 }