1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX, LOCK_PREFIX. */
70 #define REX_PREFIX 6 /* must come last. */
71 #define MAX_PREFIXES 7 /* max prefixes per opcode */
73 /* we define the syntax here (modulo base,index,scale syntax) */
74 #define REGISTER_PREFIX '%'
75 #define IMMEDIATE_PREFIX '$'
76 #define ABSOLUTE_PREFIX '*'
78 /* these are the instruction mnemonic suffixes in AT&T syntax or
79 memory operand size in Intel syntax. */
80 #define WORD_MNEM_SUFFIX 'w'
81 #define BYTE_MNEM_SUFFIX 'b'
82 #define SHORT_MNEM_SUFFIX 's'
83 #define LONG_MNEM_SUFFIX 'l'
84 #define QWORD_MNEM_SUFFIX 'q'
85 #define XMMWORD_MNEM_SUFFIX 'x'
86 #define YMMWORD_MNEM_SUFFIX 'y'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_sse_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
193 /* VEX prefix is either 2 byte or 3 byte. */
194 unsigned char bytes
[3];
196 /* Destination or source register specifier. */
197 const reg_entry
*register_specifier
;
200 /* 'md_assemble ()' gathers together information and puts it into a
207 const reg_entry
*regs
;
212 operand_size_mismatch
,
213 operand_type_mismatch
,
214 register_type_mismatch
,
215 number_of_operands_mismatch
,
216 invalid_instruction_suffix
,
219 unsupported_with_intel_mnemonic
,
222 invalid_vsib_address
,
223 unsupported_vector_index_register
228 /* TM holds the template for the insn were currently assembling. */
231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
235 /* OPERANDS gives the number of given operands. */
236 unsigned int operands
;
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
241 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
243 /* TYPES [i] is the type (see above #defines) which tells us how to
244 use OP[i] for the corresponding operand. */
245 i386_operand_type types
[MAX_OPERANDS
];
247 /* Displacement expression, immediate expression, or register for each
249 union i386_op op
[MAX_OPERANDS
];
251 /* Flags for operands. */
252 unsigned int flags
[MAX_OPERANDS
];
253 #define Operand_PCrel 1
255 /* Relocation type for operand */
256 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry
*base_reg
;
261 const reg_entry
*index_reg
;
262 unsigned int log2_scale_factor
;
264 /* SEG gives the seg_entries of this insn. They are zero unless
265 explicit segment overrides are given. */
266 const seg_entry
*seg
[2];
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes
;
271 unsigned char prefix
[MAX_PREFIXES
];
273 /* RM and SIB are the modrm byte and the sib byte where the
274 addressing modes of this insn are encoded. */
280 /* Swap operand in encoding. */
281 unsigned int swap_operand
;
283 /* Force 32bit displacement in encoding. */
284 unsigned int disp32_encoding
;
287 enum i386_error error
;
290 typedef struct _i386_insn i386_insn
;
292 /* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
294 const char extra_symbol_chars
[] = "*%-(["
303 #if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
305 && !defined (TE_GNU) \
306 && !defined (TE_LINUX) \
307 && !defined (TE_NETWARE) \
308 && !defined (TE_FreeBSD) \
309 && !defined (TE_DragonFly) \
310 && !defined (TE_NetBSD)))
311 /* This array holds the chars that always start a comment. If the
312 pre-processor is disabled, these aren't very useful. The option
313 --divide will remove '/' from this list. */
314 const char *i386_comment_chars
= "#/";
315 #define SVR4_COMMENT_CHARS 1
316 #define PREFIX_SEPARATOR '\\'
319 const char *i386_comment_chars
= "#";
320 #define PREFIX_SEPARATOR '/'
323 /* This array holds the chars that only start a comment at the beginning of
324 a line. If the line seems to have the form '# 123 filename'
325 .line and .file directives will appear in the pre-processed output.
326 Note that input_file.c hand checks for '#' at the beginning of the
327 first line of the input file. This is because the compiler outputs
328 #NO_APP at the beginning of its output.
329 Also note that comments started like this one will always work if
330 '/' isn't otherwise defined. */
331 const char line_comment_chars
[] = "#/";
333 const char line_separator_chars
[] = ";";
335 /* Chars that can be used to separate mant from exp in floating point
337 const char EXP_CHARS
[] = "eE";
339 /* Chars that mean this number is a floating point constant
342 const char FLT_CHARS
[] = "fFdDxX";
344 /* Tables for lexical analysis. */
345 static char mnemonic_chars
[256];
346 static char register_chars
[256];
347 static char operand_chars
[256];
348 static char identifier_chars
[256];
349 static char digit_chars
[256];
351 /* Lexical macros. */
352 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
353 #define is_operand_char(x) (operand_chars[(unsigned char) x])
354 #define is_register_char(x) (register_chars[(unsigned char) x])
355 #define is_space_char(x) ((x) == ' ')
356 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
357 #define is_digit_char(x) (digit_chars[(unsigned char) x])
359 /* All non-digit non-letter characters that may occur in an operand. */
360 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
362 /* md_assemble() always leaves the strings it's passed unaltered. To
363 effect this we maintain a stack of saved characters that we've smashed
364 with '\0's (indicating end of strings for various sub-fields of the
365 assembler instruction). */
366 static char save_stack
[32];
367 static char *save_stack_p
;
368 #define END_STRING_AND_SAVE(s) \
369 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
370 #define RESTORE_END_STRING(s) \
371 do { *(s) = *--save_stack_p; } while (0)
373 /* The instruction we're assembling. */
376 /* Possible templates for current insn. */
377 static const templates
*current_templates
;
379 /* Per instruction expressionS buffers: max displacements & immediates. */
380 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
381 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
383 /* Current operand we are working on. */
384 static int this_operand
= -1;
386 /* We support four different modes. FLAG_CODE variable is used to distinguish
394 static enum flag_code flag_code
;
395 static unsigned int object_64bit
;
396 static unsigned int disallow_64bit_reloc
;
397 static int use_rela_relocations
= 0;
399 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
400 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
401 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
403 /* The ELF ABI to use. */
411 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
414 /* The names used to print error messages. */
415 static const char *flag_code_names
[] =
422 /* 1 for intel syntax,
424 static int intel_syntax
= 0;
426 /* 1 for intel mnemonic,
427 0 if att mnemonic. */
428 static int intel_mnemonic
= !SYSV386_COMPAT
;
430 /* 1 if support old (<= 2.8.1) versions of gcc. */
431 static int old_gcc
= OLDGCC_COMPAT
;
433 /* 1 if pseudo registers are permitted. */
434 static int allow_pseudo_reg
= 0;
436 /* 1 if register prefix % not required. */
437 static int allow_naked_reg
= 0;
439 /* 1 if pseudo index register, eiz/riz, is allowed . */
440 static int allow_index_reg
= 0;
450 /* Register prefix used for error message. */
451 static const char *register_prefix
= "%";
453 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
454 leave, push, and pop instructions so that gcc has the same stack
455 frame as in 32 bit mode. */
456 static char stackop_size
= '\0';
458 /* Non-zero to optimize code alignment. */
459 int optimize_align_code
= 1;
461 /* Non-zero to quieten some warnings. */
462 static int quiet_warnings
= 0;
465 static const char *cpu_arch_name
= NULL
;
466 static char *cpu_sub_arch_name
= NULL
;
468 /* CPU feature flags. */
469 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
471 /* If we have selected a cpu we are generating instructions for. */
472 static int cpu_arch_tune_set
= 0;
474 /* Cpu we are generating instructions for. */
475 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
477 /* CPU feature flags of cpu we are generating instructions for. */
478 static i386_cpu_flags cpu_arch_tune_flags
;
480 /* CPU instruction set architecture used. */
481 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
483 /* CPU feature flags of instruction set architecture used. */
484 i386_cpu_flags cpu_arch_isa_flags
;
486 /* If set, conditional jumps are not automatically promoted to handle
487 larger than a byte offset. */
488 static unsigned int no_cond_jump_promotion
= 0;
490 /* Encode SSE instructions with VEX prefix. */
491 static unsigned int sse2avx
;
493 /* Encode scalar AVX instructions with specific vector length. */
500 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
501 static symbolS
*GOT_symbol
;
503 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
504 unsigned int x86_dwarf2_return_column
;
506 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
507 int x86_cie_data_alignment
;
509 /* Interface to relax_segment.
510 There are 3 major relax states for 386 jump insns because the
511 different types of jumps add different sizes to frags when we're
512 figuring out what sort of jump to choose to reach a given label. */
515 #define UNCOND_JUMP 0
517 #define COND_JUMP86 2
522 #define SMALL16 (SMALL | CODE16)
524 #define BIG16 (BIG | CODE16)
528 #define INLINE __inline__
534 #define ENCODE_RELAX_STATE(type, size) \
535 ((relax_substateT) (((type) << 2) | (size)))
536 #define TYPE_FROM_RELAX_STATE(s) \
538 #define DISP_SIZE_FROM_RELAX_STATE(s) \
539 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
541 /* This table is used by relax_frag to promote short jumps to long
542 ones where necessary. SMALL (short) jumps may be promoted to BIG
543 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
544 don't allow a short jump in a 32 bit code segment to be promoted to
545 a 16 bit offset jump because it's slower (requires data size
546 prefix), and doesn't work, unless the destination is in the bottom
547 64k of the code segment (The top 16 bits of eip are zeroed). */
549 const relax_typeS md_relax_table
[] =
552 1) most positive reach of this state,
553 2) most negative reach of this state,
554 3) how many bytes this mode will have in the variable part of the frag
555 4) which index into the table to try if we can't fit into this one. */
557 /* UNCOND_JUMP states. */
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
560 /* dword jmp adds 4 bytes to frag:
561 0 extra opcode bytes, 4 displacement bytes. */
563 /* word jmp adds 2 byte2 to frag:
564 0 extra opcode bytes, 2 displacement bytes. */
567 /* COND_JUMP states. */
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
570 /* dword conditionals adds 5 bytes to frag:
571 1 extra opcode byte, 4 displacement bytes. */
573 /* word conditionals add 3 bytes to frag:
574 1 extra opcode byte, 2 displacement bytes. */
577 /* COND_JUMP86 states. */
578 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
580 /* dword conditionals adds 5 bytes to frag:
581 1 extra opcode byte, 4 displacement bytes. */
583 /* word conditionals add 4 bytes to frag:
584 1 displacement byte and a 3 byte long branch insn. */
588 static const arch_entry cpu_arch
[] =
590 /* Do not replace the first two entries - i386_target_format()
591 relies on them being there in this order. */
592 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
593 CPU_GENERIC32_FLAGS
, 0, 0 },
594 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
595 CPU_GENERIC64_FLAGS
, 0, 0 },
596 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
597 CPU_NONE_FLAGS
, 0, 0 },
598 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
599 CPU_I186_FLAGS
, 0, 0 },
600 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
601 CPU_I286_FLAGS
, 0, 0 },
602 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
603 CPU_I386_FLAGS
, 0, 0 },
604 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
605 CPU_I486_FLAGS
, 0, 0 },
606 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
607 CPU_I586_FLAGS
, 0, 0 },
608 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
609 CPU_I686_FLAGS
, 0, 0 },
610 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
611 CPU_I586_FLAGS
, 0, 0 },
612 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
613 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
614 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
615 CPU_P2_FLAGS
, 0, 0 },
616 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
617 CPU_P3_FLAGS
, 0, 0 },
618 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
619 CPU_P4_FLAGS
, 0, 0 },
620 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
621 CPU_CORE_FLAGS
, 0, 0 },
622 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
623 CPU_NOCONA_FLAGS
, 0, 0 },
624 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
625 CPU_CORE_FLAGS
, 1, 0 },
626 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
627 CPU_CORE_FLAGS
, 0, 0 },
628 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
629 CPU_CORE2_FLAGS
, 1, 0 },
630 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
631 CPU_CORE2_FLAGS
, 0, 0 },
632 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
633 CPU_COREI7_FLAGS
, 0, 0 },
634 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
635 CPU_L1OM_FLAGS
, 0, 0 },
636 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
637 CPU_K1OM_FLAGS
, 0, 0 },
638 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
639 CPU_K6_FLAGS
, 0, 0 },
640 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
641 CPU_K6_2_FLAGS
, 0, 0 },
642 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
643 CPU_ATHLON_FLAGS
, 0, 0 },
644 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
645 CPU_K8_FLAGS
, 1, 0 },
646 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
647 CPU_K8_FLAGS
, 0, 0 },
648 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
649 CPU_K8_FLAGS
, 0, 0 },
650 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
651 CPU_AMDFAM10_FLAGS
, 0, 0 },
652 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
653 CPU_BDVER1_FLAGS
, 0, 0 },
654 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
655 CPU_BDVER2_FLAGS
, 0, 0 },
656 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
657 CPU_8087_FLAGS
, 0, 0 },
658 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
659 CPU_287_FLAGS
, 0, 0 },
660 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
661 CPU_387_FLAGS
, 0, 0 },
662 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
663 CPU_ANY87_FLAGS
, 0, 1 },
664 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
665 CPU_MMX_FLAGS
, 0, 0 },
666 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
667 CPU_3DNOWA_FLAGS
, 0, 1 },
668 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
669 CPU_SSE_FLAGS
, 0, 0 },
670 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
671 CPU_SSE2_FLAGS
, 0, 0 },
672 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
673 CPU_SSE3_FLAGS
, 0, 0 },
674 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
675 CPU_SSSE3_FLAGS
, 0, 0 },
676 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
677 CPU_SSE4_1_FLAGS
, 0, 0 },
678 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
679 CPU_SSE4_2_FLAGS
, 0, 0 },
680 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
681 CPU_SSE4_2_FLAGS
, 0, 0 },
682 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
683 CPU_ANY_SSE_FLAGS
, 0, 1 },
684 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
685 CPU_AVX_FLAGS
, 0, 0 },
686 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
687 CPU_AVX2_FLAGS
, 0, 0 },
688 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
689 CPU_ANY_AVX_FLAGS
, 0, 1 },
690 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
691 CPU_VMX_FLAGS
, 0, 0 },
692 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
693 CPU_SMX_FLAGS
, 0, 0 },
694 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
695 CPU_XSAVE_FLAGS
, 0, 0 },
696 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
697 CPU_XSAVEOPT_FLAGS
, 0, 0 },
698 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
699 CPU_AES_FLAGS
, 0, 0 },
700 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
701 CPU_PCLMUL_FLAGS
, 0, 0 },
702 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
703 CPU_PCLMUL_FLAGS
, 1, 0 },
704 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
705 CPU_FSGSBASE_FLAGS
, 0, 0 },
706 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
707 CPU_RDRND_FLAGS
, 0, 0 },
708 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
709 CPU_F16C_FLAGS
, 0, 0 },
710 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
711 CPU_BMI2_FLAGS
, 0, 0 },
712 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
713 CPU_FMA_FLAGS
, 0, 0 },
714 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
715 CPU_FMA4_FLAGS
, 0, 0 },
716 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
717 CPU_XOP_FLAGS
, 0, 0 },
718 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
719 CPU_LWP_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
721 CPU_MOVBE_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
723 CPU_EPT_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
725 CPU_LZCNT_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
727 CPU_INVPCID_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
729 CPU_CLFLUSH_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
731 CPU_NOP_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
733 CPU_SYSCALL_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
735 CPU_RDTSCP_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
737 CPU_3DNOW_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
739 CPU_3DNOWA_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
741 CPU_PADLOCK_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
743 CPU_SVME_FLAGS
, 1, 0 },
744 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
745 CPU_SVME_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
747 CPU_SSE4A_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
749 CPU_ABM_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
751 CPU_BMI_FLAGS
, 0, 0 },
752 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
753 CPU_TBM_FLAGS
, 0, 0 },
757 /* Like s_lcomm_internal in gas/read.c but the alignment string
758 is allowed to be optional. */
761 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
768 && *input_line_pointer
== ',')
770 align
= parse_align (needs_align
- 1);
772 if (align
== (addressT
) -1)
787 bss_alloc (symbolP
, size
, align
);
792 pe_lcomm (int needs_align
)
794 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
798 const pseudo_typeS md_pseudo_table
[] =
800 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
801 {"align", s_align_bytes
, 0},
803 {"align", s_align_ptwo
, 0},
805 {"arch", set_cpu_arch
, 0},
809 {"lcomm", pe_lcomm
, 1},
811 {"ffloat", float_cons
, 'f'},
812 {"dfloat", float_cons
, 'd'},
813 {"tfloat", float_cons
, 'x'},
815 {"slong", signed_cons
, 4},
816 {"noopt", s_ignore
, 0},
817 {"optim", s_ignore
, 0},
818 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
819 {"code16", set_code_flag
, CODE_16BIT
},
820 {"code32", set_code_flag
, CODE_32BIT
},
821 {"code64", set_code_flag
, CODE_64BIT
},
822 {"intel_syntax", set_intel_syntax
, 1},
823 {"att_syntax", set_intel_syntax
, 0},
824 {"intel_mnemonic", set_intel_mnemonic
, 1},
825 {"att_mnemonic", set_intel_mnemonic
, 0},
826 {"allow_index_reg", set_allow_index_reg
, 1},
827 {"disallow_index_reg", set_allow_index_reg
, 0},
828 {"sse_check", set_sse_check
, 0},
829 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
830 {"largecomm", handle_large_common
, 0},
832 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
833 {"loc", dwarf2_directive_loc
, 0},
834 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
837 {"secrel32", pe_directive_secrel
, 0},
842 /* For interface with expression (). */
843 extern char *input_line_pointer
;
845 /* Hash table for instruction mnemonic lookup. */
846 static struct hash_control
*op_hash
;
848 /* Hash table for register lookup. */
849 static struct hash_control
*reg_hash
;
852 i386_align_code (fragS
*fragP
, int count
)
854 /* Various efficient no-op patterns for aligning code labels.
855 Note: Don't try to assemble the instructions in the comments.
856 0L and 0w are not legal. */
857 static const char f32_1
[] =
859 static const char f32_2
[] =
860 {0x66,0x90}; /* xchg %ax,%ax */
861 static const char f32_3
[] =
862 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
863 static const char f32_4
[] =
864 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
865 static const char f32_5
[] =
867 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
868 static const char f32_6
[] =
869 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
870 static const char f32_7
[] =
871 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
872 static const char f32_8
[] =
874 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
875 static const char f32_9
[] =
876 {0x89,0xf6, /* movl %esi,%esi */
877 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
878 static const char f32_10
[] =
879 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
880 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
881 static const char f32_11
[] =
882 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
883 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
884 static const char f32_12
[] =
885 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
886 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
887 static const char f32_13
[] =
888 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
889 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
890 static const char f32_14
[] =
891 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
892 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
893 static const char f16_3
[] =
894 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
895 static const char f16_4
[] =
896 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
897 static const char f16_5
[] =
899 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
900 static const char f16_6
[] =
901 {0x89,0xf6, /* mov %si,%si */
902 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
903 static const char f16_7
[] =
904 {0x8d,0x74,0x00, /* lea 0(%si),%si */
905 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
906 static const char f16_8
[] =
907 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
908 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
909 static const char jump_31
[] =
910 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
911 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
912 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
913 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
914 static const char *const f32_patt
[] = {
915 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
916 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
918 static const char *const f16_patt
[] = {
919 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
922 static const char alt_3
[] =
924 /* nopl 0(%[re]ax) */
925 static const char alt_4
[] =
926 {0x0f,0x1f,0x40,0x00};
927 /* nopl 0(%[re]ax,%[re]ax,1) */
928 static const char alt_5
[] =
929 {0x0f,0x1f,0x44,0x00,0x00};
930 /* nopw 0(%[re]ax,%[re]ax,1) */
931 static const char alt_6
[] =
932 {0x66,0x0f,0x1f,0x44,0x00,0x00};
933 /* nopl 0L(%[re]ax) */
934 static const char alt_7
[] =
935 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
936 /* nopl 0L(%[re]ax,%[re]ax,1) */
937 static const char alt_8
[] =
938 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
939 /* nopw 0L(%[re]ax,%[re]ax,1) */
940 static const char alt_9
[] =
941 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
942 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
943 static const char alt_10
[] =
944 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
946 nopw %cs:0L(%[re]ax,%[re]ax,1) */
947 static const char alt_long_11
[] =
949 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
952 nopw %cs:0L(%[re]ax,%[re]ax,1) */
953 static const char alt_long_12
[] =
956 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
960 nopw %cs:0L(%[re]ax,%[re]ax,1) */
961 static const char alt_long_13
[] =
965 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
970 nopw %cs:0L(%[re]ax,%[re]ax,1) */
971 static const char alt_long_14
[] =
976 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
982 nopw %cs:0L(%[re]ax,%[re]ax,1) */
983 static const char alt_long_15
[] =
989 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
990 /* nopl 0(%[re]ax,%[re]ax,1)
991 nopw 0(%[re]ax,%[re]ax,1) */
992 static const char alt_short_11
[] =
993 {0x0f,0x1f,0x44,0x00,0x00,
994 0x66,0x0f,0x1f,0x44,0x00,0x00};
995 /* nopw 0(%[re]ax,%[re]ax,1)
996 nopw 0(%[re]ax,%[re]ax,1) */
997 static const char alt_short_12
[] =
998 {0x66,0x0f,0x1f,0x44,0x00,0x00,
999 0x66,0x0f,0x1f,0x44,0x00,0x00};
1000 /* nopw 0(%[re]ax,%[re]ax,1)
1002 static const char alt_short_13
[] =
1003 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1004 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1007 static const char alt_short_14
[] =
1008 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1009 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1011 nopl 0L(%[re]ax,%[re]ax,1) */
1012 static const char alt_short_15
[] =
1013 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1014 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1015 static const char *const alt_short_patt
[] = {
1016 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1017 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1018 alt_short_14
, alt_short_15
1020 static const char *const alt_long_patt
[] = {
1021 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1022 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1023 alt_long_14
, alt_long_15
1026 /* Only align for at least a positive non-zero boundary. */
1027 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1030 /* We need to decide which NOP sequence to use for 32bit and
1031 64bit. When -mtune= is used:
1033 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1034 PROCESSOR_GENERIC32, f32_patt will be used.
1035 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1036 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1037 PROCESSOR_GENERIC64, alt_long_patt will be used.
1038 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1039 PROCESSOR_AMDFAM10, and PROCESSOR_BD, alt_short_patt
1042 When -mtune= isn't used, alt_long_patt will be used if
1043 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1046 When -march= or .arch is used, we can't use anything beyond
1047 cpu_arch_isa_flags. */
1049 if (flag_code
== CODE_16BIT
)
1053 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1055 /* Adjust jump offset. */
1056 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1059 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1060 f16_patt
[count
- 1], count
);
1064 const char *const *patt
= NULL
;
1066 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1068 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1069 switch (cpu_arch_tune
)
1071 case PROCESSOR_UNKNOWN
:
1072 /* We use cpu_arch_isa_flags to check if we SHOULD
1073 optimize with nops. */
1074 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1075 patt
= alt_long_patt
;
1079 case PROCESSOR_PENTIUM4
:
1080 case PROCESSOR_NOCONA
:
1081 case PROCESSOR_CORE
:
1082 case PROCESSOR_CORE2
:
1083 case PROCESSOR_COREI7
:
1084 case PROCESSOR_L1OM
:
1085 case PROCESSOR_K1OM
:
1086 case PROCESSOR_GENERIC64
:
1087 patt
= alt_long_patt
;
1090 case PROCESSOR_ATHLON
:
1092 case PROCESSOR_AMDFAM10
:
1094 patt
= alt_short_patt
;
1096 case PROCESSOR_I386
:
1097 case PROCESSOR_I486
:
1098 case PROCESSOR_PENTIUM
:
1099 case PROCESSOR_PENTIUMPRO
:
1100 case PROCESSOR_GENERIC32
:
1107 switch (fragP
->tc_frag_data
.tune
)
1109 case PROCESSOR_UNKNOWN
:
1110 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1111 PROCESSOR_UNKNOWN. */
1115 case PROCESSOR_I386
:
1116 case PROCESSOR_I486
:
1117 case PROCESSOR_PENTIUM
:
1119 case PROCESSOR_ATHLON
:
1121 case PROCESSOR_AMDFAM10
:
1123 case PROCESSOR_GENERIC32
:
1124 /* We use cpu_arch_isa_flags to check if we CAN optimize
1126 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1127 patt
= alt_short_patt
;
1131 case PROCESSOR_PENTIUMPRO
:
1132 case PROCESSOR_PENTIUM4
:
1133 case PROCESSOR_NOCONA
:
1134 case PROCESSOR_CORE
:
1135 case PROCESSOR_CORE2
:
1136 case PROCESSOR_COREI7
:
1137 case PROCESSOR_L1OM
:
1138 case PROCESSOR_K1OM
:
1139 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1140 patt
= alt_long_patt
;
1144 case PROCESSOR_GENERIC64
:
1145 patt
= alt_long_patt
;
1150 if (patt
== f32_patt
)
1152 /* If the padding is less than 15 bytes, we use the normal
1153 ones. Otherwise, we use a jump instruction and adjust
1157 /* For 64bit, the limit is 3 bytes. */
1158 if (flag_code
== CODE_64BIT
1159 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1164 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1165 patt
[count
- 1], count
);
1168 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1170 /* Adjust jump offset. */
1171 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1176 /* Maximum length of an instruction is 15 byte. If the
1177 padding is greater than 15 bytes and we don't use jump,
1178 we have to break it into smaller pieces. */
1179 int padding
= count
;
1180 while (padding
> 15)
1183 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1188 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1189 patt
[padding
- 1], padding
);
1192 fragP
->fr_var
= count
;
1196 operand_type_all_zero (const union i386_operand_type
*x
)
1198 switch (ARRAY_SIZE(x
->array
))
1207 return !x
->array
[0];
1214 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1216 switch (ARRAY_SIZE(x
->array
))
1231 operand_type_equal (const union i386_operand_type
*x
,
1232 const union i386_operand_type
*y
)
1234 switch (ARRAY_SIZE(x
->array
))
1237 if (x
->array
[2] != y
->array
[2])
1240 if (x
->array
[1] != y
->array
[1])
1243 return x
->array
[0] == y
->array
[0];
1251 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1253 switch (ARRAY_SIZE(x
->array
))
1262 return !x
->array
[0];
1269 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1271 switch (ARRAY_SIZE(x
->array
))
1286 cpu_flags_equal (const union i386_cpu_flags
*x
,
1287 const union i386_cpu_flags
*y
)
1289 switch (ARRAY_SIZE(x
->array
))
1292 if (x
->array
[2] != y
->array
[2])
1295 if (x
->array
[1] != y
->array
[1])
1298 return x
->array
[0] == y
->array
[0];
1306 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1308 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1309 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1312 static INLINE i386_cpu_flags
1313 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1315 switch (ARRAY_SIZE (x
.array
))
1318 x
.array
[2] &= y
.array
[2];
1320 x
.array
[1] &= y
.array
[1];
1322 x
.array
[0] &= y
.array
[0];
1330 static INLINE i386_cpu_flags
1331 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1333 switch (ARRAY_SIZE (x
.array
))
1336 x
.array
[2] |= y
.array
[2];
1338 x
.array
[1] |= y
.array
[1];
1340 x
.array
[0] |= y
.array
[0];
1348 static INLINE i386_cpu_flags
1349 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1351 switch (ARRAY_SIZE (x
.array
))
1354 x
.array
[2] &= ~y
.array
[2];
1356 x
.array
[1] &= ~y
.array
[1];
1358 x
.array
[0] &= ~y
.array
[0];
1366 #define CPU_FLAGS_ARCH_MATCH 0x1
1367 #define CPU_FLAGS_64BIT_MATCH 0x2
1368 #define CPU_FLAGS_AES_MATCH 0x4
1369 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1370 #define CPU_FLAGS_AVX_MATCH 0x10
1372 #define CPU_FLAGS_32BIT_MATCH \
1373 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1374 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1375 #define CPU_FLAGS_PERFECT_MATCH \
1376 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1378 /* Return CPU flags match bits. */
1381 cpu_flags_match (const insn_template
*t
)
1383 i386_cpu_flags x
= t
->cpu_flags
;
1384 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1386 x
.bitfield
.cpu64
= 0;
1387 x
.bitfield
.cpuno64
= 0;
1389 if (cpu_flags_all_zero (&x
))
1391 /* This instruction is available on all archs. */
1392 match
|= CPU_FLAGS_32BIT_MATCH
;
1396 /* This instruction is available only on some archs. */
1397 i386_cpu_flags cpu
= cpu_arch_flags
;
1399 cpu
.bitfield
.cpu64
= 0;
1400 cpu
.bitfield
.cpuno64
= 0;
1401 cpu
= cpu_flags_and (x
, cpu
);
1402 if (!cpu_flags_all_zero (&cpu
))
1404 if (x
.bitfield
.cpuavx
)
1406 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1407 if (cpu
.bitfield
.cpuavx
)
1409 /* Check SSE2AVX. */
1410 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1412 match
|= (CPU_FLAGS_ARCH_MATCH
1413 | CPU_FLAGS_AVX_MATCH
);
1415 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1416 match
|= CPU_FLAGS_AES_MATCH
;
1418 if (!x
.bitfield
.cpupclmul
1419 || cpu
.bitfield
.cpupclmul
)
1420 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1424 match
|= CPU_FLAGS_ARCH_MATCH
;
1427 match
|= CPU_FLAGS_32BIT_MATCH
;
1433 static INLINE i386_operand_type
1434 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1436 switch (ARRAY_SIZE (x
.array
))
1439 x
.array
[2] &= y
.array
[2];
1441 x
.array
[1] &= y
.array
[1];
1443 x
.array
[0] &= y
.array
[0];
1451 static INLINE i386_operand_type
1452 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1454 switch (ARRAY_SIZE (x
.array
))
1457 x
.array
[2] |= y
.array
[2];
1459 x
.array
[1] |= y
.array
[1];
1461 x
.array
[0] |= y
.array
[0];
1469 static INLINE i386_operand_type
1470 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1472 switch (ARRAY_SIZE (x
.array
))
1475 x
.array
[2] ^= y
.array
[2];
1477 x
.array
[1] ^= y
.array
[1];
1479 x
.array
[0] ^= y
.array
[0];
1487 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1488 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1489 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1490 static const i386_operand_type inoutportreg
1491 = OPERAND_TYPE_INOUTPORTREG
;
1492 static const i386_operand_type reg16_inoutportreg
1493 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1494 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1495 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1496 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1497 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1498 static const i386_operand_type anydisp
1499 = OPERAND_TYPE_ANYDISP
;
1500 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1501 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1502 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1503 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1504 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1505 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1506 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1507 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1508 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1509 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1510 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1511 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1522 operand_type_check (i386_operand_type t
, enum operand_type c
)
1527 return (t
.bitfield
.reg8
1530 || t
.bitfield
.reg64
);
1533 return (t
.bitfield
.imm8
1537 || t
.bitfield
.imm32s
1538 || t
.bitfield
.imm64
);
1541 return (t
.bitfield
.disp8
1542 || t
.bitfield
.disp16
1543 || t
.bitfield
.disp32
1544 || t
.bitfield
.disp32s
1545 || t
.bitfield
.disp64
);
1548 return (t
.bitfield
.disp8
1549 || t
.bitfield
.disp16
1550 || t
.bitfield
.disp32
1551 || t
.bitfield
.disp32s
1552 || t
.bitfield
.disp64
1553 || t
.bitfield
.baseindex
);
1562 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1563 operand J for instruction template T. */
1566 match_reg_size (const insn_template
*t
, unsigned int j
)
1568 return !((i
.types
[j
].bitfield
.byte
1569 && !t
->operand_types
[j
].bitfield
.byte
)
1570 || (i
.types
[j
].bitfield
.word
1571 && !t
->operand_types
[j
].bitfield
.word
)
1572 || (i
.types
[j
].bitfield
.dword
1573 && !t
->operand_types
[j
].bitfield
.dword
)
1574 || (i
.types
[j
].bitfield
.qword
1575 && !t
->operand_types
[j
].bitfield
.qword
));
1578 /* Return 1 if there is no conflict in any size on operand J for
1579 instruction template T. */
1582 match_mem_size (const insn_template
*t
, unsigned int j
)
1584 return (match_reg_size (t
, j
)
1585 && !((i
.types
[j
].bitfield
.unspecified
1586 && !t
->operand_types
[j
].bitfield
.unspecified
)
1587 || (i
.types
[j
].bitfield
.fword
1588 && !t
->operand_types
[j
].bitfield
.fword
)
1589 || (i
.types
[j
].bitfield
.tbyte
1590 && !t
->operand_types
[j
].bitfield
.tbyte
)
1591 || (i
.types
[j
].bitfield
.xmmword
1592 && !t
->operand_types
[j
].bitfield
.xmmword
)
1593 || (i
.types
[j
].bitfield
.ymmword
1594 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1597 /* Return 1 if there is no size conflict on any operands for
1598 instruction template T. */
1601 operand_size_match (const insn_template
*t
)
1606 /* Don't check jump instructions. */
1607 if (t
->opcode_modifier
.jump
1608 || t
->opcode_modifier
.jumpbyte
1609 || t
->opcode_modifier
.jumpdword
1610 || t
->opcode_modifier
.jumpintersegment
)
1613 /* Check memory and accumulator operand size. */
1614 for (j
= 0; j
< i
.operands
; j
++)
1616 if (t
->operand_types
[j
].bitfield
.anysize
)
1619 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1625 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1634 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1637 i
.error
= operand_size_mismatch
;
1641 /* Check reverse. */
1642 gas_assert (i
.operands
== 2);
1645 for (j
= 0; j
< 2; j
++)
1647 if (t
->operand_types
[j
].bitfield
.acc
1648 && !match_reg_size (t
, j
? 0 : 1))
1651 if (i
.types
[j
].bitfield
.mem
1652 && !match_mem_size (t
, j
? 0 : 1))
1660 operand_type_match (i386_operand_type overlap
,
1661 i386_operand_type given
)
1663 i386_operand_type temp
= overlap
;
1665 temp
.bitfield
.jumpabsolute
= 0;
1666 temp
.bitfield
.unspecified
= 0;
1667 temp
.bitfield
.byte
= 0;
1668 temp
.bitfield
.word
= 0;
1669 temp
.bitfield
.dword
= 0;
1670 temp
.bitfield
.fword
= 0;
1671 temp
.bitfield
.qword
= 0;
1672 temp
.bitfield
.tbyte
= 0;
1673 temp
.bitfield
.xmmword
= 0;
1674 temp
.bitfield
.ymmword
= 0;
1675 if (operand_type_all_zero (&temp
))
1678 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1679 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1683 i
.error
= operand_type_mismatch
;
1687 /* If given types g0 and g1 are registers they must be of the same type
1688 unless the expected operand type register overlap is null.
1689 Note that Acc in a template matches every size of reg. */
1692 operand_type_register_match (i386_operand_type m0
,
1693 i386_operand_type g0
,
1694 i386_operand_type t0
,
1695 i386_operand_type m1
,
1696 i386_operand_type g1
,
1697 i386_operand_type t1
)
1699 if (!operand_type_check (g0
, reg
))
1702 if (!operand_type_check (g1
, reg
))
1705 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1706 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1707 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1708 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1711 if (m0
.bitfield
.acc
)
1713 t0
.bitfield
.reg8
= 1;
1714 t0
.bitfield
.reg16
= 1;
1715 t0
.bitfield
.reg32
= 1;
1716 t0
.bitfield
.reg64
= 1;
1719 if (m1
.bitfield
.acc
)
1721 t1
.bitfield
.reg8
= 1;
1722 t1
.bitfield
.reg16
= 1;
1723 t1
.bitfield
.reg32
= 1;
1724 t1
.bitfield
.reg64
= 1;
1727 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1728 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1729 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1730 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1733 i
.error
= register_type_mismatch
;
1738 static INLINE
unsigned int
1739 mode_from_disp_size (i386_operand_type t
)
1741 if (t
.bitfield
.disp8
)
1743 else if (t
.bitfield
.disp16
1744 || t
.bitfield
.disp32
1745 || t
.bitfield
.disp32s
)
1752 fits_in_signed_byte (offsetT num
)
1754 return (num
>= -128) && (num
<= 127);
1758 fits_in_unsigned_byte (offsetT num
)
1760 return (num
& 0xff) == num
;
1764 fits_in_unsigned_word (offsetT num
)
1766 return (num
& 0xffff) == num
;
1770 fits_in_signed_word (offsetT num
)
1772 return (-32768 <= num
) && (num
<= 32767);
1776 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1781 return (!(((offsetT
) -1 << 31) & num
)
1782 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1784 } /* fits_in_signed_long() */
1787 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1792 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1794 } /* fits_in_unsigned_long() */
1797 fits_in_imm4 (offsetT num
)
1799 return (num
& 0xf) == num
;
1802 static i386_operand_type
1803 smallest_imm_type (offsetT num
)
1805 i386_operand_type t
;
1807 operand_type_set (&t
, 0);
1808 t
.bitfield
.imm64
= 1;
1810 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1812 /* This code is disabled on the 486 because all the Imm1 forms
1813 in the opcode table are slower on the i486. They're the
1814 versions with the implicitly specified single-position
1815 displacement, which has another syntax if you really want to
1817 t
.bitfield
.imm1
= 1;
1818 t
.bitfield
.imm8
= 1;
1819 t
.bitfield
.imm8s
= 1;
1820 t
.bitfield
.imm16
= 1;
1821 t
.bitfield
.imm32
= 1;
1822 t
.bitfield
.imm32s
= 1;
1824 else if (fits_in_signed_byte (num
))
1826 t
.bitfield
.imm8
= 1;
1827 t
.bitfield
.imm8s
= 1;
1828 t
.bitfield
.imm16
= 1;
1829 t
.bitfield
.imm32
= 1;
1830 t
.bitfield
.imm32s
= 1;
1832 else if (fits_in_unsigned_byte (num
))
1834 t
.bitfield
.imm8
= 1;
1835 t
.bitfield
.imm16
= 1;
1836 t
.bitfield
.imm32
= 1;
1837 t
.bitfield
.imm32s
= 1;
1839 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1841 t
.bitfield
.imm16
= 1;
1842 t
.bitfield
.imm32
= 1;
1843 t
.bitfield
.imm32s
= 1;
1845 else if (fits_in_signed_long (num
))
1847 t
.bitfield
.imm32
= 1;
1848 t
.bitfield
.imm32s
= 1;
1850 else if (fits_in_unsigned_long (num
))
1851 t
.bitfield
.imm32
= 1;
1857 offset_in_range (offsetT val
, int size
)
1863 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1864 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1865 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1867 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1873 /* If BFD64, sign extend val for 32bit address mode. */
1874 if (flag_code
!= CODE_64BIT
1875 || i
.prefix
[ADDR_PREFIX
])
1876 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1877 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1880 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1882 char buf1
[40], buf2
[40];
1884 sprint_value (buf1
, val
);
1885 sprint_value (buf2
, val
& mask
);
1886 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1900 a. PREFIX_EXIST if attempting to add a prefix where one from the
1901 same class already exists.
1902 b. PREFIX_LOCK if lock prefix is added.
1903 c. PREFIX_REP if rep/repne prefix is added.
1904 d. PREFIX_OTHER if other prefix is added.
1907 static enum PREFIX_GROUP
1908 add_prefix (unsigned int prefix
)
1910 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1913 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1914 && flag_code
== CODE_64BIT
)
1916 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1917 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1918 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1929 case CS_PREFIX_OPCODE
:
1930 case DS_PREFIX_OPCODE
:
1931 case ES_PREFIX_OPCODE
:
1932 case FS_PREFIX_OPCODE
:
1933 case GS_PREFIX_OPCODE
:
1934 case SS_PREFIX_OPCODE
:
1938 case REPNE_PREFIX_OPCODE
:
1939 case REPE_PREFIX_OPCODE
:
1944 case LOCK_PREFIX_OPCODE
:
1953 case ADDR_PREFIX_OPCODE
:
1957 case DATA_PREFIX_OPCODE
:
1961 if (i
.prefix
[q
] != 0)
1969 i
.prefix
[q
] |= prefix
;
1972 as_bad (_("same type of prefix used twice"));
1978 update_code_flag (int value
, int check
)
1980 PRINTF_LIKE ((*as_error
));
1982 flag_code
= (enum flag_code
) value
;
1983 if (flag_code
== CODE_64BIT
)
1985 cpu_arch_flags
.bitfield
.cpu64
= 1;
1986 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1990 cpu_arch_flags
.bitfield
.cpu64
= 0;
1991 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1993 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1996 as_error
= as_fatal
;
1999 (*as_error
) (_("64bit mode not supported on `%s'."),
2000 cpu_arch_name
? cpu_arch_name
: default_arch
);
2002 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2005 as_error
= as_fatal
;
2008 (*as_error
) (_("32bit mode not supported on `%s'."),
2009 cpu_arch_name
? cpu_arch_name
: default_arch
);
2011 stackop_size
= '\0';
2015 set_code_flag (int value
)
2017 update_code_flag (value
, 0);
2021 set_16bit_gcc_code_flag (int new_code_flag
)
2023 flag_code
= (enum flag_code
) new_code_flag
;
2024 if (flag_code
!= CODE_16BIT
)
2026 cpu_arch_flags
.bitfield
.cpu64
= 0;
2027 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2028 stackop_size
= LONG_MNEM_SUFFIX
;
2032 set_intel_syntax (int syntax_flag
)
2034 /* Find out if register prefixing is specified. */
2035 int ask_naked_reg
= 0;
2038 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2040 char *string
= input_line_pointer
;
2041 int e
= get_symbol_end ();
2043 if (strcmp (string
, "prefix") == 0)
2045 else if (strcmp (string
, "noprefix") == 0)
2048 as_bad (_("bad argument to syntax directive."));
2049 *input_line_pointer
= e
;
2051 demand_empty_rest_of_line ();
2053 intel_syntax
= syntax_flag
;
2055 if (ask_naked_reg
== 0)
2056 allow_naked_reg
= (intel_syntax
2057 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2059 allow_naked_reg
= (ask_naked_reg
< 0);
2061 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2063 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2064 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2065 register_prefix
= allow_naked_reg
? "" : "%";
2069 set_intel_mnemonic (int mnemonic_flag
)
2071 intel_mnemonic
= mnemonic_flag
;
2075 set_allow_index_reg (int flag
)
2077 allow_index_reg
= flag
;
2081 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2085 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2087 char *string
= input_line_pointer
;
2088 int e
= get_symbol_end ();
2090 if (strcmp (string
, "none") == 0)
2091 sse_check
= sse_check_none
;
2092 else if (strcmp (string
, "warning") == 0)
2093 sse_check
= sse_check_warning
;
2094 else if (strcmp (string
, "error") == 0)
2095 sse_check
= sse_check_error
;
2097 as_bad (_("bad argument to sse_check directive."));
2098 *input_line_pointer
= e
;
2101 as_bad (_("missing argument for sse_check directive"));
2103 demand_empty_rest_of_line ();
2107 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2108 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2110 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2111 static const char *arch
;
2113 /* Intel LIOM is only supported on ELF. */
2119 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2120 use default_arch. */
2121 arch
= cpu_arch_name
;
2123 arch
= default_arch
;
2126 /* If we are targeting Intel L1OM, we must enable it. */
2127 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2128 || new_flag
.bitfield
.cpul1om
)
2131 /* If we are targeting Intel K1OM, we must enable it. */
2132 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2133 || new_flag
.bitfield
.cpuk1om
)
2136 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2141 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2145 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2147 char *string
= input_line_pointer
;
2148 int e
= get_symbol_end ();
2150 i386_cpu_flags flags
;
2152 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2154 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2156 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2160 cpu_arch_name
= cpu_arch
[j
].name
;
2161 cpu_sub_arch_name
= NULL
;
2162 cpu_arch_flags
= cpu_arch
[j
].flags
;
2163 if (flag_code
== CODE_64BIT
)
2165 cpu_arch_flags
.bitfield
.cpu64
= 1;
2166 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2170 cpu_arch_flags
.bitfield
.cpu64
= 0;
2171 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2173 cpu_arch_isa
= cpu_arch
[j
].type
;
2174 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2175 if (!cpu_arch_tune_set
)
2177 cpu_arch_tune
= cpu_arch_isa
;
2178 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2183 if (!cpu_arch
[j
].negated
)
2184 flags
= cpu_flags_or (cpu_arch_flags
,
2187 flags
= cpu_flags_and_not (cpu_arch_flags
,
2189 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2191 if (cpu_sub_arch_name
)
2193 char *name
= cpu_sub_arch_name
;
2194 cpu_sub_arch_name
= concat (name
,
2196 (const char *) NULL
);
2200 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2201 cpu_arch_flags
= flags
;
2202 cpu_arch_isa_flags
= flags
;
2204 *input_line_pointer
= e
;
2205 demand_empty_rest_of_line ();
2209 if (j
>= ARRAY_SIZE (cpu_arch
))
2210 as_bad (_("no such architecture: `%s'"), string
);
2212 *input_line_pointer
= e
;
2215 as_bad (_("missing cpu architecture"));
2217 no_cond_jump_promotion
= 0;
2218 if (*input_line_pointer
== ','
2219 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2221 char *string
= ++input_line_pointer
;
2222 int e
= get_symbol_end ();
2224 if (strcmp (string
, "nojumps") == 0)
2225 no_cond_jump_promotion
= 1;
2226 else if (strcmp (string
, "jumps") == 0)
2229 as_bad (_("no such architecture modifier: `%s'"), string
);
2231 *input_line_pointer
= e
;
2234 demand_empty_rest_of_line ();
2237 enum bfd_architecture
2240 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2242 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2243 || flag_code
!= CODE_64BIT
)
2244 as_fatal (_("Intel L1OM is 64bit ELF only"));
2245 return bfd_arch_l1om
;
2247 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2249 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2250 || flag_code
!= CODE_64BIT
)
2251 as_fatal (_("Intel K1OM is 64bit ELF only"));
2252 return bfd_arch_k1om
;
2255 return bfd_arch_i386
;
2261 if (!strncmp (default_arch
, "x86_64", 6))
2263 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2265 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2266 || default_arch
[6] != '\0')
2267 as_fatal (_("Intel L1OM is 64bit ELF only"));
2268 return bfd_mach_l1om
;
2270 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2272 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2273 || default_arch
[6] != '\0')
2274 as_fatal (_("Intel K1OM is 64bit ELF only"));
2275 return bfd_mach_k1om
;
2277 else if (default_arch
[6] == '\0')
2278 return bfd_mach_x86_64
;
2280 return bfd_mach_x64_32
;
2282 else if (!strcmp (default_arch
, "i386"))
2283 return bfd_mach_i386_i386
;
2285 as_fatal (_("unknown architecture"));
2291 const char *hash_err
;
2293 /* Initialize op_hash hash table. */
2294 op_hash
= hash_new ();
2297 const insn_template
*optab
;
2298 templates
*core_optab
;
2300 /* Setup for loop. */
2302 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2303 core_optab
->start
= optab
;
2308 if (optab
->name
== NULL
2309 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2311 /* different name --> ship out current template list;
2312 add to hash table; & begin anew. */
2313 core_optab
->end
= optab
;
2314 hash_err
= hash_insert (op_hash
,
2316 (void *) core_optab
);
2319 as_fatal (_("internal Error: Can't hash %s: %s"),
2323 if (optab
->name
== NULL
)
2325 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2326 core_optab
->start
= optab
;
2331 /* Initialize reg_hash hash table. */
2332 reg_hash
= hash_new ();
2334 const reg_entry
*regtab
;
2335 unsigned int regtab_size
= i386_regtab_size
;
2337 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2339 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2341 as_fatal (_("internal Error: Can't hash %s: %s"),
2347 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2352 for (c
= 0; c
< 256; c
++)
2357 mnemonic_chars
[c
] = c
;
2358 register_chars
[c
] = c
;
2359 operand_chars
[c
] = c
;
2361 else if (ISLOWER (c
))
2363 mnemonic_chars
[c
] = c
;
2364 register_chars
[c
] = c
;
2365 operand_chars
[c
] = c
;
2367 else if (ISUPPER (c
))
2369 mnemonic_chars
[c
] = TOLOWER (c
);
2370 register_chars
[c
] = mnemonic_chars
[c
];
2371 operand_chars
[c
] = c
;
2374 if (ISALPHA (c
) || ISDIGIT (c
))
2375 identifier_chars
[c
] = c
;
2378 identifier_chars
[c
] = c
;
2379 operand_chars
[c
] = c
;
2384 identifier_chars
['@'] = '@';
2387 identifier_chars
['?'] = '?';
2388 operand_chars
['?'] = '?';
2390 digit_chars
['-'] = '-';
2391 mnemonic_chars
['_'] = '_';
2392 mnemonic_chars
['-'] = '-';
2393 mnemonic_chars
['.'] = '.';
2394 identifier_chars
['_'] = '_';
2395 identifier_chars
['.'] = '.';
2397 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2398 operand_chars
[(unsigned char) *p
] = *p
;
2401 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2404 record_alignment (text_section
, 2);
2405 record_alignment (data_section
, 2);
2406 record_alignment (bss_section
, 2);
2410 if (flag_code
== CODE_64BIT
)
2412 #if defined (OBJ_COFF) && defined (TE_PE)
2413 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2416 x86_dwarf2_return_column
= 16;
2418 x86_cie_data_alignment
= -8;
2422 x86_dwarf2_return_column
= 8;
2423 x86_cie_data_alignment
= -4;
2428 i386_print_statistics (FILE *file
)
2430 hash_print_statistics (file
, "i386 opcode", op_hash
);
2431 hash_print_statistics (file
, "i386 register", reg_hash
);
2436 /* Debugging routines for md_assemble. */
2437 static void pte (insn_template
*);
2438 static void pt (i386_operand_type
);
2439 static void pe (expressionS
*);
2440 static void ps (symbolS
*);
2443 pi (char *line
, i386_insn
*x
)
2447 fprintf (stdout
, "%s: template ", line
);
2449 fprintf (stdout
, " address: base %s index %s scale %x\n",
2450 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2451 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2452 x
->log2_scale_factor
);
2453 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2454 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2455 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2456 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2457 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2458 (x
->rex
& REX_W
) != 0,
2459 (x
->rex
& REX_R
) != 0,
2460 (x
->rex
& REX_X
) != 0,
2461 (x
->rex
& REX_B
) != 0);
2462 for (j
= 0; j
< x
->operands
; j
++)
2464 fprintf (stdout
, " #%d: ", j
+ 1);
2466 fprintf (stdout
, "\n");
2467 if (x
->types
[j
].bitfield
.reg8
2468 || x
->types
[j
].bitfield
.reg16
2469 || x
->types
[j
].bitfield
.reg32
2470 || x
->types
[j
].bitfield
.reg64
2471 || x
->types
[j
].bitfield
.regmmx
2472 || x
->types
[j
].bitfield
.regxmm
2473 || x
->types
[j
].bitfield
.regymm
2474 || x
->types
[j
].bitfield
.sreg2
2475 || x
->types
[j
].bitfield
.sreg3
2476 || x
->types
[j
].bitfield
.control
2477 || x
->types
[j
].bitfield
.debug
2478 || x
->types
[j
].bitfield
.test
)
2479 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2480 if (operand_type_check (x
->types
[j
], imm
))
2482 if (operand_type_check (x
->types
[j
], disp
))
2483 pe (x
->op
[j
].disps
);
2488 pte (insn_template
*t
)
2491 fprintf (stdout
, " %d operands ", t
->operands
);
2492 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2493 if (t
->extension_opcode
!= None
)
2494 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2495 if (t
->opcode_modifier
.d
)
2496 fprintf (stdout
, "D");
2497 if (t
->opcode_modifier
.w
)
2498 fprintf (stdout
, "W");
2499 fprintf (stdout
, "\n");
2500 for (j
= 0; j
< t
->operands
; j
++)
2502 fprintf (stdout
, " #%d type ", j
+ 1);
2503 pt (t
->operand_types
[j
]);
2504 fprintf (stdout
, "\n");
2511 fprintf (stdout
, " operation %d\n", e
->X_op
);
2512 fprintf (stdout
, " add_number %ld (%lx)\n",
2513 (long) e
->X_add_number
, (long) e
->X_add_number
);
2514 if (e
->X_add_symbol
)
2516 fprintf (stdout
, " add_symbol ");
2517 ps (e
->X_add_symbol
);
2518 fprintf (stdout
, "\n");
2522 fprintf (stdout
, " op_symbol ");
2523 ps (e
->X_op_symbol
);
2524 fprintf (stdout
, "\n");
2531 fprintf (stdout
, "%s type %s%s",
2533 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2534 segment_name (S_GET_SEGMENT (s
)));
2537 static struct type_name
2539 i386_operand_type mask
;
2542 const type_names
[] =
2544 { OPERAND_TYPE_REG8
, "r8" },
2545 { OPERAND_TYPE_REG16
, "r16" },
2546 { OPERAND_TYPE_REG32
, "r32" },
2547 { OPERAND_TYPE_REG64
, "r64" },
2548 { OPERAND_TYPE_IMM8
, "i8" },
2549 { OPERAND_TYPE_IMM8
, "i8s" },
2550 { OPERAND_TYPE_IMM16
, "i16" },
2551 { OPERAND_TYPE_IMM32
, "i32" },
2552 { OPERAND_TYPE_IMM32S
, "i32s" },
2553 { OPERAND_TYPE_IMM64
, "i64" },
2554 { OPERAND_TYPE_IMM1
, "i1" },
2555 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2556 { OPERAND_TYPE_DISP8
, "d8" },
2557 { OPERAND_TYPE_DISP16
, "d16" },
2558 { OPERAND_TYPE_DISP32
, "d32" },
2559 { OPERAND_TYPE_DISP32S
, "d32s" },
2560 { OPERAND_TYPE_DISP64
, "d64" },
2561 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2562 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2563 { OPERAND_TYPE_CONTROL
, "control reg" },
2564 { OPERAND_TYPE_TEST
, "test reg" },
2565 { OPERAND_TYPE_DEBUG
, "debug reg" },
2566 { OPERAND_TYPE_FLOATREG
, "FReg" },
2567 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2568 { OPERAND_TYPE_SREG2
, "SReg2" },
2569 { OPERAND_TYPE_SREG3
, "SReg3" },
2570 { OPERAND_TYPE_ACC
, "Acc" },
2571 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2572 { OPERAND_TYPE_REGMMX
, "rMMX" },
2573 { OPERAND_TYPE_REGXMM
, "rXMM" },
2574 { OPERAND_TYPE_REGYMM
, "rYMM" },
2575 { OPERAND_TYPE_ESSEG
, "es" },
2579 pt (i386_operand_type t
)
2582 i386_operand_type a
;
2584 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2586 a
= operand_type_and (t
, type_names
[j
].mask
);
2587 if (!operand_type_all_zero (&a
))
2588 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2593 #endif /* DEBUG386 */
2595 static bfd_reloc_code_real_type
2596 reloc (unsigned int size
,
2599 bfd_reloc_code_real_type other
)
2601 if (other
!= NO_RELOC
)
2603 reloc_howto_type
*rel
;
2608 case BFD_RELOC_X86_64_GOT32
:
2609 return BFD_RELOC_X86_64_GOT64
;
2611 case BFD_RELOC_X86_64_PLTOFF64
:
2612 return BFD_RELOC_X86_64_PLTOFF64
;
2614 case BFD_RELOC_X86_64_GOTPC32
:
2615 other
= BFD_RELOC_X86_64_GOTPC64
;
2617 case BFD_RELOC_X86_64_GOTPCREL
:
2618 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2620 case BFD_RELOC_X86_64_TPOFF32
:
2621 other
= BFD_RELOC_X86_64_TPOFF64
;
2623 case BFD_RELOC_X86_64_DTPOFF32
:
2624 other
= BFD_RELOC_X86_64_DTPOFF64
;
2630 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2631 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2634 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2636 as_bad (_("unknown relocation (%u)"), other
);
2637 else if (size
!= bfd_get_reloc_size (rel
))
2638 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2639 bfd_get_reloc_size (rel
),
2641 else if (pcrel
&& !rel
->pc_relative
)
2642 as_bad (_("non-pc-relative relocation for pc-relative field"));
2643 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2645 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2647 as_bad (_("relocated field and relocation type differ in signedness"));
2656 as_bad (_("there are no unsigned pc-relative relocations"));
2659 case 1: return BFD_RELOC_8_PCREL
;
2660 case 2: return BFD_RELOC_16_PCREL
;
2661 case 4: return BFD_RELOC_32_PCREL
;
2662 case 8: return BFD_RELOC_64_PCREL
;
2664 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2671 case 4: return BFD_RELOC_X86_64_32S
;
2676 case 1: return BFD_RELOC_8
;
2677 case 2: return BFD_RELOC_16
;
2678 case 4: return BFD_RELOC_32
;
2679 case 8: return BFD_RELOC_64
;
2681 as_bad (_("cannot do %s %u byte relocation"),
2682 sign
> 0 ? "signed" : "unsigned", size
);
2688 /* Here we decide which fixups can be adjusted to make them relative to
2689 the beginning of the section instead of the symbol. Basically we need
2690 to make sure that the dynamic relocations are done correctly, so in
2691 some cases we force the original symbol to be used. */
2694 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2696 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2700 /* Don't adjust pc-relative references to merge sections in 64-bit
2702 if (use_rela_relocations
2703 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2707 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2708 and changed later by validate_fix. */
2709 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2710 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2713 /* adjust_reloc_syms doesn't know about the GOT. */
2714 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2715 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2716 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2717 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2718 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2719 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2720 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2721 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2722 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2723 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2724 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2725 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2726 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2727 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2728 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2729 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2730 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2731 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2732 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2733 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2734 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2735 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2736 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2737 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2738 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2739 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2740 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2741 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2748 intel_float_operand (const char *mnemonic
)
2750 /* Note that the value returned is meaningful only for opcodes with (memory)
2751 operands, hence the code here is free to improperly handle opcodes that
2752 have no operands (for better performance and smaller code). */
2754 if (mnemonic
[0] != 'f')
2755 return 0; /* non-math */
2757 switch (mnemonic
[1])
2759 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2760 the fs segment override prefix not currently handled because no
2761 call path can make opcodes without operands get here */
2763 return 2 /* integer op */;
2765 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2766 return 3; /* fldcw/fldenv */
2769 if (mnemonic
[2] != 'o' /* fnop */)
2770 return 3; /* non-waiting control op */
2773 if (mnemonic
[2] == 's')
2774 return 3; /* frstor/frstpm */
2777 if (mnemonic
[2] == 'a')
2778 return 3; /* fsave */
2779 if (mnemonic
[2] == 't')
2781 switch (mnemonic
[3])
2783 case 'c': /* fstcw */
2784 case 'd': /* fstdw */
2785 case 'e': /* fstenv */
2786 case 's': /* fsts[gw] */
2792 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2793 return 0; /* fxsave/fxrstor are not really math ops */
2800 /* Build the VEX prefix. */
2803 build_vex_prefix (const insn_template
*t
)
2805 unsigned int register_specifier
;
2806 unsigned int implied_prefix
;
2807 unsigned int vector_length
;
2809 /* Check register specifier. */
2810 if (i
.vex
.register_specifier
)
2812 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2813 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2814 register_specifier
+= 8;
2815 register_specifier
= ~register_specifier
& 0xf;
2818 register_specifier
= 0xf;
2820 /* Use 2-byte VEX prefix by swappping destination and source
2823 && i
.operands
== i
.reg_operands
2824 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2825 && i
.tm
.opcode_modifier
.s
2828 unsigned int xchg
= i
.operands
- 1;
2829 union i386_op temp_op
;
2830 i386_operand_type temp_type
;
2832 temp_type
= i
.types
[xchg
];
2833 i
.types
[xchg
] = i
.types
[0];
2834 i
.types
[0] = temp_type
;
2835 temp_op
= i
.op
[xchg
];
2836 i
.op
[xchg
] = i
.op
[0];
2839 gas_assert (i
.rm
.mode
== 3);
2843 i
.rm
.regmem
= i
.rm
.reg
;
2846 /* Use the next insn. */
2850 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2851 vector_length
= avxscalar
;
2853 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2855 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2860 case DATA_PREFIX_OPCODE
:
2863 case REPE_PREFIX_OPCODE
:
2866 case REPNE_PREFIX_OPCODE
:
2873 /* Use 2-byte VEX prefix if possible. */
2874 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2875 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2876 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2878 /* 2-byte VEX prefix. */
2882 i
.vex
.bytes
[0] = 0xc5;
2884 /* Check the REX.R bit. */
2885 r
= (i
.rex
& REX_R
) ? 0 : 1;
2886 i
.vex
.bytes
[1] = (r
<< 7
2887 | register_specifier
<< 3
2888 | vector_length
<< 2
2893 /* 3-byte VEX prefix. */
2898 switch (i
.tm
.opcode_modifier
.vexopcode
)
2902 i
.vex
.bytes
[0] = 0xc4;
2906 i
.vex
.bytes
[0] = 0xc4;
2910 i
.vex
.bytes
[0] = 0xc4;
2914 i
.vex
.bytes
[0] = 0x8f;
2918 i
.vex
.bytes
[0] = 0x8f;
2922 i
.vex
.bytes
[0] = 0x8f;
2928 /* The high 3 bits of the second VEX byte are 1's compliment
2929 of RXB bits from REX. */
2930 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2932 /* Check the REX.W bit. */
2933 w
= (i
.rex
& REX_W
) ? 1 : 0;
2934 if (i
.tm
.opcode_modifier
.vexw
)
2939 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2943 i
.vex
.bytes
[2] = (w
<< 7
2944 | register_specifier
<< 3
2945 | vector_length
<< 2
2951 process_immext (void)
2955 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2957 /* SSE3 Instructions have the fixed operands with an opcode
2958 suffix which is coded in the same place as an 8-bit immediate
2959 field would be. Here we check those operands and remove them
2963 for (x
= 0; x
< i
.operands
; x
++)
2964 if (i
.op
[x
].regs
->reg_num
!= x
)
2965 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2966 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2972 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2973 which is coded in the same place as an 8-bit immediate field
2974 would be. Here we fake an 8-bit immediate operand from the
2975 opcode suffix stored in tm.extension_opcode.
2977 AVX instructions also use this encoding, for some of
2978 3 argument instructions. */
2980 gas_assert (i
.imm_operands
== 0
2982 || (i
.tm
.opcode_modifier
.vex
2983 && i
.operands
<= 4)));
2985 exp
= &im_expressions
[i
.imm_operands
++];
2986 i
.op
[i
.operands
].imms
= exp
;
2987 i
.types
[i
.operands
] = imm8
;
2989 exp
->X_op
= O_constant
;
2990 exp
->X_add_number
= i
.tm
.extension_opcode
;
2991 i
.tm
.extension_opcode
= None
;
2994 /* This is the guts of the machine-dependent assembler. LINE points to a
2995 machine dependent instruction. This function is supposed to emit
2996 the frags/bytes it assembles to. */
2999 md_assemble (char *line
)
3002 char mnemonic
[MAX_MNEM_SIZE
];
3003 const insn_template
*t
;
3005 /* Initialize globals. */
3006 memset (&i
, '\0', sizeof (i
));
3007 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3008 i
.reloc
[j
] = NO_RELOC
;
3009 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3010 memset (im_expressions
, '\0', sizeof (im_expressions
));
3011 save_stack_p
= save_stack
;
3013 /* First parse an instruction mnemonic & call i386_operand for the operands.
3014 We assume that the scrubber has arranged it so that line[0] is the valid
3015 start of a (possibly prefixed) mnemonic. */
3017 line
= parse_insn (line
, mnemonic
);
3021 line
= parse_operands (line
, mnemonic
);
3026 /* Now we've parsed the mnemonic into a set of templates, and have the
3027 operands at hand. */
3029 /* All intel opcodes have reversed operands except for "bound" and
3030 "enter". We also don't reverse intersegment "jmp" and "call"
3031 instructions with 2 immediate operands so that the immediate segment
3032 precedes the offset, as it does when in AT&T mode. */
3035 && (strcmp (mnemonic
, "bound") != 0)
3036 && (strcmp (mnemonic
, "invlpga") != 0)
3037 && !(operand_type_check (i
.types
[0], imm
)
3038 && operand_type_check (i
.types
[1], imm
)))
3041 /* The order of the immediates should be reversed
3042 for 2 immediates extrq and insertq instructions */
3043 if (i
.imm_operands
== 2
3044 && (strcmp (mnemonic
, "extrq") == 0
3045 || strcmp (mnemonic
, "insertq") == 0))
3046 swap_2_operands (0, 1);
3051 /* Don't optimize displacement for movabs since it only takes 64bit
3054 && !i
.disp32_encoding
3055 && (flag_code
!= CODE_64BIT
3056 || strcmp (mnemonic
, "movabs") != 0))
3059 /* Next, we find a template that matches the given insn,
3060 making sure the overlap of the given operands types is consistent
3061 with the template operand types. */
3063 if (!(t
= match_template ()))
3066 if (sse_check
!= sse_check_none
3067 && !i
.tm
.opcode_modifier
.noavx
3068 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3069 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3070 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3071 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3072 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3073 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3075 (sse_check
== sse_check_warning
3077 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3080 /* Zap movzx and movsx suffix. The suffix has been set from
3081 "word ptr" or "byte ptr" on the source operand in Intel syntax
3082 or extracted from mnemonic in AT&T syntax. But we'll use
3083 the destination register to choose the suffix for encoding. */
3084 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3086 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3087 there is no suffix, the default will be byte extension. */
3088 if (i
.reg_operands
!= 2
3091 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3096 if (i
.tm
.opcode_modifier
.fwait
)
3097 if (!add_prefix (FWAIT_OPCODE
))
3100 /* Check for lock without a lockable instruction. Destination operand
3101 must be memory unless it is xchg (0x86). */
3102 if (i
.prefix
[LOCK_PREFIX
]
3103 && (!i
.tm
.opcode_modifier
.islockable
3104 || i
.mem_operands
== 0
3105 || (i
.tm
.base_opcode
!= 0x86
3106 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3108 as_bad (_("expecting lockable instruction after `lock'"));
3112 /* Check string instruction segment overrides. */
3113 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3115 if (!check_string ())
3117 i
.disp_operands
= 0;
3120 if (!process_suffix ())
3123 /* Update operand types. */
3124 for (j
= 0; j
< i
.operands
; j
++)
3125 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3127 /* Make still unresolved immediate matches conform to size of immediate
3128 given in i.suffix. */
3129 if (!finalize_imm ())
3132 if (i
.types
[0].bitfield
.imm1
)
3133 i
.imm_operands
= 0; /* kludge for shift insns. */
3135 /* We only need to check those implicit registers for instructions
3136 with 3 operands or less. */
3137 if (i
.operands
<= 3)
3138 for (j
= 0; j
< i
.operands
; j
++)
3139 if (i
.types
[j
].bitfield
.inoutportreg
3140 || i
.types
[j
].bitfield
.shiftcount
3141 || i
.types
[j
].bitfield
.acc
3142 || i
.types
[j
].bitfield
.floatacc
)
3145 /* ImmExt should be processed after SSE2AVX. */
3146 if (!i
.tm
.opcode_modifier
.sse2avx
3147 && i
.tm
.opcode_modifier
.immext
)
3150 /* For insns with operands there are more diddles to do to the opcode. */
3153 if (!process_operands ())
3156 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3158 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3159 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3162 if (i
.tm
.opcode_modifier
.vex
)
3163 build_vex_prefix (t
);
3165 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3166 instructions may define INT_OPCODE as well, so avoid this corner
3167 case for those instructions that use MODRM. */
3168 if (i
.tm
.base_opcode
== INT_OPCODE
3169 && !i
.tm
.opcode_modifier
.modrm
3170 && i
.op
[0].imms
->X_add_number
== 3)
3172 i
.tm
.base_opcode
= INT3_OPCODE
;
3176 if ((i
.tm
.opcode_modifier
.jump
3177 || i
.tm
.opcode_modifier
.jumpbyte
3178 || i
.tm
.opcode_modifier
.jumpdword
)
3179 && i
.op
[0].disps
->X_op
== O_constant
)
3181 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3182 the absolute address given by the constant. Since ix86 jumps and
3183 calls are pc relative, we need to generate a reloc. */
3184 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3185 i
.op
[0].disps
->X_op
= O_symbol
;
3188 if (i
.tm
.opcode_modifier
.rex64
)
3191 /* For 8 bit registers we need an empty rex prefix. Also if the
3192 instruction already has a prefix, we need to convert old
3193 registers to new ones. */
3195 if ((i
.types
[0].bitfield
.reg8
3196 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3197 || (i
.types
[1].bitfield
.reg8
3198 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3199 || ((i
.types
[0].bitfield
.reg8
3200 || i
.types
[1].bitfield
.reg8
)
3205 i
.rex
|= REX_OPCODE
;
3206 for (x
= 0; x
< 2; x
++)
3208 /* Look for 8 bit operand that uses old registers. */
3209 if (i
.types
[x
].bitfield
.reg8
3210 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3212 /* In case it is "hi" register, give up. */
3213 if (i
.op
[x
].regs
->reg_num
> 3)
3214 as_bad (_("can't encode register '%s%s' in an "
3215 "instruction requiring REX prefix."),
3216 register_prefix
, i
.op
[x
].regs
->reg_name
);
3218 /* Otherwise it is equivalent to the extended register.
3219 Since the encoding doesn't change this is merely
3220 cosmetic cleanup for debug output. */
3222 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3228 add_prefix (REX_OPCODE
| i
.rex
);
3230 /* We are ready to output the insn. */
3235 parse_insn (char *line
, char *mnemonic
)
3238 char *token_start
= l
;
3241 const insn_template
*t
;
3244 /* Non-zero if we found a prefix only acceptable with string insns. */
3245 const char *expecting_string_instruction
= NULL
;
3250 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3255 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3257 as_bad (_("no such instruction: `%s'"), token_start
);
3262 if (!is_space_char (*l
)
3263 && *l
!= END_OF_INSN
3265 || (*l
!= PREFIX_SEPARATOR
3268 as_bad (_("invalid character %s in mnemonic"),
3269 output_invalid (*l
));
3272 if (token_start
== l
)
3274 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3275 as_bad (_("expecting prefix; got nothing"));
3277 as_bad (_("expecting mnemonic; got nothing"));
3281 /* Look up instruction (or prefix) via hash table. */
3282 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3284 if (*l
!= END_OF_INSN
3285 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3286 && current_templates
3287 && current_templates
->start
->opcode_modifier
.isprefix
)
3289 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3291 as_bad ((flag_code
!= CODE_64BIT
3292 ? _("`%s' is only supported in 64-bit mode")
3293 : _("`%s' is not supported in 64-bit mode")),
3294 current_templates
->start
->name
);
3297 /* If we are in 16-bit mode, do not allow addr16 or data16.
3298 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3299 if ((current_templates
->start
->opcode_modifier
.size16
3300 || current_templates
->start
->opcode_modifier
.size32
)
3301 && flag_code
!= CODE_64BIT
3302 && (current_templates
->start
->opcode_modifier
.size32
3303 ^ (flag_code
== CODE_16BIT
)))
3305 as_bad (_("redundant %s prefix"),
3306 current_templates
->start
->name
);
3309 /* Add prefix, checking for repeated prefixes. */
3310 switch (add_prefix (current_templates
->start
->base_opcode
))
3315 expecting_string_instruction
= current_templates
->start
->name
;
3320 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3327 if (!current_templates
)
3329 /* Check if we should swap operand or force 32bit displacement in
3331 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3333 else if (mnem_p
- 4 == dot_p
3337 i
.disp32_encoding
= 1;
3342 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3345 if (!current_templates
)
3348 /* See if we can get a match by trimming off a suffix. */
3351 case WORD_MNEM_SUFFIX
:
3352 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3353 i
.suffix
= SHORT_MNEM_SUFFIX
;
3355 case BYTE_MNEM_SUFFIX
:
3356 case QWORD_MNEM_SUFFIX
:
3357 i
.suffix
= mnem_p
[-1];
3359 current_templates
= (const templates
*) hash_find (op_hash
,
3362 case SHORT_MNEM_SUFFIX
:
3363 case LONG_MNEM_SUFFIX
:
3366 i
.suffix
= mnem_p
[-1];
3368 current_templates
= (const templates
*) hash_find (op_hash
,
3377 if (intel_float_operand (mnemonic
) == 1)
3378 i
.suffix
= SHORT_MNEM_SUFFIX
;
3380 i
.suffix
= LONG_MNEM_SUFFIX
;
3382 current_templates
= (const templates
*) hash_find (op_hash
,
3387 if (!current_templates
)
3389 as_bad (_("no such instruction: `%s'"), token_start
);
3394 if (current_templates
->start
->opcode_modifier
.jump
3395 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3397 /* Check for a branch hint. We allow ",pt" and ",pn" for
3398 predict taken and predict not taken respectively.
3399 I'm not sure that branch hints actually do anything on loop
3400 and jcxz insns (JumpByte) for current Pentium4 chips. They
3401 may work in the future and it doesn't hurt to accept them
3403 if (l
[0] == ',' && l
[1] == 'p')
3407 if (!add_prefix (DS_PREFIX_OPCODE
))
3411 else if (l
[2] == 'n')
3413 if (!add_prefix (CS_PREFIX_OPCODE
))
3419 /* Any other comma loses. */
3422 as_bad (_("invalid character %s in mnemonic"),
3423 output_invalid (*l
));
3427 /* Check if instruction is supported on specified architecture. */
3429 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3431 supported
|= cpu_flags_match (t
);
3432 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3436 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3438 as_bad (flag_code
== CODE_64BIT
3439 ? _("`%s' is not supported in 64-bit mode")
3440 : _("`%s' is only supported in 64-bit mode"),
3441 current_templates
->start
->name
);
3444 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3446 as_bad (_("`%s' is not supported on `%s%s'"),
3447 current_templates
->start
->name
,
3448 cpu_arch_name
? cpu_arch_name
: default_arch
,
3449 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3454 if (!cpu_arch_flags
.bitfield
.cpui386
3455 && (flag_code
!= CODE_16BIT
))
3457 as_warn (_("use .code16 to ensure correct addressing mode"));
3460 /* Check for rep/repne without a string instruction. */
3461 if (expecting_string_instruction
)
3463 static templates override
;
3465 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3466 if (t
->opcode_modifier
.isstring
)
3468 if (t
>= current_templates
->end
)
3470 as_bad (_("expecting string instruction after `%s'"),
3471 expecting_string_instruction
);
3474 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3475 if (!t
->opcode_modifier
.isstring
)
3478 current_templates
= &override
;
3485 parse_operands (char *l
, const char *mnemonic
)
3489 /* 1 if operand is pending after ','. */
3490 unsigned int expecting_operand
= 0;
3492 /* Non-zero if operand parens not balanced. */
3493 unsigned int paren_not_balanced
;
3495 while (*l
!= END_OF_INSN
)
3497 /* Skip optional white space before operand. */
3498 if (is_space_char (*l
))
3500 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3502 as_bad (_("invalid character %s before operand %d"),
3503 output_invalid (*l
),
3507 token_start
= l
; /* after white space */
3508 paren_not_balanced
= 0;
3509 while (paren_not_balanced
|| *l
!= ',')
3511 if (*l
== END_OF_INSN
)
3513 if (paren_not_balanced
)
3516 as_bad (_("unbalanced parenthesis in operand %d."),
3519 as_bad (_("unbalanced brackets in operand %d."),
3524 break; /* we are done */
3526 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3528 as_bad (_("invalid character %s in operand %d"),
3529 output_invalid (*l
),
3536 ++paren_not_balanced
;
3538 --paren_not_balanced
;
3543 ++paren_not_balanced
;
3545 --paren_not_balanced
;
3549 if (l
!= token_start
)
3550 { /* Yes, we've read in another operand. */
3551 unsigned int operand_ok
;
3552 this_operand
= i
.operands
++;
3553 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3554 if (i
.operands
> MAX_OPERANDS
)
3556 as_bad (_("spurious operands; (%d operands/instruction max)"),
3560 /* Now parse operand adding info to 'i' as we go along. */
3561 END_STRING_AND_SAVE (l
);
3565 i386_intel_operand (token_start
,
3566 intel_float_operand (mnemonic
));
3568 operand_ok
= i386_att_operand (token_start
);
3570 RESTORE_END_STRING (l
);
3576 if (expecting_operand
)
3578 expecting_operand_after_comma
:
3579 as_bad (_("expecting operand after ','; got nothing"));
3584 as_bad (_("expecting operand before ','; got nothing"));
3589 /* Now *l must be either ',' or END_OF_INSN. */
3592 if (*++l
== END_OF_INSN
)
3594 /* Just skip it, if it's \n complain. */
3595 goto expecting_operand_after_comma
;
3597 expecting_operand
= 1;
3604 swap_2_operands (int xchg1
, int xchg2
)
3606 union i386_op temp_op
;
3607 i386_operand_type temp_type
;
3608 enum bfd_reloc_code_real temp_reloc
;
3610 temp_type
= i
.types
[xchg2
];
3611 i
.types
[xchg2
] = i
.types
[xchg1
];
3612 i
.types
[xchg1
] = temp_type
;
3613 temp_op
= i
.op
[xchg2
];
3614 i
.op
[xchg2
] = i
.op
[xchg1
];
3615 i
.op
[xchg1
] = temp_op
;
3616 temp_reloc
= i
.reloc
[xchg2
];
3617 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3618 i
.reloc
[xchg1
] = temp_reloc
;
3622 swap_operands (void)
3628 swap_2_operands (1, i
.operands
- 2);
3631 swap_2_operands (0, i
.operands
- 1);
3637 if (i
.mem_operands
== 2)
3639 const seg_entry
*temp_seg
;
3640 temp_seg
= i
.seg
[0];
3641 i
.seg
[0] = i
.seg
[1];
3642 i
.seg
[1] = temp_seg
;
3646 /* Try to ensure constant immediates are represented in the smallest
3651 char guess_suffix
= 0;
3655 guess_suffix
= i
.suffix
;
3656 else if (i
.reg_operands
)
3658 /* Figure out a suffix from the last register operand specified.
3659 We can't do this properly yet, ie. excluding InOutPortReg,
3660 but the following works for instructions with immediates.
3661 In any case, we can't set i.suffix yet. */
3662 for (op
= i
.operands
; --op
>= 0;)
3663 if (i
.types
[op
].bitfield
.reg8
)
3665 guess_suffix
= BYTE_MNEM_SUFFIX
;
3668 else if (i
.types
[op
].bitfield
.reg16
)
3670 guess_suffix
= WORD_MNEM_SUFFIX
;
3673 else if (i
.types
[op
].bitfield
.reg32
)
3675 guess_suffix
= LONG_MNEM_SUFFIX
;
3678 else if (i
.types
[op
].bitfield
.reg64
)
3680 guess_suffix
= QWORD_MNEM_SUFFIX
;
3684 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3685 guess_suffix
= WORD_MNEM_SUFFIX
;
3687 for (op
= i
.operands
; --op
>= 0;)
3688 if (operand_type_check (i
.types
[op
], imm
))
3690 switch (i
.op
[op
].imms
->X_op
)
3693 /* If a suffix is given, this operand may be shortened. */
3694 switch (guess_suffix
)
3696 case LONG_MNEM_SUFFIX
:
3697 i
.types
[op
].bitfield
.imm32
= 1;
3698 i
.types
[op
].bitfield
.imm64
= 1;
3700 case WORD_MNEM_SUFFIX
:
3701 i
.types
[op
].bitfield
.imm16
= 1;
3702 i
.types
[op
].bitfield
.imm32
= 1;
3703 i
.types
[op
].bitfield
.imm32s
= 1;
3704 i
.types
[op
].bitfield
.imm64
= 1;
3706 case BYTE_MNEM_SUFFIX
:
3707 i
.types
[op
].bitfield
.imm8
= 1;
3708 i
.types
[op
].bitfield
.imm8s
= 1;
3709 i
.types
[op
].bitfield
.imm16
= 1;
3710 i
.types
[op
].bitfield
.imm32
= 1;
3711 i
.types
[op
].bitfield
.imm32s
= 1;
3712 i
.types
[op
].bitfield
.imm64
= 1;
3716 /* If this operand is at most 16 bits, convert it
3717 to a signed 16 bit number before trying to see
3718 whether it will fit in an even smaller size.
3719 This allows a 16-bit operand such as $0xffe0 to
3720 be recognised as within Imm8S range. */
3721 if ((i
.types
[op
].bitfield
.imm16
)
3722 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3724 i
.op
[op
].imms
->X_add_number
=
3725 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3727 if ((i
.types
[op
].bitfield
.imm32
)
3728 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3731 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3732 ^ ((offsetT
) 1 << 31))
3733 - ((offsetT
) 1 << 31));
3736 = operand_type_or (i
.types
[op
],
3737 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3739 /* We must avoid matching of Imm32 templates when 64bit
3740 only immediate is available. */
3741 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3742 i
.types
[op
].bitfield
.imm32
= 0;
3749 /* Symbols and expressions. */
3751 /* Convert symbolic operand to proper sizes for matching, but don't
3752 prevent matching a set of insns that only supports sizes other
3753 than those matching the insn suffix. */
3755 i386_operand_type mask
, allowed
;
3756 const insn_template
*t
;
3758 operand_type_set (&mask
, 0);
3759 operand_type_set (&allowed
, 0);
3761 for (t
= current_templates
->start
;
3762 t
< current_templates
->end
;
3764 allowed
= operand_type_or (allowed
,
3765 t
->operand_types
[op
]);
3766 switch (guess_suffix
)
3768 case QWORD_MNEM_SUFFIX
:
3769 mask
.bitfield
.imm64
= 1;
3770 mask
.bitfield
.imm32s
= 1;
3772 case LONG_MNEM_SUFFIX
:
3773 mask
.bitfield
.imm32
= 1;
3775 case WORD_MNEM_SUFFIX
:
3776 mask
.bitfield
.imm16
= 1;
3778 case BYTE_MNEM_SUFFIX
:
3779 mask
.bitfield
.imm8
= 1;
3784 allowed
= operand_type_and (mask
, allowed
);
3785 if (!operand_type_all_zero (&allowed
))
3786 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3793 /* Try to use the smallest displacement type too. */
3795 optimize_disp (void)
3799 for (op
= i
.operands
; --op
>= 0;)
3800 if (operand_type_check (i
.types
[op
], disp
))
3802 if (i
.op
[op
].disps
->X_op
== O_constant
)
3804 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3806 if (i
.types
[op
].bitfield
.disp16
3807 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3809 /* If this operand is at most 16 bits, convert
3810 to a signed 16 bit number and don't use 64bit
3812 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3813 i
.types
[op
].bitfield
.disp64
= 0;
3815 if (i
.types
[op
].bitfield
.disp32
3816 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3818 /* If this operand is at most 32 bits, convert
3819 to a signed 32 bit number and don't use 64bit
3821 op_disp
&= (((offsetT
) 2 << 31) - 1);
3822 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3823 i
.types
[op
].bitfield
.disp64
= 0;
3825 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3827 i
.types
[op
].bitfield
.disp8
= 0;
3828 i
.types
[op
].bitfield
.disp16
= 0;
3829 i
.types
[op
].bitfield
.disp32
= 0;
3830 i
.types
[op
].bitfield
.disp32s
= 0;
3831 i
.types
[op
].bitfield
.disp64
= 0;
3835 else if (flag_code
== CODE_64BIT
)
3837 if (fits_in_signed_long (op_disp
))
3839 i
.types
[op
].bitfield
.disp64
= 0;
3840 i
.types
[op
].bitfield
.disp32s
= 1;
3842 if (i
.prefix
[ADDR_PREFIX
]
3843 && fits_in_unsigned_long (op_disp
))
3844 i
.types
[op
].bitfield
.disp32
= 1;
3846 if ((i
.types
[op
].bitfield
.disp32
3847 || i
.types
[op
].bitfield
.disp32s
3848 || i
.types
[op
].bitfield
.disp16
)
3849 && fits_in_signed_byte (op_disp
))
3850 i
.types
[op
].bitfield
.disp8
= 1;
3852 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3853 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3855 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3856 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3857 i
.types
[op
].bitfield
.disp8
= 0;
3858 i
.types
[op
].bitfield
.disp16
= 0;
3859 i
.types
[op
].bitfield
.disp32
= 0;
3860 i
.types
[op
].bitfield
.disp32s
= 0;
3861 i
.types
[op
].bitfield
.disp64
= 0;
3864 /* We only support 64bit displacement on constants. */
3865 i
.types
[op
].bitfield
.disp64
= 0;
3869 /* Check if operands are valid for the instruction. */
3872 check_VecOperands (const insn_template
*t
)
3874 /* Without VSIB byte, we can't have a vector register for index. */
3875 if (!t
->opcode_modifier
.vecsib
3877 && (i
.index_reg
->reg_type
.bitfield
.regxmm
3878 || i
.index_reg
->reg_type
.bitfield
.regymm
))
3880 i
.error
= unsupported_vector_index_register
;
3884 /* For VSIB byte, we need a vector register for index and no PC
3885 relative addressing is allowed. */
3886 if (t
->opcode_modifier
.vecsib
3888 || !((t
->opcode_modifier
.vecsib
== VecSIB128
3889 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
3890 || (t
->opcode_modifier
.vecsib
== VecSIB256
3891 && i
.index_reg
->reg_type
.bitfield
.regymm
))
3892 || (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)))
3894 i
.error
= invalid_vsib_address
;
3901 /* Check if operands are valid for the instruction. Update VEX
3905 VEX_check_operands (const insn_template
*t
)
3907 if (!t
->opcode_modifier
.vex
)
3910 /* Only check VEX_Imm4, which must be the first operand. */
3911 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3913 if (i
.op
[0].imms
->X_op
!= O_constant
3914 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3920 /* Turn off Imm8 so that update_imm won't complain. */
3921 i
.types
[0] = vec_imm4
;
3927 static const insn_template
*
3928 match_template (void)
3930 /* Points to template once we've found it. */
3931 const insn_template
*t
;
3932 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3933 i386_operand_type overlap4
;
3934 unsigned int found_reverse_match
;
3935 i386_opcode_modifier suffix_check
;
3936 i386_operand_type operand_types
[MAX_OPERANDS
];
3937 int addr_prefix_disp
;
3939 unsigned int found_cpu_match
;
3940 unsigned int check_register
;
3942 #if MAX_OPERANDS != 5
3943 # error "MAX_OPERANDS must be 5."
3946 found_reverse_match
= 0;
3947 addr_prefix_disp
= -1;
3949 memset (&suffix_check
, 0, sizeof (suffix_check
));
3950 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3951 suffix_check
.no_bsuf
= 1;
3952 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3953 suffix_check
.no_wsuf
= 1;
3954 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3955 suffix_check
.no_ssuf
= 1;
3956 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3957 suffix_check
.no_lsuf
= 1;
3958 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3959 suffix_check
.no_qsuf
= 1;
3960 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3961 suffix_check
.no_ldsuf
= 1;
3963 /* Must have right number of operands. */
3964 i
.error
= number_of_operands_mismatch
;
3966 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3968 addr_prefix_disp
= -1;
3970 if (i
.operands
!= t
->operands
)
3973 /* Check processor support. */
3974 i
.error
= unsupported
;
3975 found_cpu_match
= (cpu_flags_match (t
)
3976 == CPU_FLAGS_PERFECT_MATCH
);
3977 if (!found_cpu_match
)
3980 /* Check old gcc support. */
3981 i
.error
= old_gcc_only
;
3982 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3985 /* Check AT&T mnemonic. */
3986 i
.error
= unsupported_with_intel_mnemonic
;
3987 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3990 /* Check AT&T/Intel syntax. */
3991 i
.error
= unsupported_syntax
;
3992 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3993 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3996 /* Check the suffix, except for some instructions in intel mode. */
3997 i
.error
= invalid_instruction_suffix
;
3998 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3999 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4000 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4001 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4002 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4003 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4004 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4007 if (!operand_size_match (t
))
4010 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4011 operand_types
[j
] = t
->operand_types
[j
];
4013 /* In general, don't allow 64-bit operands in 32-bit mode. */
4014 if (i
.suffix
== QWORD_MNEM_SUFFIX
4015 && flag_code
!= CODE_64BIT
4017 ? (!t
->opcode_modifier
.ignoresize
4018 && !intel_float_operand (t
->name
))
4019 : intel_float_operand (t
->name
) != 2)
4020 && ((!operand_types
[0].bitfield
.regmmx
4021 && !operand_types
[0].bitfield
.regxmm
4022 && !operand_types
[0].bitfield
.regymm
)
4023 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4024 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4025 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
4026 && (t
->base_opcode
!= 0x0fc7
4027 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4030 /* In general, don't allow 32-bit operands on pre-386. */
4031 else if (i
.suffix
== LONG_MNEM_SUFFIX
4032 && !cpu_arch_flags
.bitfield
.cpui386
4034 ? (!t
->opcode_modifier
.ignoresize
4035 && !intel_float_operand (t
->name
))
4036 : intel_float_operand (t
->name
) != 2)
4037 && ((!operand_types
[0].bitfield
.regmmx
4038 && !operand_types
[0].bitfield
.regxmm
)
4039 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4040 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4043 /* Do not verify operands when there are none. */
4047 /* We've found a match; break out of loop. */
4051 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4052 into Disp32/Disp16/Disp32 operand. */
4053 if (i
.prefix
[ADDR_PREFIX
] != 0)
4055 /* There should be only one Disp operand. */
4059 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4061 if (operand_types
[j
].bitfield
.disp16
)
4063 addr_prefix_disp
= j
;
4064 operand_types
[j
].bitfield
.disp32
= 1;
4065 operand_types
[j
].bitfield
.disp16
= 0;
4071 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4073 if (operand_types
[j
].bitfield
.disp32
)
4075 addr_prefix_disp
= j
;
4076 operand_types
[j
].bitfield
.disp32
= 0;
4077 operand_types
[j
].bitfield
.disp16
= 1;
4083 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4085 if (operand_types
[j
].bitfield
.disp64
)
4087 addr_prefix_disp
= j
;
4088 operand_types
[j
].bitfield
.disp64
= 0;
4089 operand_types
[j
].bitfield
.disp32
= 1;
4097 /* We check register size if needed. */
4098 check_register
= t
->opcode_modifier
.checkregsize
;
4099 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4100 switch (t
->operands
)
4103 if (!operand_type_match (overlap0
, i
.types
[0]))
4107 /* xchg %eax, %eax is a special case. It is an aliase for nop
4108 only in 32bit mode and we can use opcode 0x90. In 64bit
4109 mode, we can't use 0x90 for xchg %eax, %eax since it should
4110 zero-extend %eax to %rax. */
4111 if (flag_code
== CODE_64BIT
4112 && t
->base_opcode
== 0x90
4113 && operand_type_equal (&i
.types
[0], &acc32
)
4114 && operand_type_equal (&i
.types
[1], &acc32
))
4118 /* If we swap operand in encoding, we either match
4119 the next one or reverse direction of operands. */
4120 if (t
->opcode_modifier
.s
)
4122 else if (t
->opcode_modifier
.d
)
4127 /* If we swap operand in encoding, we match the next one. */
4128 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4132 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4133 if (!operand_type_match (overlap0
, i
.types
[0])
4134 || !operand_type_match (overlap1
, i
.types
[1])
4136 && !operand_type_register_match (overlap0
, i
.types
[0],
4138 overlap1
, i
.types
[1],
4141 /* Check if other direction is valid ... */
4142 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4146 /* Try reversing direction of operands. */
4147 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4148 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4149 if (!operand_type_match (overlap0
, i
.types
[0])
4150 || !operand_type_match (overlap1
, i
.types
[1])
4152 && !operand_type_register_match (overlap0
,
4159 /* Does not match either direction. */
4162 /* found_reverse_match holds which of D or FloatDR
4164 if (t
->opcode_modifier
.d
)
4165 found_reverse_match
= Opcode_D
;
4166 else if (t
->opcode_modifier
.floatd
)
4167 found_reverse_match
= Opcode_FloatD
;
4169 found_reverse_match
= 0;
4170 if (t
->opcode_modifier
.floatr
)
4171 found_reverse_match
|= Opcode_FloatR
;
4175 /* Found a forward 2 operand match here. */
4176 switch (t
->operands
)
4179 overlap4
= operand_type_and (i
.types
[4],
4182 overlap3
= operand_type_and (i
.types
[3],
4185 overlap2
= operand_type_and (i
.types
[2],
4190 switch (t
->operands
)
4193 if (!operand_type_match (overlap4
, i
.types
[4])
4194 || !operand_type_register_match (overlap3
,
4202 if (!operand_type_match (overlap3
, i
.types
[3])
4204 && !operand_type_register_match (overlap2
,
4212 /* Here we make use of the fact that there are no
4213 reverse match 3 operand instructions, and all 3
4214 operand instructions only need to be checked for
4215 register consistency between operands 2 and 3. */
4216 if (!operand_type_match (overlap2
, i
.types
[2])
4218 && !operand_type_register_match (overlap1
,
4228 /* Found either forward/reverse 2, 3 or 4 operand match here:
4229 slip through to break. */
4231 if (!found_cpu_match
)
4233 found_reverse_match
= 0;
4237 /* Check if vector operands are valid. */
4238 if (check_VecOperands (t
))
4241 /* Check if VEX operands are valid. */
4242 if (VEX_check_operands (t
))
4245 /* We've found a match; break out of loop. */
4249 if (t
== current_templates
->end
)
4251 /* We found no match. */
4252 const char *err_msg
;
4257 case operand_size_mismatch
:
4258 err_msg
= _("operand size mismatch");
4260 case operand_type_mismatch
:
4261 err_msg
= _("operand type mismatch");
4263 case register_type_mismatch
:
4264 err_msg
= _("register type mismatch");
4266 case number_of_operands_mismatch
:
4267 err_msg
= _("number of operands mismatch");
4269 case invalid_instruction_suffix
:
4270 err_msg
= _("invalid instruction suffix");
4273 err_msg
= _("Imm4 isn't the first operand");
4276 err_msg
= _("only supported with old gcc");
4278 case unsupported_with_intel_mnemonic
:
4279 err_msg
= _("unsupported with Intel mnemonic");
4281 case unsupported_syntax
:
4282 err_msg
= _("unsupported syntax");
4285 err_msg
= _("unsupported");
4287 case invalid_vsib_address
:
4288 err_msg
= _("invalid VSIB address");
4290 case unsupported_vector_index_register
:
4291 err_msg
= _("unsupported vector index register");
4294 as_bad (_("%s for `%s'"), err_msg
,
4295 current_templates
->start
->name
);
4299 if (!quiet_warnings
)
4302 && (i
.types
[0].bitfield
.jumpabsolute
4303 != operand_types
[0].bitfield
.jumpabsolute
))
4305 as_warn (_("indirect %s without `*'"), t
->name
);
4308 if (t
->opcode_modifier
.isprefix
4309 && t
->opcode_modifier
.ignoresize
)
4311 /* Warn them that a data or address size prefix doesn't
4312 affect assembly of the next line of code. */
4313 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4317 /* Copy the template we found. */
4320 if (addr_prefix_disp
!= -1)
4321 i
.tm
.operand_types
[addr_prefix_disp
]
4322 = operand_types
[addr_prefix_disp
];
4324 if (found_reverse_match
)
4326 /* If we found a reverse match we must alter the opcode
4327 direction bit. found_reverse_match holds bits to change
4328 (different for int & float insns). */
4330 i
.tm
.base_opcode
^= found_reverse_match
;
4332 i
.tm
.operand_types
[0] = operand_types
[1];
4333 i
.tm
.operand_types
[1] = operand_types
[0];
4342 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4343 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4345 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4347 as_bad (_("`%s' operand %d must use `%ses' segment"),
4353 /* There's only ever one segment override allowed per instruction.
4354 This instruction possibly has a legal segment override on the
4355 second operand, so copy the segment to where non-string
4356 instructions store it, allowing common code. */
4357 i
.seg
[0] = i
.seg
[1];
4359 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4361 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4363 as_bad (_("`%s' operand %d must use `%ses' segment"),
4374 process_suffix (void)
4376 /* If matched instruction specifies an explicit instruction mnemonic
4378 if (i
.tm
.opcode_modifier
.size16
)
4379 i
.suffix
= WORD_MNEM_SUFFIX
;
4380 else if (i
.tm
.opcode_modifier
.size32
)
4381 i
.suffix
= LONG_MNEM_SUFFIX
;
4382 else if (i
.tm
.opcode_modifier
.size64
)
4383 i
.suffix
= QWORD_MNEM_SUFFIX
;
4384 else if (i
.reg_operands
)
4386 /* If there's no instruction mnemonic suffix we try to invent one
4387 based on register operands. */
4390 /* We take i.suffix from the last register operand specified,
4391 Destination register type is more significant than source
4392 register type. crc32 in SSE4.2 prefers source register
4394 if (i
.tm
.base_opcode
== 0xf20f38f1)
4396 if (i
.types
[0].bitfield
.reg16
)
4397 i
.suffix
= WORD_MNEM_SUFFIX
;
4398 else if (i
.types
[0].bitfield
.reg32
)
4399 i
.suffix
= LONG_MNEM_SUFFIX
;
4400 else if (i
.types
[0].bitfield
.reg64
)
4401 i
.suffix
= QWORD_MNEM_SUFFIX
;
4403 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4405 if (i
.types
[0].bitfield
.reg8
)
4406 i
.suffix
= BYTE_MNEM_SUFFIX
;
4413 if (i
.tm
.base_opcode
== 0xf20f38f1
4414 || i
.tm
.base_opcode
== 0xf20f38f0)
4416 /* We have to know the operand size for crc32. */
4417 as_bad (_("ambiguous memory operand size for `%s`"),
4422 for (op
= i
.operands
; --op
>= 0;)
4423 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4425 if (i
.types
[op
].bitfield
.reg8
)
4427 i
.suffix
= BYTE_MNEM_SUFFIX
;
4430 else if (i
.types
[op
].bitfield
.reg16
)
4432 i
.suffix
= WORD_MNEM_SUFFIX
;
4435 else if (i
.types
[op
].bitfield
.reg32
)
4437 i
.suffix
= LONG_MNEM_SUFFIX
;
4440 else if (i
.types
[op
].bitfield
.reg64
)
4442 i
.suffix
= QWORD_MNEM_SUFFIX
;
4448 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4451 && i
.tm
.opcode_modifier
.ignoresize
4452 && i
.tm
.opcode_modifier
.no_bsuf
)
4454 else if (!check_byte_reg ())
4457 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4460 && i
.tm
.opcode_modifier
.ignoresize
4461 && i
.tm
.opcode_modifier
.no_lsuf
)
4463 else if (!check_long_reg ())
4466 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4469 && i
.tm
.opcode_modifier
.ignoresize
4470 && i
.tm
.opcode_modifier
.no_qsuf
)
4472 else if (!check_qword_reg ())
4475 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4478 && i
.tm
.opcode_modifier
.ignoresize
4479 && i
.tm
.opcode_modifier
.no_wsuf
)
4481 else if (!check_word_reg ())
4484 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4485 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4487 /* Skip if the instruction has x/y suffix. match_template
4488 should check if it is a valid suffix. */
4490 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4491 /* Do nothing if the instruction is going to ignore the prefix. */
4496 else if (i
.tm
.opcode_modifier
.defaultsize
4498 /* exclude fldenv/frstor/fsave/fstenv */
4499 && i
.tm
.opcode_modifier
.no_ssuf
)
4501 i
.suffix
= stackop_size
;
4503 else if (intel_syntax
4505 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4506 || i
.tm
.opcode_modifier
.jumpbyte
4507 || i
.tm
.opcode_modifier
.jumpintersegment
4508 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4509 && i
.tm
.extension_opcode
<= 3)))
4514 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4516 i
.suffix
= QWORD_MNEM_SUFFIX
;
4520 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4521 i
.suffix
= LONG_MNEM_SUFFIX
;
4524 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4525 i
.suffix
= WORD_MNEM_SUFFIX
;
4534 if (i
.tm
.opcode_modifier
.w
)
4536 as_bad (_("no instruction mnemonic suffix given and "
4537 "no register operands; can't size instruction"));
4543 unsigned int suffixes
;
4545 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4546 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4548 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4550 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4552 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4554 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4557 /* There are more than suffix matches. */
4558 if (i
.tm
.opcode_modifier
.w
4559 || ((suffixes
& (suffixes
- 1))
4560 && !i
.tm
.opcode_modifier
.defaultsize
4561 && !i
.tm
.opcode_modifier
.ignoresize
))
4563 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4569 /* Change the opcode based on the operand size given by i.suffix;
4570 We don't need to change things for byte insns. */
4573 && i
.suffix
!= BYTE_MNEM_SUFFIX
4574 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4575 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4577 /* It's not a byte, select word/dword operation. */
4578 if (i
.tm
.opcode_modifier
.w
)
4580 if (i
.tm
.opcode_modifier
.shortform
)
4581 i
.tm
.base_opcode
|= 8;
4583 i
.tm
.base_opcode
|= 1;
4586 /* Now select between word & dword operations via the operand
4587 size prefix, except for instructions that will ignore this
4589 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4591 /* The address size override prefix changes the size of the
4593 if ((flag_code
== CODE_32BIT
4594 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4595 || (flag_code
!= CODE_32BIT
4596 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4597 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4600 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4601 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4602 && !i
.tm
.opcode_modifier
.ignoresize
4603 && !i
.tm
.opcode_modifier
.floatmf
4604 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4605 || (flag_code
== CODE_64BIT
4606 && i
.tm
.opcode_modifier
.jumpbyte
)))
4608 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4610 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4611 prefix
= ADDR_PREFIX_OPCODE
;
4613 if (!add_prefix (prefix
))
4617 /* Set mode64 for an operand. */
4618 if (i
.suffix
== QWORD_MNEM_SUFFIX
4619 && flag_code
== CODE_64BIT
4620 && !i
.tm
.opcode_modifier
.norex64
)
4622 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4623 need rex64. cmpxchg8b is also a special case. */
4624 if (! (i
.operands
== 2
4625 && i
.tm
.base_opcode
== 0x90
4626 && i
.tm
.extension_opcode
== None
4627 && operand_type_equal (&i
.types
[0], &acc64
)
4628 && operand_type_equal (&i
.types
[1], &acc64
))
4629 && ! (i
.operands
== 1
4630 && i
.tm
.base_opcode
== 0xfc7
4631 && i
.tm
.extension_opcode
== 1
4632 && !operand_type_check (i
.types
[0], reg
)
4633 && operand_type_check (i
.types
[0], anymem
)))
4637 /* Size floating point instruction. */
4638 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4639 if (i
.tm
.opcode_modifier
.floatmf
)
4640 i
.tm
.base_opcode
^= 4;
4647 check_byte_reg (void)
4651 for (op
= i
.operands
; --op
>= 0;)
4653 /* If this is an eight bit register, it's OK. If it's the 16 or
4654 32 bit version of an eight bit register, we will just use the
4655 low portion, and that's OK too. */
4656 if (i
.types
[op
].bitfield
.reg8
)
4659 /* crc32 doesn't generate this warning. */
4660 if (i
.tm
.base_opcode
== 0xf20f38f0)
4663 if ((i
.types
[op
].bitfield
.reg16
4664 || i
.types
[op
].bitfield
.reg32
4665 || i
.types
[op
].bitfield
.reg64
)
4666 && i
.op
[op
].regs
->reg_num
< 4)
4668 /* Prohibit these changes in the 64bit mode, since the
4669 lowering is more complicated. */
4670 if (flag_code
== CODE_64BIT
4671 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4673 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4674 register_prefix
, i
.op
[op
].regs
->reg_name
,
4678 #if REGISTER_WARNINGS
4680 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4681 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4683 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4684 ? REGNAM_AL
- REGNAM_AX
4685 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4687 i
.op
[op
].regs
->reg_name
,
4692 /* Any other register is bad. */
4693 if (i
.types
[op
].bitfield
.reg16
4694 || i
.types
[op
].bitfield
.reg32
4695 || i
.types
[op
].bitfield
.reg64
4696 || i
.types
[op
].bitfield
.regmmx
4697 || i
.types
[op
].bitfield
.regxmm
4698 || i
.types
[op
].bitfield
.regymm
4699 || i
.types
[op
].bitfield
.sreg2
4700 || i
.types
[op
].bitfield
.sreg3
4701 || i
.types
[op
].bitfield
.control
4702 || i
.types
[op
].bitfield
.debug
4703 || i
.types
[op
].bitfield
.test
4704 || i
.types
[op
].bitfield
.floatreg
4705 || i
.types
[op
].bitfield
.floatacc
)
4707 as_bad (_("`%s%s' not allowed with `%s%c'"),
4709 i
.op
[op
].regs
->reg_name
,
4719 check_long_reg (void)
4723 for (op
= i
.operands
; --op
>= 0;)
4724 /* Reject eight bit registers, except where the template requires
4725 them. (eg. movzb) */
4726 if (i
.types
[op
].bitfield
.reg8
4727 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4728 || i
.tm
.operand_types
[op
].bitfield
.reg32
4729 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4731 as_bad (_("`%s%s' not allowed with `%s%c'"),
4733 i
.op
[op
].regs
->reg_name
,
4738 /* Warn if the e prefix on a general reg is missing. */
4739 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4740 && i
.types
[op
].bitfield
.reg16
4741 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4742 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4744 /* Prohibit these changes in the 64bit mode, since the
4745 lowering is more complicated. */
4746 if (flag_code
== CODE_64BIT
)
4748 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4749 register_prefix
, i
.op
[op
].regs
->reg_name
,
4753 #if REGISTER_WARNINGS
4755 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4757 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4759 i
.op
[op
].regs
->reg_name
,
4763 /* Warn if the r prefix on a general reg is missing. */
4764 else if (i
.types
[op
].bitfield
.reg64
4765 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4766 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4769 && i
.tm
.opcode_modifier
.toqword
4770 && !i
.types
[0].bitfield
.regxmm
)
4772 /* Convert to QWORD. We want REX byte. */
4773 i
.suffix
= QWORD_MNEM_SUFFIX
;
4777 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4778 register_prefix
, i
.op
[op
].regs
->reg_name
,
4787 check_qword_reg (void)
4791 for (op
= i
.operands
; --op
>= 0; )
4792 /* Reject eight bit registers, except where the template requires
4793 them. (eg. movzb) */
4794 if (i
.types
[op
].bitfield
.reg8
4795 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4796 || i
.tm
.operand_types
[op
].bitfield
.reg32
4797 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4799 as_bad (_("`%s%s' not allowed with `%s%c'"),
4801 i
.op
[op
].regs
->reg_name
,
4806 /* Warn if the e prefix on a general reg is missing. */
4807 else if ((i
.types
[op
].bitfield
.reg16
4808 || i
.types
[op
].bitfield
.reg32
)
4809 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4810 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4812 /* Prohibit these changes in the 64bit mode, since the
4813 lowering is more complicated. */
4815 && i
.tm
.opcode_modifier
.todword
4816 && !i
.types
[0].bitfield
.regxmm
)
4818 /* Convert to DWORD. We don't want REX byte. */
4819 i
.suffix
= LONG_MNEM_SUFFIX
;
4823 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4824 register_prefix
, i
.op
[op
].regs
->reg_name
,
4833 check_word_reg (void)
4836 for (op
= i
.operands
; --op
>= 0;)
4837 /* Reject eight bit registers, except where the template requires
4838 them. (eg. movzb) */
4839 if (i
.types
[op
].bitfield
.reg8
4840 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4841 || i
.tm
.operand_types
[op
].bitfield
.reg32
4842 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4844 as_bad (_("`%s%s' not allowed with `%s%c'"),
4846 i
.op
[op
].regs
->reg_name
,
4851 /* Warn if the e prefix on a general reg is present. */
4852 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4853 && i
.types
[op
].bitfield
.reg32
4854 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4855 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4857 /* Prohibit these changes in the 64bit mode, since the
4858 lowering is more complicated. */
4859 if (flag_code
== CODE_64BIT
)
4861 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4862 register_prefix
, i
.op
[op
].regs
->reg_name
,
4867 #if REGISTER_WARNINGS
4868 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4870 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4872 i
.op
[op
].regs
->reg_name
,
4880 update_imm (unsigned int j
)
4882 i386_operand_type overlap
= i
.types
[j
];
4883 if ((overlap
.bitfield
.imm8
4884 || overlap
.bitfield
.imm8s
4885 || overlap
.bitfield
.imm16
4886 || overlap
.bitfield
.imm32
4887 || overlap
.bitfield
.imm32s
4888 || overlap
.bitfield
.imm64
)
4889 && !operand_type_equal (&overlap
, &imm8
)
4890 && !operand_type_equal (&overlap
, &imm8s
)
4891 && !operand_type_equal (&overlap
, &imm16
)
4892 && !operand_type_equal (&overlap
, &imm32
)
4893 && !operand_type_equal (&overlap
, &imm32s
)
4894 && !operand_type_equal (&overlap
, &imm64
))
4898 i386_operand_type temp
;
4900 operand_type_set (&temp
, 0);
4901 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4903 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4904 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4906 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4907 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4908 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4910 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4911 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4914 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4917 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4918 || operand_type_equal (&overlap
, &imm16_32
)
4919 || operand_type_equal (&overlap
, &imm16_32s
))
4921 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4926 if (!operand_type_equal (&overlap
, &imm8
)
4927 && !operand_type_equal (&overlap
, &imm8s
)
4928 && !operand_type_equal (&overlap
, &imm16
)
4929 && !operand_type_equal (&overlap
, &imm32
)
4930 && !operand_type_equal (&overlap
, &imm32s
)
4931 && !operand_type_equal (&overlap
, &imm64
))
4933 as_bad (_("no instruction mnemonic suffix given; "
4934 "can't determine immediate size"));
4938 i
.types
[j
] = overlap
;
4948 /* Update the first 2 immediate operands. */
4949 n
= i
.operands
> 2 ? 2 : i
.operands
;
4952 for (j
= 0; j
< n
; j
++)
4953 if (update_imm (j
) == 0)
4956 /* The 3rd operand can't be immediate operand. */
4957 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4964 bad_implicit_operand (int xmm
)
4966 const char *ireg
= xmm
? "xmm0" : "ymm0";
4969 as_bad (_("the last operand of `%s' must be `%s%s'"),
4970 i
.tm
.name
, register_prefix
, ireg
);
4972 as_bad (_("the first operand of `%s' must be `%s%s'"),
4973 i
.tm
.name
, register_prefix
, ireg
);
4978 process_operands (void)
4980 /* Default segment register this instruction will use for memory
4981 accesses. 0 means unknown. This is only for optimizing out
4982 unnecessary segment overrides. */
4983 const seg_entry
*default_seg
= 0;
4985 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4987 unsigned int dupl
= i
.operands
;
4988 unsigned int dest
= dupl
- 1;
4991 /* The destination must be an xmm register. */
4992 gas_assert (i
.reg_operands
4993 && MAX_OPERANDS
> dupl
4994 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4996 if (i
.tm
.opcode_modifier
.firstxmm0
)
4998 /* The first operand is implicit and must be xmm0. */
4999 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5000 if (i
.op
[0].regs
->reg_num
!= 0)
5001 return bad_implicit_operand (1);
5003 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5005 /* Keep xmm0 for instructions with VEX prefix and 3
5011 /* We remove the first xmm0 and keep the number of
5012 operands unchanged, which in fact duplicates the
5014 for (j
= 1; j
< i
.operands
; j
++)
5016 i
.op
[j
- 1] = i
.op
[j
];
5017 i
.types
[j
- 1] = i
.types
[j
];
5018 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5022 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5024 gas_assert ((MAX_OPERANDS
- 1) > dupl
5025 && (i
.tm
.opcode_modifier
.vexsources
5028 /* Add the implicit xmm0 for instructions with VEX prefix
5030 for (j
= i
.operands
; j
> 0; j
--)
5032 i
.op
[j
] = i
.op
[j
- 1];
5033 i
.types
[j
] = i
.types
[j
- 1];
5034 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5037 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5038 i
.types
[0] = regxmm
;
5039 i
.tm
.operand_types
[0] = regxmm
;
5042 i
.reg_operands
+= 2;
5047 i
.op
[dupl
] = i
.op
[dest
];
5048 i
.types
[dupl
] = i
.types
[dest
];
5049 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5058 i
.op
[dupl
] = i
.op
[dest
];
5059 i
.types
[dupl
] = i
.types
[dest
];
5060 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5063 if (i
.tm
.opcode_modifier
.immext
)
5066 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5070 /* The first operand is implicit and must be xmm0/ymm0. */
5071 gas_assert (i
.reg_operands
5072 && (operand_type_equal (&i
.types
[0], ®xmm
)
5073 || operand_type_equal (&i
.types
[0], ®ymm
)));
5074 if (i
.op
[0].regs
->reg_num
!= 0)
5075 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5077 for (j
= 1; j
< i
.operands
; j
++)
5079 i
.op
[j
- 1] = i
.op
[j
];
5080 i
.types
[j
- 1] = i
.types
[j
];
5082 /* We need to adjust fields in i.tm since they are used by
5083 build_modrm_byte. */
5084 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5091 else if (i
.tm
.opcode_modifier
.regkludge
)
5093 /* The imul $imm, %reg instruction is converted into
5094 imul $imm, %reg, %reg, and the clr %reg instruction
5095 is converted into xor %reg, %reg. */
5097 unsigned int first_reg_op
;
5099 if (operand_type_check (i
.types
[0], reg
))
5103 /* Pretend we saw the extra register operand. */
5104 gas_assert (i
.reg_operands
== 1
5105 && i
.op
[first_reg_op
+ 1].regs
== 0);
5106 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5107 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5112 if (i
.tm
.opcode_modifier
.shortform
)
5114 if (i
.types
[0].bitfield
.sreg2
5115 || i
.types
[0].bitfield
.sreg3
)
5117 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5118 && i
.op
[0].regs
->reg_num
== 1)
5120 as_bad (_("you can't `pop %scs'"), register_prefix
);
5123 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5124 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5129 /* The register or float register operand is in operand
5133 if (i
.types
[0].bitfield
.floatreg
5134 || operand_type_check (i
.types
[0], reg
))
5138 /* Register goes in low 3 bits of opcode. */
5139 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5140 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5142 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5144 /* Warn about some common errors, but press on regardless.
5145 The first case can be generated by gcc (<= 2.8.1). */
5146 if (i
.operands
== 2)
5148 /* Reversed arguments on faddp, fsubp, etc. */
5149 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5150 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5151 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5155 /* Extraneous `l' suffix on fp insn. */
5156 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5157 register_prefix
, i
.op
[0].regs
->reg_name
);
5162 else if (i
.tm
.opcode_modifier
.modrm
)
5164 /* The opcode is completed (modulo i.tm.extension_opcode which
5165 must be put into the modrm byte). Now, we make the modrm and
5166 index base bytes based on all the info we've collected. */
5168 default_seg
= build_modrm_byte ();
5170 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5174 else if (i
.tm
.opcode_modifier
.isstring
)
5176 /* For the string instructions that allow a segment override
5177 on one of their operands, the default segment is ds. */
5181 if (i
.tm
.base_opcode
== 0x8d /* lea */
5184 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5186 /* If a segment was explicitly specified, and the specified segment
5187 is not the default, use an opcode prefix to select it. If we
5188 never figured out what the default segment is, then default_seg
5189 will be zero at this point, and the specified segment prefix will
5191 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5193 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5199 static const seg_entry
*
5200 build_modrm_byte (void)
5202 const seg_entry
*default_seg
= 0;
5203 unsigned int source
, dest
;
5206 /* The first operand of instructions with VEX prefix and 3 sources
5207 must be VEX_Imm4. */
5208 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5211 unsigned int nds
, reg_slot
;
5214 if (i
.tm
.opcode_modifier
.veximmext
5215 && i
.tm
.opcode_modifier
.immext
)
5217 dest
= i
.operands
- 2;
5218 gas_assert (dest
== 3);
5221 dest
= i
.operands
- 1;
5224 /* There are 2 kinds of instructions:
5225 1. 5 operands: 4 register operands or 3 register operands
5226 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5227 VexW0 or VexW1. The destination must be either XMM or YMM
5229 2. 4 operands: 4 register operands or 3 register operands
5230 plus 1 memory operand, VexXDS, and VexImmExt */
5231 gas_assert ((i
.reg_operands
== 4
5232 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5233 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5234 && (i
.tm
.opcode_modifier
.veximmext
5235 || (i
.imm_operands
== 1
5236 && i
.types
[0].bitfield
.vec_imm4
5237 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5238 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5239 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5240 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5242 if (i
.imm_operands
== 0)
5244 /* When there is no immediate operand, generate an 8bit
5245 immediate operand to encode the first operand. */
5246 exp
= &im_expressions
[i
.imm_operands
++];
5247 i
.op
[i
.operands
].imms
= exp
;
5248 i
.types
[i
.operands
] = imm8
;
5250 /* If VexW1 is set, the first operand is the source and
5251 the second operand is encoded in the immediate operand. */
5252 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5263 /* FMA swaps REG and NDS. */
5264 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5272 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5274 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5276 exp
->X_op
= O_constant
;
5278 = ((i
.op
[reg_slot
].regs
->reg_num
5279 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5284 unsigned int imm_slot
;
5286 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5288 /* If VexW0 is set, the third operand is the source and
5289 the second operand is encoded in the immediate
5296 /* VexW1 is set, the second operand is the source and
5297 the third operand is encoded in the immediate
5303 if (i
.tm
.opcode_modifier
.immext
)
5305 /* When ImmExt is set, the immdiate byte is the last
5307 imm_slot
= i
.operands
- 1;
5315 /* Turn on Imm8 so that output_imm will generate it. */
5316 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5319 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5321 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5323 i
.op
[imm_slot
].imms
->X_add_number
5324 |= ((i
.op
[reg_slot
].regs
->reg_num
5325 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5329 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5330 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5332 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5337 /* i.reg_operands MUST be the number of real register operands;
5338 implicit registers do not count. If there are 3 register
5339 operands, it must be a instruction with VexNDS. For a
5340 instruction with VexNDD, the destination register is encoded
5341 in VEX prefix. If there are 4 register operands, it must be
5342 a instruction with VEX prefix and 3 sources. */
5343 if (i
.mem_operands
== 0
5344 && ((i
.reg_operands
== 2
5345 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5346 || (i
.reg_operands
== 3
5347 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5348 || (i
.reg_operands
== 4 && vex_3_sources
)))
5356 /* When there are 3 operands, one of them may be immediate,
5357 which may be the first or the last operand. Otherwise,
5358 the first operand must be shift count register (cl) or it
5359 is an instruction with VexNDS. */
5360 gas_assert (i
.imm_operands
== 1
5361 || (i
.imm_operands
== 0
5362 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5363 || i
.types
[0].bitfield
.shiftcount
)));
5364 if (operand_type_check (i
.types
[0], imm
)
5365 || i
.types
[0].bitfield
.shiftcount
)
5371 /* When there are 4 operands, the first two must be 8bit
5372 immediate operands. The source operand will be the 3rd
5375 For instructions with VexNDS, if the first operand
5376 an imm8, the source operand is the 2nd one. If the last
5377 operand is imm8, the source operand is the first one. */
5378 gas_assert ((i
.imm_operands
== 2
5379 && i
.types
[0].bitfield
.imm8
5380 && i
.types
[1].bitfield
.imm8
)
5381 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5382 && i
.imm_operands
== 1
5383 && (i
.types
[0].bitfield
.imm8
5384 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5385 if (i
.imm_operands
== 2)
5389 if (i
.types
[0].bitfield
.imm8
)
5405 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5407 /* For instructions with VexNDS, the register-only
5408 source operand must be 32/64bit integer, XMM or
5409 YMM register. It is encoded in VEX prefix. We
5410 need to clear RegMem bit before calling
5411 operand_type_equal. */
5413 i386_operand_type op
;
5416 /* Check register-only source operand when two source
5417 operands are swapped. */
5418 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5419 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5427 op
= i
.tm
.operand_types
[vvvv
];
5428 op
.bitfield
.regmem
= 0;
5429 if ((dest
+ 1) >= i
.operands
5430 || (op
.bitfield
.reg32
!= 1
5431 && !op
.bitfield
.reg64
!= 1
5432 && !operand_type_equal (&op
, ®xmm
)
5433 && !operand_type_equal (&op
, ®ymm
)))
5435 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5441 /* One of the register operands will be encoded in the i.tm.reg
5442 field, the other in the combined i.tm.mode and i.tm.regmem
5443 fields. If no form of this instruction supports a memory
5444 destination operand, then we assume the source operand may
5445 sometimes be a memory operand and so we need to store the
5446 destination in the i.rm.reg field. */
5447 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5448 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5450 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5451 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5452 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5454 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5459 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5460 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5461 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5463 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5466 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5468 if (!i
.types
[0].bitfield
.control
5469 && !i
.types
[1].bitfield
.control
)
5471 i
.rex
&= ~(REX_R
| REX_B
);
5472 add_prefix (LOCK_PREFIX_OPCODE
);
5476 { /* If it's not 2 reg operands... */
5481 unsigned int fake_zero_displacement
= 0;
5484 for (op
= 0; op
< i
.operands
; op
++)
5485 if (operand_type_check (i
.types
[op
], anymem
))
5487 gas_assert (op
< i
.operands
);
5489 if (i
.tm
.opcode_modifier
.vecsib
)
5491 if (i
.index_reg
->reg_num
== RegEiz
5492 || i
.index_reg
->reg_num
== RegRiz
)
5495 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5498 i
.sib
.base
= NO_BASE_REGISTER
;
5499 i
.sib
.scale
= i
.log2_scale_factor
;
5500 i
.types
[op
].bitfield
.disp8
= 0;
5501 i
.types
[op
].bitfield
.disp16
= 0;
5502 i
.types
[op
].bitfield
.disp64
= 0;
5503 if (flag_code
!= CODE_64BIT
)
5505 /* Must be 32 bit */
5506 i
.types
[op
].bitfield
.disp32
= 1;
5507 i
.types
[op
].bitfield
.disp32s
= 0;
5511 i
.types
[op
].bitfield
.disp32
= 0;
5512 i
.types
[op
].bitfield
.disp32s
= 1;
5515 i
.sib
.index
= i
.index_reg
->reg_num
;
5516 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5522 if (i
.base_reg
== 0)
5525 if (!i
.disp_operands
)
5527 fake_zero_displacement
= 1;
5528 /* Instructions with VSIB byte need 32bit displacement
5529 if there is no base register. */
5530 if (i
.tm
.opcode_modifier
.vecsib
)
5531 i
.types
[op
].bitfield
.disp32
= 1;
5533 if (i
.index_reg
== 0)
5535 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5536 /* Operand is just <disp> */
5537 if (flag_code
== CODE_64BIT
)
5539 /* 64bit mode overwrites the 32bit absolute
5540 addressing by RIP relative addressing and
5541 absolute addressing is encoded by one of the
5542 redundant SIB forms. */
5543 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5544 i
.sib
.base
= NO_BASE_REGISTER
;
5545 i
.sib
.index
= NO_INDEX_REGISTER
;
5546 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5547 ? disp32s
: disp32
);
5549 else if ((flag_code
== CODE_16BIT
)
5550 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5552 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5553 i
.types
[op
] = disp16
;
5557 i
.rm
.regmem
= NO_BASE_REGISTER
;
5558 i
.types
[op
] = disp32
;
5561 else if (!i
.tm
.opcode_modifier
.vecsib
)
5563 /* !i.base_reg && i.index_reg */
5564 if (i
.index_reg
->reg_num
== RegEiz
5565 || i
.index_reg
->reg_num
== RegRiz
)
5566 i
.sib
.index
= NO_INDEX_REGISTER
;
5568 i
.sib
.index
= i
.index_reg
->reg_num
;
5569 i
.sib
.base
= NO_BASE_REGISTER
;
5570 i
.sib
.scale
= i
.log2_scale_factor
;
5571 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5572 i
.types
[op
].bitfield
.disp8
= 0;
5573 i
.types
[op
].bitfield
.disp16
= 0;
5574 i
.types
[op
].bitfield
.disp64
= 0;
5575 if (flag_code
!= CODE_64BIT
)
5577 /* Must be 32 bit */
5578 i
.types
[op
].bitfield
.disp32
= 1;
5579 i
.types
[op
].bitfield
.disp32s
= 0;
5583 i
.types
[op
].bitfield
.disp32
= 0;
5584 i
.types
[op
].bitfield
.disp32s
= 1;
5586 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5590 /* RIP addressing for 64bit mode. */
5591 else if (i
.base_reg
->reg_num
== RegRip
||
5592 i
.base_reg
->reg_num
== RegEip
)
5594 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5595 i
.rm
.regmem
= NO_BASE_REGISTER
;
5596 i
.types
[op
].bitfield
.disp8
= 0;
5597 i
.types
[op
].bitfield
.disp16
= 0;
5598 i
.types
[op
].bitfield
.disp32
= 0;
5599 i
.types
[op
].bitfield
.disp32s
= 1;
5600 i
.types
[op
].bitfield
.disp64
= 0;
5601 i
.flags
[op
] |= Operand_PCrel
;
5602 if (! i
.disp_operands
)
5603 fake_zero_displacement
= 1;
5605 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5607 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5608 switch (i
.base_reg
->reg_num
)
5611 if (i
.index_reg
== 0)
5613 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5614 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5618 if (i
.index_reg
== 0)
5621 if (operand_type_check (i
.types
[op
], disp
) == 0)
5623 /* fake (%bp) into 0(%bp) */
5624 i
.types
[op
].bitfield
.disp8
= 1;
5625 fake_zero_displacement
= 1;
5628 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5629 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5631 default: /* (%si) -> 4 or (%di) -> 5 */
5632 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5634 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5636 else /* i.base_reg and 32/64 bit mode */
5638 if (flag_code
== CODE_64BIT
5639 && operand_type_check (i
.types
[op
], disp
))
5641 i386_operand_type temp
;
5642 operand_type_set (&temp
, 0);
5643 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5645 if (i
.prefix
[ADDR_PREFIX
] == 0)
5646 i
.types
[op
].bitfield
.disp32s
= 1;
5648 i
.types
[op
].bitfield
.disp32
= 1;
5651 if (!i
.tm
.opcode_modifier
.vecsib
)
5652 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5653 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5655 i
.sib
.base
= i
.base_reg
->reg_num
;
5656 /* x86-64 ignores REX prefix bit here to avoid decoder
5658 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5661 if (i
.disp_operands
== 0)
5663 fake_zero_displacement
= 1;
5664 i
.types
[op
].bitfield
.disp8
= 1;
5667 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5671 i
.sib
.scale
= i
.log2_scale_factor
;
5672 if (i
.index_reg
== 0)
5674 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5675 /* <disp>(%esp) becomes two byte modrm with no index
5676 register. We've already stored the code for esp
5677 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5678 Any base register besides %esp will not use the
5679 extra modrm byte. */
5680 i
.sib
.index
= NO_INDEX_REGISTER
;
5682 else if (!i
.tm
.opcode_modifier
.vecsib
)
5684 if (i
.index_reg
->reg_num
== RegEiz
5685 || i
.index_reg
->reg_num
== RegRiz
)
5686 i
.sib
.index
= NO_INDEX_REGISTER
;
5688 i
.sib
.index
= i
.index_reg
->reg_num
;
5689 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5690 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5695 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5696 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5699 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5702 if (fake_zero_displacement
)
5704 /* Fakes a zero displacement assuming that i.types[op]
5705 holds the correct displacement size. */
5708 gas_assert (i
.op
[op
].disps
== 0);
5709 exp
= &disp_expressions
[i
.disp_operands
++];
5710 i
.op
[op
].disps
= exp
;
5711 exp
->X_op
= O_constant
;
5712 exp
->X_add_number
= 0;
5713 exp
->X_add_symbol
= (symbolS
*) 0;
5714 exp
->X_op_symbol
= (symbolS
*) 0;
5722 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5724 if (operand_type_check (i
.types
[0], imm
))
5725 i
.vex
.register_specifier
= NULL
;
5728 /* VEX.vvvv encodes one of the sources when the first
5729 operand is not an immediate. */
5730 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5731 i
.vex
.register_specifier
= i
.op
[0].regs
;
5733 i
.vex
.register_specifier
= i
.op
[1].regs
;
5736 /* Destination is a XMM register encoded in the ModRM.reg
5738 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5739 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5742 /* ModRM.rm and VEX.B encodes the other source. */
5743 if (!i
.mem_operands
)
5747 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5748 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5750 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5752 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5756 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5758 i
.vex
.register_specifier
= i
.op
[2].regs
;
5759 if (!i
.mem_operands
)
5762 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5763 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5767 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5768 (if any) based on i.tm.extension_opcode. Again, we must be
5769 careful to make sure that segment/control/debug/test/MMX
5770 registers are coded into the i.rm.reg field. */
5771 else if (i
.reg_operands
)
5774 unsigned int vex_reg
= ~0;
5776 for (op
= 0; op
< i
.operands
; op
++)
5777 if (i
.types
[op
].bitfield
.reg8
5778 || i
.types
[op
].bitfield
.reg16
5779 || i
.types
[op
].bitfield
.reg32
5780 || i
.types
[op
].bitfield
.reg64
5781 || i
.types
[op
].bitfield
.regmmx
5782 || i
.types
[op
].bitfield
.regxmm
5783 || i
.types
[op
].bitfield
.regymm
5784 || i
.types
[op
].bitfield
.sreg2
5785 || i
.types
[op
].bitfield
.sreg3
5786 || i
.types
[op
].bitfield
.control
5787 || i
.types
[op
].bitfield
.debug
5788 || i
.types
[op
].bitfield
.test
)
5793 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5795 /* For instructions with VexNDS, the register-only
5796 source operand is encoded in VEX prefix. */
5797 gas_assert (mem
!= (unsigned int) ~0);
5802 gas_assert (op
< i
.operands
);
5806 /* Check register-only source operand when two source
5807 operands are swapped. */
5808 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5809 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5813 gas_assert (mem
== (vex_reg
+ 1)
5814 && op
< i
.operands
);
5819 gas_assert (vex_reg
< i
.operands
);
5823 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5825 /* For instructions with VexNDD, the register destination
5826 is encoded in VEX prefix. */
5827 if (i
.mem_operands
== 0)
5829 /* There is no memory operand. */
5830 gas_assert ((op
+ 2) == i
.operands
);
5835 /* There are only 2 operands. */
5836 gas_assert (op
< 2 && i
.operands
== 2);
5841 gas_assert (op
< i
.operands
);
5843 if (vex_reg
!= (unsigned int) ~0)
5845 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5847 if (type
->bitfield
.reg32
!= 1
5848 && type
->bitfield
.reg64
!= 1
5849 && !operand_type_equal (type
, ®xmm
)
5850 && !operand_type_equal (type
, ®ymm
))
5853 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5856 /* Don't set OP operand twice. */
5859 /* If there is an extension opcode to put here, the
5860 register number must be put into the regmem field. */
5861 if (i
.tm
.extension_opcode
!= None
)
5863 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5864 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5869 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5870 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5875 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5876 must set it to 3 to indicate this is a register operand
5877 in the regmem field. */
5878 if (!i
.mem_operands
)
5882 /* Fill in i.rm.reg field with extension opcode (if any). */
5883 if (i
.tm
.extension_opcode
!= None
)
5884 i
.rm
.reg
= i
.tm
.extension_opcode
;
5890 output_branch (void)
5896 relax_substateT subtype
;
5900 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
5901 size
= i
.disp32_encoding
? BIG
: SMALL
;
5904 if (i
.prefix
[DATA_PREFIX
] != 0)
5910 /* Pentium4 branch hints. */
5911 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5912 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5917 if (i
.prefix
[REX_PREFIX
] != 0)
5923 if (i
.prefixes
!= 0 && !intel_syntax
)
5924 as_warn (_("skipping prefixes on this instruction"));
5926 /* It's always a symbol; End frag & setup for relax.
5927 Make sure there is enough room in this frag for the largest
5928 instruction we may generate in md_convert_frag. This is 2
5929 bytes for the opcode and room for the prefix and largest
5931 frag_grow (prefix
+ 2 + 4);
5932 /* Prefix and 1 opcode byte go in fr_fix. */
5933 p
= frag_more (prefix
+ 1);
5934 if (i
.prefix
[DATA_PREFIX
] != 0)
5935 *p
++ = DATA_PREFIX_OPCODE
;
5936 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5937 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5938 *p
++ = i
.prefix
[SEG_PREFIX
];
5939 if (i
.prefix
[REX_PREFIX
] != 0)
5940 *p
++ = i
.prefix
[REX_PREFIX
];
5941 *p
= i
.tm
.base_opcode
;
5943 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5944 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
5945 else if (cpu_arch_flags
.bitfield
.cpui386
)
5946 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
5948 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
5951 sym
= i
.op
[0].disps
->X_add_symbol
;
5952 off
= i
.op
[0].disps
->X_add_number
;
5954 if (i
.op
[0].disps
->X_op
!= O_constant
5955 && i
.op
[0].disps
->X_op
!= O_symbol
)
5957 /* Handle complex expressions. */
5958 sym
= make_expr_symbol (i
.op
[0].disps
);
5962 /* 1 possible extra opcode + 4 byte displacement go in var part.
5963 Pass reloc in fr_var. */
5964 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5974 if (i
.tm
.opcode_modifier
.jumpbyte
)
5976 /* This is a loop or jecxz type instruction. */
5978 if (i
.prefix
[ADDR_PREFIX
] != 0)
5980 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5983 /* Pentium4 branch hints. */
5984 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5985 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5987 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5996 if (flag_code
== CODE_16BIT
)
5999 if (i
.prefix
[DATA_PREFIX
] != 0)
6001 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6011 if (i
.prefix
[REX_PREFIX
] != 0)
6013 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6017 if (i
.prefixes
!= 0 && !intel_syntax
)
6018 as_warn (_("skipping prefixes on this instruction"));
6020 p
= frag_more (1 + size
);
6021 *p
++ = i
.tm
.base_opcode
;
6023 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6024 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6026 /* All jumps handled here are signed, but don't use a signed limit
6027 check for 32 and 16 bit jumps as we want to allow wrap around at
6028 4G and 64k respectively. */
6030 fixP
->fx_signed
= 1;
6034 output_interseg_jump (void)
6042 if (flag_code
== CODE_16BIT
)
6046 if (i
.prefix
[DATA_PREFIX
] != 0)
6052 if (i
.prefix
[REX_PREFIX
] != 0)
6062 if (i
.prefixes
!= 0 && !intel_syntax
)
6063 as_warn (_("skipping prefixes on this instruction"));
6065 /* 1 opcode; 2 segment; offset */
6066 p
= frag_more (prefix
+ 1 + 2 + size
);
6068 if (i
.prefix
[DATA_PREFIX
] != 0)
6069 *p
++ = DATA_PREFIX_OPCODE
;
6071 if (i
.prefix
[REX_PREFIX
] != 0)
6072 *p
++ = i
.prefix
[REX_PREFIX
];
6074 *p
++ = i
.tm
.base_opcode
;
6075 if (i
.op
[1].imms
->X_op
== O_constant
)
6077 offsetT n
= i
.op
[1].imms
->X_add_number
;
6080 && !fits_in_unsigned_word (n
)
6081 && !fits_in_signed_word (n
))
6083 as_bad (_("16-bit jump out of range"));
6086 md_number_to_chars (p
, n
, size
);
6089 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6090 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6091 if (i
.op
[0].imms
->X_op
!= O_constant
)
6092 as_bad (_("can't handle non absolute segment in `%s'"),
6094 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6100 fragS
*insn_start_frag
;
6101 offsetT insn_start_off
;
6103 /* Tie dwarf2 debug info to the address at the start of the insn.
6104 We can't do this after the insn has been output as the current
6105 frag may have been closed off. eg. by frag_var. */
6106 dwarf2_emit_insn (0);
6108 insn_start_frag
= frag_now
;
6109 insn_start_off
= frag_now_fix ();
6112 if (i
.tm
.opcode_modifier
.jump
)
6114 else if (i
.tm
.opcode_modifier
.jumpbyte
6115 || i
.tm
.opcode_modifier
.jumpdword
)
6117 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6118 output_interseg_jump ();
6121 /* Output normal instructions here. */
6125 unsigned int prefix
;
6127 /* Since the VEX prefix contains the implicit prefix, we don't
6128 need the explicit prefix. */
6129 if (!i
.tm
.opcode_modifier
.vex
)
6131 switch (i
.tm
.opcode_length
)
6134 if (i
.tm
.base_opcode
& 0xff000000)
6136 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6141 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6143 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6144 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6147 if (prefix
!= REPE_PREFIX_OPCODE
6148 || (i
.prefix
[REP_PREFIX
]
6149 != REPE_PREFIX_OPCODE
))
6150 add_prefix (prefix
);
6153 add_prefix (prefix
);
6162 /* The prefix bytes. */
6163 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6165 FRAG_APPEND_1_CHAR (*q
);
6168 if (i
.tm
.opcode_modifier
.vex
)
6170 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6175 /* REX byte is encoded in VEX prefix. */
6179 FRAG_APPEND_1_CHAR (*q
);
6182 /* There should be no other prefixes for instructions
6187 /* Now the VEX prefix. */
6188 p
= frag_more (i
.vex
.length
);
6189 for (j
= 0; j
< i
.vex
.length
; j
++)
6190 p
[j
] = i
.vex
.bytes
[j
];
6193 /* Now the opcode; be careful about word order here! */
6194 if (i
.tm
.opcode_length
== 1)
6196 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6200 switch (i
.tm
.opcode_length
)
6204 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6214 /* Put out high byte first: can't use md_number_to_chars! */
6215 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6216 *p
= i
.tm
.base_opcode
& 0xff;
6219 /* Now the modrm byte and sib byte (if present). */
6220 if (i
.tm
.opcode_modifier
.modrm
)
6222 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6225 /* If i.rm.regmem == ESP (4)
6226 && i.rm.mode != (Register mode)
6228 ==> need second modrm byte. */
6229 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6231 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6232 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6234 | i
.sib
.scale
<< 6));
6237 if (i
.disp_operands
)
6238 output_disp (insn_start_frag
, insn_start_off
);
6241 output_imm (insn_start_frag
, insn_start_off
);
6247 pi ("" /*line*/, &i
);
6249 #endif /* DEBUG386 */
6252 /* Return the size of the displacement operand N. */
6255 disp_size (unsigned int n
)
6258 if (i
.types
[n
].bitfield
.disp64
)
6260 else if (i
.types
[n
].bitfield
.disp8
)
6262 else if (i
.types
[n
].bitfield
.disp16
)
6267 /* Return the size of the immediate operand N. */
6270 imm_size (unsigned int n
)
6273 if (i
.types
[n
].bitfield
.imm64
)
6275 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6277 else if (i
.types
[n
].bitfield
.imm16
)
6283 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6288 for (n
= 0; n
< i
.operands
; n
++)
6290 if (operand_type_check (i
.types
[n
], disp
))
6292 if (i
.op
[n
].disps
->X_op
== O_constant
)
6294 int size
= disp_size (n
);
6297 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6299 p
= frag_more (size
);
6300 md_number_to_chars (p
, val
, size
);
6304 enum bfd_reloc_code_real reloc_type
;
6305 int size
= disp_size (n
);
6306 int sign
= i
.types
[n
].bitfield
.disp32s
;
6307 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6309 /* We can't have 8 bit displacement here. */
6310 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6312 /* The PC relative address is computed relative
6313 to the instruction boundary, so in case immediate
6314 fields follows, we need to adjust the value. */
6315 if (pcrel
&& i
.imm_operands
)
6320 for (n1
= 0; n1
< i
.operands
; n1
++)
6321 if (operand_type_check (i
.types
[n1
], imm
))
6323 /* Only one immediate is allowed for PC
6324 relative address. */
6325 gas_assert (sz
== 0);
6327 i
.op
[n
].disps
->X_add_number
-= sz
;
6329 /* We should find the immediate. */
6330 gas_assert (sz
!= 0);
6333 p
= frag_more (size
);
6334 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6336 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6337 && (((reloc_type
== BFD_RELOC_32
6338 || reloc_type
== BFD_RELOC_X86_64_32S
6339 || (reloc_type
== BFD_RELOC_64
6341 && (i
.op
[n
].disps
->X_op
== O_symbol
6342 || (i
.op
[n
].disps
->X_op
== O_add
6343 && ((symbol_get_value_expression
6344 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6346 || reloc_type
== BFD_RELOC_32_PCREL
))
6350 if (insn_start_frag
== frag_now
)
6351 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6356 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6357 for (fr
= insn_start_frag
->fr_next
;
6358 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6360 add
+= p
- frag_now
->fr_literal
;
6365 reloc_type
= BFD_RELOC_386_GOTPC
;
6366 i
.op
[n
].imms
->X_add_number
+= add
;
6368 else if (reloc_type
== BFD_RELOC_64
)
6369 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6371 /* Don't do the adjustment for x86-64, as there
6372 the pcrel addressing is relative to the _next_
6373 insn, and that is taken care of in other code. */
6374 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6376 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6377 i
.op
[n
].disps
, pcrel
, reloc_type
);
6384 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6389 for (n
= 0; n
< i
.operands
; n
++)
6391 if (operand_type_check (i
.types
[n
], imm
))
6393 if (i
.op
[n
].imms
->X_op
== O_constant
)
6395 int size
= imm_size (n
);
6398 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6400 p
= frag_more (size
);
6401 md_number_to_chars (p
, val
, size
);
6405 /* Not absolute_section.
6406 Need a 32-bit fixup (don't support 8bit
6407 non-absolute imms). Try to support other
6409 enum bfd_reloc_code_real reloc_type
;
6410 int size
= imm_size (n
);
6413 if (i
.types
[n
].bitfield
.imm32s
6414 && (i
.suffix
== QWORD_MNEM_SUFFIX
6415 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6420 p
= frag_more (size
);
6421 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6423 /* This is tough to explain. We end up with this one if we
6424 * have operands that look like
6425 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6426 * obtain the absolute address of the GOT, and it is strongly
6427 * preferable from a performance point of view to avoid using
6428 * a runtime relocation for this. The actual sequence of
6429 * instructions often look something like:
6434 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6436 * The call and pop essentially return the absolute address
6437 * of the label .L66 and store it in %ebx. The linker itself
6438 * will ultimately change the first operand of the addl so
6439 * that %ebx points to the GOT, but to keep things simple, the
6440 * .o file must have this operand set so that it generates not
6441 * the absolute address of .L66, but the absolute address of
6442 * itself. This allows the linker itself simply treat a GOTPC
6443 * relocation as asking for a pcrel offset to the GOT to be
6444 * added in, and the addend of the relocation is stored in the
6445 * operand field for the instruction itself.
6447 * Our job here is to fix the operand so that it would add
6448 * the correct offset so that %ebx would point to itself. The
6449 * thing that is tricky is that .-.L66 will point to the
6450 * beginning of the instruction, so we need to further modify
6451 * the operand so that it will point to itself. There are
6452 * other cases where you have something like:
6454 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6456 * and here no correction would be required. Internally in
6457 * the assembler we treat operands of this form as not being
6458 * pcrel since the '.' is explicitly mentioned, and I wonder
6459 * whether it would simplify matters to do it this way. Who
6460 * knows. In earlier versions of the PIC patches, the
6461 * pcrel_adjust field was used to store the correction, but
6462 * since the expression is not pcrel, I felt it would be
6463 * confusing to do it this way. */
6465 if ((reloc_type
== BFD_RELOC_32
6466 || reloc_type
== BFD_RELOC_X86_64_32S
6467 || reloc_type
== BFD_RELOC_64
)
6469 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6470 && (i
.op
[n
].imms
->X_op
== O_symbol
6471 || (i
.op
[n
].imms
->X_op
== O_add
6472 && ((symbol_get_value_expression
6473 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6478 if (insn_start_frag
== frag_now
)
6479 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6484 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6485 for (fr
= insn_start_frag
->fr_next
;
6486 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6488 add
+= p
- frag_now
->fr_literal
;
6492 reloc_type
= BFD_RELOC_386_GOTPC
;
6494 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6496 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6497 i
.op
[n
].imms
->X_add_number
+= add
;
6499 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6500 i
.op
[n
].imms
, 0, reloc_type
);
6506 /* x86_cons_fix_new is called via the expression parsing code when a
6507 reloc is needed. We use this hook to get the correct .got reloc. */
6508 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6509 static int cons_sign
= -1;
6512 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6515 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6517 got_reloc
= NO_RELOC
;
6520 if (exp
->X_op
== O_secrel
)
6522 exp
->X_op
= O_symbol
;
6523 r
= BFD_RELOC_32_SECREL
;
6527 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6530 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6532 # define lex_got(reloc, adjust, types) NULL
6534 /* Parse operands of the form
6535 <symbol>@GOTOFF+<nnn>
6536 and similar .plt or .got references.
6538 If we find one, set up the correct relocation in RELOC and copy the
6539 input string, minus the `@GOTOFF' into a malloc'd buffer for
6540 parsing by the calling routine. Return this buffer, and if ADJUST
6541 is non-null set it to the length of the string we removed from the
6542 input line. Otherwise return NULL. */
6544 lex_got (enum bfd_reloc_code_real
*rel
,
6546 i386_operand_type
*types
)
6548 /* Some of the relocations depend on the size of what field is to
6549 be relocated. But in our callers i386_immediate and i386_displacement
6550 we don't yet know the operand size (this will be set by insn
6551 matching). Hence we record the word32 relocation here,
6552 and adjust the reloc according to the real size in reloc(). */
6553 static const struct {
6556 const enum bfd_reloc_code_real rel
[2];
6557 const i386_operand_type types64
;
6559 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6560 BFD_RELOC_X86_64_PLTOFF64
},
6561 OPERAND_TYPE_IMM64
},
6562 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6563 BFD_RELOC_X86_64_PLT32
},
6564 OPERAND_TYPE_IMM32_32S_DISP32
},
6565 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6566 BFD_RELOC_X86_64_GOTPLT64
},
6567 OPERAND_TYPE_IMM64_DISP64
},
6568 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6569 BFD_RELOC_X86_64_GOTOFF64
},
6570 OPERAND_TYPE_IMM64_DISP64
},
6571 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6572 BFD_RELOC_X86_64_GOTPCREL
},
6573 OPERAND_TYPE_IMM32_32S_DISP32
},
6574 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6575 BFD_RELOC_X86_64_TLSGD
},
6576 OPERAND_TYPE_IMM32_32S_DISP32
},
6577 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6578 _dummy_first_bfd_reloc_code_real
},
6579 OPERAND_TYPE_NONE
},
6580 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6581 BFD_RELOC_X86_64_TLSLD
},
6582 OPERAND_TYPE_IMM32_32S_DISP32
},
6583 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6584 BFD_RELOC_X86_64_GOTTPOFF
},
6585 OPERAND_TYPE_IMM32_32S_DISP32
},
6586 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6587 BFD_RELOC_X86_64_TPOFF32
},
6588 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6589 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6590 _dummy_first_bfd_reloc_code_real
},
6591 OPERAND_TYPE_NONE
},
6592 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6593 BFD_RELOC_X86_64_DTPOFF32
},
6594 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6595 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6596 _dummy_first_bfd_reloc_code_real
},
6597 OPERAND_TYPE_NONE
},
6598 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6599 _dummy_first_bfd_reloc_code_real
},
6600 OPERAND_TYPE_NONE
},
6601 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6602 BFD_RELOC_X86_64_GOT32
},
6603 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6604 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6605 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6606 OPERAND_TYPE_IMM32_32S_DISP32
},
6607 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6608 BFD_RELOC_X86_64_TLSDESC_CALL
},
6609 OPERAND_TYPE_IMM32_32S_DISP32
},
6614 #if defined (OBJ_MAYBE_ELF)
6619 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6620 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6623 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6625 int len
= gotrel
[j
].len
;
6626 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6628 if (gotrel
[j
].rel
[object_64bit
] != 0)
6631 char *tmpbuf
, *past_reloc
;
6633 *rel
= gotrel
[j
].rel
[object_64bit
];
6639 if (flag_code
!= CODE_64BIT
)
6641 types
->bitfield
.imm32
= 1;
6642 types
->bitfield
.disp32
= 1;
6645 *types
= gotrel
[j
].types64
;
6648 if (GOT_symbol
== NULL
)
6649 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6651 /* The length of the first part of our input line. */
6652 first
= cp
- input_line_pointer
;
6654 /* The second part goes from after the reloc token until
6655 (and including) an end_of_line char or comma. */
6656 past_reloc
= cp
+ 1 + len
;
6658 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6660 second
= cp
+ 1 - past_reloc
;
6662 /* Allocate and copy string. The trailing NUL shouldn't
6663 be necessary, but be safe. */
6664 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6665 memcpy (tmpbuf
, input_line_pointer
, first
);
6666 if (second
!= 0 && *past_reloc
!= ' ')
6667 /* Replace the relocation token with ' ', so that
6668 errors like foo@GOTOFF1 will be detected. */
6669 tmpbuf
[first
++] = ' ';
6670 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6671 tmpbuf
[first
+ second
] = '\0';
6675 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6676 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6681 /* Might be a symbol version string. Don't as_bad here. */
6687 x86_cons (expressionS
*exp
, int size
)
6689 intel_syntax
= -intel_syntax
;
6692 if (size
== 4 || (object_64bit
&& size
== 8))
6694 /* Handle @GOTOFF and the like in an expression. */
6696 char *gotfree_input_line
;
6699 save
= input_line_pointer
;
6700 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6701 if (gotfree_input_line
)
6702 input_line_pointer
= gotfree_input_line
;
6706 if (gotfree_input_line
)
6708 /* expression () has merrily parsed up to the end of line,
6709 or a comma - in the wrong buffer. Transfer how far
6710 input_line_pointer has moved to the right buffer. */
6711 input_line_pointer
= (save
6712 + (input_line_pointer
- gotfree_input_line
)
6714 free (gotfree_input_line
);
6715 if (exp
->X_op
== O_constant
6716 || exp
->X_op
== O_absent
6717 || exp
->X_op
== O_illegal
6718 || exp
->X_op
== O_register
6719 || exp
->X_op
== O_big
)
6721 char c
= *input_line_pointer
;
6722 *input_line_pointer
= 0;
6723 as_bad (_("missing or invalid expression `%s'"), save
);
6724 *input_line_pointer
= c
;
6731 intel_syntax
= -intel_syntax
;
6734 i386_intel_simplify (exp
);
6738 signed_cons (int size
)
6740 if (flag_code
== CODE_64BIT
)
6748 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
6755 if (exp
.X_op
== O_symbol
)
6756 exp
.X_op
= O_secrel
;
6758 emit_expr (&exp
, 4);
6760 while (*input_line_pointer
++ == ',');
6762 input_line_pointer
--;
6763 demand_empty_rest_of_line ();
6768 i386_immediate (char *imm_start
)
6770 char *save_input_line_pointer
;
6771 char *gotfree_input_line
;
6774 i386_operand_type types
;
6776 operand_type_set (&types
, ~0);
6778 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6780 as_bad (_("at most %d immediate operands are allowed"),
6781 MAX_IMMEDIATE_OPERANDS
);
6785 exp
= &im_expressions
[i
.imm_operands
++];
6786 i
.op
[this_operand
].imms
= exp
;
6788 if (is_space_char (*imm_start
))
6791 save_input_line_pointer
= input_line_pointer
;
6792 input_line_pointer
= imm_start
;
6794 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6795 if (gotfree_input_line
)
6796 input_line_pointer
= gotfree_input_line
;
6798 exp_seg
= expression (exp
);
6801 if (*input_line_pointer
)
6802 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6804 input_line_pointer
= save_input_line_pointer
;
6805 if (gotfree_input_line
)
6807 free (gotfree_input_line
);
6809 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6810 exp
->X_op
= O_illegal
;
6813 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6817 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6818 i386_operand_type types
, const char *imm_start
)
6820 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6823 as_bad (_("missing or invalid immediate expression `%s'"),
6827 else if (exp
->X_op
== O_constant
)
6829 /* Size it properly later. */
6830 i
.types
[this_operand
].bitfield
.imm64
= 1;
6831 /* If not 64bit, sign extend val. */
6832 if (flag_code
!= CODE_64BIT
6833 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6835 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6837 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6838 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6839 && exp_seg
!= absolute_section
6840 && exp_seg
!= text_section
6841 && exp_seg
!= data_section
6842 && exp_seg
!= bss_section
6843 && exp_seg
!= undefined_section
6844 && !bfd_is_com_section (exp_seg
))
6846 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6850 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6853 as_bad (_("illegal immediate register operand %s"), imm_start
);
6858 /* This is an address. The size of the address will be
6859 determined later, depending on destination register,
6860 suffix, or the default for the section. */
6861 i
.types
[this_operand
].bitfield
.imm8
= 1;
6862 i
.types
[this_operand
].bitfield
.imm16
= 1;
6863 i
.types
[this_operand
].bitfield
.imm32
= 1;
6864 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6865 i
.types
[this_operand
].bitfield
.imm64
= 1;
6866 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6874 i386_scale (char *scale
)
6877 char *save
= input_line_pointer
;
6879 input_line_pointer
= scale
;
6880 val
= get_absolute_expression ();
6885 i
.log2_scale_factor
= 0;
6888 i
.log2_scale_factor
= 1;
6891 i
.log2_scale_factor
= 2;
6894 i
.log2_scale_factor
= 3;
6898 char sep
= *input_line_pointer
;
6900 *input_line_pointer
= '\0';
6901 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6903 *input_line_pointer
= sep
;
6904 input_line_pointer
= save
;
6908 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6910 as_warn (_("scale factor of %d without an index register"),
6911 1 << i
.log2_scale_factor
);
6912 i
.log2_scale_factor
= 0;
6914 scale
= input_line_pointer
;
6915 input_line_pointer
= save
;
6920 i386_displacement (char *disp_start
, char *disp_end
)
6924 char *save_input_line_pointer
;
6925 char *gotfree_input_line
;
6927 i386_operand_type bigdisp
, types
= anydisp
;
6930 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6932 as_bad (_("at most %d displacement operands are allowed"),
6933 MAX_MEMORY_OPERANDS
);
6937 operand_type_set (&bigdisp
, 0);
6938 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6939 || (!current_templates
->start
->opcode_modifier
.jump
6940 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6942 bigdisp
.bitfield
.disp32
= 1;
6943 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6944 if (flag_code
== CODE_64BIT
)
6948 bigdisp
.bitfield
.disp32s
= 1;
6949 bigdisp
.bitfield
.disp64
= 1;
6952 else if ((flag_code
== CODE_16BIT
) ^ override
)
6954 bigdisp
.bitfield
.disp32
= 0;
6955 bigdisp
.bitfield
.disp16
= 1;
6960 /* For PC-relative branches, the width of the displacement
6961 is dependent upon data size, not address size. */
6962 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6963 if (flag_code
== CODE_64BIT
)
6965 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6966 bigdisp
.bitfield
.disp16
= 1;
6969 bigdisp
.bitfield
.disp32
= 1;
6970 bigdisp
.bitfield
.disp32s
= 1;
6976 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6978 : LONG_MNEM_SUFFIX
));
6979 bigdisp
.bitfield
.disp32
= 1;
6980 if ((flag_code
== CODE_16BIT
) ^ override
)
6982 bigdisp
.bitfield
.disp32
= 0;
6983 bigdisp
.bitfield
.disp16
= 1;
6987 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6990 exp
= &disp_expressions
[i
.disp_operands
];
6991 i
.op
[this_operand
].disps
= exp
;
6993 save_input_line_pointer
= input_line_pointer
;
6994 input_line_pointer
= disp_start
;
6995 END_STRING_AND_SAVE (disp_end
);
6997 #ifndef GCC_ASM_O_HACK
6998 #define GCC_ASM_O_HACK 0
7001 END_STRING_AND_SAVE (disp_end
+ 1);
7002 if (i
.types
[this_operand
].bitfield
.baseIndex
7003 && displacement_string_end
[-1] == '+')
7005 /* This hack is to avoid a warning when using the "o"
7006 constraint within gcc asm statements.
7009 #define _set_tssldt_desc(n,addr,limit,type) \
7010 __asm__ __volatile__ ( \
7012 "movw %w1,2+%0\n\t" \
7014 "movb %b1,4+%0\n\t" \
7015 "movb %4,5+%0\n\t" \
7016 "movb $0,6+%0\n\t" \
7017 "movb %h1,7+%0\n\t" \
7019 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7021 This works great except that the output assembler ends
7022 up looking a bit weird if it turns out that there is
7023 no offset. You end up producing code that looks like:
7036 So here we provide the missing zero. */
7038 *displacement_string_end
= '0';
7041 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7042 if (gotfree_input_line
)
7043 input_line_pointer
= gotfree_input_line
;
7045 exp_seg
= expression (exp
);
7048 if (*input_line_pointer
)
7049 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7051 RESTORE_END_STRING (disp_end
+ 1);
7053 input_line_pointer
= save_input_line_pointer
;
7054 if (gotfree_input_line
)
7056 free (gotfree_input_line
);
7058 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7059 exp
->X_op
= O_illegal
;
7062 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
7064 RESTORE_END_STRING (disp_end
);
7070 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7071 i386_operand_type types
, const char *disp_start
)
7073 i386_operand_type bigdisp
;
7076 /* We do this to make sure that the section symbol is in
7077 the symbol table. We will ultimately change the relocation
7078 to be relative to the beginning of the section. */
7079 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
7080 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
7081 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7083 if (exp
->X_op
!= O_symbol
)
7086 if (S_IS_LOCAL (exp
->X_add_symbol
)
7087 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
7088 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
7089 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
7090 exp
->X_op
= O_subtract
;
7091 exp
->X_op_symbol
= GOT_symbol
;
7092 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
7093 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
7094 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7095 i
.reloc
[this_operand
] = BFD_RELOC_64
;
7097 i
.reloc
[this_operand
] = BFD_RELOC_32
;
7100 else if (exp
->X_op
== O_absent
7101 || exp
->X_op
== O_illegal
7102 || exp
->X_op
== O_big
)
7105 as_bad (_("missing or invalid displacement expression `%s'"),
7110 else if (flag_code
== CODE_64BIT
7111 && !i
.prefix
[ADDR_PREFIX
]
7112 && exp
->X_op
== O_constant
)
7114 /* Since displacement is signed extended to 64bit, don't allow
7115 disp32 and turn off disp32s if they are out of range. */
7116 i
.types
[this_operand
].bitfield
.disp32
= 0;
7117 if (!fits_in_signed_long (exp
->X_add_number
))
7119 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7120 if (i
.types
[this_operand
].bitfield
.baseindex
)
7122 as_bad (_("0x%lx out range of signed 32bit displacement"),
7123 (long) exp
->X_add_number
);
7129 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7130 else if (exp
->X_op
!= O_constant
7131 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7132 && exp_seg
!= absolute_section
7133 && exp_seg
!= text_section
7134 && exp_seg
!= data_section
7135 && exp_seg
!= bss_section
7136 && exp_seg
!= undefined_section
7137 && !bfd_is_com_section (exp_seg
))
7139 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7144 /* Check if this is a displacement only operand. */
7145 bigdisp
= i
.types
[this_operand
];
7146 bigdisp
.bitfield
.disp8
= 0;
7147 bigdisp
.bitfield
.disp16
= 0;
7148 bigdisp
.bitfield
.disp32
= 0;
7149 bigdisp
.bitfield
.disp32s
= 0;
7150 bigdisp
.bitfield
.disp64
= 0;
7151 if (operand_type_all_zero (&bigdisp
))
7152 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7158 /* Make sure the memory operand we've been dealt is valid.
7159 Return 1 on success, 0 on a failure. */
7162 i386_index_check (const char *operand_string
)
7165 const char *kind
= "base/index";
7166 #if INFER_ADDR_PREFIX
7172 if (current_templates
->start
->opcode_modifier
.isstring
7173 && !current_templates
->start
->opcode_modifier
.immext
7174 && (current_templates
->end
[-1].opcode_modifier
.isstring
7177 /* Memory operands of string insns are special in that they only allow
7178 a single register (rDI, rSI, or rBX) as their memory address. */
7179 unsigned int expected
;
7181 kind
= "string address";
7183 if (current_templates
->start
->opcode_modifier
.w
)
7185 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7187 if (!type
.bitfield
.baseindex
7188 || ((!i
.mem_operands
!= !intel_syntax
)
7189 && current_templates
->end
[-1].operand_types
[1]
7190 .bitfield
.baseindex
))
7191 type
= current_templates
->end
[-1].operand_types
[1];
7192 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7195 expected
= 3 /* rBX */;
7197 if (!i
.base_reg
|| i
.index_reg
7198 || operand_type_check (i
.types
[this_operand
], disp
))
7200 else if (!(flag_code
== CODE_64BIT
7201 ? i
.prefix
[ADDR_PREFIX
]
7202 ? i
.base_reg
->reg_type
.bitfield
.reg32
7203 : i
.base_reg
->reg_type
.bitfield
.reg64
7204 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7205 ? i
.base_reg
->reg_type
.bitfield
.reg32
7206 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7208 else if (i
.base_reg
->reg_num
!= expected
)
7215 for (j
= 0; j
< i386_regtab_size
; ++j
)
7216 if ((flag_code
== CODE_64BIT
7217 ? i
.prefix
[ADDR_PREFIX
]
7218 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7219 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7220 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7221 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7222 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7223 && i386_regtab
[j
].reg_num
== expected
)
7225 gas_assert (j
< i386_regtab_size
);
7226 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7228 intel_syntax
? '[' : '(',
7230 i386_regtab
[j
].reg_name
,
7231 intel_syntax
? ']' : ')');
7235 else if (flag_code
== CODE_64BIT
)
7238 && ((i
.prefix
[ADDR_PREFIX
] == 0
7239 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7240 || (i
.prefix
[ADDR_PREFIX
]
7241 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7243 || i
.base_reg
->reg_num
!=
7244 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7246 && !(i
.index_reg
->reg_type
.bitfield
.regxmm
7247 || i
.index_reg
->reg_type
.bitfield
.regymm
)
7248 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7249 || (i
.prefix
[ADDR_PREFIX
] == 0
7250 && i
.index_reg
->reg_num
!= RegRiz
7251 && !i
.index_reg
->reg_type
.bitfield
.reg64
7253 || (i
.prefix
[ADDR_PREFIX
]
7254 && i
.index_reg
->reg_num
!= RegEiz
7255 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7260 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7264 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7265 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7267 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7268 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7270 && i
.base_reg
->reg_num
< 6
7271 && i
.index_reg
->reg_num
>= 6
7272 && i
.log2_scale_factor
== 0))))
7279 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7281 && !i
.index_reg
->reg_type
.bitfield
.regxmm
7282 && !i
.index_reg
->reg_type
.bitfield
.regymm
7283 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7284 && i
.index_reg
->reg_num
!= RegEiz
)
7285 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7291 #if INFER_ADDR_PREFIX
7292 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7294 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7296 /* Change the size of any displacement too. At most one of
7297 Disp16 or Disp32 is set.
7298 FIXME. There doesn't seem to be any real need for separate
7299 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7300 Removing them would probably clean up the code quite a lot. */
7301 if (flag_code
!= CODE_64BIT
7302 && (i
.types
[this_operand
].bitfield
.disp16
7303 || i
.types
[this_operand
].bitfield
.disp32
))
7304 i
.types
[this_operand
]
7305 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7310 as_bad (_("`%s' is not a valid %s expression"),
7315 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7317 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7318 ? flag_code
== CODE_32BIT
7327 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7331 i386_att_operand (char *operand_string
)
7335 char *op_string
= operand_string
;
7337 if (is_space_char (*op_string
))
7340 /* We check for an absolute prefix (differentiating,
7341 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7342 if (*op_string
== ABSOLUTE_PREFIX
)
7345 if (is_space_char (*op_string
))
7347 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7350 /* Check if operand is a register. */
7351 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7353 i386_operand_type temp
;
7355 /* Check for a segment override by searching for ':' after a
7356 segment register. */
7358 if (is_space_char (*op_string
))
7360 if (*op_string
== ':'
7361 && (r
->reg_type
.bitfield
.sreg2
7362 || r
->reg_type
.bitfield
.sreg3
))
7367 i
.seg
[i
.mem_operands
] = &es
;
7370 i
.seg
[i
.mem_operands
] = &cs
;
7373 i
.seg
[i
.mem_operands
] = &ss
;
7376 i
.seg
[i
.mem_operands
] = &ds
;
7379 i
.seg
[i
.mem_operands
] = &fs
;
7382 i
.seg
[i
.mem_operands
] = &gs
;
7386 /* Skip the ':' and whitespace. */
7388 if (is_space_char (*op_string
))
7391 if (!is_digit_char (*op_string
)
7392 && !is_identifier_char (*op_string
)
7393 && *op_string
!= '('
7394 && *op_string
!= ABSOLUTE_PREFIX
)
7396 as_bad (_("bad memory operand `%s'"), op_string
);
7399 /* Handle case of %es:*foo. */
7400 if (*op_string
== ABSOLUTE_PREFIX
)
7403 if (is_space_char (*op_string
))
7405 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7407 goto do_memory_reference
;
7411 as_bad (_("junk `%s' after register"), op_string
);
7415 temp
.bitfield
.baseindex
= 0;
7416 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7418 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7419 i
.op
[this_operand
].regs
= r
;
7422 else if (*op_string
== REGISTER_PREFIX
)
7424 as_bad (_("bad register name `%s'"), op_string
);
7427 else if (*op_string
== IMMEDIATE_PREFIX
)
7430 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7432 as_bad (_("immediate operand illegal with absolute jump"));
7435 if (!i386_immediate (op_string
))
7438 else if (is_digit_char (*op_string
)
7439 || is_identifier_char (*op_string
)
7440 || *op_string
== '(')
7442 /* This is a memory reference of some sort. */
7445 /* Start and end of displacement string expression (if found). */
7446 char *displacement_string_start
;
7447 char *displacement_string_end
;
7449 do_memory_reference
:
7450 if ((i
.mem_operands
== 1
7451 && !current_templates
->start
->opcode_modifier
.isstring
)
7452 || i
.mem_operands
== 2)
7454 as_bad (_("too many memory references for `%s'"),
7455 current_templates
->start
->name
);
7459 /* Check for base index form. We detect the base index form by
7460 looking for an ')' at the end of the operand, searching
7461 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7463 base_string
= op_string
+ strlen (op_string
);
7466 if (is_space_char (*base_string
))
7469 /* If we only have a displacement, set-up for it to be parsed later. */
7470 displacement_string_start
= op_string
;
7471 displacement_string_end
= base_string
+ 1;
7473 if (*base_string
== ')')
7476 unsigned int parens_balanced
= 1;
7477 /* We've already checked that the number of left & right ()'s are
7478 equal, so this loop will not be infinite. */
7482 if (*base_string
== ')')
7484 if (*base_string
== '(')
7487 while (parens_balanced
);
7489 temp_string
= base_string
;
7491 /* Skip past '(' and whitespace. */
7493 if (is_space_char (*base_string
))
7496 if (*base_string
== ','
7497 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7500 displacement_string_end
= temp_string
;
7502 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7506 base_string
= end_op
;
7507 if (is_space_char (*base_string
))
7511 /* There may be an index reg or scale factor here. */
7512 if (*base_string
== ',')
7515 if (is_space_char (*base_string
))
7518 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7521 base_string
= end_op
;
7522 if (is_space_char (*base_string
))
7524 if (*base_string
== ',')
7527 if (is_space_char (*base_string
))
7530 else if (*base_string
!= ')')
7532 as_bad (_("expecting `,' or `)' "
7533 "after index register in `%s'"),
7538 else if (*base_string
== REGISTER_PREFIX
)
7540 as_bad (_("bad register name `%s'"), base_string
);
7544 /* Check for scale factor. */
7545 if (*base_string
!= ')')
7547 char *end_scale
= i386_scale (base_string
);
7552 base_string
= end_scale
;
7553 if (is_space_char (*base_string
))
7555 if (*base_string
!= ')')
7557 as_bad (_("expecting `)' "
7558 "after scale factor in `%s'"),
7563 else if (!i
.index_reg
)
7565 as_bad (_("expecting index register or scale factor "
7566 "after `,'; got '%c'"),
7571 else if (*base_string
!= ')')
7573 as_bad (_("expecting `,' or `)' "
7574 "after base register in `%s'"),
7579 else if (*base_string
== REGISTER_PREFIX
)
7581 as_bad (_("bad register name `%s'"), base_string
);
7586 /* If there's an expression beginning the operand, parse it,
7587 assuming displacement_string_start and
7588 displacement_string_end are meaningful. */
7589 if (displacement_string_start
!= displacement_string_end
)
7591 if (!i386_displacement (displacement_string_start
,
7592 displacement_string_end
))
7596 /* Special case for (%dx) while doing input/output op. */
7598 && operand_type_equal (&i
.base_reg
->reg_type
,
7599 ®16_inoutportreg
)
7601 && i
.log2_scale_factor
== 0
7602 && i
.seg
[i
.mem_operands
] == 0
7603 && !operand_type_check (i
.types
[this_operand
], disp
))
7605 i
.types
[this_operand
] = inoutportreg
;
7609 if (i386_index_check (operand_string
) == 0)
7611 i
.types
[this_operand
].bitfield
.mem
= 1;
7616 /* It's not a memory operand; argh! */
7617 as_bad (_("invalid char %s beginning operand %d `%s'"),
7618 output_invalid (*op_string
),
7623 return 1; /* Normal return. */
7626 /* md_estimate_size_before_relax()
7628 Called just before relax() for rs_machine_dependent frags. The x86
7629 assembler uses these frags to handle variable size jump
7632 Any symbol that is now undefined will not become defined.
7633 Return the correct fr_subtype in the frag.
7634 Return the initial "guess for variable size of frag" to caller.
7635 The guess is actually the growth beyond the fixed part. Whatever
7636 we do to grow the fixed or variable part contributes to our
7640 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
7642 /* We've already got fragP->fr_subtype right; all we have to do is
7643 check for un-relaxable symbols. On an ELF system, we can't relax
7644 an externally visible symbol, because it may be overridden by a
7646 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7647 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7649 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7650 || S_IS_WEAK (fragP
->fr_symbol
)
7651 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7652 & BSF_GNU_INDIRECT_FUNCTION
))))
7654 #if defined (OBJ_COFF) && defined (TE_PE)
7655 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7656 && S_IS_WEAK (fragP
->fr_symbol
))
7660 /* Symbol is undefined in this segment, or we need to keep a
7661 reloc so that weak symbols can be overridden. */
7662 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7663 enum bfd_reloc_code_real reloc_type
;
7664 unsigned char *opcode
;
7667 if (fragP
->fr_var
!= NO_RELOC
)
7668 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7670 reloc_type
= BFD_RELOC_16_PCREL
;
7672 reloc_type
= BFD_RELOC_32_PCREL
;
7674 old_fr_fix
= fragP
->fr_fix
;
7675 opcode
= (unsigned char *) fragP
->fr_opcode
;
7677 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7680 /* Make jmp (0xeb) a (d)word displacement jump. */
7682 fragP
->fr_fix
+= size
;
7683 fix_new (fragP
, old_fr_fix
, size
,
7685 fragP
->fr_offset
, 1,
7691 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7693 /* Negate the condition, and branch past an
7694 unconditional jump. */
7697 /* Insert an unconditional jump. */
7699 /* We added two extra opcode bytes, and have a two byte
7701 fragP
->fr_fix
+= 2 + 2;
7702 fix_new (fragP
, old_fr_fix
+ 2, 2,
7704 fragP
->fr_offset
, 1,
7711 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7716 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7718 fragP
->fr_offset
, 1,
7720 fixP
->fx_signed
= 1;
7724 /* This changes the byte-displacement jump 0x7N
7725 to the (d)word-displacement jump 0x0f,0x8N. */
7726 opcode
[1] = opcode
[0] + 0x10;
7727 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7728 /* We've added an opcode byte. */
7729 fragP
->fr_fix
+= 1 + size
;
7730 fix_new (fragP
, old_fr_fix
+ 1, size
,
7732 fragP
->fr_offset
, 1,
7737 BAD_CASE (fragP
->fr_subtype
);
7741 return fragP
->fr_fix
- old_fr_fix
;
7744 /* Guess size depending on current relax state. Initially the relax
7745 state will correspond to a short jump and we return 1, because
7746 the variable part of the frag (the branch offset) is one byte
7747 long. However, we can relax a section more than once and in that
7748 case we must either set fr_subtype back to the unrelaxed state,
7749 or return the value for the appropriate branch. */
7750 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7753 /* Called after relax() is finished.
7755 In: Address of frag.
7756 fr_type == rs_machine_dependent.
7757 fr_subtype is what the address relaxed to.
7759 Out: Any fixSs and constants are set up.
7760 Caller will turn frag into a ".space 0". */
7763 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
7766 unsigned char *opcode
;
7767 unsigned char *where_to_put_displacement
= NULL
;
7768 offsetT target_address
;
7769 offsetT opcode_address
;
7770 unsigned int extension
= 0;
7771 offsetT displacement_from_opcode_start
;
7773 opcode
= (unsigned char *) fragP
->fr_opcode
;
7775 /* Address we want to reach in file space. */
7776 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7778 /* Address opcode resides at in file space. */
7779 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7781 /* Displacement from opcode start to fill into instruction. */
7782 displacement_from_opcode_start
= target_address
- opcode_address
;
7784 if ((fragP
->fr_subtype
& BIG
) == 0)
7786 /* Don't have to change opcode. */
7787 extension
= 1; /* 1 opcode + 1 displacement */
7788 where_to_put_displacement
= &opcode
[1];
7792 if (no_cond_jump_promotion
7793 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7794 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7795 _("long jump required"));
7797 switch (fragP
->fr_subtype
)
7799 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7800 extension
= 4; /* 1 opcode + 4 displacement */
7802 where_to_put_displacement
= &opcode
[1];
7805 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7806 extension
= 2; /* 1 opcode + 2 displacement */
7808 where_to_put_displacement
= &opcode
[1];
7811 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7812 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7813 extension
= 5; /* 2 opcode + 4 displacement */
7814 opcode
[1] = opcode
[0] + 0x10;
7815 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7816 where_to_put_displacement
= &opcode
[2];
7819 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7820 extension
= 3; /* 2 opcode + 2 displacement */
7821 opcode
[1] = opcode
[0] + 0x10;
7822 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7823 where_to_put_displacement
= &opcode
[2];
7826 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7831 where_to_put_displacement
= &opcode
[3];
7835 BAD_CASE (fragP
->fr_subtype
);
7840 /* If size if less then four we are sure that the operand fits,
7841 but if it's 4, then it could be that the displacement is larger
7843 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7845 && ((addressT
) (displacement_from_opcode_start
- extension
7846 + ((addressT
) 1 << 31))
7847 > (((addressT
) 2 << 31) - 1)))
7849 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7850 _("jump target out of range"));
7851 /* Make us emit 0. */
7852 displacement_from_opcode_start
= extension
;
7854 /* Now put displacement after opcode. */
7855 md_number_to_chars ((char *) where_to_put_displacement
,
7856 (valueT
) (displacement_from_opcode_start
- extension
),
7857 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7858 fragP
->fr_fix
+= extension
;
7861 /* Apply a fixup (fixP) to segment data, once it has been determined
7862 by our caller that we have all the info we need to fix it up.
7864 Parameter valP is the pointer to the value of the bits.
7866 On the 386, immediates, displacements, and data pointers are all in
7867 the same (little-endian) format, so we don't need to care about which
7871 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
7873 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7874 valueT value
= *valP
;
7876 #if !defined (TE_Mach)
7879 switch (fixP
->fx_r_type
)
7885 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7888 case BFD_RELOC_X86_64_32S
:
7889 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7892 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7895 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7900 if (fixP
->fx_addsy
!= NULL
7901 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7902 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7903 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7904 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7905 && !use_rela_relocations
)
7907 /* This is a hack. There should be a better way to handle this.
7908 This covers for the fact that bfd_install_relocation will
7909 subtract the current location (for partial_inplace, PC relative
7910 relocations); see more below. */
7914 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7917 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7922 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7925 || (symbol_section_p (fixP
->fx_addsy
)
7926 && sym_seg
!= absolute_section
))
7927 && !generic_force_reloc (fixP
))
7929 /* Yes, we add the values in twice. This is because
7930 bfd_install_relocation subtracts them out again. I think
7931 bfd_install_relocation is broken, but I don't dare change
7933 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7937 #if defined (OBJ_COFF) && defined (TE_PE)
7938 /* For some reason, the PE format does not store a
7939 section address offset for a PC relative symbol. */
7940 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7941 || S_IS_WEAK (fixP
->fx_addsy
))
7942 value
+= md_pcrel_from (fixP
);
7945 #if defined (OBJ_COFF) && defined (TE_PE)
7946 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7948 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7952 /* Fix a few things - the dynamic linker expects certain values here,
7953 and we must not disappoint it. */
7954 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7955 if (IS_ELF
&& fixP
->fx_addsy
)
7956 switch (fixP
->fx_r_type
)
7958 case BFD_RELOC_386_PLT32
:
7959 case BFD_RELOC_X86_64_PLT32
:
7960 /* Make the jump instruction point to the address of the operand. At
7961 runtime we merely add the offset to the actual PLT entry. */
7965 case BFD_RELOC_386_TLS_GD
:
7966 case BFD_RELOC_386_TLS_LDM
:
7967 case BFD_RELOC_386_TLS_IE_32
:
7968 case BFD_RELOC_386_TLS_IE
:
7969 case BFD_RELOC_386_TLS_GOTIE
:
7970 case BFD_RELOC_386_TLS_GOTDESC
:
7971 case BFD_RELOC_X86_64_TLSGD
:
7972 case BFD_RELOC_X86_64_TLSLD
:
7973 case BFD_RELOC_X86_64_GOTTPOFF
:
7974 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7975 value
= 0; /* Fully resolved at runtime. No addend. */
7977 case BFD_RELOC_386_TLS_LE
:
7978 case BFD_RELOC_386_TLS_LDO_32
:
7979 case BFD_RELOC_386_TLS_LE_32
:
7980 case BFD_RELOC_X86_64_DTPOFF32
:
7981 case BFD_RELOC_X86_64_DTPOFF64
:
7982 case BFD_RELOC_X86_64_TPOFF32
:
7983 case BFD_RELOC_X86_64_TPOFF64
:
7984 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7987 case BFD_RELOC_386_TLS_DESC_CALL
:
7988 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7989 value
= 0; /* Fully resolved at runtime. No addend. */
7990 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7994 case BFD_RELOC_386_GOT32
:
7995 case BFD_RELOC_X86_64_GOT32
:
7996 value
= 0; /* Fully resolved at runtime. No addend. */
7999 case BFD_RELOC_VTABLE_INHERIT
:
8000 case BFD_RELOC_VTABLE_ENTRY
:
8007 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
8009 #endif /* !defined (TE_Mach) */
8011 /* Are we finished with this relocation now? */
8012 if (fixP
->fx_addsy
== NULL
)
8014 #if defined (OBJ_COFF) && defined (TE_PE)
8015 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8018 /* Remember value for tc_gen_reloc. */
8019 fixP
->fx_addnumber
= value
;
8020 /* Clear out the frag for now. */
8024 else if (use_rela_relocations
)
8026 fixP
->fx_no_overflow
= 1;
8027 /* Remember value for tc_gen_reloc. */
8028 fixP
->fx_addnumber
= value
;
8032 md_number_to_chars (p
, value
, fixP
->fx_size
);
8036 md_atof (int type
, char *litP
, int *sizeP
)
8038 /* This outputs the LITTLENUMs in REVERSE order;
8039 in accord with the bigendian 386. */
8040 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
8043 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
8046 output_invalid (int c
)
8049 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8052 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8053 "(0x%x)", (unsigned char) c
);
8054 return output_invalid_buf
;
8057 /* REG_STRING starts *before* REGISTER_PREFIX. */
8059 static const reg_entry
*
8060 parse_real_register (char *reg_string
, char **end_op
)
8062 char *s
= reg_string
;
8064 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
8067 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8068 if (*s
== REGISTER_PREFIX
)
8071 if (is_space_char (*s
))
8075 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
8077 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
8078 return (const reg_entry
*) NULL
;
8082 /* For naked regs, make sure that we are not dealing with an identifier.
8083 This prevents confusing an identifier like `eax_var' with register
8085 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
8086 return (const reg_entry
*) NULL
;
8090 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
8092 /* Handle floating point regs, allowing spaces in the (i) part. */
8093 if (r
== i386_regtab
/* %st is first entry of table */)
8095 if (is_space_char (*s
))
8100 if (is_space_char (*s
))
8102 if (*s
>= '0' && *s
<= '7')
8106 if (is_space_char (*s
))
8111 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8116 /* We have "%st(" then garbage. */
8117 return (const reg_entry
*) NULL
;
8121 if (r
== NULL
|| allow_pseudo_reg
)
8124 if (operand_type_all_zero (&r
->reg_type
))
8125 return (const reg_entry
*) NULL
;
8127 if ((r
->reg_type
.bitfield
.reg32
8128 || r
->reg_type
.bitfield
.sreg3
8129 || r
->reg_type
.bitfield
.control
8130 || r
->reg_type
.bitfield
.debug
8131 || r
->reg_type
.bitfield
.test
)
8132 && !cpu_arch_flags
.bitfield
.cpui386
)
8133 return (const reg_entry
*) NULL
;
8135 if (r
->reg_type
.bitfield
.floatreg
8136 && !cpu_arch_flags
.bitfield
.cpu8087
8137 && !cpu_arch_flags
.bitfield
.cpu287
8138 && !cpu_arch_flags
.bitfield
.cpu387
)
8139 return (const reg_entry
*) NULL
;
8141 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8142 return (const reg_entry
*) NULL
;
8144 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8145 return (const reg_entry
*) NULL
;
8147 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8148 return (const reg_entry
*) NULL
;
8150 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8151 if (!allow_index_reg
8152 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8153 return (const reg_entry
*) NULL
;
8155 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8156 || r
->reg_type
.bitfield
.reg64
)
8157 && (!cpu_arch_flags
.bitfield
.cpulm
8158 || !operand_type_equal (&r
->reg_type
, &control
))
8159 && flag_code
!= CODE_64BIT
)
8160 return (const reg_entry
*) NULL
;
8162 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8163 return (const reg_entry
*) NULL
;
8168 /* REG_STRING starts *before* REGISTER_PREFIX. */
8170 static const reg_entry
*
8171 parse_register (char *reg_string
, char **end_op
)
8175 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8176 r
= parse_real_register (reg_string
, end_op
);
8181 char *save
= input_line_pointer
;
8185 input_line_pointer
= reg_string
;
8186 c
= get_symbol_end ();
8187 symbolP
= symbol_find (reg_string
);
8188 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8190 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8192 know (e
->X_op
== O_register
);
8193 know (e
->X_add_number
>= 0
8194 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8195 r
= i386_regtab
+ e
->X_add_number
;
8196 *end_op
= input_line_pointer
;
8198 *input_line_pointer
= c
;
8199 input_line_pointer
= save
;
8205 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8208 char *end
= input_line_pointer
;
8211 r
= parse_register (name
, &input_line_pointer
);
8212 if (r
&& end
<= input_line_pointer
)
8214 *nextcharP
= *input_line_pointer
;
8215 *input_line_pointer
= 0;
8216 e
->X_op
= O_register
;
8217 e
->X_add_number
= r
- i386_regtab
;
8220 input_line_pointer
= end
;
8222 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8226 md_operand (expressionS
*e
)
8231 switch (*input_line_pointer
)
8233 case REGISTER_PREFIX
:
8234 r
= parse_real_register (input_line_pointer
, &end
);
8237 e
->X_op
= O_register
;
8238 e
->X_add_number
= r
- i386_regtab
;
8239 input_line_pointer
= end
;
8244 gas_assert (intel_syntax
);
8245 end
= input_line_pointer
++;
8247 if (*input_line_pointer
== ']')
8249 ++input_line_pointer
;
8250 e
->X_op_symbol
= make_expr_symbol (e
);
8251 e
->X_add_symbol
= NULL
;
8252 e
->X_add_number
= 0;
8258 input_line_pointer
= end
;
8265 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8266 const char *md_shortopts
= "kVQ:sqn";
8268 const char *md_shortopts
= "qn";
8271 #define OPTION_32 (OPTION_MD_BASE + 0)
8272 #define OPTION_64 (OPTION_MD_BASE + 1)
8273 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8274 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8275 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8276 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8277 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8278 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8279 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8280 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8281 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8282 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8283 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8284 #define OPTION_X32 (OPTION_MD_BASE + 13)
8286 struct option md_longopts
[] =
8288 {"32", no_argument
, NULL
, OPTION_32
},
8289 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8290 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8291 {"64", no_argument
, NULL
, OPTION_64
},
8293 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8294 {"x32", no_argument
, NULL
, OPTION_X32
},
8296 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8297 {"march", required_argument
, NULL
, OPTION_MARCH
},
8298 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8299 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8300 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8301 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8302 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8303 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8304 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8305 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8306 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8307 {NULL
, no_argument
, NULL
, 0}
8309 size_t md_longopts_size
= sizeof (md_longopts
);
8312 md_parse_option (int c
, char *arg
)
8320 optimize_align_code
= 0;
8327 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8328 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8329 should be emitted or not. FIXME: Not implemented. */
8333 /* -V: SVR4 argument to print version ID. */
8335 print_version_id ();
8338 /* -k: Ignore for FreeBSD compatibility. */
8343 /* -s: On i386 Solaris, this tells the native assembler to use
8344 .stab instead of .stab.excl. We always use .stab anyhow. */
8347 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8348 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8351 const char **list
, **l
;
8353 list
= bfd_target_list ();
8354 for (l
= list
; *l
!= NULL
; l
++)
8355 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8356 || strcmp (*l
, "coff-x86-64") == 0
8357 || strcmp (*l
, "pe-x86-64") == 0
8358 || strcmp (*l
, "pei-x86-64") == 0
8359 || strcmp (*l
, "mach-o-x86-64") == 0)
8361 default_arch
= "x86_64";
8365 as_fatal (_("no compiled in support for x86_64"));
8371 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8375 const char **list
, **l
;
8377 list
= bfd_target_list ();
8378 for (l
= list
; *l
!= NULL
; l
++)
8379 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8381 default_arch
= "x86_64:32";
8385 as_fatal (_("no compiled in support for 32bit x86_64"));
8389 as_fatal (_("32bit x86_64 is only supported for ELF"));
8394 default_arch
= "i386";
8398 #ifdef SVR4_COMMENT_CHARS
8403 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8405 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8409 i386_comment_chars
= n
;
8415 arch
= xstrdup (arg
);
8419 as_fatal (_("invalid -march= option: `%s'"), arg
);
8420 next
= strchr (arch
, '+');
8423 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8425 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8428 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8431 cpu_arch_name
= cpu_arch
[j
].name
;
8432 cpu_sub_arch_name
= NULL
;
8433 cpu_arch_flags
= cpu_arch
[j
].flags
;
8434 cpu_arch_isa
= cpu_arch
[j
].type
;
8435 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8436 if (!cpu_arch_tune_set
)
8438 cpu_arch_tune
= cpu_arch_isa
;
8439 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8443 else if (*cpu_arch
[j
].name
== '.'
8444 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8446 /* ISA entension. */
8447 i386_cpu_flags flags
;
8449 if (!cpu_arch
[j
].negated
)
8450 flags
= cpu_flags_or (cpu_arch_flags
,
8453 flags
= cpu_flags_and_not (cpu_arch_flags
,
8455 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8457 if (cpu_sub_arch_name
)
8459 char *name
= cpu_sub_arch_name
;
8460 cpu_sub_arch_name
= concat (name
,
8462 (const char *) NULL
);
8466 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8467 cpu_arch_flags
= flags
;
8468 cpu_arch_isa_flags
= flags
;
8474 if (j
>= ARRAY_SIZE (cpu_arch
))
8475 as_fatal (_("invalid -march= option: `%s'"), arg
);
8479 while (next
!= NULL
);
8484 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8485 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8487 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8489 cpu_arch_tune_set
= 1;
8490 cpu_arch_tune
= cpu_arch
[j
].type
;
8491 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8495 if (j
>= ARRAY_SIZE (cpu_arch
))
8496 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8499 case OPTION_MMNEMONIC
:
8500 if (strcasecmp (arg
, "att") == 0)
8502 else if (strcasecmp (arg
, "intel") == 0)
8505 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
8508 case OPTION_MSYNTAX
:
8509 if (strcasecmp (arg
, "att") == 0)
8511 else if (strcasecmp (arg
, "intel") == 0)
8514 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
8517 case OPTION_MINDEX_REG
:
8518 allow_index_reg
= 1;
8521 case OPTION_MNAKED_REG
:
8522 allow_naked_reg
= 1;
8525 case OPTION_MOLD_GCC
:
8529 case OPTION_MSSE2AVX
:
8533 case OPTION_MSSE_CHECK
:
8534 if (strcasecmp (arg
, "error") == 0)
8535 sse_check
= sse_check_error
;
8536 else if (strcasecmp (arg
, "warning") == 0)
8537 sse_check
= sse_check_warning
;
8538 else if (strcasecmp (arg
, "none") == 0)
8539 sse_check
= sse_check_none
;
8541 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
8544 case OPTION_MAVXSCALAR
:
8545 if (strcasecmp (arg
, "128") == 0)
8547 else if (strcasecmp (arg
, "256") == 0)
8550 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
8559 #define MESSAGE_TEMPLATE \
8563 show_arch (FILE *stream
, int ext
, int check
)
8565 static char message
[] = MESSAGE_TEMPLATE
;
8566 char *start
= message
+ 27;
8568 int size
= sizeof (MESSAGE_TEMPLATE
);
8575 left
= size
- (start
- message
);
8576 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8578 /* Should it be skipped? */
8579 if (cpu_arch
[j
].skip
)
8582 name
= cpu_arch
[j
].name
;
8583 len
= cpu_arch
[j
].len
;
8586 /* It is an extension. Skip if we aren't asked to show it. */
8597 /* It is an processor. Skip if we show only extension. */
8600 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8602 /* It is an impossible processor - skip. */
8606 /* Reserve 2 spaces for ", " or ",\0" */
8609 /* Check if there is any room. */
8617 p
= mempcpy (p
, name
, len
);
8621 /* Output the current message now and start a new one. */
8624 fprintf (stream
, "%s\n", message
);
8626 left
= size
- (start
- message
) - len
- 2;
8628 gas_assert (left
>= 0);
8630 p
= mempcpy (p
, name
, len
);
8635 fprintf (stream
, "%s\n", message
);
8639 md_show_usage (FILE *stream
)
8641 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8642 fprintf (stream
, _("\
8644 -V print assembler version number\n\
8647 fprintf (stream
, _("\
8648 -n Do not optimize code alignment\n\
8649 -q quieten some warnings\n"));
8650 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8651 fprintf (stream
, _("\
8654 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8655 || defined (TE_PE) || defined (TE_PEP))
8656 fprintf (stream
, _("\
8657 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8659 #ifdef SVR4_COMMENT_CHARS
8660 fprintf (stream
, _("\
8661 --divide do not treat `/' as a comment character\n"));
8663 fprintf (stream
, _("\
8664 --divide ignored\n"));
8666 fprintf (stream
, _("\
8667 -march=CPU[,+EXTENSION...]\n\
8668 generate code for CPU and EXTENSION, CPU is one of:\n"));
8669 show_arch (stream
, 0, 1);
8670 fprintf (stream
, _("\
8671 EXTENSION is combination of:\n"));
8672 show_arch (stream
, 1, 0);
8673 fprintf (stream
, _("\
8674 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8675 show_arch (stream
, 0, 0);
8676 fprintf (stream
, _("\
8677 -msse2avx encode SSE instructions with VEX prefix\n"));
8678 fprintf (stream
, _("\
8679 -msse-check=[none|error|warning]\n\
8680 check SSE instructions\n"));
8681 fprintf (stream
, _("\
8682 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8684 fprintf (stream
, _("\
8685 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8686 fprintf (stream
, _("\
8687 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8688 fprintf (stream
, _("\
8689 -mindex-reg support pseudo index registers\n"));
8690 fprintf (stream
, _("\
8691 -mnaked-reg don't require `%%' prefix for registers\n"));
8692 fprintf (stream
, _("\
8693 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8696 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8697 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8698 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8700 /* Pick the target format to use. */
8703 i386_target_format (void)
8705 if (!strncmp (default_arch
, "x86_64", 6))
8707 update_code_flag (CODE_64BIT
, 1);
8708 if (default_arch
[6] == '\0')
8709 x86_elf_abi
= X86_64_ABI
;
8711 x86_elf_abi
= X86_64_X32_ABI
;
8713 else if (!strcmp (default_arch
, "i386"))
8714 update_code_flag (CODE_32BIT
, 1);
8716 as_fatal (_("unknown architecture"));
8718 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8719 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8720 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8721 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8723 switch (OUTPUT_FLAVOR
)
8725 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8726 case bfd_target_aout_flavour
:
8727 return AOUT_TARGET_FORMAT
;
8729 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8730 # if defined (TE_PE) || defined (TE_PEP)
8731 case bfd_target_coff_flavour
:
8732 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8733 # elif defined (TE_GO32)
8734 case bfd_target_coff_flavour
:
8737 case bfd_target_coff_flavour
:
8741 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8742 case bfd_target_elf_flavour
:
8746 switch (x86_elf_abi
)
8749 format
= ELF_TARGET_FORMAT
;
8752 use_rela_relocations
= 1;
8754 format
= ELF_TARGET_FORMAT64
;
8756 case X86_64_X32_ABI
:
8757 use_rela_relocations
= 1;
8759 disallow_64bit_reloc
= 1;
8760 format
= ELF_TARGET_FORMAT32
;
8763 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8765 if (x86_elf_abi
!= X86_64_ABI
)
8766 as_fatal (_("Intel L1OM is 64bit only"));
8767 return ELF_TARGET_L1OM_FORMAT
;
8769 if (cpu_arch_isa
== PROCESSOR_K1OM
)
8771 if (x86_elf_abi
!= X86_64_ABI
)
8772 as_fatal (_("Intel K1OM is 64bit only"));
8773 return ELF_TARGET_K1OM_FORMAT
;
8779 #if defined (OBJ_MACH_O)
8780 case bfd_target_mach_o_flavour
:
8781 if (flag_code
== CODE_64BIT
)
8783 use_rela_relocations
= 1;
8785 return "mach-o-x86-64";
8788 return "mach-o-i386";
8796 #endif /* OBJ_MAYBE_ more than one */
8798 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8800 i386_elf_emit_arch_note (void)
8802 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8805 asection
*seg
= now_seg
;
8806 subsegT subseg
= now_subseg
;
8807 Elf_Internal_Note i_note
;
8808 Elf_External_Note e_note
;
8809 asection
*note_secp
;
8812 /* Create the .note section. */
8813 note_secp
= subseg_new (".note", 0);
8814 bfd_set_section_flags (stdoutput
,
8816 SEC_HAS_CONTENTS
| SEC_READONLY
);
8818 /* Process the arch string. */
8819 len
= strlen (cpu_arch_name
);
8821 i_note
.namesz
= len
+ 1;
8823 i_note
.type
= NT_ARCH
;
8824 p
= frag_more (sizeof (e_note
.namesz
));
8825 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8826 p
= frag_more (sizeof (e_note
.descsz
));
8827 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8828 p
= frag_more (sizeof (e_note
.type
));
8829 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8830 p
= frag_more (len
+ 1);
8831 strcpy (p
, cpu_arch_name
);
8833 frag_align (2, 0, 0);
8835 subseg_set (seg
, subseg
);
8841 md_undefined_symbol (char *name
)
8843 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8844 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8845 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8846 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8850 if (symbol_find (name
))
8851 as_bad (_("GOT already in symbol table"));
8852 GOT_symbol
= symbol_new (name
, undefined_section
,
8853 (valueT
) 0, &zero_address_frag
);
8860 /* Round up a section size to the appropriate boundary. */
8863 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8865 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8866 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8868 /* For a.out, force the section size to be aligned. If we don't do
8869 this, BFD will align it for us, but it will not write out the
8870 final bytes of the section. This may be a bug in BFD, but it is
8871 easier to fix it here since that is how the other a.out targets
8875 align
= bfd_get_section_alignment (stdoutput
, segment
);
8876 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8883 /* On the i386, PC-relative offsets are relative to the start of the
8884 next instruction. That is, the address of the offset, plus its
8885 size, since the offset is always the last part of the insn. */
8888 md_pcrel_from (fixS
*fixP
)
8890 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8896 s_bss (int ignore ATTRIBUTE_UNUSED
)
8900 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8902 obj_elf_section_change_hook ();
8904 temp
= get_absolute_expression ();
8905 subseg_set (bss_section
, (subsegT
) temp
);
8906 demand_empty_rest_of_line ();
8912 i386_validate_fix (fixS
*fixp
)
8914 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8916 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8920 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8925 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8927 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8934 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
8937 bfd_reloc_code_real_type code
;
8939 switch (fixp
->fx_r_type
)
8941 case BFD_RELOC_X86_64_PLT32
:
8942 case BFD_RELOC_X86_64_GOT32
:
8943 case BFD_RELOC_X86_64_GOTPCREL
:
8944 case BFD_RELOC_386_PLT32
:
8945 case BFD_RELOC_386_GOT32
:
8946 case BFD_RELOC_386_GOTOFF
:
8947 case BFD_RELOC_386_GOTPC
:
8948 case BFD_RELOC_386_TLS_GD
:
8949 case BFD_RELOC_386_TLS_LDM
:
8950 case BFD_RELOC_386_TLS_LDO_32
:
8951 case BFD_RELOC_386_TLS_IE_32
:
8952 case BFD_RELOC_386_TLS_IE
:
8953 case BFD_RELOC_386_TLS_GOTIE
:
8954 case BFD_RELOC_386_TLS_LE_32
:
8955 case BFD_RELOC_386_TLS_LE
:
8956 case BFD_RELOC_386_TLS_GOTDESC
:
8957 case BFD_RELOC_386_TLS_DESC_CALL
:
8958 case BFD_RELOC_X86_64_TLSGD
:
8959 case BFD_RELOC_X86_64_TLSLD
:
8960 case BFD_RELOC_X86_64_DTPOFF32
:
8961 case BFD_RELOC_X86_64_DTPOFF64
:
8962 case BFD_RELOC_X86_64_GOTTPOFF
:
8963 case BFD_RELOC_X86_64_TPOFF32
:
8964 case BFD_RELOC_X86_64_TPOFF64
:
8965 case BFD_RELOC_X86_64_GOTOFF64
:
8966 case BFD_RELOC_X86_64_GOTPC32
:
8967 case BFD_RELOC_X86_64_GOT64
:
8968 case BFD_RELOC_X86_64_GOTPCREL64
:
8969 case BFD_RELOC_X86_64_GOTPC64
:
8970 case BFD_RELOC_X86_64_GOTPLT64
:
8971 case BFD_RELOC_X86_64_PLTOFF64
:
8972 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8973 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8975 case BFD_RELOC_VTABLE_ENTRY
:
8976 case BFD_RELOC_VTABLE_INHERIT
:
8978 case BFD_RELOC_32_SECREL
:
8980 code
= fixp
->fx_r_type
;
8982 case BFD_RELOC_X86_64_32S
:
8983 if (!fixp
->fx_pcrel
)
8985 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8986 code
= fixp
->fx_r_type
;
8992 switch (fixp
->fx_size
)
8995 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8996 _("can not do %d byte pc-relative relocation"),
8998 code
= BFD_RELOC_32_PCREL
;
9000 case 1: code
= BFD_RELOC_8_PCREL
; break;
9001 case 2: code
= BFD_RELOC_16_PCREL
; break;
9002 case 4: code
= BFD_RELOC_32_PCREL
; break;
9004 case 8: code
= BFD_RELOC_64_PCREL
; break;
9010 switch (fixp
->fx_size
)
9013 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9014 _("can not do %d byte relocation"),
9016 code
= BFD_RELOC_32
;
9018 case 1: code
= BFD_RELOC_8
; break;
9019 case 2: code
= BFD_RELOC_16
; break;
9020 case 4: code
= BFD_RELOC_32
; break;
9022 case 8: code
= BFD_RELOC_64
; break;
9029 if ((code
== BFD_RELOC_32
9030 || code
== BFD_RELOC_32_PCREL
9031 || code
== BFD_RELOC_X86_64_32S
)
9033 && fixp
->fx_addsy
== GOT_symbol
)
9036 code
= BFD_RELOC_386_GOTPC
;
9038 code
= BFD_RELOC_X86_64_GOTPC32
;
9040 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
9042 && fixp
->fx_addsy
== GOT_symbol
)
9044 code
= BFD_RELOC_X86_64_GOTPC64
;
9047 rel
= (arelent
*) xmalloc (sizeof (arelent
));
9048 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9049 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9051 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9053 if (!use_rela_relocations
)
9055 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9056 vtable entry to be used in the relocation's section offset. */
9057 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9058 rel
->address
= fixp
->fx_offset
;
9059 #if defined (OBJ_COFF) && defined (TE_PE)
9060 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
9061 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
9066 /* Use the rela in 64bit mode. */
9069 if (disallow_64bit_reloc
)
9072 case BFD_RELOC_X86_64_DTPOFF64
:
9073 case BFD_RELOC_X86_64_TPOFF64
:
9074 case BFD_RELOC_64_PCREL
:
9075 case BFD_RELOC_X86_64_GOTOFF64
:
9076 case BFD_RELOC_X86_64_GOT64
:
9077 case BFD_RELOC_X86_64_GOTPCREL64
:
9078 case BFD_RELOC_X86_64_GOTPC64
:
9079 case BFD_RELOC_X86_64_GOTPLT64
:
9080 case BFD_RELOC_X86_64_PLTOFF64
:
9081 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9082 _("cannot represent relocation type %s in x32 mode"),
9083 bfd_get_reloc_code_name (code
));
9089 if (!fixp
->fx_pcrel
)
9090 rel
->addend
= fixp
->fx_offset
;
9094 case BFD_RELOC_X86_64_PLT32
:
9095 case BFD_RELOC_X86_64_GOT32
:
9096 case BFD_RELOC_X86_64_GOTPCREL
:
9097 case BFD_RELOC_X86_64_TLSGD
:
9098 case BFD_RELOC_X86_64_TLSLD
:
9099 case BFD_RELOC_X86_64_GOTTPOFF
:
9100 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9101 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9102 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
9105 rel
->addend
= (section
->vma
9107 + fixp
->fx_addnumber
9108 + md_pcrel_from (fixp
));
9113 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9114 if (rel
->howto
== NULL
)
9116 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9117 _("cannot represent relocation type %s"),
9118 bfd_get_reloc_code_name (code
));
9119 /* Set howto to a garbage value so that we can keep going. */
9120 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
9121 gas_assert (rel
->howto
!= NULL
);
9127 #include "tc-i386-intel.c"
9130 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9132 int saved_naked_reg
;
9133 char saved_register_dot
;
9135 saved_naked_reg
= allow_naked_reg
;
9136 allow_naked_reg
= 1;
9137 saved_register_dot
= register_chars
['.'];
9138 register_chars
['.'] = '.';
9139 allow_pseudo_reg
= 1;
9140 expression_and_evaluate (exp
);
9141 allow_pseudo_reg
= 0;
9142 register_chars
['.'] = saved_register_dot
;
9143 allow_naked_reg
= saved_naked_reg
;
9145 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9147 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9149 exp
->X_op
= O_constant
;
9150 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9151 .dw2_regnum
[flag_code
>> 1];
9154 exp
->X_op
= O_illegal
;
9159 tc_x86_frame_initial_instructions (void)
9161 static unsigned int sp_regno
[2];
9163 if (!sp_regno
[flag_code
>> 1])
9165 char *saved_input
= input_line_pointer
;
9166 char sp
[][4] = {"esp", "rsp"};
9169 input_line_pointer
= sp
[flag_code
>> 1];
9170 tc_x86_parse_to_dw2regnum (&exp
);
9171 gas_assert (exp
.X_op
== O_constant
);
9172 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9173 input_line_pointer
= saved_input
;
9176 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9177 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9181 x86_dwarf2_addr_size (void)
9183 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9184 if (x86_elf_abi
== X86_64_X32_ABI
)
9187 return bfd_arch_bits_per_address (stdoutput
) / 8;
9191 i386_elf_section_type (const char *str
, size_t len
)
9193 if (flag_code
== CODE_64BIT
9194 && len
== sizeof ("unwind") - 1
9195 && strncmp (str
, "unwind", 6) == 0)
9196 return SHT_X86_64_UNWIND
;
9203 i386_solaris_fix_up_eh_frame (segT sec
)
9205 if (flag_code
== CODE_64BIT
)
9206 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9212 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9216 exp
.X_op
= O_secrel
;
9217 exp
.X_add_symbol
= symbol
;
9218 exp
.X_add_number
= 0;
9219 emit_expr (&exp
, size
);
9223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9224 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9227 x86_64_section_letter (int letter
, char **ptr_msg
)
9229 if (flag_code
== CODE_64BIT
)
9232 return SHF_X86_64_LARGE
;
9234 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9237 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9242 x86_64_section_word (char *str
, size_t len
)
9244 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9245 return SHF_X86_64_LARGE
;
9251 handle_large_common (int small ATTRIBUTE_UNUSED
)
9253 if (flag_code
!= CODE_64BIT
)
9255 s_comm_internal (0, elf_common_parse
);
9256 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9260 static segT lbss_section
;
9261 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9262 asection
*saved_bss_section
= bss_section
;
9264 if (lbss_section
== NULL
)
9266 flagword applicable
;
9268 subsegT subseg
= now_subseg
;
9270 /* The .lbss section is for local .largecomm symbols. */
9271 lbss_section
= subseg_new (".lbss", 0);
9272 applicable
= bfd_applicable_section_flags (stdoutput
);
9273 bfd_set_section_flags (stdoutput
, lbss_section
,
9274 applicable
& SEC_ALLOC
);
9275 seg_info (lbss_section
)->bss
= 1;
9277 subseg_set (seg
, subseg
);
9280 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9281 bss_section
= lbss_section
;
9283 s_comm_internal (0, elf_common_parse
);
9285 elf_com_section_ptr
= saved_com_section_ptr
;
9286 bss_section
= saved_bss_section
;
9289 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */