1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #include "bfin-aux.h" /* Opcode generating auxiliaries. */
28 #include "elf/common.h"
31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
32 bfin_gen_dsp32alu
(HL
, aopcde
, aop
, s
, x
, dst0
, dst1
, src0
, src1
)
34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
35 bfin_gen_dsp32mac
(op1
, MM
, mmod
, w1
, P
, h01
, h11
, h00
, h10
, op0
, \
38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
39 bfin_gen_dsp32mult
(op1
, MM
, mmod
, w1
, P
, h01
, h11
, h00
, h10
, op0
, \
42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
43 bfin_gen_dsp32shift
(sopcde
, dst0
, src0
, src1
, sop
, hls
)
45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
46 bfin_gen_dsp32shiftimm
(sopcde
, dst0
, immag
, src1
, sop
, hls
)
48 #define LDIMMHALF_R(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf
(reg
, h
, s
, z
, hword
, 1)
51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
52 bfin_gen_ldimmhalf
(reg
, h
, s
, z
, hword
, 2)
54 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
55 bfin_gen_ldstidxi
(ptr
, reg
, w
, sz
, z
, offset
)
57 #define LDST(ptr, reg, aop, sz, z, w) \
58 bfin_gen_ldst
(ptr
, reg
, aop
, sz
, z
, w
)
60 #define LDSTII(ptr, reg, offset, w, op) \
61 bfin_gen_ldstii
(ptr
, reg
, offset
, w
, op
)
63 #define DSPLDST(i, m, reg, aop, w) \
64 bfin_gen_dspldst
(i
, reg
, aop
, w
, m
)
66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
67 bfin_gen_ldstpmod
(ptr
, reg
, aop
, w
, idx
)
69 #define LDSTIIFP(offset, reg, w) \
70 bfin_gen_ldstiifp
(reg
, offset
, w
)
72 #define LOGI2OP(dst, src, opc) \
73 bfin_gen_logi2op
(opc
, src
, dst.regno
& CODE_MASK
)
75 #define ALU2OP(dst, src, opc) \
76 bfin_gen_alu2op
(dst
, src
, opc
)
78 #define BRCC(t, b, offset) \
79 bfin_gen_brcc
(t
, b
, offset
)
81 #define UJUMP(offset) \
82 bfin_gen_ujump
(offset
)
84 #define PROGCTRL(prgfunc, poprnd) \
85 bfin_gen_progctrl
(prgfunc
, poprnd
)
87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
88 bfin_gen_pushpopmultiple
(dr
, pr
, d
, p
, w
)
90 #define PUSHPOPREG(reg, w) \
91 bfin_gen_pushpopreg
(reg
, w
)
93 #define CALLA(addr, s) \
94 bfin_gen_calla
(addr
, s
)
96 #define LINKAGE(r, framesize) \
97 bfin_gen_linkage
(r
, framesize
)
99 #define COMPI2OPD(dst, src, op) \
100 bfin_gen_compi2opd
(dst
, src
, op
)
102 #define COMPI2OPP(dst, src, op) \
103 bfin_gen_compi2opp
(dst
, src
, op
)
105 #define DAGMODIK(i, op) \
106 bfin_gen_dagmodik
(i
, op
)
108 #define DAGMODIM(i, m, op, br) \
109 bfin_gen_dagmodim
(i
, m
, op
, br
)
111 #define COMP3OP(dst, src0, src1, opc) \
112 bfin_gen_comp3op
(src0
, src1
, dst
, opc
)
114 #define PTR2OP(dst, src, opc) \
115 bfin_gen_ptr2op
(dst
, src
, opc
)
117 #define CCFLAG(x, y, opc, i, g) \
118 bfin_gen_ccflag
(x
, y
, opc
, i
, g
)
120 #define CCMV(src, dst, t) \
121 bfin_gen_ccmv
(src
, dst
, t
)
123 #define CACTRL(reg, a, op) \
124 bfin_gen_cactrl
(reg
, a
, op
)
126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
127 bfin_gen_loopsetup
(soffset
, c
, rop
, eoffset
, reg
)
129 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
130 #define IS_RANGE(bits, expr, sign, mul) \
131 value_match
(expr
, bits
, sign
, mul
, 1)
132 #define IS_URANGE(bits, expr, sign, mul) \
133 value_match
(expr
, bits
, sign
, mul
, 0)
134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
136 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
137 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
139 #define IS_PCREL4(expr) \
140 (value_match
(expr
, 4, 0, 2, 0))
142 #define IS_LPPCREL10(expr) \
143 (value_match
(expr
, 10, 0, 2, 0))
145 #define IS_PCREL10(expr) \
146 (value_match
(expr
, 10, 0, 2, 1))
148 #define IS_PCREL12(expr) \
149 (value_match
(expr
, 12, 0, 2, 1))
151 #define IS_PCREL24(expr) \
152 (value_match
(expr
, 24, 0, 2, 1))
155 static int value_match
(Expr_Node
*, int, int, int, int);
160 static Expr_Node
*binary
(Expr_Op_Type
, Expr_Node
*, Expr_Node
*);
161 static Expr_Node
*unary
(Expr_Op_Type
, Expr_Node
*);
163 static void notethat
(char *, ...
);
165 char *current_inputline
;
167 int yyerror (char *);
169 /* Used to set SRCx fields to all 1s as described in the PRM. */
170 static Register reg7
= {REG_R7
, 0};
172 void error (char *format
, ...
)
175 static char buffer
[2000];
177 va_start
(ap
, format
);
178 vsprintf
(buffer
, format
, ap
);
181 as_bad
("%s", buffer
);
190 else if
(yytext
[0] != ';')
191 error ("%s. Input text was %s.", msg
, yytext
);
199 in_range_p
(Expr_Node
*exp
, int from
, int to
, unsigned int mask
)
201 int val
= EXPR_VALUE
(exp
);
202 if
(exp
->type
!= Expr_Node_Constant
)
204 if
(val
< from || val
> to
)
206 return
(val
& mask
) == 0;
209 extern
int yylex (void);
211 #define imm3(x) EXPR_VALUE (x)
212 #define imm4(x) EXPR_VALUE (x)
213 #define uimm4(x) EXPR_VALUE (x)
214 #define imm5(x) EXPR_VALUE (x)
215 #define uimm5(x) EXPR_VALUE (x)
216 #define imm6(x) EXPR_VALUE (x)
217 #define imm7(x) EXPR_VALUE (x)
218 #define uimm8(x) EXPR_VALUE (x)
219 #define imm16(x) EXPR_VALUE (x)
220 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
221 #define uimm16(x) EXPR_VALUE (x)
223 /* Return true if a value is inside a range. */
224 #define IN_RANGE(x, low, high) \
225 (((EXPR_VALUE
(x
)) >= (low
)) && (EXPR_VALUE
(x
)) <= ((high
)))
227 /* Auxiliary functions. */
230 valid_dreg_pair
(Register
*reg1
, Expr_Node
*reg2
)
232 if
(!IS_DREG
(*reg1
))
234 yyerror ("Dregs expected");
238 if
(reg1
->regno
!= 1 && reg1
->regno
!= 3)
240 yyerror ("Bad register pair");
244 if
(imm7
(reg2
) != reg1
->regno
- 1)
246 yyerror ("Bad register pair");
255 check_multiply_halfregs
(Macfunc
*aa
, Macfunc
*ab
)
257 if
((!REG_EQUAL
(aa
->s0
, ab
->s0
) && !REG_EQUAL
(aa
->s0
, ab
->s1
))
258 ||
(!REG_EQUAL
(aa
->s1
, ab
->s1
) && !REG_EQUAL
(aa
->s1
, ab
->s0
)))
259 return
yyerror ("Source multiplication register mismatch");
265 /* Check mac option. */
268 check_macfunc_option
(Macfunc
*a
, Opt_mode
*opt
)
270 /* Default option is always valid. */
274 if
((a
->w
== 1 && a
->P
== 1
275 && opt
->mod
!= M_FU
&& opt
->mod
!= M_IS
&& opt
->mod
!= M_IU
276 && opt
->mod
!= M_S2RND
&& opt
->mod
!= M_ISS2
)
277 ||
(a
->w
== 1 && a
->P
== 0
278 && opt
->mod
!= M_FU
&& opt
->mod
!= M_IS
&& opt
->mod
!= M_IU
279 && opt
->mod
!= M_T
&& opt
->mod
!= M_TFU
&& opt
->mod
!= M_S2RND
280 && opt
->mod
!= M_ISS2
&& opt
->mod
!= M_IH
)
281 ||
(a
->w
== 0 && a
->P
== 0
282 && opt
->mod
!= M_FU
&& opt
->mod
!= M_IS
&& opt
->mod
!= M_W32
))
288 /* Check (vector) mac funcs and ops. */
291 check_macfuncs
(Macfunc
*aa
, Opt_mode
*opa
,
292 Macfunc
*ab
, Opt_mode
*opb
)
294 /* Variables for swapping. */
298 /* The option mode should be put at the end of the second instruction
299 of the vector except M, which should follow MAC1 instruction. */
301 return
yyerror ("Bad opt mode");
303 /* If a0macfunc comes before a1macfunc, swap them. */
307 /* (M) is not allowed here. */
309 return
yyerror ("(M) not allowed with A0MAC");
311 return
yyerror ("Vector AxMACs can't be same");
313 mtmp
= *aa
; *aa
= *ab
; *ab
= mtmp
;
314 otmp
= *opa
; *opa
= *opb
; *opb
= otmp
;
319 return
yyerror ("(M) not allowed with A0MAC");
321 return
yyerror ("Vector AxMACs can't be same");
324 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
325 assignment_or_macfuncs. */
326 if
((aa
->op
== 0 || aa
->op
== 1 || aa
->op
== 2)
327 && (ab
->op
== 0 || ab
->op
== 1 || ab
->op
== 2))
329 if
(check_multiply_halfregs
(aa
, ab
) < 0)
334 /* Only one of the assign_macfuncs has a half reg multiply
335 Evil trick: Just 'OR' their source register codes:
336 We can do that, because we know they were initialized to 0
337 in the rules that don't use multiply_halfregs. */
338 aa
->s0.regno |
= (ab
->s0.regno
& CODE_MASK
);
339 aa
->s1.regno |
= (ab
->s1.regno
& CODE_MASK
);
342 if
(aa
->w
== ab
->w
&& aa
->P
!= ab
->P
)
343 return
yyerror ("Destination Dreg sizes (full or half) must match");
347 if
(aa
->P
&& (aa
->dst.regno
- ab
->dst.regno
) != 1)
348 return
yyerror ("Destination Dregs (full) must differ by one");
349 if
(!aa
->P
&& aa
->dst.regno
!= ab
->dst.regno
)
350 return
yyerror ("Destination Dregs (half) must match");
353 /* Make sure mod flags get ORed, too. */
354 opb
->mod |
= opa
->mod
;
357 if
(check_macfunc_option
(aa
, opb
) < 0
358 && check_macfunc_option
(ab
, opb
) < 0)
359 return
yyerror ("bad option");
361 /* Make sure first macfunc has got both P flags ORed. */
369 is_group1
(INSTR_T x
)
371 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
372 if
((x
->value
& 0xc000) == 0x8000 ||
(x
->value
== 0x0000))
379 is_group2
(INSTR_T x
)
381 if
((((x
->value
& 0xfc00) == 0x9c00) /* dspLDST. */
382 && !((x
->value
& 0xfde0) == 0x9c60) /* dagMODim. */
383 && !((x
->value
& 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
384 && !((x
->value
& 0xfde0) == 0x9d60)) /* pick dagMODik. */
385 ||
(x
->value
== 0x0000))
396 if
((x
->value
& 0xf000) == 0x8000)
398 int aop
= ((x
->value
>> 9) & 0x3);
399 int w
= ((x
->value
>> 11) & 0x1);
405 if
(((x
->value
& 0xFF60) == 0x9E60) ||
/* dagMODim_0 */
406 ((x
->value
& 0xFFF0) == 0x9F60)) /* dagMODik_0 */
409 /* decode_dspLDST_0 */
410 if
((x
->value
& 0xFC00) == 0x9C00)
412 int w
= ((x
->value
>> 9) & 0x1);
421 gen_multi_instr_1
(INSTR_T dsp32
, INSTR_T dsp16_grp1
, INSTR_T dsp16_grp2
)
423 int mask1
= dsp32 ? insn_regmask
(dsp32
->value
, dsp32
->next
->value
) : 0;
424 int mask2
= dsp16_grp1 ? insn_regmask
(dsp16_grp1
->value
, 0) : 0;
425 int mask3
= dsp16_grp2 ? insn_regmask
(dsp16_grp2
->value
, 0) : 0;
427 if
((mask1
& mask2
) ||
(mask1
& mask3
) ||
(mask2
& mask3
))
428 yyerror ("resource conflict in multi-issue instruction");
430 /* Anomaly 05000074 */
431 if
(ENABLE_AC_05000074
432 && dsp32
!= NULL
&& dsp16_grp1
!= NULL
433 && (dsp32
->value
& 0xf780) == 0xc680
434 && ((dsp16_grp1
->value
& 0xfe40) == 0x9240
435 ||
(dsp16_grp1
->value
& 0xfe08) == 0xba08
436 ||
(dsp16_grp1
->value
& 0xfc00) == 0xbc00))
437 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
438 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
440 if
(is_store
(dsp16_grp1
) && is_store
(dsp16_grp2
))
441 yyerror ("Only one instruction in multi-issue instruction can be a store");
443 return bfin_gen_multi_instr
(dsp32
, dsp16_grp1
, dsp16_grp2
);
455 struct { int r0
; int s0
; int x0
; int aop
; } modcodes
;
456 struct { int r0
; } r0
;
463 /* Vector Specific. */
464 %token BYTEOP16P BYTEOP16M
465 %token BYTEOP1P BYTEOP2P BYTEOP3P
466 %token BYTEUNPACK BYTEPACK
469 %token ALIGN8 ALIGN16 ALIGN24
471 %token EXTRACT DEPOSIT EXPADJ SEARCH
472 %token ONES SIGN SIGNBITS
480 %token CCREG BYTE_DREG
481 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
482 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
487 %token RTI RTS RTX RTN RTE
498 %token JUMP JUMP_DOT_S JUMP_DOT_L
505 %token NOT TILDA BANG
511 %token MINUS PLUS STAR SLASH
515 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
516 %token _MINUS_MINUS _PLUS_PLUS
518 /* Shift/rotate ops. */
519 %token SHIFT LSHIFT ASHIFT BXORSHIFT
520 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
522 %token LESS_LESS GREATER_GREATER
523 %token _GREATER_GREATER_GREATER
524 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
527 /* In place operators. */
528 %token ASSIGN _STAR_ASSIGN
529 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
530 %token _MINUS_ASSIGN _PLUS_ASSIGN
532 /* Assignments, comparisons. */
533 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
538 %token FLUSHINV FLUSH
539 %token IFLUSH PREFETCH
556 %token R RND RNDL RNDH RND12 RND20
561 %token BITTGL BITCLR BITSET BITTST BITMUX
564 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
566 /* Semantic auxiliaries. */
569 %token COLON SEMICOLON
570 %token RPAREN LPAREN LBRACK RBRACK
574 %token GOT GOT17M4 FUNCDESC_GOT17M4
584 %type
<modcodes
> byteop_mod
586 %type
<reg
> a_plusassign
587 %type
<reg
> a_minusassign
588 %type
<macfunc
> multiply_halfregs
589 %type
<macfunc
> assign_macfunc
590 %type
<macfunc
> a_macfunc
594 %type
<modcodes
> vsmod
595 %type
<modcodes
> ccstat
598 %type
<reg
> reg_with_postinc
599 %type
<reg
> reg_with_predec
603 %type
<symbol
> SYMBOL
606 %type
<reg
> BYTE_DREG
607 %type
<reg
> REG_A_DOUBLE_ZERO
608 %type
<reg
> REG_A_DOUBLE_ONE
610 %type
<reg
> STATUS_REG
614 %type
<modcodes
> smod
615 %type
<modcodes
> b3_op
616 %type
<modcodes
> rnd_op
617 %type
<modcodes
> post_op
619 %type
<r0
> iu_or_nothing
620 %type
<r0
> plus_minus
624 %type
<modcodes
> amod0
625 %type
<modcodes
> amod1
626 %type
<modcodes
> amod2
628 %type
<r0
> w32_or_nothing
632 %type
<expr
> got_or_expr
634 %type
<value
> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
636 /* Precedence rules. */
640 %left LESS_LESS GREATER_GREATER
642 %left STAR SLASH PERCENT
653 if
(insn
== (INSTR_T
) 0)
654 return NO_INSN_GENERATED
;
655 else if
(insn
== (INSTR_T
) - 1)
656 return SEMANTIC_ERROR
;
658 return INSN_GENERATED
;
663 /* Parallel instructions. */
664 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
666 if
(($1->value
& 0xf800) == 0xc000)
668 if
(is_group1
($3) && is_group2
($5))
669 $$
= gen_multi_instr_1
($1, $3, $5);
670 else if
(is_group2
($3) && is_group1
($5))
671 $$
= gen_multi_instr_1
($1, $5, $3);
673 return
yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
675 else if
(($3->value
& 0xf800) == 0xc000)
677 if
(is_group1
($1) && is_group2
($5))
678 $$
= gen_multi_instr_1
($3, $1, $5);
679 else if
(is_group2
($1) && is_group1
($5))
680 $$
= gen_multi_instr_1
($3, $5, $1);
682 return
yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
684 else if
(($5->value
& 0xf800) == 0xc000)
686 if
(is_group1
($1) && is_group2
($3))
687 $$
= gen_multi_instr_1
($5, $1, $3);
688 else if
(is_group2
($1) && is_group1
($3))
689 $$
= gen_multi_instr_1
($5, $3, $1);
691 return
yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
694 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
697 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
699 if
(($1->value
& 0xf800) == 0xc000)
702 $$
= gen_multi_instr_1
($1, $3, 0);
703 else if
(is_group2
($3))
704 $$
= gen_multi_instr_1
($1, 0, $3);
706 return
yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
708 else if
(($3->value
& 0xf800) == 0xc000)
711 $$
= gen_multi_instr_1
($3, $1, 0);
712 else if
(is_group2
($1))
713 $$
= gen_multi_instr_1
($3, 0, $1);
715 return
yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
717 else if
(is_group1
($1) && is_group2
($3))
718 $$
= gen_multi_instr_1
(0, $1, $3);
719 else if
(is_group2
($1) && is_group1
($3))
720 $$
= gen_multi_instr_1
(0, $3, $1);
722 return
yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
737 $$
= DSP32MAC
(3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
739 | assign_macfunc opt_mode
743 int h00
, h10
, h01
, h11
;
745 if
(check_macfunc_option
(&$1, &$2) < 0)
746 return
yyerror ("bad option");
751 return
yyerror ("(m) not allowed with a0 unit");
770 $$
= DSP32MAC
(op1
, $2.MM
, $2.mod
, w1
, $1.P
, h01
, h11
, h00
, h10
,
771 &$1.dst
, op0
, &$1.s0
, &$1.s1
, w0
);
777 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
781 if
(check_macfuncs
(&$1, &$2, &$4, &$5) < 0)
783 notethat
("assign_macfunc (.), assign_macfunc (.)\n");
790 $$
= DSP32MAC
($1.op
, $2.MM
, $5.mod
, $1.w
, $1.P
,
791 IS_H
($1.s0
), IS_H
($1.s1
), IS_H
($4.s0
), IS_H
($4.s1
),
792 dst
, $4.op
, &$1.s0
, &$1.s1
, $4.w
);
799 notethat
("dsp32alu: DISALGNEXCPT\n");
800 $$
= DSP32ALU
(18, 0, 0, 0, 0, 0, 0, 0, 3);
802 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
804 if
(IS_DREG
($1) && !IS_A1
($4) && IS_A1
($5))
806 notethat
("dsp32alu: dregs = ( A0 += A1 )\n");
807 $$
= DSP32ALU
(11, 0, 0, &$1, ®7
, ®7
, 0, 0, 0);
810 return
yyerror ("Register mismatch");
812 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
814 if
(!IS_A1
($4) && IS_A1
($5))
816 notethat
("dsp32alu: dregs_half = ( A0 += A1 )\n");
817 $$
= DSP32ALU
(11, IS_H
($1), 0, &$1, ®7
, ®7
, 0, 0, 1);
820 return
yyerror ("Register mismatch");
822 | A_ZERO_DOT_H ASSIGN HALF_REG
824 notethat
("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
825 $$
= DSP32ALU
(9, IS_H
($3), 0, 0, &$3, 0, 0, 0, 0);
827 | A_ONE_DOT_H ASSIGN HALF_REG
829 notethat
("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
830 $$
= DSP32ALU
(9, IS_H
($3), 0, 0, &$3, 0, 0, 0, 2);
832 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
833 COLON expr COMMA REG COLON expr RPAREN aligndir
835 if
(!IS_DREG
($2) ||
!IS_DREG
($4))
836 return
yyerror ("Dregs expected");
837 else if
(REG_SAME
($2, $4))
838 return
yyerror ("Illegal dest register combination");
839 else if
(!valid_dreg_pair
(&$9, $11))
840 return
yyerror ("Bad dreg pair");
841 else if
(!valid_dreg_pair
(&$13, $15))
842 return
yyerror ("Bad dreg pair");
845 notethat
("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (aligndir)\n");
846 $$
= DSP32ALU
(21, 0, &$2, &$4, &$9, &$13, $17.r0
, 0, 0);
850 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
851 REG COLON expr RPAREN aligndir
853 if
(!IS_DREG
($2) ||
!IS_DREG
($4))
854 return
yyerror ("Dregs expected");
855 else if
(REG_SAME
($2, $4))
856 return
yyerror ("Illegal dest register combination");
857 else if
(!valid_dreg_pair
(&$9, $11))
858 return
yyerror ("Bad dreg pair");
859 else if
(!valid_dreg_pair
(&$13, $15))
860 return
yyerror ("Bad dreg pair");
863 notethat
("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
864 $$
= DSP32ALU
(21, 0, &$2, &$4, &$9, &$13, $17.r0
, 0, 1);
868 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
870 if
(!IS_DREG
($2) ||
!IS_DREG
($4))
871 return
yyerror ("Dregs expected");
872 else if
(REG_SAME
($2, $4))
873 return
yyerror ("Illegal dest register combination");
874 else if
(!valid_dreg_pair
(&$8, $10))
875 return
yyerror ("Bad dreg pair");
878 notethat
("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
879 $$
= DSP32ALU
(24, 0, &$2, &$4, &$8, 0, $11.r0
, 0, 1);
882 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
884 if
(REG_SAME
($2, $4))
885 return
yyerror ("Illegal dest register combination");
887 if
(IS_DREG
($2) && IS_DREG
($4) && IS_DREG
($8))
889 notethat
("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
890 $$
= DSP32ALU
(13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0
);
893 return
yyerror ("Register mismatch");
895 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
896 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
898 if
(REG_SAME
($1, $7))
899 return
yyerror ("Illegal dest register combination");
901 if
(IS_DREG
($1) && IS_DREG
($7))
903 notethat
("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
904 $$
= DSP32ALU
(12, 0, &$1, &$7, ®7
, ®7
, 0, 0, 1);
907 return
yyerror ("Register mismatch");
911 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
913 if
(REG_SAME
($1, $7))
914 return
yyerror ("Resource conflict in dest reg");
916 if
(IS_DREG
($1) && IS_DREG
($7) && !REG_SAME
($3, $5)
917 && IS_A1
($9) && !IS_A1
($11))
919 notethat
("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
920 $$
= DSP32ALU
(17, 0, &$1, &$7, ®7
, ®7
, $12.s0
, $12.x0
, 0);
923 else if
(IS_DREG
($1) && IS_DREG
($7) && !REG_SAME
($3, $5)
924 && !IS_A1
($9) && IS_A1
($11))
926 notethat
("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
927 $$
= DSP32ALU
(17, 0, &$1, &$7, ®7
, ®7
, $12.s0
, $12.x0
, 1);
930 return
yyerror ("Register mismatch");
933 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
936 return
yyerror ("Operators must differ");
938 if
(IS_DREG
($1) && IS_DREG
($3) && IS_DREG
($5)
939 && REG_SAME
($3, $9) && REG_SAME
($5, $11))
941 notethat
("dsp32alu: dregs = dregs + dregs,"
942 "dregs = dregs - dregs (amod1)\n");
943 $$
= DSP32ALU
(4, 0, &$1, &$7, &$3, &$5, $12.s0
, $12.x0
, 2);
946 return
yyerror ("Register mismatch");
949 /* Bar Operations. */
951 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
953 if
(!REG_SAME
($3, $9) ||
!REG_SAME
($5, $11))
954 return
yyerror ("Differing source registers");
956 if
(!IS_DREG
($1) ||
!IS_DREG
($3) ||
!IS_DREG
($5) ||
!IS_DREG
($7))
957 return
yyerror ("Dregs expected");
959 if
(REG_SAME
($1, $7))
960 return
yyerror ("Resource conflict in dest reg");
962 if
($4.r0
== 1 && $10.r0
== 2)
964 notethat
("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
965 $$
= DSP32ALU
(1, 1, &$1, &$7, &$3, &$5, $12.s0
, $12.x0
, $12.r0
);
967 else if
($4.r0
== 0 && $10.r0
== 3)
969 notethat
("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
970 $$
= DSP32ALU
(1, 0, &$1, &$7, &$3, &$5, $12.s0
, $12.x0
, $12.r0
);
973 return
yyerror ("Bar operand mismatch");
976 | REG ASSIGN ABS REG vmod
980 if
(IS_DREG
($1) && IS_DREG
($4))
984 notethat
("dsp32alu: dregs = ABS dregs (v)\n");
989 /* Vector version of ABS. */
990 notethat
("dsp32alu: dregs = ABS dregs\n");
993 $$
= DSP32ALU
(op
, 0, 0, &$1, &$4, 0, 0, 0, 2);
996 return
yyerror ("Dregs expected");
1000 notethat
("dsp32alu: Ax = ABS Ax\n");
1001 $$
= DSP32ALU
(16, IS_A1
($1), 0, 0, ®7
, ®7
, 0, 0, IS_A1
($3));
1003 | A_ZERO_DOT_L ASSIGN HALF_REG
1007 notethat
("dsp32alu: A0.l = reg_half\n");
1008 $$
= DSP32ALU
(9, IS_H
($3), 0, 0, &$3, 0, 0, 0, 0);
1011 return
yyerror ("A0.l = Rx.l expected");
1013 | A_ONE_DOT_L ASSIGN HALF_REG
1017 notethat
("dsp32alu: A1.l = reg_half\n");
1018 $$
= DSP32ALU
(9, IS_H
($3), 0, 0, &$3, 0, 0, 0, 2);
1021 return
yyerror ("A1.l = Rx.l expected");
1024 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
1026 if
(IS_DREG
($1) && IS_DREG
($5) && IS_DREG
($7))
1028 notethat
("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
1029 $$
= DSP32SHIFT
(13, &$1, &$7, &$5, $3.r0
, 0);
1032 return
yyerror ("Dregs expected");
1035 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
1038 return
yyerror ("Dregs expected");
1039 else if
(!valid_dreg_pair
(&$5, $7))
1040 return
yyerror ("Bad dreg pair");
1041 else if
(!valid_dreg_pair
(&$9, $11))
1042 return
yyerror ("Bad dreg pair");
1045 notethat
("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1046 $$
= DSP32ALU
(20, 0, 0, &$1, &$5, &$9, $13.s0
, 0, $13.r0
);
1049 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1052 return
yyerror ("Dregs expected");
1053 else if
(!valid_dreg_pair
(&$5, $7))
1054 return
yyerror ("Bad dreg pair");
1055 else if
(!valid_dreg_pair
(&$9, $11))
1056 return
yyerror ("Bad dreg pair");
1059 notethat
("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1060 $$
= DSP32ALU
(20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1064 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1068 return
yyerror ("Dregs expected");
1069 else if
(!valid_dreg_pair
(&$5, $7))
1070 return
yyerror ("Bad dreg pair");
1071 else if
(!valid_dreg_pair
(&$9, $11))
1072 return
yyerror ("Bad dreg pair");
1075 notethat
("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1076 $$
= DSP32ALU
(22, $13.r0
, 0, &$1, &$5, &$9, $13.s0
, $13.x0
, $13.aop
);
1080 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1084 return
yyerror ("Dregs expected");
1085 else if
(!valid_dreg_pair
(&$5, $7))
1086 return
yyerror ("Bad dreg pair");
1087 else if
(!valid_dreg_pair
(&$9, $11))
1088 return
yyerror ("Bad dreg pair");
1091 notethat
("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1092 $$
= DSP32ALU
(23, $13.x0
, 0, &$1, &$5, &$9, $13.s0
, 0, 0);
1096 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1098 if
(IS_DREG
($1) && IS_DREG
($5) && IS_DREG
($7))
1100 notethat
("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1101 $$
= DSP32ALU
(24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1104 return
yyerror ("Dregs expected");
1107 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1108 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1110 if
(IS_HCOMPL
($1, $3) && IS_HCOMPL
($7, $14) && IS_HCOMPL
($10, $17))
1112 notethat
("dsp32alu: dregs_hi = dregs_lo ="
1113 "SIGN (dregs_hi) * dregs_hi + "
1114 "SIGN (dregs_lo) * dregs_lo \n");
1116 $$
= DSP32ALU
(12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1119 return
yyerror ("Dregs expected");
1121 | REG ASSIGN REG plus_minus REG amod1
1123 if
(IS_DREG
($1) && IS_DREG
($3) && IS_DREG
($5))
1127 /* No saturation flag specified, generate the 16 bit variant. */
1128 notethat
("COMP3op: dregs = dregs +- dregs\n");
1129 $$
= COMP3OP
(&$1, &$3, &$5, $4.r0
);
1133 /* Saturation flag specified, generate the 32 bit variant. */
1134 notethat
("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1135 $$
= DSP32ALU
(4, 0, 0, &$1, &$3, &$5, $6.s0
, $6.x0
, $4.r0
);
1139 if
(IS_PREG
($1) && IS_PREG
($3) && IS_PREG
($5) && $4.r0
== 0)
1141 notethat
("COMP3op: pregs = pregs + pregs\n");
1142 $$
= COMP3OP
(&$1, &$3, &$5, 5);
1145 return
yyerror ("Dregs expected");
1147 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1151 if
(IS_DREG
($1) && IS_DREG
($5) && IS_DREG
($7))
1158 notethat
("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1159 $$
= DSP32ALU
(op
, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0
);
1162 return
yyerror ("Dregs expected");
1165 | a_assign MINUS REG_A
1167 notethat
("dsp32alu: Ax = - Ax\n");
1168 $$
= DSP32ALU
(14, IS_A1
($1), 0, 0, ®7
, ®7
, 0, 0, IS_A1
($3));
1170 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1172 notethat
("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1173 $$
= DSP32ALU
(2 |
$4.r0
, IS_H
($1), 0, &$1, &$3, &$5,
1174 $6.s0
, $6.x0
, HL2
($3, $5));
1176 | a_assign a_assign expr
1178 if
(EXPR_VALUE
($3) == 0 && !REG_SAME
($1, $2))
1180 notethat
("dsp32alu: A1 = A0 = 0\n");
1181 $$
= DSP32ALU
(8, 0, 0, 0, ®7
, ®7
, 0, 0, 2);
1184 return
yyerror ("Bad value, 0 expected");
1188 | a_assign REG_A LPAREN S RPAREN
1190 if
(REG_SAME
($1, $2))
1192 notethat
("dsp32alu: Ax = Ax (S)\n");
1193 $$
= DSP32ALU
(8, 0, 0, 0, ®7
, ®7
, 1, 0, IS_A1
($1));
1196 return
yyerror ("Registers must be equal");
1199 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1203 notethat
("dsp32alu: dregs_half = dregs (RND)\n");
1204 $$
= DSP32ALU
(12, IS_H
($1), 0, &$1, &$3, 0, 0, 0, 3);
1207 return
yyerror ("Dregs expected");
1210 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1212 if
(IS_DREG
($3) && IS_DREG
($5))
1214 notethat
("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1215 $$
= DSP32ALU
(5, IS_H
($1), 0, &$1, &$3, &$5, 0, 0, $4.r0
);
1218 return
yyerror ("Dregs expected");
1221 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1223 if
(IS_DREG
($3) && IS_DREG
($5))
1225 notethat
("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1226 $$
= DSP32ALU
(5, IS_H
($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 |
2);
1229 return
yyerror ("Dregs expected");
1234 if
(!REG_SAME
($1, $2))
1236 notethat
("dsp32alu: An = Am\n");
1237 $$
= DSP32ALU
(8, 0, 0, 0, ®7
, ®7
, IS_A1
($1), 0, 3);
1240 return
yyerror ("Accu reg arguments must differ");
1247 notethat
("dsp32alu: An = dregs\n");
1248 $$
= DSP32ALU
(9, 0, 0, 0, &$2, 0, 1, 0, IS_A1
($1) << 1);
1251 return
yyerror ("Dregs expected");
1254 | REG ASSIGN HALF_REG xpmod
1258 if
($1.regno
== REG_A0x
&& IS_DREG
($3))
1260 notethat
("dsp32alu: A0.x = dregs_lo\n");
1261 $$
= DSP32ALU
(9, 0, 0, 0, &$3, 0, 0, 0, 1);
1263 else if
($1.regno
== REG_A1x
&& IS_DREG
($3))
1265 notethat
("dsp32alu: A1.x = dregs_lo\n");
1266 $$
= DSP32ALU
(9, 0, 0, 0, &$3, 0, 0, 0, 3);
1268 else if
(IS_DREG
($1) && IS_DREG
($3))
1270 notethat
("ALU2op: dregs = dregs_lo\n");
1271 $$
= ALU2OP
(&$1, &$3, 10 |
($4.r0 ?
0: 1));
1274 return
yyerror ("Register mismatch");
1277 return
yyerror ("Low reg expected");
1280 | HALF_REG ASSIGN expr
1282 notethat
("LDIMMhalf: pregs_half = imm16\n");
1284 if
(!IS_DREG
($1) && !IS_PREG
($1) && !IS_IREG
($1)
1285 && !IS_MREG
($1) && !IS_BREG
($1) && !IS_LREG
($1))
1286 return
yyerror ("Wrong register for load immediate");
1288 if
(!IS_IMM
($3, 16) && !IS_UIMM
($3, 16))
1289 return
yyerror ("Constant out of range");
1291 $$
= LDIMMHALF_R
(&$1, IS_H
($1), 0, 0, $3);
1296 notethat
("dsp32alu: An = 0\n");
1299 return
yyerror ("0 expected");
1301 $$
= DSP32ALU
(8, 0, 0, 0, 0, 0, 0, 0, IS_A1
($1));
1304 | REG ASSIGN expr xpmod1
1306 if
(!IS_DREG
($1) && !IS_PREG
($1) && !IS_IREG
($1)
1307 && !IS_MREG
($1) && !IS_BREG
($1) && !IS_LREG
($1))
1308 return
yyerror ("Wrong register for load immediate");
1312 /* 7 bit immediate value if possible.
1313 We will check for that constant value for efficiency
1314 If it goes to reloc, it will be 16 bit. */
1315 if
(IS_CONST
($3) && IS_IMM
($3, 7) && IS_DREG
($1))
1317 notethat
("COMPI2opD: dregs = imm7 (x) \n");
1318 $$
= COMPI2OPD
(&$1, imm7
($3), 0);
1320 else if
(IS_CONST
($3) && IS_IMM
($3, 7) && IS_PREG
($1))
1322 notethat
("COMPI2opP: pregs = imm7 (x)\n");
1323 $$
= COMPI2OPP
(&$1, imm7
($3), 0);
1327 if
(IS_CONST
($3) && !IS_IMM
($3, 16))
1328 return
yyerror ("Immediate value out of range");
1330 notethat
("LDIMMhalf: regs = luimm16 (x)\n");
1332 $$
= LDIMMHALF_R5
(&$1, 0, 1, 0, $3);
1337 /* (z) There is no 7 bit zero extended instruction.
1338 If the expr is a relocation, generate it. */
1340 if
(IS_CONST
($3) && !IS_UIMM
($3, 16))
1341 return
yyerror ("Immediate value out of range");
1343 notethat
("LDIMMhalf: regs = luimm16 (x)\n");
1345 $$
= LDIMMHALF_R5
(&$1, 0, 0, 1, $3);
1349 | HALF_REG ASSIGN REG
1352 return
yyerror ("Low reg expected");
1354 if
(IS_DREG
($1) && $3.regno
== REG_A0x
)
1356 notethat
("dsp32alu: dregs_lo = A0.x\n");
1357 $$
= DSP32ALU
(10, 0, 0, &$1, ®7
, ®7
, 0, 0, 0);
1359 else if
(IS_DREG
($1) && $3.regno
== REG_A1x
)
1361 notethat
("dsp32alu: dregs_lo = A1.x\n");
1362 $$
= DSP32ALU
(10, 0, 0, &$1, ®7
, ®7
, 0, 0, 1);
1365 return
yyerror ("Register mismatch");
1368 | REG ASSIGN REG op_bar_op REG amod0
1370 if
(IS_DREG
($1) && IS_DREG
($3) && IS_DREG
($5))
1372 notethat
("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1373 $$
= DSP32ALU
(0, 0, 0, &$1, &$3, &$5, $6.s0
, $6.x0
, $4.r0
);
1376 return
yyerror ("Register mismatch");
1379 | REG ASSIGN BYTE_DREG xpmod
1381 if
(IS_DREG
($1) && IS_DREG
($3))
1383 notethat
("ALU2op: dregs = dregs_byte\n");
1384 $$
= ALU2OP
(&$1, &$3, 12 |
($4.r0 ?
0: 1));
1387 return
yyerror ("Register mismatch");
1390 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1392 if
(REG_SAME
($1, $3) && REG_SAME
($5, $7) && !REG_SAME
($1, $5))
1394 notethat
("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1395 $$
= DSP32ALU
(16, 0, 0, 0, ®7
, ®7
, 0, 0, 3);
1398 return
yyerror ("Register mismatch");
1401 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1403 if
(REG_SAME
($1, $3) && REG_SAME
($5, $7) && !REG_SAME
($1, $5))
1405 notethat
("dsp32alu: A1 = - A1 , A0 = - A0\n");
1406 $$
= DSP32ALU
(14, 0, 0, 0, ®7
, ®7
, 0, 0, 3);
1409 return
yyerror ("Register mismatch");
1412 | a_minusassign REG_A w32_or_nothing
1414 if
(!IS_A1
($1) && IS_A1
($2))
1416 notethat
("dsp32alu: A0 -= A1\n");
1417 $$
= DSP32ALU
(11, 0, 0, 0, ®7
, ®7
, $3.r0
, 0, 3);
1420 return
yyerror ("Register mismatch");
1423 | REG _MINUS_ASSIGN expr
1425 if
(IS_IREG
($1) && EXPR_VALUE
($3) == 4)
1427 notethat
("dagMODik: iregs -= 4\n");
1428 $$
= DAGMODIK
(&$1, 3);
1430 else if
(IS_IREG
($1) && EXPR_VALUE
($3) == 2)
1432 notethat
("dagMODik: iregs -= 2\n");
1433 $$
= DAGMODIK
(&$1, 1);
1436 return
yyerror ("Register or value mismatch");
1439 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1441 if
(IS_IREG
($1) && IS_MREG
($3))
1443 notethat
("dagMODim: iregs += mregs (opt_brev)\n");
1445 $$
= DAGMODIM
(&$1, &$3, 0, 1);
1447 else if
(IS_PREG
($1) && IS_PREG
($3))
1449 notethat
("PTR2op: pregs += pregs (BREV )\n");
1450 $$
= PTR2OP
(&$1, &$3, 5);
1453 return
yyerror ("Register mismatch");
1456 | REG _MINUS_ASSIGN REG
1458 if
(IS_IREG
($1) && IS_MREG
($3))
1460 notethat
("dagMODim: iregs -= mregs\n");
1461 $$
= DAGMODIM
(&$1, &$3, 1, 0);
1463 else if
(IS_PREG
($1) && IS_PREG
($3))
1465 notethat
("PTR2op: pregs -= pregs\n");
1466 $$
= PTR2OP
(&$1, &$3, 0);
1469 return
yyerror ("Register mismatch");
1472 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1474 if
(!IS_A1
($1) && IS_A1
($3))
1476 notethat
("dsp32alu: A0 += A1 (W32)\n");
1477 $$
= DSP32ALU
(11, 0, 0, 0, ®7
, ®7
, $4.r0
, 0, 2);
1480 return
yyerror ("Register mismatch");
1483 | REG _PLUS_ASSIGN REG
1485 if
(IS_IREG
($1) && IS_MREG
($3))
1487 notethat
("dagMODim: iregs += mregs\n");
1488 $$
= DAGMODIM
(&$1, &$3, 0, 0);
1491 return
yyerror ("iregs += mregs expected");
1494 | REG _PLUS_ASSIGN expr
1498 if
(EXPR_VALUE
($3) == 4)
1500 notethat
("dagMODik: iregs += 4\n");
1501 $$
= DAGMODIK
(&$1, 2);
1503 else if
(EXPR_VALUE
($3) == 2)
1505 notethat
("dagMODik: iregs += 2\n");
1506 $$
= DAGMODIK
(&$1, 0);
1509 return
yyerror ("iregs += [ 2 | 4 ");
1511 else if
(IS_PREG
($1) && IS_IMM
($3, 7))
1513 notethat
("COMPI2opP: pregs += imm7\n");
1514 $$
= COMPI2OPP
(&$1, imm7
($3), 1);
1516 else if
(IS_DREG
($1) && IS_IMM
($3, 7))
1518 notethat
("COMPI2opD: dregs += imm7\n");
1519 $$
= COMPI2OPD
(&$1, imm7
($3), 1);
1521 else if
((IS_DREG
($1) || IS_PREG
($1)) && IS_CONST
($3))
1522 return
yyerror ("Immediate value out of range");
1524 return
yyerror ("Register mismatch");
1527 | REG _STAR_ASSIGN REG
1529 if
(IS_DREG
($1) && IS_DREG
($3))
1531 notethat
("ALU2op: dregs *= dregs\n");
1532 $$
= ALU2OP
(&$1, &$3, 3);
1535 return
yyerror ("Register mismatch");
1538 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1540 if
(!valid_dreg_pair
(&$3, $5))
1541 return
yyerror ("Bad dreg pair");
1542 else if
(!valid_dreg_pair
(&$7, $9))
1543 return
yyerror ("Bad dreg pair");
1546 notethat
("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1547 $$
= DSP32ALU
(18, 0, 0, 0, &$3, &$7, $11.r0
, 0, 0);
1551 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1553 if
(REG_SAME
($1, $2) && REG_SAME
($7, $8) && !REG_SAME
($1, $7))
1555 notethat
("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1556 $$
= DSP32ALU
(8, 0, 0, 0, ®7
, ®7
, 1, 0, 2);
1559 return
yyerror ("Register mismatch");
1562 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1564 if
(IS_DREG
($1) && IS_DREG
($4) && IS_DREG
($6)
1565 && REG_SAME
($1, $4))
1567 if
(EXPR_VALUE
($9) == 1)
1569 notethat
("ALU2op: dregs = (dregs + dregs) << 1\n");
1570 $$
= ALU2OP
(&$1, &$6, 4);
1572 else if
(EXPR_VALUE
($9) == 2)
1574 notethat
("ALU2op: dregs = (dregs + dregs) << 2\n");
1575 $$
= ALU2OP
(&$1, &$6, 5);
1578 return
yyerror ("Bad shift value");
1580 else if
(IS_PREG
($1) && IS_PREG
($4) && IS_PREG
($6)
1581 && REG_SAME
($1, $4))
1583 if
(EXPR_VALUE
($9) == 1)
1585 notethat
("PTR2op: pregs = (pregs + pregs) << 1\n");
1586 $$
= PTR2OP
(&$1, &$6, 6);
1588 else if
(EXPR_VALUE
($9) == 2)
1590 notethat
("PTR2op: pregs = (pregs + pregs) << 2\n");
1591 $$
= PTR2OP
(&$1, &$6, 7);
1594 return
yyerror ("Bad shift value");
1597 return
yyerror ("Register mismatch");
1601 | REG ASSIGN REG BAR REG
1603 if
(IS_DREG
($1) && IS_DREG
($3) && IS_DREG
($5))
1605 notethat
("COMP3op: dregs = dregs | dregs\n");
1606 $$
= COMP3OP
(&$1, &$3, &$5, 3);
1609 return
yyerror ("Dregs expected");
1611 | REG ASSIGN REG CARET REG
1613 if
(IS_DREG
($1) && IS_DREG
($3) && IS_DREG
($5))
1615 notethat
("COMP3op: dregs = dregs ^ dregs\n");
1616 $$
= COMP3OP
(&$1, &$3, &$5, 4);
1619 return
yyerror ("Dregs expected");
1621 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1623 if
(IS_PREG
($1) && IS_PREG
($3) && IS_PREG
($6))
1625 if
(EXPR_VALUE
($8) == 1)
1627 notethat
("COMP3op: pregs = pregs + (pregs << 1)\n");
1628 $$
= COMP3OP
(&$1, &$3, &$6, 6);
1630 else if
(EXPR_VALUE
($8) == 2)
1632 notethat
("COMP3op: pregs = pregs + (pregs << 2)\n");
1633 $$
= COMP3OP
(&$1, &$3, &$6, 7);
1636 return
yyerror ("Bad shift value");
1639 return
yyerror ("Dregs expected");
1641 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1643 if
($3.regno
== REG_A0
&& $5.regno
== REG_A1
)
1645 notethat
("CCflag: CC = A0 == A1\n");
1646 $$
= CCFLAG
(0, 0, 5, 0, 0);
1649 return
yyerror ("AREGs are in bad order or same");
1651 | CCREG ASSIGN REG_A LESS_THAN REG_A
1653 if
($3.regno
== REG_A0
&& $5.regno
== REG_A1
)
1655 notethat
("CCflag: CC = A0 < A1\n");
1656 $$
= CCFLAG
(0, 0, 6, 0, 0);
1659 return
yyerror ("AREGs are in bad order or same");
1661 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1663 if
((IS_DREG
($3) && IS_DREG
($5))
1664 ||
(IS_PREG
($3) && IS_PREG
($5)))
1666 notethat
("CCflag: CC = dpregs < dpregs\n");
1667 $$
= CCFLAG
(&$3, $5.regno
& CODE_MASK
, $6.r0
, 0, IS_PREG
($3) ?
1 : 0);
1670 return
yyerror ("Bad register in comparison");
1672 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1674 if
(!IS_DREG
($3) && !IS_PREG
($3))
1675 return
yyerror ("Bad register in comparison");
1677 if
(($6.r0
== 1 && IS_IMM
($5, 3))
1678 ||
($6.r0
== 3 && IS_UIMM
($5, 3)))
1680 notethat
("CCflag: CC = dpregs < (u)imm3\n");
1681 $$
= CCFLAG
(&$3, imm3
($5), $6.r0
, 1, IS_PREG
($3) ?
1 : 0);
1684 return
yyerror ("Bad constant value");
1686 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1688 if
((IS_DREG
($3) && IS_DREG
($5))
1689 ||
(IS_PREG
($3) && IS_PREG
($5)))
1691 notethat
("CCflag: CC = dpregs == dpregs\n");
1692 $$
= CCFLAG
(&$3, $5.regno
& CODE_MASK
, 0, 0, IS_PREG
($3) ?
1 : 0);
1695 return
yyerror ("Bad register in comparison");
1697 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1699 if
(!IS_DREG
($3) && !IS_PREG
($3))
1700 return
yyerror ("Bad register in comparison");
1704 notethat
("CCflag: CC = dpregs == imm3\n");
1705 $$
= CCFLAG
(&$3, imm3
($5), 0, 1, IS_PREG
($3) ?
1 : 0);
1708 return
yyerror ("Bad constant range");
1710 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1712 if
($3.regno
== REG_A0
&& $5.regno
== REG_A1
)
1714 notethat
("CCflag: CC = A0 <= A1\n");
1715 $$
= CCFLAG
(0, 0, 7, 0, 0);
1718 return
yyerror ("AREGs are in bad order or same");
1720 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1722 if
((IS_DREG
($3) && IS_DREG
($5))
1723 ||
(IS_PREG
($3) && IS_PREG
($5)))
1725 notethat
("CCflag: CC = dpregs <= dpregs (..)\n");
1726 $$
= CCFLAG
(&$3, $5.regno
& CODE_MASK
,
1727 1 + $6.r0
, 0, IS_PREG
($3) ?
1 : 0);
1730 return
yyerror ("Bad register in comparison");
1732 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1734 if
(!IS_DREG
($3) && !IS_PREG
($3))
1735 return
yyerror ("Bad register in comparison");
1737 if
(($6.r0
== 1 && IS_IMM
($5, 3))
1738 ||
($6.r0
== 3 && IS_UIMM
($5, 3)))
1740 notethat
("CCflag: CC = dpregs <= (u)imm3\n");
1741 $$
= CCFLAG
(&$3, imm3
($5), 1 + $6.r0
, 1, IS_PREG
($3) ?
1 : 0);
1744 return
yyerror ("Bad constant value");
1747 | REG ASSIGN REG AMPERSAND REG
1749 if
(IS_DREG
($1) && IS_DREG
($3) && IS_DREG
($5))
1751 notethat
("COMP3op: dregs = dregs & dregs\n");
1752 $$
= COMP3OP
(&$1, &$3, &$5, 2);
1755 return
yyerror ("Dregs expected");
1760 notethat
("CC2stat operation\n");
1761 $$
= bfin_gen_cc2stat
($1.r0
, $1.x0
, $1.s0
);
1766 if
((IS_GENREG
($1) && IS_GENREG
($3))
1767 ||
(IS_GENREG
($1) && IS_DAGREG
($3))
1768 ||
(IS_DAGREG
($1) && IS_GENREG
($3))
1769 ||
(IS_DAGREG
($1) && IS_DAGREG
($3))
1770 ||
(IS_GENREG
($1) && $3.regno
== REG_USP
)
1771 ||
($1.regno
== REG_USP
&& IS_GENREG
($3))
1772 ||
($1.regno
== REG_USP
&& $3.regno
== REG_USP
)
1773 ||
(IS_DREG
($1) && IS_SYSREG
($3))
1774 ||
(IS_PREG
($1) && IS_SYSREG
($3))
1775 ||
(IS_SYSREG
($1) && IS_GENREG
($3))
1776 ||
(IS_ALLREG
($1) && IS_EMUDAT
($3))
1777 ||
(IS_EMUDAT
($1) && IS_ALLREG
($3))
1778 ||
(IS_SYSREG
($1) && $3.regno
== REG_USP
))
1780 $$
= bfin_gen_regmv
(&$3, &$1);
1783 return
yyerror ("Unsupported register move");
1790 notethat
("CC2dreg: CC = dregs\n");
1791 $$
= bfin_gen_cc2dreg
(1, &$3);
1794 return
yyerror ("Only 'CC = Dreg' supported");
1801 notethat
("CC2dreg: dregs = CC\n");
1802 $$
= bfin_gen_cc2dreg
(0, &$1);
1805 return
yyerror ("Only 'Dreg = CC' supported");
1808 | CCREG _ASSIGN_BANG CCREG
1810 notethat
("CC2dreg: CC =! CC\n");
1811 $$
= bfin_gen_cc2dreg
(3, 0);
1816 | HALF_REG ASSIGN multiply_halfregs opt_mode
1818 notethat
("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1820 if
(!IS_H
($1) && $4.MM
)
1821 return
yyerror ("(M) not allowed with MAC0");
1823 if
($4.mod
!= 0 && $4.mod
!= M_FU
&& $4.mod
!= M_IS
1824 && $4.mod
!= M_IU
&& $4.mod
!= M_T
&& $4.mod
!= M_TFU
1825 && $4.mod
!= M_S2RND
&& $4.mod
!= M_ISS2
&& $4.mod
!= M_IH
)
1826 return
yyerror ("bad option.");
1830 $$
= DSP32MULT
(0, $4.MM
, $4.mod
, 1, 0,
1831 IS_H
($3.s0
), IS_H
($3.s1
), 0, 0,
1832 &$1, 0, &$3.s0
, &$3.s1
, 0);
1836 $$
= DSP32MULT
(0, 0, $4.mod
, 0, 0,
1837 0, 0, IS_H
($3.s0
), IS_H
($3.s1
),
1838 &$1, 0, &$3.s0
, &$3.s1
, 1);
1842 | REG ASSIGN multiply_halfregs opt_mode
1844 /* Odd registers can use (M). */
1846 return
yyerror ("Dreg expected");
1848 if
(IS_EVEN
($1) && $4.MM
)
1849 return
yyerror ("(M) not allowed with MAC0");
1851 if
($4.mod
!= 0 && $4.mod
!= M_FU
&& $4.mod
!= M_IS
1852 && $4.mod
!= M_S2RND
&& $4.mod
!= M_ISS2
)
1853 return
yyerror ("bad option");
1857 notethat
("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1859 $$
= DSP32MULT
(0, $4.MM
, $4.mod
, 1, 1,
1860 IS_H
($3.s0
), IS_H
($3.s1
), 0, 0,
1861 &$1, 0, &$3.s0
, &$3.s1
, 0);
1865 notethat
("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1866 $$
= DSP32MULT
(0, 0, $4.mod
, 0, 1,
1867 0, 0, IS_H
($3.s0
), IS_H
($3.s1
),
1868 &$1, 0, &$3.s0
, &$3.s1
, 1);
1872 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1873 HALF_REG ASSIGN multiply_halfregs opt_mode
1875 if
(!IS_DREG
($1) ||
!IS_DREG
($6))
1876 return
yyerror ("Dregs expected");
1878 if
(!IS_HCOMPL
($1, $6))
1879 return
yyerror ("Dest registers mismatch");
1881 if
(check_multiply_halfregs
(&$3, &$8) < 0)
1884 if
((!IS_H
($1) && $4.MM
)
1885 ||
(!IS_H
($6) && $9.MM
))
1886 return
yyerror ("(M) not allowed with MAC0");
1888 notethat
("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1889 "dregs_lo = multiply_halfregs opt_mode\n");
1892 $$
= DSP32MULT
(0, $4.MM
, $9.mod
, 1, 0,
1893 IS_H
($3.s0
), IS_H
($3.s1
), IS_H
($8.s0
), IS_H
($8.s1
),
1894 &$1, 0, &$3.s0
, &$3.s1
, 1);
1896 $$
= DSP32MULT
(0, $9.MM
, $9.mod
, 1, 0,
1897 IS_H
($8.s0
), IS_H
($8.s1
), IS_H
($3.s0
), IS_H
($3.s1
),
1898 &$1, 0, &$3.s0
, &$3.s1
, 1);
1901 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1903 if
(!IS_DREG
($1) ||
!IS_DREG
($6))
1904 return
yyerror ("Dregs expected");
1906 if
((IS_EVEN
($1) && $6.regno
- $1.regno
!= 1)
1907 ||
(IS_EVEN
($6) && $1.regno
- $6.regno
!= 1))
1908 return
yyerror ("Dest registers mismatch");
1910 if
(check_multiply_halfregs
(&$3, &$8) < 0)
1913 if
((IS_EVEN
($1) && $4.MM
)
1914 ||
(IS_EVEN
($6) && $9.MM
))
1915 return
yyerror ("(M) not allowed with MAC0");
1917 notethat
("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1918 "dregs = multiply_halfregs opt_mode\n");
1921 $$
= DSP32MULT
(0, $9.MM
, $9.mod
, 1, 1,
1922 IS_H
($8.s0
), IS_H
($8.s1
), IS_H
($3.s0
), IS_H
($3.s1
),
1923 &$1, 0, &$3.s0
, &$3.s1
, 1);
1925 $$
= DSP32MULT
(0, $4.MM
, $9.mod
, 1, 1,
1926 IS_H
($3.s0
), IS_H
($3.s1
), IS_H
($8.s0
), IS_H
($8.s1
),
1927 &$1, 0, &$3.s0
, &$3.s1
, 1);
1932 | a_assign ASHIFT REG_A BY HALF_REG
1934 if
(!REG_SAME
($1, $3))
1935 return
yyerror ("Aregs must be same");
1937 if
(IS_DREG
($5) && !IS_H
($5))
1939 notethat
("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1940 $$
= DSP32SHIFT
(3, 0, &$5, 0, 0, IS_A1
($1));
1943 return
yyerror ("Dregs expected");
1946 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1948 if
(IS_DREG
($6) && !IS_H
($6))
1950 notethat
("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1951 $$
= DSP32SHIFT
(0, &$1, &$6, &$4, $7.s0
, HL2
($1, $4));
1954 return
yyerror ("Dregs expected");
1957 | a_assign REG_A LESS_LESS expr
1959 if
(!REG_SAME
($1, $2))
1960 return
yyerror ("Aregs must be same");
1962 if
(IS_UIMM
($4, 5))
1964 notethat
("dsp32shiftimm: A0 = A0 << uimm5\n");
1965 $$
= DSP32SHIFTIMM
(3, 0, imm5
($4), 0, 0, IS_A1
($1));
1968 return
yyerror ("Bad shift value");
1971 | REG ASSIGN REG LESS_LESS expr vsmod
1973 if
(IS_DREG
($1) && IS_DREG
($3) && IS_UIMM
($5, 5))
1978 notethat
("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1979 $$
= DSP32SHIFTIMM
(1, &$1, imm4
($5), &$3, $6.s0 ?
1 : 2, 0);
1983 notethat
("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1984 $$
= DSP32SHIFTIMM
(2, &$1, imm6
($5), &$3, $6.s0 ?
1 : 2, 0);
1987 else if
($6.s0
== 0 && IS_PREG
($1) && IS_PREG
($3))
1989 if
(EXPR_VALUE
($5) == 2)
1991 notethat
("PTR2op: pregs = pregs << 2\n");
1992 $$
= PTR2OP
(&$1, &$3, 1);
1994 else if
(EXPR_VALUE
($5) == 1)
1996 notethat
("COMP3op: pregs = pregs << 1\n");
1997 $$
= COMP3OP
(&$1, &$3, &$3, 5);
2000 return
yyerror ("Bad shift value");
2003 return
yyerror ("Bad shift value or register");
2005 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
2007 if
(IS_UIMM
($5, 4))
2011 notethat
("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
2012 $$
= DSP32SHIFTIMM
(0x0, &$1, imm5
($5), &$3, $6.s0
, HL2
($1, $3));
2016 notethat
("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
2017 $$
= DSP32SHIFTIMM
(0x0, &$1, imm5
($5), &$3, 2, HL2
($1, $3));
2021 return
yyerror ("Bad shift value");
2023 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
2027 if
(IS_DREG
($1) && IS_DREG
($4) && IS_DREG
($6) && !IS_H
($6))
2032 notethat
("dsp32shift: dregs = ASHIFT dregs BY "
2033 "dregs_lo (V, .)\n");
2039 notethat
("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
2041 $$
= DSP32SHIFT
(op
, &$1, &$6, &$4, $7.s0
, 0);
2044 return
yyerror ("Dregs expected");
2048 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2050 if
(IS_DREG_L
($1) && IS_DREG_L
($5) && IS_DREG_L
($7))
2052 notethat
("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2053 $$
= DSP32SHIFT
(7, &$1, &$7, &$5, $9.r0
, 0);
2056 return
yyerror ("Bad shift value or register");
2060 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2062 if
(IS_DREG_L
($1) && IS_DREG_L
($5) && IS_DREG_L
($7))
2064 notethat
("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2065 $$
= DSP32SHIFT
(7, &$1, &$7, &$5, 2, 0);
2067 else if
(IS_DREG_L
($1) && IS_DREG_H
($5) && IS_DREG_L
($7))
2069 notethat
("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2070 $$
= DSP32SHIFT
(7, &$1, &$7, &$5, 3, 0);
2073 return
yyerror ("Bad shift value or register");
2078 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2080 if
(IS_DREG
($1) && IS_DREG
($5) && IS_DREG
($7))
2082 notethat
("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2083 $$
= DSP32SHIFT
(10, &$1, &$7, &$5, 2, 0);
2086 return
yyerror ("Register mismatch");
2089 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2091 if
(IS_DREG
($1) && IS_DREG
($5) && IS_DREG
($7))
2093 notethat
("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2094 $$
= DSP32SHIFT
(10, &$1, &$7, &$5, 3, 0);
2097 return
yyerror ("Register mismatch");
2100 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2102 if
(IS_DREG
($1) && IS_DREG
($5) && IS_DREG_L
($7))
2104 notethat
("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2105 $$
= DSP32SHIFT
(10, &$1, &$7, &$5, $9.r0
, 0);
2108 return
yyerror ("Register mismatch");
2111 | a_assign REG_A _GREATER_GREATER_GREATER expr
2113 if
(!REG_SAME
($1, $2))
2114 return
yyerror ("Aregs must be same");
2116 if
(IS_UIMM
($4, 5))
2118 notethat
("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2119 $$
= DSP32SHIFTIMM
(3, 0, -imm6
($4), 0, 0, IS_A1
($1));
2122 return
yyerror ("Shift value range error");
2124 | a_assign LSHIFT REG_A BY HALF_REG
2126 if
(REG_SAME
($1, $3) && IS_DREG_L
($5))
2128 notethat
("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2129 $$
= DSP32SHIFT
(3, 0, &$5, 0, 1, IS_A1
($1));
2132 return
yyerror ("Register mismatch");
2135 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2137 if
(IS_DREG
($1) && IS_DREG
($4) && IS_DREG_L
($6))
2139 notethat
("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2140 $$
= DSP32SHIFT
(0, &$1, &$6, &$4, 2, HL2
($1, $4));
2143 return
yyerror ("Register mismatch");
2146 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2148 if
(IS_DREG
($1) && IS_DREG
($4) && IS_DREG_L
($6))
2150 notethat
("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2151 $$
= DSP32SHIFT
($7.r0 ?
1: 2, &$1, &$6, &$4, 2, 0);
2154 return
yyerror ("Register mismatch");
2157 | REG ASSIGN SHIFT REG BY HALF_REG
2159 if
(IS_DREG
($1) && IS_DREG
($4) && IS_DREG_L
($6))
2161 notethat
("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2162 $$
= DSP32SHIFT
(2, &$1, &$6, &$4, 2, 0);
2165 return
yyerror ("Register mismatch");
2168 | a_assign REG_A GREATER_GREATER expr
2170 if
(REG_SAME
($1, $2) && IS_IMM
($4, 6) >= 0)
2172 notethat
("dsp32shiftimm: Ax = Ax >> imm6\n");
2173 $$
= DSP32SHIFTIMM
(3, 0, -imm6
($4), 0, 1, IS_A1
($1));
2176 return
yyerror ("Accu register expected");
2179 | REG ASSIGN REG GREATER_GREATER expr vmod
2183 if
(IS_DREG
($1) && IS_DREG
($3) && IS_UIMM
($5, 5))
2185 notethat
("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2186 $$
= DSP32SHIFTIMM
(1, &$1, -uimm5
($5), &$3, 2, 0);
2189 return
yyerror ("Register mismatch");
2193 if
(IS_DREG
($1) && IS_DREG
($3) && IS_UIMM
($5, 5))
2195 notethat
("dsp32shiftimm: dregs = dregs >> uimm5\n");
2196 $$
= DSP32SHIFTIMM
(2, &$1, -imm6
($5), &$3, 2, 0);
2198 else if
(IS_PREG
($1) && IS_PREG
($3) && EXPR_VALUE
($5) == 2)
2200 notethat
("PTR2op: pregs = pregs >> 2\n");
2201 $$
= PTR2OP
(&$1, &$3, 3);
2203 else if
(IS_PREG
($1) && IS_PREG
($3) && EXPR_VALUE
($5) == 1)
2205 notethat
("PTR2op: pregs = pregs >> 1\n");
2206 $$
= PTR2OP
(&$1, &$3, 4);
2209 return
yyerror ("Register mismatch");
2212 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2214 if
(IS_UIMM
($5, 5))
2216 notethat
("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2217 $$
= DSP32SHIFTIMM
(0, &$1, -uimm5
($5), &$3, 2, HL2
($1, $3));
2220 return
yyerror ("Register mismatch");
2222 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2224 if
(IS_UIMM
($5, 5))
2226 notethat
("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2227 $$
= DSP32SHIFTIMM
(0, &$1, -uimm5
($5), &$3,
2228 $6.s0
, HL2
($1, $3));
2231 return
yyerror ("Register or modifier mismatch");
2235 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2237 if
(IS_DREG
($1) && IS_DREG
($3) && IS_UIMM
($5, 5))
2242 notethat
("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2243 $$
= DSP32SHIFTIMM
(1, &$1, -uimm5
($5), &$3, $6.s0
, 0);
2247 notethat
("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2248 $$
= DSP32SHIFTIMM
(2, &$1, -uimm5
($5), &$3, $6.s0
, 0);
2252 return
yyerror ("Register mismatch");
2255 | HALF_REG ASSIGN ONES REG
2257 if
(IS_DREG_L
($1) && IS_DREG
($4))
2259 notethat
("dsp32shift: dregs_lo = ONES dregs\n");
2260 $$
= DSP32SHIFT
(6, &$1, 0, &$4, 3, 0);
2263 return
yyerror ("Register mismatch");
2266 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2268 if
(IS_DREG
($1) && IS_DREG
($5) && IS_DREG
($7))
2270 notethat
("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2271 $$
= DSP32SHIFT
(4, &$1, &$7, &$5, HL2
($5, $7), 0);
2274 return
yyerror ("Register mismatch");
2277 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2280 && $7.regno
== REG_A0
2281 && IS_DREG
($9) && !IS_H
($1) && !IS_A1
($7))
2283 notethat
("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2284 $$
= DSP32SHIFT
(11, &$1, &$9, 0, 0, 0);
2287 return
yyerror ("Register mismatch");
2290 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2293 && $7.regno
== REG_A0
2294 && IS_DREG
($9) && !IS_H
($1) && !IS_A1
($7))
2296 notethat
("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2297 $$
= DSP32SHIFT
(11, &$1, &$9, 0, 1, 0);
2300 return
yyerror ("Register mismatch");
2303 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2305 if
(IS_DREG
($1) && !IS_H
($1) && !REG_SAME
($7, $9))
2307 notethat
("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2308 $$
= DSP32SHIFT
(12, &$1, 0, 0, 1, 0);
2311 return
yyerror ("Register mismatch");
2314 | a_assign ROT REG_A BY HALF_REG
2316 if
(REG_SAME
($1, $3) && IS_DREG_L
($5))
2318 notethat
("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2319 $$
= DSP32SHIFT
(3, 0, &$5, 0, 2, IS_A1
($1));
2322 return
yyerror ("Register mismatch");
2325 | REG ASSIGN ROT REG BY HALF_REG
2327 if
(IS_DREG
($1) && IS_DREG
($4) && IS_DREG_L
($6))
2329 notethat
("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2330 $$
= DSP32SHIFT
(2, &$1, &$6, &$4, 3, 0);
2333 return
yyerror ("Register mismatch");
2336 | a_assign ROT REG_A BY expr
2340 notethat
("dsp32shiftimm: An = ROT An BY imm6\n");
2341 $$
= DSP32SHIFTIMM
(3, 0, imm6
($5), 0, 2, IS_A1
($1));
2344 return
yyerror ("Register mismatch");
2347 | REG ASSIGN ROT REG BY expr
2349 if
(IS_DREG
($1) && IS_DREG
($4) && IS_IMM
($6, 6))
2351 $$
= DSP32SHIFTIMM
(2, &$1, imm6
($6), &$4, 3, IS_A1
($1));
2354 return
yyerror ("Register mismatch");
2357 | HALF_REG ASSIGN SIGNBITS REG_A
2361 notethat
("dsp32shift: dregs_lo = SIGNBITS An\n");
2362 $$
= DSP32SHIFT
(6, &$1, 0, 0, IS_A1
($4), 0);
2365 return
yyerror ("Register mismatch");
2368 | HALF_REG ASSIGN SIGNBITS REG
2370 if
(IS_DREG_L
($1) && IS_DREG
($4))
2372 notethat
("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2373 $$
= DSP32SHIFT
(5, &$1, 0, &$4, 0, 0);
2376 return
yyerror ("Register mismatch");
2379 | HALF_REG ASSIGN SIGNBITS HALF_REG
2383 notethat
("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2384 $$
= DSP32SHIFT
(5, &$1, 0, &$4, 1 + IS_H
($4), 0);
2387 return
yyerror ("Register mismatch");
2390 /* The ASR bit is just inverted here. */
2391 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2393 if
(IS_DREG_L
($1) && IS_DREG
($5))
2395 notethat
("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2396 $$
= DSP32SHIFT
(9, &$1, 0, &$5, ($7.r0 ?
0 : 1), 0);
2399 return
yyerror ("Register mismatch");
2402 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2404 if
(IS_DREG
($1) && IS_DREG
($5) && IS_DREG
($7))
2406 notethat
("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2407 $$
= DSP32SHIFT
(9, &$1, &$7, &$5, 2 |
($9.r0 ?
0 : 1), 0);
2410 return
yyerror ("Register mismatch");
2413 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2415 if
(REG_SAME
($3, $5))
2416 return
yyerror ("Illegal source register combination");
2418 if
(IS_DREG
($3) && IS_DREG
($5) && !IS_A1
($7))
2420 notethat
("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2421 $$
= DSP32SHIFT
(8, 0, &$3, &$5, $9.r0
, 0);
2424 return
yyerror ("Register mismatch");
2427 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2429 if
(!IS_A1
($1) && !IS_A1
($4) && IS_A1
($6))
2431 notethat
("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2432 $$
= DSP32SHIFT
(12, 0, 0, 0, 0, 0);
2435 return
yyerror ("Dregs expected");
2439 /* LOGI2op: BITCLR (dregs, uimm5). */
2440 | BITCLR LPAREN REG COMMA expr RPAREN
2442 if
(IS_DREG
($3) && IS_UIMM
($5, 5))
2444 notethat
("LOGI2op: BITCLR (dregs , uimm5 )\n");
2445 $$
= LOGI2OP
($3, uimm5
($5), 4);
2448 return
yyerror ("Register mismatch");
2451 /* LOGI2op: BITSET (dregs, uimm5). */
2452 | BITSET LPAREN REG COMMA expr RPAREN
2454 if
(IS_DREG
($3) && IS_UIMM
($5, 5))
2456 notethat
("LOGI2op: BITCLR (dregs , uimm5 )\n");
2457 $$
= LOGI2OP
($3, uimm5
($5), 2);
2460 return
yyerror ("Register mismatch");
2463 /* LOGI2op: BITTGL (dregs, uimm5). */
2464 | BITTGL LPAREN REG COMMA expr RPAREN
2466 if
(IS_DREG
($3) && IS_UIMM
($5, 5))
2468 notethat
("LOGI2op: BITCLR (dregs , uimm5 )\n");
2469 $$
= LOGI2OP
($3, uimm5
($5), 3);
2472 return
yyerror ("Register mismatch");
2475 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2477 if
(IS_DREG
($5) && IS_UIMM
($7, 5))
2479 notethat
("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2480 $$
= LOGI2OP
($5, uimm5
($7), 0);
2483 return
yyerror ("Register mismatch or value error");
2486 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2488 if
(IS_DREG
($5) && IS_UIMM
($7, 5))
2490 notethat
("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2491 $$
= LOGI2OP
($5, uimm5
($7), 1);
2494 return
yyerror ("Register mismatch or value error");
2497 | IF BANG CCREG REG ASSIGN REG
2499 if
((IS_DREG
($4) || IS_PREG
($4))
2500 && (IS_DREG
($6) || IS_PREG
($6)))
2502 notethat
("ccMV: IF ! CC gregs = gregs\n");
2503 $$
= CCMV
(&$6, &$4, 0);
2506 return
yyerror ("Register mismatch");
2509 | IF CCREG REG ASSIGN REG
2511 if
((IS_DREG
($5) || IS_PREG
($5))
2512 && (IS_DREG
($3) || IS_PREG
($3)))
2514 notethat
("ccMV: IF CC gregs = gregs\n");
2515 $$
= CCMV
(&$5, &$3, 1);
2518 return
yyerror ("Register mismatch");
2521 | IF BANG CCREG JUMP expr
2523 if
(IS_PCREL10
($5))
2525 notethat
("BRCC: IF !CC JUMP pcrel11m2\n");
2526 $$
= BRCC
(0, 0, $5);
2529 return
yyerror ("Bad jump offset");
2532 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2534 if
(IS_PCREL10
($5))
2536 notethat
("BRCC: IF !CC JUMP pcrel11m2\n");
2537 $$
= BRCC
(0, 1, $5);
2540 return
yyerror ("Bad jump offset");
2543 | IF CCREG JUMP expr
2545 if
(IS_PCREL10
($4))
2547 notethat
("BRCC: IF CC JUMP pcrel11m2\n");
2548 $$
= BRCC
(1, 0, $4);
2551 return
yyerror ("Bad jump offset");
2554 | IF CCREG JUMP expr LPAREN BP RPAREN
2556 if
(IS_PCREL10
($4))
2558 notethat
("BRCC: IF !CC JUMP pcrel11m2\n");
2559 $$
= BRCC
(1, 1, $4);
2562 return
yyerror ("Bad jump offset");
2566 notethat
("ProgCtrl: NOP\n");
2567 $$
= PROGCTRL
(0, 0);
2572 notethat
("ProgCtrl: RTS\n");
2573 $$
= PROGCTRL
(1, 0);
2578 notethat
("ProgCtrl: RTI\n");
2579 $$
= PROGCTRL
(1, 1);
2584 notethat
("ProgCtrl: RTX\n");
2585 $$
= PROGCTRL
(1, 2);
2590 notethat
("ProgCtrl: RTN\n");
2591 $$
= PROGCTRL
(1, 3);
2596 notethat
("ProgCtrl: RTE\n");
2597 $$
= PROGCTRL
(1, 4);
2602 notethat
("ProgCtrl: IDLE\n");
2603 $$
= PROGCTRL
(2, 0);
2608 notethat
("ProgCtrl: CSYNC\n");
2609 $$
= PROGCTRL
(2, 3);
2614 notethat
("ProgCtrl: SSYNC\n");
2615 $$
= PROGCTRL
(2, 4);
2620 notethat
("ProgCtrl: EMUEXCPT\n");
2621 $$
= PROGCTRL
(2, 5);
2628 notethat
("ProgCtrl: CLI dregs\n");
2629 $$
= PROGCTRL
(3, $2.regno
& CODE_MASK
);
2632 return
yyerror ("Dreg expected for CLI");
2639 notethat
("ProgCtrl: STI dregs\n");
2640 $$
= PROGCTRL
(4, $2.regno
& CODE_MASK
);
2643 return
yyerror ("Dreg expected for STI");
2646 | JUMP LPAREN REG RPAREN
2650 notethat
("ProgCtrl: JUMP (pregs )\n");
2651 $$
= PROGCTRL
(5, $3.regno
& CODE_MASK
);
2654 return
yyerror ("Bad register for indirect jump");
2657 | CALL LPAREN REG RPAREN
2661 notethat
("ProgCtrl: CALL (pregs )\n");
2662 $$
= PROGCTRL
(6, $3.regno
& CODE_MASK
);
2665 return
yyerror ("Bad register for indirect call");
2668 | CALL LPAREN PC PLUS REG RPAREN
2672 notethat
("ProgCtrl: CALL (PC + pregs )\n");
2673 $$
= PROGCTRL
(7, $5.regno
& CODE_MASK
);
2676 return
yyerror ("Bad register for indirect call");
2679 | JUMP LPAREN PC PLUS REG RPAREN
2683 notethat
("ProgCtrl: JUMP (PC + pregs )\n");
2684 $$
= PROGCTRL
(8, $5.regno
& CODE_MASK
);
2687 return
yyerror ("Bad register for indirect jump");
2692 if
(IS_UIMM
($2, 4))
2694 notethat
("ProgCtrl: RAISE uimm4\n");
2695 $$
= PROGCTRL
(9, uimm4
($2));
2698 return
yyerror ("Bad value for RAISE");
2703 notethat
("ProgCtrl: EMUEXCPT\n");
2704 $$
= PROGCTRL
(10, uimm4
($2));
2707 | TESTSET LPAREN REG RPAREN
2711 if
($3.regno
== REG_SP ||
$3.regno
== REG_FP
)
2712 return
yyerror ("Bad register for TESTSET");
2714 notethat
("ProgCtrl: TESTSET (pregs )\n");
2715 $$
= PROGCTRL
(11, $3.regno
& CODE_MASK
);
2718 return
yyerror ("Preg expected");
2723 if
(IS_PCREL12
($2))
2725 notethat
("UJUMP: JUMP pcrel12\n");
2729 return
yyerror ("Bad value for relative jump");
2734 if
(IS_PCREL12
($2))
2736 notethat
("UJUMP: JUMP_DOT_S pcrel12\n");
2740 return
yyerror ("Bad value for relative jump");
2745 if
(IS_PCREL24
($2))
2747 notethat
("CALLa: jump.l pcrel24\n");
2751 return
yyerror ("Bad value for long jump");
2756 if
(IS_PCREL24
($2))
2758 notethat
("CALLa: jump.l pcrel24\n");
2762 return
yyerror ("Bad value for long jump");
2767 if
(IS_PCREL24
($2))
2769 notethat
("CALLa: CALL pcrel25m2\n");
2773 return
yyerror ("Bad call address");
2777 if
(IS_PCREL24
($2))
2779 notethat
("CALLa: CALL pcrel25m2\n");
2783 return
yyerror ("Bad call address");
2787 /* ALU2op: DIVQ (dregs, dregs). */
2788 | DIVQ LPAREN REG COMMA REG RPAREN
2790 if
(IS_DREG
($3) && IS_DREG
($5))
2791 $$
= ALU2OP
(&$3, &$5, 8);
2793 return
yyerror ("Bad registers for DIVQ");
2796 | DIVS LPAREN REG COMMA REG RPAREN
2798 if
(IS_DREG
($3) && IS_DREG
($5))
2799 $$
= ALU2OP
(&$3, &$5, 9);
2801 return
yyerror ("Bad registers for DIVS");
2804 | REG ASSIGN MINUS REG vsmod
2806 if
(IS_DREG
($1) && IS_DREG
($4))
2808 if
($5.r0
== 0 && $5.s0
== 0 && $5.aop
== 0)
2810 notethat
("ALU2op: dregs = - dregs\n");
2811 $$
= ALU2OP
(&$1, &$4, 14);
2813 else if
($5.r0
== 1 && $5.s0
== 0 && $5.aop
== 3)
2815 notethat
("dsp32alu: dregs = - dregs (.)\n");
2816 $$
= DSP32ALU
(15, 0, 0, &$1, &$4, 0, $5.s0
, 0, 3);
2820 notethat
("dsp32alu: dregs = - dregs (.)\n");
2821 $$
= DSP32ALU
(7, 0, 0, &$1, &$4, 0, $5.s0
, 0, 3);
2825 return
yyerror ("Dregs expected");
2828 | REG ASSIGN TILDA REG
2830 if
(IS_DREG
($1) && IS_DREG
($4))
2832 notethat
("ALU2op: dregs = ~dregs\n");
2833 $$
= ALU2OP
(&$1, &$4, 15);
2836 return
yyerror ("Dregs expected");
2839 | REG _GREATER_GREATER_ASSIGN REG
2841 if
(IS_DREG
($1) && IS_DREG
($3))
2843 notethat
("ALU2op: dregs >>= dregs\n");
2844 $$
= ALU2OP
(&$1, &$3, 1);
2847 return
yyerror ("Dregs expected");
2850 | REG _GREATER_GREATER_ASSIGN expr
2852 if
(IS_DREG
($1) && IS_UIMM
($3, 5))
2854 notethat
("LOGI2op: dregs >>= uimm5\n");
2855 $$
= LOGI2OP
($1, uimm5
($3), 6);
2858 return
yyerror ("Dregs expected or value error");
2861 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2863 if
(IS_DREG
($1) && IS_DREG
($3))
2865 notethat
("ALU2op: dregs >>>= dregs\n");
2866 $$
= ALU2OP
(&$1, &$3, 0);
2869 return
yyerror ("Dregs expected");
2872 | REG _LESS_LESS_ASSIGN REG
2874 if
(IS_DREG
($1) && IS_DREG
($3))
2876 notethat
("ALU2op: dregs <<= dregs\n");
2877 $$
= ALU2OP
(&$1, &$3, 2);
2880 return
yyerror ("Dregs expected");
2883 | REG _LESS_LESS_ASSIGN expr
2885 if
(IS_DREG
($1) && IS_UIMM
($3, 5))
2887 notethat
("LOGI2op: dregs <<= uimm5\n");
2888 $$
= LOGI2OP
($1, uimm5
($3), 7);
2891 return
yyerror ("Dregs expected or const value error");
2895 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2897 if
(IS_DREG
($1) && IS_UIMM
($3, 5))
2899 notethat
("LOGI2op: dregs >>>= uimm5\n");
2900 $$
= LOGI2OP
($1, uimm5
($3), 5);
2903 return
yyerror ("Dregs expected");
2906 /* Cache Control. */
2908 | FLUSH LBRACK REG RBRACK
2910 notethat
("CaCTRL: FLUSH [ pregs ]\n");
2912 $$
= CACTRL
(&$3, 0, 2);
2914 return
yyerror ("Bad register(s) for FLUSH");
2917 | FLUSH reg_with_postinc
2921 notethat
("CaCTRL: FLUSH [ pregs ++ ]\n");
2922 $$
= CACTRL
(&$2, 1, 2);
2925 return
yyerror ("Bad register(s) for FLUSH");
2928 | FLUSHINV LBRACK REG RBRACK
2932 notethat
("CaCTRL: FLUSHINV [ pregs ]\n");
2933 $$
= CACTRL
(&$3, 0, 1);
2936 return
yyerror ("Bad register(s) for FLUSH");
2939 | FLUSHINV reg_with_postinc
2943 notethat
("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2944 $$
= CACTRL
(&$2, 1, 1);
2947 return
yyerror ("Bad register(s) for FLUSH");
2950 /* CaCTRL: IFLUSH [pregs]. */
2951 | IFLUSH LBRACK REG RBRACK
2955 notethat
("CaCTRL: IFLUSH [ pregs ]\n");
2956 $$
= CACTRL
(&$3, 0, 3);
2959 return
yyerror ("Bad register(s) for FLUSH");
2962 | IFLUSH reg_with_postinc
2966 notethat
("CaCTRL: IFLUSH [ pregs ++ ]\n");
2967 $$
= CACTRL
(&$2, 1, 3);
2970 return
yyerror ("Bad register(s) for FLUSH");
2973 | PREFETCH LBRACK REG RBRACK
2977 notethat
("CaCTRL: PREFETCH [ pregs ]\n");
2978 $$
= CACTRL
(&$3, 0, 0);
2981 return
yyerror ("Bad register(s) for PREFETCH");
2984 | PREFETCH reg_with_postinc
2988 notethat
("CaCTRL: PREFETCH [ pregs ++ ]\n");
2989 $$
= CACTRL
(&$2, 1, 0);
2992 return
yyerror ("Bad register(s) for PREFETCH");
2996 /* LDST: B [ pregs <post_op> ] = dregs. */
2998 | B LBRACK REG post_op RBRACK ASSIGN REG
3001 return
yyerror ("Dreg expected for source operand");
3003 return
yyerror ("Preg expected in address");
3005 notethat
("LDST: B [ pregs <post_op> ] = dregs\n");
3006 $$
= LDST
(&$3, &$7, $4.x0
, 2, 0, 1);
3009 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
3010 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
3012 Expr_Node
*tmp
= $5;
3015 return
yyerror ("Dreg expected for source operand");
3017 return
yyerror ("Preg expected in address");
3020 return
yyerror ("Plain symbol used as offset");
3023 tmp
= unary
(Expr_Op_Type_NEG
, tmp
);
3025 if
(in_range_p
(tmp
, -32768, 32767, 0))
3027 notethat
("LDST: B [ pregs + imm16 ] = dregs\n");
3028 $$
= LDSTIDXI
(&$3, &$8, 1, 2, 0, $5);
3031 return
yyerror ("Displacement out of range");
3035 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
3036 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
3038 Expr_Node
*tmp
= $5;
3041 return
yyerror ("Dreg expected for source operand");
3043 return
yyerror ("Preg expected in address");
3046 tmp
= unary
(Expr_Op_Type_NEG
, tmp
);
3049 return
yyerror ("Plain symbol used as offset");
3051 if
(in_range_p
(tmp
, 0, 30, 1))
3053 notethat
("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3054 $$
= LDSTII
(&$3, &$8, tmp
, 1, 1);
3056 else if
(in_range_p
(tmp
, -65536, 65535, 1))
3058 notethat
("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3059 $$
= LDSTIDXI
(&$3, &$8, 1, 1, 0, tmp
);
3062 return
yyerror ("Displacement out of range");
3065 /* LDST: W [ pregs <post_op> ] = dregs. */
3066 | W LBRACK REG post_op RBRACK ASSIGN REG
3069 return
yyerror ("Dreg expected for source operand");
3071 return
yyerror ("Preg expected in address");
3073 notethat
("LDST: W [ pregs <post_op> ] = dregs\n");
3074 $$
= LDST
(&$3, &$7, $4.x0
, 1, 0, 1);
3077 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3080 return
yyerror ("Dreg expected for source operand");
3083 if
(!IS_IREG
($3) && !IS_PREG
($3))
3084 return
yyerror ("Ireg or Preg expected in address");
3086 else if
(!IS_IREG
($3))
3087 return
yyerror ("Ireg expected in address");
3091 notethat
("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3092 $$
= DSPLDST
(&$3, 1 + IS_H
($7), &$7, $4.x0
, 1);
3096 notethat
("LDSTpmod: W [ pregs ] = dregs_half\n");
3097 $$
= LDSTPMOD
(&$3, &$7, &$3, 1 + IS_H
($7), 1);
3101 /* LDSTiiFP: [ FP - const ] = dpregs. */
3102 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3104 Expr_Node
*tmp
= $4;
3105 int ispreg
= IS_PREG
($7);
3108 return
yyerror ("Preg expected in address");
3110 if
(!IS_DREG
($7) && !ispreg
)
3111 return
yyerror ("Preg expected for source operand");
3114 tmp
= unary
(Expr_Op_Type_NEG
, tmp
);
3117 return
yyerror ("Plain symbol used as offset");
3119 if
(in_range_p
(tmp
, 0, 63, 3))
3121 notethat
("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3122 $$
= LDSTII
(&$2, &$7, tmp
, 1, ispreg ?
3 : 0);
3124 else if
($2.regno
== REG_FP
&& in_range_p
(tmp
, -128, 0, 3))
3126 notethat
("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3127 tmp
= unary
(Expr_Op_Type_NEG
, tmp
);
3128 $$
= LDSTIIFP
(tmp
, &$7, 1);
3130 else if
(in_range_p
(tmp
, -131072, 131071, 3))
3132 notethat
("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3133 $$
= LDSTIDXI
(&$2, &$7, 1, 0, ispreg ?
1 : 0, tmp
);
3136 return
yyerror ("Displacement out of range");
3139 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3141 Expr_Node
*tmp
= $7;
3143 return
yyerror ("Dreg expected for destination operand");
3145 return
yyerror ("Preg expected in address");
3148 tmp
= unary
(Expr_Op_Type_NEG
, tmp
);
3151 return
yyerror ("Plain symbol used as offset");
3153 if
(in_range_p
(tmp
, 0, 30, 1))
3155 notethat
("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3156 $$
= LDSTII
(&$5, &$1, tmp
, 0, 1 << $9.r0
);
3158 else if
(in_range_p
(tmp
, -65536, 65535, 1))
3160 notethat
("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3161 $$
= LDSTIDXI
(&$5, &$1, 0, 1, $9.r0
, tmp
);
3164 return
yyerror ("Displacement out of range");
3167 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3170 return
yyerror ("Dreg expected for source operand");
3173 if
(!IS_IREG
($5) && !IS_PREG
($5))
3174 return
yyerror ("Ireg or Preg expected in address");
3176 else if
(!IS_IREG
($5))
3177 return
yyerror ("Ireg expected in address");
3181 notethat
("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3182 $$
= DSPLDST
(&$5, 1 + IS_H
($1), &$1, $6.x0
, 0);
3186 notethat
("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3187 $$
= LDSTPMOD
(&$5, &$1, &$5, 1 + IS_H
($1), 0);
3192 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3195 return
yyerror ("Dreg expected for destination operand");
3197 return
yyerror ("Preg expected in address");
3199 notethat
("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3200 $$
= LDST
(&$5, &$1, $6.x0
, 1, $8.r0
, 0);
3203 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3206 return
yyerror ("Dreg expected for destination operand");
3207 if
(!IS_PREG
($5) ||
!IS_PREG
($7))
3208 return
yyerror ("Preg expected in address");
3210 notethat
("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3211 $$
= LDSTPMOD
(&$5, &$1, &$7, 3, $9.r0
);
3214 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3217 return
yyerror ("Dreg expected for destination operand");
3218 if
(!IS_PREG
($5) ||
!IS_PREG
($7))
3219 return
yyerror ("Preg expected in address");
3221 notethat
("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3222 $$
= LDSTPMOD
(&$5, &$1, &$7, 1 + IS_H
($1), 0);
3225 | LBRACK REG post_op RBRACK ASSIGN REG
3227 if
(!IS_IREG
($2) && !IS_PREG
($2))
3228 return
yyerror ("Ireg or Preg expected in address");
3229 else if
(IS_IREG
($2) && !IS_DREG
($6))
3230 return
yyerror ("Dreg expected for source operand");
3231 else if
(IS_PREG
($2) && !IS_DREG
($6) && !IS_PREG
($6))
3232 return
yyerror ("Dreg or Preg expected for source operand");
3236 notethat
("dspLDST: [ iregs <post_op> ] = dregs\n");
3237 $$
= DSPLDST
(&$2, 0, &$6, $3.x0
, 1);
3239 else if
(IS_DREG
($6))
3241 notethat
("LDST: [ pregs <post_op> ] = dregs\n");
3242 $$
= LDST
(&$2, &$6, $3.x0
, 0, 0, 1);
3246 notethat
("LDST: [ pregs <post_op> ] = pregs\n");
3247 $$
= LDST
(&$2, &$6, $3.x0
, 0, 1, 1);
3251 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3254 return
yyerror ("Dreg expected for source operand");
3256 if
(IS_IREG
($2) && IS_MREG
($4))
3258 notethat
("dspLDST: [ iregs ++ mregs ] = dregs\n");
3259 $$
= DSPLDST
(&$2, $4.regno
& CODE_MASK
, &$7, 3, 1);
3261 else if
(IS_PREG
($2) && IS_PREG
($4))
3263 notethat
("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3264 $$
= LDSTPMOD
(&$2, &$7, &$4, 0, 1);
3267 return
yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3270 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3273 return
yyerror ("Dreg expected for source operand");
3275 if
(IS_PREG
($3) && IS_PREG
($5))
3277 notethat
("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3278 $$
= LDSTPMOD
(&$3, &$8, &$5, 1 + IS_H
($8), 1);
3281 return
yyerror ("Preg ++ Preg expected in address");
3284 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3286 Expr_Node
*tmp
= $7;
3288 return
yyerror ("Dreg expected for destination operand");
3290 return
yyerror ("Preg expected in address");
3293 tmp
= unary
(Expr_Op_Type_NEG
, tmp
);
3296 return
yyerror ("Plain symbol used as offset");
3298 if
(in_range_p
(tmp
, -32768, 32767, 0))
3300 notethat
("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3302 $$
= LDSTIDXI
(&$5, &$1, 0, 2, $9.r0
, tmp
);
3305 return
yyerror ("Displacement out of range");
3308 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3311 return
yyerror ("Dreg expected for destination operand");
3313 return
yyerror ("Preg expected in address");
3315 notethat
("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3317 $$
= LDST
(&$5, &$1, $6.x0
, 2, $8.r0
, 0);
3320 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3323 return
yyerror ("Dreg expected for destination operand");
3325 if
(IS_IREG
($4) && IS_MREG
($6))
3327 notethat
("dspLDST: dregs = [ iregs ++ mregs ]\n");
3328 $$
= DSPLDST
(&$4, $6.regno
& CODE_MASK
, &$1, 3, 0);
3330 else if
(IS_PREG
($4) && IS_PREG
($6))
3332 notethat
("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3333 $$
= LDSTPMOD
(&$4, &$1, &$6, 0, 0);
3336 return
yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3339 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3341 Expr_Node
*tmp
= $6;
3342 int ispreg
= IS_PREG
($1);
3343 int isgot
= IS_RELOC
($6);
3346 return
yyerror ("Preg expected in address");
3348 if
(!IS_DREG
($1) && !ispreg
)
3349 return
yyerror ("Dreg or Preg expected for destination operand");
3351 if
(tmp
->type
== Expr_Node_Reloc
3352 && strcmp
(tmp
->value.s_value
,
3353 "_current_shared_library_p5_offset_") != 0)
3354 return
yyerror ("Plain symbol used as offset");
3357 tmp
= unary
(Expr_Op_Type_NEG
, tmp
);
3361 notethat
("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3362 $$
= LDSTIDXI
(&$4, &$1, 0, 0, ispreg ?
1 : 0, tmp
);
3364 else if
(in_range_p
(tmp
, 0, 63, 3))
3366 notethat
("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3367 $$
= LDSTII
(&$4, &$1, tmp
, 0, ispreg ?
3 : 0);
3369 else if
($4.regno
== REG_FP
&& in_range_p
(tmp
, -128, 0, 3))
3371 notethat
("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3372 tmp
= unary
(Expr_Op_Type_NEG
, tmp
);
3373 $$
= LDSTIIFP
(tmp
, &$1, 0);
3375 else if
(in_range_p
(tmp
, -131072, 131071, 3))
3377 notethat
("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3378 $$
= LDSTIDXI
(&$4, &$1, 0, 0, ispreg ?
1 : 0, tmp
);
3382 return
yyerror ("Displacement out of range");
3385 | REG ASSIGN LBRACK REG post_op RBRACK
3387 if
(!IS_IREG
($4) && !IS_PREG
($4))
3388 return
yyerror ("Ireg or Preg expected in address");
3389 else if
(IS_IREG
($4) && !IS_DREG
($1))
3390 return
yyerror ("Dreg expected in destination operand");
3391 else if
(IS_PREG
($4) && !IS_DREG
($1) && !IS_PREG
($1)
3392 && ($4.regno
!= REG_SP ||
!IS_ALLREG
($1) ||
$5.x0
!= 0))
3393 return
yyerror ("Dreg or Preg expected in destination operand");
3397 notethat
("dspLDST: dregs = [ iregs <post_op> ]\n");
3398 $$
= DSPLDST
(&$4, 0, &$1, $5.x0
, 0);
3400 else if
(IS_DREG
($1))
3402 notethat
("LDST: dregs = [ pregs <post_op> ]\n");
3403 $$
= LDST
(&$4, &$1, $5.x0
, 0, 0, 0);
3405 else if
(IS_PREG
($1))
3407 if
(REG_SAME
($1, $4) && $5.x0
!= 2)
3408 return
yyerror ("Pregs can't be same");
3410 notethat
("LDST: pregs = [ pregs <post_op> ]\n");
3411 $$
= LDST
(&$4, &$1, $5.x0
, 0, 1, 0);
3415 notethat
("PushPopReg: allregs = [ SP ++ ]\n");
3416 $$
= PUSHPOPREG
(&$1, 0);
3421 /* PushPopMultiple. */
3422 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3424 if
($1.regno
!= REG_SP
)
3425 yyerror ("Stack Pointer expected");
3426 if
($4.regno
== REG_R7
3427 && IN_RANGE
($6, 0, 7)
3428 && $8.regno
== REG_P5
3429 && IN_RANGE
($10, 0, 5))
3431 notethat
("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3432 $$
= PUSHPOPMULTIPLE
(imm5
($6), imm5
($10), 1, 1, 1);
3435 return
yyerror ("Bad register for PushPopMultiple");
3438 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3440 if
($1.regno
!= REG_SP
)
3441 yyerror ("Stack Pointer expected");
3443 if
($4.regno
== REG_R7
&& IN_RANGE
($6, 0, 7))
3445 notethat
("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3446 $$
= PUSHPOPMULTIPLE
(imm5
($6), 0, 1, 0, 1);
3448 else if
($4.regno
== REG_P5
&& IN_RANGE
($6, 0, 6))
3450 notethat
("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3451 $$
= PUSHPOPMULTIPLE
(0, imm5
($6), 0, 1, 1);
3454 return
yyerror ("Bad register for PushPopMultiple");
3457 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3459 if
($11.regno
!= REG_SP
)
3460 yyerror ("Stack Pointer expected");
3461 if
($2.regno
== REG_R7
&& (IN_RANGE
($4, 0, 7))
3462 && $6.regno
== REG_P5
&& (IN_RANGE
($8, 0, 6)))
3464 notethat
("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3465 $$
= PUSHPOPMULTIPLE
(imm5
($4), imm5
($8), 1, 1, 0);
3468 return
yyerror ("Bad register range for PushPopMultiple");
3471 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3473 if
($7.regno
!= REG_SP
)
3474 yyerror ("Stack Pointer expected");
3476 if
($2.regno
== REG_R7
&& IN_RANGE
($4, 0, 7))
3478 notethat
("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3479 $$
= PUSHPOPMULTIPLE
(imm5
($4), 0, 1, 0, 0);
3481 else if
($2.regno
== REG_P5
&& IN_RANGE
($4, 0, 6))
3483 notethat
("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3484 $$
= PUSHPOPMULTIPLE
(0, imm5
($4), 0, 1, 0);
3487 return
yyerror ("Bad register range for PushPopMultiple");
3490 | reg_with_predec ASSIGN REG
3492 if
($1.regno
!= REG_SP
)
3493 yyerror ("Stack Pointer expected");
3497 notethat
("PushPopReg: [ -- SP ] = allregs\n");
3498 $$
= PUSHPOPREG
(&$3, 1);
3501 return
yyerror ("Bad register for PushPopReg");
3508 if
(IS_URANGE
(16, $2, 0, 4))
3509 $$
= LINKAGE
(0, uimm16s4
($2));
3511 return
yyerror ("Bad constant for LINK");
3516 notethat
("linkage: UNLINK\n");
3517 $$
= LINKAGE
(1, 0);
3523 | LSETUP LPAREN expr COMMA expr RPAREN REG
3525 if
(IS_PCREL4
($3) && IS_LPPCREL10
($5) && IS_CREG
($7))
3527 notethat
("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3528 $$
= LOOPSETUP
($3, &$7, 0, $5, 0);
3531 return
yyerror ("Bad register or values for LSETUP");
3534 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3536 if
(IS_PCREL4
($3) && IS_LPPCREL10
($5)
3537 && IS_PREG
($9) && IS_CREG
($7))
3539 notethat
("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3540 $$
= LOOPSETUP
($3, &$7, 1, $5, &$9);
3543 return
yyerror ("Bad register or values for LSETUP");
3546 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3548 if
(IS_PCREL4
($3) && IS_LPPCREL10
($5)
3549 && IS_PREG
($9) && IS_CREG
($7)
3550 && EXPR_VALUE
($11) == 1)
3552 notethat
("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3553 $$
= LOOPSETUP
($3, &$7, 3, $5, &$9);
3556 return
yyerror ("Bad register or values for LSETUP");
3563 return
yyerror ("Invalid expression in loop statement");
3565 return
yyerror ("Invalid loop counter register");
3566 $$
= bfin_gen_loop
($2, &$3, 0, 0);
3568 | LOOP expr REG ASSIGN REG
3570 if
(IS_RELOC
($2) && IS_PREG
($5) && IS_CREG
($3))
3572 notethat
("Loop: LOOP expr counters = pregs\n");
3573 $$
= bfin_gen_loop
($2, &$3, 1, &$5);
3576 return
yyerror ("Bad register or values for LOOP");
3578 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3580 if
(IS_RELOC
($2) && IS_PREG
($5) && IS_CREG
($3) && EXPR_VALUE
($7) == 1)
3582 notethat
("Loop: LOOP expr counters = pregs >> 1\n");
3583 $$
= bfin_gen_loop
($2, &$3, 3, &$5);
3586 return
yyerror ("Bad register or values for LOOP");
3592 Expr_Node_Value val
;
3594 Expr_Node
*tmp
= Expr_Node_Create
(Expr_Node_Constant
, val
, NULL
, NULL
);
3595 bfin_loop_attempt_create_label
(tmp
, 1);
3596 if
(!IS_RELOC
(tmp
))
3597 return
yyerror ("Invalid expression in LOOP_BEGIN statement");
3598 bfin_loop_beginend
(tmp
, 1);
3604 return
yyerror ("Invalid expression in LOOP_BEGIN statement");
3606 bfin_loop_beginend
($2, 1);
3613 Expr_Node_Value val
;
3615 Expr_Node
*tmp
= Expr_Node_Create
(Expr_Node_Constant
, val
, NULL
, NULL
);
3616 bfin_loop_attempt_create_label
(tmp
, 1);
3617 if
(!IS_RELOC
(tmp
))
3618 return
yyerror ("Invalid expression in LOOP_END statement");
3619 bfin_loop_beginend
(tmp
, 0);
3625 return
yyerror ("Invalid expression in LOOP_END statement");
3627 bfin_loop_beginend
($2, 0);
3635 notethat
("psedoDEBUG: ABORT\n");
3636 $$
= bfin_gen_pseudodbg
(3, 3, 0);
3641 notethat
("pseudoDEBUG: DBG\n");
3642 $$
= bfin_gen_pseudodbg
(3, 7, 0);
3646 notethat
("pseudoDEBUG: DBG REG_A\n");
3647 $$
= bfin_gen_pseudodbg
(3, IS_A1
($2), 0);
3651 notethat
("pseudoDEBUG: DBG allregs\n");
3652 $$
= bfin_gen_pseudodbg
(0, $2.regno
& CODE_MASK
, ($2.regno
& CLASS_MASK
) >> 4);
3655 | DBGCMPLX LPAREN REG RPAREN
3658 return
yyerror ("Dregs expected");
3659 notethat
("pseudoDEBUG: DBGCMPLX (dregs )\n");
3660 $$
= bfin_gen_pseudodbg
(3, 6, ($3.regno
& CODE_MASK
) >> 4);
3665 notethat
("psedoDEBUG: DBGHALT\n");
3666 $$
= bfin_gen_pseudodbg
(3, 5, 0);
3671 notethat
("psedoDEBUG: HLT\n");
3672 $$
= bfin_gen_pseudodbg
(3, 4, 0);
3675 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3677 notethat
("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
3678 $$
= bfin_gen_pseudodbg_assert
(IS_H
($3), &$3, uimm16
($5));
3681 | DBGAH LPAREN REG COMMA expr RPAREN
3683 notethat
("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
3684 $$
= bfin_gen_pseudodbg_assert
(3, &$3, uimm16
($5));
3687 | DBGAL LPAREN REG COMMA expr RPAREN
3689 notethat
("psedodbg_assert: DBGAL (regs , uimm16 )\n");
3690 $$
= bfin_gen_pseudodbg_assert
(2, &$3, uimm16
($5));
3695 if
(!IS_UIMM
($2, 8))
3696 return
yyerror ("Constant out of range");
3697 notethat
("psedodbg_assert: OUTC uimm8\n");
3698 $$
= bfin_gen_pseudochr
(uimm8
($2));
3704 return
yyerror ("Dregs expected");
3705 notethat
("psedodbg_assert: OUTC dreg\n");
3706 $$
= bfin_gen_pseudodbg
(2, $2.regno
& CODE_MASK
, 0);
3713 /* Register rules. */
3715 REG_A: REG_A_DOUBLE_ZERO
3733 | LPAREN M COMMA MMOD RPAREN
3738 | LPAREN MMOD COMMA M RPAREN
3743 | LPAREN MMOD RPAREN
3755 asr_asl: LPAREN ASL RPAREN
3836 | LPAREN asr_asl_0 RPAREN
3848 | LPAREN asr_asl_0 COMMA sco RPAREN
3854 | LPAREN sco COMMA asr_asl_0 RPAREN
3914 | LPAREN V COMMA S RPAREN
3919 | LPAREN S COMMA V RPAREN
3981 | LPAREN MMOD RPAREN
3984 return
yyerror ("Bad modifier");
3988 | LPAREN MMOD COMMA R RPAREN
3991 return
yyerror ("Bad modifier");
3995 | LPAREN R COMMA MMOD RPAREN
3998 return
yyerror ("Bad modifier");
4025 | LPAREN MMOD RPAREN
4030 return
yyerror ("Only (W32) allowed");
4038 | LPAREN MMOD RPAREN
4043 return
yyerror ("(IU) expected");
4047 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
4053 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
4105 $$.r0
= 1; /* HL. */
4108 $$.aop
= 0; /* aop. */
4113 $$.r0
= 1; /* HL. */
4116 $$.aop
= 1; /* aop. */
4119 | LPAREN RNDL RPAREN
4121 $$.r0
= 0; /* HL. */
4124 $$.aop
= 0; /* aop. */
4129 $$.r0
= 0; /* HL. */
4135 | LPAREN RNDH COMMA R RPAREN
4137 $$.r0
= 1; /* HL. */
4140 $$.aop
= 0; /* aop. */
4142 | LPAREN TH COMMA R RPAREN
4144 $$.r0
= 1; /* HL. */
4147 $$.aop
= 1; /* aop. */
4149 | LPAREN RNDL COMMA R RPAREN
4151 $$.r0
= 0; /* HL. */
4154 $$.aop
= 0; /* aop. */
4157 | LPAREN TL COMMA R RPAREN
4159 $$.r0
= 0; /* HL. */
4162 $$.aop
= 1; /* aop. */
4170 $$.x0
= 0; /* HL. */
4175 $$.x0
= 1; /* HL. */
4177 | LPAREN LO COMMA R RPAREN
4180 $$.x0
= 0; /* HL. */
4182 | LPAREN HI COMMA R RPAREN
4185 $$.x0
= 1; /* HL. */
4203 /* Assignments, Macfuncs. */
4229 if
(IS_A1
($3) && IS_EVEN
($1))
4230 return
yyerror ("Cannot move A1 to even register");
4231 else if
(!IS_A1
($3) && !IS_EVEN
($1))
4232 return
yyerror ("Cannot move A0 to odd register");
4248 | REG ASSIGN LPAREN a_macfunc RPAREN
4250 if
($4.n
&& IS_EVEN
($1))
4251 return
yyerror ("Cannot move A1 to even register");
4252 else if
(!$4.n
&& !IS_EVEN
($1))
4253 return
yyerror ("Cannot move A0 to odd register");
4261 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4263 if
($4.n
&& !IS_H
($1))
4264 return
yyerror ("Cannot move A1 to low half of register");
4265 else if
(!$4.n
&& IS_H
($1))
4266 return
yyerror ("Cannot move A0 to high half of register");
4274 | HALF_REG ASSIGN REG_A
4276 if
(IS_A1
($3) && !IS_H
($1))
4277 return
yyerror ("Cannot move A1 to low half of register");
4278 else if
(!IS_A1
($3) && IS_H
($1))
4279 return
yyerror ("Cannot move A0 to high half of register");
4292 a_assign multiply_halfregs
4299 | a_plusassign multiply_halfregs
4306 | a_minusassign multiply_halfregs
4316 HALF_REG STAR HALF_REG
4318 if
(IS_DREG
($1) && IS_DREG
($3))
4324 return
yyerror ("Dregs expected");
4348 CCREG cc_op STATUS_REG
4360 | STATUS_REG cc_op CCREG
4374 /* Expressions and Symbols. */
4378 Expr_Node_Value val
;
4379 val.s_value
= S_GET_NAME
($1);
4380 $$
= Expr_Node_Create
(Expr_Node_Reloc
, val
, NULL
, NULL
);
4386 { $$
= BFD_RELOC_BFIN_GOT
; }
4388 { $$
= BFD_RELOC_BFIN_GOT17M4
; }
4390 { $$
= BFD_RELOC_BFIN_FUNCDESC_GOT17M4
; }
4393 got: symbol AT any_gotrel
4395 Expr_Node_Value val
;
4397 $$
= Expr_Node_Create
(Expr_Node_GOT_Reloc
, val
, $1, NULL
);
4420 Expr_Node_Value val
;
4422 $$
= Expr_Node_Create
(Expr_Node_Constant
, val
, NULL
, NULL
);
4428 | LPAREN expr_1 RPAREN
4434 $$
= unary
(Expr_Op_Type_COMP
, $2);
4436 | MINUS expr_1 %prec TILDA
4438 $$
= unary
(Expr_Op_Type_NEG
, $2);
4448 expr_1: expr_1 STAR expr_1
4450 $$
= binary
(Expr_Op_Type_Mult
, $1, $3);
4452 | expr_1 SLASH expr_1
4454 $$
= binary
(Expr_Op_Type_Div
, $1, $3);
4456 | expr_1 PERCENT expr_1
4458 $$
= binary
(Expr_Op_Type_Mod
, $1, $3);
4460 | expr_1 PLUS expr_1
4462 $$
= binary
(Expr_Op_Type_Add
, $1, $3);
4464 | expr_1 MINUS expr_1
4466 $$
= binary
(Expr_Op_Type_Sub
, $1, $3);
4468 | expr_1 LESS_LESS expr_1
4470 $$
= binary
(Expr_Op_Type_Lshift
, $1, $3);
4472 | expr_1 GREATER_GREATER expr_1
4474 $$
= binary
(Expr_Op_Type_Rshift
, $1, $3);
4476 | expr_1 AMPERSAND expr_1
4478 $$
= binary
(Expr_Op_Type_BAND
, $1, $3);
4480 | expr_1 CARET expr_1
4482 $$
= binary
(Expr_Op_Type_LOR
, $1, $3);
4486 $$
= binary
(Expr_Op_Type_BOR
, $1, $3);
4498 mkexpr
(int x
, SYMBOL_T s
)
4500 EXPR_T e
= (EXPR_T
) ALLOCATE
(sizeof
(struct expression_cell
));
4507 value_match
(Expr_Node
*exp
, int sz
, int sign
, int mul
, int issigned
)
4509 int umax
= (1 << sz
) - 1;
4510 int min
= -1 << (sz
- 1);
4511 int max
= (1 << (sz
- 1)) - 1;
4513 int v
= (EXPR_VALUE
(exp
)) & 0xffffffff;
4517 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__
, __LINE__
, mul
);
4528 if
(v
>= min
&& v
<= max
) return
1;
4531 fprintf
(stderr
, "signed value %lx out of range\n", v
* mul
);
4535 if
(v
<= umax
&& v
>= 0)
4538 fprintf
(stderr
, "unsigned value %lx out of range\n", v
* mul
);
4543 /* Return the expression structure that allows symbol operations.
4544 If the left and right children are constants, do the operation. */
4546 binary
(Expr_Op_Type op
, Expr_Node
*x
, Expr_Node
*y
)
4548 Expr_Node_Value val
;
4550 if
(x
->type
== Expr_Node_Constant
&& y
->type
== Expr_Node_Constant
)
4554 case Expr_Op_Type_Add
:
4555 x
->value.i_value
+= y
->value.i_value
;
4557 case Expr_Op_Type_Sub
:
4558 x
->value.i_value
-= y
->value.i_value
;
4560 case Expr_Op_Type_Mult
:
4561 x
->value.i_value
*= y
->value.i_value
;
4563 case Expr_Op_Type_Div
:
4564 if
(y
->value.i_value
== 0)
4565 error ("Illegal Expression: Division by zero.");
4567 x
->value.i_value
/= y
->value.i_value
;
4569 case Expr_Op_Type_Mod
:
4570 x
->value.i_value %
= y
->value.i_value
;
4572 case Expr_Op_Type_Lshift
:
4573 x
->value.i_value
<<= y
->value.i_value
;
4575 case Expr_Op_Type_Rshift
:
4576 x
->value.i_value
>>= y
->value.i_value
;
4578 case Expr_Op_Type_BAND
:
4579 x
->value.i_value
&= y
->value.i_value
;
4581 case Expr_Op_Type_BOR
:
4582 x
->value.i_value |
= y
->value.i_value
;
4584 case Expr_Op_Type_BXOR
:
4585 x
->value.i_value ^
= y
->value.i_value
;
4587 case Expr_Op_Type_LAND
:
4588 x
->value.i_value
= x
->value.i_value
&& y
->value.i_value
;
4590 case Expr_Op_Type_LOR
:
4591 x
->value.i_value
= x
->value.i_value || y
->value.i_value
;
4595 error ("%s:%d: Internal assembler error\n", __FILE__
, __LINE__
);
4599 /* Canonicalize order to EXPR OP CONSTANT. */
4600 if
(x
->type
== Expr_Node_Constant
)
4606 /* Canonicalize subtraction of const to addition of negated const. */
4607 if
(op
== Expr_Op_Type_Sub
&& y
->type
== Expr_Node_Constant
)
4609 op
= Expr_Op_Type_Add
;
4610 y
->value.i_value
= -y
->value.i_value
;
4612 if
(y
->type
== Expr_Node_Constant
&& x
->type
== Expr_Node_Binop
4613 && x
->Right_Child
->type
== Expr_Node_Constant
)
4615 if
(op
== x
->value.op_value
&& x
->value.op_value
== Expr_Op_Type_Add
)
4617 x
->Right_Child
->value.i_value
+= y
->value.i_value
;
4622 /* Create a new expression structure. */
4624 return Expr_Node_Create
(Expr_Node_Binop
, val
, x
, y
);
4628 unary
(Expr_Op_Type op
, Expr_Node
*x
)
4630 if
(x
->type
== Expr_Node_Constant
)
4634 case Expr_Op_Type_NEG
:
4635 x
->value.i_value
= -x
->value.i_value
;
4637 case Expr_Op_Type_COMP
:
4638 x
->value.i_value
= ~x
->value.i_value
;
4641 error ("%s:%d: Internal assembler error\n", __FILE__
, __LINE__
);
4647 /* Create a new expression structure. */
4648 Expr_Node_Value val
;
4650 return Expr_Node_Create
(Expr_Node_Unop
, val
, x
, NULL
);
4654 int debug_codeselection
= 0;
4656 notethat
(char *format
, ...
)
4659 va_start
(ap
, format
);
4660 if
(debug_codeselection
)
4662 vfprintf
(errorf
, format
, ap
);
4668 main
(int argc
, char **argv
)