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2007-10-19 H.J. Lu <hongjiu.lu@intel.com>
[binutils.git] / opcodes / mips-dis.c
blob186646a5acae67e927cfc30b8e6d78e578bd6ab0
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
63 static const char * const mips_gpr_names_numeric[32] =
64 {
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
69 };
70
71 static const char * const mips_gpr_names_oldabi[32] =
72 {
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
77 };
78
79 static const char * const mips_gpr_names_newabi[32] =
80 {
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85 };
86
87 static const char * const mips_fpr_names_numeric[32] =
88 {
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 };
94
95 static const char * const mips_fpr_names_32[32] =
96 {
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101 };
102
103 static const char * const mips_fpr_names_n32[32] =
104 {
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109 };
110
111 static const char * const mips_fpr_names_64[32] =
112 {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117 };
118
119 static const char * const mips_cp0_names_numeric[32] =
120 {
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125 };
126
127 static const char * const mips_cp0_names_r3000[32] =
128 {
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
137 };
138
139 static const char * const mips_cp0_names_r4000[32] =
140 {
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
149 };
150
151 static const char * const mips_cp0_names_mips3264[32] =
152 {
153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
161 };
162
163 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164 {
165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
194 };
195
196 static const char * const mips_cp0_names_mips3264r2[32] =
197 {
198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
206 };
207
208 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209 {
210 { 4, 1, "c0_contextconfig" },
211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
227 { 5, 1, "c0_pagegrain" },
228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
282 };
283
284 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
285 static const char * const mips_cp0_names_sb1[32] =
286 {
287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
295 };
296
297 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298 {
299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
320 };
321
322 static const char * const mips_hwr_names_numeric[32] =
323 {
324 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
325 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
326 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
327 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
328 };
329
330 static const char * const mips_hwr_names_mips3264r2[32] =
331 {
332 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
333 "$4", "$5", "$6", "$7",
334 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
335 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
336 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
337 };
338
339 struct mips_abi_choice
340 {
341 const char * name;
342 const char * const *gpr_names;
343 const char * const *fpr_names;
344 };
345
346 struct mips_abi_choice mips_abi_choices[] =
347 {
348 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
349 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
350 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
351 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
352 };
353
354 struct mips_arch_choice
355 {
356 const char *name;
357 int bfd_mach_valid;
358 unsigned long bfd_mach;
359 int processor;
360 int isa;
361 const char * const *cp0_names;
362 const struct mips_cp0sel_name *cp0sel_names;
363 unsigned int cp0sel_names_len;
364 const char * const *hwr_names;
365 };
366
367 const struct mips_arch_choice mips_arch_choices[] =
368 {
369 { "numeric", 0, 0, 0, 0,
370 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
371
372 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
373 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
374 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
376 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
377 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
378 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
382 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
384 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
386 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
388 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
389 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
390 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
391 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
392 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
393 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
394 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
395 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
396 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
397 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
398 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
399 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
400 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
401 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
402 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
403 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
404 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
405 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
406 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
407 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
408 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
409 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
410 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
411 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
412 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
413 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
414
415 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
416 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
417 _MIPS32 Architecture For Programmers Volume I: Introduction to the
418 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
419 page 1. */
420 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
421 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
422 mips_cp0_names_mips3264,
423 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
424 mips_hwr_names_numeric },
425
426 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
427 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
428 | INSN_MIPS3D | INSN_MT),
429 mips_cp0_names_mips3264r2,
430 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
431 mips_hwr_names_mips3264r2 },
432
433 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
434 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
435 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
436 mips_cp0_names_mips3264,
437 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
438 mips_hwr_names_numeric },
439
440 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
441 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
442 | INSN_DSP64 | INSN_MT | INSN_MDMX),
443 mips_cp0_names_mips3264r2,
444 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
445 mips_hwr_names_mips3264r2 },
446
447 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
448 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
449 mips_cp0_names_sb1,
450 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
451 mips_hwr_names_numeric },
452
453 /* This entry, mips16, is here only for ISA/processor selection; do
454 not print its name. */
455 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
456 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
457 };
458
459 /* ISA and processor type to disassemble for, and register names to use.
460 set_default_mips_dis_options and parse_mips_dis_options fill in these
461 values. */
462 static int mips_processor;
463 static int mips_isa;
464 static const char * const *mips_gpr_names;
465 static const char * const *mips_fpr_names;
466 static const char * const *mips_cp0_names;
467 static const struct mips_cp0sel_name *mips_cp0sel_names;
468 static int mips_cp0sel_names_len;
469 static const char * const *mips_hwr_names;
470
471 /* Other options */
472 static int no_aliases; /* If set disassemble as most general inst. */
473 \f
474 static const struct mips_abi_choice *
475 choose_abi_by_name (const char *name, unsigned int namelen)
476 {
477 const struct mips_abi_choice *c;
478 unsigned int i;
479
480 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
481 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
482 && strlen (mips_abi_choices[i].name) == namelen)
483 c = &mips_abi_choices[i];
484
485 return c;
486 }
487
488 static const struct mips_arch_choice *
489 choose_arch_by_name (const char *name, unsigned int namelen)
490 {
491 const struct mips_arch_choice *c = NULL;
492 unsigned int i;
493
494 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
495 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
496 && strlen (mips_arch_choices[i].name) == namelen)
497 c = &mips_arch_choices[i];
498
499 return c;
500 }
501
502 static const struct mips_arch_choice *
503 choose_arch_by_number (unsigned long mach)
504 {
505 static unsigned long hint_bfd_mach;
506 static const struct mips_arch_choice *hint_arch_choice;
507 const struct mips_arch_choice *c;
508 unsigned int i;
509
510 /* We optimize this because even if the user specifies no
511 flags, this will be done for every instruction! */
512 if (hint_bfd_mach == mach
513 && hint_arch_choice != NULL
514 && hint_arch_choice->bfd_mach == hint_bfd_mach)
515 return hint_arch_choice;
516
517 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
518 {
519 if (mips_arch_choices[i].bfd_mach_valid
520 && mips_arch_choices[i].bfd_mach == mach)
521 {
522 c = &mips_arch_choices[i];
523 hint_bfd_mach = mach;
524 hint_arch_choice = c;
525 }
526 }
527 return c;
528 }
529
530 /* Check if the object uses NewABI conventions. */
531
532 static int
533 is_newabi (Elf_Internal_Ehdr *header)
534 {
535 /* There are no old-style ABIs which use 64-bit ELF. */
536 if (header->e_ident[EI_CLASS] == ELFCLASS64)
537 return 1;
538
539 /* If a 32-bit ELF file, n32 is a new-style ABI. */
540 if ((header->e_flags & EF_MIPS_ABI2) != 0)
541 return 1;
542
543 return 0;
544 }
545
546 static void
547 set_default_mips_dis_options (struct disassemble_info *info)
548 {
549 const struct mips_arch_choice *chosen_arch;
550
551 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
552 and numeric FPR, CP0 register, and HWR names. */
553 mips_isa = ISA_MIPS3;
554 mips_processor = CPU_R3000;
555 mips_gpr_names = mips_gpr_names_oldabi;
556 mips_fpr_names = mips_fpr_names_numeric;
557 mips_cp0_names = mips_cp0_names_numeric;
558 mips_cp0sel_names = NULL;
559 mips_cp0sel_names_len = 0;
560 mips_hwr_names = mips_hwr_names_numeric;
561 no_aliases = 0;
562
563 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
564 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
565 {
566 Elf_Internal_Ehdr *header;
567
568 header = elf_elfheader (info->section->owner);
569 if (is_newabi (header))
570 mips_gpr_names = mips_gpr_names_newabi;
571 }
572
573 /* Set ISA, architecture, and cp0 register names as best we can. */
574 #if ! SYMTAB_AVAILABLE
575 /* This is running out on a target machine, not in a host tool.
576 FIXME: Where does mips_target_info come from? */
577 target_processor = mips_target_info.processor;
578 mips_isa = mips_target_info.isa;
579 #else
580 chosen_arch = choose_arch_by_number (info->mach);
581 if (chosen_arch != NULL)
582 {
583 mips_processor = chosen_arch->processor;
584 mips_isa = chosen_arch->isa;
585 mips_cp0_names = chosen_arch->cp0_names;
586 mips_cp0sel_names = chosen_arch->cp0sel_names;
587 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
588 mips_hwr_names = chosen_arch->hwr_names;
589 }
590 #endif
591 }
592
593 static void
594 parse_mips_dis_option (const char *option, unsigned int len)
595 {
596 unsigned int i, optionlen, vallen;
597 const char *val;
598 const struct mips_abi_choice *chosen_abi;
599 const struct mips_arch_choice *chosen_arch;
600
601 /* Try to match options that are simple flags */
602 if (CONST_STRNEQ (option, "no-aliases"))
603 {
604 no_aliases = 1;
605 return;
606 }
607
608 /* Look for the = that delimits the end of the option name. */
609 for (i = 0; i < len; i++)
610 if (option[i] == '=')
611 break;
612
613 if (i == 0) /* Invalid option: no name before '='. */
614 return;
615 if (i == len) /* Invalid option: no '='. */
616 return;
617 if (i == (len - 1)) /* Invalid option: no value after '='. */
618 return;
619
620 optionlen = i;
621 val = option + (optionlen + 1);
622 vallen = len - (optionlen + 1);
623
624 if (strncmp ("gpr-names", option, optionlen) == 0
625 && strlen ("gpr-names") == optionlen)
626 {
627 chosen_abi = choose_abi_by_name (val, vallen);
628 if (chosen_abi != NULL)
629 mips_gpr_names = chosen_abi->gpr_names;
630 return;
631 }
632
633 if (strncmp ("fpr-names", option, optionlen) == 0
634 && strlen ("fpr-names") == optionlen)
635 {
636 chosen_abi = choose_abi_by_name (val, vallen);
637 if (chosen_abi != NULL)
638 mips_fpr_names = chosen_abi->fpr_names;
639 return;
640 }
641
642 if (strncmp ("cp0-names", option, optionlen) == 0
643 && strlen ("cp0-names") == optionlen)
644 {
645 chosen_arch = choose_arch_by_name (val, vallen);
646 if (chosen_arch != NULL)
647 {
648 mips_cp0_names = chosen_arch->cp0_names;
649 mips_cp0sel_names = chosen_arch->cp0sel_names;
650 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
651 }
652 return;
653 }
654
655 if (strncmp ("hwr-names", option, optionlen) == 0
656 && strlen ("hwr-names") == optionlen)
657 {
658 chosen_arch = choose_arch_by_name (val, vallen);
659 if (chosen_arch != NULL)
660 mips_hwr_names = chosen_arch->hwr_names;
661 return;
662 }
663
664 if (strncmp ("reg-names", option, optionlen) == 0
665 && strlen ("reg-names") == optionlen)
666 {
667 /* We check both ABI and ARCH here unconditionally, so
668 that "numeric" will do the desirable thing: select
669 numeric register names for all registers. Other than
670 that, a given name probably won't match both. */
671 chosen_abi = choose_abi_by_name (val, vallen);
672 if (chosen_abi != NULL)
673 {
674 mips_gpr_names = chosen_abi->gpr_names;
675 mips_fpr_names = chosen_abi->fpr_names;
676 }
677 chosen_arch = choose_arch_by_name (val, vallen);
678 if (chosen_arch != NULL)
679 {
680 mips_cp0_names = chosen_arch->cp0_names;
681 mips_cp0sel_names = chosen_arch->cp0sel_names;
682 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
683 mips_hwr_names = chosen_arch->hwr_names;
684 }
685 return;
686 }
687
688 /* Invalid option. */
689 }
690
691 static void
692 parse_mips_dis_options (const char *options)
693 {
694 const char *option_end;
695
696 if (options == NULL)
697 return;
698
699 while (*options != '\0')
700 {
701 /* Skip empty options. */
702 if (*options == ',')
703 {
704 options++;
705 continue;
706 }
707
708 /* We know that *options is neither NUL or a comma. */
709 option_end = options + 1;
710 while (*option_end != ',' && *option_end != '\0')
711 option_end++;
712
713 parse_mips_dis_option (options, option_end - options);
714
715 /* Go on to the next one. If option_end points to a comma, it
716 will be skipped above. */
717 options = option_end;
718 }
719 }
720
721 static const struct mips_cp0sel_name *
722 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
723 unsigned int len,
724 unsigned int cp0reg,
725 unsigned int sel)
726 {
727 unsigned int i;
728
729 for (i = 0; i < len; i++)
730 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
731 return &names[i];
732 return NULL;
733 }
734 \f
735 /* Print insn arguments for 32/64-bit code. */
736
737 static void
738 print_insn_args (const char *d,
739 register unsigned long int l,
740 bfd_vma pc,
741 struct disassemble_info *info,
742 const struct mips_opcode *opp)
743 {
744 int op, delta;
745 unsigned int lsb, msb, msbd;
746
747 lsb = 0;
748
749 for (; *d != '\0'; d++)
750 {
751 switch (*d)
752 {
753 case ',':
754 case '(':
755 case ')':
756 case '[':
757 case ']':
758 (*info->fprintf_func) (info->stream, "%c", *d);
759 break;
760
761 case '+':
762 /* Extension character; switch for second char. */
763 d++;
764 switch (*d)
765 {
766 case '\0':
767 /* xgettext:c-format */
768 (*info->fprintf_func) (info->stream,
769 _("# internal error, incomplete extension sequence (+)"));
770 return;
771
772 case 'A':
773 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
774 (*info->fprintf_func) (info->stream, "0x%x", lsb);
775 break;
776
777 case 'B':
778 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
779 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
780 break;
781
782 case '1':
783 (*info->fprintf_func) (info->stream, "0x%lx",
784 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
785 break;
786
787 case '2':
788 (*info->fprintf_func) (info->stream, "0x%lx",
789 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
790 break;
791
792 case '3':
793 (*info->fprintf_func) (info->stream, "0x%lx",
794 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
795 break;
796
797 case '4':
798 (*info->fprintf_func) (info->stream, "0x%lx",
799 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
800 break;
801
802 case 'C':
803 case 'H':
804 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
805 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
806 break;
807
808 case 'D':
809 {
810 const struct mips_cp0sel_name *n;
811 unsigned int cp0reg, sel;
812
813 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
814 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
815
816 /* CP0 register including 'sel' code for mtcN (et al.), to be
817 printed textually if known. If not known, print both
818 CP0 register name and sel numerically since CP0 register
819 with sel 0 may have a name unrelated to register being
820 printed. */
821 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
822 mips_cp0sel_names_len, cp0reg, sel);
823 if (n != NULL)
824 (*info->fprintf_func) (info->stream, "%s", n->name);
825 else
826 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
827 break;
828 }
829
830 case 'E':
831 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
832 (*info->fprintf_func) (info->stream, "0x%x", lsb);
833 break;
834
835 case 'F':
836 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
837 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
838 break;
839
840 case 'G':
841 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
842 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
843 break;
844
845 case 't': /* Coprocessor 0 reg name */
846 (*info->fprintf_func) (info->stream, "%s",
847 mips_cp0_names[(l >> OP_SH_RT) &
848 OP_MASK_RT]);
849 break;
850
851 case 'T': /* Coprocessor 0 reg name */
852 {
853 const struct mips_cp0sel_name *n;
854 unsigned int cp0reg, sel;
855
856 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
857 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
858
859 /* CP0 register including 'sel' code for mftc0, to be
860 printed textually if known. If not known, print both
861 CP0 register name and sel numerically since CP0 register
862 with sel 0 may have a name unrelated to register being
863 printed. */
864 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
865 mips_cp0sel_names_len, cp0reg, sel);
866 if (n != NULL)
867 (*info->fprintf_func) (info->stream, "%s", n->name);
868 else
869 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
870 break;
871 }
872
873 default:
874 /* xgettext:c-format */
875 (*info->fprintf_func) (info->stream,
876 _("# internal error, undefined extension sequence (+%c)"),
877 *d);
878 return;
879 }
880 break;
881
882 case '2':
883 (*info->fprintf_func) (info->stream, "0x%lx",
884 (l >> OP_SH_BP) & OP_MASK_BP);
885 break;
886
887 case '3':
888 (*info->fprintf_func) (info->stream, "0x%lx",
889 (l >> OP_SH_SA3) & OP_MASK_SA3);
890 break;
891
892 case '4':
893 (*info->fprintf_func) (info->stream, "0x%lx",
894 (l >> OP_SH_SA4) & OP_MASK_SA4);
895 break;
896
897 case '5':
898 (*info->fprintf_func) (info->stream, "0x%lx",
899 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
900 break;
901
902 case '6':
903 (*info->fprintf_func) (info->stream, "0x%lx",
904 (l >> OP_SH_RS) & OP_MASK_RS);
905 break;
906
907 case '7':
908 (*info->fprintf_func) (info->stream, "$ac%ld",
909 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
910 break;
911
912 case '8':
913 (*info->fprintf_func) (info->stream, "0x%lx",
914 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
915 break;
916
917 case '9':
918 (*info->fprintf_func) (info->stream, "$ac%ld",
919 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
920 break;
921
922 case '0': /* dsp 6-bit signed immediate in bit 20 */
923 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
924 if (delta & 0x20) /* test sign bit */
925 delta |= ~OP_MASK_DSPSFT;
926 (*info->fprintf_func) (info->stream, "%d", delta);
927 break;
928
929 case ':': /* dsp 7-bit signed immediate in bit 19 */
930 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
931 if (delta & 0x40) /* test sign bit */
932 delta |= ~OP_MASK_DSPSFT_7;
933 (*info->fprintf_func) (info->stream, "%d", delta);
934 break;
935
936 case '\'':
937 (*info->fprintf_func) (info->stream, "0x%lx",
938 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
939 break;
940
941 case '@': /* dsp 10-bit signed immediate in bit 16 */
942 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
943 if (delta & 0x200) /* test sign bit */
944 delta |= ~OP_MASK_IMM10;
945 (*info->fprintf_func) (info->stream, "%d", delta);
946 break;
947
948 case '!':
949 (*info->fprintf_func) (info->stream, "%ld",
950 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
951 break;
952
953 case '$':
954 (*info->fprintf_func) (info->stream, "%ld",
955 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
956 break;
957
958 case '*':
959 (*info->fprintf_func) (info->stream, "$ac%ld",
960 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
961 break;
962
963 case '&':
964 (*info->fprintf_func) (info->stream, "$ac%ld",
965 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
966 break;
967
968 case 'g':
969 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
970 (*info->fprintf_func) (info->stream, "$%ld",
971 (l >> OP_SH_RD) & OP_MASK_RD);
972 break;
973
974 case 's':
975 case 'b':
976 case 'r':
977 case 'v':
978 (*info->fprintf_func) (info->stream, "%s",
979 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
980 break;
981
982 case 't':
983 case 'w':
984 (*info->fprintf_func) (info->stream, "%s",
985 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
986 break;
987
988 case 'i':
989 case 'u':
990 (*info->fprintf_func) (info->stream, "0x%lx",
991 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
992 break;
993
994 case 'j': /* Same as i, but sign-extended. */
995 case 'o':
996 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
997 if (delta & 0x8000)
998 delta |= ~0xffff;
999 (*info->fprintf_func) (info->stream, "%d",
1000 delta);
1001 break;
1002
1003 case 'h':
1004 (*info->fprintf_func) (info->stream, "0x%x",
1005 (unsigned int) ((l >> OP_SH_PREFX)
1006 & OP_MASK_PREFX));
1007 break;
1008
1009 case 'k':
1010 (*info->fprintf_func) (info->stream, "0x%x",
1011 (unsigned int) ((l >> OP_SH_CACHE)
1012 & OP_MASK_CACHE));
1013 break;
1014
1015 case 'a':
1016 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1017 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1018 /* For gdb disassembler, force odd address on jalx. */
1019 if (info->flavour == bfd_target_unknown_flavour
1020 && strcmp (opp->name, "jalx") == 0)
1021 info->target |= 1;
1022 (*info->print_address_func) (info->target, info);
1023 break;
1024
1025 case 'p':
1026 /* Sign extend the displacement. */
1027 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1028 if (delta & 0x8000)
1029 delta |= ~0xffff;
1030 info->target = (delta << 2) + pc + INSNLEN;
1031 (*info->print_address_func) (info->target, info);
1032 break;
1033
1034 case 'd':
1035 (*info->fprintf_func) (info->stream, "%s",
1036 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1037 break;
1038
1039 case 'U':
1040 {
1041 /* First check for both rd and rt being equal. */
1042 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1043 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1044 (*info->fprintf_func) (info->stream, "%s",
1045 mips_gpr_names[reg]);
1046 else
1047 {
1048 /* If one is zero use the other. */
1049 if (reg == 0)
1050 (*info->fprintf_func) (info->stream, "%s",
1051 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1052 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1053 (*info->fprintf_func) (info->stream, "%s",
1054 mips_gpr_names[reg]);
1055 else /* Bogus, result depends on processor. */
1056 (*info->fprintf_func) (info->stream, "%s or %s",
1057 mips_gpr_names[reg],
1058 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1059 }
1060 }
1061 break;
1062
1063 case 'z':
1064 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1065 break;
1066
1067 case '<':
1068 (*info->fprintf_func) (info->stream, "0x%lx",
1069 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1070 break;
1071
1072 case 'c':
1073 (*info->fprintf_func) (info->stream, "0x%lx",
1074 (l >> OP_SH_CODE) & OP_MASK_CODE);
1075 break;
1076
1077 case 'q':
1078 (*info->fprintf_func) (info->stream, "0x%lx",
1079 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1080 break;
1081
1082 case 'C':
1083 (*info->fprintf_func) (info->stream, "0x%lx",
1084 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1085 break;
1086
1087 case 'B':
1088 (*info->fprintf_func) (info->stream, "0x%lx",
1089
1090 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1091 break;
1092
1093 case 'J':
1094 (*info->fprintf_func) (info->stream, "0x%lx",
1095 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1096 break;
1097
1098 case 'S':
1099 case 'V':
1100 (*info->fprintf_func) (info->stream, "%s",
1101 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1102 break;
1103
1104 case 'T':
1105 case 'W':
1106 (*info->fprintf_func) (info->stream, "%s",
1107 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1108 break;
1109
1110 case 'D':
1111 (*info->fprintf_func) (info->stream, "%s",
1112 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1113 break;
1114
1115 case 'R':
1116 (*info->fprintf_func) (info->stream, "%s",
1117 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1118 break;
1119
1120 case 'E':
1121 /* Coprocessor register for lwcN instructions, et al.
1122
1123 Note that there is no load/store cp0 instructions, and
1124 that FPU (cp1) instructions disassemble this field using
1125 'T' format. Therefore, until we gain understanding of
1126 cp2 register names, we can simply print the register
1127 numbers. */
1128 (*info->fprintf_func) (info->stream, "$%ld",
1129 (l >> OP_SH_RT) & OP_MASK_RT);
1130 break;
1131
1132 case 'G':
1133 /* Coprocessor register for mtcN instructions, et al. Note
1134 that FPU (cp1) instructions disassemble this field using
1135 'S' format. Therefore, we only need to worry about cp0,
1136 cp2, and cp3. */
1137 op = (l >> OP_SH_OP) & OP_MASK_OP;
1138 if (op == OP_OP_COP0)
1139 (*info->fprintf_func) (info->stream, "%s",
1140 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1141 else
1142 (*info->fprintf_func) (info->stream, "$%ld",
1143 (l >> OP_SH_RD) & OP_MASK_RD);
1144 break;
1145
1146 case 'K':
1147 (*info->fprintf_func) (info->stream, "%s",
1148 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1149 break;
1150
1151 case 'N':
1152 (*info->fprintf_func) (info->stream,
1153 ((opp->pinfo & (FP_D | FP_S)) != 0
1154 ? "$fcc%ld" : "$cc%ld"),
1155 (l >> OP_SH_BCC) & OP_MASK_BCC);
1156 break;
1157
1158 case 'M':
1159 (*info->fprintf_func) (info->stream, "$fcc%ld",
1160 (l >> OP_SH_CCC) & OP_MASK_CCC);
1161 break;
1162
1163 case 'P':
1164 (*info->fprintf_func) (info->stream, "%ld",
1165 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1166 break;
1167
1168 case 'e':
1169 (*info->fprintf_func) (info->stream, "%ld",
1170 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1171 break;
1172
1173 case '%':
1174 (*info->fprintf_func) (info->stream, "%ld",
1175 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1176 break;
1177
1178 case 'H':
1179 (*info->fprintf_func) (info->stream, "%ld",
1180 (l >> OP_SH_SEL) & OP_MASK_SEL);
1181 break;
1182
1183 case 'O':
1184 (*info->fprintf_func) (info->stream, "%ld",
1185 (l >> OP_SH_ALN) & OP_MASK_ALN);
1186 break;
1187
1188 case 'Q':
1189 {
1190 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1191
1192 if ((vsel & 0x10) == 0)
1193 {
1194 int fmt;
1195
1196 vsel &= 0x0f;
1197 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1198 if ((vsel & 1) == 0)
1199 break;
1200 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1201 (l >> OP_SH_FT) & OP_MASK_FT,
1202 vsel >> 1);
1203 }
1204 else if ((vsel & 0x08) == 0)
1205 {
1206 (*info->fprintf_func) (info->stream, "$v%ld",
1207 (l >> OP_SH_FT) & OP_MASK_FT);
1208 }
1209 else
1210 {
1211 (*info->fprintf_func) (info->stream, "0x%lx",
1212 (l >> OP_SH_FT) & OP_MASK_FT);
1213 }
1214 }
1215 break;
1216
1217 case 'X':
1218 (*info->fprintf_func) (info->stream, "$v%ld",
1219 (l >> OP_SH_FD) & OP_MASK_FD);
1220 break;
1221
1222 case 'Y':
1223 (*info->fprintf_func) (info->stream, "$v%ld",
1224 (l >> OP_SH_FS) & OP_MASK_FS);
1225 break;
1226
1227 case 'Z':
1228 (*info->fprintf_func) (info->stream, "$v%ld",
1229 (l >> OP_SH_FT) & OP_MASK_FT);
1230 break;
1231
1232 default:
1233 /* xgettext:c-format */
1234 (*info->fprintf_func) (info->stream,
1235 _("# internal error, undefined modifier (%c)"),
1236 *d);
1237 return;
1238 }
1239 }
1240 }
1241 \f
1242 /* Print the mips instruction at address MEMADDR in debugged memory,
1243 on using INFO. Returns length of the instruction, in bytes, which is
1244 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1245 this is little-endian code. */
1246
1247 static int
1248 print_insn_mips (bfd_vma memaddr,
1249 unsigned long int word,
1250 struct disassemble_info *info)
1251 {
1252 const struct mips_opcode *op;
1253 static bfd_boolean init = 0;
1254 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1255
1256 /* Build a hash table to shorten the search time. */
1257 if (! init)
1258 {
1259 unsigned int i;
1260
1261 for (i = 0; i <= OP_MASK_OP; i++)
1262 {
1263 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1264 {
1265 if (op->pinfo == INSN_MACRO
1266 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1267 continue;
1268 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1269 {
1270 mips_hash[i] = op;
1271 break;
1272 }
1273 }
1274 }
1275
1276 init = 1;
1277 }
1278
1279 info->bytes_per_chunk = INSNLEN;
1280 info->display_endian = info->endian;
1281 info->insn_info_valid = 1;
1282 info->branch_delay_insns = 0;
1283 info->data_size = 0;
1284 info->insn_type = dis_nonbranch;
1285 info->target = 0;
1286 info->target2 = 0;
1287
1288 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1289 if (op != NULL)
1290 {
1291 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1292 {
1293 if (op->pinfo != INSN_MACRO
1294 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1295 && (word & op->mask) == op->match)
1296 {
1297 const char *d;
1298
1299 /* We always allow to disassemble the jalx instruction. */
1300 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1301 && strcmp (op->name, "jalx"))
1302 continue;
1303
1304 /* Figure out instruction type and branch delay information. */
1305 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1306 {
1307 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1308 info->insn_type = dis_jsr;
1309 else
1310 info->insn_type = dis_branch;
1311 info->branch_delay_insns = 1;
1312 }
1313 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1314 | INSN_COND_BRANCH_LIKELY)) != 0)
1315 {
1316 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1317 info->insn_type = dis_condjsr;
1318 else
1319 info->insn_type = dis_condbranch;
1320 info->branch_delay_insns = 1;
1321 }
1322 else if ((op->pinfo & (INSN_STORE_MEMORY
1323 | INSN_LOAD_MEMORY_DELAY)) != 0)
1324 info->insn_type = dis_dref;
1325
1326 (*info->fprintf_func) (info->stream, "%s", op->name);
1327
1328 d = op->args;
1329 if (d != NULL && *d != '\0')
1330 {
1331 (*info->fprintf_func) (info->stream, "\t");
1332 print_insn_args (d, word, memaddr, info, op);
1333 }
1334
1335 return INSNLEN;
1336 }
1337 }
1338 }
1339
1340 /* Handle undefined instructions. */
1341 info->insn_type = dis_noninsn;
1342 (*info->fprintf_func) (info->stream, "0x%lx", word);
1343 return INSNLEN;
1344 }
1345 \f
1346 /* Disassemble an operand for a mips16 instruction. */
1347
1348 static void
1349 print_mips16_insn_arg (char type,
1350 const struct mips_opcode *op,
1351 int l,
1352 bfd_boolean use_extend,
1353 int extend,
1354 bfd_vma memaddr,
1355 struct disassemble_info *info)
1356 {
1357 switch (type)
1358 {
1359 case ',':
1360 case '(':
1361 case ')':
1362 (*info->fprintf_func) (info->stream, "%c", type);
1363 break;
1364
1365 case 'y':
1366 case 'w':
1367 (*info->fprintf_func) (info->stream, "%s",
1368 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1369 & MIPS16OP_MASK_RY)));
1370 break;
1371
1372 case 'x':
1373 case 'v':
1374 (*info->fprintf_func) (info->stream, "%s",
1375 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1376 & MIPS16OP_MASK_RX)));
1377 break;
1378
1379 case 'z':
1380 (*info->fprintf_func) (info->stream, "%s",
1381 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1382 & MIPS16OP_MASK_RZ)));
1383 break;
1384
1385 case 'Z':
1386 (*info->fprintf_func) (info->stream, "%s",
1387 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1388 & MIPS16OP_MASK_MOVE32Z)));
1389 break;
1390
1391 case '0':
1392 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1393 break;
1394
1395 case 'S':
1396 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1397 break;
1398
1399 case 'P':
1400 (*info->fprintf_func) (info->stream, "$pc");
1401 break;
1402
1403 case 'R':
1404 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1405 break;
1406
1407 case 'X':
1408 (*info->fprintf_func) (info->stream, "%s",
1409 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1410 & MIPS16OP_MASK_REGR32)]);
1411 break;
1412
1413 case 'Y':
1414 (*info->fprintf_func) (info->stream, "%s",
1415 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1416 break;
1417
1418 case '<':
1419 case '>':
1420 case '[':
1421 case ']':
1422 case '4':
1423 case '5':
1424 case 'H':
1425 case 'W':
1426 case 'D':
1427 case 'j':
1428 case '6':
1429 case '8':
1430 case 'V':
1431 case 'C':
1432 case 'U':
1433 case 'k':
1434 case 'K':
1435 case 'p':
1436 case 'q':
1437 case 'A':
1438 case 'B':
1439 case 'E':
1440 {
1441 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1442
1443 shift = 0;
1444 signedp = 0;
1445 extbits = 16;
1446 pcrel = 0;
1447 extu = 0;
1448 branch = 0;
1449 switch (type)
1450 {
1451 case '<':
1452 nbits = 3;
1453 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1454 extbits = 5;
1455 extu = 1;
1456 break;
1457 case '>':
1458 nbits = 3;
1459 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1460 extbits = 5;
1461 extu = 1;
1462 break;
1463 case '[':
1464 nbits = 3;
1465 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1466 extbits = 6;
1467 extu = 1;
1468 break;
1469 case ']':
1470 nbits = 3;
1471 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1472 extbits = 6;
1473 extu = 1;
1474 break;
1475 case '4':
1476 nbits = 4;
1477 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1478 signedp = 1;
1479 extbits = 15;
1480 break;
1481 case '5':
1482 nbits = 5;
1483 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1484 info->insn_type = dis_dref;
1485 info->data_size = 1;
1486 break;
1487 case 'H':
1488 nbits = 5;
1489 shift = 1;
1490 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1491 info->insn_type = dis_dref;
1492 info->data_size = 2;
1493 break;
1494 case 'W':
1495 nbits = 5;
1496 shift = 2;
1497 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1498 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1499 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1500 {
1501 info->insn_type = dis_dref;
1502 info->data_size = 4;
1503 }
1504 break;
1505 case 'D':
1506 nbits = 5;
1507 shift = 3;
1508 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1509 info->insn_type = dis_dref;
1510 info->data_size = 8;
1511 break;
1512 case 'j':
1513 nbits = 5;
1514 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1515 signedp = 1;
1516 break;
1517 case '6':
1518 nbits = 6;
1519 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1520 break;
1521 case '8':
1522 nbits = 8;
1523 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1524 break;
1525 case 'V':
1526 nbits = 8;
1527 shift = 2;
1528 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1529 /* FIXME: This might be lw, or it might be addiu to $sp or
1530 $pc. We assume it's load. */
1531 info->insn_type = dis_dref;
1532 info->data_size = 4;
1533 break;
1534 case 'C':
1535 nbits = 8;
1536 shift = 3;
1537 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1538 info->insn_type = dis_dref;
1539 info->data_size = 8;
1540 break;
1541 case 'U':
1542 nbits = 8;
1543 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1544 extu = 1;
1545 break;
1546 case 'k':
1547 nbits = 8;
1548 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1549 signedp = 1;
1550 break;
1551 case 'K':
1552 nbits = 8;
1553 shift = 3;
1554 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1555 signedp = 1;
1556 break;
1557 case 'p':
1558 nbits = 8;
1559 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1560 signedp = 1;
1561 pcrel = 1;
1562 branch = 1;
1563 info->insn_type = dis_condbranch;
1564 break;
1565 case 'q':
1566 nbits = 11;
1567 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1568 signedp = 1;
1569 pcrel = 1;
1570 branch = 1;
1571 info->insn_type = dis_branch;
1572 break;
1573 case 'A':
1574 nbits = 8;
1575 shift = 2;
1576 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1577 pcrel = 1;
1578 /* FIXME: This can be lw or la. We assume it is lw. */
1579 info->insn_type = dis_dref;
1580 info->data_size = 4;
1581 break;
1582 case 'B':
1583 nbits = 5;
1584 shift = 3;
1585 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1586 pcrel = 1;
1587 info->insn_type = dis_dref;
1588 info->data_size = 8;
1589 break;
1590 case 'E':
1591 nbits = 5;
1592 shift = 2;
1593 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1594 pcrel = 1;
1595 break;
1596 default:
1597 abort ();
1598 }
1599
1600 if (! use_extend)
1601 {
1602 if (signedp && immed >= (1 << (nbits - 1)))
1603 immed -= 1 << nbits;
1604 immed <<= shift;
1605 if ((type == '<' || type == '>' || type == '[' || type == ']')
1606 && immed == 0)
1607 immed = 8;
1608 }
1609 else
1610 {
1611 if (extbits == 16)
1612 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1613 else if (extbits == 15)
1614 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1615 else
1616 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1617 immed &= (1 << extbits) - 1;
1618 if (! extu && immed >= (1 << (extbits - 1)))
1619 immed -= 1 << extbits;
1620 }
1621
1622 if (! pcrel)
1623 (*info->fprintf_func) (info->stream, "%d", immed);
1624 else
1625 {
1626 bfd_vma baseaddr;
1627
1628 if (branch)
1629 {
1630 immed *= 2;
1631 baseaddr = memaddr + 2;
1632 }
1633 else if (use_extend)
1634 baseaddr = memaddr - 2;
1635 else
1636 {
1637 int status;
1638 bfd_byte buffer[2];
1639
1640 baseaddr = memaddr;
1641
1642 /* If this instruction is in the delay slot of a jr
1643 instruction, the base address is the address of the
1644 jr instruction. If it is in the delay slot of jalr
1645 instruction, the base address is the address of the
1646 jalr instruction. This test is unreliable: we have
1647 no way of knowing whether the previous word is
1648 instruction or data. */
1649 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1650 info);
1651 if (status == 0
1652 && (((info->endian == BFD_ENDIAN_BIG
1653 ? bfd_getb16 (buffer)
1654 : bfd_getl16 (buffer))
1655 & 0xf800) == 0x1800))
1656 baseaddr = memaddr - 4;
1657 else
1658 {
1659 status = (*info->read_memory_func) (memaddr - 2, buffer,
1660 2, info);
1661 if (status == 0
1662 && (((info->endian == BFD_ENDIAN_BIG
1663 ? bfd_getb16 (buffer)
1664 : bfd_getl16 (buffer))
1665 & 0xf81f) == 0xe800))
1666 baseaddr = memaddr - 2;
1667 }
1668 }
1669 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1670 if (pcrel && branch
1671 && info->flavour == bfd_target_unknown_flavour)
1672 /* For gdb disassembler, maintain odd address. */
1673 info->target |= 1;
1674 (*info->print_address_func) (info->target, info);
1675 }
1676 }
1677 break;
1678
1679 case 'a':
1680 {
1681 int jalx = l & 0x400;
1682
1683 if (! use_extend)
1684 extend = 0;
1685 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1686 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1687 /* For gdb disassembler, maintain odd address. */
1688 l |= 1;
1689 }
1690 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1691 (*info->print_address_func) (info->target, info);
1692 info->insn_type = dis_jsr;
1693 info->branch_delay_insns = 1;
1694 break;
1695
1696 case 'l':
1697 case 'L':
1698 {
1699 int need_comma, amask, smask;
1700
1701 need_comma = 0;
1702
1703 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1704
1705 amask = (l >> 3) & 7;
1706
1707 if (amask > 0 && amask < 5)
1708 {
1709 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1710 if (amask > 1)
1711 (*info->fprintf_func) (info->stream, "-%s",
1712 mips_gpr_names[amask + 3]);
1713 need_comma = 1;
1714 }
1715
1716 smask = (l >> 1) & 3;
1717 if (smask == 3)
1718 {
1719 (*info->fprintf_func) (info->stream, "%s??",
1720 need_comma ? "," : "");
1721 need_comma = 1;
1722 }
1723 else if (smask > 0)
1724 {
1725 (*info->fprintf_func) (info->stream, "%s%s",
1726 need_comma ? "," : "",
1727 mips_gpr_names[16]);
1728 if (smask > 1)
1729 (*info->fprintf_func) (info->stream, "-%s",
1730 mips_gpr_names[smask + 15]);
1731 need_comma = 1;
1732 }
1733
1734 if (l & 1)
1735 {
1736 (*info->fprintf_func) (info->stream, "%s%s",
1737 need_comma ? "," : "",
1738 mips_gpr_names[31]);
1739 need_comma = 1;
1740 }
1741
1742 if (amask == 5 || amask == 6)
1743 {
1744 (*info->fprintf_func) (info->stream, "%s$f0",
1745 need_comma ? "," : "");
1746 if (amask == 6)
1747 (*info->fprintf_func) (info->stream, "-$f1");
1748 }
1749 }
1750 break;
1751
1752 case 'm':
1753 case 'M':
1754 /* MIPS16e save/restore. */
1755 {
1756 int need_comma = 0;
1757 int amask, args, statics;
1758 int nsreg, smask;
1759 int framesz;
1760 int i, j;
1761
1762 l = l & 0x7f;
1763 if (use_extend)
1764 l |= extend << 16;
1765
1766 amask = (l >> 16) & 0xf;
1767 if (amask == MIPS16_ALL_ARGS)
1768 {
1769 args = 4;
1770 statics = 0;
1771 }
1772 else if (amask == MIPS16_ALL_STATICS)
1773 {
1774 args = 0;
1775 statics = 4;
1776 }
1777 else
1778 {
1779 args = amask >> 2;
1780 statics = amask & 3;
1781 }
1782
1783 if (args > 0) {
1784 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1785 if (args > 1)
1786 (*info->fprintf_func) (info->stream, "-%s",
1787 mips_gpr_names[4 + args - 1]);
1788 need_comma = 1;
1789 }
1790
1791 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1792 if (framesz == 0 && !use_extend)
1793 framesz = 128;
1794
1795 (*info->fprintf_func) (info->stream, "%s%d",
1796 need_comma ? "," : "",
1797 framesz);
1798
1799 if (l & 0x40) /* $ra */
1800 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1801
1802 nsreg = (l >> 24) & 0x7;
1803 smask = 0;
1804 if (l & 0x20) /* $s0 */
1805 smask |= 1 << 0;
1806 if (l & 0x10) /* $s1 */
1807 smask |= 1 << 1;
1808 if (nsreg > 0) /* $s2-$s8 */
1809 smask |= ((1 << nsreg) - 1) << 2;
1810
1811 /* Find first set static reg bit. */
1812 for (i = 0; i < 9; i++)
1813 {
1814 if (smask & (1 << i))
1815 {
1816 (*info->fprintf_func) (info->stream, ",%s",
1817 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1818 /* Skip over string of set bits. */
1819 for (j = i; smask & (2 << j); j++)
1820 continue;
1821 if (j > i)
1822 (*info->fprintf_func) (info->stream, "-%s",
1823 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1824 i = j + 1;
1825 }
1826 }
1827
1828 /* Statics $ax - $a3. */
1829 if (statics == 1)
1830 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1831 else if (statics > 0)
1832 (*info->fprintf_func) (info->stream, ",%s-%s",
1833 mips_gpr_names[7 - statics + 1],
1834 mips_gpr_names[7]);
1835 }
1836 break;
1837
1838 default:
1839 /* xgettext:c-format */
1840 (*info->fprintf_func)
1841 (info->stream,
1842 _("# internal disassembler error, unrecognised modifier (%c)"),
1843 type);
1844 abort ();
1845 }
1846 }
1847
1848 /* Disassemble mips16 instructions. */
1849
1850 static int
1851 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1852 {
1853 int status;
1854 bfd_byte buffer[2];
1855 int length;
1856 int insn;
1857 bfd_boolean use_extend;
1858 int extend = 0;
1859 const struct mips_opcode *op, *opend;
1860
1861 info->bytes_per_chunk = 2;
1862 info->display_endian = info->endian;
1863 info->insn_info_valid = 1;
1864 info->branch_delay_insns = 0;
1865 info->data_size = 0;
1866 info->insn_type = dis_nonbranch;
1867 info->target = 0;
1868 info->target2 = 0;
1869
1870 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1871 if (status != 0)
1872 {
1873 (*info->memory_error_func) (status, memaddr, info);
1874 return -1;
1875 }
1876
1877 length = 2;
1878
1879 if (info->endian == BFD_ENDIAN_BIG)
1880 insn = bfd_getb16 (buffer);
1881 else
1882 insn = bfd_getl16 (buffer);
1883
1884 /* Handle the extend opcode specially. */
1885 use_extend = FALSE;
1886 if ((insn & 0xf800) == 0xf000)
1887 {
1888 use_extend = TRUE;
1889 extend = insn & 0x7ff;
1890
1891 memaddr += 2;
1892
1893 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1894 if (status != 0)
1895 {
1896 (*info->fprintf_func) (info->stream, "extend 0x%x",
1897 (unsigned int) extend);
1898 (*info->memory_error_func) (status, memaddr, info);
1899 return -1;
1900 }
1901
1902 if (info->endian == BFD_ENDIAN_BIG)
1903 insn = bfd_getb16 (buffer);
1904 else
1905 insn = bfd_getl16 (buffer);
1906
1907 /* Check for an extend opcode followed by an extend opcode. */
1908 if ((insn & 0xf800) == 0xf000)
1909 {
1910 (*info->fprintf_func) (info->stream, "extend 0x%x",
1911 (unsigned int) extend);
1912 info->insn_type = dis_noninsn;
1913 return length;
1914 }
1915
1916 length += 2;
1917 }
1918
1919 /* FIXME: Should probably use a hash table on the major opcode here. */
1920
1921 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1922 for (op = mips16_opcodes; op < opend; op++)
1923 {
1924 if (op->pinfo != INSN_MACRO
1925 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1926 && (insn & op->mask) == op->match)
1927 {
1928 const char *s;
1929
1930 if (strchr (op->args, 'a') != NULL)
1931 {
1932 if (use_extend)
1933 {
1934 (*info->fprintf_func) (info->stream, "extend 0x%x",
1935 (unsigned int) extend);
1936 info->insn_type = dis_noninsn;
1937 return length - 2;
1938 }
1939
1940 use_extend = FALSE;
1941
1942 memaddr += 2;
1943
1944 status = (*info->read_memory_func) (memaddr, buffer, 2,
1945 info);
1946 if (status == 0)
1947 {
1948 use_extend = TRUE;
1949 if (info->endian == BFD_ENDIAN_BIG)
1950 extend = bfd_getb16 (buffer);
1951 else
1952 extend = bfd_getl16 (buffer);
1953 length += 2;
1954 }
1955 }
1956
1957 (*info->fprintf_func) (info->stream, "%s", op->name);
1958 if (op->args[0] != '\0')
1959 (*info->fprintf_func) (info->stream, "\t");
1960
1961 for (s = op->args; *s != '\0'; s++)
1962 {
1963 if (*s == ','
1964 && s[1] == 'w'
1965 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1966 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1967 {
1968 /* Skip the register and the comma. */
1969 ++s;
1970 continue;
1971 }
1972 if (*s == ','
1973 && s[1] == 'v'
1974 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1975 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1976 {
1977 /* Skip the register and the comma. */
1978 ++s;
1979 continue;
1980 }
1981 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1982 info);
1983 }
1984
1985 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1986 {
1987 info->branch_delay_insns = 1;
1988 if (info->insn_type != dis_jsr)
1989 info->insn_type = dis_branch;
1990 }
1991
1992 return length;
1993 }
1994 }
1995
1996 if (use_extend)
1997 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1998 (*info->fprintf_func) (info->stream, "0x%x", insn);
1999 info->insn_type = dis_noninsn;
2000
2001 return length;
2002 }
2003
2004 /* In an environment where we do not know the symbol type of the
2005 instruction we are forced to assume that the low order bit of the
2006 instructions' address may mark it as a mips16 instruction. If we
2007 are single stepping, or the pc is within the disassembled function,
2008 this works. Otherwise, we need a clue. Sometimes. */
2009
2010 static int
2011 _print_insn_mips (bfd_vma memaddr,
2012 struct disassemble_info *info,
2013 enum bfd_endian endianness)
2014 {
2015 bfd_byte buffer[INSNLEN];
2016 int status;
2017
2018 set_default_mips_dis_options (info);
2019 parse_mips_dis_options (info->disassembler_options);
2020
2021 #if 1
2022 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2023 /* Only a few tools will work this way. */
2024 if (memaddr & 0x01)
2025 return print_insn_mips16 (memaddr, info);
2026 #endif
2027
2028 #if SYMTAB_AVAILABLE
2029 if (info->mach == bfd_mach_mips16
2030 || (info->flavour == bfd_target_elf_flavour
2031 && info->symbols != NULL
2032 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
2033 == STO_MIPS16)))
2034 return print_insn_mips16 (memaddr, info);
2035 #endif
2036
2037 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2038 if (status == 0)
2039 {
2040 unsigned long insn;
2041
2042 if (endianness == BFD_ENDIAN_BIG)
2043 insn = (unsigned long) bfd_getb32 (buffer);
2044 else
2045 insn = (unsigned long) bfd_getl32 (buffer);
2046
2047 return print_insn_mips (memaddr, insn, info);
2048 }
2049 else
2050 {
2051 (*info->memory_error_func) (status, memaddr, info);
2052 return -1;
2053 }
2054 }
2055
2056 int
2057 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2058 {
2059 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2060 }
2061
2062 int
2063 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2064 {
2065 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2066 }
2067 \f
2068 void
2069 print_mips_disassembler_options (FILE *stream)
2070 {
2071 unsigned int i;
2072
2073 fprintf (stream, _("\n\
2074 The following MIPS specific disassembler options are supported for use\n\
2075 with the -M switch (multiple options should be separated by commas):\n"));
2076
2077 fprintf (stream, _("\n\
2078 gpr-names=ABI Print GPR names according to specified ABI.\n\
2079 Default: based on binary being disassembled.\n"));
2080
2081 fprintf (stream, _("\n\
2082 fpr-names=ABI Print FPR names according to specified ABI.\n\
2083 Default: numeric.\n"));
2084
2085 fprintf (stream, _("\n\
2086 cp0-names=ARCH Print CP0 register names according to\n\
2087 specified architecture.\n\
2088 Default: based on binary being disassembled.\n"));
2089
2090 fprintf (stream, _("\n\
2091 hwr-names=ARCH Print HWR names according to specified \n\
2092 architecture.\n\
2093 Default: based on binary being disassembled.\n"));
2094
2095 fprintf (stream, _("\n\
2096 reg-names=ABI Print GPR and FPR names according to\n\
2097 specified ABI.\n"));
2098
2099 fprintf (stream, _("\n\
2100 reg-names=ARCH Print CP0 register and HWR names according to\n\
2101 specified architecture.\n"));
2102
2103 fprintf (stream, _("\n\
2104 For the options above, the following values are supported for \"ABI\":\n\
2105 "));
2106 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2107 fprintf (stream, " %s", mips_abi_choices[i].name);
2108 fprintf (stream, _("\n"));
2109
2110 fprintf (stream, _("\n\
2111 For the options above, The following values are supported for \"ARCH\":\n\
2112 "));
2113 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2114 if (*mips_arch_choices[i].name != '\0')
2115 fprintf (stream, " %s", mips_arch_choices[i].name);
2116 fprintf (stream, _("\n"));
2117
2118 fprintf (stream, _("\n"));
2119 }
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