1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma
, disassemble_info
*);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma
);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma
);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma
get64 (void);
60 static bfd_signed_vma
get32 (void);
61 static bfd_signed_vma
get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma
, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void CMPXCHG8B_Fixup (int, int);
112 static void XMM_Fixup (int, int);
113 static void CRC32_Fixup (int, int);
114 static void FXSAVE_Fixup (int, int);
115 static void OP_LWPCB_E (int, int);
116 static void OP_LWP_E (int, int);
117 static void OP_Vex_2src_1 (int, int);
118 static void OP_Vex_2src_2 (int, int);
120 static void MOVBE_Fixup (int, int);
123 /* Points to first byte not fetched. */
124 bfd_byte
*max_fetched
;
125 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 enum address_mode address_mode
;
140 /* Flags for the prefixes for the current instruction. See below. */
143 /* REX prefix the current instruction. See below. */
145 /* Bits of REX we've already used. */
147 /* REX bits in original REX prefix ignored. */
148 static int rex_ignored
;
149 /* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153 #define USED_REX(value) \
158 rex_used |= (value) | REX_OPCODE; \
161 rex_used |= REX_OPCODE; \
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes
;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
193 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
194 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
196 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
197 status
= (*info
->read_memory_func
) (start
,
199 addr
- priv
->max_fetched
,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv
->max_fetched
== priv
->the_buffer
)
210 (*info
->memory_error_func
) (status
, start
, info
);
211 longjmp (priv
->bailout
, 1);
214 priv
->max_fetched
= addr
;
218 #define XX { NULL, 0 }
219 #define Bad_Opcode NULL, { { NULL, 0 } }
221 #define Eb { OP_E, b_mode }
222 #define EbS { OP_E, b_swap_mode }
223 #define Ev { OP_E, v_mode }
224 #define EvS { OP_E, v_swap_mode }
225 #define Ed { OP_E, d_mode }
226 #define Edq { OP_E, dq_mode }
227 #define Edqw { OP_E, dqw_mode }
228 #define Edqb { OP_E, dqb_mode }
229 #define Edqd { OP_E, dqd_mode }
230 #define Eq { OP_E, q_mode }
231 #define indirEv { OP_indirE, stack_v_mode }
232 #define indirEp { OP_indirE, f_mode }
233 #define stackEv { OP_E, stack_v_mode }
234 #define Em { OP_E, m_mode }
235 #define Ew { OP_E, w_mode }
236 #define M { OP_M, 0 } /* lea, lgdt, etc. */
237 #define Ma { OP_M, a_mode }
238 #define Mb { OP_M, b_mode }
239 #define Md { OP_M, d_mode }
240 #define Mo { OP_M, o_mode }
241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242 #define Mq { OP_M, q_mode }
243 #define Mx { OP_M, x_mode }
244 #define Mxmm { OP_M, xmm_mode }
245 #define Gb { OP_G, b_mode }
246 #define Gv { OP_G, v_mode }
247 #define Gd { OP_G, d_mode }
248 #define Gdq { OP_G, dq_mode }
249 #define Gm { OP_G, m_mode }
250 #define Gw { OP_G, w_mode }
251 #define Rd { OP_R, d_mode }
252 #define Rm { OP_R, m_mode }
253 #define Ib { OP_I, b_mode }
254 #define sIb { OP_sI, b_mode } /* sign extened byte */
255 #define Iv { OP_I, v_mode }
256 #define sIv { OP_sI, v_mode }
257 #define Iq { OP_I, q_mode }
258 #define Iv64 { OP_I64, v_mode }
259 #define Iw { OP_I, w_mode }
260 #define I1 { OP_I, const_1_mode }
261 #define Jb { OP_J, b_mode }
262 #define Jv { OP_J, v_mode }
263 #define Cm { OP_C, m_mode }
264 #define Dm { OP_D, m_mode }
265 #define Td { OP_T, d_mode }
266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
268 #define RMeAX { OP_REG, eAX_reg }
269 #define RMeBX { OP_REG, eBX_reg }
270 #define RMeCX { OP_REG, eCX_reg }
271 #define RMeDX { OP_REG, eDX_reg }
272 #define RMeSP { OP_REG, eSP_reg }
273 #define RMeBP { OP_REG, eBP_reg }
274 #define RMeSI { OP_REG, eSI_reg }
275 #define RMeDI { OP_REG, eDI_reg }
276 #define RMrAX { OP_REG, rAX_reg }
277 #define RMrBX { OP_REG, rBX_reg }
278 #define RMrCX { OP_REG, rCX_reg }
279 #define RMrDX { OP_REG, rDX_reg }
280 #define RMrSP { OP_REG, rSP_reg }
281 #define RMrBP { OP_REG, rBP_reg }
282 #define RMrSI { OP_REG, rSI_reg }
283 #define RMrDI { OP_REG, rDI_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMCL { OP_REG, cl_reg }
286 #define RMDL { OP_REG, dl_reg }
287 #define RMBL { OP_REG, bl_reg }
288 #define RMAH { OP_REG, ah_reg }
289 #define RMCH { OP_REG, ch_reg }
290 #define RMDH { OP_REG, dh_reg }
291 #define RMBH { OP_REG, bh_reg }
292 #define RMAX { OP_REG, ax_reg }
293 #define RMDX { OP_REG, dx_reg }
295 #define eAX { OP_IMREG, eAX_reg }
296 #define eBX { OP_IMREG, eBX_reg }
297 #define eCX { OP_IMREG, eCX_reg }
298 #define eDX { OP_IMREG, eDX_reg }
299 #define eSP { OP_IMREG, eSP_reg }
300 #define eBP { OP_IMREG, eBP_reg }
301 #define eSI { OP_IMREG, eSI_reg }
302 #define eDI { OP_IMREG, eDI_reg }
303 #define AL { OP_IMREG, al_reg }
304 #define CL { OP_IMREG, cl_reg }
305 #define DL { OP_IMREG, dl_reg }
306 #define BL { OP_IMREG, bl_reg }
307 #define AH { OP_IMREG, ah_reg }
308 #define CH { OP_IMREG, ch_reg }
309 #define DH { OP_IMREG, dh_reg }
310 #define BH { OP_IMREG, bh_reg }
311 #define AX { OP_IMREG, ax_reg }
312 #define DX { OP_IMREG, dx_reg }
313 #define zAX { OP_IMREG, z_mode_ax_reg }
314 #define indirDX { OP_IMREG, indir_dx_reg }
316 #define Sw { OP_SEG, w_mode }
317 #define Sv { OP_SEG, v_mode }
318 #define Ap { OP_DIR, 0 }
319 #define Ob { OP_OFF64, b_mode }
320 #define Ov { OP_OFF64, v_mode }
321 #define Xb { OP_DSreg, eSI_reg }
322 #define Xv { OP_DSreg, eSI_reg }
323 #define Xz { OP_DSreg, eSI_reg }
324 #define Yb { OP_ESreg, eDI_reg }
325 #define Yv { OP_ESreg, eDI_reg }
326 #define DSBX { OP_DSreg, eBX_reg }
328 #define es { OP_REG, es_reg }
329 #define ss { OP_REG, ss_reg }
330 #define cs { OP_REG, cs_reg }
331 #define ds { OP_REG, ds_reg }
332 #define fs { OP_REG, fs_reg }
333 #define gs { OP_REG, gs_reg }
335 #define MX { OP_MMX, 0 }
336 #define XM { OP_XMM, 0 }
337 #define XMScalar { OP_XMM, scalar_mode }
338 #define XMM { OP_XMM, xmm_mode }
339 #define EM { OP_EM, v_mode }
340 #define EMS { OP_EM, v_swap_mode }
341 #define EMd { OP_EM, d_mode }
342 #define EMx { OP_EM, x_mode }
343 #define EXw { OP_EX, w_mode }
344 #define EXd { OP_EX, d_mode }
345 #define EXdScalar { OP_EX, d_scalar_mode }
346 #define EXdS { OP_EX, d_swap_mode }
347 #define EXq { OP_EX, q_mode }
348 #define EXqScalar { OP_EX, q_scalar_mode }
349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
350 #define EXqS { OP_EX, q_swap_mode }
351 #define EXx { OP_EX, x_mode }
352 #define EXxS { OP_EX, x_swap_mode }
353 #define EXxmm { OP_EX, xmm_mode }
354 #define EXxmmq { OP_EX, xmmq_mode }
355 #define EXymmq { OP_EX, ymmq_mode }
356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
358 #define MS { OP_MS, v_mode }
359 #define XS { OP_XS, v_mode }
360 #define EMCq { OP_EMC, q_mode }
361 #define MXC { OP_MXC, 0 }
362 #define OPSUF { OP_3DNowSuffix, 0 }
363 #define CMP { CMP_Fixup, 0 }
364 #define XMM0 { XMM_Fixup, 0 }
365 #define FXSAVE { FXSAVE_Fixup, 0 }
366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
369 #define Vex { OP_VEX, vex_mode }
370 #define VexScalar { OP_VEX, vex_scalar_mode }
371 #define Vex128 { OP_VEX, vex128_mode }
372 #define Vex256 { OP_VEX, vex256_mode }
373 #define VexGdq { OP_VEX, dq_mode }
374 #define VexI4 { VEXI4_Fixup, 0}
375 #define EXdVex { OP_EX_Vex, d_mode }
376 #define EXdVexS { OP_EX_Vex, d_swap_mode }
377 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
378 #define EXqVex { OP_EX_Vex, q_mode }
379 #define EXqVexS { OP_EX_Vex, q_swap_mode }
380 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
381 #define EXVexW { OP_EX_VexW, x_mode }
382 #define EXdVexW { OP_EX_VexW, d_mode }
383 #define EXqVexW { OP_EX_VexW, q_mode }
384 #define EXVexImmW { OP_EX_VexImmW, x_mode }
385 #define XMVex { OP_XMM_Vex, 0 }
386 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
387 #define XMVexW { OP_XMM_VexW, 0 }
388 #define XMVexI4 { OP_REG_VexI4, x_mode }
389 #define PCLMUL { PCLMUL_Fixup, 0 }
390 #define VZERO { VZERO_Fixup, 0 }
391 #define VCMP { VCMP_Fixup, 0 }
393 /* Used handle "rep" prefix for string instructions. */
394 #define Xbr { REP_Fixup, eSI_reg }
395 #define Xvr { REP_Fixup, eSI_reg }
396 #define Ybr { REP_Fixup, eDI_reg }
397 #define Yvr { REP_Fixup, eDI_reg }
398 #define Yzr { REP_Fixup, eDI_reg }
399 #define indirDXr { REP_Fixup, indir_dx_reg }
400 #define ALr { REP_Fixup, al_reg }
401 #define eAXr { REP_Fixup, eAX_reg }
403 #define cond_jump_flag { NULL, cond_jump_mode }
404 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
406 /* bits in sizeflag */
407 #define SUFFIX_ALWAYS 4
415 /* byte operand with operand swapped */
417 /* operand size depends on prefixes */
419 /* operand size depends on prefixes with operand swapped */
423 /* double word operand */
425 /* double word operand with operand swapped */
427 /* quad word operand */
429 /* quad word operand with operand swapped */
431 /* ten-byte operand */
433 /* 16-byte XMM or 32-byte YMM operand */
435 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
437 /* 16-byte XMM operand */
439 /* 16-byte XMM or quad word operand */
441 /* 32-byte YMM or quad word operand */
443 /* d_mode in 32bit, q_mode in 64bit mode. */
445 /* pair of v_mode operands */
449 /* operand size depends on REX prefixes. */
451 /* registers like dq_mode, memory like w_mode. */
453 /* 4- or 6-byte pointer operand */
456 /* v_mode for stack-related opcodes. */
458 /* non-quad operand size depends on prefixes */
460 /* 16-byte operand */
462 /* registers like dq_mode, memory like b_mode. */
464 /* registers like dq_mode, memory like d_mode. */
466 /* normal vex mode */
468 /* 128bit vex mode */
470 /* 256bit vex mode */
472 /* operand size depends on the VEX.W bit. */
475 /* scalar, ignore vector length. */
477 /* like d_mode, ignore vector length. */
479 /* like d_swap_mode, ignore vector length. */
481 /* like q_mode, ignore vector length. */
483 /* like q_swap_mode, ignore vector length. */
485 /* like vex_mode, ignore vector length. */
487 /* like vex_w_dq_mode, ignore vector length. */
488 vex_scalar_w_dq_mode
,
553 #define FLOAT NULL, { { NULL, FLOATCODE } }
555 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
556 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
557 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
558 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
559 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
560 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
561 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
562 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
563 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
564 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
565 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
566 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
664 MOD_VEX_0F12_PREFIX_0
,
666 MOD_VEX_0F16_PREFIX_0
,
682 MOD_VEX_0FD7_PREFIX_2
,
683 MOD_VEX_0FE7_PREFIX_2
,
684 MOD_VEX_0FF0_PREFIX_3
,
685 MOD_VEX_0F3818_PREFIX_2
,
686 MOD_VEX_0F3819_PREFIX_2
,
687 MOD_VEX_0F381A_PREFIX_2
,
688 MOD_VEX_0F382A_PREFIX_2
,
689 MOD_VEX_0F382C_PREFIX_2
,
690 MOD_VEX_0F382D_PREFIX_2
,
691 MOD_VEX_0F382E_PREFIX_2
,
692 MOD_VEX_0F382F_PREFIX_2
862 PREFIX_VEX_0F71_REG_2
,
863 PREFIX_VEX_0F71_REG_4
,
864 PREFIX_VEX_0F71_REG_6
,
865 PREFIX_VEX_0F72_REG_2
,
866 PREFIX_VEX_0F72_REG_4
,
867 PREFIX_VEX_0F72_REG_6
,
868 PREFIX_VEX_0F73_REG_2
,
869 PREFIX_VEX_0F73_REG_3
,
870 PREFIX_VEX_0F73_REG_6
,
871 PREFIX_VEX_0F73_REG_7
,
1021 PREFIX_VEX_0F38F3_REG_1
,
1022 PREFIX_VEX_0F38F3_REG_2
,
1023 PREFIX_VEX_0F38F3_REG_3
,
1116 THREE_BYTE_0F38
= 0,
1137 VEX_LEN_0F10_P_1
= 0,
1141 VEX_LEN_0F12_P_0_M_0
,
1142 VEX_LEN_0F12_P_0_M_1
,
1145 VEX_LEN_0F16_P_0_M_0
,
1146 VEX_LEN_0F16_P_0_M_1
,
1195 VEX_LEN_0F71_R_2_P_2
,
1196 VEX_LEN_0F71_R_4_P_2
,
1197 VEX_LEN_0F71_R_6_P_2
,
1198 VEX_LEN_0F72_R_2_P_2
,
1199 VEX_LEN_0F72_R_4_P_2
,
1200 VEX_LEN_0F72_R_6_P_2
,
1201 VEX_LEN_0F73_R_2_P_2
,
1202 VEX_LEN_0F73_R_3_P_2
,
1203 VEX_LEN_0F73_R_6_P_2
,
1204 VEX_LEN_0F73_R_7_P_2
,
1210 VEX_LEN_0FAE_R_2_M_0
,
1211 VEX_LEN_0FAE_R_3_M_0
,
1222 VEX_LEN_0FD7_P_2_M_1
,
1271 VEX_LEN_0F3819_P_2_M_0
,
1272 VEX_LEN_0F381A_P_2_M_0
,
1284 VEX_LEN_0F382A_P_2_M_0
,
1309 VEX_LEN_0F38F3_R_1_P_0
,
1310 VEX_LEN_0F38F3_R_2_P_0
,
1311 VEX_LEN_0F38F3_R_3_P_0
,
1344 VEX_LEN_0FXOP_09_80
,
1532 VEX_W_0F3818_P_2_M_0
,
1533 VEX_W_0F3819_P_2_M_0
,
1534 VEX_W_0F381A_P_2_M_0
,
1546 VEX_W_0F382A_P_2_M_0
,
1548 VEX_W_0F382C_P_2_M_0
,
1549 VEX_W_0F382D_P_2_M_0
,
1550 VEX_W_0F382E_P_2_M_0
,
1551 VEX_W_0F382F_P_2_M_0
,
1607 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1618 /* Upper case letters in the instruction names here are macros.
1619 'A' => print 'b' if no register operands or suffix_always is true
1620 'B' => print 'b' if suffix_always is true
1621 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1623 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1624 suffix_always is true
1625 'E' => print 'e' if 32-bit form of jcxz
1626 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1627 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1628 'H' => print ",pt" or ",pn" branch hint
1629 'I' => honor following macro letter even in Intel mode (implemented only
1630 for some of the macro letters)
1632 'K' => print 'd' or 'q' if rex prefix is present.
1633 'L' => print 'l' if suffix_always is true
1634 'M' => print 'r' if intel_mnemonic is false.
1635 'N' => print 'n' if instruction has no wait "prefix"
1636 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1637 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1638 or suffix_always is true. print 'q' if rex prefix is present.
1639 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1641 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1642 'S' => print 'w', 'l' or 'q' if suffix_always is true
1643 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1644 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1645 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1646 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1647 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1648 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1649 suffix_always is true.
1650 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1651 '!' => change condition from true to false or from false to true.
1652 '%' => add 1 upper case letter to the macro.
1654 2 upper case letter macros:
1655 "XY" => print 'x' or 'y' if no register operands or suffix_always
1657 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1658 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1659 or suffix_always is true
1660 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1661 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1662 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1664 Many of the above letters print nothing in Intel mode. See "putop"
1667 Braces '{' and '}', and vertical bars '|', indicate alternative
1668 mnemonic strings for AT&T and Intel. */
1670 static const struct dis386 dis386
[] = {
1672 { "addB", { Eb
, Gb
} },
1673 { "addS", { Ev
, Gv
} },
1674 { "addB", { Gb
, EbS
} },
1675 { "addS", { Gv
, EvS
} },
1676 { "addB", { AL
, Ib
} },
1677 { "addS", { eAX
, Iv
} },
1678 { X86_64_TABLE (X86_64_06
) },
1679 { X86_64_TABLE (X86_64_07
) },
1681 { "orB", { Eb
, Gb
} },
1682 { "orS", { Ev
, Gv
} },
1683 { "orB", { Gb
, EbS
} },
1684 { "orS", { Gv
, EvS
} },
1685 { "orB", { AL
, Ib
} },
1686 { "orS", { eAX
, Iv
} },
1687 { X86_64_TABLE (X86_64_0D
) },
1688 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1690 { "adcB", { Eb
, Gb
} },
1691 { "adcS", { Ev
, Gv
} },
1692 { "adcB", { Gb
, EbS
} },
1693 { "adcS", { Gv
, EvS
} },
1694 { "adcB", { AL
, Ib
} },
1695 { "adcS", { eAX
, Iv
} },
1696 { X86_64_TABLE (X86_64_16
) },
1697 { X86_64_TABLE (X86_64_17
) },
1699 { "sbbB", { Eb
, Gb
} },
1700 { "sbbS", { Ev
, Gv
} },
1701 { "sbbB", { Gb
, EbS
} },
1702 { "sbbS", { Gv
, EvS
} },
1703 { "sbbB", { AL
, Ib
} },
1704 { "sbbS", { eAX
, Iv
} },
1705 { X86_64_TABLE (X86_64_1E
) },
1706 { X86_64_TABLE (X86_64_1F
) },
1708 { "andB", { Eb
, Gb
} },
1709 { "andS", { Ev
, Gv
} },
1710 { "andB", { Gb
, EbS
} },
1711 { "andS", { Gv
, EvS
} },
1712 { "andB", { AL
, Ib
} },
1713 { "andS", { eAX
, Iv
} },
1714 { Bad_Opcode
}, /* SEG ES prefix */
1715 { X86_64_TABLE (X86_64_27
) },
1717 { "subB", { Eb
, Gb
} },
1718 { "subS", { Ev
, Gv
} },
1719 { "subB", { Gb
, EbS
} },
1720 { "subS", { Gv
, EvS
} },
1721 { "subB", { AL
, Ib
} },
1722 { "subS", { eAX
, Iv
} },
1723 { Bad_Opcode
}, /* SEG CS prefix */
1724 { X86_64_TABLE (X86_64_2F
) },
1726 { "xorB", { Eb
, Gb
} },
1727 { "xorS", { Ev
, Gv
} },
1728 { "xorB", { Gb
, EbS
} },
1729 { "xorS", { Gv
, EvS
} },
1730 { "xorB", { AL
, Ib
} },
1731 { "xorS", { eAX
, Iv
} },
1732 { Bad_Opcode
}, /* SEG SS prefix */
1733 { X86_64_TABLE (X86_64_37
) },
1735 { "cmpB", { Eb
, Gb
} },
1736 { "cmpS", { Ev
, Gv
} },
1737 { "cmpB", { Gb
, EbS
} },
1738 { "cmpS", { Gv
, EvS
} },
1739 { "cmpB", { AL
, Ib
} },
1740 { "cmpS", { eAX
, Iv
} },
1741 { Bad_Opcode
}, /* SEG DS prefix */
1742 { X86_64_TABLE (X86_64_3F
) },
1744 { "inc{S|}", { RMeAX
} },
1745 { "inc{S|}", { RMeCX
} },
1746 { "inc{S|}", { RMeDX
} },
1747 { "inc{S|}", { RMeBX
} },
1748 { "inc{S|}", { RMeSP
} },
1749 { "inc{S|}", { RMeBP
} },
1750 { "inc{S|}", { RMeSI
} },
1751 { "inc{S|}", { RMeDI
} },
1753 { "dec{S|}", { RMeAX
} },
1754 { "dec{S|}", { RMeCX
} },
1755 { "dec{S|}", { RMeDX
} },
1756 { "dec{S|}", { RMeBX
} },
1757 { "dec{S|}", { RMeSP
} },
1758 { "dec{S|}", { RMeBP
} },
1759 { "dec{S|}", { RMeSI
} },
1760 { "dec{S|}", { RMeDI
} },
1762 { "pushV", { RMrAX
} },
1763 { "pushV", { RMrCX
} },
1764 { "pushV", { RMrDX
} },
1765 { "pushV", { RMrBX
} },
1766 { "pushV", { RMrSP
} },
1767 { "pushV", { RMrBP
} },
1768 { "pushV", { RMrSI
} },
1769 { "pushV", { RMrDI
} },
1771 { "popV", { RMrAX
} },
1772 { "popV", { RMrCX
} },
1773 { "popV", { RMrDX
} },
1774 { "popV", { RMrBX
} },
1775 { "popV", { RMrSP
} },
1776 { "popV", { RMrBP
} },
1777 { "popV", { RMrSI
} },
1778 { "popV", { RMrDI
} },
1780 { X86_64_TABLE (X86_64_60
) },
1781 { X86_64_TABLE (X86_64_61
) },
1782 { X86_64_TABLE (X86_64_62
) },
1783 { X86_64_TABLE (X86_64_63
) },
1784 { Bad_Opcode
}, /* seg fs */
1785 { Bad_Opcode
}, /* seg gs */
1786 { Bad_Opcode
}, /* op size prefix */
1787 { Bad_Opcode
}, /* adr size prefix */
1789 { "pushT", { sIv
} },
1790 { "imulS", { Gv
, Ev
, Iv
} },
1791 { "pushT", { sIb
} },
1792 { "imulS", { Gv
, Ev
, sIb
} },
1793 { "ins{b|}", { Ybr
, indirDX
} },
1794 { X86_64_TABLE (X86_64_6D
) },
1795 { "outs{b|}", { indirDXr
, Xb
} },
1796 { X86_64_TABLE (X86_64_6F
) },
1798 { "joH", { Jb
, XX
, cond_jump_flag
} },
1799 { "jnoH", { Jb
, XX
, cond_jump_flag
} },
1800 { "jbH", { Jb
, XX
, cond_jump_flag
} },
1801 { "jaeH", { Jb
, XX
, cond_jump_flag
} },
1802 { "jeH", { Jb
, XX
, cond_jump_flag
} },
1803 { "jneH", { Jb
, XX
, cond_jump_flag
} },
1804 { "jbeH", { Jb
, XX
, cond_jump_flag
} },
1805 { "jaH", { Jb
, XX
, cond_jump_flag
} },
1807 { "jsH", { Jb
, XX
, cond_jump_flag
} },
1808 { "jnsH", { Jb
, XX
, cond_jump_flag
} },
1809 { "jpH", { Jb
, XX
, cond_jump_flag
} },
1810 { "jnpH", { Jb
, XX
, cond_jump_flag
} },
1811 { "jlH", { Jb
, XX
, cond_jump_flag
} },
1812 { "jgeH", { Jb
, XX
, cond_jump_flag
} },
1813 { "jleH", { Jb
, XX
, cond_jump_flag
} },
1814 { "jgH", { Jb
, XX
, cond_jump_flag
} },
1816 { REG_TABLE (REG_80
) },
1817 { REG_TABLE (REG_81
) },
1819 { REG_TABLE (REG_82
) },
1820 { "testB", { Eb
, Gb
} },
1821 { "testS", { Ev
, Gv
} },
1822 { "xchgB", { Eb
, Gb
} },
1823 { "xchgS", { Ev
, Gv
} },
1825 { "movB", { Eb
, Gb
} },
1826 { "movS", { Ev
, Gv
} },
1827 { "movB", { Gb
, EbS
} },
1828 { "movS", { Gv
, EvS
} },
1829 { "movD", { Sv
, Sw
} },
1830 { MOD_TABLE (MOD_8D
) },
1831 { "movD", { Sw
, Sv
} },
1832 { REG_TABLE (REG_8F
) },
1834 { PREFIX_TABLE (PREFIX_90
) },
1835 { "xchgS", { RMeCX
, eAX
} },
1836 { "xchgS", { RMeDX
, eAX
} },
1837 { "xchgS", { RMeBX
, eAX
} },
1838 { "xchgS", { RMeSP
, eAX
} },
1839 { "xchgS", { RMeBP
, eAX
} },
1840 { "xchgS", { RMeSI
, eAX
} },
1841 { "xchgS", { RMeDI
, eAX
} },
1843 { "cW{t|}R", { XX
} },
1844 { "cR{t|}O", { XX
} },
1845 { X86_64_TABLE (X86_64_9A
) },
1846 { Bad_Opcode
}, /* fwait */
1847 { "pushfT", { XX
} },
1848 { "popfT", { XX
} },
1852 { "mov%LB", { AL
, Ob
} },
1853 { "mov%LS", { eAX
, Ov
} },
1854 { "mov%LB", { Ob
, AL
} },
1855 { "mov%LS", { Ov
, eAX
} },
1856 { "movs{b|}", { Ybr
, Xb
} },
1857 { "movs{R|}", { Yvr
, Xv
} },
1858 { "cmps{b|}", { Xb
, Yb
} },
1859 { "cmps{R|}", { Xv
, Yv
} },
1861 { "testB", { AL
, Ib
} },
1862 { "testS", { eAX
, Iv
} },
1863 { "stosB", { Ybr
, AL
} },
1864 { "stosS", { Yvr
, eAX
} },
1865 { "lodsB", { ALr
, Xb
} },
1866 { "lodsS", { eAXr
, Xv
} },
1867 { "scasB", { AL
, Yb
} },
1868 { "scasS", { eAX
, Yv
} },
1870 { "movB", { RMAL
, Ib
} },
1871 { "movB", { RMCL
, Ib
} },
1872 { "movB", { RMDL
, Ib
} },
1873 { "movB", { RMBL
, Ib
} },
1874 { "movB", { RMAH
, Ib
} },
1875 { "movB", { RMCH
, Ib
} },
1876 { "movB", { RMDH
, Ib
} },
1877 { "movB", { RMBH
, Ib
} },
1879 { "mov%LV", { RMeAX
, Iv64
} },
1880 { "mov%LV", { RMeCX
, Iv64
} },
1881 { "mov%LV", { RMeDX
, Iv64
} },
1882 { "mov%LV", { RMeBX
, Iv64
} },
1883 { "mov%LV", { RMeSP
, Iv64
} },
1884 { "mov%LV", { RMeBP
, Iv64
} },
1885 { "mov%LV", { RMeSI
, Iv64
} },
1886 { "mov%LV", { RMeDI
, Iv64
} },
1888 { REG_TABLE (REG_C0
) },
1889 { REG_TABLE (REG_C1
) },
1892 { X86_64_TABLE (X86_64_C4
) },
1893 { X86_64_TABLE (X86_64_C5
) },
1894 { REG_TABLE (REG_C6
) },
1895 { REG_TABLE (REG_C7
) },
1897 { "enterT", { Iw
, Ib
} },
1898 { "leaveT", { XX
} },
1899 { "Jret{|f}P", { Iw
} },
1900 { "Jret{|f}P", { XX
} },
1903 { X86_64_TABLE (X86_64_CE
) },
1904 { "iretP", { XX
} },
1906 { REG_TABLE (REG_D0
) },
1907 { REG_TABLE (REG_D1
) },
1908 { REG_TABLE (REG_D2
) },
1909 { REG_TABLE (REG_D3
) },
1910 { X86_64_TABLE (X86_64_D4
) },
1911 { X86_64_TABLE (X86_64_D5
) },
1913 { "xlat", { DSBX
} },
1924 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
1925 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
1926 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
1927 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
1928 { "inB", { AL
, Ib
} },
1929 { "inG", { zAX
, Ib
} },
1930 { "outB", { Ib
, AL
} },
1931 { "outG", { Ib
, zAX
} },
1933 { "callT", { Jv
} },
1935 { X86_64_TABLE (X86_64_EA
) },
1937 { "inB", { AL
, indirDX
} },
1938 { "inG", { zAX
, indirDX
} },
1939 { "outB", { indirDX
, AL
} },
1940 { "outG", { indirDX
, zAX
} },
1942 { Bad_Opcode
}, /* lock prefix */
1943 { "icebp", { XX
} },
1944 { Bad_Opcode
}, /* repne */
1945 { Bad_Opcode
}, /* repz */
1948 { REG_TABLE (REG_F6
) },
1949 { REG_TABLE (REG_F7
) },
1957 { REG_TABLE (REG_FE
) },
1958 { REG_TABLE (REG_FF
) },
1961 static const struct dis386 dis386_twobyte
[] = {
1963 { REG_TABLE (REG_0F00
) },
1964 { REG_TABLE (REG_0F01
) },
1965 { "larS", { Gv
, Ew
} },
1966 { "lslS", { Gv
, Ew
} },
1968 { "syscall", { XX
} },
1970 { "sysretP", { XX
} },
1973 { "wbinvd", { XX
} },
1977 { REG_TABLE (REG_0F0D
) },
1978 { "femms", { XX
} },
1979 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
1981 { PREFIX_TABLE (PREFIX_0F10
) },
1982 { PREFIX_TABLE (PREFIX_0F11
) },
1983 { PREFIX_TABLE (PREFIX_0F12
) },
1984 { MOD_TABLE (MOD_0F13
) },
1985 { "unpcklpX", { XM
, EXx
} },
1986 { "unpckhpX", { XM
, EXx
} },
1987 { PREFIX_TABLE (PREFIX_0F16
) },
1988 { MOD_TABLE (MOD_0F17
) },
1990 { REG_TABLE (REG_0F18
) },
1999 { MOD_TABLE (MOD_0F20
) },
2000 { MOD_TABLE (MOD_0F21
) },
2001 { MOD_TABLE (MOD_0F22
) },
2002 { MOD_TABLE (MOD_0F23
) },
2003 { MOD_TABLE (MOD_0F24
) },
2005 { MOD_TABLE (MOD_0F26
) },
2008 { "movapX", { XM
, EXx
} },
2009 { "movapX", { EXxS
, XM
} },
2010 { PREFIX_TABLE (PREFIX_0F2A
) },
2011 { PREFIX_TABLE (PREFIX_0F2B
) },
2012 { PREFIX_TABLE (PREFIX_0F2C
) },
2013 { PREFIX_TABLE (PREFIX_0F2D
) },
2014 { PREFIX_TABLE (PREFIX_0F2E
) },
2015 { PREFIX_TABLE (PREFIX_0F2F
) },
2017 { "wrmsr", { XX
} },
2018 { "rdtsc", { XX
} },
2019 { "rdmsr", { XX
} },
2020 { "rdpmc", { XX
} },
2021 { "sysenter", { XX
} },
2022 { "sysexit", { XX
} },
2024 { "getsec", { XX
} },
2026 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2028 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2035 { "cmovoS", { Gv
, Ev
} },
2036 { "cmovnoS", { Gv
, Ev
} },
2037 { "cmovbS", { Gv
, Ev
} },
2038 { "cmovaeS", { Gv
, Ev
} },
2039 { "cmoveS", { Gv
, Ev
} },
2040 { "cmovneS", { Gv
, Ev
} },
2041 { "cmovbeS", { Gv
, Ev
} },
2042 { "cmovaS", { Gv
, Ev
} },
2044 { "cmovsS", { Gv
, Ev
} },
2045 { "cmovnsS", { Gv
, Ev
} },
2046 { "cmovpS", { Gv
, Ev
} },
2047 { "cmovnpS", { Gv
, Ev
} },
2048 { "cmovlS", { Gv
, Ev
} },
2049 { "cmovgeS", { Gv
, Ev
} },
2050 { "cmovleS", { Gv
, Ev
} },
2051 { "cmovgS", { Gv
, Ev
} },
2053 { MOD_TABLE (MOD_0F51
) },
2054 { PREFIX_TABLE (PREFIX_0F51
) },
2055 { PREFIX_TABLE (PREFIX_0F52
) },
2056 { PREFIX_TABLE (PREFIX_0F53
) },
2057 { "andpX", { XM
, EXx
} },
2058 { "andnpX", { XM
, EXx
} },
2059 { "orpX", { XM
, EXx
} },
2060 { "xorpX", { XM
, EXx
} },
2062 { PREFIX_TABLE (PREFIX_0F58
) },
2063 { PREFIX_TABLE (PREFIX_0F59
) },
2064 { PREFIX_TABLE (PREFIX_0F5A
) },
2065 { PREFIX_TABLE (PREFIX_0F5B
) },
2066 { PREFIX_TABLE (PREFIX_0F5C
) },
2067 { PREFIX_TABLE (PREFIX_0F5D
) },
2068 { PREFIX_TABLE (PREFIX_0F5E
) },
2069 { PREFIX_TABLE (PREFIX_0F5F
) },
2071 { PREFIX_TABLE (PREFIX_0F60
) },
2072 { PREFIX_TABLE (PREFIX_0F61
) },
2073 { PREFIX_TABLE (PREFIX_0F62
) },
2074 { "packsswb", { MX
, EM
} },
2075 { "pcmpgtb", { MX
, EM
} },
2076 { "pcmpgtw", { MX
, EM
} },
2077 { "pcmpgtd", { MX
, EM
} },
2078 { "packuswb", { MX
, EM
} },
2080 { "punpckhbw", { MX
, EM
} },
2081 { "punpckhwd", { MX
, EM
} },
2082 { "punpckhdq", { MX
, EM
} },
2083 { "packssdw", { MX
, EM
} },
2084 { PREFIX_TABLE (PREFIX_0F6C
) },
2085 { PREFIX_TABLE (PREFIX_0F6D
) },
2086 { "movK", { MX
, Edq
} },
2087 { PREFIX_TABLE (PREFIX_0F6F
) },
2089 { PREFIX_TABLE (PREFIX_0F70
) },
2090 { REG_TABLE (REG_0F71
) },
2091 { REG_TABLE (REG_0F72
) },
2092 { REG_TABLE (REG_0F73
) },
2093 { "pcmpeqb", { MX
, EM
} },
2094 { "pcmpeqw", { MX
, EM
} },
2095 { "pcmpeqd", { MX
, EM
} },
2098 { PREFIX_TABLE (PREFIX_0F78
) },
2099 { PREFIX_TABLE (PREFIX_0F79
) },
2100 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2102 { PREFIX_TABLE (PREFIX_0F7C
) },
2103 { PREFIX_TABLE (PREFIX_0F7D
) },
2104 { PREFIX_TABLE (PREFIX_0F7E
) },
2105 { PREFIX_TABLE (PREFIX_0F7F
) },
2107 { "joH", { Jv
, XX
, cond_jump_flag
} },
2108 { "jnoH", { Jv
, XX
, cond_jump_flag
} },
2109 { "jbH", { Jv
, XX
, cond_jump_flag
} },
2110 { "jaeH", { Jv
, XX
, cond_jump_flag
} },
2111 { "jeH", { Jv
, XX
, cond_jump_flag
} },
2112 { "jneH", { Jv
, XX
, cond_jump_flag
} },
2113 { "jbeH", { Jv
, XX
, cond_jump_flag
} },
2114 { "jaH", { Jv
, XX
, cond_jump_flag
} },
2116 { "jsH", { Jv
, XX
, cond_jump_flag
} },
2117 { "jnsH", { Jv
, XX
, cond_jump_flag
} },
2118 { "jpH", { Jv
, XX
, cond_jump_flag
} },
2119 { "jnpH", { Jv
, XX
, cond_jump_flag
} },
2120 { "jlH", { Jv
, XX
, cond_jump_flag
} },
2121 { "jgeH", { Jv
, XX
, cond_jump_flag
} },
2122 { "jleH", { Jv
, XX
, cond_jump_flag
} },
2123 { "jgH", { Jv
, XX
, cond_jump_flag
} },
2126 { "setno", { Eb
} },
2128 { "setae", { Eb
} },
2130 { "setne", { Eb
} },
2131 { "setbe", { Eb
} },
2135 { "setns", { Eb
} },
2137 { "setnp", { Eb
} },
2139 { "setge", { Eb
} },
2140 { "setle", { Eb
} },
2143 { "pushT", { fs
} },
2145 { "cpuid", { XX
} },
2146 { "btS", { Ev
, Gv
} },
2147 { "shldS", { Ev
, Gv
, Ib
} },
2148 { "shldS", { Ev
, Gv
, CL
} },
2149 { REG_TABLE (REG_0FA6
) },
2150 { REG_TABLE (REG_0FA7
) },
2152 { "pushT", { gs
} },
2155 { "btsS", { Ev
, Gv
} },
2156 { "shrdS", { Ev
, Gv
, Ib
} },
2157 { "shrdS", { Ev
, Gv
, CL
} },
2158 { REG_TABLE (REG_0FAE
) },
2159 { "imulS", { Gv
, Ev
} },
2161 { "cmpxchgB", { Eb
, Gb
} },
2162 { "cmpxchgS", { Ev
, Gv
} },
2163 { MOD_TABLE (MOD_0FB2
) },
2164 { "btrS", { Ev
, Gv
} },
2165 { MOD_TABLE (MOD_0FB4
) },
2166 { MOD_TABLE (MOD_0FB5
) },
2167 { "movz{bR|x}", { Gv
, Eb
} },
2168 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2170 { PREFIX_TABLE (PREFIX_0FB8
) },
2172 { REG_TABLE (REG_0FBA
) },
2173 { "btcS", { Ev
, Gv
} },
2174 { PREFIX_TABLE (PREFIX_0FBC
) },
2175 { PREFIX_TABLE (PREFIX_0FBD
) },
2176 { "movs{bR|x}", { Gv
, Eb
} },
2177 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2179 { "xaddB", { Eb
, Gb
} },
2180 { "xaddS", { Ev
, Gv
} },
2181 { PREFIX_TABLE (PREFIX_0FC2
) },
2182 { PREFIX_TABLE (PREFIX_0FC3
) },
2183 { "pinsrw", { MX
, Edqw
, Ib
} },
2184 { "pextrw", { Gdq
, MS
, Ib
} },
2185 { "shufpX", { XM
, EXx
, Ib
} },
2186 { REG_TABLE (REG_0FC7
) },
2188 { "bswap", { RMeAX
} },
2189 { "bswap", { RMeCX
} },
2190 { "bswap", { RMeDX
} },
2191 { "bswap", { RMeBX
} },
2192 { "bswap", { RMeSP
} },
2193 { "bswap", { RMeBP
} },
2194 { "bswap", { RMeSI
} },
2195 { "bswap", { RMeDI
} },
2197 { PREFIX_TABLE (PREFIX_0FD0
) },
2198 { "psrlw", { MX
, EM
} },
2199 { "psrld", { MX
, EM
} },
2200 { "psrlq", { MX
, EM
} },
2201 { "paddq", { MX
, EM
} },
2202 { "pmullw", { MX
, EM
} },
2203 { PREFIX_TABLE (PREFIX_0FD6
) },
2204 { MOD_TABLE (MOD_0FD7
) },
2206 { "psubusb", { MX
, EM
} },
2207 { "psubusw", { MX
, EM
} },
2208 { "pminub", { MX
, EM
} },
2209 { "pand", { MX
, EM
} },
2210 { "paddusb", { MX
, EM
} },
2211 { "paddusw", { MX
, EM
} },
2212 { "pmaxub", { MX
, EM
} },
2213 { "pandn", { MX
, EM
} },
2215 { "pavgb", { MX
, EM
} },
2216 { "psraw", { MX
, EM
} },
2217 { "psrad", { MX
, EM
} },
2218 { "pavgw", { MX
, EM
} },
2219 { "pmulhuw", { MX
, EM
} },
2220 { "pmulhw", { MX
, EM
} },
2221 { PREFIX_TABLE (PREFIX_0FE6
) },
2222 { PREFIX_TABLE (PREFIX_0FE7
) },
2224 { "psubsb", { MX
, EM
} },
2225 { "psubsw", { MX
, EM
} },
2226 { "pminsw", { MX
, EM
} },
2227 { "por", { MX
, EM
} },
2228 { "paddsb", { MX
, EM
} },
2229 { "paddsw", { MX
, EM
} },
2230 { "pmaxsw", { MX
, EM
} },
2231 { "pxor", { MX
, EM
} },
2233 { PREFIX_TABLE (PREFIX_0FF0
) },
2234 { "psllw", { MX
, EM
} },
2235 { "pslld", { MX
, EM
} },
2236 { "psllq", { MX
, EM
} },
2237 { "pmuludq", { MX
, EM
} },
2238 { "pmaddwd", { MX
, EM
} },
2239 { "psadbw", { MX
, EM
} },
2240 { PREFIX_TABLE (PREFIX_0FF7
) },
2242 { "psubb", { MX
, EM
} },
2243 { "psubw", { MX
, EM
} },
2244 { "psubd", { MX
, EM
} },
2245 { "psubq", { MX
, EM
} },
2246 { "paddb", { MX
, EM
} },
2247 { "paddw", { MX
, EM
} },
2248 { "paddd", { MX
, EM
} },
2252 static const unsigned char onebyte_has_modrm
[256] = {
2253 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2254 /* ------------------------------- */
2255 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2256 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2257 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2258 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2259 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2260 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2261 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2262 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2263 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2264 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2265 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2266 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2267 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2268 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2269 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2270 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2271 /* ------------------------------- */
2272 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2275 static const unsigned char twobyte_has_modrm
[256] = {
2276 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2277 /* ------------------------------- */
2278 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2279 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2280 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2281 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2282 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2283 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2284 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2285 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2286 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2287 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2288 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2289 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2290 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2291 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2292 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2293 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2294 /* ------------------------------- */
2295 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2298 static char obuf
[100];
2300 static char *mnemonicendp
;
2301 static char scratchbuf
[100];
2302 static unsigned char *start_codep
;
2303 static unsigned char *insn_codep
;
2304 static unsigned char *codep
;
2305 static int last_lock_prefix
;
2306 static int last_repz_prefix
;
2307 static int last_repnz_prefix
;
2308 static int last_data_prefix
;
2309 static int last_addr_prefix
;
2310 static int last_rex_prefix
;
2311 static int last_seg_prefix
;
2312 #define MAX_CODE_LENGTH 15
2313 /* We can up to 14 prefixes since the maximum instruction length is
2315 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2316 static disassemble_info
*the_info
;
2324 static unsigned char need_modrm
;
2334 int register_specifier
;
2340 static unsigned char need_vex
;
2341 static unsigned char need_vex_reg
;
2342 static unsigned char vex_w_done
;
2350 /* If we are accessing mod/rm/reg without need_modrm set, then the
2351 values are stale. Hitting this abort likely indicates that you
2352 need to update onebyte_has_modrm or twobyte_has_modrm. */
2353 #define MODRM_CHECK if (!need_modrm) abort ()
2355 static const char **names64
;
2356 static const char **names32
;
2357 static const char **names16
;
2358 static const char **names8
;
2359 static const char **names8rex
;
2360 static const char **names_seg
;
2361 static const char *index64
;
2362 static const char *index32
;
2363 static const char **index16
;
2365 static const char *intel_names64
[] = {
2366 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2367 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2369 static const char *intel_names32
[] = {
2370 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2371 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2373 static const char *intel_names16
[] = {
2374 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2375 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2377 static const char *intel_names8
[] = {
2378 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2380 static const char *intel_names8rex
[] = {
2381 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2382 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2384 static const char *intel_names_seg
[] = {
2385 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2387 static const char *intel_index64
= "riz";
2388 static const char *intel_index32
= "eiz";
2389 static const char *intel_index16
[] = {
2390 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2393 static const char *att_names64
[] = {
2394 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2395 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2397 static const char *att_names32
[] = {
2398 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2399 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2401 static const char *att_names16
[] = {
2402 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2403 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2405 static const char *att_names8
[] = {
2406 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2408 static const char *att_names8rex
[] = {
2409 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2410 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2412 static const char *att_names_seg
[] = {
2413 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2415 static const char *att_index64
= "%riz";
2416 static const char *att_index32
= "%eiz";
2417 static const char *att_index16
[] = {
2418 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2421 static const char **names_mm
;
2422 static const char *intel_names_mm
[] = {
2423 "mm0", "mm1", "mm2", "mm3",
2424 "mm4", "mm5", "mm6", "mm7"
2426 static const char *att_names_mm
[] = {
2427 "%mm0", "%mm1", "%mm2", "%mm3",
2428 "%mm4", "%mm5", "%mm6", "%mm7"
2431 static const char **names_xmm
;
2432 static const char *intel_names_xmm
[] = {
2433 "xmm0", "xmm1", "xmm2", "xmm3",
2434 "xmm4", "xmm5", "xmm6", "xmm7",
2435 "xmm8", "xmm9", "xmm10", "xmm11",
2436 "xmm12", "xmm13", "xmm14", "xmm15"
2438 static const char *att_names_xmm
[] = {
2439 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2440 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2441 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2442 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2445 static const char **names_ymm
;
2446 static const char *intel_names_ymm
[] = {
2447 "ymm0", "ymm1", "ymm2", "ymm3",
2448 "ymm4", "ymm5", "ymm6", "ymm7",
2449 "ymm8", "ymm9", "ymm10", "ymm11",
2450 "ymm12", "ymm13", "ymm14", "ymm15"
2452 static const char *att_names_ymm
[] = {
2453 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2454 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2455 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2456 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2459 static const struct dis386 reg_table
[][8] = {
2462 { "addA", { Eb
, Ib
} },
2463 { "orA", { Eb
, Ib
} },
2464 { "adcA", { Eb
, Ib
} },
2465 { "sbbA", { Eb
, Ib
} },
2466 { "andA", { Eb
, Ib
} },
2467 { "subA", { Eb
, Ib
} },
2468 { "xorA", { Eb
, Ib
} },
2469 { "cmpA", { Eb
, Ib
} },
2473 { "addQ", { Ev
, Iv
} },
2474 { "orQ", { Ev
, Iv
} },
2475 { "adcQ", { Ev
, Iv
} },
2476 { "sbbQ", { Ev
, Iv
} },
2477 { "andQ", { Ev
, Iv
} },
2478 { "subQ", { Ev
, Iv
} },
2479 { "xorQ", { Ev
, Iv
} },
2480 { "cmpQ", { Ev
, Iv
} },
2484 { "addQ", { Ev
, sIb
} },
2485 { "orQ", { Ev
, sIb
} },
2486 { "adcQ", { Ev
, sIb
} },
2487 { "sbbQ", { Ev
, sIb
} },
2488 { "andQ", { Ev
, sIb
} },
2489 { "subQ", { Ev
, sIb
} },
2490 { "xorQ", { Ev
, sIb
} },
2491 { "cmpQ", { Ev
, sIb
} },
2495 { "popU", { stackEv
} },
2496 { XOP_8F_TABLE (XOP_09
) },
2500 { XOP_8F_TABLE (XOP_09
) },
2504 { "rolA", { Eb
, Ib
} },
2505 { "rorA", { Eb
, Ib
} },
2506 { "rclA", { Eb
, Ib
} },
2507 { "rcrA", { Eb
, Ib
} },
2508 { "shlA", { Eb
, Ib
} },
2509 { "shrA", { Eb
, Ib
} },
2511 { "sarA", { Eb
, Ib
} },
2515 { "rolQ", { Ev
, Ib
} },
2516 { "rorQ", { Ev
, Ib
} },
2517 { "rclQ", { Ev
, Ib
} },
2518 { "rcrQ", { Ev
, Ib
} },
2519 { "shlQ", { Ev
, Ib
} },
2520 { "shrQ", { Ev
, Ib
} },
2522 { "sarQ", { Ev
, Ib
} },
2526 { "movA", { Eb
, Ib
} },
2530 { "movQ", { Ev
, Iv
} },
2534 { "rolA", { Eb
, I1
} },
2535 { "rorA", { Eb
, I1
} },
2536 { "rclA", { Eb
, I1
} },
2537 { "rcrA", { Eb
, I1
} },
2538 { "shlA", { Eb
, I1
} },
2539 { "shrA", { Eb
, I1
} },
2541 { "sarA", { Eb
, I1
} },
2545 { "rolQ", { Ev
, I1
} },
2546 { "rorQ", { Ev
, I1
} },
2547 { "rclQ", { Ev
, I1
} },
2548 { "rcrQ", { Ev
, I1
} },
2549 { "shlQ", { Ev
, I1
} },
2550 { "shrQ", { Ev
, I1
} },
2552 { "sarQ", { Ev
, I1
} },
2556 { "rolA", { Eb
, CL
} },
2557 { "rorA", { Eb
, CL
} },
2558 { "rclA", { Eb
, CL
} },
2559 { "rcrA", { Eb
, CL
} },
2560 { "shlA", { Eb
, CL
} },
2561 { "shrA", { Eb
, CL
} },
2563 { "sarA", { Eb
, CL
} },
2567 { "rolQ", { Ev
, CL
} },
2568 { "rorQ", { Ev
, CL
} },
2569 { "rclQ", { Ev
, CL
} },
2570 { "rcrQ", { Ev
, CL
} },
2571 { "shlQ", { Ev
, CL
} },
2572 { "shrQ", { Ev
, CL
} },
2574 { "sarQ", { Ev
, CL
} },
2578 { "testA", { Eb
, Ib
} },
2582 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
2583 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
2584 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
2585 { "idivA", { Eb
} }, /* and idiv for consistency. */
2589 { "testQ", { Ev
, Iv
} },
2593 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
2594 { "imulQ", { Ev
} },
2596 { "idivQ", { Ev
} },
2607 { "call{T|}", { indirEv
} },
2608 { "Jcall{T|}", { indirEp
} },
2609 { "jmp{T|}", { indirEv
} },
2610 { "Jjmp{T|}", { indirEp
} },
2611 { "pushU", { stackEv
} },
2616 { "sldtD", { Sv
} },
2627 { MOD_TABLE (MOD_0F01_REG_0
) },
2628 { MOD_TABLE (MOD_0F01_REG_1
) },
2629 { MOD_TABLE (MOD_0F01_REG_2
) },
2630 { MOD_TABLE (MOD_0F01_REG_3
) },
2631 { "smswD", { Sv
} },
2634 { MOD_TABLE (MOD_0F01_REG_7
) },
2638 { "prefetch", { Mb
} },
2639 { "prefetchw", { Mb
} },
2643 { MOD_TABLE (MOD_0F18_REG_0
) },
2644 { MOD_TABLE (MOD_0F18_REG_1
) },
2645 { MOD_TABLE (MOD_0F18_REG_2
) },
2646 { MOD_TABLE (MOD_0F18_REG_3
) },
2652 { MOD_TABLE (MOD_0F71_REG_2
) },
2654 { MOD_TABLE (MOD_0F71_REG_4
) },
2656 { MOD_TABLE (MOD_0F71_REG_6
) },
2662 { MOD_TABLE (MOD_0F72_REG_2
) },
2664 { MOD_TABLE (MOD_0F72_REG_4
) },
2666 { MOD_TABLE (MOD_0F72_REG_6
) },
2672 { MOD_TABLE (MOD_0F73_REG_2
) },
2673 { MOD_TABLE (MOD_0F73_REG_3
) },
2676 { MOD_TABLE (MOD_0F73_REG_6
) },
2677 { MOD_TABLE (MOD_0F73_REG_7
) },
2681 { "montmul", { { OP_0f07
, 0 } } },
2682 { "xsha1", { { OP_0f07
, 0 } } },
2683 { "xsha256", { { OP_0f07
, 0 } } },
2687 { "xstore-rng", { { OP_0f07
, 0 } } },
2688 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
2689 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
2690 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
2691 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
2692 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
2696 { MOD_TABLE (MOD_0FAE_REG_0
) },
2697 { MOD_TABLE (MOD_0FAE_REG_1
) },
2698 { MOD_TABLE (MOD_0FAE_REG_2
) },
2699 { MOD_TABLE (MOD_0FAE_REG_3
) },
2700 { MOD_TABLE (MOD_0FAE_REG_4
) },
2701 { MOD_TABLE (MOD_0FAE_REG_5
) },
2702 { MOD_TABLE (MOD_0FAE_REG_6
) },
2703 { MOD_TABLE (MOD_0FAE_REG_7
) },
2711 { "btQ", { Ev
, Ib
} },
2712 { "btsQ", { Ev
, Ib
} },
2713 { "btrQ", { Ev
, Ib
} },
2714 { "btcQ", { Ev
, Ib
} },
2719 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
2724 { MOD_TABLE (MOD_0FC7_REG_6
) },
2725 { MOD_TABLE (MOD_0FC7_REG_7
) },
2731 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
2733 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
2735 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
2741 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
2743 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
2745 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
2751 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
2752 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
2755 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
2756 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
2762 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
2763 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
2765 /* REG_VEX_0F38F3 */
2768 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
2769 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
2770 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
2774 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
2775 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
2779 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2780 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2784 static const struct dis386 prefix_table
[][4] = {
2787 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2788 { "pause", { XX
} },
2789 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2794 { "movups", { XM
, EXx
} },
2795 { "movss", { XM
, EXd
} },
2796 { "movupd", { XM
, EXx
} },
2797 { "movsd", { XM
, EXq
} },
2802 { "movups", { EXxS
, XM
} },
2803 { "movss", { EXdS
, XM
} },
2804 { "movupd", { EXxS
, XM
} },
2805 { "movsd", { EXqS
, XM
} },
2810 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
2811 { "movsldup", { XM
, EXx
} },
2812 { "movlpd", { XM
, EXq
} },
2813 { "movddup", { XM
, EXq
} },
2818 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
2819 { "movshdup", { XM
, EXx
} },
2820 { "movhpd", { XM
, EXq
} },
2825 { "cvtpi2ps", { XM
, EMCq
} },
2826 { "cvtsi2ss%LQ", { XM
, Ev
} },
2827 { "cvtpi2pd", { XM
, EMCq
} },
2828 { "cvtsi2sd%LQ", { XM
, Ev
} },
2833 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
2834 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
2835 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
2836 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
2841 { "cvttps2pi", { MXC
, EXq
} },
2842 { "cvttss2siY", { Gv
, EXd
} },
2843 { "cvttpd2pi", { MXC
, EXx
} },
2844 { "cvttsd2siY", { Gv
, EXq
} },
2849 { "cvtps2pi", { MXC
, EXq
} },
2850 { "cvtss2siY", { Gv
, EXd
} },
2851 { "cvtpd2pi", { MXC
, EXx
} },
2852 { "cvtsd2siY", { Gv
, EXq
} },
2857 { "ucomiss",{ XM
, EXd
} },
2859 { "ucomisd",{ XM
, EXq
} },
2864 { "comiss", { XM
, EXd
} },
2866 { "comisd", { XM
, EXq
} },
2871 { "sqrtps", { XM
, EXx
} },
2872 { "sqrtss", { XM
, EXd
} },
2873 { "sqrtpd", { XM
, EXx
} },
2874 { "sqrtsd", { XM
, EXq
} },
2879 { "rsqrtps",{ XM
, EXx
} },
2880 { "rsqrtss",{ XM
, EXd
} },
2885 { "rcpps", { XM
, EXx
} },
2886 { "rcpss", { XM
, EXd
} },
2891 { "addps", { XM
, EXx
} },
2892 { "addss", { XM
, EXd
} },
2893 { "addpd", { XM
, EXx
} },
2894 { "addsd", { XM
, EXq
} },
2899 { "mulps", { XM
, EXx
} },
2900 { "mulss", { XM
, EXd
} },
2901 { "mulpd", { XM
, EXx
} },
2902 { "mulsd", { XM
, EXq
} },
2907 { "cvtps2pd", { XM
, EXq
} },
2908 { "cvtss2sd", { XM
, EXd
} },
2909 { "cvtpd2ps", { XM
, EXx
} },
2910 { "cvtsd2ss", { XM
, EXq
} },
2915 { "cvtdq2ps", { XM
, EXx
} },
2916 { "cvttps2dq", { XM
, EXx
} },
2917 { "cvtps2dq", { XM
, EXx
} },
2922 { "subps", { XM
, EXx
} },
2923 { "subss", { XM
, EXd
} },
2924 { "subpd", { XM
, EXx
} },
2925 { "subsd", { XM
, EXq
} },
2930 { "minps", { XM
, EXx
} },
2931 { "minss", { XM
, EXd
} },
2932 { "minpd", { XM
, EXx
} },
2933 { "minsd", { XM
, EXq
} },
2938 { "divps", { XM
, EXx
} },
2939 { "divss", { XM
, EXd
} },
2940 { "divpd", { XM
, EXx
} },
2941 { "divsd", { XM
, EXq
} },
2946 { "maxps", { XM
, EXx
} },
2947 { "maxss", { XM
, EXd
} },
2948 { "maxpd", { XM
, EXx
} },
2949 { "maxsd", { XM
, EXq
} },
2954 { "punpcklbw",{ MX
, EMd
} },
2956 { "punpcklbw",{ MX
, EMx
} },
2961 { "punpcklwd",{ MX
, EMd
} },
2963 { "punpcklwd",{ MX
, EMx
} },
2968 { "punpckldq",{ MX
, EMd
} },
2970 { "punpckldq",{ MX
, EMx
} },
2977 { "punpcklqdq", { XM
, EXx
} },
2984 { "punpckhqdq", { XM
, EXx
} },
2989 { "movq", { MX
, EM
} },
2990 { "movdqu", { XM
, EXx
} },
2991 { "movdqa", { XM
, EXx
} },
2996 { "pshufw", { MX
, EM
, Ib
} },
2997 { "pshufhw",{ XM
, EXx
, Ib
} },
2998 { "pshufd", { XM
, EXx
, Ib
} },
2999 { "pshuflw",{ XM
, EXx
, Ib
} },
3002 /* PREFIX_0F73_REG_3 */
3006 { "psrldq", { XS
, Ib
} },
3009 /* PREFIX_0F73_REG_7 */
3013 { "pslldq", { XS
, Ib
} },
3018 {"vmread", { Em
, Gm
} },
3020 {"extrq", { XS
, Ib
, Ib
} },
3021 {"insertq", { XM
, XS
, Ib
, Ib
} },
3026 {"vmwrite", { Gm
, Em
} },
3028 {"extrq", { XM
, XS
} },
3029 {"insertq", { XM
, XS
} },
3036 { "haddpd", { XM
, EXx
} },
3037 { "haddps", { XM
, EXx
} },
3044 { "hsubpd", { XM
, EXx
} },
3045 { "hsubps", { XM
, EXx
} },
3050 { "movK", { Edq
, MX
} },
3051 { "movq", { XM
, EXq
} },
3052 { "movK", { Edq
, XM
} },
3057 { "movq", { EMS
, MX
} },
3058 { "movdqu", { EXxS
, XM
} },
3059 { "movdqa", { EXxS
, XM
} },
3062 /* PREFIX_0FAE_REG_0 */
3065 { "rdfsbase", { Ev
} },
3068 /* PREFIX_0FAE_REG_1 */
3071 { "rdgsbase", { Ev
} },
3074 /* PREFIX_0FAE_REG_2 */
3077 { "wrfsbase", { Ev
} },
3080 /* PREFIX_0FAE_REG_3 */
3083 { "wrgsbase", { Ev
} },
3089 { "popcntS", { Gv
, Ev
} },
3094 { "bsfS", { Gv
, Ev
} },
3095 { "tzcntS", { Gv
, Ev
} },
3096 { "bsfS", { Gv
, Ev
} },
3101 { "bsrS", { Gv
, Ev
} },
3102 { "lzcntS", { Gv
, Ev
} },
3103 { "bsrS", { Gv
, Ev
} },
3108 { "cmpps", { XM
, EXx
, CMP
} },
3109 { "cmpss", { XM
, EXd
, CMP
} },
3110 { "cmppd", { XM
, EXx
, CMP
} },
3111 { "cmpsd", { XM
, EXq
, CMP
} },
3116 { "movntiS", { Ma
, Gv
} },
3119 /* PREFIX_0FC7_REG_6 */
3121 { "vmptrld",{ Mq
} },
3122 { "vmxon", { Mq
} },
3123 { "vmclear",{ Mq
} },
3130 { "addsubpd", { XM
, EXx
} },
3131 { "addsubps", { XM
, EXx
} },
3137 { "movq2dq",{ XM
, MS
} },
3138 { "movq", { EXqS
, XM
} },
3139 { "movdq2q",{ MX
, XS
} },
3145 { "cvtdq2pd", { XM
, EXq
} },
3146 { "cvttpd2dq", { XM
, EXx
} },
3147 { "cvtpd2dq", { XM
, EXx
} },
3152 { "movntq", { Mq
, MX
} },
3154 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3162 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3167 { "maskmovq", { MX
, MS
} },
3169 { "maskmovdqu", { XM
, XS
} },
3176 { "pblendvb", { XM
, EXx
, XMM0
} },
3183 { "blendvps", { XM
, EXx
, XMM0
} },
3190 { "blendvpd", { XM
, EXx
, XMM0
} },
3197 { "ptest", { XM
, EXx
} },
3204 { "pmovsxbw", { XM
, EXq
} },
3211 { "pmovsxbd", { XM
, EXd
} },
3218 { "pmovsxbq", { XM
, EXw
} },
3225 { "pmovsxwd", { XM
, EXq
} },
3232 { "pmovsxwq", { XM
, EXd
} },
3239 { "pmovsxdq", { XM
, EXq
} },
3246 { "pmuldq", { XM
, EXx
} },
3253 { "pcmpeqq", { XM
, EXx
} },
3260 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3267 { "packusdw", { XM
, EXx
} },
3274 { "pmovzxbw", { XM
, EXq
} },
3281 { "pmovzxbd", { XM
, EXd
} },
3288 { "pmovzxbq", { XM
, EXw
} },
3295 { "pmovzxwd", { XM
, EXq
} },
3302 { "pmovzxwq", { XM
, EXd
} },
3309 { "pmovzxdq", { XM
, EXq
} },
3316 { "pcmpgtq", { XM
, EXx
} },
3323 { "pminsb", { XM
, EXx
} },
3330 { "pminsd", { XM
, EXx
} },
3337 { "pminuw", { XM
, EXx
} },
3344 { "pminud", { XM
, EXx
} },
3351 { "pmaxsb", { XM
, EXx
} },
3358 { "pmaxsd", { XM
, EXx
} },
3365 { "pmaxuw", { XM
, EXx
} },
3372 { "pmaxud", { XM
, EXx
} },
3379 { "pmulld", { XM
, EXx
} },
3386 { "phminposuw", { XM
, EXx
} },
3393 { "invept", { Gm
, Mo
} },
3400 { "invvpid", { Gm
, Mo
} },
3407 { "aesimc", { XM
, EXx
} },
3414 { "aesenc", { XM
, EXx
} },
3421 { "aesenclast", { XM
, EXx
} },
3428 { "aesdec", { XM
, EXx
} },
3435 { "aesdeclast", { XM
, EXx
} },
3440 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3442 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3443 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
3448 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3450 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3451 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
3458 { "roundps", { XM
, EXx
, Ib
} },
3465 { "roundpd", { XM
, EXx
, Ib
} },
3472 { "roundss", { XM
, EXd
, Ib
} },
3479 { "roundsd", { XM
, EXq
, Ib
} },
3486 { "blendps", { XM
, EXx
, Ib
} },
3493 { "blendpd", { XM
, EXx
, Ib
} },
3500 { "pblendw", { XM
, EXx
, Ib
} },
3507 { "pextrb", { Edqb
, XM
, Ib
} },
3514 { "pextrw", { Edqw
, XM
, Ib
} },
3521 { "pextrK", { Edq
, XM
, Ib
} },
3528 { "extractps", { Edqd
, XM
, Ib
} },
3535 { "pinsrb", { XM
, Edqb
, Ib
} },
3542 { "insertps", { XM
, EXd
, Ib
} },
3549 { "pinsrK", { XM
, Edq
, Ib
} },
3556 { "dpps", { XM
, EXx
, Ib
} },
3563 { "dppd", { XM
, EXx
, Ib
} },
3570 { "mpsadbw", { XM
, EXx
, Ib
} },
3577 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
3584 { "pcmpestrm", { XM
, EXx
, Ib
} },
3591 { "pcmpestri", { XM
, EXx
, Ib
} },
3598 { "pcmpistrm", { XM
, EXx
, Ib
} },
3605 { "pcmpistri", { XM
, EXx
, Ib
} },
3612 { "aeskeygenassist", { XM
, EXx
, Ib
} },
3615 /* PREFIX_VEX_0F10 */
3617 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
3618 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
3619 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
3620 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
3623 /* PREFIX_VEX_0F11 */
3625 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
3626 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
3627 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
3628 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
3631 /* PREFIX_VEX_0F12 */
3633 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3634 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
3635 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
3636 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
3639 /* PREFIX_VEX_0F16 */
3641 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3642 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
3643 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
3646 /* PREFIX_VEX_0F2A */
3649 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
3651 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
3654 /* PREFIX_VEX_0F2C */
3657 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
3659 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
3662 /* PREFIX_VEX_0F2D */
3665 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
3667 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
3670 /* PREFIX_VEX_0F2E */
3672 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
3674 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
3677 /* PREFIX_VEX_0F2F */
3679 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
3681 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
3684 /* PREFIX_VEX_0F51 */
3686 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
3687 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
3688 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
3689 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
3692 /* PREFIX_VEX_0F52 */
3694 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
3695 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
3698 /* PREFIX_VEX_0F53 */
3700 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
3701 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
3704 /* PREFIX_VEX_0F58 */
3706 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
3707 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
3708 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
3709 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
3712 /* PREFIX_VEX_0F59 */
3714 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
3715 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
3716 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
3717 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
3720 /* PREFIX_VEX_0F5A */
3722 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
3723 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
3724 { "vcvtpd2ps%XY", { XMM
, EXx
} },
3725 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
3728 /* PREFIX_VEX_0F5B */
3730 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
3731 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
3732 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
3735 /* PREFIX_VEX_0F5C */
3737 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
3738 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
3739 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
3740 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
3743 /* PREFIX_VEX_0F5D */
3745 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
3746 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
3747 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
3748 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
3751 /* PREFIX_VEX_0F5E */
3753 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
3754 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
3755 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
3756 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
3759 /* PREFIX_VEX_0F5F */
3761 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
3762 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
3763 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
3764 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
3767 /* PREFIX_VEX_0F60 */
3771 { VEX_LEN_TABLE (VEX_LEN_0F60_P_2
) },
3774 /* PREFIX_VEX_0F61 */
3778 { VEX_LEN_TABLE (VEX_LEN_0F61_P_2
) },
3781 /* PREFIX_VEX_0F62 */
3785 { VEX_LEN_TABLE (VEX_LEN_0F62_P_2
) },
3788 /* PREFIX_VEX_0F63 */
3792 { VEX_LEN_TABLE (VEX_LEN_0F63_P_2
) },
3795 /* PREFIX_VEX_0F64 */
3799 { VEX_LEN_TABLE (VEX_LEN_0F64_P_2
) },
3802 /* PREFIX_VEX_0F65 */
3806 { VEX_LEN_TABLE (VEX_LEN_0F65_P_2
) },
3809 /* PREFIX_VEX_0F66 */
3813 { VEX_LEN_TABLE (VEX_LEN_0F66_P_2
) },
3816 /* PREFIX_VEX_0F67 */
3820 { VEX_LEN_TABLE (VEX_LEN_0F67_P_2
) },
3823 /* PREFIX_VEX_0F68 */
3827 { VEX_LEN_TABLE (VEX_LEN_0F68_P_2
) },
3830 /* PREFIX_VEX_0F69 */
3834 { VEX_LEN_TABLE (VEX_LEN_0F69_P_2
) },
3837 /* PREFIX_VEX_0F6A */
3841 { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2
) },
3844 /* PREFIX_VEX_0F6B */
3848 { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2
) },
3851 /* PREFIX_VEX_0F6C */
3855 { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2
) },
3858 /* PREFIX_VEX_0F6D */
3862 { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2
) },
3865 /* PREFIX_VEX_0F6E */
3869 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
3872 /* PREFIX_VEX_0F6F */
3875 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
3876 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
3879 /* PREFIX_VEX_0F70 */
3882 { VEX_LEN_TABLE (VEX_LEN_0F70_P_1
) },
3883 { VEX_LEN_TABLE (VEX_LEN_0F70_P_2
) },
3884 { VEX_LEN_TABLE (VEX_LEN_0F70_P_3
) },
3887 /* PREFIX_VEX_0F71_REG_2 */
3891 { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2
) },
3894 /* PREFIX_VEX_0F71_REG_4 */
3898 { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2
) },
3901 /* PREFIX_VEX_0F71_REG_6 */
3905 { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2
) },
3908 /* PREFIX_VEX_0F72_REG_2 */
3912 { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2
) },
3915 /* PREFIX_VEX_0F72_REG_4 */
3919 { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2
) },
3922 /* PREFIX_VEX_0F72_REG_6 */
3926 { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2
) },
3929 /* PREFIX_VEX_0F73_REG_2 */
3933 { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2
) },
3936 /* PREFIX_VEX_0F73_REG_3 */
3940 { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2
) },
3943 /* PREFIX_VEX_0F73_REG_6 */
3947 { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2
) },
3950 /* PREFIX_VEX_0F73_REG_7 */
3954 { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2
) },
3957 /* PREFIX_VEX_0F74 */
3961 { VEX_LEN_TABLE (VEX_LEN_0F74_P_2
) },
3964 /* PREFIX_VEX_0F75 */
3968 { VEX_LEN_TABLE (VEX_LEN_0F75_P_2
) },
3971 /* PREFIX_VEX_0F76 */
3975 { VEX_LEN_TABLE (VEX_LEN_0F76_P_2
) },
3978 /* PREFIX_VEX_0F77 */
3980 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
3983 /* PREFIX_VEX_0F7C */
3987 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
3988 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
3991 /* PREFIX_VEX_0F7D */
3995 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
3996 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
3999 /* PREFIX_VEX_0F7E */
4002 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
4003 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4006 /* PREFIX_VEX_0F7F */
4009 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
4010 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
4013 /* PREFIX_VEX_0FC2 */
4015 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
4016 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
4017 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
4018 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
4021 /* PREFIX_VEX_0FC4 */
4025 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
4028 /* PREFIX_VEX_0FC5 */
4032 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
4035 /* PREFIX_VEX_0FD0 */
4039 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
4040 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
4043 /* PREFIX_VEX_0FD1 */
4047 { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2
) },
4050 /* PREFIX_VEX_0FD2 */
4054 { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2
) },
4057 /* PREFIX_VEX_0FD3 */
4061 { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2
) },
4064 /* PREFIX_VEX_0FD4 */
4068 { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2
) },
4071 /* PREFIX_VEX_0FD5 */
4075 { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2
) },
4078 /* PREFIX_VEX_0FD6 */
4082 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
4085 /* PREFIX_VEX_0FD7 */
4089 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
4092 /* PREFIX_VEX_0FD8 */
4096 { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2
) },
4099 /* PREFIX_VEX_0FD9 */
4103 { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2
) },
4106 /* PREFIX_VEX_0FDA */
4110 { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2
) },
4113 /* PREFIX_VEX_0FDB */
4117 { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2
) },
4120 /* PREFIX_VEX_0FDC */
4124 { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2
) },
4127 /* PREFIX_VEX_0FDD */
4131 { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2
) },
4134 /* PREFIX_VEX_0FDE */
4138 { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2
) },
4141 /* PREFIX_VEX_0FDF */
4145 { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2
) },
4148 /* PREFIX_VEX_0FE0 */
4152 { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2
) },
4155 /* PREFIX_VEX_0FE1 */
4159 { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2
) },
4162 /* PREFIX_VEX_0FE2 */
4166 { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2
) },
4169 /* PREFIX_VEX_0FE3 */
4173 { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2
) },
4176 /* PREFIX_VEX_0FE4 */
4180 { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2
) },
4183 /* PREFIX_VEX_0FE5 */
4187 { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2
) },
4190 /* PREFIX_VEX_0FE6 */
4193 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
4194 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
4195 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
4198 /* PREFIX_VEX_0FE7 */
4202 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
4205 /* PREFIX_VEX_0FE8 */
4209 { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2
) },
4212 /* PREFIX_VEX_0FE9 */
4216 { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2
) },
4219 /* PREFIX_VEX_0FEA */
4223 { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2
) },
4226 /* PREFIX_VEX_0FEB */
4230 { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2
) },
4233 /* PREFIX_VEX_0FEC */
4237 { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2
) },
4240 /* PREFIX_VEX_0FED */
4244 { VEX_LEN_TABLE (VEX_LEN_0FED_P_2
) },
4247 /* PREFIX_VEX_0FEE */
4251 { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2
) },
4254 /* PREFIX_VEX_0FEF */
4258 { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2
) },
4261 /* PREFIX_VEX_0FF0 */
4266 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4269 /* PREFIX_VEX_0FF1 */
4273 { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2
) },
4276 /* PREFIX_VEX_0FF2 */
4280 { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2
) },
4283 /* PREFIX_VEX_0FF3 */
4287 { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2
) },
4290 /* PREFIX_VEX_0FF4 */
4294 { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2
) },
4297 /* PREFIX_VEX_0FF5 */
4301 { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2
) },
4304 /* PREFIX_VEX_0FF6 */
4308 { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2
) },
4311 /* PREFIX_VEX_0FF7 */
4315 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
4318 /* PREFIX_VEX_0FF8 */
4322 { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2
) },
4325 /* PREFIX_VEX_0FF9 */
4329 { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2
) },
4332 /* PREFIX_VEX_0FFA */
4336 { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2
) },
4339 /* PREFIX_VEX_0FFB */
4343 { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2
) },
4346 /* PREFIX_VEX_0FFC */
4350 { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2
) },
4353 /* PREFIX_VEX_0FFD */
4357 { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2
) },
4360 /* PREFIX_VEX_0FFE */
4364 { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2
) },
4367 /* PREFIX_VEX_0F3800 */
4371 { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2
) },
4374 /* PREFIX_VEX_0F3801 */
4378 { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2
) },
4381 /* PREFIX_VEX_0F3802 */
4385 { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2
) },
4388 /* PREFIX_VEX_0F3803 */
4392 { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2
) },
4395 /* PREFIX_VEX_0F3804 */
4399 { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2
) },
4402 /* PREFIX_VEX_0F3805 */
4406 { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2
) },
4409 /* PREFIX_VEX_0F3806 */
4413 { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2
) },
4416 /* PREFIX_VEX_0F3807 */
4420 { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2
) },
4423 /* PREFIX_VEX_0F3808 */
4427 { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2
) },
4430 /* PREFIX_VEX_0F3809 */
4434 { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2
) },
4437 /* PREFIX_VEX_0F380A */
4441 { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2
) },
4444 /* PREFIX_VEX_0F380B */
4448 { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2
) },
4451 /* PREFIX_VEX_0F380C */
4455 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
4458 /* PREFIX_VEX_0F380D */
4462 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
4465 /* PREFIX_VEX_0F380E */
4469 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
4472 /* PREFIX_VEX_0F380F */
4476 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
4479 /* PREFIX_VEX_0F3813 */
4483 { "vcvtph2ps", { XM
, EXxmmq
} },
4486 /* PREFIX_VEX_0F3817 */
4490 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
4493 /* PREFIX_VEX_0F3818 */
4497 { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2
) },
4500 /* PREFIX_VEX_0F3819 */
4504 { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2
) },
4507 /* PREFIX_VEX_0F381A */
4511 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
4514 /* PREFIX_VEX_0F381C */
4518 { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2
) },
4521 /* PREFIX_VEX_0F381D */
4525 { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2
) },
4528 /* PREFIX_VEX_0F381E */
4532 { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2
) },
4535 /* PREFIX_VEX_0F3820 */
4539 { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2
) },
4542 /* PREFIX_VEX_0F3821 */
4546 { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2
) },
4549 /* PREFIX_VEX_0F3822 */
4553 { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2
) },
4556 /* PREFIX_VEX_0F3823 */
4560 { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2
) },
4563 /* PREFIX_VEX_0F3824 */
4567 { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2
) },
4570 /* PREFIX_VEX_0F3825 */
4574 { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2
) },
4577 /* PREFIX_VEX_0F3828 */
4581 { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2
) },
4584 /* PREFIX_VEX_0F3829 */
4588 { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2
) },
4591 /* PREFIX_VEX_0F382A */
4595 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
4598 /* PREFIX_VEX_0F382B */
4602 { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2
) },
4605 /* PREFIX_VEX_0F382C */
4609 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
4612 /* PREFIX_VEX_0F382D */
4616 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
4619 /* PREFIX_VEX_0F382E */
4623 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
4626 /* PREFIX_VEX_0F382F */
4630 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
4633 /* PREFIX_VEX_0F3830 */
4637 { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2
) },
4640 /* PREFIX_VEX_0F3831 */
4644 { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2
) },
4647 /* PREFIX_VEX_0F3832 */
4651 { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2
) },
4654 /* PREFIX_VEX_0F3833 */
4658 { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2
) },
4661 /* PREFIX_VEX_0F3834 */
4665 { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2
) },
4668 /* PREFIX_VEX_0F3835 */
4672 { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2
) },
4675 /* PREFIX_VEX_0F3837 */
4679 { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2
) },
4682 /* PREFIX_VEX_0F3838 */
4686 { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2
) },
4689 /* PREFIX_VEX_0F3839 */
4693 { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2
) },
4696 /* PREFIX_VEX_0F383A */
4700 { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2
) },
4703 /* PREFIX_VEX_0F383B */
4707 { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2
) },
4710 /* PREFIX_VEX_0F383C */
4714 { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2
) },
4717 /* PREFIX_VEX_0F383D */
4721 { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2
) },
4724 /* PREFIX_VEX_0F383E */
4728 { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2
) },
4731 /* PREFIX_VEX_0F383F */
4735 { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2
) },
4738 /* PREFIX_VEX_0F3840 */
4742 { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2
) },
4745 /* PREFIX_VEX_0F3841 */
4749 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
4752 /* PREFIX_VEX_0F3896 */
4756 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
4759 /* PREFIX_VEX_0F3897 */
4763 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
4766 /* PREFIX_VEX_0F3898 */
4770 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
4773 /* PREFIX_VEX_0F3899 */
4777 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4780 /* PREFIX_VEX_0F389A */
4784 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
4787 /* PREFIX_VEX_0F389B */
4791 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4794 /* PREFIX_VEX_0F389C */
4798 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
4801 /* PREFIX_VEX_0F389D */
4805 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4808 /* PREFIX_VEX_0F389E */
4812 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
4815 /* PREFIX_VEX_0F389F */
4819 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4822 /* PREFIX_VEX_0F38A6 */
4826 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
4830 /* PREFIX_VEX_0F38A7 */
4834 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
4837 /* PREFIX_VEX_0F38A8 */
4841 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
4844 /* PREFIX_VEX_0F38A9 */
4848 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4851 /* PREFIX_VEX_0F38AA */
4855 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
4858 /* PREFIX_VEX_0F38AB */
4862 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4865 /* PREFIX_VEX_0F38AC */
4869 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
4872 /* PREFIX_VEX_0F38AD */
4876 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4879 /* PREFIX_VEX_0F38AE */
4883 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
4886 /* PREFIX_VEX_0F38AF */
4890 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4893 /* PREFIX_VEX_0F38B6 */
4897 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
4900 /* PREFIX_VEX_0F38B7 */
4904 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
4907 /* PREFIX_VEX_0F38B8 */
4911 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
4914 /* PREFIX_VEX_0F38B9 */
4918 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4921 /* PREFIX_VEX_0F38BA */
4925 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
4928 /* PREFIX_VEX_0F38BB */
4932 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4935 /* PREFIX_VEX_0F38BC */
4939 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
4942 /* PREFIX_VEX_0F38BD */
4946 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4949 /* PREFIX_VEX_0F38BE */
4953 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
4956 /* PREFIX_VEX_0F38BF */
4960 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4963 /* PREFIX_VEX_0F38DB */
4967 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
4970 /* PREFIX_VEX_0F38DC */
4974 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
4977 /* PREFIX_VEX_0F38DD */
4981 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
4984 /* PREFIX_VEX_0F38DE */
4988 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
4991 /* PREFIX_VEX_0F38DF */
4995 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
4998 /* PREFIX_VEX_0F38F2 */
5000 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
5003 /* PREFIX_VEX_0F38F3_REG_1 */
5005 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
5008 /* PREFIX_VEX_0F38F3_REG_2 */
5010 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
5013 /* PREFIX_VEX_0F38F3_REG_3 */
5015 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
5018 /* PREFIX_VEX_0F38F7 */
5020 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
5023 /* PREFIX_VEX_0F3A04 */
5027 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
5030 /* PREFIX_VEX_0F3A05 */
5034 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
5037 /* PREFIX_VEX_0F3A06 */
5041 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
5044 /* PREFIX_VEX_0F3A08 */
5048 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
5051 /* PREFIX_VEX_0F3A09 */
5055 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
5058 /* PREFIX_VEX_0F3A0A */
5062 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
5065 /* PREFIX_VEX_0F3A0B */
5069 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
5072 /* PREFIX_VEX_0F3A0C */
5076 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
5079 /* PREFIX_VEX_0F3A0D */
5083 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
5086 /* PREFIX_VEX_0F3A0E */
5090 { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2
) },
5093 /* PREFIX_VEX_0F3A0F */
5097 { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2
) },
5100 /* PREFIX_VEX_0F3A14 */
5104 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
5107 /* PREFIX_VEX_0F3A15 */
5111 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
5114 /* PREFIX_VEX_0F3A16 */
5118 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
5121 /* PREFIX_VEX_0F3A17 */
5125 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
5128 /* PREFIX_VEX_0F3A18 */
5132 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
5135 /* PREFIX_VEX_0F3A19 */
5139 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
5142 /* PREFIX_VEX_0F3A1D */
5146 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
5149 /* PREFIX_VEX_0F3A20 */
5153 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
5156 /* PREFIX_VEX_0F3A21 */
5160 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
5163 /* PREFIX_VEX_0F3A22 */
5167 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
5170 /* PREFIX_VEX_0F3A40 */
5174 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
5177 /* PREFIX_VEX_0F3A41 */
5181 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
5184 /* PREFIX_VEX_0F3A42 */
5188 { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2
) },
5191 /* PREFIX_VEX_0F3A44 */
5195 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
5198 /* PREFIX_VEX_0F3A48 */
5202 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
5205 /* PREFIX_VEX_0F3A49 */
5209 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
5212 /* PREFIX_VEX_0F3A4A */
5216 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
5219 /* PREFIX_VEX_0F3A4B */
5223 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
5226 /* PREFIX_VEX_0F3A4C */
5230 { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2
) },
5233 /* PREFIX_VEX_0F3A5C */
5237 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5240 /* PREFIX_VEX_0F3A5D */
5244 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5247 /* PREFIX_VEX_0F3A5E */
5251 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5254 /* PREFIX_VEX_0F3A5F */
5258 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5261 /* PREFIX_VEX_0F3A60 */
5265 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
5269 /* PREFIX_VEX_0F3A61 */
5273 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
5276 /* PREFIX_VEX_0F3A62 */
5280 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
5283 /* PREFIX_VEX_0F3A63 */
5287 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
5290 /* PREFIX_VEX_0F3A68 */
5294 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5297 /* PREFIX_VEX_0F3A69 */
5301 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5304 /* PREFIX_VEX_0F3A6A */
5308 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
5311 /* PREFIX_VEX_0F3A6B */
5315 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
5318 /* PREFIX_VEX_0F3A6C */
5322 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5325 /* PREFIX_VEX_0F3A6D */
5329 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5332 /* PREFIX_VEX_0F3A6E */
5336 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
5339 /* PREFIX_VEX_0F3A6F */
5343 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
5346 /* PREFIX_VEX_0F3A78 */
5350 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5353 /* PREFIX_VEX_0F3A79 */
5357 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5360 /* PREFIX_VEX_0F3A7A */
5364 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
5367 /* PREFIX_VEX_0F3A7B */
5371 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
5374 /* PREFIX_VEX_0F3A7C */
5378 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5382 /* PREFIX_VEX_0F3A7D */
5386 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5389 /* PREFIX_VEX_0F3A7E */
5393 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
5396 /* PREFIX_VEX_0F3A7F */
5400 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
5403 /* PREFIX_VEX_0F3ADF */
5407 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
5411 static const struct dis386 x86_64_table
[][2] = {
5414 { "pushP", { es
} },
5424 { "pushP", { cs
} },
5429 { "pushP", { ss
} },
5439 { "pushP", { ds
} },
5469 { "pushaP", { XX
} },
5474 { "popaP", { XX
} },
5479 { MOD_TABLE (MOD_62_32BIT
) },
5484 { "arpl", { Ew
, Gw
} },
5485 { "movs{lq|xd}", { Gv
, Ed
} },
5490 { "ins{R|}", { Yzr
, indirDX
} },
5491 { "ins{G|}", { Yzr
, indirDX
} },
5496 { "outs{R|}", { indirDXr
, Xz
} },
5497 { "outs{G|}", { indirDXr
, Xz
} },
5502 { "Jcall{T|}", { Ap
} },
5507 { MOD_TABLE (MOD_C4_32BIT
) },
5508 { VEX_C4_TABLE (VEX_0F
) },
5513 { MOD_TABLE (MOD_C5_32BIT
) },
5514 { VEX_C5_TABLE (VEX_0F
) },
5534 { "Jjmp{T|}", { Ap
} },
5537 /* X86_64_0F01_REG_0 */
5539 { "sgdt{Q|IQ}", { M
} },
5543 /* X86_64_0F01_REG_1 */
5545 { "sidt{Q|IQ}", { M
} },
5549 /* X86_64_0F01_REG_2 */
5551 { "lgdt{Q|Q}", { M
} },
5555 /* X86_64_0F01_REG_3 */
5557 { "lidt{Q|Q}", { M
} },
5562 static const struct dis386 three_byte_table
[][256] = {
5564 /* THREE_BYTE_0F38 */
5567 { "pshufb", { MX
, EM
} },
5568 { "phaddw", { MX
, EM
} },
5569 { "phaddd", { MX
, EM
} },
5570 { "phaddsw", { MX
, EM
} },
5571 { "pmaddubsw", { MX
, EM
} },
5572 { "phsubw", { MX
, EM
} },
5573 { "phsubd", { MX
, EM
} },
5574 { "phsubsw", { MX
, EM
} },
5576 { "psignb", { MX
, EM
} },
5577 { "psignw", { MX
, EM
} },
5578 { "psignd", { MX
, EM
} },
5579 { "pmulhrsw", { MX
, EM
} },
5585 { PREFIX_TABLE (PREFIX_0F3810
) },
5589 { PREFIX_TABLE (PREFIX_0F3814
) },
5590 { PREFIX_TABLE (PREFIX_0F3815
) },
5592 { PREFIX_TABLE (PREFIX_0F3817
) },
5598 { "pabsb", { MX
, EM
} },
5599 { "pabsw", { MX
, EM
} },
5600 { "pabsd", { MX
, EM
} },
5603 { PREFIX_TABLE (PREFIX_0F3820
) },
5604 { PREFIX_TABLE (PREFIX_0F3821
) },
5605 { PREFIX_TABLE (PREFIX_0F3822
) },
5606 { PREFIX_TABLE (PREFIX_0F3823
) },
5607 { PREFIX_TABLE (PREFIX_0F3824
) },
5608 { PREFIX_TABLE (PREFIX_0F3825
) },
5612 { PREFIX_TABLE (PREFIX_0F3828
) },
5613 { PREFIX_TABLE (PREFIX_0F3829
) },
5614 { PREFIX_TABLE (PREFIX_0F382A
) },
5615 { PREFIX_TABLE (PREFIX_0F382B
) },
5621 { PREFIX_TABLE (PREFIX_0F3830
) },
5622 { PREFIX_TABLE (PREFIX_0F3831
) },
5623 { PREFIX_TABLE (PREFIX_0F3832
) },
5624 { PREFIX_TABLE (PREFIX_0F3833
) },
5625 { PREFIX_TABLE (PREFIX_0F3834
) },
5626 { PREFIX_TABLE (PREFIX_0F3835
) },
5628 { PREFIX_TABLE (PREFIX_0F3837
) },
5630 { PREFIX_TABLE (PREFIX_0F3838
) },
5631 { PREFIX_TABLE (PREFIX_0F3839
) },
5632 { PREFIX_TABLE (PREFIX_0F383A
) },
5633 { PREFIX_TABLE (PREFIX_0F383B
) },
5634 { PREFIX_TABLE (PREFIX_0F383C
) },
5635 { PREFIX_TABLE (PREFIX_0F383D
) },
5636 { PREFIX_TABLE (PREFIX_0F383E
) },
5637 { PREFIX_TABLE (PREFIX_0F383F
) },
5639 { PREFIX_TABLE (PREFIX_0F3840
) },
5640 { PREFIX_TABLE (PREFIX_0F3841
) },
5711 { PREFIX_TABLE (PREFIX_0F3880
) },
5712 { PREFIX_TABLE (PREFIX_0F3881
) },
5813 { PREFIX_TABLE (PREFIX_0F38DB
) },
5814 { PREFIX_TABLE (PREFIX_0F38DC
) },
5815 { PREFIX_TABLE (PREFIX_0F38DD
) },
5816 { PREFIX_TABLE (PREFIX_0F38DE
) },
5817 { PREFIX_TABLE (PREFIX_0F38DF
) },
5837 { PREFIX_TABLE (PREFIX_0F38F0
) },
5838 { PREFIX_TABLE (PREFIX_0F38F1
) },
5855 /* THREE_BYTE_0F3A */
5867 { PREFIX_TABLE (PREFIX_0F3A08
) },
5868 { PREFIX_TABLE (PREFIX_0F3A09
) },
5869 { PREFIX_TABLE (PREFIX_0F3A0A
) },
5870 { PREFIX_TABLE (PREFIX_0F3A0B
) },
5871 { PREFIX_TABLE (PREFIX_0F3A0C
) },
5872 { PREFIX_TABLE (PREFIX_0F3A0D
) },
5873 { PREFIX_TABLE (PREFIX_0F3A0E
) },
5874 { "palignr", { MX
, EM
, Ib
} },
5880 { PREFIX_TABLE (PREFIX_0F3A14
) },
5881 { PREFIX_TABLE (PREFIX_0F3A15
) },
5882 { PREFIX_TABLE (PREFIX_0F3A16
) },
5883 { PREFIX_TABLE (PREFIX_0F3A17
) },
5894 { PREFIX_TABLE (PREFIX_0F3A20
) },
5895 { PREFIX_TABLE (PREFIX_0F3A21
) },
5896 { PREFIX_TABLE (PREFIX_0F3A22
) },
5930 { PREFIX_TABLE (PREFIX_0F3A40
) },
5931 { PREFIX_TABLE (PREFIX_0F3A41
) },
5932 { PREFIX_TABLE (PREFIX_0F3A42
) },
5934 { PREFIX_TABLE (PREFIX_0F3A44
) },
5966 { PREFIX_TABLE (PREFIX_0F3A60
) },
5967 { PREFIX_TABLE (PREFIX_0F3A61
) },
5968 { PREFIX_TABLE (PREFIX_0F3A62
) },
5969 { PREFIX_TABLE (PREFIX_0F3A63
) },
6108 { PREFIX_TABLE (PREFIX_0F3ADF
) },
6147 /* THREE_BYTE_0F7A */
6186 { "ptest", { XX
} },
6223 { "phaddbw", { XM
, EXq
} },
6224 { "phaddbd", { XM
, EXq
} },
6225 { "phaddbq", { XM
, EXq
} },
6228 { "phaddwd", { XM
, EXq
} },
6229 { "phaddwq", { XM
, EXq
} },
6234 { "phadddq", { XM
, EXq
} },
6241 { "phaddubw", { XM
, EXq
} },
6242 { "phaddubd", { XM
, EXq
} },
6243 { "phaddubq", { XM
, EXq
} },
6246 { "phadduwd", { XM
, EXq
} },
6247 { "phadduwq", { XM
, EXq
} },
6252 { "phaddudq", { XM
, EXq
} },
6259 { "phsubbw", { XM
, EXq
} },
6260 { "phsubbd", { XM
, EXq
} },
6261 { "phsubbq", { XM
, EXq
} },
6440 static const struct dis386 xop_table
[][256] = {
6593 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6594 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6595 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6603 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6604 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6611 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6612 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6613 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6621 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6622 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6626 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6627 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6630 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6648 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6660 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
6661 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
6662 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
6663 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
6673 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
6674 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
6675 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
6676 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
6709 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
6710 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
6711 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
6712 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
6755 { REG_TABLE (REG_XOP_LWPCB
) },
6879 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
6880 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
6881 { "vfrczss", { XM
, EXd
} },
6882 { "vfrczsd", { XM
, EXq
} },
6897 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6898 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6899 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
6900 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6901 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6902 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6903 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
6904 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6906 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
6907 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6908 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
6909 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6952 { "vphaddbw", { XM
, EXxmm
} },
6953 { "vphaddbd", { XM
, EXxmm
} },
6954 { "vphaddbq", { XM
, EXxmm
} },
6957 { "vphaddwd", { XM
, EXxmm
} },
6958 { "vphaddwq", { XM
, EXxmm
} },
6963 { "vphadddq", { XM
, EXxmm
} },
6970 { "vphaddubw", { XM
, EXxmm
} },
6971 { "vphaddubd", { XM
, EXxmm
} },
6972 { "vphaddubq", { XM
, EXxmm
} },
6975 { "vphadduwd", { XM
, EXxmm
} },
6976 { "vphadduwq", { XM
, EXxmm
} },
6981 { "vphaddudq", { XM
, EXxmm
} },
6988 { "vphsubbw", { XM
, EXxmm
} },
6989 { "vphsubwd", { XM
, EXxmm
} },
6990 { "vphsubdq", { XM
, EXxmm
} },
7046 { REG_TABLE (REG_XOP_LWP
) },
7316 static const struct dis386 vex_table
[][256] = {
7338 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
7339 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
7340 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
7341 { MOD_TABLE (MOD_VEX_0F13
) },
7342 { VEX_W_TABLE (VEX_W_0F14
) },
7343 { VEX_W_TABLE (VEX_W_0F15
) },
7344 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
7345 { MOD_TABLE (MOD_VEX_0F17
) },
7365 { VEX_W_TABLE (VEX_W_0F28
) },
7366 { VEX_W_TABLE (VEX_W_0F29
) },
7367 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
7368 { MOD_TABLE (MOD_VEX_0F2B
) },
7369 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
7370 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
7371 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
7372 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
7410 { MOD_TABLE (MOD_VEX_0F50
) },
7411 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
7412 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
7413 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
7414 { "vandpX", { XM
, Vex
, EXx
} },
7415 { "vandnpX", { XM
, Vex
, EXx
} },
7416 { "vorpX", { XM
, Vex
, EXx
} },
7417 { "vxorpX", { XM
, Vex
, EXx
} },
7419 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
7420 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
7421 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
7422 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
7423 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
7424 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
7425 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
7426 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
7428 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
7429 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
7430 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
7431 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
7432 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
7433 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
7434 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
7435 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
7437 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
7438 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
7439 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
7440 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
7441 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
7442 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
7443 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
7444 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
7446 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
7447 { REG_TABLE (REG_VEX_0F71
) },
7448 { REG_TABLE (REG_VEX_0F72
) },
7449 { REG_TABLE (REG_VEX_0F73
) },
7450 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
7451 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
7452 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
7453 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
7459 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
7460 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
7461 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
7462 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
7515 { REG_TABLE (REG_VEX_0FAE
) },
7538 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
7540 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
7541 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
7542 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
7554 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
7555 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
7556 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
7557 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
7558 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
7559 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
7560 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
7561 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
7563 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
7564 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
7565 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
7566 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
7567 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
7568 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
7569 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
7570 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
7572 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
7573 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
7574 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
7575 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
7576 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
7577 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
7578 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
7579 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
7581 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
7582 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
7583 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
7584 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
7585 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
7586 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
7587 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
7588 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
7590 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
7591 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
7592 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
7593 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
7594 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
7595 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
7596 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
7597 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
7599 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
7600 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
7601 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
7602 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
7603 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
7604 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
7605 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
7611 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
7612 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
7613 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
7614 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
7615 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
7616 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
7617 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
7618 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
7620 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
7621 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
7622 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
7623 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
7624 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
7625 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
7626 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
7627 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
7632 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
7636 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
7638 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
7639 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
7640 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
7642 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
7643 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
7644 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
7647 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
7648 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
7649 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
7650 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
7651 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
7652 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
7656 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
7657 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
7658 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
7659 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
7660 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
7661 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
7662 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
7663 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
7665 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
7666 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
7667 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
7668 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
7669 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
7670 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
7672 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
7674 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
7675 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
7676 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
7677 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
7678 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
7679 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
7680 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
7681 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
7683 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
7684 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
7779 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
7780 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
7782 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
7783 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
7784 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
7785 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
7786 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
7787 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
7788 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
7789 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
7797 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
7798 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
7800 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
7801 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
7802 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
7803 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
7804 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
7805 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
7806 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
7807 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
7815 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
7816 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
7818 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
7819 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
7820 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
7821 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
7822 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
7823 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
7824 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
7825 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
7857 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
7858 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
7859 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
7860 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
7861 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
7883 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
7884 { REG_TABLE (REG_VEX_0F38F3
) },
7888 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
7906 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
7907 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
7908 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
7911 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
7912 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
7913 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
7914 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
7915 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
7916 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
7917 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
7918 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
7924 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
7925 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
7926 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
7927 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
7929 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
7930 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
7934 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
7938 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
7939 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
7940 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
7974 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
7975 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
7976 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
7978 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
7983 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
7984 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
7985 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
7986 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
7987 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
8005 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
8006 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
8007 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
8008 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
8010 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
8011 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
8012 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
8013 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
8019 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
8020 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
8021 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
8022 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
8023 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
8024 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
8025 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
8026 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
8037 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
8038 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
8039 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
8040 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
8041 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
8042 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
8043 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
8044 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
8152 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
8192 static const struct dis386 vex_len_table
[][2] = {
8193 /* VEX_LEN_0F10_P_1 */
8195 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
8196 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
8199 /* VEX_LEN_0F10_P_3 */
8201 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
8202 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
8205 /* VEX_LEN_0F11_P_1 */
8207 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
8208 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
8211 /* VEX_LEN_0F11_P_3 */
8213 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
8214 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
8217 /* VEX_LEN_0F12_P_0_M_0 */
8219 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
8222 /* VEX_LEN_0F12_P_0_M_1 */
8224 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
8227 /* VEX_LEN_0F12_P_2 */
8229 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
8232 /* VEX_LEN_0F13_M_0 */
8234 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
8237 /* VEX_LEN_0F16_P_0_M_0 */
8239 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
8242 /* VEX_LEN_0F16_P_0_M_1 */
8244 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
8247 /* VEX_LEN_0F16_P_2 */
8249 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
8252 /* VEX_LEN_0F17_M_0 */
8254 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
8257 /* VEX_LEN_0F2A_P_1 */
8259 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8260 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8263 /* VEX_LEN_0F2A_P_3 */
8265 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8266 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8269 /* VEX_LEN_0F2C_P_1 */
8271 { "vcvttss2siY", { Gv
, EXdScalar
} },
8272 { "vcvttss2siY", { Gv
, EXdScalar
} },
8275 /* VEX_LEN_0F2C_P_3 */
8277 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8278 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8281 /* VEX_LEN_0F2D_P_1 */
8283 { "vcvtss2siY", { Gv
, EXdScalar
} },
8284 { "vcvtss2siY", { Gv
, EXdScalar
} },
8287 /* VEX_LEN_0F2D_P_3 */
8289 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8290 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8293 /* VEX_LEN_0F2E_P_0 */
8295 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
8296 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
8299 /* VEX_LEN_0F2E_P_2 */
8301 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
8302 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
8305 /* VEX_LEN_0F2F_P_0 */
8307 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
8308 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
8311 /* VEX_LEN_0F2F_P_2 */
8313 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
8314 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
8317 /* VEX_LEN_0F51_P_1 */
8319 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
8320 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
8323 /* VEX_LEN_0F51_P_3 */
8325 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
8326 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
8329 /* VEX_LEN_0F52_P_1 */
8331 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
8332 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
8335 /* VEX_LEN_0F53_P_1 */
8337 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
8338 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
8341 /* VEX_LEN_0F58_P_1 */
8343 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
8344 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
8347 /* VEX_LEN_0F58_P_3 */
8349 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
8350 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
8353 /* VEX_LEN_0F59_P_1 */
8355 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
8356 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
8359 /* VEX_LEN_0F59_P_3 */
8361 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
8362 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
8365 /* VEX_LEN_0F5A_P_1 */
8367 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
8368 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
8371 /* VEX_LEN_0F5A_P_3 */
8373 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
8374 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
8377 /* VEX_LEN_0F5C_P_1 */
8379 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
8380 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
8383 /* VEX_LEN_0F5C_P_3 */
8385 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
8386 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
8389 /* VEX_LEN_0F5D_P_1 */
8391 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
8392 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
8395 /* VEX_LEN_0F5D_P_3 */
8397 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
8398 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
8401 /* VEX_LEN_0F5E_P_1 */
8403 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
8404 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
8407 /* VEX_LEN_0F5E_P_3 */
8409 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
8410 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
8413 /* VEX_LEN_0F5F_P_1 */
8415 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
8416 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
8419 /* VEX_LEN_0F5F_P_3 */
8421 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
8422 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
8425 /* VEX_LEN_0F60_P_2 */
8427 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
8430 /* VEX_LEN_0F61_P_2 */
8432 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
8435 /* VEX_LEN_0F62_P_2 */
8437 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
8440 /* VEX_LEN_0F63_P_2 */
8442 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
8445 /* VEX_LEN_0F64_P_2 */
8447 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
8450 /* VEX_LEN_0F65_P_2 */
8452 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
8455 /* VEX_LEN_0F66_P_2 */
8457 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
8460 /* VEX_LEN_0F67_P_2 */
8462 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
8465 /* VEX_LEN_0F68_P_2 */
8467 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
8470 /* VEX_LEN_0F69_P_2 */
8472 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
8475 /* VEX_LEN_0F6A_P_2 */
8477 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
8480 /* VEX_LEN_0F6B_P_2 */
8482 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
8485 /* VEX_LEN_0F6C_P_2 */
8487 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
8490 /* VEX_LEN_0F6D_P_2 */
8492 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
8495 /* VEX_LEN_0F6E_P_2 */
8497 { "vmovK", { XMScalar
, Edq
} },
8498 { "vmovK", { XMScalar
, Edq
} },
8501 /* VEX_LEN_0F70_P_1 */
8503 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
8506 /* VEX_LEN_0F70_P_2 */
8508 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
8511 /* VEX_LEN_0F70_P_3 */
8513 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
8516 /* VEX_LEN_0F71_R_2_P_2 */
8518 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
8521 /* VEX_LEN_0F71_R_4_P_2 */
8523 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
8526 /* VEX_LEN_0F71_R_6_P_2 */
8528 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
8531 /* VEX_LEN_0F72_R_2_P_2 */
8533 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
8536 /* VEX_LEN_0F72_R_4_P_2 */
8538 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
8541 /* VEX_LEN_0F72_R_6_P_2 */
8543 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
8546 /* VEX_LEN_0F73_R_2_P_2 */
8548 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
8551 /* VEX_LEN_0F73_R_3_P_2 */
8553 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
8556 /* VEX_LEN_0F73_R_6_P_2 */
8558 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
8561 /* VEX_LEN_0F73_R_7_P_2 */
8563 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
8566 /* VEX_LEN_0F74_P_2 */
8568 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
8571 /* VEX_LEN_0F75_P_2 */
8573 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
8576 /* VEX_LEN_0F76_P_2 */
8578 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
8581 /* VEX_LEN_0F7E_P_1 */
8583 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
8584 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
8587 /* VEX_LEN_0F7E_P_2 */
8589 { "vmovK", { Edq
, XMScalar
} },
8590 { "vmovK", { Edq
, XMScalar
} },
8593 /* VEX_LEN_0FAE_R_2_M_0 */
8595 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
8598 /* VEX_LEN_0FAE_R_3_M_0 */
8600 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
8603 /* VEX_LEN_0FC2_P_1 */
8605 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
8606 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
8609 /* VEX_LEN_0FC2_P_3 */
8611 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
8612 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
8615 /* VEX_LEN_0FC4_P_2 */
8617 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
8620 /* VEX_LEN_0FC5_P_2 */
8622 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
8625 /* VEX_LEN_0FD1_P_2 */
8627 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
8630 /* VEX_LEN_0FD2_P_2 */
8632 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
8635 /* VEX_LEN_0FD3_P_2 */
8637 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
8640 /* VEX_LEN_0FD4_P_2 */
8642 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
8645 /* VEX_LEN_0FD5_P_2 */
8647 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
8650 /* VEX_LEN_0FD6_P_2 */
8652 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
8653 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
8656 /* VEX_LEN_0FD7_P_2_M_1 */
8658 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
8661 /* VEX_LEN_0FD8_P_2 */
8663 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
8666 /* VEX_LEN_0FD9_P_2 */
8668 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
8671 /* VEX_LEN_0FDA_P_2 */
8673 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
8676 /* VEX_LEN_0FDB_P_2 */
8678 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
8681 /* VEX_LEN_0FDC_P_2 */
8683 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
8686 /* VEX_LEN_0FDD_P_2 */
8688 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
8691 /* VEX_LEN_0FDE_P_2 */
8693 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
8696 /* VEX_LEN_0FDF_P_2 */
8698 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
8701 /* VEX_LEN_0FE0_P_2 */
8703 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
8706 /* VEX_LEN_0FE1_P_2 */
8708 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
8711 /* VEX_LEN_0FE2_P_2 */
8713 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
8716 /* VEX_LEN_0FE3_P_2 */
8718 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
8721 /* VEX_LEN_0FE4_P_2 */
8723 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
8726 /* VEX_LEN_0FE5_P_2 */
8728 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
8731 /* VEX_LEN_0FE8_P_2 */
8733 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
8736 /* VEX_LEN_0FE9_P_2 */
8738 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
8741 /* VEX_LEN_0FEA_P_2 */
8743 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
8746 /* VEX_LEN_0FEB_P_2 */
8748 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
8751 /* VEX_LEN_0FEC_P_2 */
8753 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
8756 /* VEX_LEN_0FED_P_2 */
8758 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
8761 /* VEX_LEN_0FEE_P_2 */
8763 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
8766 /* VEX_LEN_0FEF_P_2 */
8768 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
8771 /* VEX_LEN_0FF1_P_2 */
8773 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
8776 /* VEX_LEN_0FF2_P_2 */
8778 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
8781 /* VEX_LEN_0FF3_P_2 */
8783 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
8786 /* VEX_LEN_0FF4_P_2 */
8788 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
8791 /* VEX_LEN_0FF5_P_2 */
8793 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
8796 /* VEX_LEN_0FF6_P_2 */
8798 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
8801 /* VEX_LEN_0FF7_P_2 */
8803 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
8806 /* VEX_LEN_0FF8_P_2 */
8808 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
8811 /* VEX_LEN_0FF9_P_2 */
8813 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
8816 /* VEX_LEN_0FFA_P_2 */
8818 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
8821 /* VEX_LEN_0FFB_P_2 */
8823 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
8826 /* VEX_LEN_0FFC_P_2 */
8828 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
8831 /* VEX_LEN_0FFD_P_2 */
8833 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
8836 /* VEX_LEN_0FFE_P_2 */
8838 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
8841 /* VEX_LEN_0F3800_P_2 */
8843 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
8846 /* VEX_LEN_0F3801_P_2 */
8848 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
8851 /* VEX_LEN_0F3802_P_2 */
8853 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
8856 /* VEX_LEN_0F3803_P_2 */
8858 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
8861 /* VEX_LEN_0F3804_P_2 */
8863 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
8866 /* VEX_LEN_0F3805_P_2 */
8868 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
8871 /* VEX_LEN_0F3806_P_2 */
8873 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
8876 /* VEX_LEN_0F3807_P_2 */
8878 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
8881 /* VEX_LEN_0F3808_P_2 */
8883 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
8886 /* VEX_LEN_0F3809_P_2 */
8888 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
8891 /* VEX_LEN_0F380A_P_2 */
8893 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
8896 /* VEX_LEN_0F380B_P_2 */
8898 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
8901 /* VEX_LEN_0F3819_P_2_M_0 */
8904 { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0
) },
8907 /* VEX_LEN_0F381A_P_2_M_0 */
8910 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
8913 /* VEX_LEN_0F381C_P_2 */
8915 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
8918 /* VEX_LEN_0F381D_P_2 */
8920 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
8923 /* VEX_LEN_0F381E_P_2 */
8925 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
8928 /* VEX_LEN_0F3820_P_2 */
8930 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
8933 /* VEX_LEN_0F3821_P_2 */
8935 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
8938 /* VEX_LEN_0F3822_P_2 */
8940 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
8943 /* VEX_LEN_0F3823_P_2 */
8945 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
8948 /* VEX_LEN_0F3824_P_2 */
8950 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
8953 /* VEX_LEN_0F3825_P_2 */
8955 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
8958 /* VEX_LEN_0F3828_P_2 */
8960 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
8963 /* VEX_LEN_0F3829_P_2 */
8965 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
8968 /* VEX_LEN_0F382A_P_2_M_0 */
8970 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
8973 /* VEX_LEN_0F382B_P_2 */
8975 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
8978 /* VEX_LEN_0F3830_P_2 */
8980 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
8983 /* VEX_LEN_0F3831_P_2 */
8985 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
8988 /* VEX_LEN_0F3832_P_2 */
8990 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
8993 /* VEX_LEN_0F3833_P_2 */
8995 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
8998 /* VEX_LEN_0F3834_P_2 */
9000 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
9003 /* VEX_LEN_0F3835_P_2 */
9005 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
9008 /* VEX_LEN_0F3837_P_2 */
9010 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
9013 /* VEX_LEN_0F3838_P_2 */
9015 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
9018 /* VEX_LEN_0F3839_P_2 */
9020 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
9023 /* VEX_LEN_0F383A_P_2 */
9025 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
9028 /* VEX_LEN_0F383B_P_2 */
9030 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
9033 /* VEX_LEN_0F383C_P_2 */
9035 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
9038 /* VEX_LEN_0F383D_P_2 */
9040 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
9043 /* VEX_LEN_0F383E_P_2 */
9045 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
9048 /* VEX_LEN_0F383F_P_2 */
9050 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
9053 /* VEX_LEN_0F3840_P_2 */
9055 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
9058 /* VEX_LEN_0F3841_P_2 */
9060 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9063 /* VEX_LEN_0F38DB_P_2 */
9065 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9068 /* VEX_LEN_0F38DC_P_2 */
9070 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9073 /* VEX_LEN_0F38DD_P_2 */
9075 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9078 /* VEX_LEN_0F38DE_P_2 */
9080 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9083 /* VEX_LEN_0F38DF_P_2 */
9085 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9088 /* VEX_LEN_0F38F2_P_0 */
9090 { "andnS", { Gdq
, VexGdq
, Edq
} },
9093 /* VEX_LEN_0F38F3_R_1_P_0 */
9095 { "blsrS", { VexGdq
, Edq
} },
9098 /* VEX_LEN_0F38F3_R_2_P_0 */
9100 { "blsmskS", { VexGdq
, Edq
} },
9103 /* VEX_LEN_0F38F3_R_3_P_0 */
9105 { "blsiS", { VexGdq
, Edq
} },
9108 /* VEX_LEN_0F38F7_P_0 */
9110 { "bextrS", { Gdq
, Edq
, VexGdq
} },
9113 /* VEX_LEN_0F3A06_P_2 */
9116 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9119 /* VEX_LEN_0F3A0A_P_2 */
9121 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9122 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9125 /* VEX_LEN_0F3A0B_P_2 */
9127 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9128 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9131 /* VEX_LEN_0F3A0E_P_2 */
9133 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
9136 /* VEX_LEN_0F3A0F_P_2 */
9138 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
9141 /* VEX_LEN_0F3A14_P_2 */
9143 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
9146 /* VEX_LEN_0F3A15_P_2 */
9148 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
9151 /* VEX_LEN_0F3A16_P_2 */
9153 { "vpextrK", { Edq
, XM
, Ib
} },
9156 /* VEX_LEN_0F3A17_P_2 */
9158 { "vextractps", { Edqd
, XM
, Ib
} },
9161 /* VEX_LEN_0F3A18_P_2 */
9164 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9167 /* VEX_LEN_0F3A19_P_2 */
9170 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9173 /* VEX_LEN_0F3A20_P_2 */
9175 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
9178 /* VEX_LEN_0F3A21_P_2 */
9180 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
9183 /* VEX_LEN_0F3A22_P_2 */
9185 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
9188 /* VEX_LEN_0F3A41_P_2 */
9190 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
9193 /* VEX_LEN_0F3A42_P_2 */
9195 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
9198 /* VEX_LEN_0F3A44_P_2 */
9200 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
9203 /* VEX_LEN_0F3A4C_P_2 */
9205 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
9208 /* VEX_LEN_0F3A60_P_2 */
9210 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
9213 /* VEX_LEN_0F3A61_P_2 */
9215 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
9218 /* VEX_LEN_0F3A62_P_2 */
9220 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
9223 /* VEX_LEN_0F3A63_P_2 */
9225 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
9228 /* VEX_LEN_0F3A6A_P_2 */
9230 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9233 /* VEX_LEN_0F3A6B_P_2 */
9235 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9238 /* VEX_LEN_0F3A6E_P_2 */
9240 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9243 /* VEX_LEN_0F3A6F_P_2 */
9245 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9248 /* VEX_LEN_0F3A7A_P_2 */
9250 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9253 /* VEX_LEN_0F3A7B_P_2 */
9255 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9258 /* VEX_LEN_0F3A7E_P_2 */
9260 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9263 /* VEX_LEN_0F3A7F_P_2 */
9265 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9268 /* VEX_LEN_0F3ADF_P_2 */
9270 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
9273 /* VEX_LEN_0FXOP_09_80 */
9275 { "vfrczps", { XM
, EXxmm
} },
9276 { "vfrczps", { XM
, EXymmq
} },
9279 /* VEX_LEN_0FXOP_09_81 */
9281 { "vfrczpd", { XM
, EXxmm
} },
9282 { "vfrczpd", { XM
, EXymmq
} },
9286 static const struct dis386 vex_w_table
[][2] = {
9288 /* VEX_W_0F10_P_0 */
9289 { "vmovups", { XM
, EXx
} },
9292 /* VEX_W_0F10_P_1 */
9293 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
9296 /* VEX_W_0F10_P_2 */
9297 { "vmovupd", { XM
, EXx
} },
9300 /* VEX_W_0F10_P_3 */
9301 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
9304 /* VEX_W_0F11_P_0 */
9305 { "vmovups", { EXxS
, XM
} },
9308 /* VEX_W_0F11_P_1 */
9309 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
9312 /* VEX_W_0F11_P_2 */
9313 { "vmovupd", { EXxS
, XM
} },
9316 /* VEX_W_0F11_P_3 */
9317 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
9320 /* VEX_W_0F12_P_0_M_0 */
9321 { "vmovlps", { XM
, Vex128
, EXq
} },
9324 /* VEX_W_0F12_P_0_M_1 */
9325 { "vmovhlps", { XM
, Vex128
, EXq
} },
9328 /* VEX_W_0F12_P_1 */
9329 { "vmovsldup", { XM
, EXx
} },
9332 /* VEX_W_0F12_P_2 */
9333 { "vmovlpd", { XM
, Vex128
, EXq
} },
9336 /* VEX_W_0F12_P_3 */
9337 { "vmovddup", { XM
, EXymmq
} },
9340 /* VEX_W_0F13_M_0 */
9341 { "vmovlpX", { EXq
, XM
} },
9345 { "vunpcklpX", { XM
, Vex
, EXx
} },
9349 { "vunpckhpX", { XM
, Vex
, EXx
} },
9352 /* VEX_W_0F16_P_0_M_0 */
9353 { "vmovhps", { XM
, Vex128
, EXq
} },
9356 /* VEX_W_0F16_P_0_M_1 */
9357 { "vmovlhps", { XM
, Vex128
, EXq
} },
9360 /* VEX_W_0F16_P_1 */
9361 { "vmovshdup", { XM
, EXx
} },
9364 /* VEX_W_0F16_P_2 */
9365 { "vmovhpd", { XM
, Vex128
, EXq
} },
9368 /* VEX_W_0F17_M_0 */
9369 { "vmovhpX", { EXq
, XM
} },
9373 { "vmovapX", { XM
, EXx
} },
9377 { "vmovapX", { EXxS
, XM
} },
9380 /* VEX_W_0F2B_M_0 */
9381 { "vmovntpX", { Mx
, XM
} },
9384 /* VEX_W_0F2E_P_0 */
9385 { "vucomiss", { XMScalar
, EXdScalar
} },
9388 /* VEX_W_0F2E_P_2 */
9389 { "vucomisd", { XMScalar
, EXqScalar
} },
9392 /* VEX_W_0F2F_P_0 */
9393 { "vcomiss", { XMScalar
, EXdScalar
} },
9396 /* VEX_W_0F2F_P_2 */
9397 { "vcomisd", { XMScalar
, EXqScalar
} },
9400 /* VEX_W_0F50_M_0 */
9401 { "vmovmskpX", { Gdq
, XS
} },
9404 /* VEX_W_0F51_P_0 */
9405 { "vsqrtps", { XM
, EXx
} },
9408 /* VEX_W_0F51_P_1 */
9409 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9412 /* VEX_W_0F51_P_2 */
9413 { "vsqrtpd", { XM
, EXx
} },
9416 /* VEX_W_0F51_P_3 */
9417 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
9420 /* VEX_W_0F52_P_0 */
9421 { "vrsqrtps", { XM
, EXx
} },
9424 /* VEX_W_0F52_P_1 */
9425 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9428 /* VEX_W_0F53_P_0 */
9429 { "vrcpps", { XM
, EXx
} },
9432 /* VEX_W_0F53_P_1 */
9433 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
9436 /* VEX_W_0F58_P_0 */
9437 { "vaddps", { XM
, Vex
, EXx
} },
9440 /* VEX_W_0F58_P_1 */
9441 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
9444 /* VEX_W_0F58_P_2 */
9445 { "vaddpd", { XM
, Vex
, EXx
} },
9448 /* VEX_W_0F58_P_3 */
9449 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
9452 /* VEX_W_0F59_P_0 */
9453 { "vmulps", { XM
, Vex
, EXx
} },
9456 /* VEX_W_0F59_P_1 */
9457 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
9460 /* VEX_W_0F59_P_2 */
9461 { "vmulpd", { XM
, Vex
, EXx
} },
9464 /* VEX_W_0F59_P_3 */
9465 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
9468 /* VEX_W_0F5A_P_0 */
9469 { "vcvtps2pd", { XM
, EXxmmq
} },
9472 /* VEX_W_0F5A_P_1 */
9473 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
9476 /* VEX_W_0F5A_P_3 */
9477 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
9480 /* VEX_W_0F5B_P_0 */
9481 { "vcvtdq2ps", { XM
, EXx
} },
9484 /* VEX_W_0F5B_P_1 */
9485 { "vcvttps2dq", { XM
, EXx
} },
9488 /* VEX_W_0F5B_P_2 */
9489 { "vcvtps2dq", { XM
, EXx
} },
9492 /* VEX_W_0F5C_P_0 */
9493 { "vsubps", { XM
, Vex
, EXx
} },
9496 /* VEX_W_0F5C_P_1 */
9497 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
9500 /* VEX_W_0F5C_P_2 */
9501 { "vsubpd", { XM
, Vex
, EXx
} },
9504 /* VEX_W_0F5C_P_3 */
9505 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
9508 /* VEX_W_0F5D_P_0 */
9509 { "vminps", { XM
, Vex
, EXx
} },
9512 /* VEX_W_0F5D_P_1 */
9513 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
9516 /* VEX_W_0F5D_P_2 */
9517 { "vminpd", { XM
, Vex
, EXx
} },
9520 /* VEX_W_0F5D_P_3 */
9521 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
9524 /* VEX_W_0F5E_P_0 */
9525 { "vdivps", { XM
, Vex
, EXx
} },
9528 /* VEX_W_0F5E_P_1 */
9529 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
9532 /* VEX_W_0F5E_P_2 */
9533 { "vdivpd", { XM
, Vex
, EXx
} },
9536 /* VEX_W_0F5E_P_3 */
9537 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
9540 /* VEX_W_0F5F_P_0 */
9541 { "vmaxps", { XM
, Vex
, EXx
} },
9544 /* VEX_W_0F5F_P_1 */
9545 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
9548 /* VEX_W_0F5F_P_2 */
9549 { "vmaxpd", { XM
, Vex
, EXx
} },
9552 /* VEX_W_0F5F_P_3 */
9553 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
9556 /* VEX_W_0F60_P_2 */
9557 { "vpunpcklbw", { XM
, Vex128
, EXx
} },
9560 /* VEX_W_0F61_P_2 */
9561 { "vpunpcklwd", { XM
, Vex128
, EXx
} },
9564 /* VEX_W_0F62_P_2 */
9565 { "vpunpckldq", { XM
, Vex128
, EXx
} },
9568 /* VEX_W_0F63_P_2 */
9569 { "vpacksswb", { XM
, Vex128
, EXx
} },
9572 /* VEX_W_0F64_P_2 */
9573 { "vpcmpgtb", { XM
, Vex128
, EXx
} },
9576 /* VEX_W_0F65_P_2 */
9577 { "vpcmpgtw", { XM
, Vex128
, EXx
} },
9580 /* VEX_W_0F66_P_2 */
9581 { "vpcmpgtd", { XM
, Vex128
, EXx
} },
9584 /* VEX_W_0F67_P_2 */
9585 { "vpackuswb", { XM
, Vex128
, EXx
} },
9588 /* VEX_W_0F68_P_2 */
9589 { "vpunpckhbw", { XM
, Vex128
, EXx
} },
9592 /* VEX_W_0F69_P_2 */
9593 { "vpunpckhwd", { XM
, Vex128
, EXx
} },
9596 /* VEX_W_0F6A_P_2 */
9597 { "vpunpckhdq", { XM
, Vex128
, EXx
} },
9600 /* VEX_W_0F6B_P_2 */
9601 { "vpackssdw", { XM
, Vex128
, EXx
} },
9604 /* VEX_W_0F6C_P_2 */
9605 { "vpunpcklqdq", { XM
, Vex128
, EXx
} },
9608 /* VEX_W_0F6D_P_2 */
9609 { "vpunpckhqdq", { XM
, Vex128
, EXx
} },
9612 /* VEX_W_0F6F_P_1 */
9613 { "vmovdqu", { XM
, EXx
} },
9616 /* VEX_W_0F6F_P_2 */
9617 { "vmovdqa", { XM
, EXx
} },
9620 /* VEX_W_0F70_P_1 */
9621 { "vpshufhw", { XM
, EXx
, Ib
} },
9624 /* VEX_W_0F70_P_2 */
9625 { "vpshufd", { XM
, EXx
, Ib
} },
9628 /* VEX_W_0F70_P_3 */
9629 { "vpshuflw", { XM
, EXx
, Ib
} },
9632 /* VEX_W_0F71_R_2_P_2 */
9633 { "vpsrlw", { Vex128
, XS
, Ib
} },
9636 /* VEX_W_0F71_R_4_P_2 */
9637 { "vpsraw", { Vex128
, XS
, Ib
} },
9640 /* VEX_W_0F71_R_6_P_2 */
9641 { "vpsllw", { Vex128
, XS
, Ib
} },
9644 /* VEX_W_0F72_R_2_P_2 */
9645 { "vpsrld", { Vex128
, XS
, Ib
} },
9648 /* VEX_W_0F72_R_4_P_2 */
9649 { "vpsrad", { Vex128
, XS
, Ib
} },
9652 /* VEX_W_0F72_R_6_P_2 */
9653 { "vpslld", { Vex128
, XS
, Ib
} },
9656 /* VEX_W_0F73_R_2_P_2 */
9657 { "vpsrlq", { Vex128
, XS
, Ib
} },
9660 /* VEX_W_0F73_R_3_P_2 */
9661 { "vpsrldq", { Vex128
, XS
, Ib
} },
9664 /* VEX_W_0F73_R_6_P_2 */
9665 { "vpsllq", { Vex128
, XS
, Ib
} },
9668 /* VEX_W_0F73_R_7_P_2 */
9669 { "vpslldq", { Vex128
, XS
, Ib
} },
9672 /* VEX_W_0F74_P_2 */
9673 { "vpcmpeqb", { XM
, Vex128
, EXx
} },
9676 /* VEX_W_0F75_P_2 */
9677 { "vpcmpeqw", { XM
, Vex128
, EXx
} },
9680 /* VEX_W_0F76_P_2 */
9681 { "vpcmpeqd", { XM
, Vex128
, EXx
} },
9684 /* VEX_W_0F77_P_0 */
9688 /* VEX_W_0F7C_P_2 */
9689 { "vhaddpd", { XM
, Vex
, EXx
} },
9692 /* VEX_W_0F7C_P_3 */
9693 { "vhaddps", { XM
, Vex
, EXx
} },
9696 /* VEX_W_0F7D_P_2 */
9697 { "vhsubpd", { XM
, Vex
, EXx
} },
9700 /* VEX_W_0F7D_P_3 */
9701 { "vhsubps", { XM
, Vex
, EXx
} },
9704 /* VEX_W_0F7E_P_1 */
9705 { "vmovq", { XMScalar
, EXqScalar
} },
9708 /* VEX_W_0F7F_P_1 */
9709 { "vmovdqu", { EXxS
, XM
} },
9712 /* VEX_W_0F7F_P_2 */
9713 { "vmovdqa", { EXxS
, XM
} },
9716 /* VEX_W_0FAE_R_2_M_0 */
9717 { "vldmxcsr", { Md
} },
9720 /* VEX_W_0FAE_R_3_M_0 */
9721 { "vstmxcsr", { Md
} },
9724 /* VEX_W_0FC2_P_0 */
9725 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
9728 /* VEX_W_0FC2_P_1 */
9729 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
9732 /* VEX_W_0FC2_P_2 */
9733 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
9736 /* VEX_W_0FC2_P_3 */
9737 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
9740 /* VEX_W_0FC4_P_2 */
9741 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
9744 /* VEX_W_0FC5_P_2 */
9745 { "vpextrw", { Gdq
, XS
, Ib
} },
9748 /* VEX_W_0FD0_P_2 */
9749 { "vaddsubpd", { XM
, Vex
, EXx
} },
9752 /* VEX_W_0FD0_P_3 */
9753 { "vaddsubps", { XM
, Vex
, EXx
} },
9756 /* VEX_W_0FD1_P_2 */
9757 { "vpsrlw", { XM
, Vex128
, EXx
} },
9760 /* VEX_W_0FD2_P_2 */
9761 { "vpsrld", { XM
, Vex128
, EXx
} },
9764 /* VEX_W_0FD3_P_2 */
9765 { "vpsrlq", { XM
, Vex128
, EXx
} },
9768 /* VEX_W_0FD4_P_2 */
9769 { "vpaddq", { XM
, Vex128
, EXx
} },
9772 /* VEX_W_0FD5_P_2 */
9773 { "vpmullw", { XM
, Vex128
, EXx
} },
9776 /* VEX_W_0FD6_P_2 */
9777 { "vmovq", { EXqScalarS
, XMScalar
} },
9780 /* VEX_W_0FD7_P_2_M_1 */
9781 { "vpmovmskb", { Gdq
, XS
} },
9784 /* VEX_W_0FD8_P_2 */
9785 { "vpsubusb", { XM
, Vex128
, EXx
} },
9788 /* VEX_W_0FD9_P_2 */
9789 { "vpsubusw", { XM
, Vex128
, EXx
} },
9792 /* VEX_W_0FDA_P_2 */
9793 { "vpminub", { XM
, Vex128
, EXx
} },
9796 /* VEX_W_0FDB_P_2 */
9797 { "vpand", { XM
, Vex128
, EXx
} },
9800 /* VEX_W_0FDC_P_2 */
9801 { "vpaddusb", { XM
, Vex128
, EXx
} },
9804 /* VEX_W_0FDD_P_2 */
9805 { "vpaddusw", { XM
, Vex128
, EXx
} },
9808 /* VEX_W_0FDE_P_2 */
9809 { "vpmaxub", { XM
, Vex128
, EXx
} },
9812 /* VEX_W_0FDF_P_2 */
9813 { "vpandn", { XM
, Vex128
, EXx
} },
9816 /* VEX_W_0FE0_P_2 */
9817 { "vpavgb", { XM
, Vex128
, EXx
} },
9820 /* VEX_W_0FE1_P_2 */
9821 { "vpsraw", { XM
, Vex128
, EXx
} },
9824 /* VEX_W_0FE2_P_2 */
9825 { "vpsrad", { XM
, Vex128
, EXx
} },
9828 /* VEX_W_0FE3_P_2 */
9829 { "vpavgw", { XM
, Vex128
, EXx
} },
9832 /* VEX_W_0FE4_P_2 */
9833 { "vpmulhuw", { XM
, Vex128
, EXx
} },
9836 /* VEX_W_0FE5_P_2 */
9837 { "vpmulhw", { XM
, Vex128
, EXx
} },
9840 /* VEX_W_0FE6_P_1 */
9841 { "vcvtdq2pd", { XM
, EXxmmq
} },
9844 /* VEX_W_0FE6_P_2 */
9845 { "vcvttpd2dq%XY", { XMM
, EXx
} },
9848 /* VEX_W_0FE6_P_3 */
9849 { "vcvtpd2dq%XY", { XMM
, EXx
} },
9852 /* VEX_W_0FE7_P_2_M_0 */
9853 { "vmovntdq", { Mx
, XM
} },
9856 /* VEX_W_0FE8_P_2 */
9857 { "vpsubsb", { XM
, Vex128
, EXx
} },
9860 /* VEX_W_0FE9_P_2 */
9861 { "vpsubsw", { XM
, Vex128
, EXx
} },
9864 /* VEX_W_0FEA_P_2 */
9865 { "vpminsw", { XM
, Vex128
, EXx
} },
9868 /* VEX_W_0FEB_P_2 */
9869 { "vpor", { XM
, Vex128
, EXx
} },
9872 /* VEX_W_0FEC_P_2 */
9873 { "vpaddsb", { XM
, Vex128
, EXx
} },
9876 /* VEX_W_0FED_P_2 */
9877 { "vpaddsw", { XM
, Vex128
, EXx
} },
9880 /* VEX_W_0FEE_P_2 */
9881 { "vpmaxsw", { XM
, Vex128
, EXx
} },
9884 /* VEX_W_0FEF_P_2 */
9885 { "vpxor", { XM
, Vex128
, EXx
} },
9888 /* VEX_W_0FF0_P_3_M_0 */
9889 { "vlddqu", { XM
, M
} },
9892 /* VEX_W_0FF1_P_2 */
9893 { "vpsllw", { XM
, Vex128
, EXx
} },
9896 /* VEX_W_0FF2_P_2 */
9897 { "vpslld", { XM
, Vex128
, EXx
} },
9900 /* VEX_W_0FF3_P_2 */
9901 { "vpsllq", { XM
, Vex128
, EXx
} },
9904 /* VEX_W_0FF4_P_2 */
9905 { "vpmuludq", { XM
, Vex128
, EXx
} },
9908 /* VEX_W_0FF5_P_2 */
9909 { "vpmaddwd", { XM
, Vex128
, EXx
} },
9912 /* VEX_W_0FF6_P_2 */
9913 { "vpsadbw", { XM
, Vex128
, EXx
} },
9916 /* VEX_W_0FF7_P_2 */
9917 { "vmaskmovdqu", { XM
, XS
} },
9920 /* VEX_W_0FF8_P_2 */
9921 { "vpsubb", { XM
, Vex128
, EXx
} },
9924 /* VEX_W_0FF9_P_2 */
9925 { "vpsubw", { XM
, Vex128
, EXx
} },
9928 /* VEX_W_0FFA_P_2 */
9929 { "vpsubd", { XM
, Vex128
, EXx
} },
9932 /* VEX_W_0FFB_P_2 */
9933 { "vpsubq", { XM
, Vex128
, EXx
} },
9936 /* VEX_W_0FFC_P_2 */
9937 { "vpaddb", { XM
, Vex128
, EXx
} },
9940 /* VEX_W_0FFD_P_2 */
9941 { "vpaddw", { XM
, Vex128
, EXx
} },
9944 /* VEX_W_0FFE_P_2 */
9945 { "vpaddd", { XM
, Vex128
, EXx
} },
9948 /* VEX_W_0F3800_P_2 */
9949 { "vpshufb", { XM
, Vex128
, EXx
} },
9952 /* VEX_W_0F3801_P_2 */
9953 { "vphaddw", { XM
, Vex128
, EXx
} },
9956 /* VEX_W_0F3802_P_2 */
9957 { "vphaddd", { XM
, Vex128
, EXx
} },
9960 /* VEX_W_0F3803_P_2 */
9961 { "vphaddsw", { XM
, Vex128
, EXx
} },
9964 /* VEX_W_0F3804_P_2 */
9965 { "vpmaddubsw", { XM
, Vex128
, EXx
} },
9968 /* VEX_W_0F3805_P_2 */
9969 { "vphsubw", { XM
, Vex128
, EXx
} },
9972 /* VEX_W_0F3806_P_2 */
9973 { "vphsubd", { XM
, Vex128
, EXx
} },
9976 /* VEX_W_0F3807_P_2 */
9977 { "vphsubsw", { XM
, Vex128
, EXx
} },
9980 /* VEX_W_0F3808_P_2 */
9981 { "vpsignb", { XM
, Vex128
, EXx
} },
9984 /* VEX_W_0F3809_P_2 */
9985 { "vpsignw", { XM
, Vex128
, EXx
} },
9988 /* VEX_W_0F380A_P_2 */
9989 { "vpsignd", { XM
, Vex128
, EXx
} },
9992 /* VEX_W_0F380B_P_2 */
9993 { "vpmulhrsw", { XM
, Vex128
, EXx
} },
9996 /* VEX_W_0F380C_P_2 */
9997 { "vpermilps", { XM
, Vex
, EXx
} },
10000 /* VEX_W_0F380D_P_2 */
10001 { "vpermilpd", { XM
, Vex
, EXx
} },
10004 /* VEX_W_0F380E_P_2 */
10005 { "vtestps", { XM
, EXx
} },
10008 /* VEX_W_0F380F_P_2 */
10009 { "vtestpd", { XM
, EXx
} },
10012 /* VEX_W_0F3817_P_2 */
10013 { "vptest", { XM
, EXx
} },
10016 /* VEX_W_0F3818_P_2_M_0 */
10017 { "vbroadcastss", { XM
, Md
} },
10020 /* VEX_W_0F3819_P_2_M_0 */
10021 { "vbroadcastsd", { XM
, Mq
} },
10024 /* VEX_W_0F381A_P_2_M_0 */
10025 { "vbroadcastf128", { XM
, Mxmm
} },
10028 /* VEX_W_0F381C_P_2 */
10029 { "vpabsb", { XM
, EXx
} },
10032 /* VEX_W_0F381D_P_2 */
10033 { "vpabsw", { XM
, EXx
} },
10036 /* VEX_W_0F381E_P_2 */
10037 { "vpabsd", { XM
, EXx
} },
10040 /* VEX_W_0F3820_P_2 */
10041 { "vpmovsxbw", { XM
, EXq
} },
10044 /* VEX_W_0F3821_P_2 */
10045 { "vpmovsxbd", { XM
, EXd
} },
10048 /* VEX_W_0F3822_P_2 */
10049 { "vpmovsxbq", { XM
, EXw
} },
10052 /* VEX_W_0F3823_P_2 */
10053 { "vpmovsxwd", { XM
, EXq
} },
10056 /* VEX_W_0F3824_P_2 */
10057 { "vpmovsxwq", { XM
, EXd
} },
10060 /* VEX_W_0F3825_P_2 */
10061 { "vpmovsxdq", { XM
, EXq
} },
10064 /* VEX_W_0F3828_P_2 */
10065 { "vpmuldq", { XM
, Vex128
, EXx
} },
10068 /* VEX_W_0F3829_P_2 */
10069 { "vpcmpeqq", { XM
, Vex128
, EXx
} },
10072 /* VEX_W_0F382A_P_2_M_0 */
10073 { "vmovntdqa", { XM
, Mx
} },
10076 /* VEX_W_0F382B_P_2 */
10077 { "vpackusdw", { XM
, Vex128
, EXx
} },
10080 /* VEX_W_0F382C_P_2_M_0 */
10081 { "vmaskmovps", { XM
, Vex
, Mx
} },
10084 /* VEX_W_0F382D_P_2_M_0 */
10085 { "vmaskmovpd", { XM
, Vex
, Mx
} },
10088 /* VEX_W_0F382E_P_2_M_0 */
10089 { "vmaskmovps", { Mx
, Vex
, XM
} },
10092 /* VEX_W_0F382F_P_2_M_0 */
10093 { "vmaskmovpd", { Mx
, Vex
, XM
} },
10096 /* VEX_W_0F3830_P_2 */
10097 { "vpmovzxbw", { XM
, EXq
} },
10100 /* VEX_W_0F3831_P_2 */
10101 { "vpmovzxbd", { XM
, EXd
} },
10104 /* VEX_W_0F3832_P_2 */
10105 { "vpmovzxbq", { XM
, EXw
} },
10108 /* VEX_W_0F3833_P_2 */
10109 { "vpmovzxwd", { XM
, EXq
} },
10112 /* VEX_W_0F3834_P_2 */
10113 { "vpmovzxwq", { XM
, EXd
} },
10116 /* VEX_W_0F3835_P_2 */
10117 { "vpmovzxdq", { XM
, EXq
} },
10120 /* VEX_W_0F3837_P_2 */
10121 { "vpcmpgtq", { XM
, Vex128
, EXx
} },
10124 /* VEX_W_0F3838_P_2 */
10125 { "vpminsb", { XM
, Vex128
, EXx
} },
10128 /* VEX_W_0F3839_P_2 */
10129 { "vpminsd", { XM
, Vex128
, EXx
} },
10132 /* VEX_W_0F383A_P_2 */
10133 { "vpminuw", { XM
, Vex128
, EXx
} },
10136 /* VEX_W_0F383B_P_2 */
10137 { "vpminud", { XM
, Vex128
, EXx
} },
10140 /* VEX_W_0F383C_P_2 */
10141 { "vpmaxsb", { XM
, Vex128
, EXx
} },
10144 /* VEX_W_0F383D_P_2 */
10145 { "vpmaxsd", { XM
, Vex128
, EXx
} },
10148 /* VEX_W_0F383E_P_2 */
10149 { "vpmaxuw", { XM
, Vex128
, EXx
} },
10152 /* VEX_W_0F383F_P_2 */
10153 { "vpmaxud", { XM
, Vex128
, EXx
} },
10156 /* VEX_W_0F3840_P_2 */
10157 { "vpmulld", { XM
, Vex128
, EXx
} },
10160 /* VEX_W_0F3841_P_2 */
10161 { "vphminposuw", { XM
, EXx
} },
10164 /* VEX_W_0F38DB_P_2 */
10165 { "vaesimc", { XM
, EXx
} },
10168 /* VEX_W_0F38DC_P_2 */
10169 { "vaesenc", { XM
, Vex128
, EXx
} },
10172 /* VEX_W_0F38DD_P_2 */
10173 { "vaesenclast", { XM
, Vex128
, EXx
} },
10176 /* VEX_W_0F38DE_P_2 */
10177 { "vaesdec", { XM
, Vex128
, EXx
} },
10180 /* VEX_W_0F38DF_P_2 */
10181 { "vaesdeclast", { XM
, Vex128
, EXx
} },
10184 /* VEX_W_0F3A04_P_2 */
10185 { "vpermilps", { XM
, EXx
, Ib
} },
10188 /* VEX_W_0F3A05_P_2 */
10189 { "vpermilpd", { XM
, EXx
, Ib
} },
10192 /* VEX_W_0F3A06_P_2 */
10193 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
10196 /* VEX_W_0F3A08_P_2 */
10197 { "vroundps", { XM
, EXx
, Ib
} },
10200 /* VEX_W_0F3A09_P_2 */
10201 { "vroundpd", { XM
, EXx
, Ib
} },
10204 /* VEX_W_0F3A0A_P_2 */
10205 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
10208 /* VEX_W_0F3A0B_P_2 */
10209 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
10212 /* VEX_W_0F3A0C_P_2 */
10213 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10216 /* VEX_W_0F3A0D_P_2 */
10217 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10220 /* VEX_W_0F3A0E_P_2 */
10221 { "vpblendw", { XM
, Vex128
, EXx
, Ib
} },
10224 /* VEX_W_0F3A0F_P_2 */
10225 { "vpalignr", { XM
, Vex128
, EXx
, Ib
} },
10228 /* VEX_W_0F3A14_P_2 */
10229 { "vpextrb", { Edqb
, XM
, Ib
} },
10232 /* VEX_W_0F3A15_P_2 */
10233 { "vpextrw", { Edqw
, XM
, Ib
} },
10236 /* VEX_W_0F3A18_P_2 */
10237 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10240 /* VEX_W_0F3A19_P_2 */
10241 { "vextractf128", { EXxmm
, XM
, Ib
} },
10244 /* VEX_W_0F3A20_P_2 */
10245 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10248 /* VEX_W_0F3A21_P_2 */
10249 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10252 /* VEX_W_0F3A40_P_2 */
10253 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
10256 /* VEX_W_0F3A41_P_2 */
10257 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
10260 /* VEX_W_0F3A42_P_2 */
10261 { "vmpsadbw", { XM
, Vex128
, EXx
, Ib
} },
10264 /* VEX_W_0F3A44_P_2 */
10265 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
10268 /* VEX_W_0F3A48_P_2 */
10269 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10270 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10273 /* VEX_W_0F3A49_P_2 */
10274 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10275 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10278 /* VEX_W_0F3A4A_P_2 */
10279 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
10282 /* VEX_W_0F3A4B_P_2 */
10283 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
10286 /* VEX_W_0F3A4C_P_2 */
10287 { "vpblendvb", { XM
, Vex128
, EXx
, XMVexI4
} },
10290 /* VEX_W_0F3A60_P_2 */
10291 { "vpcmpestrm", { XM
, EXx
, Ib
} },
10294 /* VEX_W_0F3A61_P_2 */
10295 { "vpcmpestri", { XM
, EXx
, Ib
} },
10298 /* VEX_W_0F3A62_P_2 */
10299 { "vpcmpistrm", { XM
, EXx
, Ib
} },
10302 /* VEX_W_0F3A63_P_2 */
10303 { "vpcmpistri", { XM
, EXx
, Ib
} },
10306 /* VEX_W_0F3ADF_P_2 */
10307 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
10311 static const struct dis386 mod_table
[][2] = {
10314 { "leaS", { Gv
, M
} },
10317 /* MOD_0F01_REG_0 */
10318 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10319 { RM_TABLE (RM_0F01_REG_0
) },
10322 /* MOD_0F01_REG_1 */
10323 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10324 { RM_TABLE (RM_0F01_REG_1
) },
10327 /* MOD_0F01_REG_2 */
10328 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10329 { RM_TABLE (RM_0F01_REG_2
) },
10332 /* MOD_0F01_REG_3 */
10333 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10334 { RM_TABLE (RM_0F01_REG_3
) },
10337 /* MOD_0F01_REG_7 */
10338 { "invlpg", { Mb
} },
10339 { RM_TABLE (RM_0F01_REG_7
) },
10342 /* MOD_0F12_PREFIX_0 */
10343 { "movlps", { XM
, EXq
} },
10344 { "movhlps", { XM
, EXq
} },
10348 { "movlpX", { EXq
, XM
} },
10351 /* MOD_0F16_PREFIX_0 */
10352 { "movhps", { XM
, EXq
} },
10353 { "movlhps", { XM
, EXq
} },
10357 { "movhpX", { EXq
, XM
} },
10360 /* MOD_0F18_REG_0 */
10361 { "prefetchnta", { Mb
} },
10364 /* MOD_0F18_REG_1 */
10365 { "prefetcht0", { Mb
} },
10368 /* MOD_0F18_REG_2 */
10369 { "prefetcht1", { Mb
} },
10372 /* MOD_0F18_REG_3 */
10373 { "prefetcht2", { Mb
} },
10378 { "movZ", { Rm
, Cm
} },
10383 { "movZ", { Rm
, Dm
} },
10388 { "movZ", { Cm
, Rm
} },
10393 { "movZ", { Dm
, Rm
} },
10398 { "movL", { Rd
, Td
} },
10403 { "movL", { Td
, Rd
} },
10406 /* MOD_0F2B_PREFIX_0 */
10407 {"movntps", { Mx
, XM
} },
10410 /* MOD_0F2B_PREFIX_1 */
10411 {"movntss", { Md
, XM
} },
10414 /* MOD_0F2B_PREFIX_2 */
10415 {"movntpd", { Mx
, XM
} },
10418 /* MOD_0F2B_PREFIX_3 */
10419 {"movntsd", { Mq
, XM
} },
10424 { "movmskpX", { Gdq
, XS
} },
10427 /* MOD_0F71_REG_2 */
10429 { "psrlw", { MS
, Ib
} },
10432 /* MOD_0F71_REG_4 */
10434 { "psraw", { MS
, Ib
} },
10437 /* MOD_0F71_REG_6 */
10439 { "psllw", { MS
, Ib
} },
10442 /* MOD_0F72_REG_2 */
10444 { "psrld", { MS
, Ib
} },
10447 /* MOD_0F72_REG_4 */
10449 { "psrad", { MS
, Ib
} },
10452 /* MOD_0F72_REG_6 */
10454 { "pslld", { MS
, Ib
} },
10457 /* MOD_0F73_REG_2 */
10459 { "psrlq", { MS
, Ib
} },
10462 /* MOD_0F73_REG_3 */
10464 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10467 /* MOD_0F73_REG_6 */
10469 { "psllq", { MS
, Ib
} },
10472 /* MOD_0F73_REG_7 */
10474 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10477 /* MOD_0FAE_REG_0 */
10478 { "fxsave", { FXSAVE
} },
10479 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10482 /* MOD_0FAE_REG_1 */
10483 { "fxrstor", { FXSAVE
} },
10484 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10487 /* MOD_0FAE_REG_2 */
10488 { "ldmxcsr", { Md
} },
10489 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10492 /* MOD_0FAE_REG_3 */
10493 { "stmxcsr", { Md
} },
10494 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10497 /* MOD_0FAE_REG_4 */
10498 { "xsave", { FXSAVE
} },
10501 /* MOD_0FAE_REG_5 */
10502 { "xrstor", { FXSAVE
} },
10503 { RM_TABLE (RM_0FAE_REG_5
) },
10506 /* MOD_0FAE_REG_6 */
10507 { "xsaveopt", { FXSAVE
} },
10508 { RM_TABLE (RM_0FAE_REG_6
) },
10511 /* MOD_0FAE_REG_7 */
10512 { "clflush", { Mb
} },
10513 { RM_TABLE (RM_0FAE_REG_7
) },
10517 { "lssS", { Gv
, Mp
} },
10521 { "lfsS", { Gv
, Mp
} },
10525 { "lgsS", { Gv
, Mp
} },
10528 /* MOD_0FC7_REG_6 */
10529 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
10530 { "rdrand", { Ev
} },
10533 /* MOD_0FC7_REG_7 */
10534 { "vmptrst", { Mq
} },
10539 { "pmovmskb", { Gdq
, MS
} },
10542 /* MOD_0FE7_PREFIX_2 */
10543 { "movntdq", { Mx
, XM
} },
10546 /* MOD_0FF0_PREFIX_3 */
10547 { "lddqu", { XM
, M
} },
10550 /* MOD_0F382A_PREFIX_2 */
10551 { "movntdqa", { XM
, Mx
} },
10555 { "bound{S|}", { Gv
, Ma
} },
10559 { "lesS", { Gv
, Mp
} },
10560 { VEX_C4_TABLE (VEX_0F
) },
10564 { "ldsS", { Gv
, Mp
} },
10565 { VEX_C5_TABLE (VEX_0F
) },
10568 /* MOD_VEX_0F12_PREFIX_0 */
10569 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10570 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10574 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10577 /* MOD_VEX_0F16_PREFIX_0 */
10578 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10579 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10583 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10587 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
10592 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
10595 /* MOD_VEX_0F71_REG_2 */
10597 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10600 /* MOD_VEX_0F71_REG_4 */
10602 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10605 /* MOD_VEX_0F71_REG_6 */
10607 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10610 /* MOD_VEX_0F72_REG_2 */
10612 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10615 /* MOD_VEX_0F72_REG_4 */
10617 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10620 /* MOD_VEX_0F72_REG_6 */
10622 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10625 /* MOD_VEX_0F73_REG_2 */
10627 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10630 /* MOD_VEX_0F73_REG_3 */
10632 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10635 /* MOD_VEX_0F73_REG_6 */
10637 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10640 /* MOD_VEX_0F73_REG_7 */
10642 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10645 /* MOD_VEX_0FAE_REG_2 */
10646 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10649 /* MOD_VEX_0FAE_REG_3 */
10650 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10653 /* MOD_VEX_0FD7_PREFIX_2 */
10655 { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1
) },
10658 /* MOD_VEX_0FE7_PREFIX_2 */
10659 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
10662 /* MOD_VEX_0FF0_PREFIX_3 */
10663 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
10666 /* MOD_VEX_0F3818_PREFIX_2 */
10667 { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0
) },
10670 /* MOD_VEX_0F3819_PREFIX_2 */
10671 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0
) },
10674 /* MOD_VEX_0F381A_PREFIX_2 */
10675 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10678 /* MOD_VEX_0F382A_PREFIX_2 */
10679 { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0
) },
10682 /* MOD_VEX_0F382C_PREFIX_2 */
10683 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10686 /* MOD_VEX_0F382D_PREFIX_2 */
10687 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10690 /* MOD_VEX_0F382E_PREFIX_2 */
10691 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10694 /* MOD_VEX_0F382F_PREFIX_2 */
10695 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10699 static const struct dis386 rm_table
[][8] = {
10701 /* RM_0F01_REG_0 */
10703 { "vmcall", { Skip_MODRM
} },
10704 { "vmlaunch", { Skip_MODRM
} },
10705 { "vmresume", { Skip_MODRM
} },
10706 { "vmxoff", { Skip_MODRM
} },
10709 /* RM_0F01_REG_1 */
10710 { "monitor", { { OP_Monitor
, 0 } } },
10711 { "mwait", { { OP_Mwait
, 0 } } },
10714 /* RM_0F01_REG_2 */
10715 { "xgetbv", { Skip_MODRM
} },
10716 { "xsetbv", { Skip_MODRM
} },
10719 /* RM_0F01_REG_3 */
10720 { "vmrun", { Skip_MODRM
} },
10721 { "vmmcall", { Skip_MODRM
} },
10722 { "vmload", { Skip_MODRM
} },
10723 { "vmsave", { Skip_MODRM
} },
10724 { "stgi", { Skip_MODRM
} },
10725 { "clgi", { Skip_MODRM
} },
10726 { "skinit", { Skip_MODRM
} },
10727 { "invlpga", { Skip_MODRM
} },
10730 /* RM_0F01_REG_7 */
10731 { "swapgs", { Skip_MODRM
} },
10732 { "rdtscp", { Skip_MODRM
} },
10735 /* RM_0FAE_REG_5 */
10736 { "lfence", { Skip_MODRM
} },
10739 /* RM_0FAE_REG_6 */
10740 { "mfence", { Skip_MODRM
} },
10743 /* RM_0FAE_REG_7 */
10744 { "sfence", { Skip_MODRM
} },
10748 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10750 /* We use the high bit to indicate different name for the same
10752 #define ADDR16_PREFIX (0x67 | 0x100)
10753 #define ADDR32_PREFIX (0x67 | 0x200)
10754 #define DATA16_PREFIX (0x66 | 0x100)
10755 #define DATA32_PREFIX (0x66 | 0x200)
10756 #define REP_PREFIX (0xf3 | 0x100)
10761 int newrex
, i
, length
;
10767 last_lock_prefix
= -1;
10768 last_repz_prefix
= -1;
10769 last_repnz_prefix
= -1;
10770 last_data_prefix
= -1;
10771 last_addr_prefix
= -1;
10772 last_rex_prefix
= -1;
10773 last_seg_prefix
= -1;
10774 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10775 all_prefixes
[i
] = 0;
10778 /* The maximum instruction length is 15bytes. */
10779 while (length
< MAX_CODE_LENGTH
- 1)
10781 FETCH_DATA (the_info
, codep
+ 1);
10785 /* REX prefixes family. */
10802 if (address_mode
== mode_64bit
)
10806 last_rex_prefix
= i
;
10809 prefixes
|= PREFIX_REPZ
;
10810 last_repz_prefix
= i
;
10813 prefixes
|= PREFIX_REPNZ
;
10814 last_repnz_prefix
= i
;
10817 prefixes
|= PREFIX_LOCK
;
10818 last_lock_prefix
= i
;
10821 prefixes
|= PREFIX_CS
;
10822 last_seg_prefix
= i
;
10825 prefixes
|= PREFIX_SS
;
10826 last_seg_prefix
= i
;
10829 prefixes
|= PREFIX_DS
;
10830 last_seg_prefix
= i
;
10833 prefixes
|= PREFIX_ES
;
10834 last_seg_prefix
= i
;
10837 prefixes
|= PREFIX_FS
;
10838 last_seg_prefix
= i
;
10841 prefixes
|= PREFIX_GS
;
10842 last_seg_prefix
= i
;
10845 prefixes
|= PREFIX_DATA
;
10846 last_data_prefix
= i
;
10849 prefixes
|= PREFIX_ADDR
;
10850 last_addr_prefix
= i
;
10853 /* fwait is really an instruction. If there are prefixes
10854 before the fwait, they belong to the fwait, *not* to the
10855 following instruction. */
10856 if (prefixes
|| rex
)
10858 prefixes
|= PREFIX_FWAIT
;
10862 prefixes
= PREFIX_FWAIT
;
10867 /* Rex is ignored when followed by another prefix. */
10873 if (*codep
!= FWAIT_OPCODE
)
10874 all_prefixes
[i
++] = *codep
;
10883 seg_prefix (int pref
)
10904 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10907 static const char *
10908 prefix_name (int pref
, int sizeflag
)
10910 static const char *rexes
[16] =
10913 "rex.B", /* 0x41 */
10914 "rex.X", /* 0x42 */
10915 "rex.XB", /* 0x43 */
10916 "rex.R", /* 0x44 */
10917 "rex.RB", /* 0x45 */
10918 "rex.RX", /* 0x46 */
10919 "rex.RXB", /* 0x47 */
10920 "rex.W", /* 0x48 */
10921 "rex.WB", /* 0x49 */
10922 "rex.WX", /* 0x4a */
10923 "rex.WXB", /* 0x4b */
10924 "rex.WR", /* 0x4c */
10925 "rex.WRB", /* 0x4d */
10926 "rex.WRX", /* 0x4e */
10927 "rex.WRXB", /* 0x4f */
10932 /* REX prefixes family. */
10949 return rexes
[pref
- 0x40];
10969 return (sizeflag
& DFLAG
) ? "data16" : "data32";
10971 if (address_mode
== mode_64bit
)
10972 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
10974 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
10977 case ADDR16_PREFIX
:
10979 case ADDR32_PREFIX
:
10981 case DATA16_PREFIX
:
10983 case DATA32_PREFIX
:
10992 static char op_out
[MAX_OPERANDS
][100];
10993 static int op_ad
, op_index
[MAX_OPERANDS
];
10994 static int two_source_ops
;
10995 static bfd_vma op_address
[MAX_OPERANDS
];
10996 static bfd_vma op_riprel
[MAX_OPERANDS
];
10997 static bfd_vma start_pc
;
11000 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11001 * (see topic "Redundant prefixes" in the "Differences from 8086"
11002 * section of the "Virtual 8086 Mode" chapter.)
11003 * 'pc' should be the address of this instruction, it will
11004 * be used to print the target address if this is a relative jump or call
11005 * The function returns the length of this instruction in bytes.
11008 static char intel_syntax
;
11009 static char intel_mnemonic
= !SYSV386_COMPAT
;
11010 static char open_char
;
11011 static char close_char
;
11012 static char separator_char
;
11013 static char scale_char
;
11015 /* Here for backwards compatibility. When gdb stops using
11016 print_insn_i386_att and print_insn_i386_intel these functions can
11017 disappear, and print_insn_i386 be merged into print_insn. */
11019 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11023 return print_insn (pc
, info
);
11027 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11031 return print_insn (pc
, info
);
11035 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11039 return print_insn (pc
, info
);
11043 print_i386_disassembler_options (FILE *stream
)
11045 fprintf (stream
, _("\n\
11046 The following i386/x86-64 specific disassembler options are supported for use\n\
11047 with the -M switch (multiple options should be separated by commas):\n"));
11049 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11050 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11051 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11052 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11053 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11054 fprintf (stream
, _(" att-mnemonic\n"
11055 " Display instruction in AT&T mnemonic\n"));
11056 fprintf (stream
, _(" intel-mnemonic\n"
11057 " Display instruction in Intel mnemonic\n"));
11058 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11059 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11060 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11061 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11062 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11063 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11067 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
11069 /* Get a pointer to struct dis386 with a valid name. */
11071 static const struct dis386
*
11072 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11074 int vindex
, vex_table_index
;
11076 if (dp
->name
!= NULL
)
11079 switch (dp
->op
[0].bytemode
)
11081 case USE_REG_TABLE
:
11082 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11085 case USE_MOD_TABLE
:
11086 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11087 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11091 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11094 case USE_PREFIX_TABLE
:
11097 /* The prefix in VEX is implicit. */
11098 switch (vex
.prefix
)
11103 case REPE_PREFIX_OPCODE
:
11106 case DATA_PREFIX_OPCODE
:
11109 case REPNE_PREFIX_OPCODE
:
11120 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
11121 if (prefixes
& PREFIX_REPZ
)
11124 all_prefixes
[last_repz_prefix
] = 0;
11128 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11130 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
11131 if (prefixes
& PREFIX_REPNZ
)
11134 all_prefixes
[last_repnz_prefix
] = 0;
11138 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11139 if (prefixes
& PREFIX_DATA
)
11142 all_prefixes
[last_data_prefix
] = 0;
11147 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11150 case USE_X86_64_TABLE
:
11151 vindex
= address_mode
== mode_64bit
? 1 : 0;
11152 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11155 case USE_3BYTE_TABLE
:
11156 FETCH_DATA (info
, codep
+ 2);
11158 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11159 modrm
.mod
= (*codep
>> 6) & 3;
11160 modrm
.reg
= (*codep
>> 3) & 7;
11161 modrm
.rm
= *codep
& 7;
11164 case USE_VEX_LEN_TABLE
:
11168 switch (vex
.length
)
11181 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11184 case USE_XOP_8F_TABLE
:
11185 FETCH_DATA (info
, codep
+ 3);
11186 /* All bits in the REX prefix are ignored. */
11188 rex
= ~(*codep
>> 5) & 0x7;
11190 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11191 switch ((*codep
& 0x1f))
11197 vex_table_index
= XOP_08
;
11200 vex_table_index
= XOP_09
;
11203 vex_table_index
= XOP_0A
;
11207 vex
.w
= *codep
& 0x80;
11208 if (vex
.w
&& address_mode
== mode_64bit
)
11211 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11212 if (address_mode
!= mode_64bit
11213 && vex
.register_specifier
> 0x7)
11219 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11220 switch ((*codep
& 0x3))
11226 vex
.prefix
= DATA_PREFIX_OPCODE
;
11229 vex
.prefix
= REPE_PREFIX_OPCODE
;
11232 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11239 dp
= &xop_table
[vex_table_index
][vindex
];
11241 FETCH_DATA (info
, codep
+ 1);
11242 modrm
.mod
= (*codep
>> 6) & 3;
11243 modrm
.reg
= (*codep
>> 3) & 7;
11244 modrm
.rm
= *codep
& 7;
11247 case USE_VEX_C4_TABLE
:
11248 FETCH_DATA (info
, codep
+ 3);
11249 /* All bits in the REX prefix are ignored. */
11251 rex
= ~(*codep
>> 5) & 0x7;
11252 switch ((*codep
& 0x1f))
11258 vex_table_index
= VEX_0F
;
11261 vex_table_index
= VEX_0F38
;
11264 vex_table_index
= VEX_0F3A
;
11268 vex
.w
= *codep
& 0x80;
11269 if (vex
.w
&& address_mode
== mode_64bit
)
11272 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11273 if (address_mode
!= mode_64bit
11274 && vex
.register_specifier
> 0x7)
11280 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11281 switch ((*codep
& 0x3))
11287 vex
.prefix
= DATA_PREFIX_OPCODE
;
11290 vex
.prefix
= REPE_PREFIX_OPCODE
;
11293 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11300 dp
= &vex_table
[vex_table_index
][vindex
];
11301 /* There is no MODRM byte for VEX [82|77]. */
11302 if (vindex
!= 0x77 && vindex
!= 0x82)
11304 FETCH_DATA (info
, codep
+ 1);
11305 modrm
.mod
= (*codep
>> 6) & 3;
11306 modrm
.reg
= (*codep
>> 3) & 7;
11307 modrm
.rm
= *codep
& 7;
11311 case USE_VEX_C5_TABLE
:
11312 FETCH_DATA (info
, codep
+ 2);
11313 /* All bits in the REX prefix are ignored. */
11315 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11317 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11318 if (address_mode
!= mode_64bit
11319 && vex
.register_specifier
> 0x7)
11327 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11328 switch ((*codep
& 0x3))
11334 vex
.prefix
= DATA_PREFIX_OPCODE
;
11337 vex
.prefix
= REPE_PREFIX_OPCODE
;
11340 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11347 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11348 /* There is no MODRM byte for VEX [82|77]. */
11349 if (vindex
!= 0x77 && vindex
!= 0x82)
11351 FETCH_DATA (info
, codep
+ 1);
11352 modrm
.mod
= (*codep
>> 6) & 3;
11353 modrm
.reg
= (*codep
>> 3) & 7;
11354 modrm
.rm
= *codep
& 7;
11358 case USE_VEX_W_TABLE
:
11362 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11373 if (dp
->name
!= NULL
)
11376 return get_valid_dis386 (dp
, info
);
11380 get_sib (disassemble_info
*info
)
11382 /* If modrm.mod == 3, operand must be register. */
11384 && address_mode
!= mode_16bit
11388 FETCH_DATA (info
, codep
+ 2);
11389 sib
.index
= (codep
[1] >> 3) & 7;
11390 sib
.scale
= (codep
[1] >> 6) & 3;
11391 sib
.base
= codep
[1] & 7;
11396 print_insn (bfd_vma pc
, disassemble_info
*info
)
11398 const struct dis386
*dp
;
11400 char *op_txt
[MAX_OPERANDS
];
11404 struct dis_private priv
;
11406 int default_prefixes
;
11408 if (info
->mach
== bfd_mach_x86_64_intel_syntax
11409 || info
->mach
== bfd_mach_x86_64
11410 || info
->mach
== bfd_mach_x64_32_intel_syntax
11411 || info
->mach
== bfd_mach_x64_32
11412 || info
->mach
== bfd_mach_l1om
11413 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11414 address_mode
= mode_64bit
;
11416 address_mode
= mode_32bit
;
11418 if (intel_syntax
== (char) -1)
11419 intel_syntax
= (info
->mach
== bfd_mach_i386_i386_intel_syntax
11420 || info
->mach
== bfd_mach_x86_64_intel_syntax
11421 || info
->mach
== bfd_mach_x64_32_intel_syntax
11422 || info
->mach
== bfd_mach_l1om_intel_syntax
);
11424 if (info
->mach
== bfd_mach_i386_i386
11425 || info
->mach
== bfd_mach_x86_64
11426 || info
->mach
== bfd_mach_x64_32
11427 || info
->mach
== bfd_mach_l1om
11428 || info
->mach
== bfd_mach_i386_i386_intel_syntax
11429 || info
->mach
== bfd_mach_x86_64_intel_syntax
11430 || info
->mach
== bfd_mach_x64_32_intel_syntax
11431 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11432 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11433 else if (info
->mach
== bfd_mach_i386_i8086
)
11434 priv
.orig_sizeflag
= 0;
11438 for (p
= info
->disassembler_options
; p
!= NULL
; )
11440 if (CONST_STRNEQ (p
, "x86-64"))
11442 address_mode
= mode_64bit
;
11443 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11445 else if (CONST_STRNEQ (p
, "i386"))
11447 address_mode
= mode_32bit
;
11448 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11450 else if (CONST_STRNEQ (p
, "i8086"))
11452 address_mode
= mode_16bit
;
11453 priv
.orig_sizeflag
= 0;
11455 else if (CONST_STRNEQ (p
, "intel"))
11458 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11459 intel_mnemonic
= 1;
11461 else if (CONST_STRNEQ (p
, "att"))
11464 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11465 intel_mnemonic
= 0;
11467 else if (CONST_STRNEQ (p
, "addr"))
11469 if (address_mode
== mode_64bit
)
11471 if (p
[4] == '3' && p
[5] == '2')
11472 priv
.orig_sizeflag
&= ~AFLAG
;
11473 else if (p
[4] == '6' && p
[5] == '4')
11474 priv
.orig_sizeflag
|= AFLAG
;
11478 if (p
[4] == '1' && p
[5] == '6')
11479 priv
.orig_sizeflag
&= ~AFLAG
;
11480 else if (p
[4] == '3' && p
[5] == '2')
11481 priv
.orig_sizeflag
|= AFLAG
;
11484 else if (CONST_STRNEQ (p
, "data"))
11486 if (p
[4] == '1' && p
[5] == '6')
11487 priv
.orig_sizeflag
&= ~DFLAG
;
11488 else if (p
[4] == '3' && p
[5] == '2')
11489 priv
.orig_sizeflag
|= DFLAG
;
11491 else if (CONST_STRNEQ (p
, "suffix"))
11492 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11494 p
= strchr (p
, ',');
11501 names64
= intel_names64
;
11502 names32
= intel_names32
;
11503 names16
= intel_names16
;
11504 names8
= intel_names8
;
11505 names8rex
= intel_names8rex
;
11506 names_seg
= intel_names_seg
;
11507 names_mm
= intel_names_mm
;
11508 names_xmm
= intel_names_xmm
;
11509 names_ymm
= intel_names_ymm
;
11510 index64
= intel_index64
;
11511 index32
= intel_index32
;
11512 index16
= intel_index16
;
11515 separator_char
= '+';
11520 names64
= att_names64
;
11521 names32
= att_names32
;
11522 names16
= att_names16
;
11523 names8
= att_names8
;
11524 names8rex
= att_names8rex
;
11525 names_seg
= att_names_seg
;
11526 names_mm
= att_names_mm
;
11527 names_xmm
= att_names_xmm
;
11528 names_ymm
= att_names_ymm
;
11529 index64
= att_index64
;
11530 index32
= att_index32
;
11531 index16
= att_index16
;
11534 separator_char
= ',';
11538 /* The output looks better if we put 7 bytes on a line, since that
11539 puts most long word instructions on a single line. Use 8 bytes
11541 if (info
->mach
== bfd_mach_l1om
11542 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11543 info
->bytes_per_line
= 8;
11545 info
->bytes_per_line
= 7;
11547 info
->private_data
= &priv
;
11548 priv
.max_fetched
= priv
.the_buffer
;
11549 priv
.insn_start
= pc
;
11552 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11560 start_codep
= priv
.the_buffer
;
11561 codep
= priv
.the_buffer
;
11563 if (setjmp (priv
.bailout
) != 0)
11567 /* Getting here means we tried for data but didn't get it. That
11568 means we have an incomplete instruction of some sort. Just
11569 print the first byte as a prefix or a .byte pseudo-op. */
11570 if (codep
> priv
.the_buffer
)
11572 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11574 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11577 /* Just print the first byte as a .byte instruction. */
11578 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11579 (unsigned int) priv
.the_buffer
[0]);
11589 sizeflag
= priv
.orig_sizeflag
;
11591 if (!ckprefix () || rex_used
)
11593 /* Too many prefixes or unused REX prefixes. */
11595 all_prefixes
[i
] && i
< (int) ARRAY_SIZE (all_prefixes
);
11597 (*info
->fprintf_func
) (info
->stream
, "%s",
11598 prefix_name (all_prefixes
[i
], sizeflag
));
11602 insn_codep
= codep
;
11604 FETCH_DATA (info
, codep
+ 1);
11605 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11607 if (((prefixes
& PREFIX_FWAIT
)
11608 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11610 (*info
->fprintf_func
) (info
->stream
, "fwait");
11614 if (*codep
== 0x0f)
11616 unsigned char threebyte
;
11617 FETCH_DATA (info
, codep
+ 2);
11618 threebyte
= *++codep
;
11619 dp
= &dis386_twobyte
[threebyte
];
11620 need_modrm
= twobyte_has_modrm
[*codep
];
11625 dp
= &dis386
[*codep
];
11626 need_modrm
= onebyte_has_modrm
[*codep
];
11630 if ((prefixes
& PREFIX_REPZ
))
11631 used_prefixes
|= PREFIX_REPZ
;
11632 if ((prefixes
& PREFIX_REPNZ
))
11633 used_prefixes
|= PREFIX_REPNZ
;
11634 if ((prefixes
& PREFIX_LOCK
))
11635 used_prefixes
|= PREFIX_LOCK
;
11637 default_prefixes
= 0;
11638 if (prefixes
& PREFIX_ADDR
)
11641 if (dp
->op
[2].bytemode
!= loop_jcxz_mode
|| intel_syntax
)
11643 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11644 all_prefixes
[last_addr_prefix
] = ADDR32_PREFIX
;
11646 all_prefixes
[last_addr_prefix
] = ADDR16_PREFIX
;
11647 default_prefixes
|= PREFIX_ADDR
;
11651 if ((prefixes
& PREFIX_DATA
))
11654 if (dp
->op
[2].bytemode
== cond_jump_mode
11655 && dp
->op
[0].bytemode
== v_mode
11658 if (sizeflag
& DFLAG
)
11659 all_prefixes
[last_data_prefix
] = DATA32_PREFIX
;
11661 all_prefixes
[last_data_prefix
] = DATA16_PREFIX
;
11662 default_prefixes
|= PREFIX_DATA
;
11664 else if (rex
& REX_W
)
11666 /* REX_W will override PREFIX_DATA. */
11667 default_prefixes
|= PREFIX_DATA
;
11673 FETCH_DATA (info
, codep
+ 1);
11674 modrm
.mod
= (*codep
>> 6) & 3;
11675 modrm
.reg
= (*codep
>> 3) & 7;
11676 modrm
.rm
= *codep
& 7;
11683 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
11686 dofloat (sizeflag
);
11690 dp
= get_valid_dis386 (dp
, info
);
11691 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
11694 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11697 op_ad
= MAX_OPERANDS
- 1 - i
;
11699 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
11704 /* See if any prefixes were not used. If so, print the first one
11705 separately. If we don't do this, we'll wind up printing an
11706 instruction stream which does not precisely correspond to the
11707 bytes we are disassembling. */
11708 if ((prefixes
& ~(used_prefixes
| default_prefixes
)) != 0)
11710 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11711 if (all_prefixes
[i
])
11714 name
= prefix_name (all_prefixes
[i
], priv
.orig_sizeflag
);
11716 name
= INTERNAL_DISASSEMBLER_ERROR
;
11717 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11722 /* Check if the REX prefix is used. */
11723 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0)
11724 all_prefixes
[last_rex_prefix
] = 0;
11726 /* Check if the SEG prefix is used. */
11727 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
11728 | PREFIX_FS
| PREFIX_GS
)) != 0
11730 & seg_prefix (all_prefixes
[last_seg_prefix
])) != 0)
11731 all_prefixes
[last_seg_prefix
] = 0;
11733 /* Check if the ADDR prefix is used. */
11734 if ((prefixes
& PREFIX_ADDR
) != 0
11735 && (used_prefixes
& PREFIX_ADDR
) != 0)
11736 all_prefixes
[last_addr_prefix
] = 0;
11738 /* Check if the DATA prefix is used. */
11739 if ((prefixes
& PREFIX_DATA
) != 0
11740 && (used_prefixes
& PREFIX_DATA
) != 0)
11741 all_prefixes
[last_data_prefix
] = 0;
11744 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11745 if (all_prefixes
[i
])
11748 name
= prefix_name (all_prefixes
[i
], sizeflag
);
11751 prefix_length
+= strlen (name
) + 1;
11752 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
11755 /* Check maximum code length. */
11756 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
11758 (*info
->fprintf_func
) (info
->stream
, "(bad)");
11759 return MAX_CODE_LENGTH
;
11762 obufp
= mnemonicendp
;
11763 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
11766 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
11768 /* The enter and bound instructions are printed with operands in the same
11769 order as the intel book; everything else is printed in reverse order. */
11770 if (intel_syntax
|| two_source_ops
)
11774 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11775 op_txt
[i
] = op_out
[i
];
11777 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
11779 op_ad
= op_index
[i
];
11780 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
11781 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
11782 riprel
= op_riprel
[i
];
11783 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
11784 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
11789 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11790 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
11794 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11798 (*info
->fprintf_func
) (info
->stream
, ",");
11799 if (op_index
[i
] != -1 && !op_riprel
[i
])
11800 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
11802 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
11806 for (i
= 0; i
< MAX_OPERANDS
; i
++)
11807 if (op_index
[i
] != -1 && op_riprel
[i
])
11809 (*info
->fprintf_func
) (info
->stream
, " # ");
11810 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
11811 + op_address
[op_index
[i
]]), info
);
11814 return codep
- priv
.the_buffer
;
11817 static const char *float_mem
[] = {
11892 static const unsigned char float_mem_mode
[] = {
11967 #define ST { OP_ST, 0 }
11968 #define STi { OP_STi, 0 }
11970 #define FGRPd9_2 NULL, { { NULL, 0 } }
11971 #define FGRPd9_4 NULL, { { NULL, 1 } }
11972 #define FGRPd9_5 NULL, { { NULL, 2 } }
11973 #define FGRPd9_6 NULL, { { NULL, 3 } }
11974 #define FGRPd9_7 NULL, { { NULL, 4 } }
11975 #define FGRPda_5 NULL, { { NULL, 5 } }
11976 #define FGRPdb_4 NULL, { { NULL, 6 } }
11977 #define FGRPde_3 NULL, { { NULL, 7 } }
11978 #define FGRPdf_4 NULL, { { NULL, 8 } }
11980 static const struct dis386 float_reg
[][8] = {
11983 { "fadd", { ST
, STi
} },
11984 { "fmul", { ST
, STi
} },
11985 { "fcom", { STi
} },
11986 { "fcomp", { STi
} },
11987 { "fsub", { ST
, STi
} },
11988 { "fsubr", { ST
, STi
} },
11989 { "fdiv", { ST
, STi
} },
11990 { "fdivr", { ST
, STi
} },
11994 { "fld", { STi
} },
11995 { "fxch", { STi
} },
12005 { "fcmovb", { ST
, STi
} },
12006 { "fcmove", { ST
, STi
} },
12007 { "fcmovbe",{ ST
, STi
} },
12008 { "fcmovu", { ST
, STi
} },
12016 { "fcmovnb",{ ST
, STi
} },
12017 { "fcmovne",{ ST
, STi
} },
12018 { "fcmovnbe",{ ST
, STi
} },
12019 { "fcmovnu",{ ST
, STi
} },
12021 { "fucomi", { ST
, STi
} },
12022 { "fcomi", { ST
, STi
} },
12027 { "fadd", { STi
, ST
} },
12028 { "fmul", { STi
, ST
} },
12031 { "fsub!M", { STi
, ST
} },
12032 { "fsubM", { STi
, ST
} },
12033 { "fdiv!M", { STi
, ST
} },
12034 { "fdivM", { STi
, ST
} },
12038 { "ffree", { STi
} },
12040 { "fst", { STi
} },
12041 { "fstp", { STi
} },
12042 { "fucom", { STi
} },
12043 { "fucomp", { STi
} },
12049 { "faddp", { STi
, ST
} },
12050 { "fmulp", { STi
, ST
} },
12053 { "fsub!Mp", { STi
, ST
} },
12054 { "fsubMp", { STi
, ST
} },
12055 { "fdiv!Mp", { STi
, ST
} },
12056 { "fdivMp", { STi
, ST
} },
12060 { "ffreep", { STi
} },
12065 { "fucomip", { ST
, STi
} },
12066 { "fcomip", { ST
, STi
} },
12071 static char *fgrps
[][8] = {
12074 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12079 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12084 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12089 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12094 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12099 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12104 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12105 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12110 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12115 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12120 swap_operand (void)
12122 mnemonicendp
[0] = '.';
12123 mnemonicendp
[1] = 's';
12128 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12129 int sizeflag ATTRIBUTE_UNUSED
)
12131 /* Skip mod/rm byte. */
12137 dofloat (int sizeflag
)
12139 const struct dis386
*dp
;
12140 unsigned char floatop
;
12142 floatop
= codep
[-1];
12144 if (modrm
.mod
!= 3)
12146 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12148 putop (float_mem
[fp_indx
], sizeflag
);
12151 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12154 /* Skip mod/rm byte. */
12158 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12159 if (dp
->name
== NULL
)
12161 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12163 /* Instruction fnstsw is only one with strange arg. */
12164 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12165 strcpy (op_out
[0], names16
[0]);
12169 putop (dp
->name
, sizeflag
);
12174 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12179 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12184 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12186 oappend ("%st" + intel_syntax
);
12190 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12192 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12193 oappend (scratchbuf
+ intel_syntax
);
12196 /* Capital letters in template are macros. */
12198 putop (const char *in_template
, int sizeflag
)
12203 unsigned int l
= 0, len
= 1;
12206 #define SAVE_LAST(c) \
12207 if (l < len && l < sizeof (last)) \
12212 for (p
= in_template
; *p
; p
++)
12229 while (*++p
!= '|')
12230 if (*p
== '}' || *p
== '\0')
12233 /* Fall through. */
12238 while (*++p
!= '}')
12249 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12253 if (l
== 0 && len
== 1)
12258 if (sizeflag
& SUFFIX_ALWAYS
)
12271 if (address_mode
== mode_64bit
12272 && !(prefixes
& PREFIX_ADDR
))
12283 if (intel_syntax
&& !alt
)
12285 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12287 if (sizeflag
& DFLAG
)
12288 *obufp
++ = intel_syntax
? 'd' : 'l';
12290 *obufp
++ = intel_syntax
? 'w' : 's';
12291 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12295 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12298 if (modrm
.mod
== 3)
12304 if (sizeflag
& DFLAG
)
12305 *obufp
++ = intel_syntax
? 'd' : 'l';
12308 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12314 case 'E': /* For jcxz/jecxz */
12315 if (address_mode
== mode_64bit
)
12317 if (sizeflag
& AFLAG
)
12323 if (sizeflag
& AFLAG
)
12325 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12330 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12332 if (sizeflag
& AFLAG
)
12333 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12335 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12336 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12340 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12342 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12346 if (!(rex
& REX_W
))
12347 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12352 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12353 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12355 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12358 if (prefixes
& PREFIX_DS
)
12379 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12384 /* Fall through. */
12387 if (l
!= 0 || len
!= 1)
12395 if (sizeflag
& SUFFIX_ALWAYS
)
12399 if (intel_mnemonic
!= cond
)
12403 if ((prefixes
& PREFIX_FWAIT
) == 0)
12406 used_prefixes
|= PREFIX_FWAIT
;
12412 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12416 if (!(rex
& REX_W
))
12417 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12421 && address_mode
== mode_64bit
12422 && (sizeflag
& DFLAG
))
12427 /* Fall through. */
12431 if ((rex
& REX_W
) == 0
12432 && (prefixes
& PREFIX_DATA
))
12434 if ((sizeflag
& DFLAG
) == 0)
12436 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12440 if ((prefixes
& PREFIX_DATA
)
12442 || (sizeflag
& SUFFIX_ALWAYS
))
12449 if (sizeflag
& DFLAG
)
12453 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12460 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12462 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12466 /* Fall through. */
12469 if (l
== 0 && len
== 1)
12472 if (intel_syntax
&& !alt
)
12475 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12481 if (sizeflag
& DFLAG
)
12482 *obufp
++ = intel_syntax
? 'd' : 'l';
12485 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12491 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12497 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12512 else if (sizeflag
& DFLAG
)
12521 if (intel_syntax
&& !p
[1]
12522 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
12524 if (!(rex
& REX_W
))
12525 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12528 if (l
== 0 && len
== 1)
12532 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12534 if (sizeflag
& SUFFIX_ALWAYS
)
12556 /* Fall through. */
12559 if (l
== 0 && len
== 1)
12564 if (sizeflag
& SUFFIX_ALWAYS
)
12570 if (sizeflag
& DFLAG
)
12574 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12588 if (address_mode
== mode_64bit
12589 && !(prefixes
& PREFIX_ADDR
))
12600 if (l
!= 0 || len
!= 1)
12605 if (need_vex
&& vex
.prefix
)
12607 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
12614 if (prefixes
& PREFIX_DATA
)
12618 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12622 if (l
== 0 && len
== 1)
12624 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12635 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12643 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12645 switch (vex
.length
)
12659 if (l
== 0 && len
== 1)
12661 /* operand size flag for cwtl, cbtw */
12670 else if (sizeflag
& DFLAG
)
12674 if (!(rex
& REX_W
))
12675 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12679 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12686 *obufp
++ = vex
.w
? 'd': 's';
12693 mnemonicendp
= obufp
;
12698 oappend (const char *s
)
12700 obufp
= stpcpy (obufp
, s
);
12706 if (prefixes
& PREFIX_CS
)
12708 used_prefixes
|= PREFIX_CS
;
12709 oappend ("%cs:" + intel_syntax
);
12711 if (prefixes
& PREFIX_DS
)
12713 used_prefixes
|= PREFIX_DS
;
12714 oappend ("%ds:" + intel_syntax
);
12716 if (prefixes
& PREFIX_SS
)
12718 used_prefixes
|= PREFIX_SS
;
12719 oappend ("%ss:" + intel_syntax
);
12721 if (prefixes
& PREFIX_ES
)
12723 used_prefixes
|= PREFIX_ES
;
12724 oappend ("%es:" + intel_syntax
);
12726 if (prefixes
& PREFIX_FS
)
12728 used_prefixes
|= PREFIX_FS
;
12729 oappend ("%fs:" + intel_syntax
);
12731 if (prefixes
& PREFIX_GS
)
12733 used_prefixes
|= PREFIX_GS
;
12734 oappend ("%gs:" + intel_syntax
);
12739 OP_indirE (int bytemode
, int sizeflag
)
12743 OP_E (bytemode
, sizeflag
);
12747 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
12749 if (address_mode
== mode_64bit
)
12757 sprintf_vma (tmp
, disp
);
12758 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
12759 strcpy (buf
+ 2, tmp
+ i
);
12763 bfd_signed_vma v
= disp
;
12770 /* Check for possible overflow on 0x8000000000000000. */
12773 strcpy (buf
, "9223372036854775808");
12787 tmp
[28 - i
] = (v
% 10) + '0';
12791 strcpy (buf
, tmp
+ 29 - i
);
12797 sprintf (buf
, "0x%x", (unsigned int) disp
);
12799 sprintf (buf
, "%d", (int) disp
);
12803 /* Put DISP in BUF as signed hex number. */
12806 print_displacement (char *buf
, bfd_vma disp
)
12808 bfd_signed_vma val
= disp
;
12817 /* Check for possible overflow. */
12820 switch (address_mode
)
12823 strcpy (buf
+ j
, "0x8000000000000000");
12826 strcpy (buf
+ j
, "0x80000000");
12829 strcpy (buf
+ j
, "0x8000");
12839 sprintf_vma (tmp
, (bfd_vma
) val
);
12840 for (i
= 0; tmp
[i
] == '0'; i
++)
12842 if (tmp
[i
] == '\0')
12844 strcpy (buf
+ j
, tmp
+ i
);
12848 intel_operand_size (int bytemode
, int sizeflag
)
12855 oappend ("BYTE PTR ");
12859 oappend ("WORD PTR ");
12862 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12864 oappend ("QWORD PTR ");
12873 oappend ("QWORD PTR ");
12876 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
12877 oappend ("DWORD PTR ");
12879 oappend ("WORD PTR ");
12880 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12884 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12886 oappend ("WORD PTR ");
12887 if (!(rex
& REX_W
))
12888 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12891 if (sizeflag
& DFLAG
)
12892 oappend ("QWORD PTR ");
12894 oappend ("DWORD PTR ");
12895 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12898 case d_scalar_mode
:
12899 case d_scalar_swap_mode
:
12902 oappend ("DWORD PTR ");
12905 case q_scalar_mode
:
12906 case q_scalar_swap_mode
:
12908 oappend ("QWORD PTR ");
12911 if (address_mode
== mode_64bit
)
12912 oappend ("QWORD PTR ");
12914 oappend ("DWORD PTR ");
12917 if (sizeflag
& DFLAG
)
12918 oappend ("FWORD PTR ");
12920 oappend ("DWORD PTR ");
12921 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12924 oappend ("TBYTE PTR ");
12930 switch (vex
.length
)
12933 oappend ("XMMWORD PTR ");
12936 oappend ("YMMWORD PTR ");
12943 oappend ("XMMWORD PTR ");
12946 oappend ("XMMWORD PTR ");
12952 switch (vex
.length
)
12955 oappend ("QWORD PTR ");
12958 oappend ("XMMWORD PTR ");
12968 switch (vex
.length
)
12971 oappend ("QWORD PTR ");
12974 oappend ("YMMWORD PTR ");
12981 oappend ("OWORD PTR ");
12983 case vex_w_dq_mode
:
12984 case vex_scalar_w_dq_mode
:
12989 oappend ("QWORD PTR ");
12991 oappend ("DWORD PTR ");
12999 OP_E_register (int bytemode
, int sizeflag
)
13001 int reg
= modrm
.rm
;
13002 const char **names
;
13008 if ((sizeflag
& SUFFIX_ALWAYS
)
13009 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
13032 names
= address_mode
== mode_64bit
? names64
: names32
;
13035 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
13053 if ((sizeflag
& DFLAG
)
13054 || (bytemode
!= v_mode
13055 && bytemode
!= v_swap_mode
))
13059 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13065 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13068 oappend (names
[reg
]);
13072 OP_E_memory (int bytemode
, int sizeflag
)
13075 int add
= (rex
& REX_B
) ? 8 : 0;
13080 intel_operand_size (bytemode
, sizeflag
);
13083 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13085 /* 32/64 bit address mode */
13103 vindex
= sib
.index
;
13109 haveindex
= vindex
!= 4;
13112 rbase
= base
+ add
;
13120 if (address_mode
== mode_64bit
&& !havesib
)
13126 FETCH_DATA (the_info
, codep
+ 1);
13128 if ((disp
& 0x80) != 0)
13136 /* In 32bit mode, we need index register to tell [offset] from
13137 [eiz*1 + offset]. */
13138 needindex
= (havesib
13141 && address_mode
== mode_32bit
);
13142 havedisp
= (havebase
13144 || (havesib
&& (haveindex
|| scale
!= 0)));
13147 if (modrm
.mod
!= 0 || base
== 5)
13149 if (havedisp
|| riprel
)
13150 print_displacement (scratchbuf
, disp
);
13152 print_operand_value (scratchbuf
, 1, disp
);
13153 oappend (scratchbuf
);
13157 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
13161 if (havebase
|| haveindex
|| riprel
)
13162 used_prefixes
|= PREFIX_ADDR
;
13164 if (havedisp
|| (intel_syntax
&& riprel
))
13166 *obufp
++ = open_char
;
13167 if (intel_syntax
&& riprel
)
13170 oappend (sizeflag
& AFLAG
? "rip" : "eip");
13174 oappend (address_mode
== mode_64bit
&& (sizeflag
& AFLAG
)
13175 ? names64
[rbase
] : names32
[rbase
]);
13178 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13179 print index to tell base + index from base. */
13183 || (havebase
&& base
!= ESP_REG_NUM
))
13185 if (!intel_syntax
|| havebase
)
13187 *obufp
++ = separator_char
;
13191 oappend (address_mode
== mode_64bit
13192 && (sizeflag
& AFLAG
)
13193 ? names64
[vindex
] : names32
[vindex
]);
13195 oappend (address_mode
== mode_64bit
13196 && (sizeflag
& AFLAG
)
13197 ? index64
: index32
);
13199 *obufp
++ = scale_char
;
13201 sprintf (scratchbuf
, "%d", 1 << scale
);
13202 oappend (scratchbuf
);
13206 && (disp
|| modrm
.mod
!= 0 || base
== 5))
13208 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
13213 else if (modrm
.mod
!= 1 && disp
!= -disp
)
13217 disp
= - (bfd_signed_vma
) disp
;
13221 print_displacement (scratchbuf
, disp
);
13223 print_operand_value (scratchbuf
, 1, disp
);
13224 oappend (scratchbuf
);
13227 *obufp
++ = close_char
;
13230 else if (intel_syntax
)
13232 if (modrm
.mod
!= 0 || base
== 5)
13234 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13235 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13239 oappend (names_seg
[ds_reg
- es_reg
]);
13242 print_operand_value (scratchbuf
, 1, disp
);
13243 oappend (scratchbuf
);
13249 /* 16 bit address mode */
13250 used_prefixes
|= prefixes
& PREFIX_ADDR
;
13257 if ((disp
& 0x8000) != 0)
13262 FETCH_DATA (the_info
, codep
+ 1);
13264 if ((disp
& 0x80) != 0)
13269 if ((disp
& 0x8000) != 0)
13275 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
13277 print_displacement (scratchbuf
, disp
);
13278 oappend (scratchbuf
);
13281 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
13283 *obufp
++ = open_char
;
13285 oappend (index16
[modrm
.rm
]);
13287 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
13289 if ((bfd_signed_vma
) disp
>= 0)
13294 else if (modrm
.mod
!= 1)
13298 disp
= - (bfd_signed_vma
) disp
;
13301 print_displacement (scratchbuf
, disp
);
13302 oappend (scratchbuf
);
13305 *obufp
++ = close_char
;
13308 else if (intel_syntax
)
13310 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13311 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13315 oappend (names_seg
[ds_reg
- es_reg
]);
13318 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
13319 oappend (scratchbuf
);
13325 OP_E (int bytemode
, int sizeflag
)
13327 /* Skip mod/rm byte. */
13331 if (modrm
.mod
== 3)
13332 OP_E_register (bytemode
, sizeflag
);
13334 OP_E_memory (bytemode
, sizeflag
);
13338 OP_G (int bytemode
, int sizeflag
)
13349 oappend (names8rex
[modrm
.reg
+ add
]);
13351 oappend (names8
[modrm
.reg
+ add
]);
13354 oappend (names16
[modrm
.reg
+ add
]);
13357 oappend (names32
[modrm
.reg
+ add
]);
13360 oappend (names64
[modrm
.reg
+ add
]);
13369 oappend (names64
[modrm
.reg
+ add
]);
13372 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
13373 oappend (names32
[modrm
.reg
+ add
]);
13375 oappend (names16
[modrm
.reg
+ add
]);
13376 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13380 if (address_mode
== mode_64bit
)
13381 oappend (names64
[modrm
.reg
+ add
]);
13383 oappend (names32
[modrm
.reg
+ add
]);
13386 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13399 FETCH_DATA (the_info
, codep
+ 8);
13400 a
= *codep
++ & 0xff;
13401 a
|= (*codep
++ & 0xff) << 8;
13402 a
|= (*codep
++ & 0xff) << 16;
13403 a
|= (*codep
++ & 0xff) << 24;
13404 b
= *codep
++ & 0xff;
13405 b
|= (*codep
++ & 0xff) << 8;
13406 b
|= (*codep
++ & 0xff) << 16;
13407 b
|= (*codep
++ & 0xff) << 24;
13408 x
= a
+ ((bfd_vma
) b
<< 32);
13416 static bfd_signed_vma
13419 bfd_signed_vma x
= 0;
13421 FETCH_DATA (the_info
, codep
+ 4);
13422 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13423 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13424 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13425 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13429 static bfd_signed_vma
13432 bfd_signed_vma x
= 0;
13434 FETCH_DATA (the_info
, codep
+ 4);
13435 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13436 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13437 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13438 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13440 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
13450 FETCH_DATA (the_info
, codep
+ 2);
13451 x
= *codep
++ & 0xff;
13452 x
|= (*codep
++ & 0xff) << 8;
13457 set_op (bfd_vma op
, int riprel
)
13459 op_index
[op_ad
] = op_ad
;
13460 if (address_mode
== mode_64bit
)
13462 op_address
[op_ad
] = op
;
13463 op_riprel
[op_ad
] = riprel
;
13467 /* Mask to get a 32-bit address. */
13468 op_address
[op_ad
] = op
& 0xffffffff;
13469 op_riprel
[op_ad
] = riprel
& 0xffffffff;
13474 OP_REG (int code
, int sizeflag
)
13486 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13487 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13488 s
= names16
[code
- ax_reg
+ add
];
13490 case es_reg
: case ss_reg
: case cs_reg
:
13491 case ds_reg
: case fs_reg
: case gs_reg
:
13492 s
= names_seg
[code
- es_reg
+ add
];
13494 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13495 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13498 s
= names8rex
[code
- al_reg
+ add
];
13500 s
= names8
[code
- al_reg
];
13502 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
13503 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
13504 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
13506 s
= names64
[code
- rAX_reg
+ add
];
13509 code
+= eAX_reg
- rAX_reg
;
13510 /* Fall through. */
13511 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13512 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13515 s
= names64
[code
- eAX_reg
+ add
];
13518 if (sizeflag
& DFLAG
)
13519 s
= names32
[code
- eAX_reg
+ add
];
13521 s
= names16
[code
- eAX_reg
+ add
];
13522 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13526 s
= INTERNAL_DISASSEMBLER_ERROR
;
13533 OP_IMREG (int code
, int sizeflag
)
13545 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13546 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13547 s
= names16
[code
- ax_reg
];
13549 case es_reg
: case ss_reg
: case cs_reg
:
13550 case ds_reg
: case fs_reg
: case gs_reg
:
13551 s
= names_seg
[code
- es_reg
];
13553 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13554 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13557 s
= names8rex
[code
- al_reg
];
13559 s
= names8
[code
- al_reg
];
13561 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13562 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13565 s
= names64
[code
- eAX_reg
];
13568 if (sizeflag
& DFLAG
)
13569 s
= names32
[code
- eAX_reg
];
13571 s
= names16
[code
- eAX_reg
];
13572 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13575 case z_mode_ax_reg
:
13576 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13580 if (!(rex
& REX_W
))
13581 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13584 s
= INTERNAL_DISASSEMBLER_ERROR
;
13591 OP_I (int bytemode
, int sizeflag
)
13594 bfd_signed_vma mask
= -1;
13599 FETCH_DATA (the_info
, codep
+ 1);
13604 if (address_mode
== mode_64bit
)
13609 /* Fall through. */
13616 if (sizeflag
& DFLAG
)
13626 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13638 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13643 scratchbuf
[0] = '$';
13644 print_operand_value (scratchbuf
+ 1, 1, op
);
13645 oappend (scratchbuf
+ intel_syntax
);
13646 scratchbuf
[0] = '\0';
13650 OP_I64 (int bytemode
, int sizeflag
)
13653 bfd_signed_vma mask
= -1;
13655 if (address_mode
!= mode_64bit
)
13657 OP_I (bytemode
, sizeflag
);
13664 FETCH_DATA (the_info
, codep
+ 1);
13674 if (sizeflag
& DFLAG
)
13684 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13692 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13697 scratchbuf
[0] = '$';
13698 print_operand_value (scratchbuf
+ 1, 1, op
);
13699 oappend (scratchbuf
+ intel_syntax
);
13700 scratchbuf
[0] = '\0';
13704 OP_sI (int bytemode
, int sizeflag
)
13711 FETCH_DATA (the_info
, codep
+ 1);
13713 if ((op
& 0x80) != 0)
13717 if (sizeflag
& DFLAG
)
13723 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13727 scratchbuf
[0] = '$';
13728 print_operand_value (scratchbuf
+ 1, 1, op
);
13729 oappend (scratchbuf
+ intel_syntax
);
13733 OP_J (int bytemode
, int sizeflag
)
13737 bfd_vma segment
= 0;
13742 FETCH_DATA (the_info
, codep
+ 1);
13744 if ((disp
& 0x80) != 0)
13749 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
13754 if ((disp
& 0x8000) != 0)
13756 /* In 16bit mode, address is wrapped around at 64k within
13757 the same segment. Otherwise, a data16 prefix on a jump
13758 instruction means that the pc is masked to 16 bits after
13759 the displacement is added! */
13761 if ((prefixes
& PREFIX_DATA
) == 0)
13762 segment
= ((start_pc
+ codep
- start_codep
)
13763 & ~((bfd_vma
) 0xffff));
13765 if (!(rex
& REX_W
))
13766 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13769 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13772 disp
= ((start_pc
+ codep
- start_codep
+ disp
) & mask
) | segment
;
13774 print_operand_value (scratchbuf
, 1, disp
);
13775 oappend (scratchbuf
);
13779 OP_SEG (int bytemode
, int sizeflag
)
13781 if (bytemode
== w_mode
)
13782 oappend (names_seg
[modrm
.reg
]);
13784 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
13788 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
13792 if (sizeflag
& DFLAG
)
13802 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13804 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
13806 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
13807 oappend (scratchbuf
);
13811 OP_OFF (int bytemode
, int sizeflag
)
13815 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13816 intel_operand_size (bytemode
, sizeflag
);
13819 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13826 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13827 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13829 oappend (names_seg
[ds_reg
- es_reg
]);
13833 print_operand_value (scratchbuf
, 1, off
);
13834 oappend (scratchbuf
);
13838 OP_OFF64 (int bytemode
, int sizeflag
)
13842 if (address_mode
!= mode_64bit
13843 || (prefixes
& PREFIX_ADDR
))
13845 OP_OFF (bytemode
, sizeflag
);
13849 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13850 intel_operand_size (bytemode
, sizeflag
);
13857 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13858 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13860 oappend (names_seg
[ds_reg
- es_reg
]);
13864 print_operand_value (scratchbuf
, 1, off
);
13865 oappend (scratchbuf
);
13869 ptr_reg (int code
, int sizeflag
)
13873 *obufp
++ = open_char
;
13874 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13875 if (address_mode
== mode_64bit
)
13877 if (!(sizeflag
& AFLAG
))
13878 s
= names32
[code
- eAX_reg
];
13880 s
= names64
[code
- eAX_reg
];
13882 else if (sizeflag
& AFLAG
)
13883 s
= names32
[code
- eAX_reg
];
13885 s
= names16
[code
- eAX_reg
];
13887 *obufp
++ = close_char
;
13892 OP_ESreg (int code
, int sizeflag
)
13898 case 0x6d: /* insw/insl */
13899 intel_operand_size (z_mode
, sizeflag
);
13901 case 0xa5: /* movsw/movsl/movsq */
13902 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13903 case 0xab: /* stosw/stosl */
13904 case 0xaf: /* scasw/scasl */
13905 intel_operand_size (v_mode
, sizeflag
);
13908 intel_operand_size (b_mode
, sizeflag
);
13911 oappend ("%es:" + intel_syntax
);
13912 ptr_reg (code
, sizeflag
);
13916 OP_DSreg (int code
, int sizeflag
)
13922 case 0x6f: /* outsw/outsl */
13923 intel_operand_size (z_mode
, sizeflag
);
13925 case 0xa5: /* movsw/movsl/movsq */
13926 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13927 case 0xad: /* lodsw/lodsl/lodsq */
13928 intel_operand_size (v_mode
, sizeflag
);
13931 intel_operand_size (b_mode
, sizeflag
);
13940 | PREFIX_GS
)) == 0)
13941 prefixes
|= PREFIX_DS
;
13943 ptr_reg (code
, sizeflag
);
13947 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13955 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
13957 all_prefixes
[last_lock_prefix
] = 0;
13958 used_prefixes
|= PREFIX_LOCK
;
13963 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
13964 oappend (scratchbuf
+ intel_syntax
);
13968 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13977 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
13979 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
13980 oappend (scratchbuf
);
13984 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13986 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
13987 oappend (scratchbuf
+ intel_syntax
);
13991 OP_R (int bytemode
, int sizeflag
)
13993 if (modrm
.mod
== 3)
13994 OP_E (bytemode
, sizeflag
);
14000 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14002 int reg
= modrm
.reg
;
14003 const char **names
;
14005 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14006 if (prefixes
& PREFIX_DATA
)
14015 oappend (names
[reg
]);
14019 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14021 int reg
= modrm
.reg
;
14022 const char **names
;
14028 && bytemode
!= xmm_mode
14029 && bytemode
!= scalar_mode
)
14031 switch (vex
.length
)
14045 oappend (names
[reg
]);
14049 OP_EM (int bytemode
, int sizeflag
)
14052 const char **names
;
14054 if (modrm
.mod
!= 3)
14057 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
14059 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14060 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14062 OP_E (bytemode
, sizeflag
);
14066 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
14069 /* Skip mod/rm byte. */
14072 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14074 if (prefixes
& PREFIX_DATA
)
14083 oappend (names
[reg
]);
14086 /* cvt* are the only instructions in sse2 which have
14087 both SSE and MMX operands and also have 0x66 prefix
14088 in their opcode. 0x66 was originally used to differentiate
14089 between SSE and MMX instruction(operands). So we have to handle the
14090 cvt* separately using OP_EMC and OP_MXC */
14092 OP_EMC (int bytemode
, int sizeflag
)
14094 if (modrm
.mod
!= 3)
14096 if (intel_syntax
&& bytemode
== v_mode
)
14098 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14099 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14101 OP_E (bytemode
, sizeflag
);
14105 /* Skip mod/rm byte. */
14108 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14109 oappend (names_mm
[modrm
.rm
]);
14113 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14115 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14116 oappend (names_mm
[modrm
.reg
]);
14120 OP_EX (int bytemode
, int sizeflag
)
14123 const char **names
;
14125 /* Skip mod/rm byte. */
14129 if (modrm
.mod
!= 3)
14131 OP_E_memory (bytemode
, sizeflag
);
14140 if ((sizeflag
& SUFFIX_ALWAYS
)
14141 && (bytemode
== x_swap_mode
14142 || bytemode
== d_swap_mode
14143 || bytemode
== d_scalar_swap_mode
14144 || bytemode
== q_swap_mode
14145 || bytemode
== q_scalar_swap_mode
))
14149 && bytemode
!= xmm_mode
14150 && bytemode
!= xmmq_mode
14151 && bytemode
!= d_scalar_mode
14152 && bytemode
!= d_scalar_swap_mode
14153 && bytemode
!= q_scalar_mode
14154 && bytemode
!= q_scalar_swap_mode
14155 && bytemode
!= vex_scalar_w_dq_mode
)
14157 switch (vex
.length
)
14171 oappend (names
[reg
]);
14175 OP_MS (int bytemode
, int sizeflag
)
14177 if (modrm
.mod
== 3)
14178 OP_EM (bytemode
, sizeflag
);
14184 OP_XS (int bytemode
, int sizeflag
)
14186 if (modrm
.mod
== 3)
14187 OP_EX (bytemode
, sizeflag
);
14193 OP_M (int bytemode
, int sizeflag
)
14195 if (modrm
.mod
== 3)
14196 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14199 OP_E (bytemode
, sizeflag
);
14203 OP_0f07 (int bytemode
, int sizeflag
)
14205 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
14208 OP_E (bytemode
, sizeflag
);
14211 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14212 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14215 NOP_Fixup1 (int bytemode
, int sizeflag
)
14217 if ((prefixes
& PREFIX_DATA
) != 0
14220 && address_mode
== mode_64bit
))
14221 OP_REG (bytemode
, sizeflag
);
14223 strcpy (obuf
, "nop");
14227 NOP_Fixup2 (int bytemode
, int sizeflag
)
14229 if ((prefixes
& PREFIX_DATA
) != 0
14232 && address_mode
== mode_64bit
))
14233 OP_IMREG (bytemode
, sizeflag
);
14236 static const char *const Suffix3DNow
[] = {
14237 /* 00 */ NULL
, NULL
, NULL
, NULL
,
14238 /* 04 */ NULL
, NULL
, NULL
, NULL
,
14239 /* 08 */ NULL
, NULL
, NULL
, NULL
,
14240 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
14241 /* 10 */ NULL
, NULL
, NULL
, NULL
,
14242 /* 14 */ NULL
, NULL
, NULL
, NULL
,
14243 /* 18 */ NULL
, NULL
, NULL
, NULL
,
14244 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
14245 /* 20 */ NULL
, NULL
, NULL
, NULL
,
14246 /* 24 */ NULL
, NULL
, NULL
, NULL
,
14247 /* 28 */ NULL
, NULL
, NULL
, NULL
,
14248 /* 2C */ NULL
, NULL
, NULL
, NULL
,
14249 /* 30 */ NULL
, NULL
, NULL
, NULL
,
14250 /* 34 */ NULL
, NULL
, NULL
, NULL
,
14251 /* 38 */ NULL
, NULL
, NULL
, NULL
,
14252 /* 3C */ NULL
, NULL
, NULL
, NULL
,
14253 /* 40 */ NULL
, NULL
, NULL
, NULL
,
14254 /* 44 */ NULL
, NULL
, NULL
, NULL
,
14255 /* 48 */ NULL
, NULL
, NULL
, NULL
,
14256 /* 4C */ NULL
, NULL
, NULL
, NULL
,
14257 /* 50 */ NULL
, NULL
, NULL
, NULL
,
14258 /* 54 */ NULL
, NULL
, NULL
, NULL
,
14259 /* 58 */ NULL
, NULL
, NULL
, NULL
,
14260 /* 5C */ NULL
, NULL
, NULL
, NULL
,
14261 /* 60 */ NULL
, NULL
, NULL
, NULL
,
14262 /* 64 */ NULL
, NULL
, NULL
, NULL
,
14263 /* 68 */ NULL
, NULL
, NULL
, NULL
,
14264 /* 6C */ NULL
, NULL
, NULL
, NULL
,
14265 /* 70 */ NULL
, NULL
, NULL
, NULL
,
14266 /* 74 */ NULL
, NULL
, NULL
, NULL
,
14267 /* 78 */ NULL
, NULL
, NULL
, NULL
,
14268 /* 7C */ NULL
, NULL
, NULL
, NULL
,
14269 /* 80 */ NULL
, NULL
, NULL
, NULL
,
14270 /* 84 */ NULL
, NULL
, NULL
, NULL
,
14271 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
14272 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
14273 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
14274 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
14275 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
14276 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
14277 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
14278 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
14279 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
14280 /* AC */ NULL
, NULL
, "pfacc", NULL
,
14281 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
14282 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
14283 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
14284 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
14285 /* C0 */ NULL
, NULL
, NULL
, NULL
,
14286 /* C4 */ NULL
, NULL
, NULL
, NULL
,
14287 /* C8 */ NULL
, NULL
, NULL
, NULL
,
14288 /* CC */ NULL
, NULL
, NULL
, NULL
,
14289 /* D0 */ NULL
, NULL
, NULL
, NULL
,
14290 /* D4 */ NULL
, NULL
, NULL
, NULL
,
14291 /* D8 */ NULL
, NULL
, NULL
, NULL
,
14292 /* DC */ NULL
, NULL
, NULL
, NULL
,
14293 /* E0 */ NULL
, NULL
, NULL
, NULL
,
14294 /* E4 */ NULL
, NULL
, NULL
, NULL
,
14295 /* E8 */ NULL
, NULL
, NULL
, NULL
,
14296 /* EC */ NULL
, NULL
, NULL
, NULL
,
14297 /* F0 */ NULL
, NULL
, NULL
, NULL
,
14298 /* F4 */ NULL
, NULL
, NULL
, NULL
,
14299 /* F8 */ NULL
, NULL
, NULL
, NULL
,
14300 /* FC */ NULL
, NULL
, NULL
, NULL
,
14304 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14306 const char *mnemonic
;
14308 FETCH_DATA (the_info
, codep
+ 1);
14309 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14310 place where an 8-bit immediate would normally go. ie. the last
14311 byte of the instruction. */
14312 obufp
= mnemonicendp
;
14313 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
14315 oappend (mnemonic
);
14318 /* Since a variable sized modrm/sib chunk is between the start
14319 of the opcode (0x0f0f) and the opcode suffix, we need to do
14320 all the modrm processing first, and don't know until now that
14321 we have a bad opcode. This necessitates some cleaning up. */
14322 op_out
[0][0] = '\0';
14323 op_out
[1][0] = '\0';
14326 mnemonicendp
= obufp
;
14329 static struct op simd_cmp_op
[] =
14331 { STRING_COMMA_LEN ("eq") },
14332 { STRING_COMMA_LEN ("lt") },
14333 { STRING_COMMA_LEN ("le") },
14334 { STRING_COMMA_LEN ("unord") },
14335 { STRING_COMMA_LEN ("neq") },
14336 { STRING_COMMA_LEN ("nlt") },
14337 { STRING_COMMA_LEN ("nle") },
14338 { STRING_COMMA_LEN ("ord") }
14342 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14344 unsigned int cmp_type
;
14346 FETCH_DATA (the_info
, codep
+ 1);
14347 cmp_type
= *codep
++ & 0xff;
14348 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
14351 char *p
= mnemonicendp
- 2;
14355 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
14356 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
14360 /* We have a reserved extension byte. Output it directly. */
14361 scratchbuf
[0] = '$';
14362 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14363 oappend (scratchbuf
+ intel_syntax
);
14364 scratchbuf
[0] = '\0';
14369 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
14370 int sizeflag ATTRIBUTE_UNUSED
)
14372 /* mwait %eax,%ecx */
14375 const char **names
= (address_mode
== mode_64bit
14376 ? names64
: names32
);
14377 strcpy (op_out
[0], names
[0]);
14378 strcpy (op_out
[1], names
[1]);
14379 two_source_ops
= 1;
14381 /* Skip mod/rm byte. */
14387 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
14388 int sizeflag ATTRIBUTE_UNUSED
)
14390 /* monitor %eax,%ecx,%edx" */
14393 const char **op1_names
;
14394 const char **names
= (address_mode
== mode_64bit
14395 ? names64
: names32
);
14397 if (!(prefixes
& PREFIX_ADDR
))
14398 op1_names
= (address_mode
== mode_16bit
14399 ? names16
: names
);
14402 /* Remove "addr16/addr32". */
14403 all_prefixes
[last_addr_prefix
] = 0;
14404 op1_names
= (address_mode
!= mode_32bit
14405 ? names32
: names16
);
14406 used_prefixes
|= PREFIX_ADDR
;
14408 strcpy (op_out
[0], op1_names
[0]);
14409 strcpy (op_out
[1], names
[1]);
14410 strcpy (op_out
[2], names
[2]);
14411 two_source_ops
= 1;
14413 /* Skip mod/rm byte. */
14421 /* Throw away prefixes and 1st. opcode byte. */
14422 codep
= insn_codep
+ 1;
14427 REP_Fixup (int bytemode
, int sizeflag
)
14429 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14431 if (prefixes
& PREFIX_REPZ
)
14432 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
14439 OP_IMREG (bytemode
, sizeflag
);
14442 OP_ESreg (bytemode
, sizeflag
);
14445 OP_DSreg (bytemode
, sizeflag
);
14454 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
14459 /* Change cmpxchg8b to cmpxchg16b. */
14460 char *p
= mnemonicendp
- 2;
14461 mnemonicendp
= stpcpy (p
, "16b");
14464 OP_M (bytemode
, sizeflag
);
14468 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
14470 const char **names
;
14474 switch (vex
.length
)
14488 oappend (names
[reg
]);
14492 CRC32_Fixup (int bytemode
, int sizeflag
)
14494 /* Add proper suffix to "crc32". */
14495 char *p
= mnemonicendp
;
14514 if (sizeflag
& DFLAG
)
14518 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14522 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14529 if (modrm
.mod
== 3)
14533 /* Skip mod/rm byte. */
14538 add
= (rex
& REX_B
) ? 8 : 0;
14539 if (bytemode
== b_mode
)
14543 oappend (names8rex
[modrm
.rm
+ add
]);
14545 oappend (names8
[modrm
.rm
+ add
]);
14551 oappend (names64
[modrm
.rm
+ add
]);
14552 else if ((prefixes
& PREFIX_DATA
))
14553 oappend (names16
[modrm
.rm
+ add
]);
14555 oappend (names32
[modrm
.rm
+ add
]);
14559 OP_E (bytemode
, sizeflag
);
14563 FXSAVE_Fixup (int bytemode
, int sizeflag
)
14565 /* Add proper suffix to "fxsave" and "fxrstor". */
14569 char *p
= mnemonicendp
;
14575 OP_M (bytemode
, sizeflag
);
14578 /* Display the destination register operand for instructions with
14582 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14585 const char **names
;
14593 reg
= vex
.register_specifier
;
14594 if (bytemode
== vex_scalar_mode
)
14596 oappend (names_xmm
[reg
]);
14600 switch (vex
.length
)
14637 oappend (names
[reg
]);
14640 /* Get the VEX immediate byte without moving codep. */
14642 static unsigned char
14643 get_vex_imm8 (int sizeflag
, int opnum
)
14645 int bytes_before_imm
= 0;
14647 if (modrm
.mod
!= 3)
14649 /* There are SIB/displacement bytes. */
14650 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14652 /* 32/64 bit address mode */
14653 int base
= modrm
.rm
;
14655 /* Check SIB byte. */
14658 FETCH_DATA (the_info
, codep
+ 1);
14660 /* When decoding the third source, don't increase
14661 bytes_before_imm as this has already been incremented
14662 by one in OP_E_memory while decoding the second
14665 bytes_before_imm
++;
14668 /* Don't increase bytes_before_imm when decoding the third source,
14669 it has already been incremented by OP_E_memory while decoding
14670 the second source operand. */
14676 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14677 SIB == 5, there is a 4 byte displacement. */
14679 /* No displacement. */
14682 /* 4 byte displacement. */
14683 bytes_before_imm
+= 4;
14686 /* 1 byte displacement. */
14687 bytes_before_imm
++;
14694 /* 16 bit address mode */
14695 /* Don't increase bytes_before_imm when decoding the third source,
14696 it has already been incremented by OP_E_memory while decoding
14697 the second source operand. */
14703 /* When modrm.rm == 6, there is a 2 byte displacement. */
14705 /* No displacement. */
14708 /* 2 byte displacement. */
14709 bytes_before_imm
+= 2;
14712 /* 1 byte displacement: when decoding the third source,
14713 don't increase bytes_before_imm as this has already
14714 been incremented by one in OP_E_memory while decoding
14715 the second source operand. */
14717 bytes_before_imm
++;
14725 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
14726 return codep
[bytes_before_imm
];
14730 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
14732 const char **names
;
14734 if (reg
== -1 && modrm
.mod
!= 3)
14736 OP_E_memory (bytemode
, sizeflag
);
14748 else if (reg
> 7 && address_mode
!= mode_64bit
)
14752 switch (vex
.length
)
14763 oappend (names
[reg
]);
14767 OP_EX_VexImmW (int bytemode
, int sizeflag
)
14770 static unsigned char vex_imm8
;
14772 if (vex_w_done
== 0)
14776 /* Skip mod/rm byte. */
14780 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
14783 reg
= vex_imm8
>> 4;
14785 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14787 else if (vex_w_done
== 1)
14792 reg
= vex_imm8
>> 4;
14794 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14798 /* Output the imm8 directly. */
14799 scratchbuf
[0] = '$';
14800 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
14801 oappend (scratchbuf
+ intel_syntax
);
14802 scratchbuf
[0] = '\0';
14808 OP_Vex_2src (int bytemode
, int sizeflag
)
14810 if (modrm
.mod
== 3)
14812 int reg
= modrm
.rm
;
14816 oappend (names_xmm
[reg
]);
14821 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
14823 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14824 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14826 OP_E (bytemode
, sizeflag
);
14831 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
14833 if (modrm
.mod
== 3)
14835 /* Skip mod/rm byte. */
14841 oappend (names_xmm
[vex
.register_specifier
]);
14843 OP_Vex_2src (bytemode
, sizeflag
);
14847 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
14850 OP_Vex_2src (bytemode
, sizeflag
);
14852 oappend (names_xmm
[vex
.register_specifier
]);
14856 OP_EX_VexW (int bytemode
, int sizeflag
)
14864 /* Skip mod/rm byte. */
14869 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
14874 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
14877 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14881 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14882 int sizeflag ATTRIBUTE_UNUSED
)
14884 /* Skip the immediate byte and check for invalid bits. */
14885 FETCH_DATA (the_info
, codep
+ 1);
14886 if (*codep
++ & 0xf)
14891 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14894 const char **names
;
14896 FETCH_DATA (the_info
, codep
+ 1);
14899 if (bytemode
!= x_mode
)
14906 if (reg
> 7 && address_mode
!= mode_64bit
)
14909 switch (vex
.length
)
14920 oappend (names
[reg
]);
14924 OP_XMM_VexW (int bytemode
, int sizeflag
)
14926 /* Turn off the REX.W bit since it is used for swapping operands
14929 OP_XMM (bytemode
, sizeflag
);
14933 OP_EX_Vex (int bytemode
, int sizeflag
)
14935 if (modrm
.mod
!= 3)
14937 if (vex
.register_specifier
!= 0)
14941 OP_EX (bytemode
, sizeflag
);
14945 OP_XMM_Vex (int bytemode
, int sizeflag
)
14947 if (modrm
.mod
!= 3)
14949 if (vex
.register_specifier
!= 0)
14953 OP_XMM (bytemode
, sizeflag
);
14957 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14959 switch (vex
.length
)
14962 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
14965 mnemonicendp
= stpcpy (obuf
, "vzeroall");
14972 static struct op vex_cmp_op
[] =
14974 { STRING_COMMA_LEN ("eq") },
14975 { STRING_COMMA_LEN ("lt") },
14976 { STRING_COMMA_LEN ("le") },
14977 { STRING_COMMA_LEN ("unord") },
14978 { STRING_COMMA_LEN ("neq") },
14979 { STRING_COMMA_LEN ("nlt") },
14980 { STRING_COMMA_LEN ("nle") },
14981 { STRING_COMMA_LEN ("ord") },
14982 { STRING_COMMA_LEN ("eq_uq") },
14983 { STRING_COMMA_LEN ("nge") },
14984 { STRING_COMMA_LEN ("ngt") },
14985 { STRING_COMMA_LEN ("false") },
14986 { STRING_COMMA_LEN ("neq_oq") },
14987 { STRING_COMMA_LEN ("ge") },
14988 { STRING_COMMA_LEN ("gt") },
14989 { STRING_COMMA_LEN ("true") },
14990 { STRING_COMMA_LEN ("eq_os") },
14991 { STRING_COMMA_LEN ("lt_oq") },
14992 { STRING_COMMA_LEN ("le_oq") },
14993 { STRING_COMMA_LEN ("unord_s") },
14994 { STRING_COMMA_LEN ("neq_us") },
14995 { STRING_COMMA_LEN ("nlt_uq") },
14996 { STRING_COMMA_LEN ("nle_uq") },
14997 { STRING_COMMA_LEN ("ord_s") },
14998 { STRING_COMMA_LEN ("eq_us") },
14999 { STRING_COMMA_LEN ("nge_uq") },
15000 { STRING_COMMA_LEN ("ngt_uq") },
15001 { STRING_COMMA_LEN ("false_os") },
15002 { STRING_COMMA_LEN ("neq_os") },
15003 { STRING_COMMA_LEN ("ge_oq") },
15004 { STRING_COMMA_LEN ("gt_oq") },
15005 { STRING_COMMA_LEN ("true_us") },
15009 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15011 unsigned int cmp_type
;
15013 FETCH_DATA (the_info
, codep
+ 1);
15014 cmp_type
= *codep
++ & 0xff;
15015 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
15018 char *p
= mnemonicendp
- 2;
15022 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
15023 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
15027 /* We have a reserved extension byte. Output it directly. */
15028 scratchbuf
[0] = '$';
15029 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15030 oappend (scratchbuf
+ intel_syntax
);
15031 scratchbuf
[0] = '\0';
15035 static const struct op pclmul_op
[] =
15037 { STRING_COMMA_LEN ("lql") },
15038 { STRING_COMMA_LEN ("hql") },
15039 { STRING_COMMA_LEN ("lqh") },
15040 { STRING_COMMA_LEN ("hqh") }
15044 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15045 int sizeflag ATTRIBUTE_UNUSED
)
15047 unsigned int pclmul_type
;
15049 FETCH_DATA (the_info
, codep
+ 1);
15050 pclmul_type
= *codep
++ & 0xff;
15051 switch (pclmul_type
)
15062 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
15065 char *p
= mnemonicendp
- 3;
15070 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
15071 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
15075 /* We have a reserved extension byte. Output it directly. */
15076 scratchbuf
[0] = '$';
15077 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
15078 oappend (scratchbuf
+ intel_syntax
);
15079 scratchbuf
[0] = '\0';
15084 MOVBE_Fixup (int bytemode
, int sizeflag
)
15086 /* Add proper suffix to "movbe". */
15087 char *p
= mnemonicendp
;
15096 if (sizeflag
& SUFFIX_ALWAYS
)
15102 if (sizeflag
& DFLAG
)
15106 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15111 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15118 OP_M (bytemode
, sizeflag
);
15122 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15125 const char **names
;
15127 /* Skip mod/rm byte. */
15141 oappend (names
[reg
]);
15145 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15147 const char **names
;
15154 oappend (names
[vex
.register_specifier
]);