include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
   3    2007, 2008, 2009 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 typedef unsigned long ppc_cpu_t;
  26
  27 /* The opcode table is an array of struct powerpc_opcode.  */
  28
  29 struct powerpc_opcode
  30 {
  31   /* The opcode name.  */
  32   const char *name;
  33
  34   /* The opcode itself.  Those bits which will be filled in with
  35      operands are zeroes.  */
  36   unsigned long opcode;
  37
  38   /* The opcode mask.  This is used by the disassembler.  This is a
  39      mask containing ones indicating those bits which must match the
  40      opcode field, and zeroes indicating those bits which need not
  41      match (and are presumably filled in by operands).  */
  42   unsigned long mask;
  43
  44   /* One bit flags for the opcode.  These are used to indicate which
  45      specific processors support the instructions.  The defined values
  46      are listed below.  */
  47   ppc_cpu_t flags;
  48
  49   /* One bit flags for the opcode.  These are used to indicate which
  50      specific processors no longer support the instructions.  The defined
  51      values are listed below.  */
  52   ppc_cpu_t deprecated;
  53
  54   /* An array of operand codes.  Each code is an index into the
  55      operand table.  They appear in the order which the operands must
  56      appear in assembly code, and are terminated by a zero.  */
  57   unsigned char operands[8];
  58 };
  59
  60 /* The table itself is sorted by major opcode number, and is otherwise
  61    in the order in which the disassembler should consider
  62    instructions.  */
  63 extern const struct powerpc_opcode powerpc_opcodes[];
  64 extern const int powerpc_num_opcodes;
  65
  66 /* Values defined for the flags field of a struct powerpc_opcode.  */
  67
  68 /* Opcode is defined for the PowerPC architecture.  */
  69 #define PPC_OPCODE_PPC                   1
  70
  71 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  72 #define PPC_OPCODE_POWER                 2
  73
  74 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  75 #define PPC_OPCODE_POWER2                4
  76
  77 /* Opcode is only defined on 32 bit architectures.  */
  78 #define PPC_OPCODE_32                    8
  79
  80 /* Opcode is only defined on 64 bit architectures.  */
  81 #define PPC_OPCODE_64                 0x10
  82
  83 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  84    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  85    but it also supports many additional POWER instructions.  */
  86 #define PPC_OPCODE_601                0x20
  87
  88 /* Opcode is supported in both the Power and PowerPC architectures
  89    (ie, compiler's -mcpu=common or assembler's -mcom).  */
  90 #define PPC_OPCODE_COMMON             0x40
  91
  92 /* Opcode is supported for any Power or PowerPC platform (this is
  93    for the assembler's -many option, and it eliminates duplicates).  */
  94 #define PPC_OPCODE_ANY                0x80
  95
  96 /* Opcode is supported as part of the 64-bit bridge.  */
  97 #define PPC_OPCODE_64_BRIDGE         0x100
  98
  99 /* Opcode is supported by Altivec Vector Unit */
 100 #define PPC_OPCODE_ALTIVEC           0x200
 101
 102 /* Opcode is supported by PowerPC 403 processor.  */
 103 #define PPC_OPCODE_403               0x400
 104
 105 /* Opcode is supported by PowerPC BookE processor.  */
 106 #define PPC_OPCODE_BOOKE             0x800
 107
 108 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
 109 #define PPC_OPCODE_BOOKE64          0x1000
 110
 111 /* Opcode is supported by PowerPC 440 processor.  */
 112 #define PPC_OPCODE_440              0x2000
 113
 114 /* Opcode is only supported by Power4 architecture.  */
 115 #define PPC_OPCODE_POWER4           0x4000
 116
 117 /* Opcode is only supported by Power7 architecture.  */
 118 #define PPC_OPCODE_POWER7           0x8000
 119
 120 /* Opcode is only supported by POWERPC Classic architecture.  */
 121 #define PPC_OPCODE_CLASSIC         0x10000
 122
 123 /* Opcode is only supported by e500x2 Core.  */
 124 #define PPC_OPCODE_SPE             0x20000
 125
 126 /* Opcode is supported by e500x2 Integer select APU.  */
 127 #define PPC_OPCODE_ISEL            0x40000
 128
 129 /* Opcode is an e500 SPE floating point instruction.  */
 130 #define PPC_OPCODE_EFS             0x80000
 131
 132 /* Opcode is supported by branch locking APU.  */
 133 #define PPC_OPCODE_BRLOCK         0x100000
 134
 135 /* Opcode is supported by performance monitor APU.  */
 136 #define PPC_OPCODE_PMR            0x200000
 137
 138 /* Opcode is supported by cache locking APU.  */
 139 #define PPC_OPCODE_CACHELCK       0x400000
 140
 141 /* Opcode is supported by machine check APU.  */
 142 #define PPC_OPCODE_RFMCI          0x800000
 143
 144 /* Opcode is only supported by Power5 architecture.  */
 145 #define PPC_OPCODE_POWER5        0x1000000
 146
 147 /* Opcode is supported by PowerPC e300 family.  */
 148 #define PPC_OPCODE_E300          0x2000000
 149
 150 /* Opcode is only supported by Power6 architecture.  */
 151 #define PPC_OPCODE_POWER6        0x4000000
 152
 153 /* Opcode is only supported by PowerPC Cell family.  */
 154 #define PPC_OPCODE_CELL          0x8000000
 155
 156 /* Opcode is supported by CPUs with paired singles support.  */
 157 #define PPC_OPCODE_PPCPS         0x10000000
 158
 159 /* Opcode is supported by Power E500MC */
 160 #define PPC_OPCODE_E500MC        0x20000000
 161
 162 /* Opcode is supported by PowerPC 405 processor.  */
 163 #define PPC_OPCODE_405           0x40000000
 164
 165 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 166 #define PPC_OPCODE_VSX           0x80000000
 167
 168 /* A macro to extract the major opcode from an instruction.  */
 169 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 170 \f
 171 /* The operands table is an array of struct powerpc_operand.  */
 172
 173 struct powerpc_operand
 174 {
 175   /* A bitmask of bits in the operand.  */
 176   unsigned int bitm;
 177
 178   /* How far the operand is left shifted in the instruction.
 179      -1 to indicate that BITM and SHIFT cannot be used to determine
 180      where the operand goes in the insn.  */
 181   int shift;
 182
 183   /* Insertion function.  This is used by the assembler.  To insert an
 184      operand value into an instruction, check this field.
 185
 186      If it is NULL, execute
 187          i |= (op & o->bitm) << o->shift;
 188      (i is the instruction which we are filling in, o is a pointer to
 189      this structure, and op is the operand value).
 190
 191      If this field is not NULL, then simply call it with the
 192      instruction and the operand value.  It will return the new value
 193      of the instruction.  If the ERRMSG argument is not NULL, then if
 194      the operand value is illegal, *ERRMSG will be set to a warning
 195      string (the operand will be inserted in any case).  If the
 196      operand value is legal, *ERRMSG will be unchanged (most operands
 197      can accept any value).  */
 198   unsigned long (*insert)
 199     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 200
 201   /* Extraction function.  This is used by the disassembler.  To
 202      extract this operand type from an instruction, check this field.
 203
 204      If it is NULL, compute
 205          op = (i >> o->shift) & o->bitm;
 206          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 207            sign_extend (op);
 208      (i is the instruction, o is a pointer to this structure, and op
 209      is the result).
 210
 211      If this field is not NULL, then simply call it with the
 212      instruction value.  It will return the value of the operand.  If
 213      the INVALID argument is not NULL, *INVALID will be set to
 214      non-zero if this operand type can not actually be extracted from
 215      this operand (i.e., the instruction does not match).  If the
 216      operand is valid, *INVALID will not be changed.  */
 217   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 218
 219   /* One bit syntax flags.  */
 220   unsigned long flags;
 221 };
 222
 223 /* Elements in the table are retrieved by indexing with values from
 224    the operands field of the powerpc_opcodes table.  */
 225
 226 extern const struct powerpc_operand powerpc_operands[];
 227 extern const unsigned int num_powerpc_operands;
 228
 229 /* Values defined for the flags field of a struct powerpc_operand.  */
 230
 231 /* This operand takes signed values.  */
 232 #define PPC_OPERAND_SIGNED (0x1)
 233
 234 /* This operand takes signed values, but also accepts a full positive
 235    range of values when running in 32 bit mode.  That is, if bits is
 236    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 237    this flag is ignored.  */
 238 #define PPC_OPERAND_SIGNOPT (0x2)
 239
 240 /* This operand does not actually exist in the assembler input.  This
 241    is used to support extended mnemonics such as mr, for which two
 242    operands fields are identical.  The assembler should call the
 243    insert function with any op value.  The disassembler should call
 244    the extract function, ignore the return value, and check the value
 245    placed in the valid argument.  */
 246 #define PPC_OPERAND_FAKE (0x4)
 247
 248 /* The next operand should be wrapped in parentheses rather than
 249    separated from this one by a comma.  This is used for the load and
 250    store instructions which want their operands to look like
 251        reg,displacement(reg)
 252    */
 253 #define PPC_OPERAND_PARENS (0x8)
 254
 255 /* This operand may use the symbolic names for the CR fields, which
 256    are
 257        lt  0    gt  1   eq  2   so  3   un  3
 258        cr0 0    cr1 1   cr2 2   cr3 3
 259        cr4 4    cr5 5   cr6 6   cr7 7
 260    These may be combined arithmetically, as in cr2*4+gt.  These are
 261    only supported on the PowerPC, not the POWER.  */
 262 #define PPC_OPERAND_CR (0x10)
 263
 264 /* This operand names a register.  The disassembler uses this to print
 265    register names with a leading 'r'.  */
 266 #define PPC_OPERAND_GPR (0x20)
 267
 268 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 269 #define PPC_OPERAND_GPR_0 (0x40)
 270
 271 /* This operand names a floating point register.  The disassembler
 272    prints these with a leading 'f'.  */
 273 #define PPC_OPERAND_FPR (0x80)
 274
 275 /* This operand is a relative branch displacement.  The disassembler
 276    prints these symbolically if possible.  */
 277 #define PPC_OPERAND_RELATIVE (0x100)
 278
 279 /* This operand is an absolute branch address.  The disassembler
 280    prints these symbolically if possible.  */
 281 #define PPC_OPERAND_ABSOLUTE (0x200)
 282
 283 /* This operand is optional, and is zero if omitted.  This is used for
 284    example, in the optional BF field in the comparison instructions.  The
 285    assembler must count the number of operands remaining on the line,
 286    and the number of operands remaining for the opcode, and decide
 287    whether this operand is present or not.  The disassembler should
 288    print this operand out only if it is not zero.  */
 289 #define PPC_OPERAND_OPTIONAL (0x400)
 290
 291 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 292    is omitted, then for the next operand use this operand value plus
 293    1, ignoring the next operand field for the opcode.  This wretched
 294    hack is needed because the Power rotate instructions can take
 295    either 4 or 5 operands.  The disassembler should print this operand
 296    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 297 #define PPC_OPERAND_NEXT (0x800)
 298
 299 /* This operand should be regarded as a negative number for the
 300    purposes of overflow checking (i.e., the normal most negative
 301    number is disallowed and one more than the normal most positive
 302    number is allowed).  This flag will only be set for a signed
 303    operand.  */
 304 #define PPC_OPERAND_NEGATIVE (0x1000)
 305
 306 /* This operand names a vector unit register.  The disassembler
 307    prints these with a leading 'v'.  */
 308 #define PPC_OPERAND_VR (0x2000)
 309
 310 /* This operand is for the DS field in a DS form instruction.  */
 311 #define PPC_OPERAND_DS (0x4000)
 312
 313 /* This operand is for the DQ field in a DQ form instruction.  */
 314 #define PPC_OPERAND_DQ (0x8000)
 315
 316 /* Valid range of operand is 0..n rather than 0..n-1.  */
 317 #define PPC_OPERAND_PLUS1 (0x10000)
 318
 319 /* Xilinx APU and FSL related operands */
 320 #define PPC_OPERAND_FSL (0x20000)
 321 #define PPC_OPERAND_FCR (0x40000)
 322 #define PPC_OPERAND_UDI (0x80000)
 323
 324 /* This operand names a vector-scalar unit register.  The disassembler
 325    prints these with a leading 'vs'.  */
 326 #define PPC_OPERAND_VSR (0x100000)
 327 \f
 328 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 329    with the operands table for simplicity.  The macro table is an
 330    array of struct powerpc_macro.  */
 331
 332 struct powerpc_macro
 333 {
 334   /* The macro name.  */
 335   const char *name;
 336
 337   /* The number of operands the macro takes.  */
 338   unsigned int operands;
 339
 340   /* One bit flags for the opcode.  These are used to indicate which
 341      specific processors support the instructions.  The values are the
 342      same as those for the struct powerpc_opcode flags field.  */
 343   ppc_cpu_t flags;
 344
 345   /* A format string to turn the macro into a normal instruction.
 346      Each %N in the string is replaced with operand number N (zero
 347      based).  */
 348   const char *format;
 349 };
 350
 351 extern const struct powerpc_macro powerpc_macros[];
 352 extern const int powerpc_num_macros;
 353
 354 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
 355
 356 #endif /* PPC_H */