1 /* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 - the resultant file is machine generated, cgen-dis.in isn't
7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
8 2008 Free Software Foundation, Inc.
10 This file is part of libopcodes.
12 This library is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 It is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software Foundation, Inc.,
24 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
35 #include "libiberty.h"
40 /* Default text to print if an instruction isn't recognized. */
41 #define UNKNOWN_INSN_MSG _("*unknown*")
43 static void print_normal
44 (CGEN_CPU_DESC
, void *, long, unsigned int, bfd_vma
, int);
45 static void print_address
46 (CGEN_CPU_DESC
, void *, bfd_vma
, unsigned int, bfd_vma
, int) ATTRIBUTE_UNUSED
;
47 static void print_keyword
48 (CGEN_CPU_DESC
, void *, CGEN_KEYWORD
*, long, unsigned int) ATTRIBUTE_UNUSED
;
49 static void print_insn_normal
50 (CGEN_CPU_DESC
, void *, const CGEN_INSN
*, CGEN_FIELDS
*, bfd_vma
, int);
52 (CGEN_CPU_DESC
, bfd_vma
, disassemble_info
*, bfd_byte
*, unsigned);
53 static int default_print_insn
54 (CGEN_CPU_DESC
, bfd_vma
, disassemble_info
*) ATTRIBUTE_UNUSED
;
56 (CGEN_CPU_DESC
, bfd_vma
, disassemble_info
*, bfd_byte
*, int, CGEN_EXTRACT_INFO
*,
59 /* -- disassembler routines inserted here. */
66 #define CGEN_VALIDATE_INSN_SUPPORTED
68 static void print_tpreg (CGEN_CPU_DESC
, PTR
, CGEN_KEYWORD
*, long, unsigned int);
69 static void print_spreg (CGEN_CPU_DESC
, PTR
, CGEN_KEYWORD
*, long, unsigned int);
72 print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
, PTR dis_info
,
73 CGEN_KEYWORD
*table ATTRIBUTE_UNUSED
, long val ATTRIBUTE_UNUSED
,
74 unsigned int flags ATTRIBUTE_UNUSED
)
76 disassemble_info
*info
= (disassemble_info
*) dis_info
;
78 (*info
->fprintf_func
) (info
->stream
, "$tp");
82 print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
, PTR dis_info
,
83 CGEN_KEYWORD
*table ATTRIBUTE_UNUSED
, long val ATTRIBUTE_UNUSED
,
84 unsigned int flags ATTRIBUTE_UNUSED
)
86 disassemble_info
*info
= (disassemble_info
*) dis_info
;
88 (*info
->fprintf_func
) (info
->stream
, "$sp");
91 /* begin-cop-ip-print-handlers */
92 /* end-cop-ip-print-handlers */
94 /************************************************************\
95 *********************** Experimental *************************
96 \************************************************************/
98 #undef CGEN_PRINT_INSN
99 #define CGEN_PRINT_INSN mep_print_insn
102 mep_print_vliw_insns (CGEN_CPU_DESC cd
, bfd_vma pc
, disassemble_info
*info
,
103 bfd_byte
*buf
, int corelength
, int copro1length
,
104 int copro2length ATTRIBUTE_UNUSED
)
108 /* char insnbuf[CGEN_MAX_INSN_SIZE]; */
109 bfd_byte insnbuf
[64];
111 /* If corelength > 0 then there is a core insn present. It
112 will be at the beginning of the buffer. After printing
113 the core insn, we need to print the + on the next line. */
118 for (i
= 0; i
< corelength
; i
++ )
120 cd
->isas
= & MEP_CORE_ISA
;
122 my_status
= print_insn (cd
, pc
, info
, insnbuf
, corelength
);
123 if (my_status
!= corelength
)
125 (*info
->fprintf_func
) (info
->stream
, UNKNOWN_INSN_MSG
);
126 my_status
= corelength
;
130 /* Print the + to indicate that the following copro insn is */
131 /* part of a vliw group. */
132 if (copro1length
> 0)
133 (*info
->fprintf_func
) (info
->stream
, " + ");
136 /* Now all that is left to be processed is the coprocessor insns
137 In vliw mode, there will always be one. Its positioning will
138 be from byte corelength to byte corelength+copro1length -1.
139 No need to check for existence. Also, the first vliw insn,
140 will, as spec'd, always be at least as long as the core insn
141 so we don't need to flush the buffer. */
142 if (copro1length
> 0)
146 for (i
= corelength
; i
< corelength
+ copro1length
; i
++ )
147 insnbuf
[i
- corelength
] = buf
[i
];
149 switch (copro1length
)
154 cd
->isas
= & MEP_COP16_ISA
;
157 cd
->isas
= & MEP_COP32_ISA
;
160 cd
->isas
= & MEP_COP48_ISA
;
163 cd
->isas
= & MEP_COP64_ISA
;
166 /* Shouldn't be anything but 16,32,48,64. */
170 my_status
= print_insn (cd
, pc
, info
, insnbuf
, copro1length
);
172 if (my_status
!= copro1length
)
174 (*info
->fprintf_func
) (info
->stream
, UNKNOWN_INSN_MSG
);
175 my_status
= copro1length
;
181 /* Now we need to process the second copro insn if it exists. We
182 have no guarantee that the second copro insn will be longer
183 than the first, so we have to flush the buffer if we are have
184 a second copro insn to process. If present, this insn will
185 be in the position from byte corelength+copro1length to byte
186 corelength+copro1length+copro2length-1 (which better equal 8
187 or else we're in big trouble. */
188 if (copro2length
> 0)
192 for (i
= 0; i
< 64 ; i
++)
195 for (i
= corelength
+ copro1length
; i
< 64; i
++)
196 insnbuf
[i
- (corelength
+ copro1length
)] = buf
[i
];
198 switch (copro2length
)
201 cd
->isas
= 1 << ISA_EXT_COP1_16
;
204 cd
->isas
= 1 << ISA_EXT_COP1_32
;
207 cd
->isas
= 1 << ISA_EXT_COP1_48
;
210 cd
->isas
= 1 << ISA_EXT_COP1_64
;
213 /* Shouldn't be anything but 16,32,48,64. */
217 my_status
= print_insn (cd
, pc
, info
, insnbuf
, copro2length
);
219 if (my_status
!= copro2length
)
221 (*info
->fprintf_func
) (info
->stream
, UNKNOWN_INSN_MSG
);
222 my_status
= copro2length
;
229 /* Status should now be the number of bytes that were printed
230 which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */
232 if ((!MEP_VLIW64
&& (status
!= 4)) || (MEP_VLIW64
&& (status
!= 8)))
238 /* The two functions mep_examine_vliw[32,64]_insns are used find out
239 which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
240 with 32 bit copro, etc.) is present. Later on, when internally
241 parallel coprocessors are handled, only these functions should
244 At this time only the following combinations are supported:
247 16 bit core insn (core) and 16 bit coprocessor insn (cop1)
248 32 bit core insn (core)
249 32 bit coprocessor insn (cop1)
250 Note: As of this time, I do not believe we have enough information
251 to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
252 no 16 bit coprocessor insns have been specified.
255 16 bit core insn (core) and 48 bit coprocessor insn (cop1)
256 32 bit core insn (core) and 32 bit coprocessor insn (cop1)
257 64 bit coprocessor insn (cop1)
259 The framework for an internally parallel coprocessor is also
260 present (2nd coprocessor insn is cop2), but at this time it
261 is not used. This only appears to be valid in VLIW64 mode. */
264 mep_examine_vliw32_insns (CGEN_CPU_DESC cd
, bfd_vma pc
, disassemble_info
*info
)
271 bfd_byte buf
[CGEN_MAX_INSN_SIZE
];
273 char indicatorcop32
[2];
275 /* At this time we're not supporting internally parallel coprocessors,
276 so cop2buflength will always be 0. */
279 /* Read in 32 bits. */
280 buflength
= 4; /* VLIW insn spans 4 bytes. */
281 status
= (*info
->read_memory_func
) (pc
, buf
, buflength
, info
);
285 (*info
->memory_error_func
) (status
, pc
, info
);
289 /* Put the big endian representation of the bytes to be examined
290 in the temporary buffers for examination. */
292 if (info
->endian
== BFD_ENDIAN_BIG
)
294 indicator16
[0] = buf
[0];
295 indicatorcop32
[0] = buf
[0];
296 indicatorcop32
[1] = buf
[1];
300 indicator16
[0] = buf
[1];
301 indicatorcop32
[0] = buf
[1];
302 indicatorcop32
[1] = buf
[0];
305 /* If the two high order bits are 00, 01 or 10, we have a 16 bit
306 core insn and a 48 bit copro insn. */
308 if ((indicator16
[0] & 0x80) && (indicator16
[0] & 0x40))
310 if ((indicatorcop32
[0] & 0xf0) == 0xf0 && (indicatorcop32
[1] & 0x07) == 0x07)
312 /* We have a 32 bit copro insn. */
314 /* All 4 4ytes are one copro insn. */
319 /* We have a 32 bit core. */
326 /* We have a 16 bit core insn and a 16 bit copro insn. */
331 /* Now we have the distrubution set. Print them out. */
332 status
= mep_print_vliw_insns (cd
, pc
, info
, buf
, corebuflength
,
333 cop1buflength
, cop2buflength
);
339 mep_examine_vliw64_insns (CGEN_CPU_DESC cd
, bfd_vma pc
, disassemble_info
*info
)
346 bfd_byte buf
[CGEN_MAX_INSN_SIZE
];
350 /* At this time we're not supporting internally parallel
351 coprocessors, so cop2buflength will always be 0. */
354 /* Read in 64 bits. */
355 buflength
= 8; /* VLIW insn spans 8 bytes. */
356 status
= (*info
->read_memory_func
) (pc
, buf
, buflength
, info
);
360 (*info
->memory_error_func
) (status
, pc
, info
);
364 /* We have all 64 bits in the buffer now. We have to figure out
365 what combination of instruction sizes are present. The two
366 high order bits will indicate whether or not we have a 16 bit
367 core insn or not. If not, then we have to look at the 7,8th
368 bytes to tell whether we have 64 bit copro insn or a 32 bit
369 core insn with a 32 bit copro insn. Endianness will make a
372 /* Put the big endian representation of the bytes to be examined
373 in the temporary buffers for examination. */
375 /* indicator16[0] = buf[0]; */
376 if (info
->endian
== BFD_ENDIAN_BIG
)
378 indicator16
[0] = buf
[0];
379 indicator64
[0] = buf
[0];
380 indicator64
[1] = buf
[1];
381 indicator64
[2] = buf
[2];
382 indicator64
[3] = buf
[3];
386 indicator16
[0] = buf
[1];
387 indicator64
[0] = buf
[1];
388 indicator64
[1] = buf
[0];
389 indicator64
[2] = buf
[3];
390 indicator64
[3] = buf
[2];
393 /* If the two high order bits are 00, 01 or 10, we have a 16 bit
394 core insn and a 48 bit copro insn. */
396 if ((indicator16
[0] & 0x80) && (indicator16
[0] & 0x40))
398 if ((indicator64
[0] & 0xf0) == 0xf0 && (indicator64
[1] & 0x07) == 0x07
399 && ((indicator64
[2] & 0xfe) != 0xf0 || (indicator64
[3] & 0xf4) != 0))
401 /* We have a 64 bit copro insn. */
403 /* All 8 bytes are one copro insn. */
408 /* We have a 32 bit core insn and a 32 bit copro insn. */
415 /* We have a 16 bit core insn and a 48 bit copro insn. */
420 /* Now we have the distrubution set. Print them out. */
421 status
= mep_print_vliw_insns (cd
, pc
, info
, buf
, corebuflength
,
422 cop1buflength
, cop2buflength
);
428 mep_print_insn (CGEN_CPU_DESC cd
, bfd_vma pc
, disassemble_info
*info
)
432 /* Extract and adapt to configuration number, if available. */
433 if (info
->section
&& info
->section
->owner
)
435 bfd
*abfd
= info
->section
->owner
;
436 mep_config_index
= abfd
->tdata
.elf_obj_data
->elf_header
->e_flags
& EF_MEP_INDEX_MASK
;
437 /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
440 /* Picking the right ISA bitmask for the current context is tricky. */
443 if (info
->section
->flags
& SEC_MEP_VLIW
)
445 /* Are we in 32 or 64 bit vliw mode? */
447 status
= mep_examine_vliw64_insns (cd
, pc
, info
);
449 status
= mep_examine_vliw32_insns (cd
, pc
, info
);
450 /* Both the above branches set their own isa bitmasks. */
454 cd
->isas
= & MEP_CORE_ISA
;
455 status
= default_print_insn (cd
, pc
, info
);
458 else /* sid or gdb */
460 status
= default_print_insn (cd
, pc
, info
);
469 void mep_cgen_print_operand
470 (CGEN_CPU_DESC
, int, PTR
, CGEN_FIELDS
*, void const *, bfd_vma
, int);
472 /* Main entry point for printing operands.
473 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
474 of dis-asm.h on cgen.h.
476 This function is basically just a big switch statement. Earlier versions
477 used tables to look up the function to use, but
478 - if the table contains both assembler and disassembler functions then
479 the disassembler contains much of the assembler and vice-versa,
480 - there's a lot of inlining possibilities as things grow,
481 - using a switch statement avoids the function call overhead.
483 This function could be moved into `print_insn_normal', but keeping it
484 separate makes clear the interface between `print_insn_normal' and each of
488 mep_cgen_print_operand (CGEN_CPU_DESC cd
,
492 void const *attrs ATTRIBUTE_UNUSED
,
496 disassemble_info
*info
= (disassemble_info
*) xinfo
;
500 case MEP_OPERAND_ADDR24A4
:
501 print_normal (cd
, info
, fields
->f_24u8a4n
, 0|(1<<CGEN_OPERAND_VIRTUAL
), pc
, length
);
503 case MEP_OPERAND_C5RMUIMM20
:
504 print_normal (cd
, info
, fields
->f_c5_rmuimm20
, 0|(1<<CGEN_OPERAND_VIRTUAL
), pc
, length
);
506 case MEP_OPERAND_C5RNMUIMM24
:
507 print_normal (cd
, info
, fields
->f_c5_rnmuimm24
, 0|(1<<CGEN_OPERAND_VIRTUAL
), pc
, length
);
509 case MEP_OPERAND_CALLNUM
:
510 print_normal (cd
, info
, fields
->f_callnum
, 0|(1<<CGEN_OPERAND_VIRTUAL
), pc
, length
);
512 case MEP_OPERAND_CCCC
:
513 print_normal (cd
, info
, fields
->f_rm
, 0, pc
, length
);
515 case MEP_OPERAND_CCRN
:
516 print_keyword (cd
, info
, & mep_cgen_opval_h_ccr
, fields
->f_ccrn
, 0|(1<<CGEN_OPERAND_VIRTUAL
));
518 case MEP_OPERAND_CDISP10
:
519 print_normal (cd
, info
, fields
->f_cdisp10
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
521 case MEP_OPERAND_CDISP10A2
:
522 print_normal (cd
, info
, fields
->f_cdisp10
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
524 case MEP_OPERAND_CDISP10A4
:
525 print_normal (cd
, info
, fields
->f_cdisp10
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
527 case MEP_OPERAND_CDISP10A8
:
528 print_normal (cd
, info
, fields
->f_cdisp10
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
530 case MEP_OPERAND_CDISP12
:
531 print_normal (cd
, info
, fields
->f_12s20
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
533 case MEP_OPERAND_CIMM4
:
534 print_normal (cd
, info
, fields
->f_rn
, 0, pc
, length
);
536 case MEP_OPERAND_CIMM5
:
537 print_normal (cd
, info
, fields
->f_5u24
, 0, pc
, length
);
539 case MEP_OPERAND_CODE16
:
540 print_normal (cd
, info
, fields
->f_16u16
, 0, pc
, length
);
542 case MEP_OPERAND_CODE24
:
543 print_normal (cd
, info
, fields
->f_24u4n
, 0|(1<<CGEN_OPERAND_VIRTUAL
), pc
, length
);
545 case MEP_OPERAND_CP_FLAG
:
546 print_keyword (cd
, info
, & mep_cgen_opval_h_ccr
, 0, 0);
548 case MEP_OPERAND_CRN
:
549 print_keyword (cd
, info
, & mep_cgen_opval_h_cr
, fields
->f_crn
, 0);
551 case MEP_OPERAND_CRN64
:
552 print_keyword (cd
, info
, & mep_cgen_opval_h_cr64
, fields
->f_crn
, 0);
554 case MEP_OPERAND_CRNX
:
555 print_keyword (cd
, info
, & mep_cgen_opval_h_cr
, fields
->f_crnx
, 0|(1<<CGEN_OPERAND_VIRTUAL
));
557 case MEP_OPERAND_CRNX64
:
558 print_keyword (cd
, info
, & mep_cgen_opval_h_cr64
, fields
->f_crnx
, 0|(1<<CGEN_OPERAND_VIRTUAL
));
560 case MEP_OPERAND_CSRN
:
561 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, fields
->f_csrn
, 0|(1<<CGEN_OPERAND_VIRTUAL
));
563 case MEP_OPERAND_CSRN_IDX
:
564 print_normal (cd
, info
, fields
->f_csrn
, 0|(1<<CGEN_OPERAND_VIRTUAL
), pc
, length
);
566 case MEP_OPERAND_DBG
:
567 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
569 case MEP_OPERAND_DEPC
:
570 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
572 case MEP_OPERAND_EPC
:
573 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
575 case MEP_OPERAND_EXC
:
576 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
578 case MEP_OPERAND_HI
:
579 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
581 case MEP_OPERAND_LO
:
582 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
584 case MEP_OPERAND_LP
:
585 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
587 case MEP_OPERAND_MB0
:
588 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
590 case MEP_OPERAND_MB1
:
591 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
593 case MEP_OPERAND_ME0
:
594 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
596 case MEP_OPERAND_ME1
:
597 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
599 case MEP_OPERAND_NPC
:
600 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
602 case MEP_OPERAND_OPT
:
603 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
605 case MEP_OPERAND_PCABS24A2
:
606 print_address (cd
, info
, fields
->f_24u5a2n
, 0|(1<<CGEN_OPERAND_ABS_ADDR
)|(1<<CGEN_OPERAND_VIRTUAL
), pc
, length
);
608 case MEP_OPERAND_PCREL12A2
:
609 print_address (cd
, info
, fields
->f_12s4a2
, 0|(1<<CGEN_OPERAND_SIGNED
)|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_PCREL_ADDR
), pc
, length
);
611 case MEP_OPERAND_PCREL17A2
:
612 print_address (cd
, info
, fields
->f_17s16a2
, 0|(1<<CGEN_OPERAND_SIGNED
)|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_PCREL_ADDR
), pc
, length
);
614 case MEP_OPERAND_PCREL24A2
:
615 print_address (cd
, info
, fields
->f_24s5a2n
, 0|(1<<CGEN_OPERAND_SIGNED
)|(1<<CGEN_OPERAND_PCREL_ADDR
)|(1<<CGEN_OPERAND_VIRTUAL
), pc
, length
);
617 case MEP_OPERAND_PCREL8A2
:
618 print_address (cd
, info
, fields
->f_8s8a2
, 0|(1<<CGEN_OPERAND_SIGNED
)|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_PCREL_ADDR
), pc
, length
);
620 case MEP_OPERAND_PSW
:
621 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
623 case MEP_OPERAND_R0
:
624 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, 0, 0);
626 case MEP_OPERAND_R1
:
627 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, 0, 0);
629 case MEP_OPERAND_RL
:
630 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rl
, 0);
632 case MEP_OPERAND_RL5
:
633 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rl5
, 0);
635 case MEP_OPERAND_RM
:
636 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rm
, 0);
638 case MEP_OPERAND_RMA
:
639 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rm
, 0);
641 case MEP_OPERAND_RN
:
642 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn
, 0);
644 case MEP_OPERAND_RN3
:
645 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn3
, 0);
647 case MEP_OPERAND_RN3C
:
648 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn3
, 0);
650 case MEP_OPERAND_RN3L
:
651 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn3
, 0);
653 case MEP_OPERAND_RN3S
:
654 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn3
, 0);
656 case MEP_OPERAND_RN3UC
:
657 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn3
, 0);
659 case MEP_OPERAND_RN3UL
:
660 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn3
, 0);
662 case MEP_OPERAND_RN3US
:
663 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn3
, 0);
665 case MEP_OPERAND_RNC
:
666 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn
, 0);
668 case MEP_OPERAND_RNL
:
669 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn
, 0);
671 case MEP_OPERAND_RNS
:
672 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn
, 0);
674 case MEP_OPERAND_RNUC
:
675 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn
, 0);
677 case MEP_OPERAND_RNUL
:
678 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn
, 0);
680 case MEP_OPERAND_RNUS
:
681 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, fields
->f_rn
, 0);
683 case MEP_OPERAND_SAR
:
684 print_keyword (cd
, info
, & mep_cgen_opval_h_csr
, 0, 0);
686 case MEP_OPERAND_SDISP16
:
687 print_normal (cd
, info
, fields
->f_16s16
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
689 case MEP_OPERAND_SIMM16
:
690 print_normal (cd
, info
, fields
->f_16s16
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
692 case MEP_OPERAND_SIMM6
:
693 print_normal (cd
, info
, fields
->f_6s8
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
695 case MEP_OPERAND_SIMM8
:
696 print_normal (cd
, info
, fields
->f_8s8
, 0|(1<<CGEN_OPERAND_SIGNED
)|(1<<CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW
), pc
, length
);
698 case MEP_OPERAND_SP
:
699 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, 0, 0);
701 case MEP_OPERAND_SPR
:
702 print_spreg (cd
, info
, & mep_cgen_opval_h_gpr
, 0, 0);
704 case MEP_OPERAND_TP
:
705 print_keyword (cd
, info
, & mep_cgen_opval_h_gpr
, 0, 0);
707 case MEP_OPERAND_TPR
:
708 print_tpreg (cd
, info
, & mep_cgen_opval_h_gpr
, 0, 0);
710 case MEP_OPERAND_UDISP2
:
711 print_normal (cd
, info
, fields
->f_2u6
, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
713 case MEP_OPERAND_UDISP7
:
714 print_normal (cd
, info
, fields
->f_7u9
, 0, pc
, length
);
716 case MEP_OPERAND_UDISP7A2
:
717 print_normal (cd
, info
, fields
->f_7u9a2
, 0, pc
, length
);
719 case MEP_OPERAND_UDISP7A4
:
720 print_normal (cd
, info
, fields
->f_7u9a4
, 0, pc
, length
);
722 case MEP_OPERAND_UIMM16
:
723 print_normal (cd
, info
, fields
->f_16u16
, 0, pc
, length
);
725 case MEP_OPERAND_UIMM2
:
726 print_normal (cd
, info
, fields
->f_2u10
, 0, pc
, length
);
728 case MEP_OPERAND_UIMM24
:
729 print_normal (cd
, info
, fields
->f_24u8n
, 0|(1<<CGEN_OPERAND_VIRTUAL
), pc
, length
);
731 case MEP_OPERAND_UIMM3
:
732 print_normal (cd
, info
, fields
->f_3u5
, 0, pc
, length
);
734 case MEP_OPERAND_UIMM4
:
735 print_normal (cd
, info
, fields
->f_4u8
, 0, pc
, length
);
737 case MEP_OPERAND_UIMM5
:
738 print_normal (cd
, info
, fields
->f_5u8
, 0, pc
, length
);
740 case MEP_OPERAND_UIMM7A4
:
741 print_normal (cd
, info
, fields
->f_7u9a4
, 0, pc
, length
);
743 case MEP_OPERAND_ZERO
:
744 print_normal (cd
, info
, 0, 0|(1<<CGEN_OPERAND_SIGNED
), pc
, length
);
748 /* xgettext:c-format */
749 fprintf (stderr
, _("Unrecognized field %d while printing insn.\n"),
755 cgen_print_fn
* const mep_cgen_print_handlers
[] =
762 mep_cgen_init_dis (CGEN_CPU_DESC cd
)
764 mep_cgen_init_opcode_table (cd
);
765 mep_cgen_init_ibld_table (cd
);
766 cd
->print_handlers
= & mep_cgen_print_handlers
[0];
767 cd
->print_operand
= mep_cgen_print_operand
;
771 /* Default print handler. */
774 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
,
778 bfd_vma pc ATTRIBUTE_UNUSED
,
779 int length ATTRIBUTE_UNUSED
)
781 disassemble_info
*info
= (disassemble_info
*) dis_info
;
783 #ifdef CGEN_PRINT_NORMAL
784 CGEN_PRINT_NORMAL (cd
, info
, value
, attrs
, pc
, length
);
787 /* Print the operand as directed by the attributes. */
788 if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_SEM_ONLY
))
789 ; /* nothing to do */
790 else if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_SIGNED
))
791 (*info
->fprintf_func
) (info
->stream
, "%ld", value
);
793 (*info
->fprintf_func
) (info
->stream
, "0x%lx", value
);
796 /* Default address handler. */
799 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
,
803 bfd_vma pc ATTRIBUTE_UNUSED
,
804 int length ATTRIBUTE_UNUSED
)
806 disassemble_info
*info
= (disassemble_info
*) dis_info
;
808 #ifdef CGEN_PRINT_ADDRESS
809 CGEN_PRINT_ADDRESS (cd
, info
, value
, attrs
, pc
, length
);
812 /* Print the operand as directed by the attributes. */
813 if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_SEM_ONLY
))
814 ; /* Nothing to do. */
815 else if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_PCREL_ADDR
))
816 (*info
->print_address_func
) (value
, info
);
817 else if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_ABS_ADDR
))
818 (*info
->print_address_func
) (value
, info
);
819 else if (CGEN_BOOL_ATTR (attrs
, CGEN_OPERAND_SIGNED
))
820 (*info
->fprintf_func
) (info
->stream
, "%ld", (long) value
);
822 (*info
->fprintf_func
) (info
->stream
, "0x%lx", (long) value
);
825 /* Keyword print handler. */
828 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
,
830 CGEN_KEYWORD
*keyword_table
,
832 unsigned int attrs ATTRIBUTE_UNUSED
)
834 disassemble_info
*info
= (disassemble_info
*) dis_info
;
835 const CGEN_KEYWORD_ENTRY
*ke
;
837 ke
= cgen_keyword_lookup_value (keyword_table
, value
);
839 (*info
->fprintf_func
) (info
->stream
, "%s", ke
->name
);
841 (*info
->fprintf_func
) (info
->stream
, "???");
844 /* Default insn printer.
846 DIS_INFO is defined as `void *' so the disassembler needn't know anything
847 about disassemble_info. */
850 print_insn_normal (CGEN_CPU_DESC cd
,
852 const CGEN_INSN
*insn
,
857 const CGEN_SYNTAX
*syntax
= CGEN_INSN_SYNTAX (insn
);
858 disassemble_info
*info
= (disassemble_info
*) dis_info
;
859 const CGEN_SYNTAX_CHAR_TYPE
*syn
;
861 CGEN_INIT_PRINT (cd
);
863 for (syn
= CGEN_SYNTAX_STRING (syntax
); *syn
; ++syn
)
865 if (CGEN_SYNTAX_MNEMONIC_P (*syn
))
867 (*info
->fprintf_func
) (info
->stream
, "%s", CGEN_INSN_MNEMONIC (insn
));
870 if (CGEN_SYNTAX_CHAR_P (*syn
))
872 (*info
->fprintf_func
) (info
->stream
, "%c", CGEN_SYNTAX_CHAR (*syn
));
876 /* We have an operand. */
877 mep_cgen_print_operand (cd
, CGEN_SYNTAX_FIELD (*syn
), info
,
878 fields
, CGEN_INSN_ATTRS (insn
), pc
, length
);
882 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
884 Returns 0 if all is well, non-zero otherwise. */
887 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
,
889 disassemble_info
*info
,
892 CGEN_EXTRACT_INFO
*ex_info
,
893 unsigned long *insn_value
)
895 int status
= (*info
->read_memory_func
) (pc
, buf
, buflen
, info
);
899 (*info
->memory_error_func
) (status
, pc
, info
);
903 ex_info
->dis_info
= info
;
904 ex_info
->valid
= (1 << buflen
) - 1;
905 ex_info
->insn_bytes
= buf
;
907 *insn_value
= bfd_get_bits (buf
, buflen
* 8, info
->endian
== BFD_ENDIAN_BIG
);
911 /* Utility to print an insn.
912 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
913 The result is the size of the insn in bytes or zero for an unknown insn
914 or -1 if an error occurs fetching data (memory_error_func will have
918 print_insn (CGEN_CPU_DESC cd
,
920 disassemble_info
*info
,
924 CGEN_INSN_INT insn_value
;
925 const CGEN_INSN_LIST
*insn_list
;
926 CGEN_EXTRACT_INFO ex_info
;
929 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
930 basesize
= cd
->base_insn_bitsize
< buflen
* 8 ?
931 cd
->base_insn_bitsize
: buflen
* 8;
932 insn_value
= cgen_get_insn_value (cd
, buf
, basesize
);
935 /* Fill in ex_info fields like read_insn would. Don't actually call
936 read_insn, since the incoming buffer is already read (and possibly
937 modified a la m32r). */
938 ex_info
.valid
= (1 << buflen
) - 1;
939 ex_info
.dis_info
= info
;
940 ex_info
.insn_bytes
= buf
;
942 /* The instructions are stored in hash lists.
943 Pick the first one and keep trying until we find the right one. */
945 insn_list
= CGEN_DIS_LOOKUP_INSN (cd
, (char *) buf
, insn_value
);
946 while (insn_list
!= NULL
)
948 const CGEN_INSN
*insn
= insn_list
->insn
;
951 unsigned long insn_value_cropped
;
953 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
954 /* Not needed as insn shouldn't be in hash lists if not supported. */
955 /* Supported by this cpu? */
956 if (! mep_cgen_insn_supported (cd
, insn
))
958 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
963 /* Basic bit mask must be correct. */
964 /* ??? May wish to allow target to defer this check until the extract
967 /* Base size may exceed this instruction's size. Extract the
968 relevant part from the buffer. */
969 if ((unsigned) (CGEN_INSN_BITSIZE (insn
) / 8) < buflen
&&
970 (unsigned) (CGEN_INSN_BITSIZE (insn
) / 8) <= sizeof (unsigned long))
971 insn_value_cropped
= bfd_get_bits (buf
, CGEN_INSN_BITSIZE (insn
),
972 info
->endian
== BFD_ENDIAN_BIG
);
974 insn_value_cropped
= insn_value
;
976 if ((insn_value_cropped
& CGEN_INSN_BASE_MASK (insn
))
977 == CGEN_INSN_BASE_VALUE (insn
))
979 /* Printing is handled in two passes. The first pass parses the
980 machine insn and extracts the fields. The second pass prints
983 /* Make sure the entire insn is loaded into insn_value, if it
985 if (((unsigned) CGEN_INSN_BITSIZE (insn
) > cd
->base_insn_bitsize
) &&
986 (unsigned) (CGEN_INSN_BITSIZE (insn
) / 8) <= sizeof (unsigned long))
988 unsigned long full_insn_value
;
989 int rc
= read_insn (cd
, pc
, info
, buf
,
990 CGEN_INSN_BITSIZE (insn
) / 8,
991 & ex_info
, & full_insn_value
);
994 length
= CGEN_EXTRACT_FN (cd
, insn
)
995 (cd
, insn
, &ex_info
, full_insn_value
, &fields
, pc
);
998 length
= CGEN_EXTRACT_FN (cd
, insn
)
999 (cd
, insn
, &ex_info
, insn_value_cropped
, &fields
, pc
);
1001 /* Length < 0 -> error. */
1006 CGEN_PRINT_FN (cd
, insn
) (cd
, info
, insn
, &fields
, pc
, length
);
1007 /* Length is in bits, result is in bytes. */
1012 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
1018 /* Default value for CGEN_PRINT_INSN.
1019 The result is the size of the insn in bytes or zero for an unknown insn
1020 or -1 if an error occured fetching bytes. */
1022 #ifndef CGEN_PRINT_INSN
1023 #define CGEN_PRINT_INSN default_print_insn
1027 default_print_insn (CGEN_CPU_DESC cd
, bfd_vma pc
, disassemble_info
*info
)
1029 bfd_byte buf
[CGEN_MAX_INSN_SIZE
];
1033 /* Attempt to read the base part of the insn. */
1034 buflen
= cd
->base_insn_bitsize
/ 8;
1035 status
= (*info
->read_memory_func
) (pc
, buf
, buflen
, info
);
1037 /* Try again with the minimum part, if min < base. */
1038 if (status
!= 0 && (cd
->min_insn_bitsize
< cd
->base_insn_bitsize
))
1040 buflen
= cd
->min_insn_bitsize
/ 8;
1041 status
= (*info
->read_memory_func
) (pc
, buf
, buflen
, info
);
1046 (*info
->memory_error_func
) (status
, pc
, info
);
1050 return print_insn (cd
, pc
, info
, buf
, buflen
);
1053 /* Main entry point.
1054 Print one instruction from PC on INFO->STREAM.
1055 Return the size of the instruction (in bytes). */
1057 typedef struct cpu_desc_list
1059 struct cpu_desc_list
*next
;
1067 print_insn_mep (bfd_vma pc
, disassemble_info
*info
)
1069 static cpu_desc_list
*cd_list
= 0;
1070 cpu_desc_list
*cl
= 0;
1071 static CGEN_CPU_DESC cd
= 0;
1072 static CGEN_BITSET
*prev_isa
;
1073 static int prev_mach
;
1074 static int prev_endian
;
1078 int endian
= (info
->endian
== BFD_ENDIAN_BIG
1080 : CGEN_ENDIAN_LITTLE
);
1081 enum bfd_architecture arch
;
1083 /* ??? gdb will set mach but leave the architecture as "unknown" */
1084 #ifndef CGEN_BFD_ARCH
1085 #define CGEN_BFD_ARCH bfd_arch_mep
1088 if (arch
== bfd_arch_unknown
)
1089 arch
= CGEN_BFD_ARCH
;
1091 /* There's no standard way to compute the machine or isa number
1092 so we leave it to the target. */
1093 #ifdef CGEN_COMPUTE_MACH
1094 mach
= CGEN_COMPUTE_MACH (info
);
1099 #ifdef CGEN_COMPUTE_ISA
1101 static CGEN_BITSET
*permanent_isa
;
1104 permanent_isa
= cgen_bitset_create (MAX_ISAS
);
1105 isa
= permanent_isa
;
1106 cgen_bitset_clear (isa
);
1107 cgen_bitset_add (isa
, CGEN_COMPUTE_ISA (info
));
1110 isa
= info
->insn_sets
;
1113 /* If we've switched cpu's, try to find a handle we've used before */
1115 && (cgen_bitset_compare (isa
, prev_isa
) != 0
1116 || mach
!= prev_mach
1117 || endian
!= prev_endian
))
1120 for (cl
= cd_list
; cl
; cl
= cl
->next
)
1122 if (cgen_bitset_compare (cl
->isa
, isa
) == 0 &&
1124 cl
->endian
== endian
)
1127 prev_isa
= cd
->isas
;
1133 /* If we haven't initialized yet, initialize the opcode table. */
1136 const bfd_arch_info_type
*arch_type
= bfd_lookup_arch (arch
, mach
);
1137 const char *mach_name
;
1141 mach_name
= arch_type
->printable_name
;
1143 prev_isa
= cgen_bitset_copy (isa
);
1145 prev_endian
= endian
;
1146 cd
= mep_cgen_cpu_open (CGEN_CPU_OPEN_ISAS
, prev_isa
,
1147 CGEN_CPU_OPEN_BFDMACH
, mach_name
,
1148 CGEN_CPU_OPEN_ENDIAN
, prev_endian
,
1153 /* Save this away for future reference. */
1154 cl
= xmalloc (sizeof (struct cpu_desc_list
));
1158 cl
->endian
= endian
;
1162 mep_cgen_init_dis (cd
);
1165 /* We try to have as much common code as possible.
1166 But at this point some targets need to take over. */
1167 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
1168 but if not possible try to move this hook elsewhere rather than
1170 length
= CGEN_PRINT_INSN (cd
, pc
, info
);
1176 (*info
->fprintf_func
) (info
->stream
, UNKNOWN_INSN_MSG
);
1177 return cd
->default_insn_bitsize
/ 8;