1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
153 /* x86 arch names, types and features */
156 const char *name
; /* arch name */
157 enum processor_type type
; /* arch type */
158 i386_cpu_flags flags
; /* cpu feature flags */
162 static void set_code_flag (int);
163 static void set_16bit_gcc_code_flag (int);
164 static void set_intel_syntax (int);
165 static void set_intel_mnemonic (int);
166 static void set_allow_index_reg (int);
167 static void set_sse_check (int);
168 static void set_cpu_arch (int);
170 static void pe_directive_secrel (int);
172 static void signed_cons (int);
173 static char *output_invalid (int c
);
174 static int i386_att_operand (char *);
175 static int i386_intel_operand (char *, int);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static void optimize_imm (void);
182 static void optimize_disp (void);
183 static const template *match_template (void);
184 static int check_string (void);
185 static int process_suffix (void);
186 static int check_byte_reg (void);
187 static int check_long_reg (void);
188 static int check_qword_reg (void);
189 static int check_word_reg (void);
190 static int finalize_imm (void);
191 static void process_drex (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
204 static const char *default_arch
= DEFAULT_ARCH
;
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes
[3];
212 /* Destination or source register specifier. */
213 const reg_entry
*register_specifier
;
216 /* 'md_assemble ()' gathers together information and puts it into a
223 const reg_entry
*regs
;
228 /* TM holds the template for the insn were currently assembling. */
231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
235 /* OPERANDS gives the number of given operands. */
236 unsigned int operands
;
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
241 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
243 /* TYPES [i] is the type (see above #defines) which tells us how to
244 use OP[i] for the corresponding operand. */
245 i386_operand_type types
[MAX_OPERANDS
];
247 /* Displacement expression, immediate expression, or register for each
249 union i386_op op
[MAX_OPERANDS
];
251 /* Flags for operands. */
252 unsigned int flags
[MAX_OPERANDS
];
253 #define Operand_PCrel 1
255 /* Relocation type for operand */
256 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry
*base_reg
;
261 const reg_entry
*index_reg
;
262 unsigned int log2_scale_factor
;
264 /* SEG gives the seg_entries of this insn. They are zero unless
265 explicit segment overrides are given. */
266 const seg_entry
*seg
[2];
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes
;
271 unsigned char prefix
[MAX_PREFIXES
];
273 /* RM and SIB are the modrm byte and the sib byte where the
274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
283 /* Swap operand in encoding. */
284 unsigned int swap_operand
: 1;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static int use_rela_relocations
= 0;
394 /* The names used to print error messages. */
395 static const char *flag_code_names
[] =
402 /* 1 for intel syntax,
404 static int intel_syntax
= 0;
406 /* 1 for intel mnemonic,
407 0 if att mnemonic. */
408 static int intel_mnemonic
= !SYSV386_COMPAT
;
410 /* 1 if support old (<= 2.8.1) versions of gcc. */
411 static int old_gcc
= OLDGCC_COMPAT
;
413 /* 1 if pseudo registers are permitted. */
414 static int allow_pseudo_reg
= 0;
416 /* 1 if register prefix % not required. */
417 static int allow_naked_reg
= 0;
419 /* 1 if pseudo index register, eiz/riz, is allowed . */
420 static int allow_index_reg
= 0;
430 /* Register prefix used for error message. */
431 static const char *register_prefix
= "%";
433 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436 static char stackop_size
= '\0';
438 /* Non-zero to optimize code alignment. */
439 int optimize_align_code
= 1;
441 /* Non-zero to quieten some warnings. */
442 static int quiet_warnings
= 0;
445 static const char *cpu_arch_name
= NULL
;
446 static char *cpu_sub_arch_name
= NULL
;
448 /* CPU feature flags. */
449 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
451 /* If we have selected a cpu we are generating instructions for. */
452 static int cpu_arch_tune_set
= 0;
454 /* Cpu we are generating instructions for. */
455 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
457 /* CPU feature flags of cpu we are generating instructions for. */
458 static i386_cpu_flags cpu_arch_tune_flags
;
460 /* CPU instruction set architecture used. */
461 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
463 /* CPU feature flags of instruction set architecture used. */
464 i386_cpu_flags cpu_arch_isa_flags
;
466 /* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468 static unsigned int no_cond_jump_promotion
= 0;
470 /* Encode SSE instructions with VEX prefix. */
471 static unsigned int sse2avx
;
473 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
474 static symbolS
*GOT_symbol
;
476 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
477 unsigned int x86_dwarf2_return_column
;
479 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480 int x86_cie_data_alignment
;
482 /* Interface to relax_segment.
483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
488 #define UNCOND_JUMP 0
490 #define COND_JUMP86 2
495 #define SMALL16 (SMALL | CODE16)
497 #define BIG16 (BIG | CODE16)
501 #define INLINE __inline__
507 #define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509 #define TYPE_FROM_RELAX_STATE(s) \
511 #define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
514 /* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
522 const relax_typeS md_relax_table
[] =
525 1) most positive reach of this state,
526 2) most negative reach of this state,
527 3) how many bytes this mode will have in the variable part of the frag
528 4) which index into the table to try if we can't fit into this one. */
530 /* UNCOND_JUMP states. */
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
546 /* word conditionals add 3 bytes to frag:
547 1 extra opcode byte, 2 displacement bytes. */
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
561 static const arch_entry cpu_arch
[] =
563 { "generic32", PROCESSOR_GENERIC32
,
564 CPU_GENERIC32_FLAGS
},
565 { "generic64", PROCESSOR_GENERIC64
,
566 CPU_GENERIC64_FLAGS
},
567 { "i8086", PROCESSOR_UNKNOWN
,
569 { "i186", PROCESSOR_UNKNOWN
,
571 { "i286", PROCESSOR_UNKNOWN
,
573 { "i386", PROCESSOR_I386
,
575 { "i486", PROCESSOR_I486
,
577 { "i586", PROCESSOR_PENTIUM
,
579 { "i686", PROCESSOR_PENTIUMPRO
,
581 { "pentium", PROCESSOR_PENTIUM
,
583 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
585 { "pentiumii", PROCESSOR_PENTIUMPRO
,
587 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
589 { "pentium4", PROCESSOR_PENTIUM4
,
591 { "prescott", PROCESSOR_NOCONA
,
593 { "nocona", PROCESSOR_NOCONA
,
595 { "yonah", PROCESSOR_CORE
,
597 { "core", PROCESSOR_CORE
,
599 { "merom", PROCESSOR_CORE2
,
601 { "core2", PROCESSOR_CORE2
,
603 { "corei7", PROCESSOR_COREI7
,
605 { "k6", PROCESSOR_K6
,
607 { "k6_2", PROCESSOR_K6
,
609 { "athlon", PROCESSOR_ATHLON
,
611 { "sledgehammer", PROCESSOR_K8
,
613 { "opteron", PROCESSOR_K8
,
615 { "k8", PROCESSOR_K8
,
617 { "amdfam10", PROCESSOR_AMDFAM10
,
618 CPU_AMDFAM10_FLAGS
},
619 { ".mmx", PROCESSOR_UNKNOWN
,
621 { ".sse", PROCESSOR_UNKNOWN
,
623 { ".sse2", PROCESSOR_UNKNOWN
,
625 { ".sse3", PROCESSOR_UNKNOWN
,
627 { ".ssse3", PROCESSOR_UNKNOWN
,
629 { ".sse4.1", PROCESSOR_UNKNOWN
,
631 { ".sse4.2", PROCESSOR_UNKNOWN
,
633 { ".sse4", PROCESSOR_UNKNOWN
,
635 { ".avx", PROCESSOR_UNKNOWN
,
637 { ".vmx", PROCESSOR_UNKNOWN
,
639 { ".smx", PROCESSOR_UNKNOWN
,
641 { ".xsave", PROCESSOR_UNKNOWN
,
643 { ".aes", PROCESSOR_UNKNOWN
,
645 { ".pclmul", PROCESSOR_UNKNOWN
,
647 { ".clmul", PROCESSOR_UNKNOWN
,
649 { ".fma", PROCESSOR_UNKNOWN
,
651 { ".movbe", PROCESSOR_UNKNOWN
,
653 { ".ept", PROCESSOR_UNKNOWN
,
655 { ".clflush", PROCESSOR_UNKNOWN
,
657 { ".syscall", PROCESSOR_UNKNOWN
,
659 { ".rdtscp", PROCESSOR_UNKNOWN
,
661 { ".3dnow", PROCESSOR_UNKNOWN
,
663 { ".3dnowa", PROCESSOR_UNKNOWN
,
665 { ".padlock", PROCESSOR_UNKNOWN
,
667 { ".pacifica", PROCESSOR_UNKNOWN
,
669 { ".svme", PROCESSOR_UNKNOWN
,
671 { ".sse4a", PROCESSOR_UNKNOWN
,
673 { ".abm", PROCESSOR_UNKNOWN
,
675 { ".sse5", PROCESSOR_UNKNOWN
,
680 /* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
684 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
691 && *input_line_pointer
== ',')
693 align
= parse_align (needs_align
- 1);
695 if (align
== (addressT
) -1)
710 bss_alloc (symbolP
, size
, align
);
715 pe_lcomm (int needs_align
)
717 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
721 const pseudo_typeS md_pseudo_table
[] =
723 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes
, 0},
726 {"align", s_align_ptwo
, 0},
728 {"arch", set_cpu_arch
, 0},
732 {"lcomm", pe_lcomm
, 1},
734 {"ffloat", float_cons
, 'f'},
735 {"dfloat", float_cons
, 'd'},
736 {"tfloat", float_cons
, 'x'},
738 {"slong", signed_cons
, 4},
739 {"noopt", s_ignore
, 0},
740 {"optim", s_ignore
, 0},
741 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
742 {"code16", set_code_flag
, CODE_16BIT
},
743 {"code32", set_code_flag
, CODE_32BIT
},
744 {"code64", set_code_flag
, CODE_64BIT
},
745 {"intel_syntax", set_intel_syntax
, 1},
746 {"att_syntax", set_intel_syntax
, 0},
747 {"intel_mnemonic", set_intel_mnemonic
, 1},
748 {"att_mnemonic", set_intel_mnemonic
, 0},
749 {"allow_index_reg", set_allow_index_reg
, 1},
750 {"disallow_index_reg", set_allow_index_reg
, 0},
751 {"sse_check", set_sse_check
, 0},
752 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common
, 0},
755 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
756 {"loc", dwarf2_directive_loc
, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
760 {"secrel32", pe_directive_secrel
, 0},
765 /* For interface with expression (). */
766 extern char *input_line_pointer
;
768 /* Hash table for instruction mnemonic lookup. */
769 static struct hash_control
*op_hash
;
771 /* Hash table for register lookup. */
772 static struct hash_control
*reg_hash
;
775 i386_align_code (fragS
*fragP
, int count
)
777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
780 static const char f32_1
[] =
782 static const char f32_2
[] =
783 {0x66,0x90}; /* xchg %ax,%ax */
784 static const char f32_3
[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4
[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5
[] =
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6
[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7
[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8
[] =
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9
[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10
[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11
[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12
[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13
[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14
[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
816 static const char f16_3
[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
818 static const char f16_4
[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5
[] =
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6
[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7
[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8
[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
832 static const char jump_31
[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
837 static const char *const f32_patt
[] = {
838 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
839 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
841 static const char *const f16_patt
[] = {
842 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
845 static const char alt_3
[] =
847 /* nopl 0(%[re]ax) */
848 static const char alt_4
[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5
[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6
[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7
[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8
[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9
[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10
[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11
[] =
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13
[] =
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14
[] =
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15
[] =
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11
[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12
[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
925 static const char alt_short_13
[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
930 static const char alt_short_14
[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15
[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt
[] = {
939 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
940 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
941 alt_short_14
, alt_short_15
943 static const char *const alt_long_patt
[] = {
944 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
945 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
946 alt_long_14
, alt_long_15
949 /* Only align for at least a positive non-zero boundary. */
950 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
962 PROCESSOR_AMDFAM10, alt_short_patt will be used.
964 When -mtune= isn't used, alt_long_patt will be used if
965 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
968 When -march= or .arch is used, we can't use anything beyond
969 cpu_arch_isa_flags. */
971 if (flag_code
== CODE_16BIT
)
975 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
977 /* Adjust jump offset. */
978 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
981 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
982 f16_patt
[count
- 1], count
);
986 const char *const *patt
= NULL
;
988 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
990 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
991 switch (cpu_arch_tune
)
993 case PROCESSOR_UNKNOWN
:
994 /* We use cpu_arch_isa_flags to check if we SHOULD
995 optimize for Cpu686. */
996 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
997 patt
= alt_long_patt
;
1001 case PROCESSOR_PENTIUMPRO
:
1002 case PROCESSOR_PENTIUM4
:
1003 case PROCESSOR_NOCONA
:
1004 case PROCESSOR_CORE
:
1005 case PROCESSOR_CORE2
:
1006 case PROCESSOR_COREI7
:
1007 case PROCESSOR_GENERIC64
:
1008 patt
= alt_long_patt
;
1011 case PROCESSOR_ATHLON
:
1013 case PROCESSOR_AMDFAM10
:
1014 patt
= alt_short_patt
;
1016 case PROCESSOR_I386
:
1017 case PROCESSOR_I486
:
1018 case PROCESSOR_PENTIUM
:
1019 case PROCESSOR_GENERIC32
:
1026 switch (fragP
->tc_frag_data
.tune
)
1028 case PROCESSOR_UNKNOWN
:
1029 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1030 PROCESSOR_UNKNOWN. */
1034 case PROCESSOR_I386
:
1035 case PROCESSOR_I486
:
1036 case PROCESSOR_PENTIUM
:
1038 case PROCESSOR_ATHLON
:
1040 case PROCESSOR_AMDFAM10
:
1041 case PROCESSOR_GENERIC32
:
1042 /* We use cpu_arch_isa_flags to check if we CAN optimize
1044 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1045 patt
= alt_short_patt
;
1049 case PROCESSOR_PENTIUMPRO
:
1050 case PROCESSOR_PENTIUM4
:
1051 case PROCESSOR_NOCONA
:
1052 case PROCESSOR_CORE
:
1053 case PROCESSOR_CORE2
:
1054 case PROCESSOR_COREI7
:
1055 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1056 patt
= alt_long_patt
;
1060 case PROCESSOR_GENERIC64
:
1061 patt
= alt_long_patt
;
1066 if (patt
== f32_patt
)
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1072 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1073 patt
[count
- 1], count
);
1076 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1078 /* Adjust jump offset. */
1079 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1084 /* Maximum length of an instruction is 15 byte. If the
1085 padding is greater than 15 bytes and we don't use jump,
1086 we have to break it into smaller pieces. */
1087 int padding
= count
;
1088 while (padding
> 15)
1091 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1096 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1097 patt
[padding
- 1], padding
);
1100 fragP
->fr_var
= count
;
1104 operand_type_all_zero (const union i386_operand_type
*x
)
1106 switch (ARRAY_SIZE(x
->array
))
1115 return !x
->array
[0];
1122 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1124 switch (ARRAY_SIZE(x
->array
))
1139 operand_type_equal (const union i386_operand_type
*x
,
1140 const union i386_operand_type
*y
)
1142 switch (ARRAY_SIZE(x
->array
))
1145 if (x
->array
[2] != y
->array
[2])
1148 if (x
->array
[1] != y
->array
[1])
1151 return x
->array
[0] == y
->array
[0];
1159 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1161 switch (ARRAY_SIZE(x
->array
))
1170 return !x
->array
[0];
1177 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1179 switch (ARRAY_SIZE(x
->array
))
1194 cpu_flags_equal (const union i386_cpu_flags
*x
,
1195 const union i386_cpu_flags
*y
)
1197 switch (ARRAY_SIZE(x
->array
))
1200 if (x
->array
[2] != y
->array
[2])
1203 if (x
->array
[1] != y
->array
[1])
1206 return x
->array
[0] == y
->array
[0];
1214 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1216 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1217 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1220 static INLINE i386_cpu_flags
1221 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1223 switch (ARRAY_SIZE (x
.array
))
1226 x
.array
[2] &= y
.array
[2];
1228 x
.array
[1] &= y
.array
[1];
1230 x
.array
[0] &= y
.array
[0];
1238 static INLINE i386_cpu_flags
1239 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1241 switch (ARRAY_SIZE (x
.array
))
1244 x
.array
[2] |= y
.array
[2];
1246 x
.array
[1] |= y
.array
[1];
1248 x
.array
[0] |= y
.array
[0];
1256 #define CPU_FLAGS_ARCH_MATCH 0x1
1257 #define CPU_FLAGS_64BIT_MATCH 0x2
1258 #define CPU_FLAGS_AES_MATCH 0x4
1259 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1260 #define CPU_FLAGS_AVX_MATCH 0x10
1262 #define CPU_FLAGS_32BIT_MATCH \
1263 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1264 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1265 #define CPU_FLAGS_PERFECT_MATCH \
1266 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1268 /* Return CPU flags match bits. */
1271 cpu_flags_match (const template *t
)
1273 i386_cpu_flags x
= t
->cpu_flags
;
1274 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1276 x
.bitfield
.cpu64
= 0;
1277 x
.bitfield
.cpuno64
= 0;
1279 if (cpu_flags_all_zero (&x
))
1281 /* This instruction is available on all archs. */
1282 match
|= CPU_FLAGS_32BIT_MATCH
;
1286 /* This instruction is available only on some archs. */
1287 i386_cpu_flags cpu
= cpu_arch_flags
;
1289 cpu
.bitfield
.cpu64
= 0;
1290 cpu
.bitfield
.cpuno64
= 0;
1291 cpu
= cpu_flags_and (x
, cpu
);
1292 if (!cpu_flags_all_zero (&cpu
))
1294 if (x
.bitfield
.cpuavx
)
1296 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1297 if (cpu
.bitfield
.cpuavx
)
1299 /* Check SSE2AVX. */
1300 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1302 match
|= (CPU_FLAGS_ARCH_MATCH
1303 | CPU_FLAGS_AVX_MATCH
);
1305 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1306 match
|= CPU_FLAGS_AES_MATCH
;
1308 if (!x
.bitfield
.cpupclmul
1309 || cpu
.bitfield
.cpupclmul
)
1310 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1314 match
|= CPU_FLAGS_ARCH_MATCH
;
1317 match
|= CPU_FLAGS_32BIT_MATCH
;
1323 static INLINE i386_operand_type
1324 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1326 switch (ARRAY_SIZE (x
.array
))
1329 x
.array
[2] &= y
.array
[2];
1331 x
.array
[1] &= y
.array
[1];
1333 x
.array
[0] &= y
.array
[0];
1341 static INLINE i386_operand_type
1342 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1344 switch (ARRAY_SIZE (x
.array
))
1347 x
.array
[2] |= y
.array
[2];
1349 x
.array
[1] |= y
.array
[1];
1351 x
.array
[0] |= y
.array
[0];
1359 static INLINE i386_operand_type
1360 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1362 switch (ARRAY_SIZE (x
.array
))
1365 x
.array
[2] ^= y
.array
[2];
1367 x
.array
[1] ^= y
.array
[1];
1369 x
.array
[0] ^= y
.array
[0];
1377 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1378 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1379 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1380 static const i386_operand_type inoutportreg
1381 = OPERAND_TYPE_INOUTPORTREG
;
1382 static const i386_operand_type reg16_inoutportreg
1383 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1384 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1385 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1386 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1387 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1388 static const i386_operand_type anydisp
1389 = OPERAND_TYPE_ANYDISP
;
1390 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1391 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1392 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1393 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1394 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1395 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1396 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1397 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1398 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1399 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1400 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1411 operand_type_check (i386_operand_type t
, enum operand_type c
)
1416 return (t
.bitfield
.reg8
1419 || t
.bitfield
.reg64
);
1422 return (t
.bitfield
.imm8
1426 || t
.bitfield
.imm32s
1427 || t
.bitfield
.imm64
);
1430 return (t
.bitfield
.disp8
1431 || t
.bitfield
.disp16
1432 || t
.bitfield
.disp32
1433 || t
.bitfield
.disp32s
1434 || t
.bitfield
.disp64
);
1437 return (t
.bitfield
.disp8
1438 || t
.bitfield
.disp16
1439 || t
.bitfield
.disp32
1440 || t
.bitfield
.disp32s
1441 || t
.bitfield
.disp64
1442 || t
.bitfield
.baseindex
);
1451 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1452 operand J for instruction template T. */
1455 match_reg_size (const template *t
, unsigned int j
)
1457 return !((i
.types
[j
].bitfield
.byte
1458 && !t
->operand_types
[j
].bitfield
.byte
)
1459 || (i
.types
[j
].bitfield
.word
1460 && !t
->operand_types
[j
].bitfield
.word
)
1461 || (i
.types
[j
].bitfield
.dword
1462 && !t
->operand_types
[j
].bitfield
.dword
)
1463 || (i
.types
[j
].bitfield
.qword
1464 && !t
->operand_types
[j
].bitfield
.qword
));
1467 /* Return 1 if there is no conflict in any size on operand J for
1468 instruction template T. */
1471 match_mem_size (const template *t
, unsigned int j
)
1473 return (match_reg_size (t
, j
)
1474 && !((i
.types
[j
].bitfield
.unspecified
1475 && !t
->operand_types
[j
].bitfield
.unspecified
)
1476 || (i
.types
[j
].bitfield
.fword
1477 && !t
->operand_types
[j
].bitfield
.fword
)
1478 || (i
.types
[j
].bitfield
.tbyte
1479 && !t
->operand_types
[j
].bitfield
.tbyte
)
1480 || (i
.types
[j
].bitfield
.xmmword
1481 && !t
->operand_types
[j
].bitfield
.xmmword
)
1482 || (i
.types
[j
].bitfield
.ymmword
1483 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1486 /* Return 1 if there is no size conflict on any operands for
1487 instruction template T. */
1490 operand_size_match (const template *t
)
1495 /* Don't check jump instructions. */
1496 if (t
->opcode_modifier
.jump
1497 || t
->opcode_modifier
.jumpbyte
1498 || t
->opcode_modifier
.jumpdword
1499 || t
->opcode_modifier
.jumpintersegment
)
1502 /* Check memory and accumulator operand size. */
1503 for (j
= 0; j
< i
.operands
; j
++)
1505 if (t
->operand_types
[j
].bitfield
.anysize
)
1508 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1514 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1522 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1525 /* Check reverse. */
1526 assert (i
.operands
== 2);
1529 for (j
= 0; j
< 2; j
++)
1531 if (t
->operand_types
[j
].bitfield
.acc
1532 && !match_reg_size (t
, j
? 0 : 1))
1538 if (i
.types
[j
].bitfield
.mem
1539 && !match_mem_size (t
, j
? 0 : 1))
1550 operand_type_match (i386_operand_type overlap
,
1551 i386_operand_type given
)
1553 i386_operand_type temp
= overlap
;
1555 temp
.bitfield
.jumpabsolute
= 0;
1556 temp
.bitfield
.unspecified
= 0;
1557 temp
.bitfield
.byte
= 0;
1558 temp
.bitfield
.word
= 0;
1559 temp
.bitfield
.dword
= 0;
1560 temp
.bitfield
.fword
= 0;
1561 temp
.bitfield
.qword
= 0;
1562 temp
.bitfield
.tbyte
= 0;
1563 temp
.bitfield
.xmmword
= 0;
1564 temp
.bitfield
.ymmword
= 0;
1565 if (operand_type_all_zero (&temp
))
1568 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1569 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1572 /* If given types g0 and g1 are registers they must be of the same type
1573 unless the expected operand type register overlap is null.
1574 Note that Acc in a template matches every size of reg. */
1577 operand_type_register_match (i386_operand_type m0
,
1578 i386_operand_type g0
,
1579 i386_operand_type t0
,
1580 i386_operand_type m1
,
1581 i386_operand_type g1
,
1582 i386_operand_type t1
)
1584 if (!operand_type_check (g0
, reg
))
1587 if (!operand_type_check (g1
, reg
))
1590 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1591 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1592 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1593 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1596 if (m0
.bitfield
.acc
)
1598 t0
.bitfield
.reg8
= 1;
1599 t0
.bitfield
.reg16
= 1;
1600 t0
.bitfield
.reg32
= 1;
1601 t0
.bitfield
.reg64
= 1;
1604 if (m1
.bitfield
.acc
)
1606 t1
.bitfield
.reg8
= 1;
1607 t1
.bitfield
.reg16
= 1;
1608 t1
.bitfield
.reg32
= 1;
1609 t1
.bitfield
.reg64
= 1;
1612 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1613 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1614 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1615 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1618 static INLINE
unsigned int
1619 mode_from_disp_size (i386_operand_type t
)
1621 if (t
.bitfield
.disp8
)
1623 else if (t
.bitfield
.disp16
1624 || t
.bitfield
.disp32
1625 || t
.bitfield
.disp32s
)
1632 fits_in_signed_byte (offsetT num
)
1634 return (num
>= -128) && (num
<= 127);
1638 fits_in_unsigned_byte (offsetT num
)
1640 return (num
& 0xff) == num
;
1644 fits_in_unsigned_word (offsetT num
)
1646 return (num
& 0xffff) == num
;
1650 fits_in_signed_word (offsetT num
)
1652 return (-32768 <= num
) && (num
<= 32767);
1656 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1661 return (!(((offsetT
) -1 << 31) & num
)
1662 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1664 } /* fits_in_signed_long() */
1667 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1672 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1674 } /* fits_in_unsigned_long() */
1676 static i386_operand_type
1677 smallest_imm_type (offsetT num
)
1679 i386_operand_type t
;
1681 operand_type_set (&t
, 0);
1682 t
.bitfield
.imm64
= 1;
1684 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1686 /* This code is disabled on the 486 because all the Imm1 forms
1687 in the opcode table are slower on the i486. They're the
1688 versions with the implicitly specified single-position
1689 displacement, which has another syntax if you really want to
1691 t
.bitfield
.imm1
= 1;
1692 t
.bitfield
.imm8
= 1;
1693 t
.bitfield
.imm8s
= 1;
1694 t
.bitfield
.imm16
= 1;
1695 t
.bitfield
.imm32
= 1;
1696 t
.bitfield
.imm32s
= 1;
1698 else if (fits_in_signed_byte (num
))
1700 t
.bitfield
.imm8
= 1;
1701 t
.bitfield
.imm8s
= 1;
1702 t
.bitfield
.imm16
= 1;
1703 t
.bitfield
.imm32
= 1;
1704 t
.bitfield
.imm32s
= 1;
1706 else if (fits_in_unsigned_byte (num
))
1708 t
.bitfield
.imm8
= 1;
1709 t
.bitfield
.imm16
= 1;
1710 t
.bitfield
.imm32
= 1;
1711 t
.bitfield
.imm32s
= 1;
1713 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1715 t
.bitfield
.imm16
= 1;
1716 t
.bitfield
.imm32
= 1;
1717 t
.bitfield
.imm32s
= 1;
1719 else if (fits_in_signed_long (num
))
1721 t
.bitfield
.imm32
= 1;
1722 t
.bitfield
.imm32s
= 1;
1724 else if (fits_in_unsigned_long (num
))
1725 t
.bitfield
.imm32
= 1;
1731 offset_in_range (offsetT val
, int size
)
1737 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1738 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1739 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1741 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1746 /* If BFD64, sign extend val. */
1747 if (!use_rela_relocations
)
1748 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1749 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1751 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1753 char buf1
[40], buf2
[40];
1755 sprint_value (buf1
, val
);
1756 sprint_value (buf2
, val
& mask
);
1757 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1762 /* Returns 0 if attempting to add a prefix where one from the same
1763 class already exists, 1 if non rep/repne added, 2 if rep/repne
1766 add_prefix (unsigned int prefix
)
1771 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1772 && flag_code
== CODE_64BIT
)
1774 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1775 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1776 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1787 case CS_PREFIX_OPCODE
:
1788 case DS_PREFIX_OPCODE
:
1789 case ES_PREFIX_OPCODE
:
1790 case FS_PREFIX_OPCODE
:
1791 case GS_PREFIX_OPCODE
:
1792 case SS_PREFIX_OPCODE
:
1796 case REPNE_PREFIX_OPCODE
:
1797 case REPE_PREFIX_OPCODE
:
1800 case LOCK_PREFIX_OPCODE
:
1808 case ADDR_PREFIX_OPCODE
:
1812 case DATA_PREFIX_OPCODE
:
1816 if (i
.prefix
[q
] != 0)
1824 i
.prefix
[q
] |= prefix
;
1827 as_bad (_("same type of prefix used twice"));
1833 set_code_flag (int value
)
1836 if (flag_code
== CODE_64BIT
)
1838 cpu_arch_flags
.bitfield
.cpu64
= 1;
1839 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1843 cpu_arch_flags
.bitfield
.cpu64
= 0;
1844 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1846 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1848 as_bad (_("64bit mode not supported on this CPU."));
1850 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1852 as_bad (_("32bit mode not supported on this CPU."));
1854 stackop_size
= '\0';
1858 set_16bit_gcc_code_flag (int new_code_flag
)
1860 flag_code
= new_code_flag
;
1861 if (flag_code
!= CODE_16BIT
)
1863 cpu_arch_flags
.bitfield
.cpu64
= 0;
1864 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1865 stackop_size
= LONG_MNEM_SUFFIX
;
1869 set_intel_syntax (int syntax_flag
)
1871 /* Find out if register prefixing is specified. */
1872 int ask_naked_reg
= 0;
1875 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1877 char *string
= input_line_pointer
;
1878 int e
= get_symbol_end ();
1880 if (strcmp (string
, "prefix") == 0)
1882 else if (strcmp (string
, "noprefix") == 0)
1885 as_bad (_("bad argument to syntax directive."));
1886 *input_line_pointer
= e
;
1888 demand_empty_rest_of_line ();
1890 intel_syntax
= syntax_flag
;
1892 if (ask_naked_reg
== 0)
1893 allow_naked_reg
= (intel_syntax
1894 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1896 allow_naked_reg
= (ask_naked_reg
< 0);
1898 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1899 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1900 register_prefix
= allow_naked_reg
? "" : "%";
1904 set_intel_mnemonic (int mnemonic_flag
)
1906 intel_mnemonic
= mnemonic_flag
;
1910 set_allow_index_reg (int flag
)
1912 allow_index_reg
= flag
;
1916 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1920 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1922 char *string
= input_line_pointer
;
1923 int e
= get_symbol_end ();
1925 if (strcmp (string
, "none") == 0)
1926 sse_check
= sse_check_none
;
1927 else if (strcmp (string
, "warning") == 0)
1928 sse_check
= sse_check_warning
;
1929 else if (strcmp (string
, "error") == 0)
1930 sse_check
= sse_check_error
;
1932 as_bad (_("bad argument to sse_check directive."));
1933 *input_line_pointer
= e
;
1936 as_bad (_("missing argument for sse_check directive"));
1938 demand_empty_rest_of_line ();
1942 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1946 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1948 char *string
= input_line_pointer
;
1949 int e
= get_symbol_end ();
1951 i386_cpu_flags flags
;
1953 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1955 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1959 cpu_arch_name
= cpu_arch
[i
].name
;
1960 cpu_sub_arch_name
= NULL
;
1961 cpu_arch_flags
= cpu_arch
[i
].flags
;
1962 if (flag_code
== CODE_64BIT
)
1964 cpu_arch_flags
.bitfield
.cpu64
= 1;
1965 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1969 cpu_arch_flags
.bitfield
.cpu64
= 0;
1970 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1972 cpu_arch_isa
= cpu_arch
[i
].type
;
1973 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1974 if (!cpu_arch_tune_set
)
1976 cpu_arch_tune
= cpu_arch_isa
;
1977 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1982 flags
= cpu_flags_or (cpu_arch_flags
,
1984 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1986 if (cpu_sub_arch_name
)
1988 char *name
= cpu_sub_arch_name
;
1989 cpu_sub_arch_name
= concat (name
,
1991 (const char *) NULL
);
1995 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1996 cpu_arch_flags
= flags
;
1998 *input_line_pointer
= e
;
1999 demand_empty_rest_of_line ();
2003 if (i
>= ARRAY_SIZE (cpu_arch
))
2004 as_bad (_("no such architecture: `%s'"), string
);
2006 *input_line_pointer
= e
;
2009 as_bad (_("missing cpu architecture"));
2011 no_cond_jump_promotion
= 0;
2012 if (*input_line_pointer
== ','
2013 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2015 char *string
= ++input_line_pointer
;
2016 int e
= get_symbol_end ();
2018 if (strcmp (string
, "nojumps") == 0)
2019 no_cond_jump_promotion
= 1;
2020 else if (strcmp (string
, "jumps") == 0)
2023 as_bad (_("no such architecture modifier: `%s'"), string
);
2025 *input_line_pointer
= e
;
2028 demand_empty_rest_of_line ();
2034 if (!strcmp (default_arch
, "x86_64"))
2035 return bfd_mach_x86_64
;
2036 else if (!strcmp (default_arch
, "i386"))
2037 return bfd_mach_i386_i386
;
2039 as_fatal (_("Unknown architecture"));
2045 const char *hash_err
;
2047 /* Initialize op_hash hash table. */
2048 op_hash
= hash_new ();
2051 const template *optab
;
2052 templates
*core_optab
;
2054 /* Setup for loop. */
2056 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2057 core_optab
->start
= optab
;
2062 if (optab
->name
== NULL
2063 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2065 /* different name --> ship out current template list;
2066 add to hash table; & begin anew. */
2067 core_optab
->end
= optab
;
2068 hash_err
= hash_insert (op_hash
,
2070 (void *) core_optab
);
2073 as_fatal (_("Internal Error: Can't hash %s: %s"),
2077 if (optab
->name
== NULL
)
2079 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2080 core_optab
->start
= optab
;
2085 /* Initialize reg_hash hash table. */
2086 reg_hash
= hash_new ();
2088 const reg_entry
*regtab
;
2089 unsigned int regtab_size
= i386_regtab_size
;
2091 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2093 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2095 as_fatal (_("Internal Error: Can't hash %s: %s"),
2101 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2106 for (c
= 0; c
< 256; c
++)
2111 mnemonic_chars
[c
] = c
;
2112 register_chars
[c
] = c
;
2113 operand_chars
[c
] = c
;
2115 else if (ISLOWER (c
))
2117 mnemonic_chars
[c
] = c
;
2118 register_chars
[c
] = c
;
2119 operand_chars
[c
] = c
;
2121 else if (ISUPPER (c
))
2123 mnemonic_chars
[c
] = TOLOWER (c
);
2124 register_chars
[c
] = mnemonic_chars
[c
];
2125 operand_chars
[c
] = c
;
2128 if (ISALPHA (c
) || ISDIGIT (c
))
2129 identifier_chars
[c
] = c
;
2132 identifier_chars
[c
] = c
;
2133 operand_chars
[c
] = c
;
2138 identifier_chars
['@'] = '@';
2141 identifier_chars
['?'] = '?';
2142 operand_chars
['?'] = '?';
2144 digit_chars
['-'] = '-';
2145 mnemonic_chars
['_'] = '_';
2146 mnemonic_chars
['-'] = '-';
2147 mnemonic_chars
['.'] = '.';
2148 identifier_chars
['_'] = '_';
2149 identifier_chars
['.'] = '.';
2151 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2152 operand_chars
[(unsigned char) *p
] = *p
;
2155 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2158 record_alignment (text_section
, 2);
2159 record_alignment (data_section
, 2);
2160 record_alignment (bss_section
, 2);
2164 if (flag_code
== CODE_64BIT
)
2166 x86_dwarf2_return_column
= 16;
2167 x86_cie_data_alignment
= -8;
2171 x86_dwarf2_return_column
= 8;
2172 x86_cie_data_alignment
= -4;
2177 i386_print_statistics (FILE *file
)
2179 hash_print_statistics (file
, "i386 opcode", op_hash
);
2180 hash_print_statistics (file
, "i386 register", reg_hash
);
2185 /* Debugging routines for md_assemble. */
2186 static void pte (template *);
2187 static void pt (i386_operand_type
);
2188 static void pe (expressionS
*);
2189 static void ps (symbolS
*);
2192 pi (char *line
, i386_insn
*x
)
2196 fprintf (stdout
, "%s: template ", line
);
2198 fprintf (stdout
, " address: base %s index %s scale %x\n",
2199 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2200 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2201 x
->log2_scale_factor
);
2202 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2203 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2204 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2205 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2206 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2207 (x
->rex
& REX_W
) != 0,
2208 (x
->rex
& REX_R
) != 0,
2209 (x
->rex
& REX_X
) != 0,
2210 (x
->rex
& REX_B
) != 0);
2211 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2212 x
->drex
.reg
, x
->drex
.rex
);
2213 for (i
= 0; i
< x
->operands
; i
++)
2215 fprintf (stdout
, " #%d: ", i
+ 1);
2217 fprintf (stdout
, "\n");
2218 if (x
->types
[i
].bitfield
.reg8
2219 || x
->types
[i
].bitfield
.reg16
2220 || x
->types
[i
].bitfield
.reg32
2221 || x
->types
[i
].bitfield
.reg64
2222 || x
->types
[i
].bitfield
.regmmx
2223 || x
->types
[i
].bitfield
.regxmm
2224 || x
->types
[i
].bitfield
.regymm
2225 || x
->types
[i
].bitfield
.sreg2
2226 || x
->types
[i
].bitfield
.sreg3
2227 || x
->types
[i
].bitfield
.control
2228 || x
->types
[i
].bitfield
.debug
2229 || x
->types
[i
].bitfield
.test
)
2230 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2231 if (operand_type_check (x
->types
[i
], imm
))
2233 if (operand_type_check (x
->types
[i
], disp
))
2234 pe (x
->op
[i
].disps
);
2242 fprintf (stdout
, " %d operands ", t
->operands
);
2243 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2244 if (t
->extension_opcode
!= None
)
2245 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2246 if (t
->opcode_modifier
.d
)
2247 fprintf (stdout
, "D");
2248 if (t
->opcode_modifier
.w
)
2249 fprintf (stdout
, "W");
2250 fprintf (stdout
, "\n");
2251 for (i
= 0; i
< t
->operands
; i
++)
2253 fprintf (stdout
, " #%d type ", i
+ 1);
2254 pt (t
->operand_types
[i
]);
2255 fprintf (stdout
, "\n");
2262 fprintf (stdout
, " operation %d\n", e
->X_op
);
2263 fprintf (stdout
, " add_number %ld (%lx)\n",
2264 (long) e
->X_add_number
, (long) e
->X_add_number
);
2265 if (e
->X_add_symbol
)
2267 fprintf (stdout
, " add_symbol ");
2268 ps (e
->X_add_symbol
);
2269 fprintf (stdout
, "\n");
2273 fprintf (stdout
, " op_symbol ");
2274 ps (e
->X_op_symbol
);
2275 fprintf (stdout
, "\n");
2282 fprintf (stdout
, "%s type %s%s",
2284 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2285 segment_name (S_GET_SEGMENT (s
)));
2288 static struct type_name
2290 i386_operand_type mask
;
2293 const type_names
[] =
2295 { OPERAND_TYPE_REG8
, "r8" },
2296 { OPERAND_TYPE_REG16
, "r16" },
2297 { OPERAND_TYPE_REG32
, "r32" },
2298 { OPERAND_TYPE_REG64
, "r64" },
2299 { OPERAND_TYPE_IMM8
, "i8" },
2300 { OPERAND_TYPE_IMM8
, "i8s" },
2301 { OPERAND_TYPE_IMM16
, "i16" },
2302 { OPERAND_TYPE_IMM32
, "i32" },
2303 { OPERAND_TYPE_IMM32S
, "i32s" },
2304 { OPERAND_TYPE_IMM64
, "i64" },
2305 { OPERAND_TYPE_IMM1
, "i1" },
2306 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2307 { OPERAND_TYPE_DISP8
, "d8" },
2308 { OPERAND_TYPE_DISP16
, "d16" },
2309 { OPERAND_TYPE_DISP32
, "d32" },
2310 { OPERAND_TYPE_DISP32S
, "d32s" },
2311 { OPERAND_TYPE_DISP64
, "d64" },
2312 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2313 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2314 { OPERAND_TYPE_CONTROL
, "control reg" },
2315 { OPERAND_TYPE_TEST
, "test reg" },
2316 { OPERAND_TYPE_DEBUG
, "debug reg" },
2317 { OPERAND_TYPE_FLOATREG
, "FReg" },
2318 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2319 { OPERAND_TYPE_SREG2
, "SReg2" },
2320 { OPERAND_TYPE_SREG3
, "SReg3" },
2321 { OPERAND_TYPE_ACC
, "Acc" },
2322 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2323 { OPERAND_TYPE_REGMMX
, "rMMX" },
2324 { OPERAND_TYPE_REGXMM
, "rXMM" },
2325 { OPERAND_TYPE_REGYMM
, "rYMM" },
2326 { OPERAND_TYPE_ESSEG
, "es" },
2330 pt (i386_operand_type t
)
2333 i386_operand_type a
;
2335 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2337 a
= operand_type_and (t
, type_names
[j
].mask
);
2338 if (!operand_type_all_zero (&a
))
2339 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2344 #endif /* DEBUG386 */
2346 static bfd_reloc_code_real_type
2347 reloc (unsigned int size
,
2350 bfd_reloc_code_real_type other
)
2352 if (other
!= NO_RELOC
)
2354 reloc_howto_type
*reloc
;
2359 case BFD_RELOC_X86_64_GOT32
:
2360 return BFD_RELOC_X86_64_GOT64
;
2362 case BFD_RELOC_X86_64_PLTOFF64
:
2363 return BFD_RELOC_X86_64_PLTOFF64
;
2365 case BFD_RELOC_X86_64_GOTPC32
:
2366 other
= BFD_RELOC_X86_64_GOTPC64
;
2368 case BFD_RELOC_X86_64_GOTPCREL
:
2369 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2371 case BFD_RELOC_X86_64_TPOFF32
:
2372 other
= BFD_RELOC_X86_64_TPOFF64
;
2374 case BFD_RELOC_X86_64_DTPOFF32
:
2375 other
= BFD_RELOC_X86_64_DTPOFF64
;
2381 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2382 if (size
== 4 && flag_code
!= CODE_64BIT
)
2385 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2387 as_bad (_("unknown relocation (%u)"), other
);
2388 else if (size
!= bfd_get_reloc_size (reloc
))
2389 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2390 bfd_get_reloc_size (reloc
),
2392 else if (pcrel
&& !reloc
->pc_relative
)
2393 as_bad (_("non-pc-relative relocation for pc-relative field"));
2394 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2396 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2398 as_bad (_("relocated field and relocation type differ in signedness"));
2407 as_bad (_("there are no unsigned pc-relative relocations"));
2410 case 1: return BFD_RELOC_8_PCREL
;
2411 case 2: return BFD_RELOC_16_PCREL
;
2412 case 4: return BFD_RELOC_32_PCREL
;
2413 case 8: return BFD_RELOC_64_PCREL
;
2415 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2422 case 4: return BFD_RELOC_X86_64_32S
;
2427 case 1: return BFD_RELOC_8
;
2428 case 2: return BFD_RELOC_16
;
2429 case 4: return BFD_RELOC_32
;
2430 case 8: return BFD_RELOC_64
;
2432 as_bad (_("cannot do %s %u byte relocation"),
2433 sign
> 0 ? "signed" : "unsigned", size
);
2439 /* Here we decide which fixups can be adjusted to make them relative to
2440 the beginning of the section instead of the symbol. Basically we need
2441 to make sure that the dynamic relocations are done correctly, so in
2442 some cases we force the original symbol to be used. */
2445 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2447 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2451 /* Don't adjust pc-relative references to merge sections in 64-bit
2453 if (use_rela_relocations
2454 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2458 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2459 and changed later by validate_fix. */
2460 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2461 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2464 /* adjust_reloc_syms doesn't know about the GOT. */
2465 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2466 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2467 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2491 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2492 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2499 intel_float_operand (const char *mnemonic
)
2501 /* Note that the value returned is meaningful only for opcodes with (memory)
2502 operands, hence the code here is free to improperly handle opcodes that
2503 have no operands (for better performance and smaller code). */
2505 if (mnemonic
[0] != 'f')
2506 return 0; /* non-math */
2508 switch (mnemonic
[1])
2510 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2511 the fs segment override prefix not currently handled because no
2512 call path can make opcodes without operands get here */
2514 return 2 /* integer op */;
2516 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2517 return 3; /* fldcw/fldenv */
2520 if (mnemonic
[2] != 'o' /* fnop */)
2521 return 3; /* non-waiting control op */
2524 if (mnemonic
[2] == 's')
2525 return 3; /* frstor/frstpm */
2528 if (mnemonic
[2] == 'a')
2529 return 3; /* fsave */
2530 if (mnemonic
[2] == 't')
2532 switch (mnemonic
[3])
2534 case 'c': /* fstcw */
2535 case 'd': /* fstdw */
2536 case 'e': /* fstenv */
2537 case 's': /* fsts[gw] */
2543 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2544 return 0; /* fxsave/fxrstor are not really math ops */
2551 /* Build the VEX prefix. */
2554 build_vex_prefix (const template *t
)
2556 unsigned int register_specifier
;
2557 unsigned int implied_prefix
;
2558 unsigned int vector_length
;
2560 /* Check register specifier. */
2561 if (i
.vex
.register_specifier
)
2563 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2564 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2565 register_specifier
+= 8;
2566 register_specifier
= ~register_specifier
& 0xf;
2569 register_specifier
= 0xf;
2571 /* Use 2-byte VEX prefix by swappping destination and source
2574 && i
.operands
== i
.reg_operands
2575 && i
.tm
.opcode_modifier
.vex0f
2576 && i
.tm
.opcode_modifier
.s
2579 unsigned int xchg
= i
.operands
- 1;
2580 union i386_op temp_op
;
2581 i386_operand_type temp_type
;
2583 temp_type
= i
.types
[xchg
];
2584 i
.types
[xchg
] = i
.types
[0];
2585 i
.types
[0] = temp_type
;
2586 temp_op
= i
.op
[xchg
];
2587 i
.op
[xchg
] = i
.op
[0];
2590 assert (i
.rm
.mode
== 3);
2594 i
.rm
.regmem
= i
.rm
.reg
;
2597 /* Use the next insn. */
2601 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2603 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2608 case DATA_PREFIX_OPCODE
:
2611 case REPE_PREFIX_OPCODE
:
2614 case REPNE_PREFIX_OPCODE
:
2621 /* Use 2-byte VEX prefix if possible. */
2622 if (i
.tm
.opcode_modifier
.vex0f
2623 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2625 /* 2-byte VEX prefix. */
2629 i
.vex
.bytes
[0] = 0xc5;
2631 /* Check the REX.R bit. */
2632 r
= (i
.rex
& REX_R
) ? 0 : 1;
2633 i
.vex
.bytes
[1] = (r
<< 7
2634 | register_specifier
<< 3
2635 | vector_length
<< 2
2640 /* 3-byte VEX prefix. */
2643 if (i
.tm
.opcode_modifier
.vex0f
)
2645 else if (i
.tm
.opcode_modifier
.vex0f38
)
2647 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2653 i
.vex
.bytes
[0] = 0xc4;
2655 /* The high 3 bits of the second VEX byte are 1's compliment
2656 of RXB bits from REX. */
2657 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2659 /* Check the REX.W bit. */
2660 w
= (i
.rex
& REX_W
) ? 1 : 0;
2661 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2666 if (i
.tm
.opcode_modifier
.vexw1
)
2670 i
.vex
.bytes
[2] = (w
<< 7
2671 | register_specifier
<< 3
2672 | vector_length
<< 2
2678 process_immext (void)
2682 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2684 /* SSE3 Instructions have the fixed operands with an opcode
2685 suffix which is coded in the same place as an 8-bit immediate
2686 field would be. Here we check those operands and remove them
2690 for (x
= 0; x
< i
.operands
; x
++)
2691 if (i
.op
[x
].regs
->reg_num
!= x
)
2692 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2693 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2699 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2700 which is coded in the same place as an 8-bit immediate field
2701 would be. Here we fake an 8-bit immediate operand from the
2702 opcode suffix stored in tm.extension_opcode.
2704 SSE5 and AVX instructions also use this encoding, for some of
2705 3 argument instructions. */
2707 assert (i
.imm_operands
== 0
2709 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2711 || (i
.tm
.opcode_modifier
.vex
2712 && i
.operands
<= 4)));
2714 exp
= &im_expressions
[i
.imm_operands
++];
2715 i
.op
[i
.operands
].imms
= exp
;
2716 i
.types
[i
.operands
] = imm8
;
2718 exp
->X_op
= O_constant
;
2719 exp
->X_add_number
= i
.tm
.extension_opcode
;
2720 i
.tm
.extension_opcode
= None
;
2723 /* This is the guts of the machine-dependent assembler. LINE points to a
2724 machine dependent instruction. This function is supposed to emit
2725 the frags/bytes it assembles to. */
2728 md_assemble (char *line
)
2731 char mnemonic
[MAX_MNEM_SIZE
];
2734 /* Initialize globals. */
2735 memset (&i
, '\0', sizeof (i
));
2736 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2737 i
.reloc
[j
] = NO_RELOC
;
2738 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2739 memset (im_expressions
, '\0', sizeof (im_expressions
));
2740 save_stack_p
= save_stack
;
2742 /* First parse an instruction mnemonic & call i386_operand for the operands.
2743 We assume that the scrubber has arranged it so that line[0] is the valid
2744 start of a (possibly prefixed) mnemonic. */
2746 line
= parse_insn (line
, mnemonic
);
2750 line
= parse_operands (line
, mnemonic
);
2754 /* Now we've parsed the mnemonic into a set of templates, and have the
2755 operands at hand. */
2757 /* All intel opcodes have reversed operands except for "bound" and
2758 "enter". We also don't reverse intersegment "jmp" and "call"
2759 instructions with 2 immediate operands so that the immediate segment
2760 precedes the offset, as it does when in AT&T mode. */
2763 && (strcmp (mnemonic
, "bound") != 0)
2764 && (strcmp (mnemonic
, "invlpga") != 0)
2765 && !(operand_type_check (i
.types
[0], imm
)
2766 && operand_type_check (i
.types
[1], imm
)))
2769 /* The order of the immediates should be reversed
2770 for 2 immediates extrq and insertq instructions */
2771 if (i
.imm_operands
== 2
2772 && (strcmp (mnemonic
, "extrq") == 0
2773 || strcmp (mnemonic
, "insertq") == 0))
2774 swap_2_operands (0, 1);
2779 /* Don't optimize displacement for movabs since it only takes 64bit
2782 && (flag_code
!= CODE_64BIT
2783 || strcmp (mnemonic
, "movabs") != 0))
2786 /* Next, we find a template that matches the given insn,
2787 making sure the overlap of the given operands types is consistent
2788 with the template operand types. */
2790 if (!(t
= match_template ()))
2793 if (sse_check
!= sse_check_none
2794 && !i
.tm
.opcode_modifier
.noavx
2795 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2796 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2797 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2798 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2799 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2800 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2802 (sse_check
== sse_check_warning
2804 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2807 /* Zap movzx and movsx suffix. The suffix has been set from
2808 "word ptr" or "byte ptr" on the source operand in Intel syntax
2809 or extracted from mnemonic in AT&T syntax. But we'll use
2810 the destination register to choose the suffix for encoding. */
2811 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2813 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2814 there is no suffix, the default will be byte extension. */
2815 if (i
.reg_operands
!= 2
2818 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2823 if (i
.tm
.opcode_modifier
.fwait
)
2824 if (!add_prefix (FWAIT_OPCODE
))
2827 /* Check string instruction segment overrides. */
2828 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2830 if (!check_string ())
2832 i
.disp_operands
= 0;
2835 if (!process_suffix ())
2838 /* Make still unresolved immediate matches conform to size of immediate
2839 given in i.suffix. */
2840 if (!finalize_imm ())
2843 if (i
.types
[0].bitfield
.imm1
)
2844 i
.imm_operands
= 0; /* kludge for shift insns. */
2846 for (j
= 0; j
< 3; j
++)
2847 if (i
.types
[j
].bitfield
.inoutportreg
2848 || i
.types
[j
].bitfield
.shiftcount
2849 || i
.types
[j
].bitfield
.acc
2850 || i
.types
[j
].bitfield
.floatacc
)
2853 /* ImmExt should be processed after SSE2AVX. */
2854 if (!i
.tm
.opcode_modifier
.sse2avx
2855 && i
.tm
.opcode_modifier
.immext
)
2858 /* For insns with operands there are more diddles to do to the opcode. */
2861 if (!process_operands ())
2864 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2866 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2867 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2870 if (i
.tm
.opcode_modifier
.vex
)
2871 build_vex_prefix (t
);
2873 /* Handle conversion of 'int $3' --> special int3 insn. */
2874 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2876 i
.tm
.base_opcode
= INT3_OPCODE
;
2880 if ((i
.tm
.opcode_modifier
.jump
2881 || i
.tm
.opcode_modifier
.jumpbyte
2882 || i
.tm
.opcode_modifier
.jumpdword
)
2883 && i
.op
[0].disps
->X_op
== O_constant
)
2885 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2886 the absolute address given by the constant. Since ix86 jumps and
2887 calls are pc relative, we need to generate a reloc. */
2888 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2889 i
.op
[0].disps
->X_op
= O_symbol
;
2892 if (i
.tm
.opcode_modifier
.rex64
)
2895 /* For 8 bit registers we need an empty rex prefix. Also if the
2896 instruction already has a prefix, we need to convert old
2897 registers to new ones. */
2899 if ((i
.types
[0].bitfield
.reg8
2900 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2901 || (i
.types
[1].bitfield
.reg8
2902 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2903 || ((i
.types
[0].bitfield
.reg8
2904 || i
.types
[1].bitfield
.reg8
)
2909 i
.rex
|= REX_OPCODE
;
2910 for (x
= 0; x
< 2; x
++)
2912 /* Look for 8 bit operand that uses old registers. */
2913 if (i
.types
[x
].bitfield
.reg8
2914 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2916 /* In case it is "hi" register, give up. */
2917 if (i
.op
[x
].regs
->reg_num
> 3)
2918 as_bad (_("can't encode register '%s%s' in an "
2919 "instruction requiring REX prefix."),
2920 register_prefix
, i
.op
[x
].regs
->reg_name
);
2922 /* Otherwise it is equivalent to the extended register.
2923 Since the encoding doesn't change this is merely
2924 cosmetic cleanup for debug output. */
2926 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2931 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2933 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2938 else if (i
.rex
!= 0)
2939 add_prefix (REX_OPCODE
| i
.rex
);
2941 /* We are ready to output the insn. */
2946 parse_insn (char *line
, char *mnemonic
)
2949 char *token_start
= l
;
2955 /* Non-zero if we found a prefix only acceptable with string insns. */
2956 const char *expecting_string_instruction
= NULL
;
2961 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2966 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2968 as_bad (_("no such instruction: `%s'"), token_start
);
2973 if (!is_space_char (*l
)
2974 && *l
!= END_OF_INSN
2976 || (*l
!= PREFIX_SEPARATOR
2979 as_bad (_("invalid character %s in mnemonic"),
2980 output_invalid (*l
));
2983 if (token_start
== l
)
2985 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2986 as_bad (_("expecting prefix; got nothing"));
2988 as_bad (_("expecting mnemonic; got nothing"));
2992 /* Look up instruction (or prefix) via hash table. */
2993 current_templates
= hash_find (op_hash
, mnemonic
);
2995 if (*l
!= END_OF_INSN
2996 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2997 && current_templates
2998 && current_templates
->start
->opcode_modifier
.isprefix
)
3000 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3002 as_bad ((flag_code
!= CODE_64BIT
3003 ? _("`%s' is only supported in 64-bit mode")
3004 : _("`%s' is not supported in 64-bit mode")),
3005 current_templates
->start
->name
);
3008 /* If we are in 16-bit mode, do not allow addr16 or data16.
3009 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3010 if ((current_templates
->start
->opcode_modifier
.size16
3011 || current_templates
->start
->opcode_modifier
.size32
)
3012 && flag_code
!= CODE_64BIT
3013 && (current_templates
->start
->opcode_modifier
.size32
3014 ^ (flag_code
== CODE_16BIT
)))
3016 as_bad (_("redundant %s prefix"),
3017 current_templates
->start
->name
);
3020 /* Add prefix, checking for repeated prefixes. */
3021 switch (add_prefix (current_templates
->start
->base_opcode
))
3026 expecting_string_instruction
= current_templates
->start
->name
;
3029 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3036 if (!current_templates
)
3038 /* Check if we should swap operand in encoding. */
3039 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3045 current_templates
= hash_find (op_hash
, mnemonic
);
3048 if (!current_templates
)
3051 /* See if we can get a match by trimming off a suffix. */
3054 case WORD_MNEM_SUFFIX
:
3055 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3056 i
.suffix
= SHORT_MNEM_SUFFIX
;
3058 case BYTE_MNEM_SUFFIX
:
3059 case QWORD_MNEM_SUFFIX
:
3060 i
.suffix
= mnem_p
[-1];
3062 current_templates
= hash_find (op_hash
, mnemonic
);
3064 case SHORT_MNEM_SUFFIX
:
3065 case LONG_MNEM_SUFFIX
:
3068 i
.suffix
= mnem_p
[-1];
3070 current_templates
= hash_find (op_hash
, mnemonic
);
3078 if (intel_float_operand (mnemonic
) == 1)
3079 i
.suffix
= SHORT_MNEM_SUFFIX
;
3081 i
.suffix
= LONG_MNEM_SUFFIX
;
3083 current_templates
= hash_find (op_hash
, mnemonic
);
3087 if (!current_templates
)
3089 as_bad (_("no such instruction: `%s'"), token_start
);
3094 if (current_templates
->start
->opcode_modifier
.jump
3095 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3097 /* Check for a branch hint. We allow ",pt" and ",pn" for
3098 predict taken and predict not taken respectively.
3099 I'm not sure that branch hints actually do anything on loop
3100 and jcxz insns (JumpByte) for current Pentium4 chips. They
3101 may work in the future and it doesn't hurt to accept them
3103 if (l
[0] == ',' && l
[1] == 'p')
3107 if (!add_prefix (DS_PREFIX_OPCODE
))
3111 else if (l
[2] == 'n')
3113 if (!add_prefix (CS_PREFIX_OPCODE
))
3119 /* Any other comma loses. */
3122 as_bad (_("invalid character %s in mnemonic"),
3123 output_invalid (*l
));
3127 /* Check if instruction is supported on specified architecture. */
3129 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3131 supported
|= cpu_flags_match (t
);
3132 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3136 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3138 as_bad (flag_code
== CODE_64BIT
3139 ? _("`%s' is not supported in 64-bit mode")
3140 : _("`%s' is only supported in 64-bit mode"),
3141 current_templates
->start
->name
);
3144 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3146 as_bad (_("`%s' is not supported on `%s%s'"),
3147 current_templates
->start
->name
,
3148 cpu_arch_name
? cpu_arch_name
: default_arch
,
3149 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3154 if (!cpu_arch_flags
.bitfield
.cpui386
3155 && (flag_code
!= CODE_16BIT
))
3157 as_warn (_("use .code16 to ensure correct addressing mode"));
3160 /* Check for rep/repne without a string instruction. */
3161 if (expecting_string_instruction
)
3163 static templates override
;
3165 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3166 if (t
->opcode_modifier
.isstring
)
3168 if (t
>= current_templates
->end
)
3170 as_bad (_("expecting string instruction after `%s'"),
3171 expecting_string_instruction
);
3174 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3175 if (!t
->opcode_modifier
.isstring
)
3178 current_templates
= &override
;
3185 parse_operands (char *l
, const char *mnemonic
)
3189 /* 1 if operand is pending after ','. */
3190 unsigned int expecting_operand
= 0;
3192 /* Non-zero if operand parens not balanced. */
3193 unsigned int paren_not_balanced
;
3195 while (*l
!= END_OF_INSN
)
3197 /* Skip optional white space before operand. */
3198 if (is_space_char (*l
))
3200 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3202 as_bad (_("invalid character %s before operand %d"),
3203 output_invalid (*l
),
3207 token_start
= l
; /* after white space */
3208 paren_not_balanced
= 0;
3209 while (paren_not_balanced
|| *l
!= ',')
3211 if (*l
== END_OF_INSN
)
3213 if (paren_not_balanced
)
3216 as_bad (_("unbalanced parenthesis in operand %d."),
3219 as_bad (_("unbalanced brackets in operand %d."),
3224 break; /* we are done */
3226 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3228 as_bad (_("invalid character %s in operand %d"),
3229 output_invalid (*l
),
3236 ++paren_not_balanced
;
3238 --paren_not_balanced
;
3243 ++paren_not_balanced
;
3245 --paren_not_balanced
;
3249 if (l
!= token_start
)
3250 { /* Yes, we've read in another operand. */
3251 unsigned int operand_ok
;
3252 this_operand
= i
.operands
++;
3253 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3254 if (i
.operands
> MAX_OPERANDS
)
3256 as_bad (_("spurious operands; (%d operands/instruction max)"),
3260 /* Now parse operand adding info to 'i' as we go along. */
3261 END_STRING_AND_SAVE (l
);
3265 i386_intel_operand (token_start
,
3266 intel_float_operand (mnemonic
));
3268 operand_ok
= i386_att_operand (token_start
);
3270 RESTORE_END_STRING (l
);
3276 if (expecting_operand
)
3278 expecting_operand_after_comma
:
3279 as_bad (_("expecting operand after ','; got nothing"));
3284 as_bad (_("expecting operand before ','; got nothing"));
3289 /* Now *l must be either ',' or END_OF_INSN. */
3292 if (*++l
== END_OF_INSN
)
3294 /* Just skip it, if it's \n complain. */
3295 goto expecting_operand_after_comma
;
3297 expecting_operand
= 1;
3304 swap_2_operands (int xchg1
, int xchg2
)
3306 union i386_op temp_op
;
3307 i386_operand_type temp_type
;
3308 enum bfd_reloc_code_real temp_reloc
;
3310 temp_type
= i
.types
[xchg2
];
3311 i
.types
[xchg2
] = i
.types
[xchg1
];
3312 i
.types
[xchg1
] = temp_type
;
3313 temp_op
= i
.op
[xchg2
];
3314 i
.op
[xchg2
] = i
.op
[xchg1
];
3315 i
.op
[xchg1
] = temp_op
;
3316 temp_reloc
= i
.reloc
[xchg2
];
3317 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3318 i
.reloc
[xchg1
] = temp_reloc
;
3322 swap_operands (void)
3328 swap_2_operands (1, i
.operands
- 2);
3331 swap_2_operands (0, i
.operands
- 1);
3337 if (i
.mem_operands
== 2)
3339 const seg_entry
*temp_seg
;
3340 temp_seg
= i
.seg
[0];
3341 i
.seg
[0] = i
.seg
[1];
3342 i
.seg
[1] = temp_seg
;
3346 /* Try to ensure constant immediates are represented in the smallest
3351 char guess_suffix
= 0;
3355 guess_suffix
= i
.suffix
;
3356 else if (i
.reg_operands
)
3358 /* Figure out a suffix from the last register operand specified.
3359 We can't do this properly yet, ie. excluding InOutPortReg,
3360 but the following works for instructions with immediates.
3361 In any case, we can't set i.suffix yet. */
3362 for (op
= i
.operands
; --op
>= 0;)
3363 if (i
.types
[op
].bitfield
.reg8
)
3365 guess_suffix
= BYTE_MNEM_SUFFIX
;
3368 else if (i
.types
[op
].bitfield
.reg16
)
3370 guess_suffix
= WORD_MNEM_SUFFIX
;
3373 else if (i
.types
[op
].bitfield
.reg32
)
3375 guess_suffix
= LONG_MNEM_SUFFIX
;
3378 else if (i
.types
[op
].bitfield
.reg64
)
3380 guess_suffix
= QWORD_MNEM_SUFFIX
;
3384 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3385 guess_suffix
= WORD_MNEM_SUFFIX
;
3387 for (op
= i
.operands
; --op
>= 0;)
3388 if (operand_type_check (i
.types
[op
], imm
))
3390 switch (i
.op
[op
].imms
->X_op
)
3393 /* If a suffix is given, this operand may be shortened. */
3394 switch (guess_suffix
)
3396 case LONG_MNEM_SUFFIX
:
3397 i
.types
[op
].bitfield
.imm32
= 1;
3398 i
.types
[op
].bitfield
.imm64
= 1;
3400 case WORD_MNEM_SUFFIX
:
3401 i
.types
[op
].bitfield
.imm16
= 1;
3402 i
.types
[op
].bitfield
.imm32
= 1;
3403 i
.types
[op
].bitfield
.imm32s
= 1;
3404 i
.types
[op
].bitfield
.imm64
= 1;
3406 case BYTE_MNEM_SUFFIX
:
3407 i
.types
[op
].bitfield
.imm8
= 1;
3408 i
.types
[op
].bitfield
.imm8s
= 1;
3409 i
.types
[op
].bitfield
.imm16
= 1;
3410 i
.types
[op
].bitfield
.imm32
= 1;
3411 i
.types
[op
].bitfield
.imm32s
= 1;
3412 i
.types
[op
].bitfield
.imm64
= 1;
3416 /* If this operand is at most 16 bits, convert it
3417 to a signed 16 bit number before trying to see
3418 whether it will fit in an even smaller size.
3419 This allows a 16-bit operand such as $0xffe0 to
3420 be recognised as within Imm8S range. */
3421 if ((i
.types
[op
].bitfield
.imm16
)
3422 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3424 i
.op
[op
].imms
->X_add_number
=
3425 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3427 if ((i
.types
[op
].bitfield
.imm32
)
3428 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3431 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3432 ^ ((offsetT
) 1 << 31))
3433 - ((offsetT
) 1 << 31));
3436 = operand_type_or (i
.types
[op
],
3437 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3439 /* We must avoid matching of Imm32 templates when 64bit
3440 only immediate is available. */
3441 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3442 i
.types
[op
].bitfield
.imm32
= 0;
3449 /* Symbols and expressions. */
3451 /* Convert symbolic operand to proper sizes for matching, but don't
3452 prevent matching a set of insns that only supports sizes other
3453 than those matching the insn suffix. */
3455 i386_operand_type mask
, allowed
;
3458 operand_type_set (&mask
, 0);
3459 operand_type_set (&allowed
, 0);
3461 for (t
= current_templates
->start
;
3462 t
< current_templates
->end
;
3464 allowed
= operand_type_or (allowed
,
3465 t
->operand_types
[op
]);
3466 switch (guess_suffix
)
3468 case QWORD_MNEM_SUFFIX
:
3469 mask
.bitfield
.imm64
= 1;
3470 mask
.bitfield
.imm32s
= 1;
3472 case LONG_MNEM_SUFFIX
:
3473 mask
.bitfield
.imm32
= 1;
3475 case WORD_MNEM_SUFFIX
:
3476 mask
.bitfield
.imm16
= 1;
3478 case BYTE_MNEM_SUFFIX
:
3479 mask
.bitfield
.imm8
= 1;
3484 allowed
= operand_type_and (mask
, allowed
);
3485 if (!operand_type_all_zero (&allowed
))
3486 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3493 /* Try to use the smallest displacement type too. */
3495 optimize_disp (void)
3499 for (op
= i
.operands
; --op
>= 0;)
3500 if (operand_type_check (i
.types
[op
], disp
))
3502 if (i
.op
[op
].disps
->X_op
== O_constant
)
3504 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3506 if (i
.types
[op
].bitfield
.disp16
3507 && (disp
& ~(offsetT
) 0xffff) == 0)
3509 /* If this operand is at most 16 bits, convert
3510 to a signed 16 bit number and don't use 64bit
3512 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3513 i
.types
[op
].bitfield
.disp64
= 0;
3515 if (i
.types
[op
].bitfield
.disp32
3516 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3518 /* If this operand is at most 32 bits, convert
3519 to a signed 32 bit number and don't use 64bit
3521 disp
&= (((offsetT
) 2 << 31) - 1);
3522 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3523 i
.types
[op
].bitfield
.disp64
= 0;
3525 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3527 i
.types
[op
].bitfield
.disp8
= 0;
3528 i
.types
[op
].bitfield
.disp16
= 0;
3529 i
.types
[op
].bitfield
.disp32
= 0;
3530 i
.types
[op
].bitfield
.disp32s
= 0;
3531 i
.types
[op
].bitfield
.disp64
= 0;
3535 else if (flag_code
== CODE_64BIT
)
3537 if (fits_in_signed_long (disp
))
3539 i
.types
[op
].bitfield
.disp64
= 0;
3540 i
.types
[op
].bitfield
.disp32s
= 1;
3542 if (fits_in_unsigned_long (disp
))
3543 i
.types
[op
].bitfield
.disp32
= 1;
3545 if ((i
.types
[op
].bitfield
.disp32
3546 || i
.types
[op
].bitfield
.disp32s
3547 || i
.types
[op
].bitfield
.disp16
)
3548 && fits_in_signed_byte (disp
))
3549 i
.types
[op
].bitfield
.disp8
= 1;
3551 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3552 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3554 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3555 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3556 i
.types
[op
].bitfield
.disp8
= 0;
3557 i
.types
[op
].bitfield
.disp16
= 0;
3558 i
.types
[op
].bitfield
.disp32
= 0;
3559 i
.types
[op
].bitfield
.disp32s
= 0;
3560 i
.types
[op
].bitfield
.disp64
= 0;
3563 /* We only support 64bit displacement on constants. */
3564 i
.types
[op
].bitfield
.disp64
= 0;
3568 static const template *
3569 match_template (void)
3571 /* Points to template once we've found it. */
3573 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3574 i386_operand_type overlap4
;
3575 unsigned int found_reverse_match
;
3576 i386_opcode_modifier suffix_check
;
3577 i386_operand_type operand_types
[MAX_OPERANDS
];
3578 int addr_prefix_disp
;
3580 unsigned int found_cpu_match
;
3581 unsigned int check_register
;
3583 #if MAX_OPERANDS != 5
3584 # error "MAX_OPERANDS must be 5."
3587 found_reverse_match
= 0;
3588 addr_prefix_disp
= -1;
3590 memset (&suffix_check
, 0, sizeof (suffix_check
));
3591 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3592 suffix_check
.no_bsuf
= 1;
3593 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3594 suffix_check
.no_wsuf
= 1;
3595 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3596 suffix_check
.no_ssuf
= 1;
3597 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3598 suffix_check
.no_lsuf
= 1;
3599 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3600 suffix_check
.no_qsuf
= 1;
3601 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3602 suffix_check
.no_ldsuf
= 1;
3604 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3606 addr_prefix_disp
= -1;
3608 /* Must have right number of operands. */
3609 if (i
.operands
!= t
->operands
)
3612 /* Check processor support. */
3613 found_cpu_match
= (cpu_flags_match (t
)
3614 == CPU_FLAGS_PERFECT_MATCH
);
3615 if (!found_cpu_match
)
3618 /* Check old gcc support. */
3619 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3622 /* Check AT&T mnemonic. */
3623 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3626 /* Check AT&T syntax Intel syntax. */
3627 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3628 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3631 /* Check the suffix, except for some instructions in intel mode. */
3632 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3633 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3634 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3635 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3636 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3637 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3638 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3641 if (!operand_size_match (t
))
3644 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3645 operand_types
[j
] = t
->operand_types
[j
];
3647 /* In general, don't allow 64-bit operands in 32-bit mode. */
3648 if (i
.suffix
== QWORD_MNEM_SUFFIX
3649 && flag_code
!= CODE_64BIT
3651 ? (!t
->opcode_modifier
.ignoresize
3652 && !intel_float_operand (t
->name
))
3653 : intel_float_operand (t
->name
) != 2)
3654 && ((!operand_types
[0].bitfield
.regmmx
3655 && !operand_types
[0].bitfield
.regxmm
3656 && !operand_types
[0].bitfield
.regymm
)
3657 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3658 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3659 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3660 && (t
->base_opcode
!= 0x0fc7
3661 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3664 /* In general, don't allow 32-bit operands on pre-386. */
3665 else if (i
.suffix
== LONG_MNEM_SUFFIX
3666 && !cpu_arch_flags
.bitfield
.cpui386
3668 ? (!t
->opcode_modifier
.ignoresize
3669 && !intel_float_operand (t
->name
))
3670 : intel_float_operand (t
->name
) != 2)
3671 && ((!operand_types
[0].bitfield
.regmmx
3672 && !operand_types
[0].bitfield
.regxmm
)
3673 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3674 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3677 /* Do not verify operands when there are none. */
3681 /* We've found a match; break out of loop. */
3685 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3686 into Disp32/Disp16/Disp32 operand. */
3687 if (i
.prefix
[ADDR_PREFIX
] != 0)
3689 /* There should be only one Disp operand. */
3693 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3695 if (operand_types
[j
].bitfield
.disp16
)
3697 addr_prefix_disp
= j
;
3698 operand_types
[j
].bitfield
.disp32
= 1;
3699 operand_types
[j
].bitfield
.disp16
= 0;
3705 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3707 if (operand_types
[j
].bitfield
.disp32
)
3709 addr_prefix_disp
= j
;
3710 operand_types
[j
].bitfield
.disp32
= 0;
3711 operand_types
[j
].bitfield
.disp16
= 1;
3717 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3719 if (operand_types
[j
].bitfield
.disp64
)
3721 addr_prefix_disp
= j
;
3722 operand_types
[j
].bitfield
.disp64
= 0;
3723 operand_types
[j
].bitfield
.disp32
= 1;
3731 /* We check register size only if size of operands can be
3732 encoded the canonical way. */
3733 check_register
= t
->opcode_modifier
.w
;
3734 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3735 switch (t
->operands
)
3738 if (!operand_type_match (overlap0
, i
.types
[0]))
3742 /* xchg %eax, %eax is a special case. It is an aliase for nop
3743 only in 32bit mode and we can use opcode 0x90. In 64bit
3744 mode, we can't use 0x90 for xchg %eax, %eax since it should
3745 zero-extend %eax to %rax. */
3746 if (flag_code
== CODE_64BIT
3747 && t
->base_opcode
== 0x90
3748 && operand_type_equal (&i
.types
[0], &acc32
)
3749 && operand_type_equal (&i
.types
[1], &acc32
))
3753 /* If we swap operand in encoding, we either match
3754 the next one or reverse direction of operands. */
3755 if (t
->opcode_modifier
.s
)
3757 else if (t
->opcode_modifier
.d
)
3762 /* If we swap operand in encoding, we match the next one. */
3763 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3767 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3768 if (!operand_type_match (overlap0
, i
.types
[0])
3769 || !operand_type_match (overlap1
, i
.types
[1])
3771 && !operand_type_register_match (overlap0
, i
.types
[0],
3773 overlap1
, i
.types
[1],
3776 /* Check if other direction is valid ... */
3777 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3781 /* Try reversing direction of operands. */
3782 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3783 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3784 if (!operand_type_match (overlap0
, i
.types
[0])
3785 || !operand_type_match (overlap1
, i
.types
[1])
3787 && !operand_type_register_match (overlap0
,
3794 /* Does not match either direction. */
3797 /* found_reverse_match holds which of D or FloatDR
3799 if (t
->opcode_modifier
.d
)
3800 found_reverse_match
= Opcode_D
;
3801 else if (t
->opcode_modifier
.floatd
)
3802 found_reverse_match
= Opcode_FloatD
;
3804 found_reverse_match
= 0;
3805 if (t
->opcode_modifier
.floatr
)
3806 found_reverse_match
|= Opcode_FloatR
;
3810 /* Found a forward 2 operand match here. */
3811 switch (t
->operands
)
3814 overlap4
= operand_type_and (i
.types
[4],
3817 overlap3
= operand_type_and (i
.types
[3],
3820 overlap2
= operand_type_and (i
.types
[2],
3825 switch (t
->operands
)
3828 if (!operand_type_match (overlap4
, i
.types
[4])
3829 || !operand_type_register_match (overlap3
,
3837 if (!operand_type_match (overlap3
, i
.types
[3])
3839 && !operand_type_register_match (overlap2
,
3847 /* Here we make use of the fact that there are no
3848 reverse match 3 operand instructions, and all 3
3849 operand instructions only need to be checked for
3850 register consistency between operands 2 and 3. */
3851 if (!operand_type_match (overlap2
, i
.types
[2])
3853 && !operand_type_register_match (overlap1
,
3863 /* Found either forward/reverse 2, 3 or 4 operand match here:
3864 slip through to break. */
3866 if (!found_cpu_match
)
3868 found_reverse_match
= 0;
3872 /* We've found a match; break out of loop. */
3876 if (t
== current_templates
->end
)
3878 /* We found no match. */
3880 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3881 current_templates
->start
->name
);
3883 as_bad (_("suffix or operands invalid for `%s'"),
3884 current_templates
->start
->name
);
3888 if (!quiet_warnings
)
3891 && (i
.types
[0].bitfield
.jumpabsolute
3892 != operand_types
[0].bitfield
.jumpabsolute
))
3894 as_warn (_("indirect %s without `*'"), t
->name
);
3897 if (t
->opcode_modifier
.isprefix
3898 && t
->opcode_modifier
.ignoresize
)
3900 /* Warn them that a data or address size prefix doesn't
3901 affect assembly of the next line of code. */
3902 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3906 /* Copy the template we found. */
3909 if (addr_prefix_disp
!= -1)
3910 i
.tm
.operand_types
[addr_prefix_disp
]
3911 = operand_types
[addr_prefix_disp
];
3913 if (found_reverse_match
)
3915 /* If we found a reverse match we must alter the opcode
3916 direction bit. found_reverse_match holds bits to change
3917 (different for int & float insns). */
3919 i
.tm
.base_opcode
^= found_reverse_match
;
3921 i
.tm
.operand_types
[0] = operand_types
[1];
3922 i
.tm
.operand_types
[1] = operand_types
[0];
3931 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3932 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3934 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3936 as_bad (_("`%s' operand %d must use `%ses' segment"),
3942 /* There's only ever one segment override allowed per instruction.
3943 This instruction possibly has a legal segment override on the
3944 second operand, so copy the segment to where non-string
3945 instructions store it, allowing common code. */
3946 i
.seg
[0] = i
.seg
[1];
3948 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3950 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3952 as_bad (_("`%s' operand %d must use `%ses' segment"),
3963 process_suffix (void)
3965 /* If matched instruction specifies an explicit instruction mnemonic
3967 if (i
.tm
.opcode_modifier
.size16
)
3968 i
.suffix
= WORD_MNEM_SUFFIX
;
3969 else if (i
.tm
.opcode_modifier
.size32
)
3970 i
.suffix
= LONG_MNEM_SUFFIX
;
3971 else if (i
.tm
.opcode_modifier
.size64
)
3972 i
.suffix
= QWORD_MNEM_SUFFIX
;
3973 else if (i
.reg_operands
)
3975 /* If there's no instruction mnemonic suffix we try to invent one
3976 based on register operands. */
3979 /* We take i.suffix from the last register operand specified,
3980 Destination register type is more significant than source
3981 register type. crc32 in SSE4.2 prefers source register
3983 if (i
.tm
.base_opcode
== 0xf20f38f1)
3985 if (i
.types
[0].bitfield
.reg16
)
3986 i
.suffix
= WORD_MNEM_SUFFIX
;
3987 else if (i
.types
[0].bitfield
.reg32
)
3988 i
.suffix
= LONG_MNEM_SUFFIX
;
3989 else if (i
.types
[0].bitfield
.reg64
)
3990 i
.suffix
= QWORD_MNEM_SUFFIX
;
3992 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3994 if (i
.types
[0].bitfield
.reg8
)
3995 i
.suffix
= BYTE_MNEM_SUFFIX
;
4002 if (i
.tm
.base_opcode
== 0xf20f38f1
4003 || i
.tm
.base_opcode
== 0xf20f38f0)
4005 /* We have to know the operand size for crc32. */
4006 as_bad (_("ambiguous memory operand size for `%s`"),
4011 for (op
= i
.operands
; --op
>= 0;)
4012 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4014 if (i
.types
[op
].bitfield
.reg8
)
4016 i
.suffix
= BYTE_MNEM_SUFFIX
;
4019 else if (i
.types
[op
].bitfield
.reg16
)
4021 i
.suffix
= WORD_MNEM_SUFFIX
;
4024 else if (i
.types
[op
].bitfield
.reg32
)
4026 i
.suffix
= LONG_MNEM_SUFFIX
;
4029 else if (i
.types
[op
].bitfield
.reg64
)
4031 i
.suffix
= QWORD_MNEM_SUFFIX
;
4037 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4039 if (!check_byte_reg ())
4042 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4044 if (!check_long_reg ())
4047 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4050 && i
.tm
.opcode_modifier
.ignoresize
4051 && i
.tm
.opcode_modifier
.no_qsuf
)
4053 else if (!check_qword_reg ())
4056 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4058 if (!check_word_reg ())
4061 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4062 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4064 /* Skip if the instruction has x/y suffix. match_template
4065 should check if it is a valid suffix. */
4067 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4068 /* Do nothing if the instruction is going to ignore the prefix. */
4073 else if (i
.tm
.opcode_modifier
.defaultsize
4075 /* exclude fldenv/frstor/fsave/fstenv */
4076 && i
.tm
.opcode_modifier
.no_ssuf
)
4078 i
.suffix
= stackop_size
;
4080 else if (intel_syntax
4082 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4083 || i
.tm
.opcode_modifier
.jumpbyte
4084 || i
.tm
.opcode_modifier
.jumpintersegment
4085 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4086 && i
.tm
.extension_opcode
<= 3)))
4091 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4093 i
.suffix
= QWORD_MNEM_SUFFIX
;
4097 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4098 i
.suffix
= LONG_MNEM_SUFFIX
;
4101 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4102 i
.suffix
= WORD_MNEM_SUFFIX
;
4111 if (i
.tm
.opcode_modifier
.w
)
4113 as_bad (_("no instruction mnemonic suffix given and "
4114 "no register operands; can't size instruction"));
4120 unsigned int suffixes
;
4122 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4123 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4125 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4127 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4129 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4131 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4134 /* There are more than suffix matches. */
4135 if (i
.tm
.opcode_modifier
.w
4136 || ((suffixes
& (suffixes
- 1))
4137 && !i
.tm
.opcode_modifier
.defaultsize
4138 && !i
.tm
.opcode_modifier
.ignoresize
))
4140 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4146 /* Change the opcode based on the operand size given by i.suffix;
4147 We don't need to change things for byte insns. */
4150 && i
.suffix
!= BYTE_MNEM_SUFFIX
4151 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4152 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4154 /* It's not a byte, select word/dword operation. */
4155 if (i
.tm
.opcode_modifier
.w
)
4157 if (i
.tm
.opcode_modifier
.shortform
)
4158 i
.tm
.base_opcode
|= 8;
4160 i
.tm
.base_opcode
|= 1;
4163 /* Now select between word & dword operations via the operand
4164 size prefix, except for instructions that will ignore this
4166 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4168 /* The address size override prefix changes the size of the
4170 if ((flag_code
== CODE_32BIT
4171 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4172 || (flag_code
!= CODE_32BIT
4173 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4174 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4177 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4178 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4179 && !i
.tm
.opcode_modifier
.ignoresize
4180 && !i
.tm
.opcode_modifier
.floatmf
4181 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4182 || (flag_code
== CODE_64BIT
4183 && i
.tm
.opcode_modifier
.jumpbyte
)))
4185 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4187 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4188 prefix
= ADDR_PREFIX_OPCODE
;
4190 if (!add_prefix (prefix
))
4194 /* Set mode64 for an operand. */
4195 if (i
.suffix
== QWORD_MNEM_SUFFIX
4196 && flag_code
== CODE_64BIT
4197 && !i
.tm
.opcode_modifier
.norex64
)
4199 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4200 need rex64. cmpxchg8b is also a special case. */
4201 if (! (i
.operands
== 2
4202 && i
.tm
.base_opcode
== 0x90
4203 && i
.tm
.extension_opcode
== None
4204 && operand_type_equal (&i
.types
[0], &acc64
)
4205 && operand_type_equal (&i
.types
[1], &acc64
))
4206 && ! (i
.operands
== 1
4207 && i
.tm
.base_opcode
== 0xfc7
4208 && i
.tm
.extension_opcode
== 1
4209 && !operand_type_check (i
.types
[0], reg
)
4210 && operand_type_check (i
.types
[0], anymem
)))
4214 /* Size floating point instruction. */
4215 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4216 if (i
.tm
.opcode_modifier
.floatmf
)
4217 i
.tm
.base_opcode
^= 4;
4224 check_byte_reg (void)
4228 for (op
= i
.operands
; --op
>= 0;)
4230 /* If this is an eight bit register, it's OK. If it's the 16 or
4231 32 bit version of an eight bit register, we will just use the
4232 low portion, and that's OK too. */
4233 if (i
.types
[op
].bitfield
.reg8
)
4236 /* Don't generate this warning if not needed. */
4237 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4240 /* crc32 doesn't generate this warning. */
4241 if (i
.tm
.base_opcode
== 0xf20f38f0)
4244 if ((i
.types
[op
].bitfield
.reg16
4245 || i
.types
[op
].bitfield
.reg32
4246 || i
.types
[op
].bitfield
.reg64
)
4247 && i
.op
[op
].regs
->reg_num
< 4)
4249 /* Prohibit these changes in the 64bit mode, since the
4250 lowering is more complicated. */
4251 if (flag_code
== CODE_64BIT
4252 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4254 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4255 register_prefix
, i
.op
[op
].regs
->reg_name
,
4259 #if REGISTER_WARNINGS
4261 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4262 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4264 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4265 ? REGNAM_AL
- REGNAM_AX
4266 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4268 i
.op
[op
].regs
->reg_name
,
4273 /* Any other register is bad. */
4274 if (i
.types
[op
].bitfield
.reg16
4275 || i
.types
[op
].bitfield
.reg32
4276 || i
.types
[op
].bitfield
.reg64
4277 || i
.types
[op
].bitfield
.regmmx
4278 || i
.types
[op
].bitfield
.regxmm
4279 || i
.types
[op
].bitfield
.regymm
4280 || i
.types
[op
].bitfield
.sreg2
4281 || i
.types
[op
].bitfield
.sreg3
4282 || i
.types
[op
].bitfield
.control
4283 || i
.types
[op
].bitfield
.debug
4284 || i
.types
[op
].bitfield
.test
4285 || i
.types
[op
].bitfield
.floatreg
4286 || i
.types
[op
].bitfield
.floatacc
)
4288 as_bad (_("`%s%s' not allowed with `%s%c'"),
4290 i
.op
[op
].regs
->reg_name
,
4300 check_long_reg (void)
4304 for (op
= i
.operands
; --op
>= 0;)
4305 /* Reject eight bit registers, except where the template requires
4306 them. (eg. movzb) */
4307 if (i
.types
[op
].bitfield
.reg8
4308 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4309 || i
.tm
.operand_types
[op
].bitfield
.reg32
4310 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4312 as_bad (_("`%s%s' not allowed with `%s%c'"),
4314 i
.op
[op
].regs
->reg_name
,
4319 /* Warn if the e prefix on a general reg is missing. */
4320 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4321 && i
.types
[op
].bitfield
.reg16
4322 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4323 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4325 /* Prohibit these changes in the 64bit mode, since the
4326 lowering is more complicated. */
4327 if (flag_code
== CODE_64BIT
)
4329 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4330 register_prefix
, i
.op
[op
].regs
->reg_name
,
4334 #if REGISTER_WARNINGS
4336 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4338 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4340 i
.op
[op
].regs
->reg_name
,
4344 /* Warn if the r prefix on a general reg is missing. */
4345 else if (i
.types
[op
].bitfield
.reg64
4346 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4347 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4350 && i
.tm
.opcode_modifier
.toqword
4351 && !i
.types
[0].bitfield
.regxmm
)
4353 /* Convert to QWORD. We want REX byte. */
4354 i
.suffix
= QWORD_MNEM_SUFFIX
;
4358 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4359 register_prefix
, i
.op
[op
].regs
->reg_name
,
4368 check_qword_reg (void)
4372 for (op
= i
.operands
; --op
>= 0; )
4373 /* Reject eight bit registers, except where the template requires
4374 them. (eg. movzb) */
4375 if (i
.types
[op
].bitfield
.reg8
4376 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4377 || i
.tm
.operand_types
[op
].bitfield
.reg32
4378 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4380 as_bad (_("`%s%s' not allowed with `%s%c'"),
4382 i
.op
[op
].regs
->reg_name
,
4387 /* Warn if the e prefix on a general reg is missing. */
4388 else if ((i
.types
[op
].bitfield
.reg16
4389 || i
.types
[op
].bitfield
.reg32
)
4390 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4391 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4393 /* Prohibit these changes in the 64bit mode, since the
4394 lowering is more complicated. */
4396 && i
.tm
.opcode_modifier
.todword
4397 && !i
.types
[0].bitfield
.regxmm
)
4399 /* Convert to DWORD. We don't want REX byte. */
4400 i
.suffix
= LONG_MNEM_SUFFIX
;
4404 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4405 register_prefix
, i
.op
[op
].regs
->reg_name
,
4414 check_word_reg (void)
4417 for (op
= i
.operands
; --op
>= 0;)
4418 /* Reject eight bit registers, except where the template requires
4419 them. (eg. movzb) */
4420 if (i
.types
[op
].bitfield
.reg8
4421 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4422 || i
.tm
.operand_types
[op
].bitfield
.reg32
4423 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4425 as_bad (_("`%s%s' not allowed with `%s%c'"),
4427 i
.op
[op
].regs
->reg_name
,
4432 /* Warn if the e prefix on a general reg is present. */
4433 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4434 && i
.types
[op
].bitfield
.reg32
4435 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4436 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4438 /* Prohibit these changes in the 64bit mode, since the
4439 lowering is more complicated. */
4440 if (flag_code
== CODE_64BIT
)
4442 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4443 register_prefix
, i
.op
[op
].regs
->reg_name
,
4448 #if REGISTER_WARNINGS
4449 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4451 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4453 i
.op
[op
].regs
->reg_name
,
4461 update_imm (unsigned int j
)
4463 i386_operand_type overlap
;
4465 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4466 if ((overlap
.bitfield
.imm8
4467 || overlap
.bitfield
.imm8s
4468 || overlap
.bitfield
.imm16
4469 || overlap
.bitfield
.imm32
4470 || overlap
.bitfield
.imm32s
4471 || overlap
.bitfield
.imm64
)
4472 && !operand_type_equal (&overlap
, &imm8
)
4473 && !operand_type_equal (&overlap
, &imm8s
)
4474 && !operand_type_equal (&overlap
, &imm16
)
4475 && !operand_type_equal (&overlap
, &imm32
)
4476 && !operand_type_equal (&overlap
, &imm32s
)
4477 && !operand_type_equal (&overlap
, &imm64
))
4481 i386_operand_type temp
;
4483 operand_type_set (&temp
, 0);
4484 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4486 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4487 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4489 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4490 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4491 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4493 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4494 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4497 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4500 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4501 || operand_type_equal (&overlap
, &imm16_32
)
4502 || operand_type_equal (&overlap
, &imm16_32s
))
4504 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4509 if (!operand_type_equal (&overlap
, &imm8
)
4510 && !operand_type_equal (&overlap
, &imm8s
)
4511 && !operand_type_equal (&overlap
, &imm16
)
4512 && !operand_type_equal (&overlap
, &imm32
)
4513 && !operand_type_equal (&overlap
, &imm32s
)
4514 && !operand_type_equal (&overlap
, &imm64
))
4516 as_bad (_("no instruction mnemonic suffix given; "
4517 "can't determine immediate size"));
4521 i
.types
[j
] = overlap
;
4531 for (j
= 0; j
< 2; j
++)
4532 if (update_imm (j
) == 0)
4535 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4536 assert (operand_type_check (i
.types
[2], imm
) == 0);
4544 i
.drex
.modrm_reg
= 0;
4545 i
.drex
.modrm_regmem
= 0;
4547 /* SSE5 4 operand instructions must have the destination the same as
4548 one of the inputs. Figure out the destination register and cache
4549 it away in the drex field, and remember which fields to use for
4551 if (i
.tm
.opcode_modifier
.drex
4552 && i
.tm
.opcode_modifier
.drexv
4555 i
.tm
.extension_opcode
= None
;
4557 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4558 if (i
.types
[0].bitfield
.regxmm
!= 0
4559 && i
.types
[1].bitfield
.regxmm
!= 0
4560 && i
.types
[2].bitfield
.regxmm
!= 0
4561 && i
.types
[3].bitfield
.regxmm
!= 0
4562 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4563 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4565 /* Clear the arguments that are stored in drex. */
4566 operand_type_set (&i
.types
[0], 0);
4567 operand_type_set (&i
.types
[3], 0);
4568 i
.reg_operands
-= 2;
4570 /* There are two different ways to encode a 4 operand
4571 instruction with all registers that uses OC1 set to
4572 0 or 1. Favor setting OC1 to 0 since this mimics the
4573 actions of other SSE5 assemblers. Use modrm encoding 2
4574 for register/register. Include the high order bit that
4575 is normally stored in the REX byte in the register
4577 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4578 i
.drex
.modrm_reg
= 2;
4579 i
.drex
.modrm_regmem
= 1;
4580 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4581 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4584 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4585 else if (i
.types
[0].bitfield
.regxmm
!= 0
4586 && i
.types
[1].bitfield
.regxmm
!= 0
4587 && (i
.types
[2].bitfield
.regxmm
4588 || operand_type_check (i
.types
[2], anymem
))
4589 && i
.types
[3].bitfield
.regxmm
!= 0
4590 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4591 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4593 /* clear the arguments that are stored in drex */
4594 operand_type_set (&i
.types
[0], 0);
4595 operand_type_set (&i
.types
[3], 0);
4596 i
.reg_operands
-= 2;
4598 /* Specify the modrm encoding for memory addressing. Include
4599 the high order bit that is normally stored in the REX byte
4600 in the register field. */
4601 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4602 i
.drex
.modrm_reg
= 1;
4603 i
.drex
.modrm_regmem
= 2;
4604 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4605 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4608 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4609 else if (i
.types
[0].bitfield
.regxmm
!= 0
4610 && operand_type_check (i
.types
[1], anymem
) != 0
4611 && i
.types
[2].bitfield
.regxmm
!= 0
4612 && i
.types
[3].bitfield
.regxmm
!= 0
4613 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4614 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4616 /* Clear the arguments that are stored in drex. */
4617 operand_type_set (&i
.types
[0], 0);
4618 operand_type_set (&i
.types
[3], 0);
4619 i
.reg_operands
-= 2;
4621 /* Specify the modrm encoding for memory addressing. Include
4622 the high order bit that is normally stored in the REX byte
4623 in the register field. */
4624 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4625 i
.drex
.modrm_reg
= 2;
4626 i
.drex
.modrm_regmem
= 1;
4627 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4628 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4631 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4632 else if (i
.types
[0].bitfield
.regxmm
!= 0
4633 && i
.types
[1].bitfield
.regxmm
!= 0
4634 && i
.types
[2].bitfield
.regxmm
!= 0
4635 && i
.types
[3].bitfield
.regxmm
!= 0
4636 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4637 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4639 /* clear the arguments that are stored in drex */
4640 operand_type_set (&i
.types
[2], 0);
4641 operand_type_set (&i
.types
[3], 0);
4642 i
.reg_operands
-= 2;
4644 /* There are two different ways to encode a 4 operand
4645 instruction with all registers that uses OC1 set to
4646 0 or 1. Favor setting OC1 to 0 since this mimics the
4647 actions of other SSE5 assemblers. Use modrm encoding
4648 2 for register/register. Include the high order bit that
4649 is normally stored in the REX byte in the register
4651 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4652 i
.drex
.modrm_reg
= 1;
4653 i
.drex
.modrm_regmem
= 0;
4655 /* Remember the register, including the upper bits */
4656 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4657 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4660 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4661 else if (i
.types
[0].bitfield
.regxmm
!= 0
4662 && (i
.types
[1].bitfield
.regxmm
4663 || operand_type_check (i
.types
[1], anymem
))
4664 && i
.types
[2].bitfield
.regxmm
!= 0
4665 && i
.types
[3].bitfield
.regxmm
!= 0
4666 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4667 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4669 /* Clear the arguments that are stored in drex. */
4670 operand_type_set (&i
.types
[2], 0);
4671 operand_type_set (&i
.types
[3], 0);
4672 i
.reg_operands
-= 2;
4674 /* Specify the modrm encoding and remember the register
4675 including the bits normally stored in the REX byte. */
4676 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4677 i
.drex
.modrm_reg
= 0;
4678 i
.drex
.modrm_regmem
= 1;
4679 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4680 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4683 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4684 else if (operand_type_check (i
.types
[0], anymem
) != 0
4685 && i
.types
[1].bitfield
.regxmm
!= 0
4686 && i
.types
[2].bitfield
.regxmm
!= 0
4687 && i
.types
[3].bitfield
.regxmm
!= 0
4688 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4689 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4691 /* clear the arguments that are stored in drex */
4692 operand_type_set (&i
.types
[2], 0);
4693 operand_type_set (&i
.types
[3], 0);
4694 i
.reg_operands
-= 2;
4696 /* Specify the modrm encoding and remember the register
4697 including the bits normally stored in the REX byte. */
4698 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4699 i
.drex
.modrm_reg
= 1;
4700 i
.drex
.modrm_regmem
= 0;
4701 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4702 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4706 as_bad (_("Incorrect operands for the '%s' instruction"),
4710 /* SSE5 instructions with the DREX byte where the only memory operand
4711 is in the 2nd argument, and the first and last xmm register must
4712 match, and is encoded in the DREX byte. */
4713 else if (i
.tm
.opcode_modifier
.drex
4714 && !i
.tm
.opcode_modifier
.drexv
4717 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4718 if (i
.types
[0].bitfield
.regxmm
!= 0
4719 && (i
.types
[1].bitfield
.regxmm
4720 || operand_type_check(i
.types
[1], anymem
))
4721 && i
.types
[2].bitfield
.regxmm
!= 0
4722 && i
.types
[3].bitfield
.regxmm
!= 0
4723 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4724 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4726 /* clear the arguments that are stored in drex */
4727 operand_type_set (&i
.types
[0], 0);
4728 operand_type_set (&i
.types
[3], 0);
4729 i
.reg_operands
-= 2;
4731 /* Specify the modrm encoding and remember the register
4732 including the high bit normally stored in the REX
4734 i
.drex
.modrm_reg
= 2;
4735 i
.drex
.modrm_regmem
= 1;
4736 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4737 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4741 as_bad (_("Incorrect operands for the '%s' instruction"),
4745 /* SSE5 3 operand instructions that the result is a register, being
4746 either operand can be a memory operand, using OC0 to note which
4747 one is the memory. */
4748 else if (i
.tm
.opcode_modifier
.drex
4749 && i
.tm
.opcode_modifier
.drexv
4752 i
.tm
.extension_opcode
= None
;
4754 /* Case 1: 3 operand insn, src1 = register. */
4755 if (i
.types
[0].bitfield
.regxmm
!= 0
4756 && i
.types
[1].bitfield
.regxmm
!= 0
4757 && i
.types
[2].bitfield
.regxmm
!= 0)
4759 /* Clear the arguments that are stored in drex. */
4760 operand_type_set (&i
.types
[2], 0);
4763 /* Specify the modrm encoding and remember the register
4764 including the high bit normally stored in the REX byte. */
4765 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4766 i
.drex
.modrm_reg
= 1;
4767 i
.drex
.modrm_regmem
= 0;
4768 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4769 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4772 /* Case 2: 3 operand insn, src1 = memory. */
4773 else if (operand_type_check (i
.types
[0], anymem
) != 0
4774 && i
.types
[1].bitfield
.regxmm
!= 0
4775 && i
.types
[2].bitfield
.regxmm
!= 0)
4777 /* Clear the arguments that are stored in drex. */
4778 operand_type_set (&i
.types
[2], 0);
4781 /* Specify the modrm encoding and remember the register
4782 including the high bit normally stored in the REX
4784 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4785 i
.drex
.modrm_reg
= 1;
4786 i
.drex
.modrm_regmem
= 0;
4787 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4788 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4791 /* Case 3: 3 operand insn, src2 = memory. */
4792 else if (i
.types
[0].bitfield
.regxmm
!= 0
4793 && operand_type_check (i
.types
[1], anymem
) != 0
4794 && i
.types
[2].bitfield
.regxmm
!= 0)
4796 /* Clear the arguments that are stored in drex. */
4797 operand_type_set (&i
.types
[2], 0);
4800 /* Specify the modrm encoding and remember the register
4801 including the high bit normally stored in the REX byte. */
4802 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4803 i
.drex
.modrm_reg
= 0;
4804 i
.drex
.modrm_regmem
= 1;
4805 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4806 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4810 as_bad (_("Incorrect operands for the '%s' instruction"),
4814 /* SSE5 4 operand instructions that are the comparison instructions
4815 where the first operand is the immediate value of the comparison
4817 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4819 /* Case 1: 4 operand insn, src1 = reg/memory. */
4820 if (operand_type_check (i
.types
[0], imm
) != 0
4821 && (i
.types
[1].bitfield
.regxmm
4822 || operand_type_check (i
.types
[1], anymem
))
4823 && i
.types
[2].bitfield
.regxmm
!= 0
4824 && i
.types
[3].bitfield
.regxmm
!= 0)
4826 /* clear the arguments that are stored in drex */
4827 operand_type_set (&i
.types
[3], 0);
4830 /* Specify the modrm encoding and remember the register
4831 including the high bit normally stored in the REX byte. */
4832 i
.drex
.modrm_reg
= 2;
4833 i
.drex
.modrm_regmem
= 1;
4834 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4835 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4838 /* Case 2: 3 operand insn with ImmExt that places the
4839 opcode_extension as an immediate argument. This is used for
4840 all of the varients of comparison that supplies the appropriate
4841 value as part of the instruction. */
4842 else if ((i
.types
[0].bitfield
.regxmm
4843 || operand_type_check (i
.types
[0], anymem
))
4844 && i
.types
[1].bitfield
.regxmm
!= 0
4845 && i
.types
[2].bitfield
.regxmm
!= 0
4846 && operand_type_check (i
.types
[3], imm
) != 0)
4848 /* clear the arguments that are stored in drex */
4849 operand_type_set (&i
.types
[2], 0);
4852 /* Specify the modrm encoding and remember the register
4853 including the high bit normally stored in the REX byte. */
4854 i
.drex
.modrm_reg
= 1;
4855 i
.drex
.modrm_regmem
= 0;
4856 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4857 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4861 as_bad (_("Incorrect operands for the '%s' instruction"),
4865 else if (i
.tm
.opcode_modifier
.drex
4866 || i
.tm
.opcode_modifier
.drexv
4867 || i
.tm
.opcode_modifier
.drexc
)
4868 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4872 bad_implicit_operand (int xmm
)
4874 const char *reg
= xmm
? "xmm0" : "ymm0";
4876 as_bad (_("the last operand of `%s' must be `%s%s'"),
4877 i
.tm
.name
, register_prefix
, reg
);
4879 as_bad (_("the first operand of `%s' must be `%s%s'"),
4880 i
.tm
.name
, register_prefix
, reg
);
4885 process_operands (void)
4887 /* Default segment register this instruction will use for memory
4888 accesses. 0 means unknown. This is only for optimizing out
4889 unnecessary segment overrides. */
4890 const seg_entry
*default_seg
= 0;
4892 /* Handle all of the DREX munging that SSE5 needs. */
4893 if (i
.tm
.opcode_modifier
.drex
4894 || i
.tm
.opcode_modifier
.drexv
4895 || i
.tm
.opcode_modifier
.drexc
)
4898 if (i
.tm
.opcode_modifier
.sse2avx
4899 && (i
.tm
.opcode_modifier
.vexnds
4900 || i
.tm
.opcode_modifier
.vexndd
))
4902 unsigned int dup
= i
.operands
;
4903 unsigned int dest
= dup
- 1;
4906 /* The destination must be an xmm register. */
4907 assert (i
.reg_operands
4908 && MAX_OPERANDS
> dup
4909 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4911 if (i
.tm
.opcode_modifier
.firstxmm0
)
4913 /* The first operand is implicit and must be xmm0. */
4914 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4915 if (i
.op
[0].regs
->reg_num
!= 0)
4916 return bad_implicit_operand (1);
4918 if (i
.tm
.opcode_modifier
.vex3sources
)
4920 /* Keep xmm0 for instructions with VEX prefix and 3
4926 /* We remove the first xmm0 and keep the number of
4927 operands unchanged, which in fact duplicates the
4929 for (j
= 1; j
< i
.operands
; j
++)
4931 i
.op
[j
- 1] = i
.op
[j
];
4932 i
.types
[j
- 1] = i
.types
[j
];
4933 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4937 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4939 assert ((MAX_OPERANDS
- 1) > dup
4940 && i
.tm
.opcode_modifier
.vex3sources
);
4942 /* Add the implicit xmm0 for instructions with VEX prefix
4944 for (j
= i
.operands
; j
> 0; j
--)
4946 i
.op
[j
] = i
.op
[j
- 1];
4947 i
.types
[j
] = i
.types
[j
- 1];
4948 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4951 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4952 i
.types
[0] = regxmm
;
4953 i
.tm
.operand_types
[0] = regxmm
;
4956 i
.reg_operands
+= 2;
4961 i
.op
[dup
] = i
.op
[dest
];
4962 i
.types
[dup
] = i
.types
[dest
];
4963 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4972 i
.op
[dup
] = i
.op
[dest
];
4973 i
.types
[dup
] = i
.types
[dest
];
4974 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4977 if (i
.tm
.opcode_modifier
.immext
)
4980 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4984 /* The first operand is implicit and must be xmm0/ymm0. */
4985 assert (i
.reg_operands
4986 && (operand_type_equal (&i
.types
[0], ®xmm
)
4987 || operand_type_equal (&i
.types
[0], ®ymm
)));
4988 if (i
.op
[0].regs
->reg_num
!= 0)
4989 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4991 for (j
= 1; j
< i
.operands
; j
++)
4993 i
.op
[j
- 1] = i
.op
[j
];
4994 i
.types
[j
- 1] = i
.types
[j
];
4996 /* We need to adjust fields in i.tm since they are used by
4997 build_modrm_byte. */
4998 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5005 else if (i
.tm
.opcode_modifier
.regkludge
)
5007 /* The imul $imm, %reg instruction is converted into
5008 imul $imm, %reg, %reg, and the clr %reg instruction
5009 is converted into xor %reg, %reg. */
5011 unsigned int first_reg_op
;
5013 if (operand_type_check (i
.types
[0], reg
))
5017 /* Pretend we saw the extra register operand. */
5018 assert (i
.reg_operands
== 1
5019 && i
.op
[first_reg_op
+ 1].regs
== 0);
5020 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5021 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5026 if (i
.tm
.opcode_modifier
.shortform
)
5028 if (i
.types
[0].bitfield
.sreg2
5029 || i
.types
[0].bitfield
.sreg3
)
5031 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5032 && i
.op
[0].regs
->reg_num
== 1)
5034 as_bad (_("you can't `pop %scs'"), register_prefix
);
5037 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5038 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5043 /* The register or float register operand is in operand
5047 if (i
.types
[0].bitfield
.floatreg
5048 || operand_type_check (i
.types
[0], reg
))
5052 /* Register goes in low 3 bits of opcode. */
5053 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5054 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5056 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5058 /* Warn about some common errors, but press on regardless.
5059 The first case can be generated by gcc (<= 2.8.1). */
5060 if (i
.operands
== 2)
5062 /* Reversed arguments on faddp, fsubp, etc. */
5063 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5064 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5065 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5069 /* Extraneous `l' suffix on fp insn. */
5070 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5071 register_prefix
, i
.op
[0].regs
->reg_name
);
5076 else if (i
.tm
.opcode_modifier
.modrm
)
5078 /* The opcode is completed (modulo i.tm.extension_opcode which
5079 must be put into the modrm byte). Now, we make the modrm and
5080 index base bytes based on all the info we've collected. */
5082 default_seg
= build_modrm_byte ();
5084 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5088 else if (i
.tm
.opcode_modifier
.isstring
)
5090 /* For the string instructions that allow a segment override
5091 on one of their operands, the default segment is ds. */
5095 if (i
.tm
.base_opcode
== 0x8d /* lea */
5098 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5100 /* If a segment was explicitly specified, and the specified segment
5101 is not the default, use an opcode prefix to select it. If we
5102 never figured out what the default segment is, then default_seg
5103 will be zero at this point, and the specified segment prefix will
5105 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5107 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5113 static const seg_entry
*
5114 build_modrm_byte (void)
5116 const seg_entry
*default_seg
= 0;
5117 unsigned int source
, dest
;
5120 /* The first operand of instructions with VEX prefix and 3 sources
5121 must be VEX_Imm4. */
5122 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5125 unsigned int nds
, reg
;
5127 dest
= i
.operands
- 1;
5132 /* This instruction must have 4 operands: 4 register operands
5133 or 3 register operands plus 1 memory operand. It must have
5134 VexNDS and VexImmExt. */
5135 assert (i
.operands
== 4
5136 && (i
.reg_operands
== 4
5137 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5138 && i
.tm
.opcode_modifier
.vexnds
5139 && i
.tm
.opcode_modifier
.veximmext
5140 && (operand_type_equal (&i
.tm
.operand_types
[dest
],
5142 || operand_type_equal (&i
.tm
.operand_types
[dest
],
5144 && (operand_type_equal (&i
.tm
.operand_types
[nds
],
5146 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5148 && (operand_type_equal (&i
.tm
.operand_types
[reg
],
5150 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5153 /* Generate an 8bit immediate operand to encode the register
5155 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5156 i
.op
[i
.operands
].imms
= exp
;
5157 i
.types
[i
.operands
] = imm8
;
5159 exp
->X_op
= O_constant
;
5161 = ((i
.op
[0].regs
->reg_num
5162 + ((i
.op
[0].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5164 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5169 /* SSE5 4 operand instructions are encoded in such a way that one of
5170 the inputs must match the destination register. Process_drex hides
5171 the 3rd argument in the drex field, so that by the time we get
5172 here, it looks to GAS as if this is a 2 operand instruction. */
5173 if ((i
.tm
.opcode_modifier
.drex
5174 || i
.tm
.opcode_modifier
.drexv
5175 || i
.tm
.opcode_modifier
.drexc
)
5176 && i
.reg_operands
== 2)
5178 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5179 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5181 i
.rm
.reg
= reg
->reg_num
;
5182 i
.rm
.regmem
= regmem
->reg_num
;
5184 if ((reg
->reg_flags
& RegRex
) != 0)
5186 if ((regmem
->reg_flags
& RegRex
) != 0)
5190 /* i.reg_operands MUST be the number of real register operands;
5191 implicit registers do not count. If there are 3 register
5192 operands, it must be a instruction with VexNDS. For a
5193 instruction with VexNDD, the destination register is encoded
5194 in VEX prefix. If there are 4 register operands, it must be
5195 a instruction with VEX prefix and 3 sources. */
5196 else if (i
.mem_operands
== 0
5197 && ((i
.reg_operands
== 2
5198 && !i
.tm
.opcode_modifier
.vexndd
)
5199 || (i
.reg_operands
== 3
5200 && i
.tm
.opcode_modifier
.vexnds
)
5201 || (i
.reg_operands
== 4 && vex_3_sources
)))
5209 /* When there are 3 operands, one of them may be immediate,
5210 which may be the first or the last operand. Otherwise,
5211 the first operand must be shift count register (cl) or it
5212 is an instruction with VexNDS. */
5213 assert (i
.imm_operands
== 1
5214 || (i
.imm_operands
== 0
5215 && (i
.tm
.opcode_modifier
.vexnds
5216 || i
.types
[0].bitfield
.shiftcount
)));
5217 if (operand_type_check (i
.types
[0], imm
)
5218 || i
.types
[0].bitfield
.shiftcount
)
5224 /* When there are 4 operands, the first two must be 8bit
5225 immediate operands. The source operand will be the 3rd
5228 For instructions with VexNDS, if the first operand
5229 an imm8, the source operand is the 2nd one. If the last
5230 operand is imm8, the source operand is the first one. */
5231 assert ((i
.imm_operands
== 2
5232 && i
.types
[0].bitfield
.imm8
5233 && i
.types
[1].bitfield
.imm8
)
5234 || (i
.tm
.opcode_modifier
.vexnds
5235 && i
.imm_operands
== 1
5236 && (i
.types
[0].bitfield
.imm8
5237 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5238 if (i
.tm
.opcode_modifier
.vexnds
)
5240 if (i
.types
[0].bitfield
.imm8
)
5258 if (i
.tm
.opcode_modifier
.vexnds
)
5260 /* For instructions with VexNDS, the register-only
5261 source operand must be XMM or YMM register. It is
5262 encoded in VEX prefix. We need to clear RegMem bit
5263 before calling operand_type_equal. */
5264 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5265 op
.bitfield
.regmem
= 0;
5266 if ((dest
+ 1) >= i
.operands
5267 || (!operand_type_equal (&op
, ®xmm
)
5268 && !operand_type_equal (&op
, ®ymm
)))
5270 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5276 /* One of the register operands will be encoded in the i.tm.reg
5277 field, the other in the combined i.tm.mode and i.tm.regmem
5278 fields. If no form of this instruction supports a memory
5279 destination operand, then we assume the source operand may
5280 sometimes be a memory operand and so we need to store the
5281 destination in the i.rm.reg field. */
5282 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5283 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5285 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5286 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5287 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5289 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5294 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5295 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5296 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5298 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5301 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5303 if (!i
.types
[0].bitfield
.control
5304 && !i
.types
[1].bitfield
.control
)
5306 i
.rex
&= ~(REX_R
| REX_B
);
5307 add_prefix (LOCK_PREFIX_OPCODE
);
5311 { /* If it's not 2 reg operands... */
5316 unsigned int fake_zero_displacement
= 0;
5319 /* This has been precalculated for SSE5 instructions
5320 that have a DREX field earlier in process_drex. */
5321 if (i
.tm
.opcode_modifier
.drex
5322 || i
.tm
.opcode_modifier
.drexv
5323 || i
.tm
.opcode_modifier
.drexc
)
5324 op
= i
.drex
.modrm_regmem
;
5327 for (op
= 0; op
< i
.operands
; op
++)
5328 if (operand_type_check (i
.types
[op
], anymem
))
5330 assert (op
< i
.operands
);
5335 if (i
.base_reg
== 0)
5338 if (!i
.disp_operands
)
5339 fake_zero_displacement
= 1;
5340 if (i
.index_reg
== 0)
5342 /* Operand is just <disp> */
5343 if (flag_code
== CODE_64BIT
)
5345 /* 64bit mode overwrites the 32bit absolute
5346 addressing by RIP relative addressing and
5347 absolute addressing is encoded by one of the
5348 redundant SIB forms. */
5349 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5350 i
.sib
.base
= NO_BASE_REGISTER
;
5351 i
.sib
.index
= NO_INDEX_REGISTER
;
5352 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5353 ? disp32s
: disp32
);
5355 else if ((flag_code
== CODE_16BIT
)
5356 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5358 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5359 i
.types
[op
] = disp16
;
5363 i
.rm
.regmem
= NO_BASE_REGISTER
;
5364 i
.types
[op
] = disp32
;
5367 else /* !i.base_reg && i.index_reg */
5369 if (i
.index_reg
->reg_num
== RegEiz
5370 || i
.index_reg
->reg_num
== RegRiz
)
5371 i
.sib
.index
= NO_INDEX_REGISTER
;
5373 i
.sib
.index
= i
.index_reg
->reg_num
;
5374 i
.sib
.base
= NO_BASE_REGISTER
;
5375 i
.sib
.scale
= i
.log2_scale_factor
;
5376 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5377 i
.types
[op
].bitfield
.disp8
= 0;
5378 i
.types
[op
].bitfield
.disp16
= 0;
5379 i
.types
[op
].bitfield
.disp64
= 0;
5380 if (flag_code
!= CODE_64BIT
)
5382 /* Must be 32 bit */
5383 i
.types
[op
].bitfield
.disp32
= 1;
5384 i
.types
[op
].bitfield
.disp32s
= 0;
5388 i
.types
[op
].bitfield
.disp32
= 0;
5389 i
.types
[op
].bitfield
.disp32s
= 1;
5391 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5395 /* RIP addressing for 64bit mode. */
5396 else if (i
.base_reg
->reg_num
== RegRip
||
5397 i
.base_reg
->reg_num
== RegEip
)
5399 i
.rm
.regmem
= NO_BASE_REGISTER
;
5400 i
.types
[op
].bitfield
.disp8
= 0;
5401 i
.types
[op
].bitfield
.disp16
= 0;
5402 i
.types
[op
].bitfield
.disp32
= 0;
5403 i
.types
[op
].bitfield
.disp32s
= 1;
5404 i
.types
[op
].bitfield
.disp64
= 0;
5405 i
.flags
[op
] |= Operand_PCrel
;
5406 if (! i
.disp_operands
)
5407 fake_zero_displacement
= 1;
5409 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5411 switch (i
.base_reg
->reg_num
)
5414 if (i
.index_reg
== 0)
5416 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5417 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5421 if (i
.index_reg
== 0)
5424 if (operand_type_check (i
.types
[op
], disp
) == 0)
5426 /* fake (%bp) into 0(%bp) */
5427 i
.types
[op
].bitfield
.disp8
= 1;
5428 fake_zero_displacement
= 1;
5431 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5432 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5434 default: /* (%si) -> 4 or (%di) -> 5 */
5435 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5437 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5439 else /* i.base_reg and 32/64 bit mode */
5441 if (flag_code
== CODE_64BIT
5442 && operand_type_check (i
.types
[op
], disp
))
5444 i386_operand_type temp
;
5445 operand_type_set (&temp
, 0);
5446 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5448 if (i
.prefix
[ADDR_PREFIX
] == 0)
5449 i
.types
[op
].bitfield
.disp32s
= 1;
5451 i
.types
[op
].bitfield
.disp32
= 1;
5454 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5455 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5457 i
.sib
.base
= i
.base_reg
->reg_num
;
5458 /* x86-64 ignores REX prefix bit here to avoid decoder
5460 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5463 if (i
.disp_operands
== 0)
5465 fake_zero_displacement
= 1;
5466 i
.types
[op
].bitfield
.disp8
= 1;
5469 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5473 i
.sib
.scale
= i
.log2_scale_factor
;
5474 if (i
.index_reg
== 0)
5476 /* <disp>(%esp) becomes two byte modrm with no index
5477 register. We've already stored the code for esp
5478 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5479 Any base register besides %esp will not use the
5480 extra modrm byte. */
5481 i
.sib
.index
= NO_INDEX_REGISTER
;
5485 if (i
.index_reg
->reg_num
== RegEiz
5486 || i
.index_reg
->reg_num
== RegRiz
)
5487 i
.sib
.index
= NO_INDEX_REGISTER
;
5489 i
.sib
.index
= i
.index_reg
->reg_num
;
5490 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5491 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5496 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5497 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5500 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5503 if (fake_zero_displacement
)
5505 /* Fakes a zero displacement assuming that i.types[op]
5506 holds the correct displacement size. */
5509 assert (i
.op
[op
].disps
== 0);
5510 exp
= &disp_expressions
[i
.disp_operands
++];
5511 i
.op
[op
].disps
= exp
;
5512 exp
->X_op
= O_constant
;
5513 exp
->X_add_number
= 0;
5514 exp
->X_add_symbol
= (symbolS
*) 0;
5515 exp
->X_op_symbol
= (symbolS
*) 0;
5523 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5524 (if any) based on i.tm.extension_opcode. Again, we must be
5525 careful to make sure that segment/control/debug/test/MMX
5526 registers are coded into the i.rm.reg field. */
5531 /* This has been precalculated for SSE5 instructions
5532 that have a DREX field earlier in process_drex. */
5533 if (i
.tm
.opcode_modifier
.drex
5534 || i
.tm
.opcode_modifier
.drexv
5535 || i
.tm
.opcode_modifier
.drexc
)
5537 op
= i
.drex
.modrm_reg
;
5538 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5539 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5544 unsigned int vex_reg
= ~0;
5546 for (op
= 0; op
< i
.operands
; op
++)
5547 if (i
.types
[op
].bitfield
.reg8
5548 || i
.types
[op
].bitfield
.reg16
5549 || i
.types
[op
].bitfield
.reg32
5550 || i
.types
[op
].bitfield
.reg64
5551 || i
.types
[op
].bitfield
.regmmx
5552 || i
.types
[op
].bitfield
.regxmm
5553 || i
.types
[op
].bitfield
.regymm
5554 || i
.types
[op
].bitfield
.sreg2
5555 || i
.types
[op
].bitfield
.sreg3
5556 || i
.types
[op
].bitfield
.control
5557 || i
.types
[op
].bitfield
.debug
5558 || i
.types
[op
].bitfield
.test
)
5563 else if (i
.tm
.opcode_modifier
.vexnds
)
5565 /* For instructions with VexNDS, the register-only
5566 source operand is encoded in VEX prefix. */
5567 assert (mem
!= (unsigned int) ~0);
5572 assert (op
< i
.operands
);
5577 assert (vex_reg
< i
.operands
);
5580 else if (i
.tm
.opcode_modifier
.vexndd
)
5582 /* For instructions with VexNDD, there should be
5583 no memory operand and the register destination
5584 is encoded in VEX prefix. */
5585 assert (i
.mem_operands
== 0
5586 && (op
+ 2) == i
.operands
);
5590 assert (op
< i
.operands
);
5592 if (vex_reg
!= (unsigned int) ~0)
5594 assert (i
.reg_operands
== 2);
5596 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5598 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5601 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5604 /* If there is an extension opcode to put here, the
5605 register number must be put into the regmem field. */
5606 if (i
.tm
.extension_opcode
!= None
)
5608 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5609 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5614 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5615 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5620 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5621 must set it to 3 to indicate this is a register operand
5622 in the regmem field. */
5623 if (!i
.mem_operands
)
5627 /* Fill in i.rm.reg field with extension opcode (if any). */
5628 if (i
.tm
.extension_opcode
!= None
5629 && !(i
.tm
.opcode_modifier
.drex
5630 || i
.tm
.opcode_modifier
.drexv
5631 || i
.tm
.opcode_modifier
.drexc
))
5632 i
.rm
.reg
= i
.tm
.extension_opcode
;
5638 output_branch (void)
5643 relax_substateT subtype
;
5648 if (flag_code
== CODE_16BIT
)
5652 if (i
.prefix
[DATA_PREFIX
] != 0)
5658 /* Pentium4 branch hints. */
5659 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5660 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5665 if (i
.prefix
[REX_PREFIX
] != 0)
5671 if (i
.prefixes
!= 0 && !intel_syntax
)
5672 as_warn (_("skipping prefixes on this instruction"));
5674 /* It's always a symbol; End frag & setup for relax.
5675 Make sure there is enough room in this frag for the largest
5676 instruction we may generate in md_convert_frag. This is 2
5677 bytes for the opcode and room for the prefix and largest
5679 frag_grow (prefix
+ 2 + 4);
5680 /* Prefix and 1 opcode byte go in fr_fix. */
5681 p
= frag_more (prefix
+ 1);
5682 if (i
.prefix
[DATA_PREFIX
] != 0)
5683 *p
++ = DATA_PREFIX_OPCODE
;
5684 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5685 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5686 *p
++ = i
.prefix
[SEG_PREFIX
];
5687 if (i
.prefix
[REX_PREFIX
] != 0)
5688 *p
++ = i
.prefix
[REX_PREFIX
];
5689 *p
= i
.tm
.base_opcode
;
5691 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5692 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5693 else if (cpu_arch_flags
.bitfield
.cpui386
)
5694 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5696 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5699 sym
= i
.op
[0].disps
->X_add_symbol
;
5700 off
= i
.op
[0].disps
->X_add_number
;
5702 if (i
.op
[0].disps
->X_op
!= O_constant
5703 && i
.op
[0].disps
->X_op
!= O_symbol
)
5705 /* Handle complex expressions. */
5706 sym
= make_expr_symbol (i
.op
[0].disps
);
5710 /* 1 possible extra opcode + 4 byte displacement go in var part.
5711 Pass reloc in fr_var. */
5712 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5722 if (i
.tm
.opcode_modifier
.jumpbyte
)
5724 /* This is a loop or jecxz type instruction. */
5726 if (i
.prefix
[ADDR_PREFIX
] != 0)
5728 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5731 /* Pentium4 branch hints. */
5732 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5733 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5735 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5744 if (flag_code
== CODE_16BIT
)
5747 if (i
.prefix
[DATA_PREFIX
] != 0)
5749 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5759 if (i
.prefix
[REX_PREFIX
] != 0)
5761 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5765 if (i
.prefixes
!= 0 && !intel_syntax
)
5766 as_warn (_("skipping prefixes on this instruction"));
5768 p
= frag_more (1 + size
);
5769 *p
++ = i
.tm
.base_opcode
;
5771 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5772 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5774 /* All jumps handled here are signed, but don't use a signed limit
5775 check for 32 and 16 bit jumps as we want to allow wrap around at
5776 4G and 64k respectively. */
5778 fixP
->fx_signed
= 1;
5782 output_interseg_jump (void)
5790 if (flag_code
== CODE_16BIT
)
5794 if (i
.prefix
[DATA_PREFIX
] != 0)
5800 if (i
.prefix
[REX_PREFIX
] != 0)
5810 if (i
.prefixes
!= 0 && !intel_syntax
)
5811 as_warn (_("skipping prefixes on this instruction"));
5813 /* 1 opcode; 2 segment; offset */
5814 p
= frag_more (prefix
+ 1 + 2 + size
);
5816 if (i
.prefix
[DATA_PREFIX
] != 0)
5817 *p
++ = DATA_PREFIX_OPCODE
;
5819 if (i
.prefix
[REX_PREFIX
] != 0)
5820 *p
++ = i
.prefix
[REX_PREFIX
];
5822 *p
++ = i
.tm
.base_opcode
;
5823 if (i
.op
[1].imms
->X_op
== O_constant
)
5825 offsetT n
= i
.op
[1].imms
->X_add_number
;
5828 && !fits_in_unsigned_word (n
)
5829 && !fits_in_signed_word (n
))
5831 as_bad (_("16-bit jump out of range"));
5834 md_number_to_chars (p
, n
, size
);
5837 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5838 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5839 if (i
.op
[0].imms
->X_op
!= O_constant
)
5840 as_bad (_("can't handle non absolute segment in `%s'"),
5842 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5848 fragS
*insn_start_frag
;
5849 offsetT insn_start_off
;
5851 /* Tie dwarf2 debug info to the address at the start of the insn.
5852 We can't do this after the insn has been output as the current
5853 frag may have been closed off. eg. by frag_var. */
5854 dwarf2_emit_insn (0);
5856 insn_start_frag
= frag_now
;
5857 insn_start_off
= frag_now_fix ();
5860 if (i
.tm
.opcode_modifier
.jump
)
5862 else if (i
.tm
.opcode_modifier
.jumpbyte
5863 || i
.tm
.opcode_modifier
.jumpdword
)
5865 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5866 output_interseg_jump ();
5869 /* Output normal instructions here. */
5873 unsigned int prefix
;
5875 /* Since the VEX prefix contains the implicit prefix, we don't
5876 need the explicit prefix. */
5877 if (!i
.tm
.opcode_modifier
.vex
)
5879 switch (i
.tm
.opcode_length
)
5882 if (i
.tm
.base_opcode
& 0xff000000)
5884 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5889 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5891 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5892 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5895 if (prefix
!= REPE_PREFIX_OPCODE
5896 || (i
.prefix
[LOCKREP_PREFIX
]
5897 != REPE_PREFIX_OPCODE
))
5898 add_prefix (prefix
);
5901 add_prefix (prefix
);
5910 /* The prefix bytes. */
5911 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5913 FRAG_APPEND_1_CHAR (*q
);
5916 if (i
.tm
.opcode_modifier
.vex
)
5918 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5923 /* REX byte is encoded in VEX prefix. */
5927 FRAG_APPEND_1_CHAR (*q
);
5930 /* There should be no other prefixes for instructions
5935 /* Now the VEX prefix. */
5936 p
= frag_more (i
.vex
.length
);
5937 for (j
= 0; j
< i
.vex
.length
; j
++)
5938 p
[j
] = i
.vex
.bytes
[j
];
5941 /* Now the opcode; be careful about word order here! */
5942 if (i
.tm
.opcode_length
== 1)
5944 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5948 switch (i
.tm
.opcode_length
)
5952 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5962 /* Put out high byte first: can't use md_number_to_chars! */
5963 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5964 *p
= i
.tm
.base_opcode
& 0xff;
5966 /* On SSE5, encode the OC1 bit in the DREX field if this
5967 encoding has multiple formats. */
5968 if (i
.tm
.opcode_modifier
.drex
5969 && i
.tm
.opcode_modifier
.drexv
5970 && DREX_OC1 (i
.tm
.extension_opcode
))
5971 *p
|= DREX_OC1_MASK
;
5974 /* Now the modrm byte and sib byte (if present). */
5975 if (i
.tm
.opcode_modifier
.modrm
)
5977 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5980 /* If i.rm.regmem == ESP (4)
5981 && i.rm.mode != (Register mode)
5983 ==> need second modrm byte. */
5984 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5986 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5987 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5989 | i
.sib
.scale
<< 6));
5992 /* Write the DREX byte if needed. */
5993 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5996 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5998 /* Encode the OC0 bit if this encoding has multiple
6000 if ((i
.tm
.opcode_modifier
.drex
6001 || i
.tm
.opcode_modifier
.drexv
)
6002 && DREX_OC0 (i
.tm
.extension_opcode
))
6003 *p
|= DREX_OC0_MASK
;
6006 if (i
.disp_operands
)
6007 output_disp (insn_start_frag
, insn_start_off
);
6010 output_imm (insn_start_frag
, insn_start_off
);
6016 pi ("" /*line*/, &i
);
6018 #endif /* DEBUG386 */
6021 /* Return the size of the displacement operand N. */
6024 disp_size (unsigned int n
)
6027 if (i
.types
[n
].bitfield
.disp64
)
6029 else if (i
.types
[n
].bitfield
.disp8
)
6031 else if (i
.types
[n
].bitfield
.disp16
)
6036 /* Return the size of the immediate operand N. */
6039 imm_size (unsigned int n
)
6042 if (i
.types
[n
].bitfield
.imm64
)
6044 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6046 else if (i
.types
[n
].bitfield
.imm16
)
6052 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6057 for (n
= 0; n
< i
.operands
; n
++)
6059 if (operand_type_check (i
.types
[n
], disp
))
6061 if (i
.op
[n
].disps
->X_op
== O_constant
)
6063 int size
= disp_size (n
);
6066 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6068 p
= frag_more (size
);
6069 md_number_to_chars (p
, val
, size
);
6073 enum bfd_reloc_code_real reloc_type
;
6074 int size
= disp_size (n
);
6075 int sign
= i
.types
[n
].bitfield
.disp32s
;
6076 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6078 /* We can't have 8 bit displacement here. */
6079 assert (!i
.types
[n
].bitfield
.disp8
);
6081 /* The PC relative address is computed relative
6082 to the instruction boundary, so in case immediate
6083 fields follows, we need to adjust the value. */
6084 if (pcrel
&& i
.imm_operands
)
6089 for (n1
= 0; n1
< i
.operands
; n1
++)
6090 if (operand_type_check (i
.types
[n1
], imm
))
6092 /* Only one immediate is allowed for PC
6093 relative address. */
6096 i
.op
[n
].disps
->X_add_number
-= sz
;
6098 /* We should find the immediate. */
6102 p
= frag_more (size
);
6103 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6105 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6106 && (((reloc_type
== BFD_RELOC_32
6107 || reloc_type
== BFD_RELOC_X86_64_32S
6108 || (reloc_type
== BFD_RELOC_64
6110 && (i
.op
[n
].disps
->X_op
== O_symbol
6111 || (i
.op
[n
].disps
->X_op
== O_add
6112 && ((symbol_get_value_expression
6113 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6115 || reloc_type
== BFD_RELOC_32_PCREL
))
6119 if (insn_start_frag
== frag_now
)
6120 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6125 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6126 for (fr
= insn_start_frag
->fr_next
;
6127 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6129 add
+= p
- frag_now
->fr_literal
;
6134 reloc_type
= BFD_RELOC_386_GOTPC
;
6135 i
.op
[n
].imms
->X_add_number
+= add
;
6137 else if (reloc_type
== BFD_RELOC_64
)
6138 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6140 /* Don't do the adjustment for x86-64, as there
6141 the pcrel addressing is relative to the _next_
6142 insn, and that is taken care of in other code. */
6143 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6145 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6146 i
.op
[n
].disps
, pcrel
, reloc_type
);
6153 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6158 for (n
= 0; n
< i
.operands
; n
++)
6160 if (operand_type_check (i
.types
[n
], imm
))
6162 if (i
.op
[n
].imms
->X_op
== O_constant
)
6164 int size
= imm_size (n
);
6167 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6169 p
= frag_more (size
);
6170 md_number_to_chars (p
, val
, size
);
6174 /* Not absolute_section.
6175 Need a 32-bit fixup (don't support 8bit
6176 non-absolute imms). Try to support other
6178 enum bfd_reloc_code_real reloc_type
;
6179 int size
= imm_size (n
);
6182 if (i
.types
[n
].bitfield
.imm32s
6183 && (i
.suffix
== QWORD_MNEM_SUFFIX
6184 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6189 p
= frag_more (size
);
6190 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6192 /* This is tough to explain. We end up with this one if we
6193 * have operands that look like
6194 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6195 * obtain the absolute address of the GOT, and it is strongly
6196 * preferable from a performance point of view to avoid using
6197 * a runtime relocation for this. The actual sequence of
6198 * instructions often look something like:
6203 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6205 * The call and pop essentially return the absolute address
6206 * of the label .L66 and store it in %ebx. The linker itself
6207 * will ultimately change the first operand of the addl so
6208 * that %ebx points to the GOT, but to keep things simple, the
6209 * .o file must have this operand set so that it generates not
6210 * the absolute address of .L66, but the absolute address of
6211 * itself. This allows the linker itself simply treat a GOTPC
6212 * relocation as asking for a pcrel offset to the GOT to be
6213 * added in, and the addend of the relocation is stored in the
6214 * operand field for the instruction itself.
6216 * Our job here is to fix the operand so that it would add
6217 * the correct offset so that %ebx would point to itself. The
6218 * thing that is tricky is that .-.L66 will point to the
6219 * beginning of the instruction, so we need to further modify
6220 * the operand so that it will point to itself. There are
6221 * other cases where you have something like:
6223 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6225 * and here no correction would be required. Internally in
6226 * the assembler we treat operands of this form as not being
6227 * pcrel since the '.' is explicitly mentioned, and I wonder
6228 * whether it would simplify matters to do it this way. Who
6229 * knows. In earlier versions of the PIC patches, the
6230 * pcrel_adjust field was used to store the correction, but
6231 * since the expression is not pcrel, I felt it would be
6232 * confusing to do it this way. */
6234 if ((reloc_type
== BFD_RELOC_32
6235 || reloc_type
== BFD_RELOC_X86_64_32S
6236 || reloc_type
== BFD_RELOC_64
)
6238 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6239 && (i
.op
[n
].imms
->X_op
== O_symbol
6240 || (i
.op
[n
].imms
->X_op
== O_add
6241 && ((symbol_get_value_expression
6242 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6247 if (insn_start_frag
== frag_now
)
6248 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6253 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6254 for (fr
= insn_start_frag
->fr_next
;
6255 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6257 add
+= p
- frag_now
->fr_literal
;
6261 reloc_type
= BFD_RELOC_386_GOTPC
;
6263 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6265 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6266 i
.op
[n
].imms
->X_add_number
+= add
;
6268 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6269 i
.op
[n
].imms
, 0, reloc_type
);
6275 /* x86_cons_fix_new is called via the expression parsing code when a
6276 reloc is needed. We use this hook to get the correct .got reloc. */
6277 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6278 static int cons_sign
= -1;
6281 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6284 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6286 got_reloc
= NO_RELOC
;
6289 if (exp
->X_op
== O_secrel
)
6291 exp
->X_op
= O_symbol
;
6292 r
= BFD_RELOC_32_SECREL
;
6296 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6299 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6300 # define lex_got(reloc, adjust, types) NULL
6302 /* Parse operands of the form
6303 <symbol>@GOTOFF+<nnn>
6304 and similar .plt or .got references.
6306 If we find one, set up the correct relocation in RELOC and copy the
6307 input string, minus the `@GOTOFF' into a malloc'd buffer for
6308 parsing by the calling routine. Return this buffer, and if ADJUST
6309 is non-null set it to the length of the string we removed from the
6310 input line. Otherwise return NULL. */
6312 lex_got (enum bfd_reloc_code_real
*reloc
,
6314 i386_operand_type
*types
)
6316 /* Some of the relocations depend on the size of what field is to
6317 be relocated. But in our callers i386_immediate and i386_displacement
6318 we don't yet know the operand size (this will be set by insn
6319 matching). Hence we record the word32 relocation here,
6320 and adjust the reloc according to the real size in reloc(). */
6321 static const struct {
6323 const enum bfd_reloc_code_real rel
[2];
6324 const i386_operand_type types64
;
6327 BFD_RELOC_X86_64_PLTOFF64
},
6328 OPERAND_TYPE_IMM64
},
6329 { "PLT", { BFD_RELOC_386_PLT32
,
6330 BFD_RELOC_X86_64_PLT32
},
6331 OPERAND_TYPE_IMM32_32S_DISP32
},
6333 BFD_RELOC_X86_64_GOTPLT64
},
6334 OPERAND_TYPE_IMM64_DISP64
},
6335 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6336 BFD_RELOC_X86_64_GOTOFF64
},
6337 OPERAND_TYPE_IMM64_DISP64
},
6339 BFD_RELOC_X86_64_GOTPCREL
},
6340 OPERAND_TYPE_IMM32_32S_DISP32
},
6341 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6342 BFD_RELOC_X86_64_TLSGD
},
6343 OPERAND_TYPE_IMM32_32S_DISP32
},
6344 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6346 OPERAND_TYPE_NONE
},
6348 BFD_RELOC_X86_64_TLSLD
},
6349 OPERAND_TYPE_IMM32_32S_DISP32
},
6350 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6351 BFD_RELOC_X86_64_GOTTPOFF
},
6352 OPERAND_TYPE_IMM32_32S_DISP32
},
6353 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6354 BFD_RELOC_X86_64_TPOFF32
},
6355 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6356 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6358 OPERAND_TYPE_NONE
},
6359 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6360 BFD_RELOC_X86_64_DTPOFF32
},
6362 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6363 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6365 OPERAND_TYPE_NONE
},
6366 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6368 OPERAND_TYPE_NONE
},
6369 { "GOT", { BFD_RELOC_386_GOT32
,
6370 BFD_RELOC_X86_64_GOT32
},
6371 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6372 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6373 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6374 OPERAND_TYPE_IMM32_32S_DISP32
},
6375 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6376 BFD_RELOC_X86_64_TLSDESC_CALL
},
6377 OPERAND_TYPE_IMM32_32S_DISP32
},
6385 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6386 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6389 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6393 len
= strlen (gotrel
[j
].str
);
6394 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6396 if (gotrel
[j
].rel
[object_64bit
] != 0)
6399 char *tmpbuf
, *past_reloc
;
6401 *reloc
= gotrel
[j
].rel
[object_64bit
];
6407 if (flag_code
!= CODE_64BIT
)
6409 types
->bitfield
.imm32
= 1;
6410 types
->bitfield
.disp32
= 1;
6413 *types
= gotrel
[j
].types64
;
6416 if (GOT_symbol
== NULL
)
6417 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6419 /* The length of the first part of our input line. */
6420 first
= cp
- input_line_pointer
;
6422 /* The second part goes from after the reloc token until
6423 (and including) an end_of_line char or comma. */
6424 past_reloc
= cp
+ 1 + len
;
6426 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6428 second
= cp
+ 1 - past_reloc
;
6430 /* Allocate and copy string. The trailing NUL shouldn't
6431 be necessary, but be safe. */
6432 tmpbuf
= xmalloc (first
+ second
+ 2);
6433 memcpy (tmpbuf
, input_line_pointer
, first
);
6434 if (second
!= 0 && *past_reloc
!= ' ')
6435 /* Replace the relocation token with ' ', so that
6436 errors like foo@GOTOFF1 will be detected. */
6437 tmpbuf
[first
++] = ' ';
6438 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6439 tmpbuf
[first
+ second
] = '\0';
6443 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6444 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6449 /* Might be a symbol version string. Don't as_bad here. */
6454 x86_cons (expressionS
*exp
, int size
)
6456 if (size
== 4 || (object_64bit
&& size
== 8))
6458 /* Handle @GOTOFF and the like in an expression. */
6460 char *gotfree_input_line
;
6463 save
= input_line_pointer
;
6464 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6465 if (gotfree_input_line
)
6466 input_line_pointer
= gotfree_input_line
;
6470 if (gotfree_input_line
)
6472 /* expression () has merrily parsed up to the end of line,
6473 or a comma - in the wrong buffer. Transfer how far
6474 input_line_pointer has moved to the right buffer. */
6475 input_line_pointer
= (save
6476 + (input_line_pointer
- gotfree_input_line
)
6478 free (gotfree_input_line
);
6479 if (exp
->X_op
== O_constant
6480 || exp
->X_op
== O_absent
6481 || exp
->X_op
== O_illegal
6482 || exp
->X_op
== O_register
6483 || exp
->X_op
== O_big
)
6485 char c
= *input_line_pointer
;
6486 *input_line_pointer
= 0;
6487 as_bad (_("missing or invalid expression `%s'"), save
);
6488 *input_line_pointer
= c
;
6497 static void signed_cons (int size
)
6499 if (flag_code
== CODE_64BIT
)
6507 pe_directive_secrel (dummy
)
6508 int dummy ATTRIBUTE_UNUSED
;
6515 if (exp
.X_op
== O_symbol
)
6516 exp
.X_op
= O_secrel
;
6518 emit_expr (&exp
, 4);
6520 while (*input_line_pointer
++ == ',');
6522 input_line_pointer
--;
6523 demand_empty_rest_of_line ();
6528 i386_immediate (char *imm_start
)
6530 char *save_input_line_pointer
;
6531 char *gotfree_input_line
;
6534 i386_operand_type types
;
6536 operand_type_set (&types
, ~0);
6538 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6540 as_bad (_("at most %d immediate operands are allowed"),
6541 MAX_IMMEDIATE_OPERANDS
);
6545 exp
= &im_expressions
[i
.imm_operands
++];
6546 i
.op
[this_operand
].imms
= exp
;
6548 if (is_space_char (*imm_start
))
6551 save_input_line_pointer
= input_line_pointer
;
6552 input_line_pointer
= imm_start
;
6554 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6555 if (gotfree_input_line
)
6556 input_line_pointer
= gotfree_input_line
;
6558 exp_seg
= expression (exp
);
6561 if (*input_line_pointer
)
6562 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6564 input_line_pointer
= save_input_line_pointer
;
6565 if (gotfree_input_line
)
6566 free (gotfree_input_line
);
6568 if (exp
->X_op
== O_absent
6569 || exp
->X_op
== O_illegal
6570 || exp
->X_op
== O_big
6571 || (gotfree_input_line
6572 && (exp
->X_op
== O_constant
6573 || exp
->X_op
== O_register
)))
6575 as_bad (_("missing or invalid immediate expression `%s'"),
6579 else if (exp
->X_op
== O_constant
)
6581 /* Size it properly later. */
6582 i
.types
[this_operand
].bitfield
.imm64
= 1;
6583 /* If BFD64, sign extend val. */
6584 if (!use_rela_relocations
6585 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6587 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6589 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6590 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6591 && exp_seg
!= absolute_section
6592 && exp_seg
!= text_section
6593 && exp_seg
!= data_section
6594 && exp_seg
!= bss_section
6595 && exp_seg
!= undefined_section
6596 && !bfd_is_com_section (exp_seg
))
6598 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6602 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6604 as_bad (_("illegal immediate register operand %s"), imm_start
);
6609 /* This is an address. The size of the address will be
6610 determined later, depending on destination register,
6611 suffix, or the default for the section. */
6612 i
.types
[this_operand
].bitfield
.imm8
= 1;
6613 i
.types
[this_operand
].bitfield
.imm16
= 1;
6614 i
.types
[this_operand
].bitfield
.imm32
= 1;
6615 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6616 i
.types
[this_operand
].bitfield
.imm64
= 1;
6617 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6625 i386_scale (char *scale
)
6628 char *save
= input_line_pointer
;
6630 input_line_pointer
= scale
;
6631 val
= get_absolute_expression ();
6636 i
.log2_scale_factor
= 0;
6639 i
.log2_scale_factor
= 1;
6642 i
.log2_scale_factor
= 2;
6645 i
.log2_scale_factor
= 3;
6649 char sep
= *input_line_pointer
;
6651 *input_line_pointer
= '\0';
6652 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6654 *input_line_pointer
= sep
;
6655 input_line_pointer
= save
;
6659 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6661 as_warn (_("scale factor of %d without an index register"),
6662 1 << i
.log2_scale_factor
);
6663 i
.log2_scale_factor
= 0;
6665 scale
= input_line_pointer
;
6666 input_line_pointer
= save
;
6671 i386_displacement (char *disp_start
, char *disp_end
)
6675 char *save_input_line_pointer
;
6676 char *gotfree_input_line
;
6678 i386_operand_type bigdisp
, types
= anydisp
;
6681 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6683 as_bad (_("at most %d displacement operands are allowed"),
6684 MAX_MEMORY_OPERANDS
);
6688 operand_type_set (&bigdisp
, 0);
6689 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6690 || (!current_templates
->start
->opcode_modifier
.jump
6691 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6693 bigdisp
.bitfield
.disp32
= 1;
6694 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6695 if (flag_code
== CODE_64BIT
)
6699 bigdisp
.bitfield
.disp32s
= 1;
6700 bigdisp
.bitfield
.disp64
= 1;
6703 else if ((flag_code
== CODE_16BIT
) ^ override
)
6705 bigdisp
.bitfield
.disp32
= 0;
6706 bigdisp
.bitfield
.disp16
= 1;
6711 /* For PC-relative branches, the width of the displacement
6712 is dependent upon data size, not address size. */
6713 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6714 if (flag_code
== CODE_64BIT
)
6716 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6717 bigdisp
.bitfield
.disp16
= 1;
6720 bigdisp
.bitfield
.disp32
= 1;
6721 bigdisp
.bitfield
.disp32s
= 1;
6727 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6729 : LONG_MNEM_SUFFIX
));
6730 bigdisp
.bitfield
.disp32
= 1;
6731 if ((flag_code
== CODE_16BIT
) ^ override
)
6733 bigdisp
.bitfield
.disp32
= 0;
6734 bigdisp
.bitfield
.disp16
= 1;
6738 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6741 exp
= &disp_expressions
[i
.disp_operands
];
6742 i
.op
[this_operand
].disps
= exp
;
6744 save_input_line_pointer
= input_line_pointer
;
6745 input_line_pointer
= disp_start
;
6746 END_STRING_AND_SAVE (disp_end
);
6748 #ifndef GCC_ASM_O_HACK
6749 #define GCC_ASM_O_HACK 0
6752 END_STRING_AND_SAVE (disp_end
+ 1);
6753 if (i
.types
[this_operand
].bitfield
.baseIndex
6754 && displacement_string_end
[-1] == '+')
6756 /* This hack is to avoid a warning when using the "o"
6757 constraint within gcc asm statements.
6760 #define _set_tssldt_desc(n,addr,limit,type) \
6761 __asm__ __volatile__ ( \
6763 "movw %w1,2+%0\n\t" \
6765 "movb %b1,4+%0\n\t" \
6766 "movb %4,5+%0\n\t" \
6767 "movb $0,6+%0\n\t" \
6768 "movb %h1,7+%0\n\t" \
6770 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6772 This works great except that the output assembler ends
6773 up looking a bit weird if it turns out that there is
6774 no offset. You end up producing code that looks like:
6787 So here we provide the missing zero. */
6789 *displacement_string_end
= '0';
6792 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6793 if (gotfree_input_line
)
6794 input_line_pointer
= gotfree_input_line
;
6796 exp_seg
= expression (exp
);
6799 if (*input_line_pointer
)
6800 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6802 RESTORE_END_STRING (disp_end
+ 1);
6804 input_line_pointer
= save_input_line_pointer
;
6805 if (gotfree_input_line
)
6806 free (gotfree_input_line
);
6809 /* We do this to make sure that the section symbol is in
6810 the symbol table. We will ultimately change the relocation
6811 to be relative to the beginning of the section. */
6812 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6813 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6814 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6816 if (exp
->X_op
!= O_symbol
)
6819 if (S_IS_LOCAL (exp
->X_add_symbol
)
6820 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6821 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6822 exp
->X_op
= O_subtract
;
6823 exp
->X_op_symbol
= GOT_symbol
;
6824 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6825 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6826 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6827 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6829 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6832 else if (exp
->X_op
== O_absent
6833 || exp
->X_op
== O_illegal
6834 || exp
->X_op
== O_big
6835 || (gotfree_input_line
6836 && (exp
->X_op
== O_constant
6837 || exp
->X_op
== O_register
)))
6840 as_bad (_("missing or invalid displacement expression `%s'"),
6845 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6846 else if (exp
->X_op
!= O_constant
6847 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6848 && exp_seg
!= absolute_section
6849 && exp_seg
!= text_section
6850 && exp_seg
!= data_section
6851 && exp_seg
!= bss_section
6852 && exp_seg
!= undefined_section
6853 && !bfd_is_com_section (exp_seg
))
6855 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6860 RESTORE_END_STRING (disp_end
);
6862 /* Check if this is a displacement only operand. */
6863 bigdisp
= i
.types
[this_operand
];
6864 bigdisp
.bitfield
.disp8
= 0;
6865 bigdisp
.bitfield
.disp16
= 0;
6866 bigdisp
.bitfield
.disp32
= 0;
6867 bigdisp
.bitfield
.disp32s
= 0;
6868 bigdisp
.bitfield
.disp64
= 0;
6869 if (operand_type_all_zero (&bigdisp
))
6870 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6876 /* Make sure the memory operand we've been dealt is valid.
6877 Return 1 on success, 0 on a failure. */
6880 i386_index_check (const char *operand_string
)
6883 const char *kind
= "base/index";
6884 #if INFER_ADDR_PREFIX
6890 if (current_templates
->start
->opcode_modifier
.isstring
6891 && !current_templates
->start
->opcode_modifier
.immext
6892 && (current_templates
->end
[-1].opcode_modifier
.isstring
6895 /* Memory operands of string insns are special in that they only allow
6896 a single register (rDI, rSI, or rBX) as their memory address. */
6897 unsigned int expected
;
6899 kind
= "string address";
6901 if (current_templates
->start
->opcode_modifier
.w
)
6903 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6905 if (!type
.bitfield
.baseindex
6906 || ((!i
.mem_operands
!= !intel_syntax
)
6907 && current_templates
->end
[-1].operand_types
[1]
6908 .bitfield
.baseindex
))
6909 type
= current_templates
->end
[-1].operand_types
[1];
6910 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6913 expected
= 3 /* rBX */;
6915 if (!i
.base_reg
|| i
.index_reg
6916 || operand_type_check (i
.types
[this_operand
], disp
))
6918 else if (!(flag_code
== CODE_64BIT
6919 ? i
.prefix
[ADDR_PREFIX
]
6920 ? i
.base_reg
->reg_type
.bitfield
.reg32
6921 : i
.base_reg
->reg_type
.bitfield
.reg64
6922 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6923 ? i
.base_reg
->reg_type
.bitfield
.reg32
6924 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6926 else if (i
.base_reg
->reg_num
!= expected
)
6933 for (j
= 0; j
< i386_regtab_size
; ++j
)
6934 if ((flag_code
== CODE_64BIT
6935 ? i
.prefix
[ADDR_PREFIX
]
6936 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6937 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6938 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6939 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6940 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6941 && i386_regtab
[j
].reg_num
== expected
)
6943 assert (j
< i386_regtab_size
);
6944 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6946 intel_syntax
? '[' : '(',
6948 i386_regtab
[j
].reg_name
,
6949 intel_syntax
? ']' : ')');
6953 else if (flag_code
== CODE_64BIT
)
6956 && ((i
.prefix
[ADDR_PREFIX
] == 0
6957 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6958 || (i
.prefix
[ADDR_PREFIX
]
6959 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6961 || i
.base_reg
->reg_num
!=
6962 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6964 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6965 || (i
.prefix
[ADDR_PREFIX
] == 0
6966 && i
.index_reg
->reg_num
!= RegRiz
6967 && !i
.index_reg
->reg_type
.bitfield
.reg64
6969 || (i
.prefix
[ADDR_PREFIX
]
6970 && i
.index_reg
->reg_num
!= RegEiz
6971 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6976 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6980 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6981 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6983 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6984 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6986 && i
.base_reg
->reg_num
< 6
6987 && i
.index_reg
->reg_num
>= 6
6988 && i
.log2_scale_factor
== 0))))
6995 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6997 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6998 && i
.index_reg
->reg_num
!= RegEiz
)
6999 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7005 #if INFER_ADDR_PREFIX
7006 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7008 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7010 /* Change the size of any displacement too. At most one of
7011 Disp16 or Disp32 is set.
7012 FIXME. There doesn't seem to be any real need for separate
7013 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7014 Removing them would probably clean up the code quite a lot. */
7015 if (flag_code
!= CODE_64BIT
7016 && (i
.types
[this_operand
].bitfield
.disp16
7017 || i
.types
[this_operand
].bitfield
.disp32
))
7018 i
.types
[this_operand
]
7019 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7024 as_bad (_("`%s' is not a valid %s expression"),
7029 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7031 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7032 ? flag_code
== CODE_32BIT
7041 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7045 i386_att_operand (char *operand_string
)
7049 char *op_string
= operand_string
;
7051 if (is_space_char (*op_string
))
7054 /* We check for an absolute prefix (differentiating,
7055 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7056 if (*op_string
== ABSOLUTE_PREFIX
)
7059 if (is_space_char (*op_string
))
7061 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7064 /* Check if operand is a register. */
7065 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7067 i386_operand_type temp
;
7069 /* Check for a segment override by searching for ':' after a
7070 segment register. */
7072 if (is_space_char (*op_string
))
7074 if (*op_string
== ':'
7075 && (r
->reg_type
.bitfield
.sreg2
7076 || r
->reg_type
.bitfield
.sreg3
))
7081 i
.seg
[i
.mem_operands
] = &es
;
7084 i
.seg
[i
.mem_operands
] = &cs
;
7087 i
.seg
[i
.mem_operands
] = &ss
;
7090 i
.seg
[i
.mem_operands
] = &ds
;
7093 i
.seg
[i
.mem_operands
] = &fs
;
7096 i
.seg
[i
.mem_operands
] = &gs
;
7100 /* Skip the ':' and whitespace. */
7102 if (is_space_char (*op_string
))
7105 if (!is_digit_char (*op_string
)
7106 && !is_identifier_char (*op_string
)
7107 && *op_string
!= '('
7108 && *op_string
!= ABSOLUTE_PREFIX
)
7110 as_bad (_("bad memory operand `%s'"), op_string
);
7113 /* Handle case of %es:*foo. */
7114 if (*op_string
== ABSOLUTE_PREFIX
)
7117 if (is_space_char (*op_string
))
7119 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7121 goto do_memory_reference
;
7125 as_bad (_("junk `%s' after register"), op_string
);
7129 temp
.bitfield
.baseindex
= 0;
7130 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7132 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7133 i
.op
[this_operand
].regs
= r
;
7136 else if (*op_string
== REGISTER_PREFIX
)
7138 as_bad (_("bad register name `%s'"), op_string
);
7141 else if (*op_string
== IMMEDIATE_PREFIX
)
7144 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7146 as_bad (_("immediate operand illegal with absolute jump"));
7149 if (!i386_immediate (op_string
))
7152 else if (is_digit_char (*op_string
)
7153 || is_identifier_char (*op_string
)
7154 || *op_string
== '(')
7156 /* This is a memory reference of some sort. */
7159 /* Start and end of displacement string expression (if found). */
7160 char *displacement_string_start
;
7161 char *displacement_string_end
;
7163 do_memory_reference
:
7164 if ((i
.mem_operands
== 1
7165 && !current_templates
->start
->opcode_modifier
.isstring
)
7166 || i
.mem_operands
== 2)
7168 as_bad (_("too many memory references for `%s'"),
7169 current_templates
->start
->name
);
7173 /* Check for base index form. We detect the base index form by
7174 looking for an ')' at the end of the operand, searching
7175 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7177 base_string
= op_string
+ strlen (op_string
);
7180 if (is_space_char (*base_string
))
7183 /* If we only have a displacement, set-up for it to be parsed later. */
7184 displacement_string_start
= op_string
;
7185 displacement_string_end
= base_string
+ 1;
7187 if (*base_string
== ')')
7190 unsigned int parens_balanced
= 1;
7191 /* We've already checked that the number of left & right ()'s are
7192 equal, so this loop will not be infinite. */
7196 if (*base_string
== ')')
7198 if (*base_string
== '(')
7201 while (parens_balanced
);
7203 temp_string
= base_string
;
7205 /* Skip past '(' and whitespace. */
7207 if (is_space_char (*base_string
))
7210 if (*base_string
== ','
7211 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7214 displacement_string_end
= temp_string
;
7216 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7220 base_string
= end_op
;
7221 if (is_space_char (*base_string
))
7225 /* There may be an index reg or scale factor here. */
7226 if (*base_string
== ',')
7229 if (is_space_char (*base_string
))
7232 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7235 base_string
= end_op
;
7236 if (is_space_char (*base_string
))
7238 if (*base_string
== ',')
7241 if (is_space_char (*base_string
))
7244 else if (*base_string
!= ')')
7246 as_bad (_("expecting `,' or `)' "
7247 "after index register in `%s'"),
7252 else if (*base_string
== REGISTER_PREFIX
)
7254 as_bad (_("bad register name `%s'"), base_string
);
7258 /* Check for scale factor. */
7259 if (*base_string
!= ')')
7261 char *end_scale
= i386_scale (base_string
);
7266 base_string
= end_scale
;
7267 if (is_space_char (*base_string
))
7269 if (*base_string
!= ')')
7271 as_bad (_("expecting `)' "
7272 "after scale factor in `%s'"),
7277 else if (!i
.index_reg
)
7279 as_bad (_("expecting index register or scale factor "
7280 "after `,'; got '%c'"),
7285 else if (*base_string
!= ')')
7287 as_bad (_("expecting `,' or `)' "
7288 "after base register in `%s'"),
7293 else if (*base_string
== REGISTER_PREFIX
)
7295 as_bad (_("bad register name `%s'"), base_string
);
7300 /* If there's an expression beginning the operand, parse it,
7301 assuming displacement_string_start and
7302 displacement_string_end are meaningful. */
7303 if (displacement_string_start
!= displacement_string_end
)
7305 if (!i386_displacement (displacement_string_start
,
7306 displacement_string_end
))
7310 /* Special case for (%dx) while doing input/output op. */
7312 && operand_type_equal (&i
.base_reg
->reg_type
,
7313 ®16_inoutportreg
)
7315 && i
.log2_scale_factor
== 0
7316 && i
.seg
[i
.mem_operands
] == 0
7317 && !operand_type_check (i
.types
[this_operand
], disp
))
7319 i
.types
[this_operand
] = inoutportreg
;
7323 if (i386_index_check (operand_string
) == 0)
7325 i
.types
[this_operand
].bitfield
.mem
= 1;
7330 /* It's not a memory operand; argh! */
7331 as_bad (_("invalid char %s beginning operand %d `%s'"),
7332 output_invalid (*op_string
),
7337 return 1; /* Normal return. */
7340 /* md_estimate_size_before_relax()
7342 Called just before relax() for rs_machine_dependent frags. The x86
7343 assembler uses these frags to handle variable size jump
7346 Any symbol that is now undefined will not become defined.
7347 Return the correct fr_subtype in the frag.
7348 Return the initial "guess for variable size of frag" to caller.
7349 The guess is actually the growth beyond the fixed part. Whatever
7350 we do to grow the fixed or variable part contributes to our
7354 md_estimate_size_before_relax (fragP
, segment
)
7358 /* We've already got fragP->fr_subtype right; all we have to do is
7359 check for un-relaxable symbols. On an ELF system, we can't relax
7360 an externally visible symbol, because it may be overridden by a
7362 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7363 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7365 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7366 || S_IS_WEAK (fragP
->fr_symbol
)))
7370 /* Symbol is undefined in this segment, or we need to keep a
7371 reloc so that weak symbols can be overridden. */
7372 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7373 enum bfd_reloc_code_real reloc_type
;
7374 unsigned char *opcode
;
7377 if (fragP
->fr_var
!= NO_RELOC
)
7378 reloc_type
= fragP
->fr_var
;
7380 reloc_type
= BFD_RELOC_16_PCREL
;
7382 reloc_type
= BFD_RELOC_32_PCREL
;
7384 old_fr_fix
= fragP
->fr_fix
;
7385 opcode
= (unsigned char *) fragP
->fr_opcode
;
7387 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7390 /* Make jmp (0xeb) a (d)word displacement jump. */
7392 fragP
->fr_fix
+= size
;
7393 fix_new (fragP
, old_fr_fix
, size
,
7395 fragP
->fr_offset
, 1,
7401 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7403 /* Negate the condition, and branch past an
7404 unconditional jump. */
7407 /* Insert an unconditional jump. */
7409 /* We added two extra opcode bytes, and have a two byte
7411 fragP
->fr_fix
+= 2 + 2;
7412 fix_new (fragP
, old_fr_fix
+ 2, 2,
7414 fragP
->fr_offset
, 1,
7421 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7426 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7428 fragP
->fr_offset
, 1,
7430 fixP
->fx_signed
= 1;
7434 /* This changes the byte-displacement jump 0x7N
7435 to the (d)word-displacement jump 0x0f,0x8N. */
7436 opcode
[1] = opcode
[0] + 0x10;
7437 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7438 /* We've added an opcode byte. */
7439 fragP
->fr_fix
+= 1 + size
;
7440 fix_new (fragP
, old_fr_fix
+ 1, size
,
7442 fragP
->fr_offset
, 1,
7447 BAD_CASE (fragP
->fr_subtype
);
7451 return fragP
->fr_fix
- old_fr_fix
;
7454 /* Guess size depending on current relax state. Initially the relax
7455 state will correspond to a short jump and we return 1, because
7456 the variable part of the frag (the branch offset) is one byte
7457 long. However, we can relax a section more than once and in that
7458 case we must either set fr_subtype back to the unrelaxed state,
7459 or return the value for the appropriate branch. */
7460 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7463 /* Called after relax() is finished.
7465 In: Address of frag.
7466 fr_type == rs_machine_dependent.
7467 fr_subtype is what the address relaxed to.
7469 Out: Any fixSs and constants are set up.
7470 Caller will turn frag into a ".space 0". */
7473 md_convert_frag (abfd
, sec
, fragP
)
7474 bfd
*abfd ATTRIBUTE_UNUSED
;
7475 segT sec ATTRIBUTE_UNUSED
;
7478 unsigned char *opcode
;
7479 unsigned char *where_to_put_displacement
= NULL
;
7480 offsetT target_address
;
7481 offsetT opcode_address
;
7482 unsigned int extension
= 0;
7483 offsetT displacement_from_opcode_start
;
7485 opcode
= (unsigned char *) fragP
->fr_opcode
;
7487 /* Address we want to reach in file space. */
7488 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7490 /* Address opcode resides at in file space. */
7491 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7493 /* Displacement from opcode start to fill into instruction. */
7494 displacement_from_opcode_start
= target_address
- opcode_address
;
7496 if ((fragP
->fr_subtype
& BIG
) == 0)
7498 /* Don't have to change opcode. */
7499 extension
= 1; /* 1 opcode + 1 displacement */
7500 where_to_put_displacement
= &opcode
[1];
7504 if (no_cond_jump_promotion
7505 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7506 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7507 _("long jump required"));
7509 switch (fragP
->fr_subtype
)
7511 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7512 extension
= 4; /* 1 opcode + 4 displacement */
7514 where_to_put_displacement
= &opcode
[1];
7517 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7518 extension
= 2; /* 1 opcode + 2 displacement */
7520 where_to_put_displacement
= &opcode
[1];
7523 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7524 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7525 extension
= 5; /* 2 opcode + 4 displacement */
7526 opcode
[1] = opcode
[0] + 0x10;
7527 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7528 where_to_put_displacement
= &opcode
[2];
7531 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7532 extension
= 3; /* 2 opcode + 2 displacement */
7533 opcode
[1] = opcode
[0] + 0x10;
7534 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7535 where_to_put_displacement
= &opcode
[2];
7538 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7543 where_to_put_displacement
= &opcode
[3];
7547 BAD_CASE (fragP
->fr_subtype
);
7552 /* If size if less then four we are sure that the operand fits,
7553 but if it's 4, then it could be that the displacement is larger
7555 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7557 && ((addressT
) (displacement_from_opcode_start
- extension
7558 + ((addressT
) 1 << 31))
7559 > (((addressT
) 2 << 31) - 1)))
7561 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7562 _("jump target out of range"));
7563 /* Make us emit 0. */
7564 displacement_from_opcode_start
= extension
;
7566 /* Now put displacement after opcode. */
7567 md_number_to_chars ((char *) where_to_put_displacement
,
7568 (valueT
) (displacement_from_opcode_start
- extension
),
7569 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7570 fragP
->fr_fix
+= extension
;
7573 /* Apply a fixup (fixS) to segment data, once it has been determined
7574 by our caller that we have all the info we need to fix it up.
7576 On the 386, immediates, displacements, and data pointers are all in
7577 the same (little-endian) format, so we don't need to care about which
7581 md_apply_fix (fixP
, valP
, seg
)
7582 /* The fix we're to put in. */
7584 /* Pointer to the value of the bits. */
7586 /* Segment fix is from. */
7587 segT seg ATTRIBUTE_UNUSED
;
7589 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7590 valueT value
= *valP
;
7592 #if !defined (TE_Mach)
7595 switch (fixP
->fx_r_type
)
7601 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7604 case BFD_RELOC_X86_64_32S
:
7605 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7608 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7611 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7616 if (fixP
->fx_addsy
!= NULL
7617 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7618 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7619 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7620 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7621 && !use_rela_relocations
)
7623 /* This is a hack. There should be a better way to handle this.
7624 This covers for the fact that bfd_install_relocation will
7625 subtract the current location (for partial_inplace, PC relative
7626 relocations); see more below. */
7630 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7633 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7635 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7638 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7641 || (symbol_section_p (fixP
->fx_addsy
)
7642 && sym_seg
!= absolute_section
))
7643 && !generic_force_reloc (fixP
))
7645 /* Yes, we add the values in twice. This is because
7646 bfd_install_relocation subtracts them out again. I think
7647 bfd_install_relocation is broken, but I don't dare change
7649 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7653 #if defined (OBJ_COFF) && defined (TE_PE)
7654 /* For some reason, the PE format does not store a
7655 section address offset for a PC relative symbol. */
7656 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7657 || S_IS_WEAK (fixP
->fx_addsy
))
7658 value
+= md_pcrel_from (fixP
);
7662 /* Fix a few things - the dynamic linker expects certain values here,
7663 and we must not disappoint it. */
7664 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7665 if (IS_ELF
&& fixP
->fx_addsy
)
7666 switch (fixP
->fx_r_type
)
7668 case BFD_RELOC_386_PLT32
:
7669 case BFD_RELOC_X86_64_PLT32
:
7670 /* Make the jump instruction point to the address of the operand. At
7671 runtime we merely add the offset to the actual PLT entry. */
7675 case BFD_RELOC_386_TLS_GD
:
7676 case BFD_RELOC_386_TLS_LDM
:
7677 case BFD_RELOC_386_TLS_IE_32
:
7678 case BFD_RELOC_386_TLS_IE
:
7679 case BFD_RELOC_386_TLS_GOTIE
:
7680 case BFD_RELOC_386_TLS_GOTDESC
:
7681 case BFD_RELOC_X86_64_TLSGD
:
7682 case BFD_RELOC_X86_64_TLSLD
:
7683 case BFD_RELOC_X86_64_GOTTPOFF
:
7684 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7685 value
= 0; /* Fully resolved at runtime. No addend. */
7687 case BFD_RELOC_386_TLS_LE
:
7688 case BFD_RELOC_386_TLS_LDO_32
:
7689 case BFD_RELOC_386_TLS_LE_32
:
7690 case BFD_RELOC_X86_64_DTPOFF32
:
7691 case BFD_RELOC_X86_64_DTPOFF64
:
7692 case BFD_RELOC_X86_64_TPOFF32
:
7693 case BFD_RELOC_X86_64_TPOFF64
:
7694 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7697 case BFD_RELOC_386_TLS_DESC_CALL
:
7698 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7699 value
= 0; /* Fully resolved at runtime. No addend. */
7700 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7704 case BFD_RELOC_386_GOT32
:
7705 case BFD_RELOC_X86_64_GOT32
:
7706 value
= 0; /* Fully resolved at runtime. No addend. */
7709 case BFD_RELOC_VTABLE_INHERIT
:
7710 case BFD_RELOC_VTABLE_ENTRY
:
7717 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7719 #endif /* !defined (TE_Mach) */
7721 /* Are we finished with this relocation now? */
7722 if (fixP
->fx_addsy
== NULL
)
7724 else if (use_rela_relocations
)
7726 fixP
->fx_no_overflow
= 1;
7727 /* Remember value for tc_gen_reloc. */
7728 fixP
->fx_addnumber
= value
;
7732 md_number_to_chars (p
, value
, fixP
->fx_size
);
7736 md_atof (int type
, char *litP
, int *sizeP
)
7738 /* This outputs the LITTLENUMs in REVERSE order;
7739 in accord with the bigendian 386. */
7740 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7743 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7746 output_invalid (int c
)
7749 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7752 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7753 "(0x%x)", (unsigned char) c
);
7754 return output_invalid_buf
;
7757 /* REG_STRING starts *before* REGISTER_PREFIX. */
7759 static const reg_entry
*
7760 parse_real_register (char *reg_string
, char **end_op
)
7762 char *s
= reg_string
;
7764 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7767 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7768 if (*s
== REGISTER_PREFIX
)
7771 if (is_space_char (*s
))
7775 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7777 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7778 return (const reg_entry
*) NULL
;
7782 /* For naked regs, make sure that we are not dealing with an identifier.
7783 This prevents confusing an identifier like `eax_var' with register
7785 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7786 return (const reg_entry
*) NULL
;
7790 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7792 /* Handle floating point regs, allowing spaces in the (i) part. */
7793 if (r
== i386_regtab
/* %st is first entry of table */)
7795 if (is_space_char (*s
))
7800 if (is_space_char (*s
))
7802 if (*s
>= '0' && *s
<= '7')
7806 if (is_space_char (*s
))
7811 r
= hash_find (reg_hash
, "st(0)");
7816 /* We have "%st(" then garbage. */
7817 return (const reg_entry
*) NULL
;
7821 if (r
== NULL
|| allow_pseudo_reg
)
7824 if (operand_type_all_zero (&r
->reg_type
))
7825 return (const reg_entry
*) NULL
;
7827 if ((r
->reg_type
.bitfield
.reg32
7828 || r
->reg_type
.bitfield
.sreg3
7829 || r
->reg_type
.bitfield
.control
7830 || r
->reg_type
.bitfield
.debug
7831 || r
->reg_type
.bitfield
.test
)
7832 && !cpu_arch_flags
.bitfield
.cpui386
)
7833 return (const reg_entry
*) NULL
;
7835 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7836 return (const reg_entry
*) NULL
;
7838 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7839 return (const reg_entry
*) NULL
;
7841 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7842 return (const reg_entry
*) NULL
;
7844 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7845 if (!allow_index_reg
7846 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7847 return (const reg_entry
*) NULL
;
7849 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7850 || r
->reg_type
.bitfield
.reg64
)
7851 && (!cpu_arch_flags
.bitfield
.cpulm
7852 || !operand_type_equal (&r
->reg_type
, &control
))
7853 && flag_code
!= CODE_64BIT
)
7854 return (const reg_entry
*) NULL
;
7856 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7857 return (const reg_entry
*) NULL
;
7862 /* REG_STRING starts *before* REGISTER_PREFIX. */
7864 static const reg_entry
*
7865 parse_register (char *reg_string
, char **end_op
)
7869 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7870 r
= parse_real_register (reg_string
, end_op
);
7875 char *save
= input_line_pointer
;
7879 input_line_pointer
= reg_string
;
7880 c
= get_symbol_end ();
7881 symbolP
= symbol_find (reg_string
);
7882 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7884 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7886 know (e
->X_op
== O_register
);
7887 know (e
->X_add_number
>= 0
7888 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7889 r
= i386_regtab
+ e
->X_add_number
;
7890 *end_op
= input_line_pointer
;
7892 *input_line_pointer
= c
;
7893 input_line_pointer
= save
;
7899 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7902 char *end
= input_line_pointer
;
7905 r
= parse_register (name
, &input_line_pointer
);
7906 if (r
&& end
<= input_line_pointer
)
7908 *nextcharP
= *input_line_pointer
;
7909 *input_line_pointer
= 0;
7910 e
->X_op
= O_register
;
7911 e
->X_add_number
= r
- i386_regtab
;
7914 input_line_pointer
= end
;
7920 md_operand (expressionS
*e
)
7922 if (*input_line_pointer
== REGISTER_PREFIX
)
7925 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7929 e
->X_op
= O_register
;
7930 e
->X_add_number
= r
- i386_regtab
;
7931 input_line_pointer
= end
;
7937 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7938 const char *md_shortopts
= "kVQ:sqn";
7940 const char *md_shortopts
= "qn";
7943 #define OPTION_32 (OPTION_MD_BASE + 0)
7944 #define OPTION_64 (OPTION_MD_BASE + 1)
7945 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7946 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7947 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7948 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7949 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7950 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7951 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7952 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7953 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7954 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7956 struct option md_longopts
[] =
7958 {"32", no_argument
, NULL
, OPTION_32
},
7959 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7960 {"64", no_argument
, NULL
, OPTION_64
},
7962 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7963 {"march", required_argument
, NULL
, OPTION_MARCH
},
7964 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7965 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7966 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7967 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7968 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7969 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7970 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7971 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7972 {NULL
, no_argument
, NULL
, 0}
7974 size_t md_longopts_size
= sizeof (md_longopts
);
7977 md_parse_option (int c
, char *arg
)
7985 optimize_align_code
= 0;
7992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7993 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7994 should be emitted or not. FIXME: Not implemented. */
7998 /* -V: SVR4 argument to print version ID. */
8000 print_version_id ();
8003 /* -k: Ignore for FreeBSD compatibility. */
8008 /* -s: On i386 Solaris, this tells the native assembler to use
8009 .stab instead of .stab.excl. We always use .stab anyhow. */
8012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8015 const char **list
, **l
;
8017 list
= bfd_target_list ();
8018 for (l
= list
; *l
!= NULL
; l
++)
8019 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8020 || strcmp (*l
, "coff-x86-64") == 0
8021 || strcmp (*l
, "pe-x86-64") == 0
8022 || strcmp (*l
, "pei-x86-64") == 0)
8024 default_arch
= "x86_64";
8028 as_fatal (_("No compiled in support for x86_64"));
8035 default_arch
= "i386";
8039 #ifdef SVR4_COMMENT_CHARS
8044 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8046 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8050 i386_comment_chars
= n
;
8056 arch
= xstrdup (arg
);
8060 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8061 next
= strchr (arch
, '+');
8064 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8066 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8069 cpu_arch_name
= cpu_arch
[i
].name
;
8070 cpu_sub_arch_name
= NULL
;
8071 cpu_arch_flags
= cpu_arch
[i
].flags
;
8072 cpu_arch_isa
= cpu_arch
[i
].type
;
8073 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8074 if (!cpu_arch_tune_set
)
8076 cpu_arch_tune
= cpu_arch_isa
;
8077 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8081 else if (*cpu_arch
[i
].name
== '.'
8082 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8084 /* ISA entension. */
8085 i386_cpu_flags flags
;
8086 flags
= cpu_flags_or (cpu_arch_flags
,
8088 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8090 if (cpu_sub_arch_name
)
8092 char *name
= cpu_sub_arch_name
;
8093 cpu_sub_arch_name
= concat (name
,
8095 (const char *) NULL
);
8099 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8100 cpu_arch_flags
= flags
;
8106 if (i
>= ARRAY_SIZE (cpu_arch
))
8107 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8111 while (next
!= NULL
);
8116 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8117 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8119 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8121 cpu_arch_tune_set
= 1;
8122 cpu_arch_tune
= cpu_arch
[i
].type
;
8123 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8127 if (i
>= ARRAY_SIZE (cpu_arch
))
8128 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8131 case OPTION_MMNEMONIC
:
8132 if (strcasecmp (arg
, "att") == 0)
8134 else if (strcasecmp (arg
, "intel") == 0)
8137 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8140 case OPTION_MSYNTAX
:
8141 if (strcasecmp (arg
, "att") == 0)
8143 else if (strcasecmp (arg
, "intel") == 0)
8146 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8149 case OPTION_MINDEX_REG
:
8150 allow_index_reg
= 1;
8153 case OPTION_MNAKED_REG
:
8154 allow_naked_reg
= 1;
8157 case OPTION_MOLD_GCC
:
8161 case OPTION_MSSE2AVX
:
8165 case OPTION_MSSE_CHECK
:
8166 if (strcasecmp (arg
, "error") == 0)
8167 sse_check
= sse_check_error
;
8168 else if (strcasecmp (arg
, "warning") == 0)
8169 sse_check
= sse_check_warning
;
8170 else if (strcasecmp (arg
, "none") == 0)
8171 sse_check
= sse_check_none
;
8173 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8183 md_show_usage (stream
)
8186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8187 fprintf (stream
, _("\
8189 -V print assembler version number\n\
8192 fprintf (stream
, _("\
8193 -n Do not optimize code alignment\n\
8194 -q quieten some warnings\n"));
8195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8196 fprintf (stream
, _("\
8199 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8200 fprintf (stream
, _("\
8201 --32/--64 generate 32bit/64bit code\n"));
8203 #ifdef SVR4_COMMENT_CHARS
8204 fprintf (stream
, _("\
8205 --divide do not treat `/' as a comment character\n"));
8207 fprintf (stream
, _("\
8208 --divide ignored\n"));
8210 fprintf (stream
, _("\
8211 -march=CPU[,+EXTENSION...]\n\
8212 generate code for CPU and EXTENSION, CPU is one of:\n\
8213 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8214 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8215 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8216 generic32, generic64\n\
8217 EXTENSION is combination of:\n\
8218 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8219 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8220 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8221 sse5, svme, abm, padlock\n"));
8222 fprintf (stream
, _("\
8223 -mtune=CPU optimize for CPU, CPU is one of:\n\
8224 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8225 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8226 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8227 generic32, generic64\n"));
8228 fprintf (stream
, _("\
8229 -msse2avx encode SSE instructions with VEX prefix\n"));
8230 fprintf (stream
, _("\
8231 -msse-check=[none|error|warning]\n\
8232 check SSE instructions\n"));
8233 fprintf (stream
, _("\
8234 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8235 fprintf (stream
, _("\
8236 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8237 fprintf (stream
, _("\
8238 -mindex-reg support pseudo index registers\n"));
8239 fprintf (stream
, _("\
8240 -mnaked-reg don't require `%%' prefix for registers\n"));
8241 fprintf (stream
, _("\
8242 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8245 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8246 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8248 /* Pick the target format to use. */
8251 i386_target_format (void)
8253 if (!strcmp (default_arch
, "x86_64"))
8255 set_code_flag (CODE_64BIT
);
8256 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8258 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8259 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8260 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8261 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8262 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8263 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8264 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8265 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8266 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8267 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8269 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8271 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8272 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8273 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8274 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8275 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8276 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8277 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8278 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8279 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8280 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8283 else if (!strcmp (default_arch
, "i386"))
8285 set_code_flag (CODE_32BIT
);
8286 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8288 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8289 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8290 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8292 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8294 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8295 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8296 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8300 as_fatal (_("Unknown architecture"));
8301 switch (OUTPUT_FLAVOR
)
8304 case bfd_target_coff_flavour
:
8305 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "pe-i386";
8308 #ifdef OBJ_MAYBE_AOUT
8309 case bfd_target_aout_flavour
:
8310 return AOUT_TARGET_FORMAT
;
8312 #ifdef OBJ_MAYBE_COFF
8313 case bfd_target_coff_flavour
:
8316 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8317 case bfd_target_elf_flavour
:
8319 if (flag_code
== CODE_64BIT
)
8322 use_rela_relocations
= 1;
8324 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8333 #endif /* OBJ_MAYBE_ more than one */
8335 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8337 i386_elf_emit_arch_note (void)
8339 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8342 asection
*seg
= now_seg
;
8343 subsegT subseg
= now_subseg
;
8344 Elf_Internal_Note i_note
;
8345 Elf_External_Note e_note
;
8346 asection
*note_secp
;
8349 /* Create the .note section. */
8350 note_secp
= subseg_new (".note", 0);
8351 bfd_set_section_flags (stdoutput
,
8353 SEC_HAS_CONTENTS
| SEC_READONLY
);
8355 /* Process the arch string. */
8356 len
= strlen (cpu_arch_name
);
8358 i_note
.namesz
= len
+ 1;
8360 i_note
.type
= NT_ARCH
;
8361 p
= frag_more (sizeof (e_note
.namesz
));
8362 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8363 p
= frag_more (sizeof (e_note
.descsz
));
8364 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8365 p
= frag_more (sizeof (e_note
.type
));
8366 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8367 p
= frag_more (len
+ 1);
8368 strcpy (p
, cpu_arch_name
);
8370 frag_align (2, 0, 0);
8372 subseg_set (seg
, subseg
);
8378 md_undefined_symbol (name
)
8381 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8382 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8383 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8384 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8388 if (symbol_find (name
))
8389 as_bad (_("GOT already in symbol table"));
8390 GOT_symbol
= symbol_new (name
, undefined_section
,
8391 (valueT
) 0, &zero_address_frag
);
8398 /* Round up a section size to the appropriate boundary. */
8401 md_section_align (segment
, size
)
8402 segT segment ATTRIBUTE_UNUSED
;
8405 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8406 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8408 /* For a.out, force the section size to be aligned. If we don't do
8409 this, BFD will align it for us, but it will not write out the
8410 final bytes of the section. This may be a bug in BFD, but it is
8411 easier to fix it here since that is how the other a.out targets
8415 align
= bfd_get_section_alignment (stdoutput
, segment
);
8416 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8423 /* On the i386, PC-relative offsets are relative to the start of the
8424 next instruction. That is, the address of the offset, plus its
8425 size, since the offset is always the last part of the insn. */
8428 md_pcrel_from (fixS
*fixP
)
8430 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8436 s_bss (int ignore ATTRIBUTE_UNUSED
)
8440 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8442 obj_elf_section_change_hook ();
8444 temp
= get_absolute_expression ();
8445 subseg_set (bss_section
, (subsegT
) temp
);
8446 demand_empty_rest_of_line ();
8452 i386_validate_fix (fixS
*fixp
)
8454 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8456 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8460 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8465 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8467 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8474 tc_gen_reloc (section
, fixp
)
8475 asection
*section ATTRIBUTE_UNUSED
;
8479 bfd_reloc_code_real_type code
;
8481 switch (fixp
->fx_r_type
)
8483 case BFD_RELOC_X86_64_PLT32
:
8484 case BFD_RELOC_X86_64_GOT32
:
8485 case BFD_RELOC_X86_64_GOTPCREL
:
8486 case BFD_RELOC_386_PLT32
:
8487 case BFD_RELOC_386_GOT32
:
8488 case BFD_RELOC_386_GOTOFF
:
8489 case BFD_RELOC_386_GOTPC
:
8490 case BFD_RELOC_386_TLS_GD
:
8491 case BFD_RELOC_386_TLS_LDM
:
8492 case BFD_RELOC_386_TLS_LDO_32
:
8493 case BFD_RELOC_386_TLS_IE_32
:
8494 case BFD_RELOC_386_TLS_IE
:
8495 case BFD_RELOC_386_TLS_GOTIE
:
8496 case BFD_RELOC_386_TLS_LE_32
:
8497 case BFD_RELOC_386_TLS_LE
:
8498 case BFD_RELOC_386_TLS_GOTDESC
:
8499 case BFD_RELOC_386_TLS_DESC_CALL
:
8500 case BFD_RELOC_X86_64_TLSGD
:
8501 case BFD_RELOC_X86_64_TLSLD
:
8502 case BFD_RELOC_X86_64_DTPOFF32
:
8503 case BFD_RELOC_X86_64_DTPOFF64
:
8504 case BFD_RELOC_X86_64_GOTTPOFF
:
8505 case BFD_RELOC_X86_64_TPOFF32
:
8506 case BFD_RELOC_X86_64_TPOFF64
:
8507 case BFD_RELOC_X86_64_GOTOFF64
:
8508 case BFD_RELOC_X86_64_GOTPC32
:
8509 case BFD_RELOC_X86_64_GOT64
:
8510 case BFD_RELOC_X86_64_GOTPCREL64
:
8511 case BFD_RELOC_X86_64_GOTPC64
:
8512 case BFD_RELOC_X86_64_GOTPLT64
:
8513 case BFD_RELOC_X86_64_PLTOFF64
:
8514 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8515 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8517 case BFD_RELOC_VTABLE_ENTRY
:
8518 case BFD_RELOC_VTABLE_INHERIT
:
8520 case BFD_RELOC_32_SECREL
:
8522 code
= fixp
->fx_r_type
;
8524 case BFD_RELOC_X86_64_32S
:
8525 if (!fixp
->fx_pcrel
)
8527 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8528 code
= fixp
->fx_r_type
;
8534 switch (fixp
->fx_size
)
8537 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8538 _("can not do %d byte pc-relative relocation"),
8540 code
= BFD_RELOC_32_PCREL
;
8542 case 1: code
= BFD_RELOC_8_PCREL
; break;
8543 case 2: code
= BFD_RELOC_16_PCREL
; break;
8544 case 4: code
= BFD_RELOC_32_PCREL
; break;
8546 case 8: code
= BFD_RELOC_64_PCREL
; break;
8552 switch (fixp
->fx_size
)
8555 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8556 _("can not do %d byte relocation"),
8558 code
= BFD_RELOC_32
;
8560 case 1: code
= BFD_RELOC_8
; break;
8561 case 2: code
= BFD_RELOC_16
; break;
8562 case 4: code
= BFD_RELOC_32
; break;
8564 case 8: code
= BFD_RELOC_64
; break;
8571 if ((code
== BFD_RELOC_32
8572 || code
== BFD_RELOC_32_PCREL
8573 || code
== BFD_RELOC_X86_64_32S
)
8575 && fixp
->fx_addsy
== GOT_symbol
)
8578 code
= BFD_RELOC_386_GOTPC
;
8580 code
= BFD_RELOC_X86_64_GOTPC32
;
8582 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8584 && fixp
->fx_addsy
== GOT_symbol
)
8586 code
= BFD_RELOC_X86_64_GOTPC64
;
8589 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8590 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8591 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8593 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8595 if (!use_rela_relocations
)
8597 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8598 vtable entry to be used in the relocation's section offset. */
8599 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8600 rel
->address
= fixp
->fx_offset
;
8604 /* Use the rela in 64bit mode. */
8607 if (!fixp
->fx_pcrel
)
8608 rel
->addend
= fixp
->fx_offset
;
8612 case BFD_RELOC_X86_64_PLT32
:
8613 case BFD_RELOC_X86_64_GOT32
:
8614 case BFD_RELOC_X86_64_GOTPCREL
:
8615 case BFD_RELOC_X86_64_TLSGD
:
8616 case BFD_RELOC_X86_64_TLSLD
:
8617 case BFD_RELOC_X86_64_GOTTPOFF
:
8618 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8619 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8620 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8623 rel
->addend
= (section
->vma
8625 + fixp
->fx_addnumber
8626 + md_pcrel_from (fixp
));
8631 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8632 if (rel
->howto
== NULL
)
8634 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8635 _("cannot represent relocation type %s"),
8636 bfd_get_reloc_code_name (code
));
8637 /* Set howto to a garbage value so that we can keep going. */
8638 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8639 assert (rel
->howto
!= NULL
);
8646 /* Parse operands using Intel syntax. This implements a recursive descent
8647 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8650 FIXME: We do not recognize the full operand grammar defined in the MASM
8651 documentation. In particular, all the structure/union and
8652 high-level macro operands are missing.
8654 Uppercase words are terminals, lower case words are non-terminals.
8655 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8656 bars '|' denote choices. Most grammar productions are implemented in
8657 functions called 'intel_<production>'.
8659 Initial production is 'expr'.
8665 binOp & | AND | \| | OR | ^ | XOR
8667 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8669 constant digits [[ radixOverride ]]
8671 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8709 => expr expr cmpOp e04
8712 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8713 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8715 hexdigit a | b | c | d | e | f
8716 | A | B | C | D | E | F
8722 mulOp * | / | % | MOD | << | SHL | >> | SHR
8726 register specialRegister
8730 segmentRegister CS | DS | ES | FS | GS | SS
8732 specialRegister CR0 | CR2 | CR3 | CR4
8733 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8734 | TR3 | TR4 | TR5 | TR6 | TR7
8736 We simplify the grammar in obvious places (e.g., register parsing is
8737 done by calling parse_register) and eliminate immediate left recursion
8738 to implement a recursive-descent parser.
8742 expr' cmpOp e04 expr'
8794 /* Parsing structure for the intel syntax parser. Used to implement the
8795 semantic actions for the operand grammar. */
8796 struct intel_parser_s
8798 char *op_string
; /* The string being parsed. */
8799 int got_a_float
; /* Whether the operand is a float. */
8800 int op_modifier
; /* Operand modifier. */
8801 int is_mem
; /* 1 if operand is memory reference. */
8802 int in_offset
; /* >=1 if parsing operand of offset. */
8803 int in_bracket
; /* >=1 if parsing operand in brackets. */
8804 const reg_entry
*reg
; /* Last register reference found. */
8805 char *disp
; /* Displacement string being built. */
8806 char *next_operand
; /* Resume point when splitting operands. */
8809 static struct intel_parser_s intel_parser
;
8811 /* Token structure for parsing intel syntax. */
8814 int code
; /* Token code. */
8815 const reg_entry
*reg
; /* Register entry for register tokens. */
8816 char *str
; /* String representation. */
8819 static struct intel_token cur_token
, prev_token
;
8821 /* Token codes for the intel parser. Since T_SHORT is already used
8822 by COFF, undefine it first to prevent a warning. */
8840 #define T_YMMWORD 16
8842 /* Prototypes for intel parser functions. */
8843 static int intel_match_token (int);
8844 static void intel_putback_token (void);
8845 static void intel_get_token (void);
8846 static int intel_expr (void);
8847 static int intel_e04 (void);
8848 static int intel_e05 (void);
8849 static int intel_e06 (void);
8850 static int intel_e09 (void);
8851 static int intel_e10 (void);
8852 static int intel_e11 (void);
8855 i386_intel_operand (char *operand_string
, int got_a_float
)
8859 const reg_entry
*final_base
= i
.base_reg
;
8860 const reg_entry
*final_index
= i
.index_reg
;
8862 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8863 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8867 /* Initialize token holders. */
8868 cur_token
.code
= prev_token
.code
= T_NIL
;
8869 cur_token
.reg
= prev_token
.reg
= NULL
;
8870 cur_token
.str
= prev_token
.str
= NULL
;
8872 /* Initialize parser structure. */
8873 intel_parser
.got_a_float
= got_a_float
;
8874 intel_parser
.op_modifier
= 0;
8875 intel_parser
.is_mem
= 0;
8876 intel_parser
.in_offset
= 0;
8877 intel_parser
.in_bracket
= 0;
8878 intel_parser
.reg
= NULL
;
8879 intel_parser
.disp
[0] = '\0';
8880 intel_parser
.next_operand
= NULL
;
8885 /* Read the first token and start the parser. */
8887 ret
= intel_expr ();
8892 if (cur_token
.code
!= T_NIL
)
8894 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8895 current_templates
->start
->name
, cur_token
.str
);
8898 /* If we found a memory reference, hand it over to i386_displacement
8899 to fill in the rest of the operand fields. */
8900 else if (intel_parser
.is_mem
)
8902 if ((i
.mem_operands
== 1
8903 && !current_templates
->start
->opcode_modifier
.isstring
)
8904 || i
.mem_operands
== 2)
8906 as_bad (_("too many memory references for '%s'"),
8907 current_templates
->start
->name
);
8912 char *s
= intel_parser
.disp
;
8914 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8915 /* See the comments in intel_bracket_expr. */
8916 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8918 /* Add the displacement expression. */
8920 ret
= i386_displacement (s
, s
+ strlen (s
));
8923 /* Swap base and index in 16-bit memory operands like
8924 [si+bx]. Since i386_index_check is also used in AT&T
8925 mode we have to do that here. */
8928 && i
.base_reg
->reg_type
.bitfield
.reg16
8929 && i
.index_reg
->reg_type
.bitfield
.reg16
8930 && i
.base_reg
->reg_num
>= 6
8931 && i
.index_reg
->reg_num
< 6)
8933 const reg_entry
*base
= i
.index_reg
;
8935 i
.index_reg
= i
.base_reg
;
8938 ret
= i386_index_check (operand_string
);
8942 i
.types
[this_operand
].bitfield
.mem
= 1;
8948 /* Constant and OFFSET expressions are handled by i386_immediate. */
8949 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8950 || intel_parser
.reg
== NULL
)
8952 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8954 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8955 as_warn (_("Segment override ignored"));
8956 i
.seg
[i
.mem_operands
] = NULL
;
8958 ret
= i386_immediate (intel_parser
.disp
);
8961 if (!final_base
&& !final_index
)
8963 final_base
= i
.base_reg
;
8964 final_index
= i
.index_reg
;
8967 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8969 if (!ret
|| !intel_parser
.next_operand
)
8971 intel_parser
.op_string
= intel_parser
.next_operand
;
8972 this_operand
= i
.operands
++;
8973 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8977 free (intel_parser
.disp
);
8979 if (final_base
|| final_index
)
8981 i
.base_reg
= final_base
;
8982 i
.index_reg
= final_index
;
8988 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8992 expr' cmpOp e04 expr'
8997 /* XXX Implement the comparison operators. */
8998 return intel_e04 ();
9015 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9016 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
9018 if (cur_token
.code
== '+')
9020 else if (cur_token
.code
== '-')
9021 nregs
= NUM_ADDRESS_REGS
;
9025 strcat (intel_parser
.disp
, cur_token
.str
);
9026 intel_match_token (cur_token
.code
);
9037 int nregs
= ~NUM_ADDRESS_REGS
;
9044 if (cur_token
.code
== '&'
9045 || cur_token
.code
== '|'
9046 || cur_token
.code
== '^')
9050 str
[0] = cur_token
.code
;
9052 strcat (intel_parser
.disp
, str
);
9057 intel_match_token (cur_token
.code
);
9062 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9063 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
9074 int nregs
= ~NUM_ADDRESS_REGS
;
9081 if (cur_token
.code
== '*'
9082 || cur_token
.code
== '/'
9083 || cur_token
.code
== '%')
9087 str
[0] = cur_token
.code
;
9089 strcat (intel_parser
.disp
, str
);
9091 else if (cur_token
.code
== T_SHL
)
9092 strcat (intel_parser
.disp
, "<<");
9093 else if (cur_token
.code
== T_SHR
)
9094 strcat (intel_parser
.disp
, ">>");
9098 intel_match_token (cur_token
.code
);
9103 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9104 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9122 int nregs
= ~NUM_ADDRESS_REGS
;
9127 /* Don't consume constants here. */
9128 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9130 /* Need to look one token ahead - if the next token
9131 is a constant, the current token is its sign. */
9134 intel_match_token (cur_token
.code
);
9135 next_code
= cur_token
.code
;
9136 intel_putback_token ();
9137 if (next_code
== T_CONST
)
9141 /* e09 OFFSET e09 */
9142 if (cur_token
.code
== T_OFFSET
)
9145 ++intel_parser
.in_offset
;
9149 else if (cur_token
.code
== T_SHORT
)
9150 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9153 else if (cur_token
.code
== '+')
9154 strcat (intel_parser
.disp
, "+");
9159 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9165 str
[0] = cur_token
.code
;
9167 strcat (intel_parser
.disp
, str
);
9174 intel_match_token (cur_token
.code
);
9182 /* e09' PTR e10 e09' */
9183 if (cur_token
.code
== T_PTR
)
9187 if (prev_token
.code
== T_BYTE
)
9189 suffix
= BYTE_MNEM_SUFFIX
;
9190 i
.types
[this_operand
].bitfield
.byte
= 1;
9193 else if (prev_token
.code
== T_WORD
)
9195 if ((current_templates
->start
->name
[0] == 'l'
9196 && current_templates
->start
->name
[2] == 's'
9197 && current_templates
->start
->name
[3] == 0)
9198 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9199 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9200 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9201 suffix
= SHORT_MNEM_SUFFIX
;
9203 suffix
= WORD_MNEM_SUFFIX
;
9204 i
.types
[this_operand
].bitfield
.word
= 1;
9207 else if (prev_token
.code
== T_DWORD
)
9209 if ((current_templates
->start
->name
[0] == 'l'
9210 && current_templates
->start
->name
[2] == 's'
9211 && current_templates
->start
->name
[3] == 0)
9212 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9213 suffix
= WORD_MNEM_SUFFIX
;
9214 else if (flag_code
== CODE_16BIT
9215 && (current_templates
->start
->opcode_modifier
.jump
9216 || current_templates
->start
->opcode_modifier
.jumpdword
))
9217 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9218 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9219 suffix
= SHORT_MNEM_SUFFIX
;
9221 suffix
= LONG_MNEM_SUFFIX
;
9222 i
.types
[this_operand
].bitfield
.dword
= 1;
9225 else if (prev_token
.code
== T_FWORD
)
9227 if (current_templates
->start
->name
[0] == 'l'
9228 && current_templates
->start
->name
[2] == 's'
9229 && current_templates
->start
->name
[3] == 0)
9230 suffix
= LONG_MNEM_SUFFIX
;
9231 else if (!intel_parser
.got_a_float
)
9233 if (flag_code
== CODE_16BIT
)
9234 add_prefix (DATA_PREFIX_OPCODE
);
9235 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9238 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9239 i
.types
[this_operand
].bitfield
.fword
= 1;
9242 else if (prev_token
.code
== T_QWORD
)
9244 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9245 || intel_parser
.got_a_float
== 1) /* "f..." */
9246 suffix
= LONG_MNEM_SUFFIX
;
9248 suffix
= QWORD_MNEM_SUFFIX
;
9249 i
.types
[this_operand
].bitfield
.qword
= 1;
9252 else if (prev_token
.code
== T_TBYTE
)
9254 if (intel_parser
.got_a_float
== 1)
9255 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9257 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9260 else if (prev_token
.code
== T_XMMWORD
)
9262 suffix
= XMMWORD_MNEM_SUFFIX
;
9263 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9266 else if (prev_token
.code
== T_YMMWORD
)
9268 suffix
= YMMWORD_MNEM_SUFFIX
;
9269 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9274 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9278 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9280 /* Operands for jump/call using 'ptr' notation denote absolute
9282 if (current_templates
->start
->opcode_modifier
.jump
9283 || current_templates
->start
->opcode_modifier
.jumpdword
)
9284 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9286 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9290 else if (i
.suffix
!= suffix
)
9292 as_bad (_("Conflicting operand modifiers"));
9298 /* e09' : e10 e09' */
9299 else if (cur_token
.code
== ':')
9301 if (prev_token
.code
!= T_REG
)
9303 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9304 segment/group identifier (which we don't have), using comma
9305 as the operand separator there is even less consistent, since
9306 there all branches only have a single operand. */
9307 if (this_operand
!= 0
9308 || intel_parser
.in_offset
9309 || intel_parser
.in_bracket
9310 || (!current_templates
->start
->opcode_modifier
.jump
9311 && !current_templates
->start
->opcode_modifier
.jumpdword
9312 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9313 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9314 return intel_match_token (T_NIL
);
9315 /* Remember the start of the 2nd operand and terminate 1st
9317 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9318 another expression), but it gets at least the simplest case
9319 (a plain number or symbol on the left side) right. */
9320 intel_parser
.next_operand
= intel_parser
.op_string
;
9321 *--intel_parser
.op_string
= '\0';
9322 return intel_match_token (':');
9330 intel_match_token (cur_token
.code
);
9336 --intel_parser
.in_offset
;
9339 if (NUM_ADDRESS_REGS
> nregs
)
9341 as_bad (_("Invalid operand to `OFFSET'"));
9344 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9347 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9348 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9353 intel_bracket_expr (void)
9355 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9356 const char *start
= intel_parser
.op_string
;
9359 if (i
.op
[this_operand
].regs
)
9360 return intel_match_token (T_NIL
);
9362 intel_match_token ('[');
9364 /* Mark as a memory operand only if it's not already known to be an
9365 offset expression. If it's an offset expression, we need to keep
9367 if (!intel_parser
.in_offset
)
9369 ++intel_parser
.in_bracket
;
9371 /* Operands for jump/call inside brackets denote absolute addresses. */
9372 if (current_templates
->start
->opcode_modifier
.jump
9373 || current_templates
->start
->opcode_modifier
.jumpdword
)
9374 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9376 /* Unfortunately gas always diverged from MASM in a respect that can't
9377 be easily fixed without risking to break code sequences likely to be
9378 encountered (the testsuite even check for this): MASM doesn't consider
9379 an expression inside brackets unconditionally as a memory reference.
9380 When that is e.g. a constant, an offset expression, or the sum of the
9381 two, this is still taken as a constant load. gas, however, always
9382 treated these as memory references. As a compromise, we'll try to make
9383 offset expressions inside brackets work the MASM way (since that's
9384 less likely to be found in real world code), but make constants alone
9385 continue to work the traditional gas way. In either case, issue a
9387 intel_parser
.op_modifier
&= ~was_offset
;
9390 strcat (intel_parser
.disp
, "[");
9392 /* Add a '+' to the displacement string if necessary. */
9393 if (*intel_parser
.disp
!= '\0'
9394 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9395 strcat (intel_parser
.disp
, "+");
9398 && (len
= intel_parser
.op_string
- start
- 1,
9399 intel_match_token (']')))
9401 /* Preserve brackets when the operand is an offset expression. */
9402 if (intel_parser
.in_offset
)
9403 strcat (intel_parser
.disp
, "]");
9406 --intel_parser
.in_bracket
;
9407 if (i
.base_reg
|| i
.index_reg
)
9408 intel_parser
.is_mem
= 1;
9409 if (!intel_parser
.is_mem
)
9411 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9412 /* Defer the warning until all of the operand was parsed. */
9413 intel_parser
.is_mem
= -1;
9414 else if (!quiet_warnings
)
9415 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9416 len
, start
, len
, start
);
9419 intel_parser
.op_modifier
|= was_offset
;
9436 while (cur_token
.code
== '[')
9438 if (!intel_bracket_expr ())
9464 switch (cur_token
.code
)
9468 intel_match_token ('(');
9469 strcat (intel_parser
.disp
, "(");
9471 if (intel_expr () && intel_match_token (')'))
9473 strcat (intel_parser
.disp
, ")");
9480 return intel_bracket_expr ();
9485 strcat (intel_parser
.disp
, cur_token
.str
);
9486 intel_match_token (cur_token
.code
);
9488 /* Mark as a memory operand only if it's not already known to be an
9489 offset expression. */
9490 if (!intel_parser
.in_offset
)
9491 intel_parser
.is_mem
= 1;
9498 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9500 intel_match_token (T_REG
);
9502 /* Check for segment change. */
9503 if (cur_token
.code
== ':')
9505 if (!reg
->reg_type
.bitfield
.sreg2
9506 && !reg
->reg_type
.bitfield
.sreg3
)
9508 as_bad (_("`%s' is not a valid segment register"),
9512 else if (i
.mem_operands
>= 2)
9513 as_warn (_("Segment override ignored"));
9514 else if (i
.seg
[i
.mem_operands
])
9515 as_warn (_("Extra segment override ignored"));
9518 if (!intel_parser
.in_offset
)
9519 intel_parser
.is_mem
= 1;
9520 switch (reg
->reg_num
)
9523 i
.seg
[i
.mem_operands
] = &es
;
9526 i
.seg
[i
.mem_operands
] = &cs
;
9529 i
.seg
[i
.mem_operands
] = &ss
;
9532 i
.seg
[i
.mem_operands
] = &ds
;
9535 i
.seg
[i
.mem_operands
] = &fs
;
9538 i
.seg
[i
.mem_operands
] = &gs
;
9544 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9546 as_bad (_("cannot use `FLAT' here"));
9550 /* Not a segment register. Check for register scaling. */
9551 else if (cur_token
.code
== '*')
9553 if (!intel_parser
.in_bracket
)
9555 as_bad (_("Register scaling only allowed in memory operands"));
9559 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9560 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9561 else if (i
.index_reg
)
9562 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9564 /* What follows must be a valid scale. */
9565 intel_match_token ('*');
9567 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9569 /* Set the scale after setting the register (otherwise,
9570 i386_scale will complain) */
9571 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9573 char *str
, sign
= cur_token
.code
;
9574 intel_match_token (cur_token
.code
);
9575 if (cur_token
.code
!= T_CONST
)
9577 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9581 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9582 strcpy (str
+ 1, cur_token
.str
);
9584 if (!i386_scale (str
))
9588 else if (!i386_scale (cur_token
.str
))
9590 intel_match_token (cur_token
.code
);
9593 /* No scaling. If this is a memory operand, the register is either a
9594 base register (first occurrence) or an index register (second
9596 else if (intel_parser
.in_bracket
)
9601 else if (!i
.index_reg
)
9605 as_bad (_("Too many register references in memory operand"));
9609 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9612 /* It's neither base nor index. */
9613 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9615 i386_operand_type temp
= reg
->reg_type
;
9616 temp
.bitfield
.baseindex
= 0;
9617 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9619 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9620 i
.op
[this_operand
].regs
= reg
;
9625 as_bad (_("Invalid use of register"));
9629 /* Since registers are not part of the displacement string (except
9630 when we're parsing offset operands), we may need to remove any
9631 preceding '+' from the displacement string. */
9632 if (*intel_parser
.disp
!= '\0'
9633 && !intel_parser
.in_offset
)
9635 char *s
= intel_parser
.disp
;
9636 s
+= strlen (s
) - 1;
9661 intel_match_token (cur_token
.code
);
9663 if (cur_token
.code
== T_PTR
)
9666 /* It must have been an identifier. */
9667 intel_putback_token ();
9668 cur_token
.code
= T_ID
;
9674 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9678 /* The identifier represents a memory reference only if it's not
9679 preceded by an offset modifier and if it's not an equate. */
9680 symbolP
= symbol_find(cur_token
.str
);
9681 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9682 intel_parser
.is_mem
= 1;
9690 char *save_str
, sign
= 0;
9692 /* Allow constants that start with `+' or `-'. */
9693 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9695 sign
= cur_token
.code
;
9696 intel_match_token (cur_token
.code
);
9697 if (cur_token
.code
!= T_CONST
)
9699 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9705 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9706 strcpy (save_str
+ !!sign
, cur_token
.str
);
9710 /* Get the next token to check for register scaling. */
9711 intel_match_token (cur_token
.code
);
9713 /* Check if this constant is a scaling factor for an
9715 if (cur_token
.code
== '*')
9717 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9719 const reg_entry
*reg
= cur_token
.reg
;
9721 if (!intel_parser
.in_bracket
)
9723 as_bad (_("Register scaling only allowed "
9724 "in memory operands"));
9728 /* Disallow things like [1*si].
9729 sp and esp are invalid as index. */
9730 if (reg
->reg_type
.bitfield
.reg16
)
9731 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9732 else if (i
.index_reg
)
9733 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9735 /* The constant is followed by `* reg', so it must be
9738 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9740 /* Set the scale after setting the register (otherwise,
9741 i386_scale will complain) */
9742 if (!i386_scale (save_str
))
9744 intel_match_token (T_REG
);
9746 /* Since registers are not part of the displacement
9747 string, we may need to remove any preceding '+' from
9748 the displacement string. */
9749 if (*intel_parser
.disp
!= '\0')
9751 char *s
= intel_parser
.disp
;
9752 s
+= strlen (s
) - 1;
9762 /* The constant was not used for register scaling. Since we have
9763 already consumed the token following `*' we now need to put it
9764 back in the stream. */
9765 intel_putback_token ();
9768 /* Add the constant to the displacement string. */
9769 strcat (intel_parser
.disp
, save_str
);
9776 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9780 /* Match the given token against cur_token. If they match, read the next
9781 token from the operand string. */
9783 intel_match_token (int code
)
9785 if (cur_token
.code
== code
)
9792 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9797 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9799 intel_get_token (void)
9802 const reg_entry
*reg
;
9803 struct intel_token new_token
;
9805 new_token
.code
= T_NIL
;
9806 new_token
.reg
= NULL
;
9807 new_token
.str
= NULL
;
9809 /* Free the memory allocated to the previous token and move
9810 cur_token to prev_token. */
9812 free (prev_token
.str
);
9814 prev_token
= cur_token
;
9816 /* Skip whitespace. */
9817 while (is_space_char (*intel_parser
.op_string
))
9818 intel_parser
.op_string
++;
9820 /* Return an empty token if we find nothing else on the line. */
9821 if (*intel_parser
.op_string
== '\0')
9823 cur_token
= new_token
;
9827 /* The new token cannot be larger than the remainder of the operand
9829 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9830 new_token
.str
[0] = '\0';
9832 if (strchr ("0123456789", *intel_parser
.op_string
))
9834 char *p
= new_token
.str
;
9835 char *q
= intel_parser
.op_string
;
9836 new_token
.code
= T_CONST
;
9838 /* Allow any kind of identifier char to encompass floating point and
9839 hexadecimal numbers. */
9840 while (is_identifier_char (*q
))
9844 /* Recognize special symbol names [0-9][bf]. */
9845 if (strlen (intel_parser
.op_string
) == 2
9846 && (intel_parser
.op_string
[1] == 'b'
9847 || intel_parser
.op_string
[1] == 'f'))
9848 new_token
.code
= T_ID
;
9851 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9853 size_t len
= end_op
- intel_parser
.op_string
;
9855 new_token
.code
= T_REG
;
9856 new_token
.reg
= reg
;
9858 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9859 new_token
.str
[len
] = '\0';
9862 else if (is_identifier_char (*intel_parser
.op_string
))
9864 char *p
= new_token
.str
;
9865 char *q
= intel_parser
.op_string
;
9867 /* A '.' or '$' followed by an identifier char is an identifier.
9868 Otherwise, it's operator '.' followed by an expression. */
9869 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9871 new_token
.code
= '.';
9872 new_token
.str
[0] = '.';
9873 new_token
.str
[1] = '\0';
9877 while (is_identifier_char (*q
) || *q
== '@')
9881 if (strcasecmp (new_token
.str
, "NOT") == 0)
9882 new_token
.code
= '~';
9884 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9885 new_token
.code
= '%';
9887 else if (strcasecmp (new_token
.str
, "AND") == 0)
9888 new_token
.code
= '&';
9890 else if (strcasecmp (new_token
.str
, "OR") == 0)
9891 new_token
.code
= '|';
9893 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9894 new_token
.code
= '^';
9896 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9897 new_token
.code
= T_SHL
;
9899 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9900 new_token
.code
= T_SHR
;
9902 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9903 new_token
.code
= T_BYTE
;
9905 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9906 new_token
.code
= T_WORD
;
9908 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9909 new_token
.code
= T_DWORD
;
9911 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9912 new_token
.code
= T_FWORD
;
9914 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9915 new_token
.code
= T_QWORD
;
9917 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9918 /* XXX remove (gcc still uses it) */
9919 || strcasecmp (new_token
.str
, "XWORD") == 0)
9920 new_token
.code
= T_TBYTE
;
9922 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9923 || strcasecmp (new_token
.str
, "OWORD") == 0)
9924 new_token
.code
= T_XMMWORD
;
9926 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9927 new_token
.code
= T_YMMWORD
;
9929 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9930 new_token
.code
= T_PTR
;
9932 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9933 new_token
.code
= T_SHORT
;
9935 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9937 new_token
.code
= T_OFFSET
;
9939 /* ??? This is not mentioned in the MASM grammar but gcc
9940 makes use of it with -mintel-syntax. OFFSET may be
9941 followed by FLAT: */
9942 if (strncasecmp (q
, " FLAT:", 6) == 0)
9943 strcat (new_token
.str
, " FLAT:");
9947 new_token
.code
= T_ID
;
9951 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9953 new_token
.code
= *intel_parser
.op_string
;
9954 new_token
.str
[0] = *intel_parser
.op_string
;
9955 new_token
.str
[1] = '\0';
9958 else if (strchr ("<>", *intel_parser
.op_string
)
9959 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9961 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9962 new_token
.str
[0] = *intel_parser
.op_string
;
9963 new_token
.str
[1] = *intel_parser
.op_string
;
9964 new_token
.str
[2] = '\0';
9968 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9970 intel_parser
.op_string
+= strlen (new_token
.str
);
9971 cur_token
= new_token
;
9974 /* Put cur_token back into the token stream and make cur_token point to
9977 intel_putback_token (void)
9979 if (cur_token
.code
!= T_NIL
)
9981 intel_parser
.op_string
-= strlen (cur_token
.str
);
9982 free (cur_token
.str
);
9984 cur_token
= prev_token
;
9986 /* Forget prev_token. */
9987 prev_token
.code
= T_NIL
;
9988 prev_token
.reg
= NULL
;
9989 prev_token
.str
= NULL
;
9993 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9995 int saved_naked_reg
;
9996 char saved_register_dot
;
9998 saved_naked_reg
= allow_naked_reg
;
9999 allow_naked_reg
= 1;
10000 saved_register_dot
= register_chars
['.'];
10001 register_chars
['.'] = '.';
10002 allow_pseudo_reg
= 1;
10003 expression_and_evaluate (exp
);
10004 allow_pseudo_reg
= 0;
10005 register_chars
['.'] = saved_register_dot
;
10006 allow_naked_reg
= saved_naked_reg
;
10008 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10010 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10012 exp
->X_op
= O_constant
;
10013 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10014 .dw2_regnum
[flag_code
>> 1];
10017 exp
->X_op
= O_illegal
;
10022 tc_x86_frame_initial_instructions (void)
10024 static unsigned int sp_regno
[2];
10026 if (!sp_regno
[flag_code
>> 1])
10028 char *saved_input
= input_line_pointer
;
10029 char sp
[][4] = {"esp", "rsp"};
10032 input_line_pointer
= sp
[flag_code
>> 1];
10033 tc_x86_parse_to_dw2regnum (&exp
);
10034 assert (exp
.X_op
== O_constant
);
10035 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10036 input_line_pointer
= saved_input
;
10039 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10040 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10044 i386_elf_section_type (const char *str
, size_t len
)
10046 if (flag_code
== CODE_64BIT
10047 && len
== sizeof ("unwind") - 1
10048 && strncmp (str
, "unwind", 6) == 0)
10049 return SHT_X86_64_UNWIND
;
10056 i386_solaris_fix_up_eh_frame (segT sec
)
10058 if (flag_code
== CODE_64BIT
)
10059 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10065 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10069 expr
.X_op
= O_secrel
;
10070 expr
.X_add_symbol
= symbol
;
10071 expr
.X_add_number
= 0;
10072 emit_expr (&expr
, size
);
10076 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10077 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10080 x86_64_section_letter (int letter
, char **ptr_msg
)
10082 if (flag_code
== CODE_64BIT
)
10085 return SHF_X86_64_LARGE
;
10087 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10090 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
10095 x86_64_section_word (char *str
, size_t len
)
10097 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10098 return SHF_X86_64_LARGE
;
10104 handle_large_common (int small ATTRIBUTE_UNUSED
)
10106 if (flag_code
!= CODE_64BIT
)
10108 s_comm_internal (0, elf_common_parse
);
10109 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10113 static segT lbss_section
;
10114 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10115 asection
*saved_bss_section
= bss_section
;
10117 if (lbss_section
== NULL
)
10119 flagword applicable
;
10120 segT seg
= now_seg
;
10121 subsegT subseg
= now_subseg
;
10123 /* The .lbss section is for local .largecomm symbols. */
10124 lbss_section
= subseg_new (".lbss", 0);
10125 applicable
= bfd_applicable_section_flags (stdoutput
);
10126 bfd_set_section_flags (stdoutput
, lbss_section
,
10127 applicable
& SEC_ALLOC
);
10128 seg_info (lbss_section
)->bss
= 1;
10130 subseg_set (seg
, subseg
);
10133 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10134 bss_section
= lbss_section
;
10136 s_comm_internal (0, elf_common_parse
);
10138 elf_com_section_ptr
= saved_com_section_ptr
;
10139 bss_section
= saved_bss_section
;
10142 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */