1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros
;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32
= -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32
= -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts
=
194 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask
;
201 unsigned long mips_cprmask
[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa
= ISA_UNKNOWN
;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16
;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d
;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx
;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch
= CPU_UNKNOWN
;
220 static const char *mips_arch_string
;
221 static const struct mips_cpu_info
*mips_arch_info
;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune
= CPU_UNKNOWN
;
226 static const char *mips_tune_string
;
227 static const struct mips_cpu_info
*mips_tune_info
;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode
= 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
289 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
291 /* Return true if the given CPU supports the MIPS3D ASE. */
292 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
295 /* Return true if the given CPU supports the MDMX ASE. */
296 #define CPU_HAS_MDMX(cpu) (FALSE \
299 /* True if CPU has a dror instruction. */
300 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
302 /* True if CPU has a ror instruction. */
303 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
305 /* Whether the processor uses hardware interlocks to protect
306 reads from the HI and LO registers, and thus does not
307 require nops to be inserted. */
309 #define hilo_interlocks (mips_arch == CPU_R4010 \
310 || mips_arch == CPU_VR5500 \
311 || mips_arch == CPU_SB1 \
314 /* Whether the processor uses hardware interlocks to protect reads
315 from the GPRs, and thus does not require nops to be inserted. */
316 #define gpr_interlocks \
317 (mips_opts.isa != ISA_MIPS1 \
318 || mips_arch == CPU_VR5400 \
319 || mips_arch == CPU_VR5500 \
320 || mips_arch == CPU_R3900)
322 /* As with other "interlocks" this is used by hardware that has FP
323 (co-processor) interlocks. */
324 /* Itbl support may require additional care here. */
325 #define cop_interlocks (mips_arch == CPU_R4300 \
326 || mips_arch == CPU_VR5400 \
327 || mips_arch == CPU_VR5500 \
328 || mips_arch == CPU_SB1 \
331 /* Is this a mfhi or mflo instruction? */
332 #define MF_HILO_INSN(PINFO) \
333 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
335 /* MIPS PIC level. */
337 enum mips_pic_level mips_pic
;
339 /* Warn about all NOPS that the assembler generates. */
340 static int warn_nops
= 0;
342 /* 1 if we should generate 32 bit offsets from the $gp register in
343 SVR4_PIC mode. Currently has no meaning in other modes. */
344 static int mips_big_got
= 0;
346 /* 1 if trap instructions should used for overflow rather than break
348 static int mips_trap
= 0;
350 /* 1 if double width floating point constants should not be constructed
351 by assembling two single width halves into two single width floating
352 point registers which just happen to alias the double width destination
353 register. On some architectures this aliasing can be disabled by a bit
354 in the status register, and the setting of this bit cannot be determined
355 automatically at assemble time. */
356 static int mips_disable_float_construction
;
358 /* Non-zero if any .set noreorder directives were used. */
360 static int mips_any_noreorder
;
362 /* Non-zero if nops should be inserted when the register referenced in
363 an mfhi/mflo instruction is read in the next two instructions. */
364 static int mips_7000_hilo_fix
;
366 /* The size of the small data section. */
367 static unsigned int g_switch_value
= 8;
368 /* Whether the -G option was used. */
369 static int g_switch_seen
= 0;
374 /* If we can determine in advance that GP optimization won't be
375 possible, we can skip the relaxation stuff that tries to produce
376 GP-relative references. This makes delay slot optimization work
379 This function can only provide a guess, but it seems to work for
380 gcc output. It needs to guess right for gcc, otherwise gcc
381 will put what it thinks is a GP-relative instruction in a branch
384 I don't know if a fix is needed for the SVR4_PIC mode. I've only
385 fixed it for the non-PIC mode. KR 95/04/07 */
386 static int nopic_need_relax
PARAMS ((symbolS
*, int));
388 /* handle of the OPCODE hash table */
389 static struct hash_control
*op_hash
= NULL
;
391 /* The opcode hash table we use for the mips16. */
392 static struct hash_control
*mips16_op_hash
= NULL
;
394 /* This array holds the chars that always start a comment. If the
395 pre-processor is disabled, these aren't very useful */
396 const char comment_chars
[] = "#";
398 /* This array holds the chars that only start a comment at the beginning of
399 a line. If the line seems to have the form '# 123 filename'
400 .line and .file directives will appear in the pre-processed output */
401 /* Note that input_file.c hand checks for '#' at the beginning of the
402 first line of the input file. This is because the compiler outputs
403 #NO_APP at the beginning of its output. */
404 /* Also note that C style comments are always supported. */
405 const char line_comment_chars
[] = "#";
407 /* This array holds machine specific line separator characters. */
408 const char line_separator_chars
[] = ";";
410 /* Chars that can be used to separate mant from exp in floating point nums */
411 const char EXP_CHARS
[] = "eE";
413 /* Chars that mean this number is a floating point constant */
416 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
418 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
419 changed in read.c . Ideally it shouldn't have to know about it at all,
420 but nothing is ideal around here.
423 static char *insn_error
;
425 static int auto_align
= 1;
427 /* When outputting SVR4 PIC code, the assembler needs to know the
428 offset in the stack frame from which to restore the $gp register.
429 This is set by the .cprestore pseudo-op, and saved in this
431 static offsetT mips_cprestore_offset
= -1;
433 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
434 more optimizations, it can use a register value instead of a memory-saved
435 offset and even an other register than $gp as global pointer. */
436 static offsetT mips_cpreturn_offset
= -1;
437 static int mips_cpreturn_register
= -1;
438 static int mips_gp_register
= GP
;
439 static int mips_gprel_offset
= 0;
441 /* Whether mips_cprestore_offset has been set in the current function
442 (or whether it has already been warned about, if not). */
443 static int mips_cprestore_valid
= 0;
445 /* This is the register which holds the stack frame, as set by the
446 .frame pseudo-op. This is needed to implement .cprestore. */
447 static int mips_frame_reg
= SP
;
449 /* Whether mips_frame_reg has been set in the current function
450 (or whether it has already been warned about, if not). */
451 static int mips_frame_reg_valid
= 0;
453 /* To output NOP instructions correctly, we need to keep information
454 about the previous two instructions. */
456 /* Whether we are optimizing. The default value of 2 means to remove
457 unneeded NOPs and swap branch instructions when possible. A value
458 of 1 means to not swap branches. A value of 0 means to always
460 static int mips_optimize
= 2;
462 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
463 equivalent to seeing no -g option at all. */
464 static int mips_debug
= 0;
466 /* The previous instruction. */
467 static struct mips_cl_insn prev_insn
;
469 /* The instruction before prev_insn. */
470 static struct mips_cl_insn prev_prev_insn
;
472 /* If we don't want information for prev_insn or prev_prev_insn, we
473 point the insn_mo field at this dummy integer. */
474 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
476 /* Non-zero if prev_insn is valid. */
477 static int prev_insn_valid
;
479 /* The frag for the previous instruction. */
480 static struct frag
*prev_insn_frag
;
482 /* The offset into prev_insn_frag for the previous instruction. */
483 static long prev_insn_where
;
485 /* The reloc type for the previous instruction, if any. */
486 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
488 /* The reloc for the previous instruction, if any. */
489 static fixS
*prev_insn_fixp
[3];
491 /* Non-zero if the previous instruction was in a delay slot. */
492 static int prev_insn_is_delay_slot
;
494 /* Non-zero if the previous instruction was in a .set noreorder. */
495 static int prev_insn_unreordered
;
497 /* Non-zero if the previous instruction uses an extend opcode (if
499 static int prev_insn_extended
;
501 /* Non-zero if the previous previous instruction was in a .set
503 static int prev_prev_insn_unreordered
;
505 /* If this is set, it points to a frag holding nop instructions which
506 were inserted before the start of a noreorder section. If those
507 nops turn out to be unnecessary, the size of the frag can be
509 static fragS
*prev_nop_frag
;
511 /* The number of nop instructions we created in prev_nop_frag. */
512 static int prev_nop_frag_holds
;
514 /* The number of nop instructions that we know we need in
516 static int prev_nop_frag_required
;
518 /* The number of instructions we've seen since prev_nop_frag. */
519 static int prev_nop_frag_since
;
521 /* For ECOFF and ELF, relocations against symbols are done in two
522 parts, with a HI relocation and a LO relocation. Each relocation
523 has only 16 bits of space to store an addend. This means that in
524 order for the linker to handle carries correctly, it must be able
525 to locate both the HI and the LO relocation. This means that the
526 relocations must appear in order in the relocation table.
528 In order to implement this, we keep track of each unmatched HI
529 relocation. We then sort them so that they immediately precede the
530 corresponding LO relocation. */
535 struct mips_hi_fixup
*next
;
538 /* The section this fixup is in. */
542 /* The list of unmatched HI relocs. */
544 static struct mips_hi_fixup
*mips_hi_fixup_list
;
546 /* Map normal MIPS register numbers to mips16 register numbers. */
548 #define X ILLEGAL_REG
549 static const int mips32_to_16_reg_map
[] =
551 X
, X
, 2, 3, 4, 5, 6, 7,
552 X
, X
, X
, X
, X
, X
, X
, X
,
553 0, 1, X
, X
, X
, X
, X
, X
,
554 X
, X
, X
, X
, X
, X
, X
, X
558 /* Map mips16 register numbers to normal MIPS register numbers. */
560 static const unsigned int mips16_to_32_reg_map
[] =
562 16, 17, 2, 3, 4, 5, 6, 7
565 static int mips_fix_4122_bugs
;
567 /* We don't relax branches by default, since this causes us to expand
568 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
569 fail to compute the offset before expanding the macro to the most
570 efficient expansion. */
572 static int mips_relax_branch
;
574 /* Since the MIPS does not have multiple forms of PC relative
575 instructions, we do not have to do relaxing as is done on other
576 platforms. However, we do have to handle GP relative addressing
577 correctly, which turns out to be a similar problem.
579 Every macro that refers to a symbol can occur in (at least) two
580 forms, one with GP relative addressing and one without. For
581 example, loading a global variable into a register generally uses
582 a macro instruction like this:
584 If i can be addressed off the GP register (this is true if it is in
585 the .sbss or .sdata section, or if it is known to be smaller than
586 the -G argument) this will generate the following instruction:
588 This instruction will use a GPREL reloc. If i can not be addressed
589 off the GP register, the following instruction sequence will be used:
592 In this case the first instruction will have a HI16 reloc, and the
593 second reloc will have a LO16 reloc. Both relocs will be against
596 The issue here is that we may not know whether i is GP addressable
597 until after we see the instruction that uses it. Therefore, we
598 want to be able to choose the final instruction sequence only at
599 the end of the assembly. This is similar to the way other
600 platforms choose the size of a PC relative instruction only at the
603 When generating position independent code we do not use GP
604 addressing in quite the same way, but the issue still arises as
605 external symbols and local symbols must be handled differently.
607 We handle these issues by actually generating both possible
608 instruction sequences. The longer one is put in a frag_var with
609 type rs_machine_dependent. We encode what to do with the frag in
610 the subtype field. We encode (1) the number of existing bytes to
611 replace, (2) the number of new bytes to use, (3) the offset from
612 the start of the existing bytes to the first reloc we must generate
613 (that is, the offset is applied from the start of the existing
614 bytes after they are replaced by the new bytes, if any), (4) the
615 offset from the start of the existing bytes to the second reloc,
616 (5) whether a third reloc is needed (the third reloc is always four
617 bytes after the second reloc), and (6) whether to warn if this
618 variant is used (this is sometimes needed if .set nomacro or .set
619 noat is in effect). All these numbers are reasonably small.
621 Generating two instruction sequences must be handled carefully to
622 ensure that delay slots are handled correctly. Fortunately, there
623 are a limited number of cases. When the second instruction
624 sequence is generated, append_insn is directed to maintain the
625 existing delay slot information, so it continues to apply to any
626 code after the second instruction sequence. This means that the
627 second instruction sequence must not impose any requirements not
628 required by the first instruction sequence.
630 These variant frags are then handled in functions called by the
631 machine independent code. md_estimate_size_before_relax returns
632 the final size of the frag. md_convert_frag sets up the final form
633 of the frag. tc_gen_reloc adjust the first reloc and adds a second
635 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
639 | (((reloc1) + 64) << 9) \
640 | (((reloc2) + 64) << 2) \
641 | ((reloc3) ? (1 << 1) : 0) \
643 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
644 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
645 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
646 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
647 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
648 #define RELAX_WARN(i) ((i) & 1)
650 /* Branch without likely bit. If label is out of range, we turn:
652 beq reg1, reg2, label
662 with the following opcode replacements:
669 bltzal <-> bgezal (with jal label instead of j label)
671 Even though keeping the delay slot instruction in the delay slot of
672 the branch would be more efficient, it would be very tricky to do
673 correctly, because we'd have to introduce a variable frag *after*
674 the delay slot instruction, and expand that instead. Let's do it
675 the easy way for now, even if the branch-not-taken case now costs
676 one additional instruction. Out-of-range branches are not supposed
677 to be common, anyway.
679 Branch likely. If label is out of range, we turn:
681 beql reg1, reg2, label
682 delay slot (annulled if branch not taken)
691 delay slot (executed only if branch taken)
694 It would be possible to generate a shorter sequence by losing the
695 likely bit, generating something like:
700 delay slot (executed only if branch taken)
712 bltzall -> bgezal (with jal label instead of j label)
713 bgezall -> bltzal (ditto)
716 but it's not clear that it would actually improve performance. */
717 #define RELAX_BRANCH_ENCODE(reloc_s2, uncond, likely, link, toofar) \
720 | ((toofar) ? 1 : 0) \
722 | ((likely) ? 4 : 0) \
723 | ((uncond) ? 8 : 0) \
724 | ((reloc_s2) ? 16 : 0)))
725 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
726 #define RELAX_BRANCH_RELOC_S2(i) (((i) & 16) != 0)
727 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
728 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
729 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
730 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1))
732 /* For mips16 code, we use an entirely different form of relaxation.
733 mips16 supports two versions of most instructions which take
734 immediate values: a small one which takes some small value, and a
735 larger one which takes a 16 bit value. Since branches also follow
736 this pattern, relaxing these values is required.
738 We can assemble both mips16 and normal MIPS code in a single
739 object. Therefore, we need to support this type of relaxation at
740 the same time that we support the relaxation described above. We
741 use the high bit of the subtype field to distinguish these cases.
743 The information we store for this type of relaxation is the
744 argument code found in the opcode file for this relocation, whether
745 the user explicitly requested a small or extended form, and whether
746 the relocation is in a jump or jal delay slot. That tells us the
747 size of the value, and how it should be stored. We also store
748 whether the fragment is considered to be extended or not. We also
749 store whether this is known to be a branch to a different section,
750 whether we have tried to relax this frag yet, and whether we have
751 ever extended a PC relative fragment because of a shift count. */
752 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
755 | ((small) ? 0x100 : 0) \
756 | ((ext) ? 0x200 : 0) \
757 | ((dslot) ? 0x400 : 0) \
758 | ((jal_dslot) ? 0x800 : 0))
759 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
760 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
761 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
762 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
763 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
764 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
765 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
766 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
767 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
768 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
769 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
770 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
772 /* Is the given value a sign-extended 32-bit value? */
773 #define IS_SEXT_32BIT_NUM(x) \
774 (((x) &~ (offsetT) 0x7fffffff) == 0 \
775 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
777 /* Is the given value a sign-extended 16-bit value? */
778 #define IS_SEXT_16BIT_NUM(x) \
779 (((x) &~ (offsetT) 0x7fff) == 0 \
780 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
783 /* Prototypes for static functions. */
786 #define internalError() \
787 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
789 #define internalError() as_fatal (_("MIPS internal Error"));
792 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
794 static int insn_uses_reg
795 PARAMS ((struct mips_cl_insn
*ip
, unsigned int reg
,
796 enum mips_regclass
class));
797 static int reg_needs_delay
798 PARAMS ((unsigned int));
799 static void mips16_mark_labels
801 static void append_insn
802 PARAMS ((char *place
, struct mips_cl_insn
* ip
, expressionS
* p
,
803 bfd_reloc_code_real_type
*r
, bfd_boolean
));
804 static void mips_no_prev_insn
806 static void mips_emit_delays
807 PARAMS ((bfd_boolean
));
809 static void macro_build
810 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *name
,
811 const char *fmt
, ...));
813 static void macro_build ();
815 static void mips16_macro_build
816 PARAMS ((char *, int *, expressionS
*, const char *, const char *, va_list));
817 static void macro_build_jalr
818 PARAMS ((int, expressionS
*));
819 static void macro_build_lui
820 PARAMS ((char *place
, int *counter
, expressionS
* ep
, int regnum
));
821 static void macro_build_ldst_constoffset
822 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *op
,
823 int valreg
, int breg
));
825 PARAMS ((int *counter
, int reg
, int unsignedp
));
826 static void check_absolute_expr
827 PARAMS ((struct mips_cl_insn
* ip
, expressionS
*));
828 static void load_register
829 PARAMS ((int *, int, expressionS
*, int));
830 static void load_address
831 PARAMS ((int *, int, expressionS
*, int *));
832 static void move_register
833 PARAMS ((int *, int, int));
835 PARAMS ((struct mips_cl_insn
* ip
));
836 static void mips16_macro
837 PARAMS ((struct mips_cl_insn
* ip
));
838 #ifdef LOSING_COMPILER
840 PARAMS ((struct mips_cl_insn
* ip
));
843 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
844 static void mips16_ip
845 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
846 static void mips16_immed
847 PARAMS ((char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
,
848 bfd_boolean
, unsigned long *, bfd_boolean
*, unsigned short *));
849 static int my_getPercentOp
850 PARAMS ((char **, unsigned int *, int *));
851 static int my_getSmallParser
852 PARAMS ((char **, unsigned int *, int *));
853 static int my_getSmallExpression
854 PARAMS ((expressionS
*, char *));
855 static void my_getExpression
856 PARAMS ((expressionS
*, char *));
858 static int support_64bit_objects
861 static void mips_set_option_string
862 PARAMS ((const char **, const char *));
863 static symbolS
*get_symbol
865 static void mips_align
866 PARAMS ((int to
, int fill
, symbolS
*label
));
869 static void s_change_sec
871 static void s_change_section
875 static void s_float_cons
877 static void s_mips_globl
881 static void s_mipsset
883 static void s_abicalls
887 static void s_cpsetup
889 static void s_cplocal
891 static void s_cprestore
893 static void s_cpreturn
895 static void s_gpvalue
899 static void s_gpdword
905 static void md_obj_begin
907 static void md_obj_end
909 static long get_number
911 static void s_mips_ent
913 static void s_mips_end
915 static void s_mips_frame
917 static void s_mips_mask
919 static void s_mips_stab
921 static void s_mips_weakext
923 static void s_mips_file
925 static void s_mips_loc
927 static int mips16_extended_frag
928 PARAMS ((fragS
*, asection
*, long));
929 static int relaxed_branch_length (fragS
*, asection
*, int);
930 static int validate_mips_insn
931 PARAMS ((const struct mips_opcode
*));
933 PARAMS ((FILE *, const char *, int *, int *));
935 static int mips_need_elf_addend_fixup
939 /* Return values of my_getSmallExpression(). */
946 /* Direct relocation creation by %percent_op(). */
965 /* Table and functions used to map between CPU/ISA names, and
966 ISA levels, and CPU numbers. */
970 const char *name
; /* CPU or ISA name. */
971 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
972 int isa
; /* ISA level. */
973 int cpu
; /* CPU number (default CPU if ISA). */
976 static void mips_set_architecture
977 PARAMS ((const struct mips_cpu_info
*));
978 static void mips_set_tune
979 PARAMS ((const struct mips_cpu_info
*));
980 static bfd_boolean mips_strict_matching_cpu_name_p
981 PARAMS ((const char *, const char *));
982 static bfd_boolean mips_matching_cpu_name_p
983 PARAMS ((const char *, const char *));
984 static const struct mips_cpu_info
*mips_parse_cpu
985 PARAMS ((const char *, const char *));
986 static const struct mips_cpu_info
*mips_cpu_info_from_isa
991 The following pseudo-ops from the Kane and Heinrich MIPS book
992 should be defined here, but are currently unsupported: .alias,
993 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
995 The following pseudo-ops from the Kane and Heinrich MIPS book are
996 specific to the type of debugging information being generated, and
997 should be defined by the object format: .aent, .begin, .bend,
998 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1001 The following pseudo-ops from the Kane and Heinrich MIPS book are
1002 not MIPS CPU specific, but are also not specific to the object file
1003 format. This file is probably the best place to define them, but
1004 they are not currently supported: .asm0, .endr, .lab, .repeat,
1007 static const pseudo_typeS mips_pseudo_table
[] =
1009 /* MIPS specific pseudo-ops. */
1010 {"option", s_option
, 0},
1011 {"set", s_mipsset
, 0},
1012 {"rdata", s_change_sec
, 'r'},
1013 {"sdata", s_change_sec
, 's'},
1014 {"livereg", s_ignore
, 0},
1015 {"abicalls", s_abicalls
, 0},
1016 {"cpload", s_cpload
, 0},
1017 {"cpsetup", s_cpsetup
, 0},
1018 {"cplocal", s_cplocal
, 0},
1019 {"cprestore", s_cprestore
, 0},
1020 {"cpreturn", s_cpreturn
, 0},
1021 {"gpvalue", s_gpvalue
, 0},
1022 {"gpword", s_gpword
, 0},
1023 {"gpdword", s_gpdword
, 0},
1024 {"cpadd", s_cpadd
, 0},
1025 {"insn", s_insn
, 0},
1027 /* Relatively generic pseudo-ops that happen to be used on MIPS
1029 {"asciiz", stringer
, 1},
1030 {"bss", s_change_sec
, 'b'},
1032 {"half", s_cons
, 1},
1033 {"dword", s_cons
, 3},
1034 {"weakext", s_mips_weakext
, 0},
1036 /* These pseudo-ops are defined in read.c, but must be overridden
1037 here for one reason or another. */
1038 {"align", s_align
, 0},
1039 {"byte", s_cons
, 0},
1040 {"data", s_change_sec
, 'd'},
1041 {"double", s_float_cons
, 'd'},
1042 {"float", s_float_cons
, 'f'},
1043 {"globl", s_mips_globl
, 0},
1044 {"global", s_mips_globl
, 0},
1045 {"hword", s_cons
, 1},
1047 {"long", s_cons
, 2},
1048 {"octa", s_cons
, 4},
1049 {"quad", s_cons
, 3},
1050 {"section", s_change_section
, 0},
1051 {"short", s_cons
, 1},
1052 {"single", s_float_cons
, 'f'},
1053 {"stabn", s_mips_stab
, 'n'},
1054 {"text", s_change_sec
, 't'},
1055 {"word", s_cons
, 2},
1057 { "extern", ecoff_directive_extern
, 0},
1062 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1064 /* These pseudo-ops should be defined by the object file format.
1065 However, a.out doesn't support them, so we have versions here. */
1066 {"aent", s_mips_ent
, 1},
1067 {"bgnb", s_ignore
, 0},
1068 {"end", s_mips_end
, 0},
1069 {"endb", s_ignore
, 0},
1070 {"ent", s_mips_ent
, 0},
1071 {"file", s_mips_file
, 0},
1072 {"fmask", s_mips_mask
, 'F'},
1073 {"frame", s_mips_frame
, 0},
1074 {"loc", s_mips_loc
, 0},
1075 {"mask", s_mips_mask
, 'R'},
1076 {"verstamp", s_ignore
, 0},
1080 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
1085 pop_insert (mips_pseudo_table
);
1086 if (! ECOFF_DEBUGGING
)
1087 pop_insert (mips_nonecoff_pseudo_table
);
1090 /* Symbols labelling the current insn. */
1092 struct insn_label_list
1094 struct insn_label_list
*next
;
1098 static struct insn_label_list
*insn_labels
;
1099 static struct insn_label_list
*free_insn_labels
;
1101 static void mips_clear_insn_labels
PARAMS ((void));
1104 mips_clear_insn_labels ()
1106 register struct insn_label_list
**pl
;
1108 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1114 static char *expr_end
;
1116 /* Expressions which appear in instructions. These are set by
1119 static expressionS imm_expr
;
1120 static expressionS offset_expr
;
1122 /* Relocs associated with imm_expr and offset_expr. */
1124 static bfd_reloc_code_real_type imm_reloc
[3]
1125 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1126 static bfd_reloc_code_real_type offset_reloc
[3]
1127 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1129 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
1131 static bfd_boolean imm_unmatched_hi
;
1133 /* These are set by mips16_ip if an explicit extension is used. */
1135 static bfd_boolean mips16_small
, mips16_ext
;
1138 /* The pdr segment for per procedure frame/regmask info. Not used for
1141 static segT pdr_seg
;
1144 /* The default target format to use. */
1147 mips_target_format ()
1149 switch (OUTPUT_FLAVOR
)
1151 case bfd_target_aout_flavour
:
1152 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1153 case bfd_target_ecoff_flavour
:
1154 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1155 case bfd_target_coff_flavour
:
1157 case bfd_target_elf_flavour
:
1159 /* This is traditional mips. */
1160 return (target_big_endian
1161 ? (HAVE_64BIT_OBJECTS
1162 ? "elf64-tradbigmips"
1164 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1165 : (HAVE_64BIT_OBJECTS
1166 ? "elf64-tradlittlemips"
1168 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1170 return (target_big_endian
1171 ? (HAVE_64BIT_OBJECTS
1174 ? "elf32-nbigmips" : "elf32-bigmips"))
1175 : (HAVE_64BIT_OBJECTS
1176 ? "elf64-littlemips"
1178 ? "elf32-nlittlemips" : "elf32-littlemips")));
1186 /* This function is called once, at assembler startup time. It should
1187 set up all the tables, etc. that the MD part of the assembler will need. */
1192 register const char *retval
= NULL
;
1196 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1197 as_warn (_("Could not set architecture and machine"));
1199 op_hash
= hash_new ();
1201 for (i
= 0; i
< NUMOPCODES
;)
1203 const char *name
= mips_opcodes
[i
].name
;
1205 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1208 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1209 mips_opcodes
[i
].name
, retval
);
1210 /* Probably a memory allocation problem? Give up now. */
1211 as_fatal (_("Broken assembler. No assembly attempted."));
1215 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1217 if (!validate_mips_insn (&mips_opcodes
[i
]))
1222 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1225 mips16_op_hash
= hash_new ();
1228 while (i
< bfd_mips16_num_opcodes
)
1230 const char *name
= mips16_opcodes
[i
].name
;
1232 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1234 as_fatal (_("internal: can't hash `%s': %s"),
1235 mips16_opcodes
[i
].name
, retval
);
1238 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1239 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1240 != mips16_opcodes
[i
].match
))
1242 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1243 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1248 while (i
< bfd_mips16_num_opcodes
1249 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1253 as_fatal (_("Broken assembler. No assembly attempted."));
1255 /* We add all the general register names to the symbol table. This
1256 helps us detect invalid uses of them. */
1257 for (i
= 0; i
< 32; i
++)
1261 sprintf (buf
, "$%d", i
);
1262 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1263 &zero_address_frag
));
1265 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1266 &zero_address_frag
));
1267 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1268 &zero_address_frag
));
1269 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1270 &zero_address_frag
));
1271 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1272 &zero_address_frag
));
1273 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1274 &zero_address_frag
));
1275 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1276 &zero_address_frag
));
1277 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1278 &zero_address_frag
));
1279 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1280 &zero_address_frag
));
1281 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1282 &zero_address_frag
));
1284 /* If we don't add these register names to the symbol table, they
1285 may end up being added as regular symbols by operand(), and then
1286 make it to the object file as undefined in case they're not
1287 regarded as local symbols. They're local in o32, since `$' is a
1288 local symbol prefix, but not in n32 or n64. */
1289 for (i
= 0; i
< 8; i
++)
1293 sprintf (buf
, "$fcc%i", i
);
1294 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1295 &zero_address_frag
));
1298 mips_no_prev_insn (FALSE
);
1301 mips_cprmask
[0] = 0;
1302 mips_cprmask
[1] = 0;
1303 mips_cprmask
[2] = 0;
1304 mips_cprmask
[3] = 0;
1306 /* set the default alignment for the text section (2**2) */
1307 record_alignment (text_section
, 2);
1309 if (USE_GLOBAL_POINTER_OPT
)
1310 bfd_set_gp_size (stdoutput
, g_switch_value
);
1312 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1314 /* On a native system, sections must be aligned to 16 byte
1315 boundaries. When configured for an embedded ELF target, we
1317 if (strcmp (TARGET_OS
, "elf") != 0)
1319 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1320 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1321 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1324 /* Create a .reginfo section for register masks and a .mdebug
1325 section for debugging information. */
1333 subseg
= now_subseg
;
1335 /* The ABI says this section should be loaded so that the
1336 running program can access it. However, we don't load it
1337 if we are configured for an embedded target */
1338 flags
= SEC_READONLY
| SEC_DATA
;
1339 if (strcmp (TARGET_OS
, "elf") != 0)
1340 flags
|= SEC_ALLOC
| SEC_LOAD
;
1342 if (mips_abi
!= N64_ABI
)
1344 sec
= subseg_new (".reginfo", (subsegT
) 0);
1346 bfd_set_section_flags (stdoutput
, sec
, flags
);
1347 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1350 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1355 /* The 64-bit ABI uses a .MIPS.options section rather than
1356 .reginfo section. */
1357 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1358 bfd_set_section_flags (stdoutput
, sec
, flags
);
1359 bfd_set_section_alignment (stdoutput
, sec
, 3);
1362 /* Set up the option header. */
1364 Elf_Internal_Options opthdr
;
1367 opthdr
.kind
= ODK_REGINFO
;
1368 opthdr
.size
= (sizeof (Elf_External_Options
)
1369 + sizeof (Elf64_External_RegInfo
));
1372 f
= frag_more (sizeof (Elf_External_Options
));
1373 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1374 (Elf_External_Options
*) f
);
1376 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1381 if (ECOFF_DEBUGGING
)
1383 sec
= subseg_new (".mdebug", (subsegT
) 0);
1384 (void) bfd_set_section_flags (stdoutput
, sec
,
1385 SEC_HAS_CONTENTS
| SEC_READONLY
);
1386 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1389 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1391 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1392 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1393 SEC_READONLY
| SEC_RELOC
1395 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1399 subseg_set (seg
, subseg
);
1403 if (! ECOFF_DEBUGGING
)
1410 if (! ECOFF_DEBUGGING
)
1418 struct mips_cl_insn insn
;
1419 bfd_reloc_code_real_type unused_reloc
[3]
1420 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1422 imm_expr
.X_op
= O_absent
;
1423 imm_unmatched_hi
= FALSE
;
1424 offset_expr
.X_op
= O_absent
;
1425 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1426 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1427 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1428 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1429 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1430 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1432 if (mips_opts
.mips16
)
1433 mips16_ip (str
, &insn
);
1436 mips_ip (str
, &insn
);
1437 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1438 str
, insn
.insn_opcode
));
1443 as_bad ("%s `%s'", insn_error
, str
);
1447 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1449 if (mips_opts
.mips16
)
1450 mips16_macro (&insn
);
1456 if (imm_expr
.X_op
!= O_absent
)
1457 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1458 else if (offset_expr
.X_op
!= O_absent
)
1459 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, FALSE
);
1461 append_insn (NULL
, &insn
, NULL
, unused_reloc
, FALSE
);
1465 /* See whether instruction IP reads register REG. CLASS is the type
1469 insn_uses_reg (ip
, reg
, class)
1470 struct mips_cl_insn
*ip
;
1472 enum mips_regclass
class;
1474 if (class == MIPS16_REG
)
1476 assert (mips_opts
.mips16
);
1477 reg
= mips16_to_32_reg_map
[reg
];
1478 class = MIPS_GR_REG
;
1481 /* Don't report on general register ZERO, since it never changes. */
1482 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1485 if (class == MIPS_FP_REG
)
1487 assert (! mips_opts
.mips16
);
1488 /* If we are called with either $f0 or $f1, we must check $f0.
1489 This is not optimal, because it will introduce an unnecessary
1490 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1491 need to distinguish reading both $f0 and $f1 or just one of
1492 them. Note that we don't have to check the other way,
1493 because there is no instruction that sets both $f0 and $f1
1494 and requires a delay. */
1495 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1496 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1497 == (reg
&~ (unsigned) 1)))
1499 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1500 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1501 == (reg
&~ (unsigned) 1)))
1504 else if (! mips_opts
.mips16
)
1506 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1507 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1509 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1510 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1515 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1516 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1517 & MIPS16OP_MASK_RX
)]
1520 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1521 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1522 & MIPS16OP_MASK_RY
)]
1525 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1526 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1527 & MIPS16OP_MASK_MOVE32Z
)]
1530 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1532 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1534 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1536 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1537 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1538 & MIPS16OP_MASK_REGR32
) == reg
)
1545 /* This function returns true if modifying a register requires a
1549 reg_needs_delay (reg
)
1552 unsigned long prev_pinfo
;
1554 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1555 if (! mips_opts
.noreorder
1556 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1557 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1558 || (! gpr_interlocks
1559 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1561 /* A load from a coprocessor or from memory. All load
1562 delays delay the use of general register rt for one
1563 instruction on the r3000. The r6000 and r4000 use
1565 /* Itbl support may require additional care here. */
1566 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1567 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1574 /* Mark instruction labels in mips16 mode. This permits the linker to
1575 handle them specially, such as generating jalx instructions when
1576 needed. We also make them odd for the duration of the assembly, in
1577 order to generate the right sort of code. We will make them even
1578 in the adjust_symtab routine, while leaving them marked. This is
1579 convenient for the debugger and the disassembler. The linker knows
1580 to make them odd again. */
1583 mips16_mark_labels ()
1585 if (mips_opts
.mips16
)
1587 struct insn_label_list
*l
;
1590 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1593 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1594 S_SET_OTHER (l
->label
, STO_MIPS16
);
1596 val
= S_GET_VALUE (l
->label
);
1598 S_SET_VALUE (l
->label
, val
+ 1);
1603 /* Output an instruction. PLACE is where to put the instruction; if
1604 it is NULL, this uses frag_more to get room. IP is the instruction
1605 information. ADDRESS_EXPR is an operand of the instruction to be
1606 used with RELOC_TYPE. */
1609 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1611 struct mips_cl_insn
*ip
;
1612 expressionS
*address_expr
;
1613 bfd_reloc_code_real_type
*reloc_type
;
1614 bfd_boolean unmatched_hi
;
1616 register unsigned long prev_pinfo
, pinfo
;
1621 /* Mark instruction labels in mips16 mode. */
1622 mips16_mark_labels ();
1624 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1625 pinfo
= ip
->insn_mo
->pinfo
;
1627 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1631 /* If the previous insn required any delay slots, see if we need
1632 to insert a NOP or two. There are eight kinds of possible
1633 hazards, of which an instruction can have at most one type.
1634 (1) a load from memory delay
1635 (2) a load from a coprocessor delay
1636 (3) an unconditional branch delay
1637 (4) a conditional branch delay
1638 (5) a move to coprocessor register delay
1639 (6) a load coprocessor register from memory delay
1640 (7) a coprocessor condition code delay
1641 (8) a HI/LO special register delay
1643 There are a lot of optimizations we could do that we don't.
1644 In particular, we do not, in general, reorder instructions.
1645 If you use gcc with optimization, it will reorder
1646 instructions and generally do much more optimization then we
1647 do here; repeating all that work in the assembler would only
1648 benefit hand written assembly code, and does not seem worth
1651 /* This is how a NOP is emitted. */
1652 #define emit_nop() \
1654 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1655 : md_number_to_chars (frag_more (4), 0, 4))
1657 /* The previous insn might require a delay slot, depending upon
1658 the contents of the current insn. */
1659 if (! mips_opts
.mips16
1660 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1661 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1662 && ! cop_interlocks
)
1663 || (! gpr_interlocks
1664 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1666 /* A load from a coprocessor or from memory. All load
1667 delays delay the use of general register rt for one
1668 instruction on the r3000. The r6000 and r4000 use
1670 /* Itbl support may require additional care here. */
1671 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1672 if (mips_optimize
== 0
1673 || insn_uses_reg (ip
,
1674 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1679 else if (! mips_opts
.mips16
1680 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1681 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1682 && ! cop_interlocks
)
1683 || (mips_opts
.isa
== ISA_MIPS1
1684 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1686 /* A generic coprocessor delay. The previous instruction
1687 modified a coprocessor general or control register. If
1688 it modified a control register, we need to avoid any
1689 coprocessor instruction (this is probably not always
1690 required, but it sometimes is). If it modified a general
1691 register, we avoid using that register.
1693 On the r6000 and r4000 loading a coprocessor register
1694 from memory is interlocked, and does not require a delay.
1696 This case is not handled very well. There is no special
1697 knowledge of CP0 handling, and the coprocessors other
1698 than the floating point unit are not distinguished at
1700 /* Itbl support may require additional care here. FIXME!
1701 Need to modify this to include knowledge about
1702 user specified delays! */
1703 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1705 if (mips_optimize
== 0
1706 || insn_uses_reg (ip
,
1707 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1712 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1714 if (mips_optimize
== 0
1715 || insn_uses_reg (ip
,
1716 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1723 /* We don't know exactly what the previous instruction
1724 does. If the current instruction uses a coprocessor
1725 register, we must insert a NOP. If previous
1726 instruction may set the condition codes, and the
1727 current instruction uses them, we must insert two
1729 /* Itbl support may require additional care here. */
1730 if (mips_optimize
== 0
1731 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1732 && (pinfo
& INSN_READ_COND_CODE
)))
1734 else if (pinfo
& INSN_COP
)
1738 else if (! mips_opts
.mips16
1739 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1740 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1741 && ! cop_interlocks
)
1743 /* The previous instruction sets the coprocessor condition
1744 codes, but does not require a general coprocessor delay
1745 (this means it is a floating point comparison
1746 instruction). If this instruction uses the condition
1747 codes, we need to insert a single NOP. */
1748 /* Itbl support may require additional care here. */
1749 if (mips_optimize
== 0
1750 || (pinfo
& INSN_READ_COND_CODE
))
1754 /* If we're fixing up mfhi/mflo for the r7000 and the
1755 previous insn was an mfhi/mflo and the current insn
1756 reads the register that the mfhi/mflo wrote to, then
1759 else if (mips_7000_hilo_fix
1760 && MF_HILO_INSN (prev_pinfo
)
1761 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1768 /* If we're fixing up mfhi/mflo for the r7000 and the
1769 2nd previous insn was an mfhi/mflo and the current insn
1770 reads the register that the mfhi/mflo wrote to, then
1773 else if (mips_7000_hilo_fix
1774 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1775 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1783 else if (prev_pinfo
& INSN_READ_LO
)
1785 /* The previous instruction reads the LO register; if the
1786 current instruction writes to the LO register, we must
1787 insert two NOPS. Some newer processors have interlocks.
1788 Also the tx39's multiply instructions can be exectuted
1789 immediatly after a read from HI/LO (without the delay),
1790 though the tx39's divide insns still do require the
1792 if (! (hilo_interlocks
1793 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1794 && (mips_optimize
== 0
1795 || (pinfo
& INSN_WRITE_LO
)))
1797 /* Most mips16 branch insns don't have a delay slot.
1798 If a read from LO is immediately followed by a branch
1799 to a write to LO we have a read followed by a write
1800 less than 2 insns away. We assume the target of
1801 a branch might be a write to LO, and insert a nop
1802 between a read and an immediately following branch. */
1803 else if (mips_opts
.mips16
1804 && (mips_optimize
== 0
1805 || (pinfo
& MIPS16_INSN_BRANCH
)))
1808 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1810 /* The previous instruction reads the HI register; if the
1811 current instruction writes to the HI register, we must
1812 insert a NOP. Some newer processors have interlocks.
1813 Also the note tx39's multiply above. */
1814 if (! (hilo_interlocks
1815 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1816 && (mips_optimize
== 0
1817 || (pinfo
& INSN_WRITE_HI
)))
1819 /* Most mips16 branch insns don't have a delay slot.
1820 If a read from HI is immediately followed by a branch
1821 to a write to HI we have a read followed by a write
1822 less than 2 insns away. We assume the target of
1823 a branch might be a write to HI, and insert a nop
1824 between a read and an immediately following branch. */
1825 else if (mips_opts
.mips16
1826 && (mips_optimize
== 0
1827 || (pinfo
& MIPS16_INSN_BRANCH
)))
1831 /* If the previous instruction was in a noreorder section, then
1832 we don't want to insert the nop after all. */
1833 /* Itbl support may require additional care here. */
1834 if (prev_insn_unreordered
)
1837 /* There are two cases which require two intervening
1838 instructions: 1) setting the condition codes using a move to
1839 coprocessor instruction which requires a general coprocessor
1840 delay and then reading the condition codes 2) reading the HI
1841 or LO register and then writing to it (except on processors
1842 which have interlocks). If we are not already emitting a NOP
1843 instruction, we must check for these cases compared to the
1844 instruction previous to the previous instruction. */
1845 if ((! mips_opts
.mips16
1846 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1847 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1848 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1849 && (pinfo
& INSN_READ_COND_CODE
)
1850 && ! cop_interlocks
)
1851 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1852 && (pinfo
& INSN_WRITE_LO
)
1853 && ! (hilo_interlocks
1854 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1855 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1856 && (pinfo
& INSN_WRITE_HI
)
1857 && ! (hilo_interlocks
1858 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1863 if (prev_prev_insn_unreordered
)
1866 if (prev_prev_nop
&& nops
== 0)
1869 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1871 /* We're out of bits in pinfo, so we must resort to string
1872 ops here. Shortcuts are selected based on opcodes being
1873 limited to the VR4122 instruction set. */
1875 const char *pn
= prev_insn
.insn_mo
->name
;
1876 const char *tn
= ip
->insn_mo
->name
;
1877 if (strncmp(pn
, "macc", 4) == 0
1878 || strncmp(pn
, "dmacc", 5) == 0)
1880 /* Errata 21 - [D]DIV[U] after [D]MACC */
1881 if (strstr (tn
, "div"))
1886 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1887 if (pn
[0] == 'd' /* dmacc */
1888 && (strncmp(tn
, "dmult", 5) == 0
1889 || strncmp(tn
, "dmacc", 5) == 0))
1894 /* Errata 24 - MT{LO,HI} after [D]MACC */
1895 if (strcmp (tn
, "mtlo") == 0
1896 || strcmp (tn
, "mthi") == 0)
1902 else if (strncmp(pn
, "dmult", 5) == 0
1903 && (strncmp(tn
, "dmult", 5) == 0
1904 || strncmp(tn
, "dmacc", 5) == 0))
1906 /* Here is the rest of errata 23. */
1909 if (nops
< min_nops
)
1913 /* If we are being given a nop instruction, don't bother with
1914 one of the nops we would otherwise output. This will only
1915 happen when a nop instruction is used with mips_optimize set
1918 && ! mips_opts
.noreorder
1919 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1922 /* Now emit the right number of NOP instructions. */
1923 if (nops
> 0 && ! mips_opts
.noreorder
)
1926 unsigned long old_frag_offset
;
1928 struct insn_label_list
*l
;
1930 old_frag
= frag_now
;
1931 old_frag_offset
= frag_now_fix ();
1933 for (i
= 0; i
< nops
; i
++)
1938 listing_prev_line ();
1939 /* We may be at the start of a variant frag. In case we
1940 are, make sure there is enough space for the frag
1941 after the frags created by listing_prev_line. The
1942 argument to frag_grow here must be at least as large
1943 as the argument to all other calls to frag_grow in
1944 this file. We don't have to worry about being in the
1945 middle of a variant frag, because the variants insert
1946 all needed nop instructions themselves. */
1950 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1954 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1955 symbol_set_frag (l
->label
, frag_now
);
1956 val
= (valueT
) frag_now_fix ();
1957 /* mips16 text labels are stored as odd. */
1958 if (mips_opts
.mips16
)
1960 S_SET_VALUE (l
->label
, val
);
1963 #ifndef NO_ECOFF_DEBUGGING
1964 if (ECOFF_DEBUGGING
)
1965 ecoff_fix_loc (old_frag
, old_frag_offset
);
1968 else if (prev_nop_frag
!= NULL
)
1970 /* We have a frag holding nops we may be able to remove. If
1971 we don't need any nops, we can decrease the size of
1972 prev_nop_frag by the size of one instruction. If we do
1973 need some nops, we count them in prev_nops_required. */
1974 if (prev_nop_frag_since
== 0)
1978 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1979 --prev_nop_frag_holds
;
1982 prev_nop_frag_required
+= nops
;
1986 if (prev_prev_nop
== 0)
1988 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1989 --prev_nop_frag_holds
;
1992 ++prev_nop_frag_required
;
1995 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1996 prev_nop_frag
= NULL
;
1998 ++prev_nop_frag_since
;
2000 /* Sanity check: by the time we reach the second instruction
2001 after prev_nop_frag, we should have used up all the nops
2002 one way or another. */
2003 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2009 && ((*reloc_type
== BFD_RELOC_16_PCREL
2010 && address_expr
->X_op
!= O_constant
)
2011 || *reloc_type
== BFD_RELOC_16_PCREL_S2
)
2012 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2013 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2014 && mips_relax_branch
2015 /* Don't try branch relaxation within .set nomacro, or within
2016 .set noat if we use $at for PIC computations. If it turns
2017 out that the branch was out-of-range, we'll get an error. */
2018 && !mips_opts
.warn_about_macros
2019 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2020 && !mips_opts
.mips16
)
2022 f
= frag_var (rs_machine_dependent
,
2023 relaxed_branch_length
2025 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2026 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2028 (*reloc_type
== BFD_RELOC_16_PCREL_S2
,
2029 pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2030 pinfo
& INSN_COND_BRANCH_LIKELY
,
2031 pinfo
& INSN_WRITE_GPR_31
,
2033 address_expr
->X_add_symbol
,
2034 address_expr
->X_add_number
,
2036 *reloc_type
= BFD_RELOC_UNUSED
;
2038 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2040 /* We need to set up a variant frag. */
2041 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2042 f
= frag_var (rs_machine_dependent
, 4, 0,
2043 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2044 mips16_small
, mips16_ext
,
2046 & INSN_UNCOND_BRANCH_DELAY
),
2047 (*prev_insn_reloc_type
2048 == BFD_RELOC_MIPS16_JMP
)),
2049 make_expr_symbol (address_expr
), 0, NULL
);
2051 else if (place
!= NULL
)
2053 else if (mips_opts
.mips16
2055 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2057 /* Make sure there is enough room to swap this instruction with
2058 a following jump instruction. */
2064 if (mips_opts
.mips16
2065 && mips_opts
.noreorder
2066 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2067 as_warn (_("extended instruction in delay slot"));
2072 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2073 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2075 if (address_expr
->X_op
== O_constant
)
2079 switch (*reloc_type
)
2082 ip
->insn_opcode
|= address_expr
->X_add_number
;
2085 case BFD_RELOC_MIPS_HIGHEST
:
2086 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2088 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2091 case BFD_RELOC_MIPS_HIGHER
:
2092 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2093 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2096 case BFD_RELOC_HI16_S
:
2097 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2101 case BFD_RELOC_HI16
:
2102 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2105 case BFD_RELOC_LO16
:
2106 case BFD_RELOC_MIPS_GOT_DISP
:
2107 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2110 case BFD_RELOC_MIPS_JMP
:
2111 if ((address_expr
->X_add_number
& 3) != 0)
2112 as_bad (_("jump to misaligned address (0x%lx)"),
2113 (unsigned long) address_expr
->X_add_number
);
2114 if (address_expr
->X_add_number
& ~0xfffffff)
2115 as_bad (_("jump address range overflow (0x%lx)"),
2116 (unsigned long) address_expr
->X_add_number
);
2117 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2120 case BFD_RELOC_MIPS16_JMP
:
2121 if ((address_expr
->X_add_number
& 3) != 0)
2122 as_bad (_("jump to misaligned address (0x%lx)"),
2123 (unsigned long) address_expr
->X_add_number
);
2124 if (address_expr
->X_add_number
& ~0xfffffff)
2125 as_bad (_("jump address range overflow (0x%lx)"),
2126 (unsigned long) address_expr
->X_add_number
);
2128 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2129 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2130 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2133 case BFD_RELOC_16_PCREL
:
2134 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2137 case BFD_RELOC_16_PCREL_S2
:
2147 /* Don't generate a reloc if we are writing into a variant frag. */
2150 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2152 (*reloc_type
== BFD_RELOC_16_PCREL
2153 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
2156 /* These relocations can have an addend that won't fit in
2157 4 octets for 64bit assembly. */
2158 if (HAVE_64BIT_GPRS
&&
2159 (*reloc_type
== BFD_RELOC_16
2160 || *reloc_type
== BFD_RELOC_32
2161 || *reloc_type
== BFD_RELOC_MIPS_JMP
2162 || *reloc_type
== BFD_RELOC_HI16_S
2163 || *reloc_type
== BFD_RELOC_LO16
2164 || *reloc_type
== BFD_RELOC_GPREL16
2165 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2166 || *reloc_type
== BFD_RELOC_GPREL32
2167 || *reloc_type
== BFD_RELOC_64
2168 || *reloc_type
== BFD_RELOC_CTOR
2169 || *reloc_type
== BFD_RELOC_MIPS_SUB
2170 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2171 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2172 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2173 || *reloc_type
== BFD_RELOC_MIPS_REL16
2174 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2175 fixp
[0]->fx_no_overflow
= 1;
2179 struct mips_hi_fixup
*hi_fixup
;
2181 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2182 hi_fixup
= ((struct mips_hi_fixup
*)
2183 xmalloc (sizeof (struct mips_hi_fixup
)));
2184 hi_fixup
->fixp
= fixp
[0];
2185 hi_fixup
->seg
= now_seg
;
2186 hi_fixup
->next
= mips_hi_fixup_list
;
2187 mips_hi_fixup_list
= hi_fixup
;
2190 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2192 /* FIXME: This symbol can be one of
2193 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2194 address_expr
->X_op
= O_absent
;
2195 address_expr
->X_add_symbol
= 0;
2196 address_expr
->X_add_number
= 0;
2198 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2199 4, address_expr
, FALSE
,
2202 /* These relocations can have an addend that won't fit in
2203 4 octets for 64bit assembly. */
2204 if (HAVE_64BIT_GPRS
&&
2205 (*reloc_type
== BFD_RELOC_16
2206 || *reloc_type
== BFD_RELOC_32
2207 || *reloc_type
== BFD_RELOC_MIPS_JMP
2208 || *reloc_type
== BFD_RELOC_HI16_S
2209 || *reloc_type
== BFD_RELOC_LO16
2210 || *reloc_type
== BFD_RELOC_GPREL16
2211 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2212 || *reloc_type
== BFD_RELOC_GPREL32
2213 || *reloc_type
== BFD_RELOC_64
2214 || *reloc_type
== BFD_RELOC_CTOR
2215 || *reloc_type
== BFD_RELOC_MIPS_SUB
2216 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2217 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2218 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2219 || *reloc_type
== BFD_RELOC_MIPS_REL16
2220 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2221 fixp
[1]->fx_no_overflow
= 1;
2223 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2225 address_expr
->X_op
= O_absent
;
2226 address_expr
->X_add_symbol
= 0;
2227 address_expr
->X_add_number
= 0;
2229 fixp
[2] = fix_new_exp (frag_now
,
2230 f
- frag_now
->fr_literal
, 4,
2231 address_expr
, FALSE
,
2234 /* These relocations can have an addend that won't fit in
2235 4 octets for 64bit assembly. */
2236 if (HAVE_64BIT_GPRS
&&
2237 (*reloc_type
== BFD_RELOC_16
2238 || *reloc_type
== BFD_RELOC_32
2239 || *reloc_type
== BFD_RELOC_MIPS_JMP
2240 || *reloc_type
== BFD_RELOC_HI16_S
2241 || *reloc_type
== BFD_RELOC_LO16
2242 || *reloc_type
== BFD_RELOC_GPREL16
2243 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2244 || *reloc_type
== BFD_RELOC_GPREL32
2245 || *reloc_type
== BFD_RELOC_64
2246 || *reloc_type
== BFD_RELOC_CTOR
2247 || *reloc_type
== BFD_RELOC_MIPS_SUB
2248 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2249 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2250 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2251 || *reloc_type
== BFD_RELOC_MIPS_REL16
2252 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2253 fixp
[2]->fx_no_overflow
= 1;
2260 if (! mips_opts
.mips16
)
2262 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2264 dwarf2_emit_insn (4);
2267 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2269 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2270 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2272 dwarf2_emit_insn (4);
2279 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2282 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2284 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2288 /* Update the register mask information. */
2289 if (! mips_opts
.mips16
)
2291 if (pinfo
& INSN_WRITE_GPR_D
)
2292 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2293 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2294 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2295 if (pinfo
& INSN_READ_GPR_S
)
2296 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2297 if (pinfo
& INSN_WRITE_GPR_31
)
2298 mips_gprmask
|= 1 << RA
;
2299 if (pinfo
& INSN_WRITE_FPR_D
)
2300 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2301 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2302 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2303 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2304 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2305 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2306 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2307 if (pinfo
& INSN_COP
)
2309 /* We don't keep enough information to sort these cases out.
2310 The itbl support does keep this information however, although
2311 we currently don't support itbl fprmats as part of the cop
2312 instruction. May want to add this support in the future. */
2314 /* Never set the bit for $0, which is always zero. */
2315 mips_gprmask
&= ~1 << 0;
2319 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2320 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2321 & MIPS16OP_MASK_RX
);
2322 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2323 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2324 & MIPS16OP_MASK_RY
);
2325 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2326 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2327 & MIPS16OP_MASK_RZ
);
2328 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2329 mips_gprmask
|= 1 << TREG
;
2330 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2331 mips_gprmask
|= 1 << SP
;
2332 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2333 mips_gprmask
|= 1 << RA
;
2334 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2335 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2336 if (pinfo
& MIPS16_INSN_READ_Z
)
2337 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2338 & MIPS16OP_MASK_MOVE32Z
);
2339 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2340 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2341 & MIPS16OP_MASK_REGR32
);
2344 if (place
== NULL
&& ! mips_opts
.noreorder
)
2346 /* Filling the branch delay slot is more complex. We try to
2347 switch the branch with the previous instruction, which we can
2348 do if the previous instruction does not set up a condition
2349 that the branch tests and if the branch is not itself the
2350 target of any branch. */
2351 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2352 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2354 if (mips_optimize
< 2
2355 /* If we have seen .set volatile or .set nomove, don't
2357 || mips_opts
.nomove
!= 0
2358 /* If we had to emit any NOP instructions, then we
2359 already know we can not swap. */
2361 /* If we don't even know the previous insn, we can not
2363 || ! prev_insn_valid
2364 /* If the previous insn is already in a branch delay
2365 slot, then we can not swap. */
2366 || prev_insn_is_delay_slot
2367 /* If the previous previous insn was in a .set
2368 noreorder, we can't swap. Actually, the MIPS
2369 assembler will swap in this situation. However, gcc
2370 configured -with-gnu-as will generate code like
2376 in which we can not swap the bne and INSN. If gcc is
2377 not configured -with-gnu-as, it does not output the
2378 .set pseudo-ops. We don't have to check
2379 prev_insn_unreordered, because prev_insn_valid will
2380 be 0 in that case. We don't want to use
2381 prev_prev_insn_valid, because we do want to be able
2382 to swap at the start of a function. */
2383 || prev_prev_insn_unreordered
2384 /* If the branch is itself the target of a branch, we
2385 can not swap. We cheat on this; all we check for is
2386 whether there is a label on this instruction. If
2387 there are any branches to anything other than a
2388 label, users must use .set noreorder. */
2389 || insn_labels
!= NULL
2390 /* If the previous instruction is in a variant frag, we
2391 can not do the swap. This does not apply to the
2392 mips16, which uses variant frags for different
2394 || (! mips_opts
.mips16
2395 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2396 /* If the branch reads the condition codes, we don't
2397 even try to swap, because in the sequence
2402 we can not swap, and I don't feel like handling that
2404 || (! mips_opts
.mips16
2405 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2406 && (pinfo
& INSN_READ_COND_CODE
))
2407 /* We can not swap with an instruction that requires a
2408 delay slot, becase the target of the branch might
2409 interfere with that instruction. */
2410 || (! mips_opts
.mips16
2411 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2413 /* Itbl support may require additional care here. */
2414 & (INSN_LOAD_COPROC_DELAY
2415 | INSN_COPROC_MOVE_DELAY
2416 | INSN_WRITE_COND_CODE
)))
2417 || (! (hilo_interlocks
2418 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2422 || (! mips_opts
.mips16
2424 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2425 || (! mips_opts
.mips16
2426 && mips_opts
.isa
== ISA_MIPS1
2427 /* Itbl support may require additional care here. */
2428 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2429 /* We can not swap with a branch instruction. */
2431 & (INSN_UNCOND_BRANCH_DELAY
2432 | INSN_COND_BRANCH_DELAY
2433 | INSN_COND_BRANCH_LIKELY
))
2434 /* We do not swap with a trap instruction, since it
2435 complicates trap handlers to have the trap
2436 instruction be in a delay slot. */
2437 || (prev_pinfo
& INSN_TRAP
)
2438 /* If the branch reads a register that the previous
2439 instruction sets, we can not swap. */
2440 || (! mips_opts
.mips16
2441 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2442 && insn_uses_reg (ip
,
2443 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2446 || (! mips_opts
.mips16
2447 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2448 && insn_uses_reg (ip
,
2449 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2452 || (mips_opts
.mips16
2453 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2454 && insn_uses_reg (ip
,
2455 ((prev_insn
.insn_opcode
2457 & MIPS16OP_MASK_RX
),
2459 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2460 && insn_uses_reg (ip
,
2461 ((prev_insn
.insn_opcode
2463 & MIPS16OP_MASK_RY
),
2465 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2466 && insn_uses_reg (ip
,
2467 ((prev_insn
.insn_opcode
2469 & MIPS16OP_MASK_RZ
),
2471 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2472 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2473 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2474 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2475 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2476 && insn_uses_reg (ip
,
2477 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2480 /* If the branch writes a register that the previous
2481 instruction sets, we can not swap (we know that
2482 branches write only to RD or to $31). */
2483 || (! mips_opts
.mips16
2484 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2485 && (((pinfo
& INSN_WRITE_GPR_D
)
2486 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2487 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2488 || ((pinfo
& INSN_WRITE_GPR_31
)
2489 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2492 || (! mips_opts
.mips16
2493 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2494 && (((pinfo
& INSN_WRITE_GPR_D
)
2495 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2496 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2497 || ((pinfo
& INSN_WRITE_GPR_31
)
2498 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2501 || (mips_opts
.mips16
2502 && (pinfo
& MIPS16_INSN_WRITE_31
)
2503 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2504 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2505 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2507 /* If the branch writes a register that the previous
2508 instruction reads, we can not swap (we know that
2509 branches only write to RD or to $31). */
2510 || (! mips_opts
.mips16
2511 && (pinfo
& INSN_WRITE_GPR_D
)
2512 && insn_uses_reg (&prev_insn
,
2513 ((ip
->insn_opcode
>> OP_SH_RD
)
2516 || (! mips_opts
.mips16
2517 && (pinfo
& INSN_WRITE_GPR_31
)
2518 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2519 || (mips_opts
.mips16
2520 && (pinfo
& MIPS16_INSN_WRITE_31
)
2521 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2522 /* If we are generating embedded PIC code, the branch
2523 might be expanded into a sequence which uses $at, so
2524 we can't swap with an instruction which reads it. */
2525 || (mips_pic
== EMBEDDED_PIC
2526 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2527 /* If the previous previous instruction has a load
2528 delay, and sets a register that the branch reads, we
2530 || (! mips_opts
.mips16
2531 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2532 /* Itbl support may require additional care here. */
2533 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2534 || (! gpr_interlocks
2535 && (prev_prev_insn
.insn_mo
->pinfo
2536 & INSN_LOAD_MEMORY_DELAY
)))
2537 && insn_uses_reg (ip
,
2538 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2541 /* If one instruction sets a condition code and the
2542 other one uses a condition code, we can not swap. */
2543 || ((pinfo
& INSN_READ_COND_CODE
)
2544 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2545 || ((pinfo
& INSN_WRITE_COND_CODE
)
2546 && (prev_pinfo
& INSN_READ_COND_CODE
))
2547 /* If the previous instruction uses the PC, we can not
2549 || (mips_opts
.mips16
2550 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2551 /* If the previous instruction was extended, we can not
2553 || (mips_opts
.mips16
&& prev_insn_extended
)
2554 /* If the previous instruction had a fixup in mips16
2555 mode, we can not swap. This normally means that the
2556 previous instruction was a 4 byte branch anyhow. */
2557 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2558 /* If the previous instruction is a sync, sync.l, or
2559 sync.p, we can not swap. */
2560 || (prev_pinfo
& INSN_SYNC
))
2562 /* We could do even better for unconditional branches to
2563 portions of this object file; we could pick up the
2564 instruction at the destination, put it in the delay
2565 slot, and bump the destination address. */
2567 /* Update the previous insn information. */
2568 prev_prev_insn
= *ip
;
2569 prev_insn
.insn_mo
= &dummy_opcode
;
2573 /* It looks like we can actually do the swap. */
2574 if (! mips_opts
.mips16
)
2579 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2580 memcpy (temp
, prev_f
, 4);
2581 memcpy (prev_f
, f
, 4);
2582 memcpy (f
, temp
, 4);
2583 if (prev_insn_fixp
[0])
2585 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2586 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2588 if (prev_insn_fixp
[1])
2590 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2591 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2593 if (prev_insn_fixp
[2])
2595 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2596 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2600 fixp
[0]->fx_frag
= prev_insn_frag
;
2601 fixp
[0]->fx_where
= prev_insn_where
;
2605 fixp
[1]->fx_frag
= prev_insn_frag
;
2606 fixp
[1]->fx_where
= prev_insn_where
;
2610 fixp
[2]->fx_frag
= prev_insn_frag
;
2611 fixp
[2]->fx_where
= prev_insn_where
;
2619 assert (prev_insn_fixp
[0] == NULL
);
2620 assert (prev_insn_fixp
[1] == NULL
);
2621 assert (prev_insn_fixp
[2] == NULL
);
2622 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2623 memcpy (temp
, prev_f
, 2);
2624 memcpy (prev_f
, f
, 2);
2625 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2627 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2628 memcpy (f
, temp
, 2);
2632 memcpy (f
, f
+ 2, 2);
2633 memcpy (f
+ 2, temp
, 2);
2637 fixp
[0]->fx_frag
= prev_insn_frag
;
2638 fixp
[0]->fx_where
= prev_insn_where
;
2642 fixp
[1]->fx_frag
= prev_insn_frag
;
2643 fixp
[1]->fx_where
= prev_insn_where
;
2647 fixp
[2]->fx_frag
= prev_insn_frag
;
2648 fixp
[2]->fx_where
= prev_insn_where
;
2652 /* Update the previous insn information; leave prev_insn
2654 prev_prev_insn
= *ip
;
2656 prev_insn_is_delay_slot
= 1;
2658 /* If that was an unconditional branch, forget the previous
2659 insn information. */
2660 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2662 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2663 prev_insn
.insn_mo
= &dummy_opcode
;
2666 prev_insn_fixp
[0] = NULL
;
2667 prev_insn_fixp
[1] = NULL
;
2668 prev_insn_fixp
[2] = NULL
;
2669 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2670 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2671 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2672 prev_insn_extended
= 0;
2674 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2676 /* We don't yet optimize a branch likely. What we should do
2677 is look at the target, copy the instruction found there
2678 into the delay slot, and increment the branch to jump to
2679 the next instruction. */
2681 /* Update the previous insn information. */
2682 prev_prev_insn
= *ip
;
2683 prev_insn
.insn_mo
= &dummy_opcode
;
2684 prev_insn_fixp
[0] = NULL
;
2685 prev_insn_fixp
[1] = NULL
;
2686 prev_insn_fixp
[2] = NULL
;
2687 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2688 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2689 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2690 prev_insn_extended
= 0;
2694 /* Update the previous insn information. */
2696 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2698 prev_prev_insn
= prev_insn
;
2701 /* Any time we see a branch, we always fill the delay slot
2702 immediately; since this insn is not a branch, we know it
2703 is not in a delay slot. */
2704 prev_insn_is_delay_slot
= 0;
2706 prev_insn_fixp
[0] = fixp
[0];
2707 prev_insn_fixp
[1] = fixp
[1];
2708 prev_insn_fixp
[2] = fixp
[2];
2709 prev_insn_reloc_type
[0] = reloc_type
[0];
2710 prev_insn_reloc_type
[1] = reloc_type
[1];
2711 prev_insn_reloc_type
[2] = reloc_type
[2];
2712 if (mips_opts
.mips16
)
2713 prev_insn_extended
= (ip
->use_extend
2714 || *reloc_type
> BFD_RELOC_UNUSED
);
2717 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2718 prev_insn_unreordered
= 0;
2719 prev_insn_frag
= frag_now
;
2720 prev_insn_where
= f
- frag_now
->fr_literal
;
2721 prev_insn_valid
= 1;
2723 else if (place
== NULL
)
2725 /* We need to record a bit of information even when we are not
2726 reordering, in order to determine the base address for mips16
2727 PC relative relocs. */
2728 prev_prev_insn
= prev_insn
;
2730 prev_insn_reloc_type
[0] = reloc_type
[0];
2731 prev_insn_reloc_type
[1] = reloc_type
[1];
2732 prev_insn_reloc_type
[2] = reloc_type
[2];
2733 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2734 prev_insn_unreordered
= 1;
2737 /* We just output an insn, so the next one doesn't have a label. */
2738 mips_clear_insn_labels ();
2740 /* We must ensure that a fixup associated with an unmatched %hi
2741 reloc does not become a variant frag. Otherwise, the
2742 rearrangement of %hi relocs in frob_file may confuse
2746 frag_wane (frag_now
);
2751 /* This function forgets that there was any previous instruction or
2752 label. If PRESERVE is non-zero, it remembers enough information to
2753 know whether nops are needed before a noreorder section. */
2756 mips_no_prev_insn (preserve
)
2761 prev_insn
.insn_mo
= &dummy_opcode
;
2762 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2763 prev_nop_frag
= NULL
;
2764 prev_nop_frag_holds
= 0;
2765 prev_nop_frag_required
= 0;
2766 prev_nop_frag_since
= 0;
2768 prev_insn_valid
= 0;
2769 prev_insn_is_delay_slot
= 0;
2770 prev_insn_unreordered
= 0;
2771 prev_insn_extended
= 0;
2772 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2773 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2774 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2775 prev_prev_insn_unreordered
= 0;
2776 mips_clear_insn_labels ();
2779 /* This function must be called whenever we turn on noreorder or emit
2780 something other than instructions. It inserts any NOPS which might
2781 be needed by the previous instruction, and clears the information
2782 kept for the previous instructions. The INSNS parameter is true if
2783 instructions are to follow. */
2786 mips_emit_delays (insns
)
2789 if (! mips_opts
.noreorder
)
2794 if ((! mips_opts
.mips16
2795 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2796 && (! cop_interlocks
2797 && (prev_insn
.insn_mo
->pinfo
2798 & (INSN_LOAD_COPROC_DELAY
2799 | INSN_COPROC_MOVE_DELAY
2800 | INSN_WRITE_COND_CODE
))))
2801 || (! hilo_interlocks
2802 && (prev_insn
.insn_mo
->pinfo
2805 || (! mips_opts
.mips16
2807 && (prev_insn
.insn_mo
->pinfo
2808 & INSN_LOAD_MEMORY_DELAY
))
2809 || (! mips_opts
.mips16
2810 && mips_opts
.isa
== ISA_MIPS1
2811 && (prev_insn
.insn_mo
->pinfo
2812 & INSN_COPROC_MEMORY_DELAY
)))
2814 /* Itbl support may require additional care here. */
2816 if ((! mips_opts
.mips16
2817 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2818 && (! cop_interlocks
2819 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2820 || (! hilo_interlocks
2821 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2822 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2825 if (prev_insn_unreordered
)
2828 else if ((! mips_opts
.mips16
2829 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2830 && (! cop_interlocks
2831 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2832 || (! hilo_interlocks
2833 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2834 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2836 /* Itbl support may require additional care here. */
2837 if (! prev_prev_insn_unreordered
)
2841 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2844 const char *pn
= prev_insn
.insn_mo
->name
;
2845 if (strncmp(pn
, "macc", 4) == 0
2846 || strncmp(pn
, "dmacc", 5) == 0
2847 || strncmp(pn
, "dmult", 5) == 0)
2851 if (nops
< min_nops
)
2857 struct insn_label_list
*l
;
2861 /* Record the frag which holds the nop instructions, so
2862 that we can remove them if we don't need them. */
2863 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2864 prev_nop_frag
= frag_now
;
2865 prev_nop_frag_holds
= nops
;
2866 prev_nop_frag_required
= 0;
2867 prev_nop_frag_since
= 0;
2870 for (; nops
> 0; --nops
)
2875 /* Move on to a new frag, so that it is safe to simply
2876 decrease the size of prev_nop_frag. */
2877 frag_wane (frag_now
);
2881 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2885 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2886 symbol_set_frag (l
->label
, frag_now
);
2887 val
= (valueT
) frag_now_fix ();
2888 /* mips16 text labels are stored as odd. */
2889 if (mips_opts
.mips16
)
2891 S_SET_VALUE (l
->label
, val
);
2896 /* Mark instruction labels in mips16 mode. */
2898 mips16_mark_labels ();
2900 mips_no_prev_insn (insns
);
2903 /* Build an instruction created by a macro expansion. This is passed
2904 a pointer to the count of instructions created so far, an
2905 expression, the name of the instruction to build, an operand format
2906 string, and corresponding arguments. */
2910 macro_build (char *place
,
2918 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2927 struct mips_cl_insn insn
;
2928 bfd_reloc_code_real_type r
[3];
2932 va_start (args
, fmt
);
2938 * If the macro is about to expand into a second instruction,
2939 * print a warning if needed. We need to pass ip as a parameter
2940 * to generate a better warning message here...
2942 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2943 as_warn (_("Macro instruction expanded into multiple instructions"));
2946 * If the macro is about to expand into a second instruction,
2947 * and it is in a delay slot, print a warning.
2951 && mips_opts
.noreorder
2952 && (prev_prev_insn
.insn_mo
->pinfo
2953 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2954 | INSN_COND_BRANCH_LIKELY
)) != 0)
2955 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2958 ++*counter
; /* bump instruction counter */
2960 if (mips_opts
.mips16
)
2962 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2967 r
[0] = BFD_RELOC_UNUSED
;
2968 r
[1] = BFD_RELOC_UNUSED
;
2969 r
[2] = BFD_RELOC_UNUSED
;
2970 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2971 assert (insn
.insn_mo
);
2972 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2974 /* Search until we get a match for NAME. */
2977 /* It is assumed here that macros will never generate
2978 MDMX or MIPS-3D instructions. */
2979 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2980 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2981 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2983 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2985 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2989 assert (insn
.insn_mo
->name
);
2990 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2993 insn
.insn_opcode
= insn
.insn_mo
->match
;
3009 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3013 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3018 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3023 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3028 int tmp
= va_arg (args
, int);
3030 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3031 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3037 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3044 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3048 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3052 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3056 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3060 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3067 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3073 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3074 assert (*r
== BFD_RELOC_GPREL16
3075 || *r
== BFD_RELOC_MIPS_LITERAL
3076 || *r
== BFD_RELOC_MIPS_HIGHER
3077 || *r
== BFD_RELOC_HI16_S
3078 || *r
== BFD_RELOC_LO16
3079 || *r
== BFD_RELOC_MIPS_GOT16
3080 || *r
== BFD_RELOC_MIPS_CALL16
3081 || *r
== BFD_RELOC_MIPS_GOT_DISP
3082 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3083 || *r
== BFD_RELOC_MIPS_GOT_OFST
3084 || *r
== BFD_RELOC_MIPS_GOT_LO16
3085 || *r
== BFD_RELOC_MIPS_CALL_LO16
3086 || (ep
->X_op
== O_subtract
3087 && *r
== BFD_RELOC_PCREL_LO16
));
3091 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3093 && (ep
->X_op
== O_constant
3094 || (ep
->X_op
== O_symbol
3095 && (*r
== BFD_RELOC_MIPS_HIGHEST
3096 || *r
== BFD_RELOC_HI16_S
3097 || *r
== BFD_RELOC_HI16
3098 || *r
== BFD_RELOC_GPREL16
3099 || *r
== BFD_RELOC_MIPS_GOT_HI16
3100 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3101 || (ep
->X_op
== O_subtract
3102 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3106 assert (ep
!= NULL
);
3108 * This allows macro() to pass an immediate expression for
3109 * creating short branches without creating a symbol.
3110 * Note that the expression still might come from the assembly
3111 * input, in which case the value is not checked for range nor
3112 * is a relocation entry generated (yuck).
3114 if (ep
->X_op
== O_constant
)
3116 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3120 if (mips_pic
== EMBEDDED_PIC
)
3121 *r
= BFD_RELOC_16_PCREL_S2
;
3123 *r
= BFD_RELOC_16_PCREL
;
3127 assert (ep
!= NULL
);
3128 *r
= BFD_RELOC_MIPS_JMP
;
3132 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3141 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3143 append_insn (place
, &insn
, ep
, r
, FALSE
);
3147 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3149 int *counter ATTRIBUTE_UNUSED
;
3155 struct mips_cl_insn insn
;
3156 bfd_reloc_code_real_type r
[3]
3157 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3159 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3160 assert (insn
.insn_mo
);
3161 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3163 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3164 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3167 assert (insn
.insn_mo
->name
);
3168 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3171 insn
.insn_opcode
= insn
.insn_mo
->match
;
3172 insn
.use_extend
= FALSE
;
3191 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3196 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3200 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3204 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3214 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3221 regno
= va_arg (args
, int);
3222 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3223 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3244 assert (ep
!= NULL
);
3246 if (ep
->X_op
!= O_constant
)
3247 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3250 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3251 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3254 *r
= BFD_RELOC_UNUSED
;
3260 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3267 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3269 append_insn (place
, &insn
, ep
, r
, FALSE
);
3273 * Generate a "jalr" instruction with a relocation hint to the called
3274 * function. This occurs in NewABI PIC code.
3277 macro_build_jalr (icnt
, ep
)
3288 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3291 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3292 0, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3296 * Generate a "lui" instruction.
3299 macro_build_lui (place
, counter
, ep
, regnum
)
3305 expressionS high_expr
;
3306 struct mips_cl_insn insn
;
3307 bfd_reloc_code_real_type r
[3]
3308 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3309 const char *name
= "lui";
3310 const char *fmt
= "t,u";
3312 assert (! mips_opts
.mips16
);
3318 high_expr
.X_op
= O_constant
;
3319 high_expr
.X_add_number
= ep
->X_add_number
;
3322 if (high_expr
.X_op
== O_constant
)
3324 /* we can compute the instruction now without a relocation entry */
3325 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3327 *r
= BFD_RELOC_UNUSED
;
3331 assert (ep
->X_op
== O_symbol
);
3332 /* _gp_disp is a special case, used from s_cpload. */
3333 assert (mips_pic
== NO_PIC
3335 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3336 *r
= BFD_RELOC_HI16_S
;
3340 * If the macro is about to expand into a second instruction,
3341 * print a warning if needed. We need to pass ip as a parameter
3342 * to generate a better warning message here...
3344 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3345 as_warn (_("Macro instruction expanded into multiple instructions"));
3348 ++*counter
; /* bump instruction counter */
3350 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3351 assert (insn
.insn_mo
);
3352 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3353 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3355 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3356 if (*r
== BFD_RELOC_UNUSED
)
3358 insn
.insn_opcode
|= high_expr
.X_add_number
;
3359 append_insn (place
, &insn
, NULL
, r
, FALSE
);
3362 append_insn (place
, &insn
, &high_expr
, r
, FALSE
);
3365 /* Generate a sequence of instructions to do a load or store from a constant
3366 offset off of a base register (breg) into/from a target register (treg),
3367 using AT if necessary. */
3369 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3376 assert (ep
->X_op
== O_constant
);
3378 /* Right now, this routine can only handle signed 32-bit contants. */
3379 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3380 as_warn (_("operand overflow"));
3382 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3384 /* Signed 16-bit offset will fit in the op. Easy! */
3385 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3386 (int) BFD_RELOC_LO16
, breg
);
3390 /* 32-bit offset, need multiple instructions and AT, like:
3391 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3392 addu $tempreg,$tempreg,$breg
3393 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3394 to handle the complete offset. */
3395 macro_build_lui (place
, counter
, ep
, AT
);
3398 macro_build (place
, counter
, (expressionS
*) NULL
,
3399 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3400 "d,v,t", AT
, AT
, breg
);
3403 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3404 (int) BFD_RELOC_LO16
, AT
);
3407 as_warn (_("Macro used $at after \".set noat\""));
3412 * Generates code to set the $at register to true (one)
3413 * if reg is less than the immediate expression.
3416 set_at (counter
, reg
, unsignedp
)
3421 if (imm_expr
.X_op
== O_constant
3422 && imm_expr
.X_add_number
>= -0x8000
3423 && imm_expr
.X_add_number
< 0x8000)
3424 macro_build ((char *) NULL
, counter
, &imm_expr
,
3425 unsignedp
? "sltiu" : "slti",
3426 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3429 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3430 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3431 unsignedp
? "sltu" : "slt",
3432 "d,v,t", AT
, reg
, AT
);
3436 /* Warn if an expression is not a constant. */
3439 check_absolute_expr (ip
, ex
)
3440 struct mips_cl_insn
*ip
;
3443 if (ex
->X_op
== O_big
)
3444 as_bad (_("unsupported large constant"));
3445 else if (ex
->X_op
!= O_constant
)
3446 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3449 /* Count the leading zeroes by performing a binary chop. This is a
3450 bulky bit of source, but performance is a LOT better for the
3451 majority of values than a simple loop to count the bits:
3452 for (lcnt = 0; (lcnt < 32); lcnt++)
3453 if ((v) & (1 << (31 - lcnt)))
3455 However it is not code size friendly, and the gain will drop a bit
3456 on certain cached systems.
3458 #define COUNT_TOP_ZEROES(v) \
3459 (((v) & ~0xffff) == 0 \
3460 ? ((v) & ~0xff) == 0 \
3461 ? ((v) & ~0xf) == 0 \
3462 ? ((v) & ~0x3) == 0 \
3463 ? ((v) & ~0x1) == 0 \
3468 : ((v) & ~0x7) == 0 \
3471 : ((v) & ~0x3f) == 0 \
3472 ? ((v) & ~0x1f) == 0 \
3475 : ((v) & ~0x7f) == 0 \
3478 : ((v) & ~0xfff) == 0 \
3479 ? ((v) & ~0x3ff) == 0 \
3480 ? ((v) & ~0x1ff) == 0 \
3483 : ((v) & ~0x7ff) == 0 \
3486 : ((v) & ~0x3fff) == 0 \
3487 ? ((v) & ~0x1fff) == 0 \
3490 : ((v) & ~0x7fff) == 0 \
3493 : ((v) & ~0xffffff) == 0 \
3494 ? ((v) & ~0xfffff) == 0 \
3495 ? ((v) & ~0x3ffff) == 0 \
3496 ? ((v) & ~0x1ffff) == 0 \
3499 : ((v) & ~0x7ffff) == 0 \
3502 : ((v) & ~0x3fffff) == 0 \
3503 ? ((v) & ~0x1fffff) == 0 \
3506 : ((v) & ~0x7fffff) == 0 \
3509 : ((v) & ~0xfffffff) == 0 \
3510 ? ((v) & ~0x3ffffff) == 0 \
3511 ? ((v) & ~0x1ffffff) == 0 \
3514 : ((v) & ~0x7ffffff) == 0 \
3517 : ((v) & ~0x3fffffff) == 0 \
3518 ? ((v) & ~0x1fffffff) == 0 \
3521 : ((v) & ~0x7fffffff) == 0 \
3526 * This routine generates the least number of instructions neccessary to load
3527 * an absolute expression value into a register.
3530 load_register (counter
, reg
, ep
, dbl
)
3537 expressionS hi32
, lo32
;
3539 if (ep
->X_op
!= O_big
)
3541 assert (ep
->X_op
== O_constant
);
3542 if (ep
->X_add_number
< 0x8000
3543 && (ep
->X_add_number
>= 0
3544 || (ep
->X_add_number
>= -0x8000
3547 || sizeof (ep
->X_add_number
) > 4))))
3549 /* We can handle 16 bit signed values with an addiu to
3550 $zero. No need to ever use daddiu here, since $zero and
3551 the result are always correct in 32 bit mode. */
3552 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3553 (int) BFD_RELOC_LO16
);
3556 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3558 /* We can handle 16 bit unsigned values with an ori to
3560 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3561 (int) BFD_RELOC_LO16
);
3564 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3567 || sizeof (ep
->X_add_number
) > 4
3568 || (ep
->X_add_number
& 0x80000000) == 0))
3569 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3570 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3573 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3574 == ~ (offsetT
) 0xffffffff)))
3576 /* 32 bit values require an lui. */
3577 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3578 (int) BFD_RELOC_HI16
);
3579 if ((ep
->X_add_number
& 0xffff) != 0)
3580 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3581 (int) BFD_RELOC_LO16
);
3586 /* The value is larger than 32 bits. */
3588 if (HAVE_32BIT_GPRS
)
3590 as_bad (_("Number (0x%lx) larger than 32 bits"),
3591 (unsigned long) ep
->X_add_number
);
3592 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3593 (int) BFD_RELOC_LO16
);
3597 if (ep
->X_op
!= O_big
)
3600 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3601 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3602 hi32
.X_add_number
&= 0xffffffff;
3604 lo32
.X_add_number
&= 0xffffffff;
3608 assert (ep
->X_add_number
> 2);
3609 if (ep
->X_add_number
== 3)
3610 generic_bignum
[3] = 0;
3611 else if (ep
->X_add_number
> 4)
3612 as_bad (_("Number larger than 64 bits"));
3613 lo32
.X_op
= O_constant
;
3614 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3615 hi32
.X_op
= O_constant
;
3616 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3619 if (hi32
.X_add_number
== 0)
3624 unsigned long hi
, lo
;
3626 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3628 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3630 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3631 reg
, 0, (int) BFD_RELOC_LO16
);
3634 if (lo32
.X_add_number
& 0x80000000)
3636 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3637 (int) BFD_RELOC_HI16
);
3638 if (lo32
.X_add_number
& 0xffff)
3639 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3640 reg
, reg
, (int) BFD_RELOC_LO16
);
3645 /* Check for 16bit shifted constant. We know that hi32 is
3646 non-zero, so start the mask on the first bit of the hi32
3651 unsigned long himask
, lomask
;
3655 himask
= 0xffff >> (32 - shift
);
3656 lomask
= (0xffff << shift
) & 0xffffffff;
3660 himask
= 0xffff << (shift
- 32);
3663 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3664 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3668 tmp
.X_op
= O_constant
;
3670 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3671 | (lo32
.X_add_number
>> shift
));
3673 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3674 macro_build ((char *) NULL
, counter
, &tmp
,
3675 "ori", "t,r,i", reg
, 0,
3676 (int) BFD_RELOC_LO16
);
3677 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3678 (shift
>= 32) ? "dsll32" : "dsll",
3680 (shift
>= 32) ? shift
- 32 : shift
);
3685 while (shift
<= (64 - 16));
3687 /* Find the bit number of the lowest one bit, and store the
3688 shifted value in hi/lo. */
3689 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3690 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3694 while ((lo
& 1) == 0)
3699 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3705 while ((hi
& 1) == 0)
3714 /* Optimize if the shifted value is a (power of 2) - 1. */
3715 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3716 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3718 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3723 /* This instruction will set the register to be all
3725 tmp
.X_op
= O_constant
;
3726 tmp
.X_add_number
= (offsetT
) -1;
3727 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3728 reg
, 0, (int) BFD_RELOC_LO16
);
3732 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3733 (bit
>= 32) ? "dsll32" : "dsll",
3735 (bit
>= 32) ? bit
- 32 : bit
);
3737 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3738 (shift
>= 32) ? "dsrl32" : "dsrl",
3740 (shift
>= 32) ? shift
- 32 : shift
);
3745 /* Sign extend hi32 before calling load_register, because we can
3746 generally get better code when we load a sign extended value. */
3747 if ((hi32
.X_add_number
& 0x80000000) != 0)
3748 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3749 load_register (counter
, reg
, &hi32
, 0);
3752 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3756 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3757 "dsll32", "d,w,<", reg
, freg
, 0);
3765 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3767 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3768 (int) BFD_RELOC_HI16
);
3769 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3770 "dsrl32", "d,w,<", reg
, reg
, 0);
3776 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3777 "d,w,<", reg
, freg
, 16);
3781 mid16
.X_add_number
>>= 16;
3782 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3783 freg
, (int) BFD_RELOC_LO16
);
3784 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3785 "d,w,<", reg
, reg
, 16);
3788 if ((lo32
.X_add_number
& 0xffff) != 0)
3789 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3790 (int) BFD_RELOC_LO16
);
3793 /* Load an address into a register. */
3796 load_address (counter
, reg
, ep
, used_at
)
3804 if (ep
->X_op
!= O_constant
3805 && ep
->X_op
!= O_symbol
)
3807 as_bad (_("expression too complex"));
3808 ep
->X_op
= O_constant
;
3811 if (ep
->X_op
== O_constant
)
3813 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3817 if (mips_pic
== NO_PIC
)
3819 /* If this is a reference to a GP relative symbol, we want
3820 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3822 lui $reg,<sym> (BFD_RELOC_HI16_S)
3823 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3824 If we have an addend, we always use the latter form.
3826 With 64bit address space and a usable $at we want
3827 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3828 lui $at,<sym> (BFD_RELOC_HI16_S)
3829 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3830 daddiu $at,<sym> (BFD_RELOC_LO16)
3834 If $at is already in use, we use an path which is suboptimal
3835 on superscalar processors.
3836 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3837 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3839 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3841 daddiu $reg,<sym> (BFD_RELOC_LO16)
3843 if (HAVE_64BIT_ADDRESSES
)
3845 /* We don't do GP optimization for now because RELAX_ENCODE can't
3846 hold the data for such large chunks. */
3848 if (*used_at
== 0 && ! mips_opts
.noat
)
3850 macro_build (p
, counter
, ep
, "lui", "t,u",
3851 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3852 macro_build (p
, counter
, ep
, "lui", "t,u",
3853 AT
, (int) BFD_RELOC_HI16_S
);
3854 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3855 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3856 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3857 AT
, AT
, (int) BFD_RELOC_LO16
);
3858 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3859 "d,w,<", reg
, reg
, 0);
3860 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3861 "d,v,t", reg
, reg
, AT
);
3866 macro_build (p
, counter
, ep
, "lui", "t,u",
3867 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3868 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3869 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3870 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3871 "d,w,<", reg
, reg
, 16);
3872 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3873 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3874 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3875 "d,w,<", reg
, reg
, 16);
3876 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3877 reg
, reg
, (int) BFD_RELOC_LO16
);
3882 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3883 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3886 macro_build ((char *) NULL
, counter
, ep
,
3887 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3888 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3889 p
= frag_var (rs_machine_dependent
, 8, 0,
3890 RELAX_ENCODE (4, 8, 0, 4, 0,
3891 mips_opts
.warn_about_macros
),
3892 ep
->X_add_symbol
, 0, NULL
);
3894 macro_build_lui (p
, counter
, ep
, reg
);
3897 macro_build (p
, counter
, ep
,
3898 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3899 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3902 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3906 /* If this is a reference to an external symbol, we want
3907 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3909 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3911 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3912 If we have NewABI, we want
3913 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3914 If there is a constant, it must be added in after. */
3915 ex
.X_add_number
= ep
->X_add_number
;
3916 ep
->X_add_number
= 0;
3920 macro_build ((char *) NULL
, counter
, ep
,
3921 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3922 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3926 macro_build ((char *) NULL
, counter
, ep
,
3927 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3928 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3929 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3930 p
= frag_var (rs_machine_dependent
, 4, 0,
3931 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3932 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3933 macro_build (p
, counter
, ep
,
3934 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3935 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3938 if (ex
.X_add_number
!= 0)
3940 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3941 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3942 ex
.X_op
= O_constant
;
3943 macro_build ((char *) NULL
, counter
, &ex
,
3944 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3945 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3948 else if (mips_pic
== SVR4_PIC
)
3953 /* This is the large GOT case. If this is a reference to an
3954 external symbol, we want
3955 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3957 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3958 Otherwise, for a reference to a local symbol, we want
3959 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3961 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3962 If we have NewABI, we want
3963 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3964 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3965 If there is a constant, it must be added in after. */
3966 ex
.X_add_number
= ep
->X_add_number
;
3967 ep
->X_add_number
= 0;
3970 macro_build ((char *) NULL
, counter
, ep
,
3971 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3972 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3973 macro_build (p
, counter
, ep
,
3974 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3975 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
3979 if (reg_needs_delay (mips_gp_register
))
3984 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3985 (int) BFD_RELOC_MIPS_GOT_HI16
);
3986 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3987 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
3988 reg
, mips_gp_register
);
3989 macro_build ((char *) NULL
, counter
, ep
,
3990 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3991 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3992 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3993 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3994 mips_opts
.warn_about_macros
),
3995 ep
->X_add_symbol
, 0, NULL
);
3998 /* We need a nop before loading from $gp. This special
3999 check is required because the lui which starts the main
4000 instruction stream does not refer to $gp, and so will not
4001 insert the nop which may be required. */
4002 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
4005 macro_build (p
, counter
, ep
,
4006 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
4007 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4009 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
4011 macro_build (p
, counter
, ep
,
4012 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4013 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4016 if (ex
.X_add_number
!= 0)
4018 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4019 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4020 ex
.X_op
= O_constant
;
4021 macro_build ((char *) NULL
, counter
, &ex
,
4022 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4023 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4026 else if (mips_pic
== EMBEDDED_PIC
)
4029 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4031 macro_build ((char *) NULL
, counter
, ep
,
4032 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4033 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
4039 /* Move the contents of register SOURCE into register DEST. */
4042 move_register (counter
, dest
, source
)
4047 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4048 HAVE_32BIT_GPRS
? "addu" : "daddu",
4049 "d,v,t", dest
, source
, 0);
4054 * This routine implements the seemingly endless macro or synthesized
4055 * instructions and addressing modes in the mips assembly language. Many
4056 * of these macros are simple and are similar to each other. These could
4057 * probably be handled by some kind of table or grammer aproach instead of
4058 * this verbose method. Others are not simple macros but are more like
4059 * optimizing code generation.
4060 * One interesting optimization is when several store macros appear
4061 * consecutivly that would load AT with the upper half of the same address.
4062 * The ensuing load upper instructions are ommited. This implies some kind
4063 * of global optimization. We currently only optimize within a single macro.
4064 * For many of the load and store macros if the address is specified as a
4065 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4066 * first load register 'at' with zero and use it as the base register. The
4067 * mips assembler simply uses register $zero. Just one tiny optimization
4072 struct mips_cl_insn
*ip
;
4074 register int treg
, sreg
, dreg
, breg
;
4090 bfd_reloc_code_real_type r
;
4091 int hold_mips_optimize
;
4093 assert (! mips_opts
.mips16
);
4095 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4096 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4097 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4098 mask
= ip
->insn_mo
->mask
;
4100 expr1
.X_op
= O_constant
;
4101 expr1
.X_op_symbol
= NULL
;
4102 expr1
.X_add_symbol
= NULL
;
4103 expr1
.X_add_number
= 1;
4115 mips_emit_delays (TRUE
);
4116 ++mips_opts
.noreorder
;
4117 mips_any_noreorder
= 1;
4119 expr1
.X_add_number
= 8;
4120 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4122 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4125 move_register (&icnt
, dreg
, sreg
);
4126 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4127 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4129 --mips_opts
.noreorder
;
4150 if (imm_expr
.X_op
== O_constant
4151 && imm_expr
.X_add_number
>= -0x8000
4152 && imm_expr
.X_add_number
< 0x8000)
4154 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4155 (int) BFD_RELOC_LO16
);
4158 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4159 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4179 if (imm_expr
.X_op
== O_constant
4180 && imm_expr
.X_add_number
>= 0
4181 && imm_expr
.X_add_number
< 0x10000)
4183 if (mask
!= M_NOR_I
)
4184 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4185 sreg
, (int) BFD_RELOC_LO16
);
4188 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4189 treg
, sreg
, (int) BFD_RELOC_LO16
);
4190 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4191 "d,v,t", treg
, treg
, 0);
4196 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4197 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4215 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4217 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4221 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4222 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4230 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4231 likely
? "bgezl" : "bgez", "s,p", sreg
);
4236 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4237 likely
? "blezl" : "blez", "s,p", treg
);
4240 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4242 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4243 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4249 /* check for > max integer */
4250 maxnum
= 0x7fffffff;
4251 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4258 if (imm_expr
.X_op
== O_constant
4259 && imm_expr
.X_add_number
>= maxnum
4260 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4263 /* result is always false */
4267 as_warn (_("Branch %s is always false (nop)"),
4269 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4275 as_warn (_("Branch likely %s is always false"),
4277 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4282 if (imm_expr
.X_op
!= O_constant
)
4283 as_bad (_("Unsupported large constant"));
4284 ++imm_expr
.X_add_number
;
4288 if (mask
== M_BGEL_I
)
4290 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4292 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4293 likely
? "bgezl" : "bgez", "s,p", sreg
);
4296 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4298 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4299 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4302 maxnum
= 0x7fffffff;
4303 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4310 maxnum
= - maxnum
- 1;
4311 if (imm_expr
.X_op
== O_constant
4312 && imm_expr
.X_add_number
<= maxnum
4313 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4316 /* result is always true */
4317 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4318 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4321 set_at (&icnt
, sreg
, 0);
4322 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4323 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4333 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4334 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4337 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4338 "d,v,t", AT
, sreg
, treg
);
4339 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4340 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4348 && imm_expr
.X_op
== O_constant
4349 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4351 if (imm_expr
.X_op
!= O_constant
)
4352 as_bad (_("Unsupported large constant"));
4353 ++imm_expr
.X_add_number
;
4357 if (mask
== M_BGEUL_I
)
4359 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4361 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4363 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4364 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4367 set_at (&icnt
, sreg
, 1);
4368 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4369 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4377 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4378 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4383 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4384 likely
? "bltzl" : "bltz", "s,p", treg
);
4387 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4389 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4390 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4398 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4399 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4404 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4405 "d,v,t", AT
, treg
, sreg
);
4406 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4407 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4415 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4416 likely
? "blezl" : "blez", "s,p", sreg
);
4421 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4422 likely
? "bgezl" : "bgez", "s,p", treg
);
4425 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4427 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4428 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4434 maxnum
= 0x7fffffff;
4435 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4442 if (imm_expr
.X_op
== O_constant
4443 && imm_expr
.X_add_number
>= maxnum
4444 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4446 if (imm_expr
.X_op
!= O_constant
)
4447 as_bad (_("Unsupported large constant"));
4448 ++imm_expr
.X_add_number
;
4452 if (mask
== M_BLTL_I
)
4454 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4456 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4457 likely
? "bltzl" : "bltz", "s,p", sreg
);
4460 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4462 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4463 likely
? "blezl" : "blez", "s,p", sreg
);
4466 set_at (&icnt
, sreg
, 0);
4467 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4468 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4476 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4477 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4482 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4483 "d,v,t", AT
, treg
, sreg
);
4484 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4485 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4493 && imm_expr
.X_op
== O_constant
4494 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4496 if (imm_expr
.X_op
!= O_constant
)
4497 as_bad (_("Unsupported large constant"));
4498 ++imm_expr
.X_add_number
;
4502 if (mask
== M_BLTUL_I
)
4504 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4506 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4508 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4509 likely
? "beql" : "beq",
4513 set_at (&icnt
, sreg
, 1);
4514 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4515 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4523 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4524 likely
? "bltzl" : "bltz", "s,p", sreg
);
4529 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4530 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4533 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4535 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4536 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4546 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4547 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4550 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4553 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4554 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4569 as_warn (_("Divide by zero."));
4571 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4574 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4579 mips_emit_delays (TRUE
);
4580 ++mips_opts
.noreorder
;
4581 mips_any_noreorder
= 1;
4584 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4585 "s,t,q", treg
, 0, 7);
4586 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4587 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4591 expr1
.X_add_number
= 8;
4592 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4593 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4594 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4598 expr1
.X_add_number
= -1;
4599 macro_build ((char *) NULL
, &icnt
, &expr1
,
4600 dbl
? "daddiu" : "addiu",
4601 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4602 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4603 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4606 expr1
.X_add_number
= 1;
4607 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4608 (int) BFD_RELOC_LO16
);
4609 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4610 "d,w,<", AT
, AT
, 31);
4614 expr1
.X_add_number
= 0x80000000;
4615 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4616 (int) BFD_RELOC_HI16
);
4620 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4621 "s,t,q", sreg
, AT
, 6);
4622 /* We want to close the noreorder block as soon as possible, so
4623 that later insns are available for delay slot filling. */
4624 --mips_opts
.noreorder
;
4628 expr1
.X_add_number
= 8;
4629 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4630 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4633 /* We want to close the noreorder block as soon as possible, so
4634 that later insns are available for delay slot filling. */
4635 --mips_opts
.noreorder
;
4637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4640 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4679 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4681 as_warn (_("Divide by zero."));
4683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4686 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4690 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4692 if (strcmp (s2
, "mflo") == 0)
4693 move_register (&icnt
, dreg
, sreg
);
4695 move_register (&icnt
, dreg
, 0);
4698 if (imm_expr
.X_op
== O_constant
4699 && imm_expr
.X_add_number
== -1
4700 && s
[strlen (s
) - 1] != 'u')
4702 if (strcmp (s2
, "mflo") == 0)
4704 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4705 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4708 move_register (&icnt
, dreg
, 0);
4712 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4734 mips_emit_delays (TRUE
);
4735 ++mips_opts
.noreorder
;
4736 mips_any_noreorder
= 1;
4739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4740 "s,t,q", treg
, 0, 7);
4741 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4743 /* We want to close the noreorder block as soon as possible, so
4744 that later insns are available for delay slot filling. */
4745 --mips_opts
.noreorder
;
4749 expr1
.X_add_number
= 8;
4750 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4751 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4754 /* We want to close the noreorder block as soon as possible, so
4755 that later insns are available for delay slot filling. */
4756 --mips_opts
.noreorder
;
4757 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4760 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4766 /* Load the address of a symbol into a register. If breg is not
4767 zero, we then add a base register to it. */
4769 if (dbl
&& HAVE_32BIT_GPRS
)
4770 as_warn (_("dla used to load 32-bit register"));
4772 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4773 as_warn (_("la used to load 64-bit address"));
4775 if (offset_expr
.X_op
== O_constant
4776 && offset_expr
.X_add_number
>= -0x8000
4777 && offset_expr
.X_add_number
< 0x8000)
4779 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4780 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4781 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4796 /* When generating embedded PIC code, we permit expressions of
4799 la $treg,foo-bar($breg)
4800 where bar is an address in the current section. These are used
4801 when getting the addresses of functions. We don't permit
4802 X_add_number to be non-zero, because if the symbol is
4803 external the relaxing code needs to know that any addend is
4804 purely the offset to X_op_symbol. */
4805 if (mips_pic
== EMBEDDED_PIC
4806 && offset_expr
.X_op
== O_subtract
4807 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4808 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4809 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4811 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4814 && (offset_expr
.X_add_number
== 0
4815 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4821 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4822 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4826 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4827 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4828 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4829 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4830 "d,v,t", tempreg
, tempreg
, breg
);
4832 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4833 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4834 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4840 if (offset_expr
.X_op
!= O_symbol
4841 && offset_expr
.X_op
!= O_constant
)
4843 as_bad (_("expression too complex"));
4844 offset_expr
.X_op
= O_constant
;
4847 if (offset_expr
.X_op
== O_constant
)
4848 load_register (&icnt
, tempreg
, &offset_expr
,
4849 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4850 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4851 : HAVE_64BIT_ADDRESSES
));
4852 else if (mips_pic
== NO_PIC
)
4854 /* If this is a reference to a GP relative symbol, we want
4855 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4857 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4858 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4859 If we have a constant, we need two instructions anyhow,
4860 so we may as well always use the latter form.
4862 With 64bit address space and a usable $at we want
4863 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4864 lui $at,<sym> (BFD_RELOC_HI16_S)
4865 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4866 daddiu $at,<sym> (BFD_RELOC_LO16)
4868 daddu $tempreg,$tempreg,$at
4870 If $at is already in use, we use an path which is suboptimal
4871 on superscalar processors.
4872 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4873 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4875 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4877 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4880 if (HAVE_64BIT_ADDRESSES
)
4882 /* We don't do GP optimization for now because RELAX_ENCODE can't
4883 hold the data for such large chunks. */
4885 if (used_at
== 0 && ! mips_opts
.noat
)
4887 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4888 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4889 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4890 AT
, (int) BFD_RELOC_HI16_S
);
4891 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4892 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4893 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4894 AT
, AT
, (int) BFD_RELOC_LO16
);
4895 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4896 "d,w,<", tempreg
, tempreg
, 0);
4897 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4898 "d,v,t", tempreg
, tempreg
, AT
);
4903 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4904 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4905 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4906 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4907 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4908 tempreg
, tempreg
, 16);
4909 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4910 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4911 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4912 tempreg
, tempreg
, 16);
4913 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4914 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4919 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4920 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4923 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4924 "t,r,j", tempreg
, mips_gp_register
,
4925 (int) BFD_RELOC_GPREL16
);
4926 p
= frag_var (rs_machine_dependent
, 8, 0,
4927 RELAX_ENCODE (4, 8, 0, 4, 0,
4928 mips_opts
.warn_about_macros
),
4929 offset_expr
.X_add_symbol
, 0, NULL
);
4931 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4934 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4935 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4938 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4940 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4942 /* If this is a reference to an external symbol, and there
4943 is no constant, we want
4944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4945 or if tempreg is PIC_CALL_REG
4946 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4947 For a local symbol, we want
4948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4950 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4952 If we have a small constant, and this is a reference to
4953 an external symbol, we want
4954 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4956 addiu $tempreg,$tempreg,<constant>
4957 For a local symbol, we want the same instruction
4958 sequence, but we output a BFD_RELOC_LO16 reloc on the
4961 If we have a large constant, and this is a reference to
4962 an external symbol, we want
4963 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4964 lui $at,<hiconstant>
4965 addiu $at,$at,<loconstant>
4966 addu $tempreg,$tempreg,$at
4967 For a local symbol, we want the same instruction
4968 sequence, but we output a BFD_RELOC_LO16 reloc on the
4971 For NewABI, we want for local or external data addresses
4972 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4973 For a local function symbol, we want
4974 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4976 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4979 expr1
.X_add_number
= offset_expr
.X_add_number
;
4980 offset_expr
.X_add_number
= 0;
4982 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4983 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4984 else if (HAVE_NEWABI
)
4985 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4986 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4987 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4988 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
4989 if (expr1
.X_add_number
== 0)
4998 /* We're going to put in an addu instruction using
4999 tempreg, so we may as well insert the nop right
5001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5005 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
5006 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
5008 ? mips_opts
.warn_about_macros
5010 offset_expr
.X_add_symbol
, 0, NULL
);
5013 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5016 macro_build (p
, &icnt
, &expr1
,
5017 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5018 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5019 /* FIXME: If breg == 0, and the next instruction uses
5020 $tempreg, then if this variant case is used an extra
5021 nop will be generated. */
5023 else if (expr1
.X_add_number
>= -0x8000
5024 && expr1
.X_add_number
< 0x8000)
5026 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5028 macro_build ((char *) NULL
, &icnt
, &expr1
,
5029 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5030 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5031 frag_var (rs_machine_dependent
, 0, 0,
5032 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5033 offset_expr
.X_add_symbol
, 0, NULL
);
5039 /* If we are going to add in a base register, and the
5040 target register and the base register are the same,
5041 then we are using AT as a temporary register. Since
5042 we want to load the constant into AT, we add our
5043 current AT (from the global offset table) and the
5044 register into the register now, and pretend we were
5045 not using a base register. */
5050 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5052 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5053 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5054 "d,v,t", treg
, AT
, breg
);
5060 /* Set mips_optimize around the lui instruction to avoid
5061 inserting an unnecessary nop after the lw. */
5062 hold_mips_optimize
= mips_optimize
;
5064 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5065 mips_optimize
= hold_mips_optimize
;
5067 macro_build ((char *) NULL
, &icnt
, &expr1
,
5068 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5069 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5071 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5072 "d,v,t", tempreg
, tempreg
, AT
);
5073 frag_var (rs_machine_dependent
, 0, 0,
5074 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
5075 offset_expr
.X_add_symbol
, 0, NULL
);
5079 else if (mips_pic
== SVR4_PIC
)
5083 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5084 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5085 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5087 /* This is the large GOT case. If this is a reference to an
5088 external symbol, and there is no constant, we want
5089 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5090 addu $tempreg,$tempreg,$gp
5091 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5092 or if tempreg is PIC_CALL_REG
5093 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5094 addu $tempreg,$tempreg,$gp
5095 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5096 For a local symbol, we want
5097 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5099 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5101 If we have a small constant, and this is a reference to
5102 an external symbol, we want
5103 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5104 addu $tempreg,$tempreg,$gp
5105 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5107 addiu $tempreg,$tempreg,<constant>
5108 For a local symbol, we want
5109 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5111 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5113 If we have a large constant, and this is a reference to
5114 an external symbol, we want
5115 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5116 addu $tempreg,$tempreg,$gp
5117 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5118 lui $at,<hiconstant>
5119 addiu $at,$at,<loconstant>
5120 addu $tempreg,$tempreg,$at
5121 For a local symbol, we want
5122 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5123 lui $at,<hiconstant>
5124 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5125 addu $tempreg,$tempreg,$at
5127 For NewABI, we want for local data addresses
5128 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5131 expr1
.X_add_number
= offset_expr
.X_add_number
;
5132 offset_expr
.X_add_number
= 0;
5134 if (reg_needs_delay (mips_gp_register
))
5138 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5140 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5141 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5143 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5144 tempreg
, lui_reloc_type
);
5145 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5146 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5147 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5148 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5149 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5150 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5151 if (expr1
.X_add_number
== 0)
5159 /* We're going to put in an addu instruction using
5160 tempreg, so we may as well insert the nop right
5162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5167 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5168 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5171 ? mips_opts
.warn_about_macros
5173 offset_expr
.X_add_symbol
, 0, NULL
);
5175 else if (expr1
.X_add_number
>= -0x8000
5176 && expr1
.X_add_number
< 0x8000)
5178 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5180 macro_build ((char *) NULL
, &icnt
, &expr1
,
5181 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5182 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5184 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5185 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5187 ? mips_opts
.warn_about_macros
5189 offset_expr
.X_add_symbol
, 0, NULL
);
5195 /* If we are going to add in a base register, and the
5196 target register and the base register are the same,
5197 then we are using AT as a temporary register. Since
5198 we want to load the constant into AT, we add our
5199 current AT (from the global offset table) and the
5200 register into the register now, and pretend we were
5201 not using a base register. */
5209 assert (tempreg
== AT
);
5210 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5212 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5213 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5214 "d,v,t", treg
, AT
, breg
);
5219 /* Set mips_optimize around the lui instruction to avoid
5220 inserting an unnecessary nop after the lw. */
5221 hold_mips_optimize
= mips_optimize
;
5223 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5224 mips_optimize
= hold_mips_optimize
;
5226 macro_build ((char *) NULL
, &icnt
, &expr1
,
5227 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5228 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5229 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5230 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5231 "d,v,t", dreg
, dreg
, AT
);
5233 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5234 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5237 ? mips_opts
.warn_about_macros
5239 offset_expr
.X_add_symbol
, 0, NULL
);
5246 /* This is needed because this instruction uses $gp, but
5247 the first instruction on the main stream does not. */
5248 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5253 local_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5254 macro_build (p
, &icnt
, &offset_expr
,
5255 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5260 if (expr1
.X_add_number
== 0 && HAVE_NEWABI
)
5262 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
5265 if (expr1
.X_add_number
>= -0x8000
5266 && expr1
.X_add_number
< 0x8000)
5268 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5270 macro_build (p
, &icnt
, &expr1
,
5271 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5272 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5273 /* FIXME: If add_number is 0, and there was no base
5274 register, the external symbol case ended with a load,
5275 so if the symbol turns out to not be external, and
5276 the next instruction uses tempreg, an unnecessary nop
5277 will be inserted. */
5283 /* We must add in the base register now, as in the
5284 external symbol case. */
5285 assert (tempreg
== AT
);
5286 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5288 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5289 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5290 "d,v,t", treg
, AT
, breg
);
5293 /* We set breg to 0 because we have arranged to add
5294 it in in both cases. */
5298 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5300 macro_build (p
, &icnt
, &expr1
,
5301 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5302 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5304 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5305 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5306 "d,v,t", tempreg
, tempreg
, AT
);
5310 else if (mips_pic
== EMBEDDED_PIC
)
5313 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5315 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5316 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5317 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5326 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5327 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5329 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5331 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5332 "d,v,t", treg
, tempreg
, breg
);
5341 /* The j instruction may not be used in PIC code, since it
5342 requires an absolute address. We convert it to a b
5344 if (mips_pic
== NO_PIC
)
5345 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5347 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5350 /* The jal instructions must be handled as macros because when
5351 generating PIC code they expand to multi-instruction
5352 sequences. Normally they are simple instructions. */
5357 if (mips_pic
== NO_PIC
5358 || mips_pic
== EMBEDDED_PIC
)
5359 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5361 else if (mips_pic
== SVR4_PIC
)
5363 if (sreg
!= PIC_CALL_REG
)
5364 as_warn (_("MIPS PIC call to register other than $25"));
5366 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5370 if (mips_cprestore_offset
< 0)
5371 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5374 if (! mips_frame_reg_valid
)
5376 as_warn (_("No .frame pseudo-op used in PIC code"));
5377 /* Quiet this warning. */
5378 mips_frame_reg_valid
= 1;
5380 if (! mips_cprestore_valid
)
5382 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5383 /* Quiet this warning. */
5384 mips_cprestore_valid
= 1;
5386 expr1
.X_add_number
= mips_cprestore_offset
;
5387 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5388 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5389 mips_gp_register
, mips_frame_reg
);
5399 if (mips_pic
== NO_PIC
)
5400 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5401 else if (mips_pic
== SVR4_PIC
)
5405 /* If this is a reference to an external symbol, and we are
5406 using a small GOT, we want
5407 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5411 lw $gp,cprestore($sp)
5412 The cprestore value is set using the .cprestore
5413 pseudo-op. If we are using a big GOT, we want
5414 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5416 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5420 lw $gp,cprestore($sp)
5421 If the symbol is not external, we want
5422 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5424 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5427 lw $gp,cprestore($sp)
5429 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5430 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5434 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5435 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5436 "t,o(b)", PIC_CALL_REG
,
5437 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5438 macro_build_jalr (icnt
, &offset_expr
);
5445 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5446 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5447 "t,o(b)", PIC_CALL_REG
,
5448 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5451 p
= frag_var (rs_machine_dependent
, 4, 0,
5452 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5453 offset_expr
.X_add_symbol
, 0, NULL
);
5459 if (reg_needs_delay (mips_gp_register
))
5463 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5464 "t,u", PIC_CALL_REG
,
5465 (int) BFD_RELOC_MIPS_CALL_HI16
);
5466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5467 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5468 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5470 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5471 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5472 "t,o(b)", PIC_CALL_REG
,
5473 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5474 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5476 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5477 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5479 offset_expr
.X_add_symbol
, 0, NULL
);
5482 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5485 macro_build (p
, &icnt
, &offset_expr
,
5486 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5487 "t,o(b)", PIC_CALL_REG
,
5488 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5490 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5493 macro_build (p
, &icnt
, &offset_expr
,
5494 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5495 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5496 (int) BFD_RELOC_LO16
);
5497 macro_build_jalr (icnt
, &offset_expr
);
5499 if (mips_cprestore_offset
< 0)
5500 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5503 if (! mips_frame_reg_valid
)
5505 as_warn (_("No .frame pseudo-op used in PIC code"));
5506 /* Quiet this warning. */
5507 mips_frame_reg_valid
= 1;
5509 if (! mips_cprestore_valid
)
5511 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5512 /* Quiet this warning. */
5513 mips_cprestore_valid
= 1;
5515 if (mips_opts
.noreorder
)
5516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5518 expr1
.X_add_number
= mips_cprestore_offset
;
5519 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5520 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5521 mips_gp_register
, mips_frame_reg
);
5525 else if (mips_pic
== EMBEDDED_PIC
)
5527 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5528 /* The linker may expand the call to a longer sequence which
5529 uses $at, so we must break rather than return. */
5554 /* Itbl support may require additional care here. */
5559 /* Itbl support may require additional care here. */
5564 /* Itbl support may require additional care here. */
5569 /* Itbl support may require additional care here. */
5581 if (mips_arch
== CPU_R4650
)
5583 as_bad (_("opcode not supported on this processor"));
5587 /* Itbl support may require additional care here. */
5592 /* Itbl support may require additional care here. */
5597 /* Itbl support may require additional care here. */
5617 if (breg
== treg
|| coproc
|| lr
)
5639 /* Itbl support may require additional care here. */
5644 /* Itbl support may require additional care here. */
5649 /* Itbl support may require additional care here. */
5654 /* Itbl support may require additional care here. */
5670 if (mips_arch
== CPU_R4650
)
5672 as_bad (_("opcode not supported on this processor"));
5677 /* Itbl support may require additional care here. */
5681 /* Itbl support may require additional care here. */
5686 /* Itbl support may require additional care here. */
5698 /* Itbl support may require additional care here. */
5699 if (mask
== M_LWC1_AB
5700 || mask
== M_SWC1_AB
5701 || mask
== M_LDC1_AB
5702 || mask
== M_SDC1_AB
5711 /* For embedded PIC, we allow loads where the offset is calculated
5712 by subtracting a symbol in the current segment from an unknown
5713 symbol, relative to a base register, e.g.:
5714 <op> $treg, <sym>-<localsym>($breg)
5715 This is used by the compiler for switch statements. */
5716 if (mips_pic
== EMBEDDED_PIC
5717 && offset_expr
.X_op
== O_subtract
5718 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5719 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5720 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5722 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5726 && (offset_expr
.X_add_number
== 0
5727 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5729 /* For this case, we output the instructions:
5730 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5731 addiu $tempreg,$tempreg,$breg
5732 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5733 If the relocation would fit entirely in 16 bits, it would be
5735 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5736 instead, but that seems quite difficult. */
5737 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5738 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5740 ((bfd_arch_bits_per_address (stdoutput
) == 32
5741 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5742 ? "addu" : "daddu"),
5743 "d,v,t", tempreg
, tempreg
, breg
);
5744 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5745 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5751 if (offset_expr
.X_op
!= O_constant
5752 && offset_expr
.X_op
!= O_symbol
)
5754 as_bad (_("expression too complex"));
5755 offset_expr
.X_op
= O_constant
;
5758 /* A constant expression in PIC code can be handled just as it
5759 is in non PIC code. */
5760 if (mips_pic
== NO_PIC
5761 || offset_expr
.X_op
== O_constant
)
5765 /* If this is a reference to a GP relative symbol, and there
5766 is no base register, we want
5767 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5768 Otherwise, if there is no base register, we want
5769 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5770 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5771 If we have a constant, we need two instructions anyhow,
5772 so we always use the latter form.
5774 If we have a base register, and this is a reference to a
5775 GP relative symbol, we want
5776 addu $tempreg,$breg,$gp
5777 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5779 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5780 addu $tempreg,$tempreg,$breg
5781 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5782 With a constant we always use the latter case.
5784 With 64bit address space and no base register and $at usable,
5786 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5787 lui $at,<sym> (BFD_RELOC_HI16_S)
5788 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5791 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5792 If we have a base register, we want
5793 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5794 lui $at,<sym> (BFD_RELOC_HI16_S)
5795 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5799 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5801 Without $at we can't generate the optimal path for superscalar
5802 processors here since this would require two temporary registers.
5803 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5804 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5806 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5808 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5809 If we have a base register, we want
5810 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5811 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5813 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5815 daddu $tempreg,$tempreg,$breg
5816 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5818 If we have 64-bit addresses, as an optimization, for
5819 addresses which are 32-bit constants (e.g. kseg0/kseg1
5820 addresses) we fall back to the 32-bit address generation
5821 mechanism since it is more efficient. Note that due to
5822 the signed offset used by memory operations, the 32-bit
5823 range is shifted down by 32768 here. This code should
5824 probably attempt to generate 64-bit constants more
5825 efficiently in general.
5827 if (HAVE_64BIT_ADDRESSES
5828 && !(offset_expr
.X_op
== O_constant
5829 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5833 /* We don't do GP optimization for now because RELAX_ENCODE can't
5834 hold the data for such large chunks. */
5836 if (used_at
== 0 && ! mips_opts
.noat
)
5838 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5839 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5840 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5841 AT
, (int) BFD_RELOC_HI16_S
);
5842 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5843 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5845 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5846 "d,v,t", AT
, AT
, breg
);
5847 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5848 "d,w,<", tempreg
, tempreg
, 0);
5849 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5850 "d,v,t", tempreg
, tempreg
, AT
);
5851 macro_build (p
, &icnt
, &offset_expr
, s
,
5852 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5857 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5858 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5859 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5860 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5861 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5862 "d,w,<", tempreg
, tempreg
, 16);
5863 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5864 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5865 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5866 "d,w,<", tempreg
, tempreg
, 16);
5868 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5869 "d,v,t", tempreg
, tempreg
, breg
);
5870 macro_build (p
, &icnt
, &offset_expr
, s
,
5871 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5879 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5880 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5885 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5886 treg
, (int) BFD_RELOC_GPREL16
,
5888 p
= frag_var (rs_machine_dependent
, 8, 0,
5889 RELAX_ENCODE (4, 8, 0, 4, 0,
5890 (mips_opts
.warn_about_macros
5892 && mips_opts
.noat
))),
5893 offset_expr
.X_add_symbol
, 0, NULL
);
5896 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5899 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5900 (int) BFD_RELOC_LO16
, tempreg
);
5904 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5905 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5911 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5912 "d,v,t", tempreg
, breg
, mips_gp_register
);
5913 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5914 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5915 p
= frag_var (rs_machine_dependent
, 12, 0,
5916 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5917 offset_expr
.X_add_symbol
, 0, NULL
);
5919 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5922 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5923 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5924 "d,v,t", tempreg
, tempreg
, breg
);
5927 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5928 (int) BFD_RELOC_LO16
, tempreg
);
5931 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5934 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5936 /* If this is a reference to an external symbol, we want
5937 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5939 <op> $treg,0($tempreg)
5941 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5943 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5944 <op> $treg,0($tempreg)
5945 If we have NewABI, we want
5946 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5947 If there is a base register, we add it to $tempreg before
5948 the <op>. If there is a constant, we stick it in the
5949 <op> instruction. We don't handle constants larger than
5950 16 bits, because we have no way to load the upper 16 bits
5951 (actually, we could handle them for the subset of cases
5952 in which we are not using $at). */
5953 assert (offset_expr
.X_op
== O_symbol
);
5954 expr1
.X_add_number
= offset_expr
.X_add_number
;
5955 offset_expr
.X_add_number
= 0;
5957 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5958 if (expr1
.X_add_number
< -0x8000
5959 || expr1
.X_add_number
>= 0x8000)
5960 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5962 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5963 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5964 (int) lw_reloc_type
, mips_gp_register
);
5965 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5966 p
= frag_var (rs_machine_dependent
, 4, 0,
5967 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5968 offset_expr
.X_add_symbol
, 0, NULL
);
5969 macro_build (p
, &icnt
, &offset_expr
,
5970 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5971 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5974 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5975 "d,v,t", tempreg
, tempreg
, breg
);
5976 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5977 (int) BFD_RELOC_LO16
, tempreg
);
5979 else if (mips_pic
== SVR4_PIC
)
5984 /* If this is a reference to an external symbol, we want
5985 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5986 addu $tempreg,$tempreg,$gp
5987 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5988 <op> $treg,0($tempreg)
5990 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5992 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5993 <op> $treg,0($tempreg)
5994 If there is a base register, we add it to $tempreg before
5995 the <op>. If there is a constant, we stick it in the
5996 <op> instruction. We don't handle constants larger than
5997 16 bits, because we have no way to load the upper 16 bits
5998 (actually, we could handle them for the subset of cases
5999 in which we are not using $at).
6002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6003 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6004 <op> $treg,0($tempreg)
6006 assert (offset_expr
.X_op
== O_symbol
);
6007 expr1
.X_add_number
= offset_expr
.X_add_number
;
6008 offset_expr
.X_add_number
= 0;
6009 if (expr1
.X_add_number
< -0x8000
6010 || expr1
.X_add_number
>= 0x8000)
6011 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6014 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6015 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6016 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
6018 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6019 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6020 "t,r,j", tempreg
, tempreg
,
6021 BFD_RELOC_MIPS_GOT_OFST
);
6023 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6024 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6025 "d,v,t", tempreg
, tempreg
, breg
);
6026 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6027 (int) BFD_RELOC_LO16
, tempreg
);
6034 if (reg_needs_delay (mips_gp_register
))
6039 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6040 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6042 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6043 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
6044 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6045 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6046 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6048 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
6049 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
6050 offset_expr
.X_add_symbol
, 0, NULL
);
6053 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6056 macro_build (p
, &icnt
, &offset_expr
,
6057 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6058 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
6061 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6063 macro_build (p
, &icnt
, &offset_expr
,
6064 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6065 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6068 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6069 "d,v,t", tempreg
, tempreg
, breg
);
6070 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6071 (int) BFD_RELOC_LO16
, tempreg
);
6073 else if (mips_pic
== EMBEDDED_PIC
)
6075 /* If there is no base register, we want
6076 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6077 If there is a base register, we want
6078 addu $tempreg,$breg,$gp
6079 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6081 assert (offset_expr
.X_op
== O_symbol
);
6084 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6085 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
6090 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6091 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6092 "d,v,t", tempreg
, breg
, mips_gp_register
);
6093 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6094 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6107 load_register (&icnt
, treg
, &imm_expr
, 0);
6111 load_register (&icnt
, treg
, &imm_expr
, 1);
6115 if (imm_expr
.X_op
== O_constant
)
6117 load_register (&icnt
, AT
, &imm_expr
, 0);
6118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6119 "mtc1", "t,G", AT
, treg
);
6124 assert (offset_expr
.X_op
== O_symbol
6125 && strcmp (segment_name (S_GET_SEGMENT
6126 (offset_expr
.X_add_symbol
)),
6128 && offset_expr
.X_add_number
== 0);
6129 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6130 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6135 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6136 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6137 order 32 bits of the value and the low order 32 bits are either
6138 zero or in OFFSET_EXPR. */
6139 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6141 if (HAVE_64BIT_GPRS
)
6142 load_register (&icnt
, treg
, &imm_expr
, 1);
6147 if (target_big_endian
)
6159 load_register (&icnt
, hreg
, &imm_expr
, 0);
6162 if (offset_expr
.X_op
== O_absent
)
6163 move_register (&icnt
, lreg
, 0);
6166 assert (offset_expr
.X_op
== O_constant
);
6167 load_register (&icnt
, lreg
, &offset_expr
, 0);
6174 /* We know that sym is in the .rdata section. First we get the
6175 upper 16 bits of the address. */
6176 if (mips_pic
== NO_PIC
)
6178 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6180 else if (mips_pic
== SVR4_PIC
)
6182 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6183 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6184 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6187 else if (mips_pic
== EMBEDDED_PIC
)
6189 /* For embedded PIC we pick up the entire address off $gp in
6190 a single instruction. */
6191 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6192 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
6193 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
6194 offset_expr
.X_op
= O_constant
;
6195 offset_expr
.X_add_number
= 0;
6200 /* Now we load the register(s). */
6201 if (HAVE_64BIT_GPRS
)
6202 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6203 treg
, (int) BFD_RELOC_LO16
, AT
);
6206 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6207 treg
, (int) BFD_RELOC_LO16
, AT
);
6210 /* FIXME: How in the world do we deal with the possible
6212 offset_expr
.X_add_number
+= 4;
6213 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6214 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6218 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6219 does not become a variant frag. */
6220 frag_wane (frag_now
);
6226 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6227 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6228 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6229 the value and the low order 32 bits are either zero or in
6231 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6233 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6234 if (HAVE_64BIT_FPRS
)
6236 assert (HAVE_64BIT_GPRS
);
6237 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6238 "dmtc1", "t,S", AT
, treg
);
6242 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6243 "mtc1", "t,G", AT
, treg
+ 1);
6244 if (offset_expr
.X_op
== O_absent
)
6245 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6246 "mtc1", "t,G", 0, treg
);
6249 assert (offset_expr
.X_op
== O_constant
);
6250 load_register (&icnt
, AT
, &offset_expr
, 0);
6251 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6252 "mtc1", "t,G", AT
, treg
);
6258 assert (offset_expr
.X_op
== O_symbol
6259 && offset_expr
.X_add_number
== 0);
6260 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6261 if (strcmp (s
, ".lit8") == 0)
6263 if (mips_opts
.isa
!= ISA_MIPS1
)
6265 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6266 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6270 breg
= mips_gp_register
;
6271 r
= BFD_RELOC_MIPS_LITERAL
;
6276 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6277 if (mips_pic
== SVR4_PIC
)
6278 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6279 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6280 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6284 /* FIXME: This won't work for a 64 bit address. */
6285 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6288 if (mips_opts
.isa
!= ISA_MIPS1
)
6290 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6291 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6293 /* To avoid confusion in tc_gen_reloc, we must ensure
6294 that this does not become a variant frag. */
6295 frag_wane (frag_now
);
6306 if (mips_arch
== CPU_R4650
)
6308 as_bad (_("opcode not supported on this processor"));
6311 /* Even on a big endian machine $fn comes before $fn+1. We have
6312 to adjust when loading from memory. */
6315 assert (mips_opts
.isa
== ISA_MIPS1
);
6316 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6317 target_big_endian
? treg
+ 1 : treg
,
6319 /* FIXME: A possible overflow which I don't know how to deal
6321 offset_expr
.X_add_number
+= 4;
6322 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6323 target_big_endian
? treg
: treg
+ 1,
6326 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6327 does not become a variant frag. */
6328 frag_wane (frag_now
);
6337 * The MIPS assembler seems to check for X_add_number not
6338 * being double aligned and generating:
6341 * addiu at,at,%lo(foo+1)
6344 * But, the resulting address is the same after relocation so why
6345 * generate the extra instruction?
6347 if (mips_arch
== CPU_R4650
)
6349 as_bad (_("opcode not supported on this processor"));
6352 /* Itbl support may require additional care here. */
6354 if (mips_opts
.isa
!= ISA_MIPS1
)
6365 if (mips_arch
== CPU_R4650
)
6367 as_bad (_("opcode not supported on this processor"));
6371 if (mips_opts
.isa
!= ISA_MIPS1
)
6379 /* Itbl support may require additional care here. */
6384 if (HAVE_64BIT_GPRS
)
6395 if (HAVE_64BIT_GPRS
)
6405 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6406 loads for the case of doing a pair of loads to simulate an 'ld'.
6407 This is not currently done by the compiler, and assembly coders
6408 writing embedded-pic code can cope. */
6410 if (offset_expr
.X_op
!= O_symbol
6411 && offset_expr
.X_op
!= O_constant
)
6413 as_bad (_("expression too complex"));
6414 offset_expr
.X_op
= O_constant
;
6417 /* Even on a big endian machine $fn comes before $fn+1. We have
6418 to adjust when loading from memory. We set coproc if we must
6419 load $fn+1 first. */
6420 /* Itbl support may require additional care here. */
6421 if (! target_big_endian
)
6424 if (mips_pic
== NO_PIC
6425 || offset_expr
.X_op
== O_constant
)
6429 /* If this is a reference to a GP relative symbol, we want
6430 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6431 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6432 If we have a base register, we use this
6434 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6435 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6436 If this is not a GP relative symbol, we want
6437 lui $at,<sym> (BFD_RELOC_HI16_S)
6438 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6439 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6440 If there is a base register, we add it to $at after the
6441 lui instruction. If there is a constant, we always use
6443 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6444 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6456 tempreg
= mips_gp_register
;
6463 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6464 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6465 "d,v,t", AT
, breg
, mips_gp_register
);
6471 /* Itbl support may require additional care here. */
6472 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6473 coproc
? treg
+ 1 : treg
,
6474 (int) BFD_RELOC_GPREL16
, tempreg
);
6475 offset_expr
.X_add_number
+= 4;
6477 /* Set mips_optimize to 2 to avoid inserting an
6479 hold_mips_optimize
= mips_optimize
;
6481 /* Itbl support may require additional care here. */
6482 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6483 coproc
? treg
: treg
+ 1,
6484 (int) BFD_RELOC_GPREL16
, tempreg
);
6485 mips_optimize
= hold_mips_optimize
;
6487 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6488 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6489 used_at
&& mips_opts
.noat
),
6490 offset_expr
.X_add_symbol
, 0, NULL
);
6492 /* We just generated two relocs. When tc_gen_reloc
6493 handles this case, it will skip the first reloc and
6494 handle the second. The second reloc already has an
6495 extra addend of 4, which we added above. We must
6496 subtract it out, and then subtract another 4 to make
6497 the first reloc come out right. The second reloc
6498 will come out right because we are going to add 4 to
6499 offset_expr when we build its instruction below.
6501 If we have a symbol, then we don't want to include
6502 the offset, because it will wind up being included
6503 when we generate the reloc. */
6505 if (offset_expr
.X_op
== O_constant
)
6506 offset_expr
.X_add_number
-= 8;
6509 offset_expr
.X_add_number
= -4;
6510 offset_expr
.X_op
= O_constant
;
6513 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6518 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6519 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6520 "d,v,t", AT
, breg
, AT
);
6524 /* Itbl support may require additional care here. */
6525 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6526 coproc
? treg
+ 1 : treg
,
6527 (int) BFD_RELOC_LO16
, AT
);
6530 /* FIXME: How do we handle overflow here? */
6531 offset_expr
.X_add_number
+= 4;
6532 /* Itbl support may require additional care here. */
6533 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6534 coproc
? treg
: treg
+ 1,
6535 (int) BFD_RELOC_LO16
, AT
);
6537 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6541 /* If this is a reference to an external symbol, we want
6542 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6547 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6549 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6550 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6551 If there is a base register we add it to $at before the
6552 lwc1 instructions. If there is a constant we include it
6553 in the lwc1 instructions. */
6555 expr1
.X_add_number
= offset_expr
.X_add_number
;
6556 offset_expr
.X_add_number
= 0;
6557 if (expr1
.X_add_number
< -0x8000
6558 || expr1
.X_add_number
>= 0x8000 - 4)
6559 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6564 frag_grow (24 + off
);
6565 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6566 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6567 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6568 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6570 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6571 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6572 "d,v,t", AT
, breg
, AT
);
6573 /* Itbl support may require additional care here. */
6574 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6575 coproc
? treg
+ 1 : treg
,
6576 (int) BFD_RELOC_LO16
, AT
);
6577 expr1
.X_add_number
+= 4;
6579 /* Set mips_optimize to 2 to avoid inserting an undesired
6581 hold_mips_optimize
= mips_optimize
;
6583 /* Itbl support may require additional care here. */
6584 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6585 coproc
? treg
: treg
+ 1,
6586 (int) BFD_RELOC_LO16
, AT
);
6587 mips_optimize
= hold_mips_optimize
;
6589 (void) frag_var (rs_machine_dependent
, 0, 0,
6590 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6591 offset_expr
.X_add_symbol
, 0, NULL
);
6593 else if (mips_pic
== SVR4_PIC
)
6598 /* If this is a reference to an external symbol, we want
6599 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6601 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6606 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6608 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6609 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6610 If there is a base register we add it to $at before the
6611 lwc1 instructions. If there is a constant we include it
6612 in the lwc1 instructions. */
6614 expr1
.X_add_number
= offset_expr
.X_add_number
;
6615 offset_expr
.X_add_number
= 0;
6616 if (expr1
.X_add_number
< -0x8000
6617 || expr1
.X_add_number
>= 0x8000 - 4)
6618 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6619 if (reg_needs_delay (mips_gp_register
))
6628 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6629 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6630 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6631 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6632 "d,v,t", AT
, AT
, mips_gp_register
);
6633 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6634 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6635 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6636 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6638 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6639 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6640 "d,v,t", AT
, breg
, AT
);
6641 /* Itbl support may require additional care here. */
6642 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6643 coproc
? treg
+ 1 : treg
,
6644 (int) BFD_RELOC_LO16
, AT
);
6645 expr1
.X_add_number
+= 4;
6647 /* Set mips_optimize to 2 to avoid inserting an undesired
6649 hold_mips_optimize
= mips_optimize
;
6651 /* Itbl support may require additional care here. */
6652 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6653 coproc
? treg
: treg
+ 1,
6654 (int) BFD_RELOC_LO16
, AT
);
6655 mips_optimize
= hold_mips_optimize
;
6656 expr1
.X_add_number
-= 4;
6658 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6659 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6660 8 + gpdel
+ off
, 1, 0),
6661 offset_expr
.X_add_symbol
, 0, NULL
);
6664 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6667 macro_build (p
, &icnt
, &offset_expr
,
6668 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6669 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6672 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6676 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6677 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6678 "d,v,t", AT
, breg
, AT
);
6681 /* Itbl support may require additional care here. */
6682 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6683 coproc
? treg
+ 1 : treg
,
6684 (int) BFD_RELOC_LO16
, AT
);
6686 expr1
.X_add_number
+= 4;
6688 /* Set mips_optimize to 2 to avoid inserting an undesired
6690 hold_mips_optimize
= mips_optimize
;
6692 /* Itbl support may require additional care here. */
6693 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6694 coproc
? treg
: treg
+ 1,
6695 (int) BFD_RELOC_LO16
, AT
);
6696 mips_optimize
= hold_mips_optimize
;
6698 else if (mips_pic
== EMBEDDED_PIC
)
6700 /* If there is no base register, we use
6701 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6702 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6703 If we have a base register, we use
6705 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6706 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6710 tempreg
= mips_gp_register
;
6715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6716 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6717 "d,v,t", AT
, breg
, mips_gp_register
);
6722 /* Itbl support may require additional care here. */
6723 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6724 coproc
? treg
+ 1 : treg
,
6725 (int) BFD_RELOC_GPREL16
, tempreg
);
6726 offset_expr
.X_add_number
+= 4;
6727 /* Itbl support may require additional care here. */
6728 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6729 coproc
? treg
: treg
+ 1,
6730 (int) BFD_RELOC_GPREL16
, tempreg
);
6746 assert (HAVE_32BIT_ADDRESSES
);
6747 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6748 (int) BFD_RELOC_LO16
, breg
);
6749 offset_expr
.X_add_number
+= 4;
6750 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6751 (int) BFD_RELOC_LO16
, breg
);
6754 /* New code added to support COPZ instructions.
6755 This code builds table entries out of the macros in mip_opcodes.
6756 R4000 uses interlocks to handle coproc delays.
6757 Other chips (like the R3000) require nops to be inserted for delays.
6759 FIXME: Currently, we require that the user handle delays.
6760 In order to fill delay slots for non-interlocked chips,
6761 we must have a way to specify delays based on the coprocessor.
6762 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6763 What are the side-effects of the cop instruction?
6764 What cache support might we have and what are its effects?
6765 Both coprocessor & memory require delays. how long???
6766 What registers are read/set/modified?
6768 If an itbl is provided to interpret cop instructions,
6769 this knowledge can be encoded in the itbl spec. */
6783 /* For now we just do C (same as Cz). The parameter will be
6784 stored in insn_opcode by mips_ip. */
6785 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6790 move_register (&icnt
, dreg
, sreg
);
6793 #ifdef LOSING_COMPILER
6795 /* Try and see if this is a new itbl instruction.
6796 This code builds table entries out of the macros in mip_opcodes.
6797 FIXME: For now we just assemble the expression and pass it's
6798 value along as a 32-bit immediate.
6799 We may want to have the assembler assemble this value,
6800 so that we gain the assembler's knowledge of delay slots,
6802 Would it be more efficient to use mask (id) here? */
6803 if (itbl_have_entries
6804 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6806 s
= ip
->insn_mo
->name
;
6808 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6809 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6816 as_warn (_("Macro used $at after \".set noat\""));
6821 struct mips_cl_insn
*ip
;
6823 register int treg
, sreg
, dreg
, breg
;
6839 bfd_reloc_code_real_type r
;
6842 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6843 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6844 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6845 mask
= ip
->insn_mo
->mask
;
6847 expr1
.X_op
= O_constant
;
6848 expr1
.X_op_symbol
= NULL
;
6849 expr1
.X_add_symbol
= NULL
;
6850 expr1
.X_add_number
= 1;
6854 #endif /* LOSING_COMPILER */
6859 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6860 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6861 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6868 /* The MIPS assembler some times generates shifts and adds. I'm
6869 not trying to be that fancy. GCC should do this for us
6871 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6872 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6873 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6874 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6888 mips_emit_delays (TRUE
);
6889 ++mips_opts
.noreorder
;
6890 mips_any_noreorder
= 1;
6892 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6893 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6894 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6895 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6897 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6898 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6899 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6902 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6903 "s,t,q", dreg
, AT
, 6);
6906 expr1
.X_add_number
= 8;
6907 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6911 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6914 --mips_opts
.noreorder
;
6915 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6928 mips_emit_delays (TRUE
);
6929 ++mips_opts
.noreorder
;
6930 mips_any_noreorder
= 1;
6932 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6933 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6934 dbl
? "dmultu" : "multu",
6935 "s,t", sreg
, imm
? AT
: treg
);
6936 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6938 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6941 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6945 expr1
.X_add_number
= 8;
6946 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6947 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6949 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6952 --mips_opts
.noreorder
;
6956 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6957 "d,v,t", AT
, 0, treg
);
6958 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6959 "d,t,s", AT
, sreg
, AT
);
6960 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6961 "d,t,s", dreg
, sreg
, treg
);
6962 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6963 "d,v,t", dreg
, dreg
, AT
);
6967 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6968 "d,v,t", AT
, 0, treg
);
6969 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6970 "d,t,s", AT
, sreg
, AT
);
6971 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6972 "d,t,s", dreg
, sreg
, treg
);
6973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6974 "d,v,t", dreg
, dreg
, AT
);
6981 if (imm_expr
.X_op
!= O_constant
)
6982 as_bad (_("rotate count too large"));
6983 rot
= imm_expr
.X_add_number
& 0x3f;
6984 if (CPU_HAS_DROR (mips_arch
))
6986 rot
= (64 - rot
) & 0x3f;
6988 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
6989 "d,w,<", dreg
, sreg
, rot
- 32);
6991 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
6992 "d,w,<", dreg
, sreg
, rot
);
6996 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
6997 "d,w,<", dreg
, sreg
, 0);
7002 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7003 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7005 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7006 "d,w,<", AT
, sreg
, rot
);
7007 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7008 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7009 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7010 "d,v,t", dreg
, dreg
, AT
);
7019 if (imm_expr
.X_op
!= O_constant
)
7020 as_bad (_("rotate count too large"));
7021 rot
= imm_expr
.X_add_number
& 0x1f;
7022 if (CPU_HAS_ROR (mips_arch
))
7024 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7025 "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7029 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7030 "d,w,<", dreg
, sreg
, 0);
7033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7034 "d,w,<", AT
, sreg
, rot
);
7035 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7036 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7037 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7038 "d,v,t", dreg
, dreg
, AT
);
7044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7045 "d,v,t", AT
, 0, treg
);
7046 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7047 "d,t,s", AT
, sreg
, AT
);
7048 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7049 "d,t,s", dreg
, sreg
, treg
);
7050 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7051 "d,v,t", dreg
, dreg
, AT
);
7055 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7056 "d,v,t", AT
, 0, treg
);
7057 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7058 "d,t,s", AT
, sreg
, AT
);
7059 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7060 "d,t,s", dreg
, sreg
, treg
);
7061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7062 "d,v,t", dreg
, dreg
, AT
);
7069 if (imm_expr
.X_op
!= O_constant
)
7070 as_bad (_("rotate count too large"));
7071 rot
= imm_expr
.X_add_number
& 0x3f;
7073 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7074 "d,w,<", dreg
, sreg
, 0);
7079 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7080 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7083 "d,w,<", AT
, sreg
, rot
);
7084 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7085 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7086 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7087 "d,v,t", dreg
, dreg
, AT
);
7096 if (imm_expr
.X_op
!= O_constant
)
7097 as_bad (_("rotate count too large"));
7098 rot
= imm_expr
.X_add_number
& 0x1f;
7100 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7101 "d,w,<", dreg
, sreg
, 0);
7104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7105 "d,w,<", AT
, sreg
, rot
);
7106 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7107 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7108 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7109 "d,v,t", dreg
, dreg
, AT
);
7115 if (mips_arch
== CPU_R4650
)
7117 as_bad (_("opcode not supported on this processor"));
7120 assert (mips_opts
.isa
== ISA_MIPS1
);
7121 /* Even on a big endian machine $fn comes before $fn+1. We have
7122 to adjust when storing to memory. */
7123 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7124 target_big_endian
? treg
+ 1 : treg
,
7125 (int) BFD_RELOC_LO16
, breg
);
7126 offset_expr
.X_add_number
+= 4;
7127 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7128 target_big_endian
? treg
: treg
+ 1,
7129 (int) BFD_RELOC_LO16
, breg
);
7134 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7135 treg
, (int) BFD_RELOC_LO16
);
7137 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7138 sreg
, (int) BFD_RELOC_LO16
);
7141 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7142 "d,v,t", dreg
, sreg
, treg
);
7143 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7144 dreg
, (int) BFD_RELOC_LO16
);
7149 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7151 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7152 sreg
, (int) BFD_RELOC_LO16
);
7157 as_warn (_("Instruction %s: result is always false"),
7159 move_register (&icnt
, dreg
, 0);
7162 if (imm_expr
.X_op
== O_constant
7163 && imm_expr
.X_add_number
>= 0
7164 && imm_expr
.X_add_number
< 0x10000)
7166 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
7167 sreg
, (int) BFD_RELOC_LO16
);
7170 else if (imm_expr
.X_op
== O_constant
7171 && imm_expr
.X_add_number
> -0x8000
7172 && imm_expr
.X_add_number
< 0)
7174 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7175 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7176 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7177 "t,r,j", dreg
, sreg
,
7178 (int) BFD_RELOC_LO16
);
7183 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7185 "d,v,t", dreg
, sreg
, AT
);
7188 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7189 (int) BFD_RELOC_LO16
);
7194 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7202 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7203 (int) BFD_RELOC_LO16
);
7206 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7208 if (imm_expr
.X_op
== O_constant
7209 && imm_expr
.X_add_number
>= -0x8000
7210 && imm_expr
.X_add_number
< 0x8000)
7212 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7213 mask
== M_SGE_I
? "slti" : "sltiu",
7214 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7219 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7220 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7221 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7225 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7226 (int) BFD_RELOC_LO16
);
7231 case M_SGT
: /* sreg > treg <==> treg < sreg */
7237 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7241 case M_SGT_I
: /* sreg > I <==> I < sreg */
7247 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7252 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7258 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7260 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7261 (int) BFD_RELOC_LO16
);
7264 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7270 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7271 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7273 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7274 (int) BFD_RELOC_LO16
);
7278 if (imm_expr
.X_op
== O_constant
7279 && imm_expr
.X_add_number
>= -0x8000
7280 && imm_expr
.X_add_number
< 0x8000)
7282 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7283 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7286 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7287 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7292 if (imm_expr
.X_op
== O_constant
7293 && imm_expr
.X_add_number
>= -0x8000
7294 && imm_expr
.X_add_number
< 0x8000)
7296 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7297 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7300 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7302 "d,v,t", dreg
, sreg
, AT
);
7307 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7308 "d,v,t", dreg
, 0, treg
);
7310 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7311 "d,v,t", dreg
, 0, sreg
);
7314 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7315 "d,v,t", dreg
, sreg
, treg
);
7316 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7317 "d,v,t", dreg
, 0, dreg
);
7322 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7324 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7325 "d,v,t", dreg
, 0, sreg
);
7330 as_warn (_("Instruction %s: result is always true"),
7332 macro_build ((char *) NULL
, &icnt
, &expr1
,
7333 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7334 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7337 if (imm_expr
.X_op
== O_constant
7338 && imm_expr
.X_add_number
>= 0
7339 && imm_expr
.X_add_number
< 0x10000)
7341 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7342 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7345 else if (imm_expr
.X_op
== O_constant
7346 && imm_expr
.X_add_number
> -0x8000
7347 && imm_expr
.X_add_number
< 0)
7349 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7350 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7351 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7352 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7357 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7359 "d,v,t", dreg
, sreg
, AT
);
7362 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7363 "d,v,t", dreg
, 0, dreg
);
7371 if (imm_expr
.X_op
== O_constant
7372 && imm_expr
.X_add_number
> -0x8000
7373 && imm_expr
.X_add_number
<= 0x8000)
7375 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7376 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7377 dbl
? "daddi" : "addi",
7378 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7381 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7382 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7383 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7389 if (imm_expr
.X_op
== O_constant
7390 && imm_expr
.X_add_number
> -0x8000
7391 && imm_expr
.X_add_number
<= 0x8000)
7393 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7394 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7395 dbl
? "daddiu" : "addiu",
7396 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7399 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7400 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7401 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7422 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7423 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7429 assert (mips_opts
.isa
== ISA_MIPS1
);
7430 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7431 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7434 * Is the double cfc1 instruction a bug in the mips assembler;
7435 * or is there a reason for it?
7437 mips_emit_delays (TRUE
);
7438 ++mips_opts
.noreorder
;
7439 mips_any_noreorder
= 1;
7440 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7442 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7444 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7445 expr1
.X_add_number
= 3;
7446 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7447 (int) BFD_RELOC_LO16
);
7448 expr1
.X_add_number
= 2;
7449 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7450 (int) BFD_RELOC_LO16
);
7451 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7453 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7454 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7455 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7456 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7459 --mips_opts
.noreorder
;
7468 if (offset_expr
.X_add_number
>= 0x7fff)
7469 as_bad (_("operand overflow"));
7470 /* avoid load delay */
7471 if (! target_big_endian
)
7472 ++offset_expr
.X_add_number
;
7473 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7474 (int) BFD_RELOC_LO16
, breg
);
7475 if (! target_big_endian
)
7476 --offset_expr
.X_add_number
;
7478 ++offset_expr
.X_add_number
;
7479 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7480 (int) BFD_RELOC_LO16
, breg
);
7481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7483 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7497 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7498 as_bad (_("operand overflow"));
7499 if (! target_big_endian
)
7500 offset_expr
.X_add_number
+= off
;
7501 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7502 (int) BFD_RELOC_LO16
, breg
);
7503 if (! target_big_endian
)
7504 offset_expr
.X_add_number
-= off
;
7506 offset_expr
.X_add_number
+= off
;
7507 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7508 (int) BFD_RELOC_LO16
, breg
);
7522 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7524 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7525 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7526 "d,v,t", AT
, AT
, breg
);
7527 if (! target_big_endian
)
7528 expr1
.X_add_number
= off
;
7530 expr1
.X_add_number
= 0;
7531 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7532 (int) BFD_RELOC_LO16
, AT
);
7533 if (! target_big_endian
)
7534 expr1
.X_add_number
= 0;
7536 expr1
.X_add_number
= off
;
7537 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7538 (int) BFD_RELOC_LO16
, AT
);
7544 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7546 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7547 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7548 "d,v,t", AT
, AT
, breg
);
7549 if (target_big_endian
)
7550 expr1
.X_add_number
= 0;
7551 macro_build ((char *) NULL
, &icnt
, &expr1
,
7552 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7553 (int) BFD_RELOC_LO16
, AT
);
7554 if (target_big_endian
)
7555 expr1
.X_add_number
= 1;
7557 expr1
.X_add_number
= 0;
7558 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7559 (int) BFD_RELOC_LO16
, AT
);
7560 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7567 if (offset_expr
.X_add_number
>= 0x7fff)
7568 as_bad (_("operand overflow"));
7569 if (target_big_endian
)
7570 ++offset_expr
.X_add_number
;
7571 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7572 (int) BFD_RELOC_LO16
, breg
);
7573 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7575 if (target_big_endian
)
7576 --offset_expr
.X_add_number
;
7578 ++offset_expr
.X_add_number
;
7579 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7580 (int) BFD_RELOC_LO16
, breg
);
7593 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7594 as_bad (_("operand overflow"));
7595 if (! target_big_endian
)
7596 offset_expr
.X_add_number
+= off
;
7597 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7598 (int) BFD_RELOC_LO16
, breg
);
7599 if (! target_big_endian
)
7600 offset_expr
.X_add_number
-= off
;
7602 offset_expr
.X_add_number
+= off
;
7603 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7604 (int) BFD_RELOC_LO16
, breg
);
7618 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7620 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7621 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7622 "d,v,t", AT
, AT
, breg
);
7623 if (! target_big_endian
)
7624 expr1
.X_add_number
= off
;
7626 expr1
.X_add_number
= 0;
7627 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7628 (int) BFD_RELOC_LO16
, AT
);
7629 if (! target_big_endian
)
7630 expr1
.X_add_number
= 0;
7632 expr1
.X_add_number
= off
;
7633 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7634 (int) BFD_RELOC_LO16
, AT
);
7639 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7641 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7642 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7643 "d,v,t", AT
, AT
, breg
);
7644 if (! target_big_endian
)
7645 expr1
.X_add_number
= 0;
7646 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7647 (int) BFD_RELOC_LO16
, AT
);
7648 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7650 if (! target_big_endian
)
7651 expr1
.X_add_number
= 1;
7653 expr1
.X_add_number
= 0;
7654 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7655 (int) BFD_RELOC_LO16
, AT
);
7656 if (! target_big_endian
)
7657 expr1
.X_add_number
= 0;
7659 expr1
.X_add_number
= 1;
7660 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7661 (int) BFD_RELOC_LO16
, AT
);
7662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7669 /* FIXME: Check if this is one of the itbl macros, since they
7670 are added dynamically. */
7671 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7675 as_warn (_("Macro used $at after \".set noat\""));
7678 /* Implement macros in mips16 mode. */
7682 struct mips_cl_insn
*ip
;
7685 int xreg
, yreg
, zreg
, tmp
;
7689 const char *s
, *s2
, *s3
;
7691 mask
= ip
->insn_mo
->mask
;
7693 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7694 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7695 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7699 expr1
.X_op
= O_constant
;
7700 expr1
.X_op_symbol
= NULL
;
7701 expr1
.X_add_symbol
= NULL
;
7702 expr1
.X_add_number
= 1;
7721 mips_emit_delays (TRUE
);
7722 ++mips_opts
.noreorder
;
7723 mips_any_noreorder
= 1;
7724 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7725 dbl
? "ddiv" : "div",
7726 "0,x,y", xreg
, yreg
);
7727 expr1
.X_add_number
= 2;
7728 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7729 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7732 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7733 since that causes an overflow. We should do that as well,
7734 but I don't see how to do the comparisons without a temporary
7736 --mips_opts
.noreorder
;
7737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7756 mips_emit_delays (TRUE
);
7757 ++mips_opts
.noreorder
;
7758 mips_any_noreorder
= 1;
7759 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7761 expr1
.X_add_number
= 2;
7762 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7765 --mips_opts
.noreorder
;
7766 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7772 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7773 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7774 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7783 if (imm_expr
.X_op
!= O_constant
)
7784 as_bad (_("Unsupported large constant"));
7785 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7786 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7787 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7791 if (imm_expr
.X_op
!= O_constant
)
7792 as_bad (_("Unsupported large constant"));
7793 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7794 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7799 if (imm_expr
.X_op
!= O_constant
)
7800 as_bad (_("Unsupported large constant"));
7801 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7802 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7825 goto do_reverse_branch
;
7829 goto do_reverse_branch
;
7841 goto do_reverse_branch
;
7852 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7854 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7881 goto do_addone_branch_i
;
7886 goto do_addone_branch_i
;
7901 goto do_addone_branch_i
;
7908 if (imm_expr
.X_op
!= O_constant
)
7909 as_bad (_("Unsupported large constant"));
7910 ++imm_expr
.X_add_number
;
7913 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7914 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7918 expr1
.X_add_number
= 0;
7919 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7921 move_register (&icnt
, xreg
, yreg
);
7922 expr1
.X_add_number
= 2;
7923 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7924 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7925 "neg", "x,w", xreg
, xreg
);
7929 /* For consistency checking, verify that all bits are specified either
7930 by the match/mask part of the instruction definition, or by the
7933 validate_mips_insn (opc
)
7934 const struct mips_opcode
*opc
;
7936 const char *p
= opc
->args
;
7938 unsigned long used_bits
= opc
->mask
;
7940 if ((used_bits
& opc
->match
) != opc
->match
)
7942 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7943 opc
->name
, opc
->args
);
7946 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7953 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7954 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7956 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7957 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7958 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7959 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7961 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7962 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7964 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7966 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7967 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7968 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7969 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7970 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7971 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7972 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7973 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7974 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7975 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7976 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7977 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7978 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7979 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7980 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7981 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7982 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7984 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7985 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7986 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7987 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7989 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7990 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7991 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7992 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7993 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7994 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7995 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7996 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7997 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8000 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8001 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8002 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8003 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8004 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8008 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8009 c
, opc
->name
, opc
->args
);
8013 if (used_bits
!= 0xffffffff)
8015 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8016 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8022 /* This routine assembles an instruction into its binary format. As a
8023 side effect, it sets one of the global variables imm_reloc or
8024 offset_reloc to the type of relocation to do if one of the operands
8025 is an address expression. */
8030 struct mips_cl_insn
*ip
;
8035 struct mips_opcode
*insn
;
8038 unsigned int lastregno
= 0;
8044 /* If the instruction contains a '.', we first try to match an instruction
8045 including the '.'. Then we try again without the '.'. */
8047 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8050 /* If we stopped on whitespace, then replace the whitespace with null for
8051 the call to hash_find. Save the character we replaced just in case we
8052 have to re-parse the instruction. */
8059 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8061 /* If we didn't find the instruction in the opcode table, try again, but
8062 this time with just the instruction up to, but not including the
8066 /* Restore the character we overwrite above (if any). */
8070 /* Scan up to the first '.' or whitespace. */
8072 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8076 /* If we did not find a '.', then we can quit now. */
8079 insn_error
= "unrecognized opcode";
8083 /* Lookup the instruction in the hash table. */
8085 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8087 insn_error
= "unrecognized opcode";
8097 assert (strcmp (insn
->name
, str
) == 0);
8099 if (OPCODE_IS_MEMBER (insn
,
8101 | (file_ase_mips16
? INSN_MIPS16
: 0)
8102 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8103 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8109 if (insn
->pinfo
!= INSN_MACRO
)
8111 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8117 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8118 && strcmp (insn
->name
, insn
[1].name
) == 0)
8127 static char buf
[100];
8128 if (mips_arch_info
->is_isa
)
8130 _("opcode not supported at this ISA level (%s)"),
8131 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8134 _("opcode not supported on this processor: %s (%s)"),
8135 mips_arch_info
->name
,
8136 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8146 ip
->insn_opcode
= insn
->match
;
8148 for (args
= insn
->args
;; ++args
)
8152 s
+= strspn (s
, " \t");
8156 case '\0': /* end of args */
8169 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8173 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8177 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8181 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8187 /* Handle optional base register.
8188 Either the base register is omitted or
8189 we must have a left paren. */
8190 /* This is dependent on the next operand specifier
8191 is a base register specification. */
8192 assert (args
[1] == 'b' || args
[1] == '5'
8193 || args
[1] == '-' || args
[1] == '4');
8197 case ')': /* these must match exactly */
8204 case '<': /* must be at least one digit */
8206 * According to the manual, if the shift amount is greater
8207 * than 31 or less than 0, then the shift amount should be
8208 * mod 32. In reality the mips assembler issues an error.
8209 * We issue a warning and mask out all but the low 5 bits.
8211 my_getExpression (&imm_expr
, s
);
8212 check_absolute_expr (ip
, &imm_expr
);
8213 if ((unsigned long) imm_expr
.X_add_number
> 31)
8215 as_warn (_("Improper shift amount (%lu)"),
8216 (unsigned long) imm_expr
.X_add_number
);
8217 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8219 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8220 imm_expr
.X_op
= O_absent
;
8224 case '>': /* shift amount minus 32 */
8225 my_getExpression (&imm_expr
, s
);
8226 check_absolute_expr (ip
, &imm_expr
);
8227 if ((unsigned long) imm_expr
.X_add_number
< 32
8228 || (unsigned long) imm_expr
.X_add_number
> 63)
8230 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8231 imm_expr
.X_op
= O_absent
;
8235 case 'k': /* cache code */
8236 case 'h': /* prefx code */
8237 my_getExpression (&imm_expr
, s
);
8238 check_absolute_expr (ip
, &imm_expr
);
8239 if ((unsigned long) imm_expr
.X_add_number
> 31)
8241 as_warn (_("Invalid value for `%s' (%lu)"),
8243 (unsigned long) imm_expr
.X_add_number
);
8244 imm_expr
.X_add_number
&= 0x1f;
8247 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8249 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8250 imm_expr
.X_op
= O_absent
;
8254 case 'c': /* break code */
8255 my_getExpression (&imm_expr
, s
);
8256 check_absolute_expr (ip
, &imm_expr
);
8257 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8259 as_warn (_("Illegal break code (%lu)"),
8260 (unsigned long) imm_expr
.X_add_number
);
8261 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8263 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8264 imm_expr
.X_op
= O_absent
;
8268 case 'q': /* lower break code */
8269 my_getExpression (&imm_expr
, s
);
8270 check_absolute_expr (ip
, &imm_expr
);
8271 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8273 as_warn (_("Illegal lower break code (%lu)"),
8274 (unsigned long) imm_expr
.X_add_number
);
8275 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8277 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8278 imm_expr
.X_op
= O_absent
;
8282 case 'B': /* 20-bit syscall/break code. */
8283 my_getExpression (&imm_expr
, s
);
8284 check_absolute_expr (ip
, &imm_expr
);
8285 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8286 as_warn (_("Illegal 20-bit code (%lu)"),
8287 (unsigned long) imm_expr
.X_add_number
);
8288 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8289 imm_expr
.X_op
= O_absent
;
8293 case 'C': /* Coprocessor code */
8294 my_getExpression (&imm_expr
, s
);
8295 check_absolute_expr (ip
, &imm_expr
);
8296 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8298 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8299 (unsigned long) imm_expr
.X_add_number
);
8300 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8302 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8303 imm_expr
.X_op
= O_absent
;
8307 case 'J': /* 19-bit wait code. */
8308 my_getExpression (&imm_expr
, s
);
8309 check_absolute_expr (ip
, &imm_expr
);
8310 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8311 as_warn (_("Illegal 19-bit code (%lu)"),
8312 (unsigned long) imm_expr
.X_add_number
);
8313 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8314 imm_expr
.X_op
= O_absent
;
8318 case 'P': /* Performance register */
8319 my_getExpression (&imm_expr
, s
);
8320 check_absolute_expr (ip
, &imm_expr
);
8321 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8323 as_warn (_("Invalid performance register (%lu)"),
8324 (unsigned long) imm_expr
.X_add_number
);
8325 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8327 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8328 imm_expr
.X_op
= O_absent
;
8332 case 'b': /* base register */
8333 case 'd': /* destination register */
8334 case 's': /* source register */
8335 case 't': /* target register */
8336 case 'r': /* both target and source */
8337 case 'v': /* both dest and source */
8338 case 'w': /* both dest and target */
8339 case 'E': /* coprocessor target register */
8340 case 'G': /* coprocessor destination register */
8341 case 'x': /* ignore register name */
8342 case 'z': /* must be zero register */
8343 case 'U': /* destination register (clo/clz). */
8358 while (ISDIGIT (*s
));
8360 as_bad (_("Invalid register number (%d)"), regno
);
8362 else if (*args
== 'E' || *args
== 'G')
8366 if (s
[1] == 'r' && s
[2] == 'a')
8371 else if (s
[1] == 'f' && s
[2] == 'p')
8376 else if (s
[1] == 's' && s
[2] == 'p')
8381 else if (s
[1] == 'g' && s
[2] == 'p')
8386 else if (s
[1] == 'a' && s
[2] == 't')
8391 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8396 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8401 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8406 else if (itbl_have_entries
)
8411 p
= s
+ 1; /* advance past '$' */
8412 n
= itbl_get_field (&p
); /* n is name */
8414 /* See if this is a register defined in an
8416 if (itbl_get_reg_val (n
, &r
))
8418 /* Get_field advances to the start of
8419 the next field, so we need to back
8420 rack to the end of the last field. */
8424 s
= strchr (s
, '\0');
8437 as_warn (_("Used $at without \".set noat\""));
8443 if (c
== 'r' || c
== 'v' || c
== 'w')
8450 /* 'z' only matches $0. */
8451 if (c
== 'z' && regno
!= 0)
8454 /* Now that we have assembled one operand, we use the args string
8455 * to figure out where it goes in the instruction. */
8462 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8466 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8469 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8470 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8475 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8478 /* This case exists because on the r3000 trunc
8479 expands into a macro which requires a gp
8480 register. On the r6000 or r4000 it is
8481 assembled into a single instruction which
8482 ignores the register. Thus the insn version
8483 is MIPS_ISA2 and uses 'x', and the macro
8484 version is MIPS_ISA1 and uses 't'. */
8487 /* This case is for the div instruction, which
8488 acts differently if the destination argument
8489 is $0. This only matches $0, and is checked
8490 outside the switch. */
8493 /* Itbl operand; not yet implemented. FIXME ?? */
8495 /* What about all other operands like 'i', which
8496 can be specified in the opcode table? */
8506 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8509 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8514 case 'O': /* MDMX alignment immediate constant. */
8515 my_getExpression (&imm_expr
, s
);
8516 check_absolute_expr (ip
, &imm_expr
);
8517 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8519 as_warn ("Improper align amount (%ld), using low bits",
8520 (long) imm_expr
.X_add_number
);
8521 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8523 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8524 imm_expr
.X_op
= O_absent
;
8528 case 'Q': /* MDMX vector, element sel, or const. */
8531 /* MDMX Immediate. */
8532 my_getExpression (&imm_expr
, s
);
8533 check_absolute_expr (ip
, &imm_expr
);
8534 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8536 as_warn (_("Invalid MDMX Immediate (%ld)"),
8537 (long) imm_expr
.X_add_number
);
8538 imm_expr
.X_add_number
&= OP_MASK_FT
;
8540 imm_expr
.X_add_number
&= OP_MASK_FT
;
8541 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8542 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8544 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8545 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8546 imm_expr
.X_op
= O_absent
;
8550 /* Not MDMX Immediate. Fall through. */
8551 case 'X': /* MDMX destination register. */
8552 case 'Y': /* MDMX source register. */
8553 case 'Z': /* MDMX target register. */
8555 case 'D': /* floating point destination register */
8556 case 'S': /* floating point source register */
8557 case 'T': /* floating point target register */
8558 case 'R': /* floating point source register */
8562 /* Accept $fN for FP and MDMX register numbers, and in
8563 addition accept $vN for MDMX register numbers. */
8564 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8565 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8576 while (ISDIGIT (*s
));
8579 as_bad (_("Invalid float register number (%d)"), regno
);
8581 if ((regno
& 1) != 0
8583 && ! (strcmp (str
, "mtc1") == 0
8584 || strcmp (str
, "mfc1") == 0
8585 || strcmp (str
, "lwc1") == 0
8586 || strcmp (str
, "swc1") == 0
8587 || strcmp (str
, "l.s") == 0
8588 || strcmp (str
, "s.s") == 0))
8589 as_warn (_("Float register should be even, was %d"),
8597 if (c
== 'V' || c
== 'W')
8608 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8613 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8616 /* This is like 'Z', but also needs to fix the MDMX
8617 vector/scalar select bits. Note that the
8618 scalar immediate case is handled above. */
8621 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8622 int max_el
= (is_qh
? 3 : 7);
8624 my_getExpression(&imm_expr
, s
);
8625 check_absolute_expr (ip
, &imm_expr
);
8627 if (imm_expr
.X_add_number
> max_el
)
8628 as_bad(_("Bad element selector %ld"),
8629 (long) imm_expr
.X_add_number
);
8630 imm_expr
.X_add_number
&= max_el
;
8631 ip
->insn_opcode
|= (imm_expr
.X_add_number
8635 as_warn(_("Expecting ']' found '%s'"), s
);
8641 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8642 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8645 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8652 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8655 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8665 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8668 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8674 my_getExpression (&imm_expr
, s
);
8675 if (imm_expr
.X_op
!= O_big
8676 && imm_expr
.X_op
!= O_constant
)
8677 insn_error
= _("absolute expression required");
8682 my_getExpression (&offset_expr
, s
);
8683 *imm_reloc
= BFD_RELOC_32
;
8696 unsigned char temp
[8];
8698 unsigned int length
;
8703 /* These only appear as the last operand in an
8704 instruction, and every instruction that accepts
8705 them in any variant accepts them in all variants.
8706 This means we don't have to worry about backing out
8707 any changes if the instruction does not match.
8709 The difference between them is the size of the
8710 floating point constant and where it goes. For 'F'
8711 and 'L' the constant is 64 bits; for 'f' and 'l' it
8712 is 32 bits. Where the constant is placed is based
8713 on how the MIPS assembler does things:
8716 f -- immediate value
8719 The .lit4 and .lit8 sections are only used if
8720 permitted by the -G argument.
8722 When generating embedded PIC code, we use the
8723 .lit8 section but not the .lit4 section (we can do
8724 .lit4 inline easily; we need to put .lit8
8725 somewhere in the data segment, and using .lit8
8726 permits the linker to eventually combine identical
8729 The code below needs to know whether the target register
8730 is 32 or 64 bits wide. It relies on the fact 'f' and
8731 'F' are used with GPR-based instructions and 'l' and
8732 'L' are used with FPR-based instructions. */
8734 f64
= *args
== 'F' || *args
== 'L';
8735 using_gprs
= *args
== 'F' || *args
== 'f';
8737 save_in
= input_line_pointer
;
8738 input_line_pointer
= s
;
8739 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8741 s
= input_line_pointer
;
8742 input_line_pointer
= save_in
;
8743 if (err
!= NULL
&& *err
!= '\0')
8745 as_bad (_("Bad floating point constant: %s"), err
);
8746 memset (temp
, '\0', sizeof temp
);
8747 length
= f64
? 8 : 4;
8750 assert (length
== (unsigned) (f64
? 8 : 4));
8754 && (! USE_GLOBAL_POINTER_OPT
8755 || mips_pic
== EMBEDDED_PIC
8756 || g_switch_value
< 4
8757 || (temp
[0] == 0 && temp
[1] == 0)
8758 || (temp
[2] == 0 && temp
[3] == 0))))
8760 imm_expr
.X_op
= O_constant
;
8761 if (! target_big_endian
)
8762 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8764 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8767 && ! mips_disable_float_construction
8768 /* Constants can only be constructed in GPRs and
8769 copied to FPRs if the GPRs are at least as wide
8770 as the FPRs. Force the constant into memory if
8771 we are using 64-bit FPRs but the GPRs are only
8774 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8775 && ((temp
[0] == 0 && temp
[1] == 0)
8776 || (temp
[2] == 0 && temp
[3] == 0))
8777 && ((temp
[4] == 0 && temp
[5] == 0)
8778 || (temp
[6] == 0 && temp
[7] == 0)))
8780 /* The value is simple enough to load with a couple of
8781 instructions. If using 32-bit registers, set
8782 imm_expr to the high order 32 bits and offset_expr to
8783 the low order 32 bits. Otherwise, set imm_expr to
8784 the entire 64 bit constant. */
8785 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8787 imm_expr
.X_op
= O_constant
;
8788 offset_expr
.X_op
= O_constant
;
8789 if (! target_big_endian
)
8791 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8792 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8796 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8797 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8799 if (offset_expr
.X_add_number
== 0)
8800 offset_expr
.X_op
= O_absent
;
8802 else if (sizeof (imm_expr
.X_add_number
) > 4)
8804 imm_expr
.X_op
= O_constant
;
8805 if (! target_big_endian
)
8806 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8808 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8812 imm_expr
.X_op
= O_big
;
8813 imm_expr
.X_add_number
= 4;
8814 if (! target_big_endian
)
8816 generic_bignum
[0] = bfd_getl16 (temp
);
8817 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8818 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8819 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8823 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8824 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8825 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8826 generic_bignum
[3] = bfd_getb16 (temp
);
8832 const char *newname
;
8835 /* Switch to the right section. */
8837 subseg
= now_subseg
;
8840 default: /* unused default case avoids warnings. */
8842 newname
= RDATA_SECTION_NAME
;
8843 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8844 || mips_pic
== EMBEDDED_PIC
)
8848 if (mips_pic
== EMBEDDED_PIC
)
8851 newname
= RDATA_SECTION_NAME
;
8854 assert (!USE_GLOBAL_POINTER_OPT
8855 || g_switch_value
>= 4);
8859 new_seg
= subseg_new (newname
, (subsegT
) 0);
8860 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8861 bfd_set_section_flags (stdoutput
, new_seg
,
8866 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8867 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8868 && strcmp (TARGET_OS
, "elf") != 0)
8869 record_alignment (new_seg
, 4);
8871 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8873 as_bad (_("Can't use floating point insn in this section"));
8875 /* Set the argument to the current address in the
8877 offset_expr
.X_op
= O_symbol
;
8878 offset_expr
.X_add_symbol
=
8879 symbol_new ("L0\001", now_seg
,
8880 (valueT
) frag_now_fix (), frag_now
);
8881 offset_expr
.X_add_number
= 0;
8883 /* Put the floating point number into the section. */
8884 p
= frag_more ((int) length
);
8885 memcpy (p
, temp
, length
);
8887 /* Switch back to the original section. */
8888 subseg_set (seg
, subseg
);
8893 case 'i': /* 16 bit unsigned immediate */
8894 case 'j': /* 16 bit signed immediate */
8895 *imm_reloc
= BFD_RELOC_LO16
;
8896 c
= my_getSmallExpression (&imm_expr
, s
);
8903 *imm_reloc
= BFD_RELOC_HI16_S
;
8904 imm_unmatched_hi
= TRUE
;
8907 else if (c
== S_EX_HIGHEST
)
8908 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8909 else if (c
== S_EX_HIGHER
)
8910 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8911 else if (c
== S_EX_GP_REL
)
8913 /* This occurs in NewABI only. */
8914 c
= my_getSmallExpression (&imm_expr
, s
);
8916 as_bad (_("bad composition of relocations"));
8919 c
= my_getSmallExpression (&imm_expr
, s
);
8921 as_bad (_("bad composition of relocations"));
8924 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8925 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8926 imm_reloc
[2] = BFD_RELOC_LO16
;
8932 *imm_reloc
= BFD_RELOC_HI16
;
8934 else if (imm_expr
.X_op
== O_constant
)
8935 imm_expr
.X_add_number
&= 0xffff;
8939 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8940 || ((imm_expr
.X_add_number
< 0
8941 || imm_expr
.X_add_number
>= 0x10000)
8942 && imm_expr
.X_op
== O_constant
))
8944 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8945 !strcmp (insn
->name
, insn
[1].name
))
8947 if (imm_expr
.X_op
== O_constant
8948 || imm_expr
.X_op
== O_big
)
8949 as_bad (_("16 bit expression not in range 0..65535"));
8957 /* The upper bound should be 0x8000, but
8958 unfortunately the MIPS assembler accepts numbers
8959 from 0x8000 to 0xffff and sign extends them, and
8960 we want to be compatible. We only permit this
8961 extended range for an instruction which does not
8962 provide any further alternates, since those
8963 alternates may handle other cases. People should
8964 use the numbers they mean, rather than relying on
8965 a mysterious sign extension. */
8966 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8967 strcmp (insn
->name
, insn
[1].name
) == 0);
8972 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8973 || ((imm_expr
.X_add_number
< -0x8000
8974 || imm_expr
.X_add_number
>= max
)
8975 && imm_expr
.X_op
== O_constant
)
8977 && imm_expr
.X_add_number
< 0
8979 && imm_expr
.X_unsigned
8980 && sizeof (imm_expr
.X_add_number
) <= 4))
8984 if (imm_expr
.X_op
== O_constant
8985 || imm_expr
.X_op
== O_big
)
8986 as_bad (_("16 bit expression not in range -32768..32767"));
8992 case 'o': /* 16 bit offset */
8993 c
= my_getSmallExpression (&offset_expr
, s
);
8995 /* If this value won't fit into a 16 bit offset, then go
8996 find a macro that will generate the 32 bit offset
8999 && (offset_expr
.X_op
!= O_constant
9000 || offset_expr
.X_add_number
>= 0x8000
9001 || offset_expr
.X_add_number
< -0x8000))
9006 if (offset_expr
.X_op
!= O_constant
)
9008 offset_expr
.X_add_number
=
9009 (offset_expr
.X_add_number
>> 16) & 0xffff;
9011 *offset_reloc
= BFD_RELOC_LO16
;
9015 case 'p': /* pc relative offset */
9016 if (mips_pic
== EMBEDDED_PIC
)
9017 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9019 *offset_reloc
= BFD_RELOC_16_PCREL
;
9020 my_getExpression (&offset_expr
, s
);
9024 case 'u': /* upper 16 bits */
9025 c
= my_getSmallExpression (&imm_expr
, s
);
9026 *imm_reloc
= BFD_RELOC_LO16
;
9033 *imm_reloc
= BFD_RELOC_HI16_S
;
9034 imm_unmatched_hi
= TRUE
;
9037 else if (c
== S_EX_HIGHEST
)
9038 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
9039 else if (c
== S_EX_GP_REL
)
9041 /* This occurs in NewABI only. */
9042 c
= my_getSmallExpression (&imm_expr
, s
);
9044 as_bad (_("bad composition of relocations"));
9047 c
= my_getSmallExpression (&imm_expr
, s
);
9049 as_bad (_("bad composition of relocations"));
9052 imm_reloc
[0] = BFD_RELOC_GPREL16
;
9053 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
9054 imm_reloc
[2] = BFD_RELOC_HI16_S
;
9060 *imm_reloc
= BFD_RELOC_HI16
;
9062 else if (imm_expr
.X_op
== O_constant
)
9063 imm_expr
.X_add_number
&= 0xffff;
9065 else if (imm_expr
.X_op
== O_constant
9066 && (imm_expr
.X_add_number
< 0
9067 || imm_expr
.X_add_number
>= 0x10000))
9068 as_bad (_("lui expression not in range 0..65535"));
9072 case 'a': /* 26 bit address */
9073 my_getExpression (&offset_expr
, s
);
9075 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9078 case 'N': /* 3 bit branch condition code */
9079 case 'M': /* 3 bit compare condition code */
9080 if (strncmp (s
, "$fcc", 4) != 0)
9090 while (ISDIGIT (*s
));
9092 as_bad (_("invalid condition code register $fcc%d"), regno
);
9094 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9096 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9100 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9111 while (ISDIGIT (*s
));
9114 c
= 8; /* Invalid sel value. */
9117 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9118 ip
->insn_opcode
|= c
;
9122 /* Must be at least one digit. */
9123 my_getExpression (&imm_expr
, s
);
9124 check_absolute_expr (ip
, &imm_expr
);
9126 if ((unsigned long) imm_expr
.X_add_number
9127 > (unsigned long) OP_MASK_VECBYTE
)
9129 as_bad (_("bad byte vector index (%ld)"),
9130 (long) imm_expr
.X_add_number
);
9131 imm_expr
.X_add_number
= 0;
9134 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9135 imm_expr
.X_op
= O_absent
;
9140 my_getExpression (&imm_expr
, s
);
9141 check_absolute_expr (ip
, &imm_expr
);
9143 if ((unsigned long) imm_expr
.X_add_number
9144 > (unsigned long) OP_MASK_VECALIGN
)
9146 as_bad (_("bad byte vector index (%ld)"),
9147 (long) imm_expr
.X_add_number
);
9148 imm_expr
.X_add_number
= 0;
9151 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9152 imm_expr
.X_op
= O_absent
;
9157 as_bad (_("bad char = '%c'\n"), *args
);
9162 /* Args don't match. */
9163 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9164 !strcmp (insn
->name
, insn
[1].name
))
9168 insn_error
= _("illegal operands");
9173 insn_error
= _("illegal operands");
9178 /* This routine assembles an instruction into its binary format when
9179 assembling for the mips16. As a side effect, it sets one of the
9180 global variables imm_reloc or offset_reloc to the type of
9181 relocation to do if one of the operands is an address expression.
9182 It also sets mips16_small and mips16_ext if the user explicitly
9183 requested a small or extended instruction. */
9188 struct mips_cl_insn
*ip
;
9192 struct mips_opcode
*insn
;
9195 unsigned int lastregno
= 0;
9200 mips16_small
= FALSE
;
9203 for (s
= str
; ISLOWER (*s
); ++s
)
9215 if (s
[1] == 't' && s
[2] == ' ')
9218 mips16_small
= TRUE
;
9222 else if (s
[1] == 'e' && s
[2] == ' ')
9231 insn_error
= _("unknown opcode");
9235 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9236 mips16_small
= TRUE
;
9238 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9240 insn_error
= _("unrecognized opcode");
9247 assert (strcmp (insn
->name
, str
) == 0);
9250 ip
->insn_opcode
= insn
->match
;
9251 ip
->use_extend
= FALSE
;
9252 imm_expr
.X_op
= O_absent
;
9253 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9254 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9255 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9256 offset_expr
.X_op
= O_absent
;
9257 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9258 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9259 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9260 for (args
= insn
->args
; 1; ++args
)
9267 /* In this switch statement we call break if we did not find
9268 a match, continue if we did find a match, or return if we
9277 /* Stuff the immediate value in now, if we can. */
9278 if (imm_expr
.X_op
== O_constant
9279 && *imm_reloc
> BFD_RELOC_UNUSED
9280 && insn
->pinfo
!= INSN_MACRO
)
9282 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9283 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9284 mips16_ext
, &ip
->insn_opcode
,
9285 &ip
->use_extend
, &ip
->extend
);
9286 imm_expr
.X_op
= O_absent
;
9287 *imm_reloc
= BFD_RELOC_UNUSED
;
9301 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9304 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9320 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9322 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9349 while (ISDIGIT (*s
));
9352 as_bad (_("invalid register number (%d)"), regno
);
9358 if (s
[1] == 'r' && s
[2] == 'a')
9363 else if (s
[1] == 'f' && s
[2] == 'p')
9368 else if (s
[1] == 's' && s
[2] == 'p')
9373 else if (s
[1] == 'g' && s
[2] == 'p')
9378 else if (s
[1] == 'a' && s
[2] == 't')
9383 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9388 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9393 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9406 if (c
== 'v' || c
== 'w')
9408 regno
= mips16_to_32_reg_map
[lastregno
];
9422 regno
= mips32_to_16_reg_map
[regno
];
9427 regno
= ILLEGAL_REG
;
9432 regno
= ILLEGAL_REG
;
9437 regno
= ILLEGAL_REG
;
9442 if (regno
== AT
&& ! mips_opts
.noat
)
9443 as_warn (_("used $at without \".set noat\""));
9450 if (regno
== ILLEGAL_REG
)
9457 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9461 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9464 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9467 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9473 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9476 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9477 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9487 if (strncmp (s
, "$pc", 3) == 0)
9511 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9513 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9514 and generate the appropriate reloc. If the text
9515 inside %gprel is not a symbol name with an
9516 optional offset, then we generate a normal reloc
9517 and will probably fail later. */
9518 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9519 if (imm_expr
.X_op
== O_symbol
)
9522 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9524 ip
->use_extend
= TRUE
;
9531 /* Just pick up a normal expression. */
9532 my_getExpression (&imm_expr
, s
);
9535 if (imm_expr
.X_op
== O_register
)
9537 /* What we thought was an expression turned out to
9540 if (s
[0] == '(' && args
[1] == '(')
9542 /* It looks like the expression was omitted
9543 before a register indirection, which means
9544 that the expression is implicitly zero. We
9545 still set up imm_expr, so that we handle
9546 explicit extensions correctly. */
9547 imm_expr
.X_op
= O_constant
;
9548 imm_expr
.X_add_number
= 0;
9549 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9556 /* We need to relax this instruction. */
9557 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9566 /* We use offset_reloc rather than imm_reloc for the PC
9567 relative operands. This lets macros with both
9568 immediate and address operands work correctly. */
9569 my_getExpression (&offset_expr
, s
);
9571 if (offset_expr
.X_op
== O_register
)
9574 /* We need to relax this instruction. */
9575 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9579 case '6': /* break code */
9580 my_getExpression (&imm_expr
, s
);
9581 check_absolute_expr (ip
, &imm_expr
);
9582 if ((unsigned long) imm_expr
.X_add_number
> 63)
9584 as_warn (_("Invalid value for `%s' (%lu)"),
9586 (unsigned long) imm_expr
.X_add_number
);
9587 imm_expr
.X_add_number
&= 0x3f;
9589 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9590 imm_expr
.X_op
= O_absent
;
9594 case 'a': /* 26 bit address */
9595 my_getExpression (&offset_expr
, s
);
9597 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9598 ip
->insn_opcode
<<= 16;
9601 case 'l': /* register list for entry macro */
9602 case 'L': /* register list for exit macro */
9612 int freg
, reg1
, reg2
;
9614 while (*s
== ' ' || *s
== ',')
9618 as_bad (_("can't parse register list"));
9630 while (ISDIGIT (*s
))
9652 as_bad (_("invalid register list"));
9657 while (ISDIGIT (*s
))
9664 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9669 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9674 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9675 mask
|= (reg2
- 3) << 3;
9676 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9677 mask
|= (reg2
- 15) << 1;
9678 else if (reg1
== RA
&& reg2
== RA
)
9682 as_bad (_("invalid register list"));
9686 /* The mask is filled in in the opcode table for the
9687 benefit of the disassembler. We remove it before
9688 applying the actual mask. */
9689 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9690 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9694 case 'e': /* extend code */
9695 my_getExpression (&imm_expr
, s
);
9696 check_absolute_expr (ip
, &imm_expr
);
9697 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9699 as_warn (_("Invalid value for `%s' (%lu)"),
9701 (unsigned long) imm_expr
.X_add_number
);
9702 imm_expr
.X_add_number
&= 0x7ff;
9704 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9705 imm_expr
.X_op
= O_absent
;
9715 /* Args don't match. */
9716 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9717 strcmp (insn
->name
, insn
[1].name
) == 0)
9724 insn_error
= _("illegal operands");
9730 /* This structure holds information we know about a mips16 immediate
9733 struct mips16_immed_operand
9735 /* The type code used in the argument string in the opcode table. */
9737 /* The number of bits in the short form of the opcode. */
9739 /* The number of bits in the extended form of the opcode. */
9741 /* The amount by which the short form is shifted when it is used;
9742 for example, the sw instruction has a shift count of 2. */
9744 /* The amount by which the short form is shifted when it is stored
9745 into the instruction code. */
9747 /* Non-zero if the short form is unsigned. */
9749 /* Non-zero if the extended form is unsigned. */
9751 /* Non-zero if the value is PC relative. */
9755 /* The mips16 immediate operand types. */
9757 static const struct mips16_immed_operand mips16_immed_operands
[] =
9759 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9760 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9761 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9762 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9763 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9764 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9765 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9766 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9767 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9768 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9769 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9770 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9771 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9772 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9773 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9774 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9775 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9776 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9777 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9778 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9779 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9782 #define MIPS16_NUM_IMMED \
9783 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9785 /* Handle a mips16 instruction with an immediate value. This or's the
9786 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9787 whether an extended value is needed; if one is needed, it sets
9788 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9789 If SMALL is true, an unextended opcode was explicitly requested.
9790 If EXT is true, an extended opcode was explicitly requested. If
9791 WARN is true, warn if EXT does not match reality. */
9794 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9803 unsigned long *insn
;
9804 bfd_boolean
*use_extend
;
9805 unsigned short *extend
;
9807 register const struct mips16_immed_operand
*op
;
9808 int mintiny
, maxtiny
;
9809 bfd_boolean needext
;
9811 op
= mips16_immed_operands
;
9812 while (op
->type
!= type
)
9815 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9820 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9823 maxtiny
= 1 << op
->nbits
;
9828 maxtiny
= (1 << op
->nbits
) - 1;
9833 mintiny
= - (1 << (op
->nbits
- 1));
9834 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9837 /* Branch offsets have an implicit 0 in the lowest bit. */
9838 if (type
== 'p' || type
== 'q')
9841 if ((val
& ((1 << op
->shift
) - 1)) != 0
9842 || val
< (mintiny
<< op
->shift
)
9843 || val
> (maxtiny
<< op
->shift
))
9848 if (warn
&& ext
&& ! needext
)
9849 as_warn_where (file
, line
,
9850 _("extended operand requested but not required"));
9851 if (small
&& needext
)
9852 as_bad_where (file
, line
, _("invalid unextended operand value"));
9854 if (small
|| (! ext
&& ! needext
))
9858 *use_extend
= FALSE
;
9859 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9860 insnval
<<= op
->op_shift
;
9865 long minext
, maxext
;
9871 maxext
= (1 << op
->extbits
) - 1;
9875 minext
= - (1 << (op
->extbits
- 1));
9876 maxext
= (1 << (op
->extbits
- 1)) - 1;
9878 if (val
< minext
|| val
> maxext
)
9879 as_bad_where (file
, line
,
9880 _("operand value out of range for instruction"));
9883 if (op
->extbits
== 16)
9885 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9888 else if (op
->extbits
== 15)
9890 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9895 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9899 *extend
= (unsigned short) extval
;
9904 static struct percent_op_match
9907 const enum small_ex_type type
;
9912 {"%call_hi", S_EX_CALL_HI
},
9913 {"%call_lo", S_EX_CALL_LO
},
9914 {"%call16", S_EX_CALL16
},
9915 {"%got_disp", S_EX_GOT_DISP
},
9916 {"%got_page", S_EX_GOT_PAGE
},
9917 {"%got_ofst", S_EX_GOT_OFST
},
9918 {"%got_hi", S_EX_GOT_HI
},
9919 {"%got_lo", S_EX_GOT_LO
},
9921 {"%gp_rel", S_EX_GP_REL
},
9922 {"%half", S_EX_HALF
},
9923 {"%highest", S_EX_HIGHEST
},
9924 {"%higher", S_EX_HIGHER
},
9930 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9931 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9932 can be nested, this is handled by blanking the innermost, parsing the
9933 rest by subsequent calls. */
9936 my_getSmallParser (str
, len
, nestlevel
)
9942 *str
+= strspn (*str
, " \t");
9943 /* Check for expression in parentheses. */
9946 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9949 /* Check for base register. */
9953 && (e
= b
+ strcspn (b
, ") \t"))
9954 && e
- b
> 1 && e
- b
< 4)
9957 && ((b
[1] == 'f' && b
[2] == 'p')
9958 || (b
[1] == 's' && b
[2] == 'p')
9959 || (b
[1] == 'g' && b
[2] == 'p')
9960 || (b
[1] == 'a' && b
[2] == 't')
9962 && ISDIGIT (b
[2]))))
9963 || (ISDIGIT (b
[1])))
9965 *len
= strcspn (*str
, ")") + 1;
9966 return S_EX_REGISTER
;
9970 /* Check for percent_op (in parentheses). */
9971 else if (b
[0] == '%')
9974 return my_getPercentOp (str
, len
, nestlevel
);
9977 /* Some other expression in the parentheses, which can contain
9978 parentheses itself. Attempt to find the matching one. */
9984 for (s
= *str
+ 1; *s
&& pcnt
; s
++, (*len
)++)
9993 /* Check for percent_op (outside of parentheses). */
9994 else if (*str
[0] == '%')
9995 return my_getPercentOp (str
, len
, nestlevel
);
9997 /* Any other expression. */
10002 my_getPercentOp (str
, len
, nestlevel
)
10007 char *tmp
= *str
+ 1;
10008 unsigned int i
= 0;
10010 while (ISALPHA (*tmp
) || *tmp
== '_')
10012 *tmp
= TOLOWER (*tmp
);
10015 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
10017 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
10021 int type
= percent_op
[i
].type
;
10023 /* Only %hi and %lo are allowed for OldABI. */
10024 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
10027 *len
= strlen (percent_op
[i
].str
);
10036 my_getSmallExpression (ep
, str
)
10040 static char *oldstr
= NULL
;
10043 int nestlevel
= -1;
10046 /* Don't update oldstr if the last call had nested percent_op's. We need
10047 it to parse the outer ones later. */
10054 c
= my_getSmallParser (&str
, &len
, &nestlevel
);
10055 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
10058 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
10060 if (nestlevel
>= 0)
10062 /* A percent_op was encountered. Don't try to get an expression if
10063 it is already blanked out. */
10064 if (*(str
+ strspn (str
+ 1, " )")) != ')')
10068 /* Let my_getExpression() stop at the closing parenthesis. */
10069 save
= *(str
+ len
);
10070 *(str
+ len
) = '\0';
10071 my_getExpression (ep
, str
);
10072 *(str
+ len
) = save
;
10076 /* Blank out including the % sign and the proper matching
10079 char *s
= strrchr (oldstr
, '%');
10082 for (end
= strchr (s
, '(') + 1; *end
&& pcnt
; end
++)
10086 else if (*end
== ')')
10090 memset (s
, ' ', end
- s
);
10094 expr_end
= str
+ len
;
10098 else if (c
== S_EX_NONE
)
10100 my_getExpression (ep
, str
);
10102 else if (c
== S_EX_REGISTER
)
10104 ep
->X_op
= O_constant
;
10106 ep
->X_add_symbol
= NULL
;
10107 ep
->X_op_symbol
= NULL
;
10108 ep
->X_add_number
= 0;
10112 as_fatal (_("internal error"));
10115 if (nestlevel
<= 0)
10116 /* All percent_op's have been handled. */
10123 my_getExpression (ep
, str
)
10130 save_in
= input_line_pointer
;
10131 input_line_pointer
= str
;
10133 expr_end
= input_line_pointer
;
10134 input_line_pointer
= save_in
;
10136 /* If we are in mips16 mode, and this is an expression based on `.',
10137 then we bump the value of the symbol by 1 since that is how other
10138 text symbols are handled. We don't bother to handle complex
10139 expressions, just `.' plus or minus a constant. */
10140 if (mips_opts
.mips16
10141 && ep
->X_op
== O_symbol
10142 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10143 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10144 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10145 && symbol_constant_p (ep
->X_add_symbol
)
10146 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10147 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10150 /* Turn a string in input_line_pointer into a floating point constant
10151 of type TYPE, and store the appropriate bytes in *LITP. The number
10152 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10153 returned, or NULL on OK. */
10156 md_atof (type
, litP
, sizeP
)
10162 LITTLENUM_TYPE words
[4];
10178 return _("bad call to md_atof");
10181 t
= atof_ieee (input_line_pointer
, type
, words
);
10183 input_line_pointer
= t
;
10187 if (! target_big_endian
)
10189 for (i
= prec
- 1; i
>= 0; i
--)
10191 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10197 for (i
= 0; i
< prec
; i
++)
10199 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10208 md_number_to_chars (buf
, val
, n
)
10213 if (target_big_endian
)
10214 number_to_chars_bigendian (buf
, val
, n
);
10216 number_to_chars_littleendian (buf
, val
, n
);
10220 static int support_64bit_objects(void)
10222 const char **list
, **l
;
10225 list
= bfd_target_list ();
10226 for (l
= list
; *l
!= NULL
; l
++)
10228 /* This is traditional mips */
10229 if (strcmp (*l
, "elf64-tradbigmips") == 0
10230 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10232 if (strcmp (*l
, "elf64-bigmips") == 0
10233 || strcmp (*l
, "elf64-littlemips") == 0)
10236 yes
= (*l
!= NULL
);
10240 #endif /* OBJ_ELF */
10242 const char *md_shortopts
= "nO::g::G:";
10244 struct option md_longopts
[] =
10246 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10247 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10248 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10249 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10250 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10251 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10252 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10253 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10254 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10255 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10256 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10257 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10258 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10259 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10260 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10261 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10262 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10263 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10264 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10265 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10266 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10267 {"break", no_argument
, NULL
, OPTION_BREAK
},
10268 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10269 #define OPTION_EB (OPTION_MD_BASE + 11)
10270 {"EB", no_argument
, NULL
, OPTION_EB
},
10271 #define OPTION_EL (OPTION_MD_BASE + 12)
10272 {"EL", no_argument
, NULL
, OPTION_EL
},
10273 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10274 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10275 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10276 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10277 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10278 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10279 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10280 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10281 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10282 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10283 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10284 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10285 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10286 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10287 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10288 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10289 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10290 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10291 {"march", required_argument
, NULL
, OPTION_MARCH
},
10292 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10293 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10294 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10295 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10296 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10297 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10298 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10299 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10300 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10301 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10302 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10303 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10304 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10305 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10306 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10307 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10308 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10309 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10310 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10311 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10312 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10313 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10314 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10315 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10316 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10317 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10318 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10319 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10320 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10321 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10322 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10323 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10324 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10325 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10326 #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39)
10327 #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
10328 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10329 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10331 #define OPTION_ELF_BASE (OPTION_MD_BASE + 41)
10332 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10333 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10334 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10335 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10336 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10337 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10338 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10339 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10340 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10341 #define OPTION_32 (OPTION_ELF_BASE + 4)
10342 {"32", no_argument
, NULL
, OPTION_32
},
10343 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10344 {"n32", no_argument
, NULL
, OPTION_N32
},
10345 #define OPTION_64 (OPTION_ELF_BASE + 6)
10346 {"64", no_argument
, NULL
, OPTION_64
},
10347 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10348 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10349 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10350 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10351 #endif /* OBJ_ELF */
10352 {NULL
, no_argument
, NULL
, 0}
10354 size_t md_longopts_size
= sizeof (md_longopts
);
10356 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10357 NEW_VALUE. Warn if another value was already specified. Note:
10358 we have to defer parsing the -march and -mtune arguments in order
10359 to handle 'from-abi' correctly, since the ABI might be specified
10360 in a later argument. */
10363 mips_set_option_string (string_ptr
, new_value
)
10364 const char **string_ptr
, *new_value
;
10366 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10367 as_warn (_("A different %s was already specified, is now %s"),
10368 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10371 *string_ptr
= new_value
;
10375 md_parse_option (c
, arg
)
10381 case OPTION_CONSTRUCT_FLOATS
:
10382 mips_disable_float_construction
= 0;
10385 case OPTION_NO_CONSTRUCT_FLOATS
:
10386 mips_disable_float_construction
= 1;
10398 target_big_endian
= 1;
10402 target_big_endian
= 0;
10410 if (arg
&& arg
[1] == '0')
10420 mips_debug
= atoi (arg
);
10421 /* When the MIPS assembler sees -g or -g2, it does not do
10422 optimizations which limit full symbolic debugging. We take
10423 that to be equivalent to -O0. */
10424 if (mips_debug
== 2)
10429 file_mips_isa
= ISA_MIPS1
;
10433 file_mips_isa
= ISA_MIPS2
;
10437 file_mips_isa
= ISA_MIPS3
;
10441 file_mips_isa
= ISA_MIPS4
;
10445 file_mips_isa
= ISA_MIPS5
;
10448 case OPTION_MIPS32
:
10449 file_mips_isa
= ISA_MIPS32
;
10452 case OPTION_MIPS64
:
10453 file_mips_isa
= ISA_MIPS64
;
10457 mips_set_option_string (&mips_tune_string
, arg
);
10461 mips_set_option_string (&mips_arch_string
, arg
);
10465 mips_set_option_string (&mips_arch_string
, "4650");
10466 mips_set_option_string (&mips_tune_string
, "4650");
10469 case OPTION_NO_M4650
:
10473 mips_set_option_string (&mips_arch_string
, "4010");
10474 mips_set_option_string (&mips_tune_string
, "4010");
10477 case OPTION_NO_M4010
:
10481 mips_set_option_string (&mips_arch_string
, "4100");
10482 mips_set_option_string (&mips_tune_string
, "4100");
10485 case OPTION_NO_M4100
:
10489 mips_set_option_string (&mips_arch_string
, "3900");
10490 mips_set_option_string (&mips_tune_string
, "3900");
10493 case OPTION_NO_M3900
:
10497 mips_opts
.ase_mdmx
= 1;
10500 case OPTION_NO_MDMX
:
10501 mips_opts
.ase_mdmx
= 0;
10504 case OPTION_MIPS16
:
10505 mips_opts
.mips16
= 1;
10506 mips_no_prev_insn (FALSE
);
10509 case OPTION_NO_MIPS16
:
10510 mips_opts
.mips16
= 0;
10511 mips_no_prev_insn (FALSE
);
10514 case OPTION_MIPS3D
:
10515 mips_opts
.ase_mips3d
= 1;
10518 case OPTION_NO_MIPS3D
:
10519 mips_opts
.ase_mips3d
= 0;
10522 case OPTION_MEMBEDDED_PIC
:
10523 mips_pic
= EMBEDDED_PIC
;
10524 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10526 as_bad (_("-G may not be used with embedded PIC code"));
10529 g_switch_value
= 0x7fffffff;
10532 case OPTION_FIX_VR4122
:
10533 mips_fix_4122_bugs
= 1;
10536 case OPTION_NO_FIX_VR4122
:
10537 mips_fix_4122_bugs
= 0;
10540 case OPTION_RELAX_BRANCH
:
10541 mips_relax_branch
= 1;
10544 case OPTION_NO_RELAX_BRANCH
:
10545 mips_relax_branch
= 0;
10549 /* When generating ELF code, we permit -KPIC and -call_shared to
10550 select SVR4_PIC, and -non_shared to select no PIC. This is
10551 intended to be compatible with Irix 5. */
10552 case OPTION_CALL_SHARED
:
10553 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10555 as_bad (_("-call_shared is supported only for ELF format"));
10558 mips_pic
= SVR4_PIC
;
10559 if (g_switch_seen
&& g_switch_value
!= 0)
10561 as_bad (_("-G may not be used with SVR4 PIC code"));
10564 g_switch_value
= 0;
10567 case OPTION_NON_SHARED
:
10568 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10570 as_bad (_("-non_shared is supported only for ELF format"));
10576 /* The -xgot option tells the assembler to use 32 offsets when
10577 accessing the got in SVR4_PIC mode. It is for Irix
10582 #endif /* OBJ_ELF */
10585 if (! USE_GLOBAL_POINTER_OPT
)
10587 as_bad (_("-G is not supported for this configuration"));
10590 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10592 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10596 g_switch_value
= atoi (arg
);
10601 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10604 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10606 as_bad (_("-32 is supported for ELF format only"));
10609 mips_abi
= O32_ABI
;
10613 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10615 as_bad (_("-n32 is supported for ELF format only"));
10618 mips_abi
= N32_ABI
;
10622 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10624 as_bad (_("-64 is supported for ELF format only"));
10627 mips_abi
= N64_ABI
;
10628 if (! support_64bit_objects())
10629 as_fatal (_("No compiled in support for 64 bit object file format"));
10631 #endif /* OBJ_ELF */
10634 file_mips_gp32
= 1;
10638 file_mips_gp32
= 0;
10642 file_mips_fp32
= 1;
10646 file_mips_fp32
= 0;
10651 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10653 as_bad (_("-mabi is supported for ELF format only"));
10656 if (strcmp (arg
, "32") == 0)
10657 mips_abi
= O32_ABI
;
10658 else if (strcmp (arg
, "o64") == 0)
10659 mips_abi
= O64_ABI
;
10660 else if (strcmp (arg
, "n32") == 0)
10661 mips_abi
= N32_ABI
;
10662 else if (strcmp (arg
, "64") == 0)
10664 mips_abi
= N64_ABI
;
10665 if (! support_64bit_objects())
10666 as_fatal (_("No compiled in support for 64 bit object file "
10669 else if (strcmp (arg
, "eabi") == 0)
10670 mips_abi
= EABI_ABI
;
10673 as_fatal (_("invalid abi -mabi=%s"), arg
);
10677 #endif /* OBJ_ELF */
10679 case OPTION_M7000_HILO_FIX
:
10680 mips_7000_hilo_fix
= TRUE
;
10683 case OPTION_MNO_7000_HILO_FIX
:
10684 mips_7000_hilo_fix
= FALSE
;
10688 case OPTION_MDEBUG
:
10689 mips_flag_mdebug
= TRUE
;
10692 case OPTION_NO_MDEBUG
:
10693 mips_flag_mdebug
= FALSE
;
10695 #endif /* OBJ_ELF */
10704 /* Set up globals to generate code for the ISA or processor
10705 described by INFO. */
10708 mips_set_architecture (info
)
10709 const struct mips_cpu_info
*info
;
10713 mips_arch_info
= info
;
10714 mips_arch
= info
->cpu
;
10715 mips_opts
.isa
= info
->isa
;
10720 /* Likewise for tuning. */
10723 mips_set_tune (info
)
10724 const struct mips_cpu_info
*info
;
10728 mips_tune_info
= info
;
10729 mips_tune
= info
->cpu
;
10735 mips_after_parse_args ()
10737 /* GP relative stuff not working for PE */
10738 if (strncmp (TARGET_OS
, "pe", 2) == 0
10739 && g_switch_value
!= 0)
10742 as_bad (_("-G not supported in this configuration."));
10743 g_switch_value
= 0;
10746 /* The following code determines the architecture and register size.
10747 Similar code was added to GCC 3.3 (see override_options() in
10748 config/mips/mips.c). The GAS and GCC code should be kept in sync
10749 as much as possible. */
10751 if (mips_arch_string
!= 0)
10752 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
10754 if (mips_tune_string
!= 0)
10755 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
10757 if (file_mips_isa
!= ISA_UNKNOWN
)
10759 /* Handle -mipsN. At this point, file_mips_isa contains the
10760 ISA level specified by -mipsN, while mips_opts.isa contains
10761 the -march selection (if any). */
10762 if (mips_arch_info
!= 0)
10764 /* -march takes precedence over -mipsN, since it is more descriptive.
10765 There's no harm in specifying both as long as the ISA levels
10767 if (file_mips_isa
!= mips_opts
.isa
)
10768 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10769 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10770 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10773 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
10776 if (mips_arch_info
== 0)
10777 mips_set_architecture (mips_parse_cpu ("default CPU",
10778 MIPS_CPU_STRING_DEFAULT
));
10780 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10781 as_bad ("-march=%s is not compatible with the selected ABI",
10782 mips_arch_info
->name
);
10784 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10785 if (mips_tune_info
== 0)
10786 mips_set_tune (mips_arch_info
);
10788 if (file_mips_gp32
>= 0)
10790 /* The user specified the size of the integer registers. Make sure
10791 it agrees with the ABI and ISA. */
10792 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10793 as_bad (_("-mgp64 used with a 32-bit processor"));
10794 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10795 as_bad (_("-mgp32 used with a 64-bit ABI"));
10796 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10797 as_bad (_("-mgp64 used with a 32-bit ABI"));
10801 /* Infer the integer register size from the ABI and processor.
10802 Restrict ourselves to 32-bit registers if that's all the
10803 processor has, or if the ABI cannot handle 64-bit registers. */
10804 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10805 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10808 /* ??? GAS treats single-float processors as though they had 64-bit
10809 float registers (although it complains when double-precision
10810 instructions are used). As things stand, saying they have 32-bit
10811 registers would lead to spurious "register must be even" messages.
10812 So here we assume float registers are always the same size as
10813 integer ones, unless the user says otherwise. */
10814 if (file_mips_fp32
< 0)
10815 file_mips_fp32
= file_mips_gp32
;
10817 /* End of GCC-shared inference code. */
10819 /* ??? When do we want this flag to be set? Who uses it? */
10820 if (file_mips_gp32
== 1
10821 && mips_abi
== NO_ABI
10822 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10823 mips_32bitmode
= 1;
10825 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10826 as_bad (_("trap exception not supported at ISA 1"));
10828 /* If the selected architecture includes support for ASEs, enable
10829 generation of code for them. */
10830 if (mips_opts
.mips16
== -1)
10831 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
10832 if (mips_opts
.ase_mips3d
== -1)
10833 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
10834 if (mips_opts
.ase_mdmx
== -1)
10835 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
10837 file_mips_isa
= mips_opts
.isa
;
10838 file_ase_mips16
= mips_opts
.mips16
;
10839 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10840 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10841 mips_opts
.gp32
= file_mips_gp32
;
10842 mips_opts
.fp32
= file_mips_fp32
;
10844 if (mips_flag_mdebug
< 0)
10846 #ifdef OBJ_MAYBE_ECOFF
10847 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10848 mips_flag_mdebug
= 1;
10850 #endif /* OBJ_MAYBE_ECOFF */
10851 mips_flag_mdebug
= 0;
10856 mips_init_after_args ()
10858 /* initialize opcodes */
10859 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10860 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10864 md_pcrel_from (fixP
)
10867 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10868 && fixP
->fx_addsy
!= (symbolS
*) NULL
10869 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10871 /* This makes a branch to an undefined symbol be a branch to the
10872 current location. */
10873 if (mips_pic
== EMBEDDED_PIC
)
10879 /* Return the address of the delay slot. */
10880 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10883 /* This is called before the symbol table is processed. In order to
10884 work with gcc when using mips-tfile, we must keep all local labels.
10885 However, in other cases, we want to discard them. If we were
10886 called with -g, but we didn't see any debugging information, it may
10887 mean that gcc is smuggling debugging information through to
10888 mips-tfile, in which case we must generate all local labels. */
10891 mips_frob_file_before_adjust ()
10893 #ifndef NO_ECOFF_DEBUGGING
10894 if (ECOFF_DEBUGGING
10896 && ! ecoff_debugging_seen
)
10897 flag_keep_locals
= 1;
10901 /* Sort any unmatched HI16_S relocs so that they immediately precede
10902 the corresponding LO reloc. This is called before md_apply_fix3 and
10903 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10904 explicit use of the %hi modifier. */
10909 struct mips_hi_fixup
*l
;
10911 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10913 segment_info_type
*seginfo
;
10916 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10918 /* Check quickly whether the next fixup happens to be a matching
10920 if (l
->fixp
->fx_next
!= NULL
10921 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10922 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10923 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10926 /* Look through the fixups for this segment for a matching %lo.
10927 When we find one, move the %hi just in front of it. We do
10928 this in two passes. In the first pass, we try to find a
10929 unique %lo. In the second pass, we permit multiple %hi
10930 relocs for a single %lo (this is a GNU extension). */
10931 seginfo
= seg_info (l
->seg
);
10932 for (pass
= 0; pass
< 2; pass
++)
10937 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10939 /* Check whether this is a %lo fixup which matches l->fixp. */
10940 if (f
->fx_r_type
== BFD_RELOC_LO16
10941 && f
->fx_addsy
== l
->fixp
->fx_addsy
10942 && f
->fx_offset
== l
->fixp
->fx_offset
10945 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10946 || prev
->fx_addsy
!= f
->fx_addsy
10947 || prev
->fx_offset
!= f
->fx_offset
))
10951 /* Move l->fixp before f. */
10952 for (pf
= &seginfo
->fix_root
;
10954 pf
= &(*pf
)->fx_next
)
10955 assert (*pf
!= NULL
);
10957 *pf
= l
->fixp
->fx_next
;
10959 l
->fixp
->fx_next
= f
;
10961 seginfo
->fix_root
= l
->fixp
;
10963 prev
->fx_next
= l
->fixp
;
10974 #if 0 /* GCC code motion plus incomplete dead code elimination
10975 can leave a %hi without a %lo. */
10977 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10978 _("Unmatched %%hi reloc"));
10984 /* When generating embedded PIC code we need to use a special
10985 relocation to represent the difference of two symbols in the .text
10986 section (switch tables use a difference of this sort). See
10987 include/coff/mips.h for details. This macro checks whether this
10988 fixup requires the special reloc. */
10989 #define SWITCH_TABLE(fixp) \
10990 ((fixp)->fx_r_type == BFD_RELOC_32 \
10991 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10992 && (fixp)->fx_addsy != NULL \
10993 && (fixp)->fx_subsy != NULL \
10994 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10995 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10997 /* When generating embedded PIC code we must keep all PC relative
10998 relocations, in case the linker has to relax a call. We also need
10999 to keep relocations for switch table entries.
11001 We may have combined relocations without symbols in the N32/N64 ABI.
11002 We have to prevent gas from dropping them. */
11005 mips_force_relocation (fixp
)
11008 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11009 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
11010 || S_FORCE_RELOC (fixp
->fx_addsy
))
11014 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11015 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11016 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11017 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11020 return (mips_pic
== EMBEDDED_PIC
11022 || SWITCH_TABLE (fixp
)
11023 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
11024 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
11029 mips_need_elf_addend_fixup (fixP
)
11032 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
11034 if (mips_pic
== EMBEDDED_PIC
11035 && S_IS_WEAK (fixP
->fx_addsy
))
11037 if (mips_pic
!= EMBEDDED_PIC
11038 && (S_IS_WEAK (fixP
->fx_addsy
)
11039 || S_IS_EXTERNAL (fixP
->fx_addsy
))
11040 && !S_IS_COMMON (fixP
->fx_addsy
))
11042 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
11043 && (((bfd_get_section_flags (stdoutput
,
11044 S_GET_SEGMENT (fixP
->fx_addsy
))
11045 & (SEC_LINK_ONCE
| SEC_MERGE
)) != 0)
11046 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
11048 sizeof (".gnu.linkonce") - 1)))
11054 /* Apply a fixup to the object file. */
11057 md_apply_fix3 (fixP
, valP
, seg
)
11060 segT seg ATTRIBUTE_UNUSED
;
11065 static int previous_fx_r_type
= 0;
11067 /* FIXME: Maybe just return for all reloc types not listed below?
11068 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
11069 if (fixP
->fx_r_type
== BFD_RELOC_8
)
11072 assert (fixP
->fx_size
== 4
11073 || fixP
->fx_r_type
== BFD_RELOC_16
11074 || fixP
->fx_r_type
== BFD_RELOC_32
11075 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
11076 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
11077 || fixP
->fx_r_type
== BFD_RELOC_LO16
11078 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
11079 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
11080 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
11081 || fixP
->fx_r_type
== BFD_RELOC_64
11082 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11083 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11084 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
11085 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
11086 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
11087 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
11088 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
11089 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11090 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
11091 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
11095 /* If we aren't adjusting this fixup to be against the section
11096 symbol, we need to adjust the value. */
11098 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11100 if (mips_need_elf_addend_fixup (fixP
))
11102 reloc_howto_type
*howto
;
11103 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
11107 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11108 if (value
!= 0 && howto
->partial_inplace
11109 && (! fixP
->fx_pcrel
|| howto
->pcrel_offset
))
11111 /* In this case, the bfd_install_relocation routine will
11112 incorrectly add the symbol value back in. We just want
11113 the addend to appear in the object file.
11115 howto->pcrel_offset is added for R_MIPS_PC16, which is
11116 generated for code like
11127 /* Make sure the addend is still non-zero. If it became zero
11128 after the last operation, set it to a spurious value and
11129 subtract the same value from the object file's contents. */
11134 /* The in-place addends for LO16 relocations are signed;
11135 leave the matching HI16 in-place addends as zero. */
11136 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
11138 bfd_vma contents
, mask
, field
;
11140 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
11143 target_big_endian
);
11145 /* MASK has bits set where the relocation should go.
11146 FIELD is -value, shifted into the appropriate place
11147 for this relocation. */
11148 mask
= 1 << (howto
->bitsize
- 1);
11149 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
11150 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
11152 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
11153 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11155 target_big_endian
);
11161 /* This code was generated using trial and error and so is
11162 fragile and not trustworthy. If you change it, you should
11163 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11164 they still pass. */
11165 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
11167 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11169 /* BFD's REL handling, for MIPS, is _very_ weird.
11170 This gives the right results, but it can't possibly
11171 be the way things are supposed to work. */
11172 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
11173 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
11174 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
11175 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11180 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
11182 /* We are not done if this is a composite relocation to set up gp. */
11183 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11184 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11185 || (fixP
->fx_r_type
== BFD_RELOC_64
11186 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11187 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11188 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11189 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11190 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11192 previous_fx_r_type
= fixP
->fx_r_type
;
11194 switch (fixP
->fx_r_type
)
11196 case BFD_RELOC_MIPS_JMP
:
11197 case BFD_RELOC_MIPS_SHIFT5
:
11198 case BFD_RELOC_MIPS_SHIFT6
:
11199 case BFD_RELOC_MIPS_GOT_DISP
:
11200 case BFD_RELOC_MIPS_GOT_PAGE
:
11201 case BFD_RELOC_MIPS_GOT_OFST
:
11202 case BFD_RELOC_MIPS_SUB
:
11203 case BFD_RELOC_MIPS_INSERT_A
:
11204 case BFD_RELOC_MIPS_INSERT_B
:
11205 case BFD_RELOC_MIPS_DELETE
:
11206 case BFD_RELOC_MIPS_HIGHEST
:
11207 case BFD_RELOC_MIPS_HIGHER
:
11208 case BFD_RELOC_MIPS_SCN_DISP
:
11209 case BFD_RELOC_MIPS_REL16
:
11210 case BFD_RELOC_MIPS_RELGOT
:
11211 case BFD_RELOC_MIPS_JALR
:
11212 case BFD_RELOC_HI16
:
11213 case BFD_RELOC_HI16_S
:
11214 case BFD_RELOC_GPREL16
:
11215 case BFD_RELOC_MIPS_LITERAL
:
11216 case BFD_RELOC_MIPS_CALL16
:
11217 case BFD_RELOC_MIPS_GOT16
:
11218 case BFD_RELOC_GPREL32
:
11219 case BFD_RELOC_MIPS_GOT_HI16
:
11220 case BFD_RELOC_MIPS_GOT_LO16
:
11221 case BFD_RELOC_MIPS_CALL_HI16
:
11222 case BFD_RELOC_MIPS_CALL_LO16
:
11223 case BFD_RELOC_MIPS16_GPREL
:
11224 if (fixP
->fx_pcrel
)
11225 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11226 _("Invalid PC relative reloc"));
11227 /* Nothing needed to do. The value comes from the reloc entry */
11230 case BFD_RELOC_MIPS16_JMP
:
11231 /* We currently always generate a reloc against a symbol, which
11232 means that we don't want an addend even if the symbol is
11234 fixP
->fx_addnumber
= 0;
11237 case BFD_RELOC_PCREL_HI16_S
:
11238 /* The addend for this is tricky if it is internal, so we just
11239 do everything here rather than in bfd_install_relocation. */
11240 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11245 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11247 /* For an external symbol adjust by the address to make it
11248 pcrel_offset. We use the address of the RELLO reloc
11249 which follows this one. */
11250 value
+= (fixP
->fx_next
->fx_frag
->fr_address
11251 + fixP
->fx_next
->fx_where
);
11253 value
= ((value
+ 0x8000) >> 16) & 0xffff;
11254 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11255 if (target_big_endian
)
11257 md_number_to_chars ((char *) buf
, value
, 2);
11260 case BFD_RELOC_PCREL_LO16
:
11261 /* The addend for this is tricky if it is internal, so we just
11262 do everything here rather than in bfd_install_relocation. */
11263 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11268 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11269 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11270 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11271 if (target_big_endian
)
11273 md_number_to_chars ((char *) buf
, value
, 2);
11277 /* This is handled like BFD_RELOC_32, but we output a sign
11278 extended value if we are only 32 bits. */
11280 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11282 if (8 <= sizeof (valueT
))
11283 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11290 w1
= w2
= fixP
->fx_where
;
11291 if (target_big_endian
)
11295 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
11296 if ((value
& 0x80000000) != 0)
11300 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
11305 case BFD_RELOC_RVA
:
11307 /* If we are deleting this reloc entry, we must fill in the
11308 value now. This can happen if we have a .word which is not
11309 resolved when it appears but is later defined. We also need
11310 to fill in the value if this is an embedded PIC switch table
11313 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11314 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11319 /* If we are deleting this reloc entry, we must fill in the
11321 assert (fixP
->fx_size
== 2);
11323 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11327 case BFD_RELOC_LO16
:
11328 /* When handling an embedded PIC switch statement, we can wind
11329 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11332 if (value
+ 0x8000 > 0xffff)
11333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11334 _("relocation overflow"));
11335 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11336 if (target_big_endian
)
11338 md_number_to_chars ((char *) buf
, value
, 2);
11342 case BFD_RELOC_16_PCREL_S2
:
11343 if ((value
& 0x3) != 0)
11344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11345 _("Branch to odd address (%lx)"), (long) value
);
11347 /* Fall through. */
11349 case BFD_RELOC_16_PCREL
:
11351 * We need to save the bits in the instruction since fixup_segment()
11352 * might be deleting the relocation entry (i.e., a branch within
11353 * the current segment).
11355 if (!fixP
->fx_done
&& value
!= 0)
11357 /* If 'value' is zero, the remaining reloc code won't actually
11358 do the store, so it must be done here. This is probably
11359 a bug somewhere. */
11361 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11362 || fixP
->fx_addsy
== NULL
/* ??? */
11363 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
11364 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11366 value
= (offsetT
) value
>> 2;
11368 /* update old instruction data */
11369 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
11370 if (target_big_endian
)
11371 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11373 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11375 if (value
+ 0x8000 <= 0xffff)
11376 insn
|= value
& 0xffff;
11379 /* The branch offset is too large. If this is an
11380 unconditional branch, and we are not generating PIC code,
11381 we can convert it to an absolute jump instruction. */
11382 if (mips_pic
== NO_PIC
11384 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11385 && (fixP
->fx_frag
->fr_address
11386 < text_section
->vma
+ text_section
->_raw_size
)
11387 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11388 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11389 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11391 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11392 insn
= 0x0c000000; /* jal */
11394 insn
= 0x08000000; /* j */
11395 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11397 fixP
->fx_addsy
= section_symbol (text_section
);
11398 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11402 /* If we got here, we have branch-relaxation disabled,
11403 and there's nothing we can do to fix this instruction
11404 without turning it into a longer sequence. */
11405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11406 _("Branch out of range"));
11410 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11413 case BFD_RELOC_VTABLE_INHERIT
:
11416 && !S_IS_DEFINED (fixP
->fx_addsy
)
11417 && !S_IS_WEAK (fixP
->fx_addsy
))
11418 S_SET_WEAK (fixP
->fx_addsy
);
11421 case BFD_RELOC_VTABLE_ENTRY
:
11435 const struct mips_opcode
*p
;
11436 int treg
, sreg
, dreg
, shamt
;
11441 for (i
= 0; i
< NUMOPCODES
; ++i
)
11443 p
= &mips_opcodes
[i
];
11444 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11446 printf ("%08lx %s\t", oc
, p
->name
);
11447 treg
= (oc
>> 16) & 0x1f;
11448 sreg
= (oc
>> 21) & 0x1f;
11449 dreg
= (oc
>> 11) & 0x1f;
11450 shamt
= (oc
>> 6) & 0x1f;
11452 for (args
= p
->args
;; ++args
)
11463 printf ("%c", *args
);
11467 assert (treg
== sreg
);
11468 printf ("$%d,$%d", treg
, sreg
);
11473 printf ("$%d", dreg
);
11478 printf ("$%d", treg
);
11482 printf ("0x%x", treg
);
11487 printf ("$%d", sreg
);
11491 printf ("0x%08lx", oc
& 0x1ffffff);
11498 printf ("%d", imm
);
11503 printf ("$%d", shamt
);
11514 printf (_("%08lx UNDEFINED\n"), oc
);
11525 name
= input_line_pointer
;
11526 c
= get_symbol_end ();
11527 p
= (symbolS
*) symbol_find_or_make (name
);
11528 *input_line_pointer
= c
;
11532 /* Align the current frag to a given power of two. The MIPS assembler
11533 also automatically adjusts any preceding label. */
11536 mips_align (to
, fill
, label
)
11541 mips_emit_delays (FALSE
);
11542 frag_align (to
, fill
, 0);
11543 record_alignment (now_seg
, to
);
11546 assert (S_GET_SEGMENT (label
) == now_seg
);
11547 symbol_set_frag (label
, frag_now
);
11548 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11552 /* Align to a given power of two. .align 0 turns off the automatic
11553 alignment used by the data creating pseudo-ops. */
11557 int x ATTRIBUTE_UNUSED
;
11560 register long temp_fill
;
11561 long max_alignment
= 15;
11565 o Note that the assembler pulls down any immediately preceeding label
11566 to the aligned address.
11567 o It's not documented but auto alignment is reinstated by
11568 a .align pseudo instruction.
11569 o Note also that after auto alignment is turned off the mips assembler
11570 issues an error on attempt to assemble an improperly aligned data item.
11575 temp
= get_absolute_expression ();
11576 if (temp
> max_alignment
)
11577 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11580 as_warn (_("Alignment negative: 0 assumed."));
11583 if (*input_line_pointer
== ',')
11585 ++input_line_pointer
;
11586 temp_fill
= get_absolute_expression ();
11593 mips_align (temp
, (int) temp_fill
,
11594 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11601 demand_empty_rest_of_line ();
11605 mips_flush_pending_output ()
11607 mips_emit_delays (FALSE
);
11608 mips_clear_insn_labels ();
11617 /* When generating embedded PIC code, we only use the .text, .lit8,
11618 .sdata and .sbss sections. We change the .data and .rdata
11619 pseudo-ops to use .sdata. */
11620 if (mips_pic
== EMBEDDED_PIC
11621 && (sec
== 'd' || sec
== 'r'))
11625 /* The ELF backend needs to know that we are changing sections, so
11626 that .previous works correctly. We could do something like check
11627 for an obj_section_change_hook macro, but that might be confusing
11628 as it would not be appropriate to use it in the section changing
11629 functions in read.c, since obj-elf.c intercepts those. FIXME:
11630 This should be cleaner, somehow. */
11631 obj_elf_section_change_hook ();
11634 mips_emit_delays (FALSE
);
11644 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11645 demand_empty_rest_of_line ();
11649 if (USE_GLOBAL_POINTER_OPT
)
11651 seg
= subseg_new (RDATA_SECTION_NAME
,
11652 (subsegT
) get_absolute_expression ());
11653 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11655 bfd_set_section_flags (stdoutput
, seg
,
11661 if (strcmp (TARGET_OS
, "elf") != 0)
11662 record_alignment (seg
, 4);
11664 demand_empty_rest_of_line ();
11668 as_bad (_("No read only data section in this object file format"));
11669 demand_empty_rest_of_line ();
11675 if (USE_GLOBAL_POINTER_OPT
)
11677 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11678 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11680 bfd_set_section_flags (stdoutput
, seg
,
11681 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11683 if (strcmp (TARGET_OS
, "elf") != 0)
11684 record_alignment (seg
, 4);
11686 demand_empty_rest_of_line ();
11691 as_bad (_("Global pointers not supported; recompile -G 0"));
11692 demand_empty_rest_of_line ();
11701 s_change_section (ignore
)
11702 int ignore ATTRIBUTE_UNUSED
;
11705 char *section_name
;
11710 int section_entry_size
;
11711 int section_alignment
;
11713 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11716 section_name
= input_line_pointer
;
11717 c
= get_symbol_end ();
11719 next_c
= *(input_line_pointer
+ 1);
11721 /* Do we have .section Name<,"flags">? */
11722 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11724 /* just after name is now '\0'. */
11725 *input_line_pointer
= c
;
11726 input_line_pointer
= section_name
;
11727 obj_elf_section (ignore
);
11730 input_line_pointer
++;
11732 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11734 section_type
= get_absolute_expression ();
11737 if (*input_line_pointer
++ == ',')
11738 section_flag
= get_absolute_expression ();
11741 if (*input_line_pointer
++ == ',')
11742 section_entry_size
= get_absolute_expression ();
11744 section_entry_size
= 0;
11745 if (*input_line_pointer
++ == ',')
11746 section_alignment
= get_absolute_expression ();
11748 section_alignment
= 0;
11750 section_name
= xstrdup (section_name
);
11752 obj_elf_change_section (section_name
, section_type
, section_flag
,
11753 section_entry_size
, 0, 0, 0);
11755 if (now_seg
->name
!= section_name
)
11756 free (section_name
);
11757 #endif /* OBJ_ELF */
11761 mips_enable_auto_align ()
11772 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11773 mips_emit_delays (FALSE
);
11774 if (log_size
> 0 && auto_align
)
11775 mips_align (log_size
, 0, label
);
11776 mips_clear_insn_labels ();
11777 cons (1 << log_size
);
11781 s_float_cons (type
)
11786 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11788 mips_emit_delays (FALSE
);
11793 mips_align (3, 0, label
);
11795 mips_align (2, 0, label
);
11798 mips_clear_insn_labels ();
11803 /* Handle .globl. We need to override it because on Irix 5 you are
11806 where foo is an undefined symbol, to mean that foo should be
11807 considered to be the address of a function. */
11811 int x ATTRIBUTE_UNUSED
;
11818 name
= input_line_pointer
;
11819 c
= get_symbol_end ();
11820 symbolP
= symbol_find_or_make (name
);
11821 *input_line_pointer
= c
;
11822 SKIP_WHITESPACE ();
11824 /* On Irix 5, every global symbol that is not explicitly labelled as
11825 being a function is apparently labelled as being an object. */
11828 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11833 secname
= input_line_pointer
;
11834 c
= get_symbol_end ();
11835 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11837 as_bad (_("%s: no such section"), secname
);
11838 *input_line_pointer
= c
;
11840 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11841 flag
= BSF_FUNCTION
;
11844 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11846 S_SET_EXTERNAL (symbolP
);
11847 demand_empty_rest_of_line ();
11852 int x ATTRIBUTE_UNUSED
;
11857 opt
= input_line_pointer
;
11858 c
= get_symbol_end ();
11862 /* FIXME: What does this mean? */
11864 else if (strncmp (opt
, "pic", 3) == 0)
11868 i
= atoi (opt
+ 3);
11872 mips_pic
= SVR4_PIC
;
11874 as_bad (_(".option pic%d not supported"), i
);
11876 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11878 if (g_switch_seen
&& g_switch_value
!= 0)
11879 as_warn (_("-G may not be used with SVR4 PIC code"));
11880 g_switch_value
= 0;
11881 bfd_set_gp_size (stdoutput
, 0);
11885 as_warn (_("Unrecognized option \"%s\""), opt
);
11887 *input_line_pointer
= c
;
11888 demand_empty_rest_of_line ();
11891 /* This structure is used to hold a stack of .set values. */
11893 struct mips_option_stack
11895 struct mips_option_stack
*next
;
11896 struct mips_set_options options
;
11899 static struct mips_option_stack
*mips_opts_stack
;
11901 /* Handle the .set pseudo-op. */
11905 int x ATTRIBUTE_UNUSED
;
11907 char *name
= input_line_pointer
, ch
;
11909 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11910 ++input_line_pointer
;
11911 ch
= *input_line_pointer
;
11912 *input_line_pointer
= '\0';
11914 if (strcmp (name
, "reorder") == 0)
11916 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11918 /* If we still have pending nops, we can discard them. The
11919 usual nop handling will insert any that are still
11921 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11922 * (mips_opts
.mips16
? 2 : 4));
11923 prev_nop_frag
= NULL
;
11925 mips_opts
.noreorder
= 0;
11927 else if (strcmp (name
, "noreorder") == 0)
11929 mips_emit_delays (TRUE
);
11930 mips_opts
.noreorder
= 1;
11931 mips_any_noreorder
= 1;
11933 else if (strcmp (name
, "at") == 0)
11935 mips_opts
.noat
= 0;
11937 else if (strcmp (name
, "noat") == 0)
11939 mips_opts
.noat
= 1;
11941 else if (strcmp (name
, "macro") == 0)
11943 mips_opts
.warn_about_macros
= 0;
11945 else if (strcmp (name
, "nomacro") == 0)
11947 if (mips_opts
.noreorder
== 0)
11948 as_bad (_("`noreorder' must be set before `nomacro'"));
11949 mips_opts
.warn_about_macros
= 1;
11951 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11953 mips_opts
.nomove
= 0;
11955 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11957 mips_opts
.nomove
= 1;
11959 else if (strcmp (name
, "bopt") == 0)
11961 mips_opts
.nobopt
= 0;
11963 else if (strcmp (name
, "nobopt") == 0)
11965 mips_opts
.nobopt
= 1;
11967 else if (strcmp (name
, "mips16") == 0
11968 || strcmp (name
, "MIPS-16") == 0)
11969 mips_opts
.mips16
= 1;
11970 else if (strcmp (name
, "nomips16") == 0
11971 || strcmp (name
, "noMIPS-16") == 0)
11972 mips_opts
.mips16
= 0;
11973 else if (strcmp (name
, "mips3d") == 0)
11974 mips_opts
.ase_mips3d
= 1;
11975 else if (strcmp (name
, "nomips3d") == 0)
11976 mips_opts
.ase_mips3d
= 0;
11977 else if (strcmp (name
, "mdmx") == 0)
11978 mips_opts
.ase_mdmx
= 1;
11979 else if (strcmp (name
, "nomdmx") == 0)
11980 mips_opts
.ase_mdmx
= 0;
11981 else if (strncmp (name
, "mips", 4) == 0)
11985 /* Permit the user to change the ISA on the fly. Needless to
11986 say, misuse can cause serious problems. */
11987 isa
= atoi (name
+ 4);
11991 mips_opts
.gp32
= file_mips_gp32
;
11992 mips_opts
.fp32
= file_mips_fp32
;
11997 mips_opts
.gp32
= 1;
11998 mips_opts
.fp32
= 1;
12004 mips_opts
.gp32
= 0;
12005 mips_opts
.fp32
= 0;
12008 as_bad (_("unknown ISA level %s"), name
+ 4);
12014 case 0: mips_opts
.isa
= file_mips_isa
; break;
12015 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
12016 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
12017 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
12018 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
12019 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
12020 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
12021 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
12022 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
12025 else if (strcmp (name
, "autoextend") == 0)
12026 mips_opts
.noautoextend
= 0;
12027 else if (strcmp (name
, "noautoextend") == 0)
12028 mips_opts
.noautoextend
= 1;
12029 else if (strcmp (name
, "push") == 0)
12031 struct mips_option_stack
*s
;
12033 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12034 s
->next
= mips_opts_stack
;
12035 s
->options
= mips_opts
;
12036 mips_opts_stack
= s
;
12038 else if (strcmp (name
, "pop") == 0)
12040 struct mips_option_stack
*s
;
12042 s
= mips_opts_stack
;
12044 as_bad (_(".set pop with no .set push"));
12047 /* If we're changing the reorder mode we need to handle
12048 delay slots correctly. */
12049 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12050 mips_emit_delays (TRUE
);
12051 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12053 if (prev_nop_frag
!= NULL
)
12055 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12056 * (mips_opts
.mips16
? 2 : 4));
12057 prev_nop_frag
= NULL
;
12061 mips_opts
= s
->options
;
12062 mips_opts_stack
= s
->next
;
12068 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12070 *input_line_pointer
= ch
;
12071 demand_empty_rest_of_line ();
12074 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12075 .option pic2. It means to generate SVR4 PIC calls. */
12078 s_abicalls (ignore
)
12079 int ignore ATTRIBUTE_UNUSED
;
12081 mips_pic
= SVR4_PIC
;
12082 if (USE_GLOBAL_POINTER_OPT
)
12084 if (g_switch_seen
&& g_switch_value
!= 0)
12085 as_warn (_("-G may not be used with SVR4 PIC code"));
12086 g_switch_value
= 0;
12088 bfd_set_gp_size (stdoutput
, 0);
12089 demand_empty_rest_of_line ();
12092 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12093 PIC code. It sets the $gp register for the function based on the
12094 function address, which is in the register named in the argument.
12095 This uses a relocation against _gp_disp, which is handled specially
12096 by the linker. The result is:
12097 lui $gp,%hi(_gp_disp)
12098 addiu $gp,$gp,%lo(_gp_disp)
12099 addu $gp,$gp,.cpload argument
12100 The .cpload argument is normally $25 == $t9. */
12104 int ignore ATTRIBUTE_UNUSED
;
12109 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12110 .cpload is ignored. */
12111 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12117 /* .cpload should be in a .set noreorder section. */
12118 if (mips_opts
.noreorder
== 0)
12119 as_warn (_(".cpload not in noreorder section"));
12121 ex
.X_op
= O_symbol
;
12122 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12123 ex
.X_op_symbol
= NULL
;
12124 ex
.X_add_number
= 0;
12126 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12127 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12129 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
12130 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
12131 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
12133 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
12134 mips_gp_register
, mips_gp_register
, tc_get_register (0));
12136 demand_empty_rest_of_line ();
12139 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12140 .cpsetup $reg1, offset|$reg2, label
12142 If offset is given, this results in:
12143 sd $gp, offset($sp)
12144 lui $gp, %hi(%neg(%gp_rel(label)))
12145 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12146 daddu $gp, $gp, $reg1
12148 If $reg2 is given, this results in:
12149 daddu $reg2, $gp, $0
12150 lui $gp, %hi(%neg(%gp_rel(label)))
12151 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12152 daddu $gp, $gp, $reg1
12153 $reg1 is normally $25 == $t9. */
12156 int ignore ATTRIBUTE_UNUSED
;
12158 expressionS ex_off
;
12159 expressionS ex_sym
;
12164 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12165 We also need NewABI support. */
12166 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12172 reg1
= tc_get_register (0);
12173 SKIP_WHITESPACE ();
12174 if (*input_line_pointer
!= ',')
12176 as_bad (_("missing argument separator ',' for .cpsetup"));
12180 ++input_line_pointer
;
12181 SKIP_WHITESPACE ();
12182 if (*input_line_pointer
== '$')
12184 mips_cpreturn_register
= tc_get_register (0);
12185 mips_cpreturn_offset
= -1;
12189 mips_cpreturn_offset
= get_absolute_expression ();
12190 mips_cpreturn_register
= -1;
12192 SKIP_WHITESPACE ();
12193 if (*input_line_pointer
!= ',')
12195 as_bad (_("missing argument separator ',' for .cpsetup"));
12199 ++input_line_pointer
;
12200 SKIP_WHITESPACE ();
12201 expression (&ex_sym
);
12203 if (mips_cpreturn_register
== -1)
12205 ex_off
.X_op
= O_constant
;
12206 ex_off
.X_add_symbol
= NULL
;
12207 ex_off
.X_op_symbol
= NULL
;
12208 ex_off
.X_add_number
= mips_cpreturn_offset
;
12210 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
12211 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12214 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12215 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
12217 /* Ensure there's room for the next two instructions, so that `f'
12218 doesn't end up with an address in the wrong frag. */
12221 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12222 (int) BFD_RELOC_GPREL16
);
12223 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12224 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12225 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12226 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12229 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
12230 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
12231 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12232 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12233 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12234 0, NULL
, 0, 0, BFD_RELOC_LO16
);
12236 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12237 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
12238 mips_gp_register
, mips_gp_register
, reg1
);
12240 demand_empty_rest_of_line ();
12245 int ignore ATTRIBUTE_UNUSED
;
12247 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12248 .cplocal is ignored. */
12249 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12255 mips_gp_register
= tc_get_register (0);
12256 demand_empty_rest_of_line ();
12259 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12260 offset from $sp. The offset is remembered, and after making a PIC
12261 call $gp is restored from that location. */
12264 s_cprestore (ignore
)
12265 int ignore ATTRIBUTE_UNUSED
;
12270 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12271 .cprestore is ignored. */
12272 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12278 mips_cprestore_offset
= get_absolute_expression ();
12279 mips_cprestore_valid
= 1;
12281 ex
.X_op
= O_constant
;
12282 ex
.X_add_symbol
= NULL
;
12283 ex
.X_op_symbol
= NULL
;
12284 ex
.X_add_number
= mips_cprestore_offset
;
12286 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
12287 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
12288 mips_gp_register
, SP
);
12290 demand_empty_rest_of_line ();
12293 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12294 was given in the preceeding .gpsetup, it results in:
12295 ld $gp, offset($sp)
12297 If a register $reg2 was given there, it results in:
12298 daddiu $gp, $gp, $reg2
12301 s_cpreturn (ignore
)
12302 int ignore ATTRIBUTE_UNUSED
;
12307 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12308 We also need NewABI support. */
12309 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12315 if (mips_cpreturn_register
== -1)
12317 ex
.X_op
= O_constant
;
12318 ex
.X_add_symbol
= NULL
;
12319 ex
.X_op_symbol
= NULL
;
12320 ex
.X_add_number
= mips_cpreturn_offset
;
12322 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
12323 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12326 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12327 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
12329 demand_empty_rest_of_line ();
12332 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12333 code. It sets the offset to use in gp_rel relocations. */
12337 int ignore ATTRIBUTE_UNUSED
;
12339 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12340 We also need NewABI support. */
12341 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12347 mips_gprel_offset
= get_absolute_expression ();
12349 demand_empty_rest_of_line ();
12352 /* Handle the .gpword pseudo-op. This is used when generating PIC
12353 code. It generates a 32 bit GP relative reloc. */
12357 int ignore ATTRIBUTE_UNUSED
;
12363 /* When not generating PIC code, this is treated as .word. */
12364 if (mips_pic
!= SVR4_PIC
)
12370 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12371 mips_emit_delays (TRUE
);
12373 mips_align (2, 0, label
);
12374 mips_clear_insn_labels ();
12378 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12380 as_bad (_("Unsupported use of .gpword"));
12381 ignore_rest_of_line ();
12385 md_number_to_chars (p
, (valueT
) 0, 4);
12386 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12387 BFD_RELOC_GPREL32
);
12389 demand_empty_rest_of_line ();
12394 int ignore ATTRIBUTE_UNUSED
;
12400 /* When not generating PIC code, this is treated as .dword. */
12401 if (mips_pic
!= SVR4_PIC
)
12407 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12408 mips_emit_delays (TRUE
);
12410 mips_align (3, 0, label
);
12411 mips_clear_insn_labels ();
12415 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12417 as_bad (_("Unsupported use of .gpdword"));
12418 ignore_rest_of_line ();
12422 md_number_to_chars (p
, (valueT
) 0, 8);
12423 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12424 BFD_RELOC_GPREL32
);
12426 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12427 ex
.X_op
= O_absent
;
12428 ex
.X_add_symbol
= 0;
12429 ex
.X_add_number
= 0;
12430 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12433 demand_empty_rest_of_line ();
12436 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12437 tables in SVR4 PIC code. */
12441 int ignore ATTRIBUTE_UNUSED
;
12446 /* This is ignored when not generating SVR4 PIC code. */
12447 if (mips_pic
!= SVR4_PIC
)
12453 /* Add $gp to the register named as an argument. */
12454 reg
= tc_get_register (0);
12455 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12456 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
12457 "d,v,t", reg
, reg
, mips_gp_register
);
12459 demand_empty_rest_of_line ();
12462 /* Handle the .insn pseudo-op. This marks instruction labels in
12463 mips16 mode. This permits the linker to handle them specially,
12464 such as generating jalx instructions when needed. We also make
12465 them odd for the duration of the assembly, in order to generate the
12466 right sort of code. We will make them even in the adjust_symtab
12467 routine, while leaving them marked. This is convenient for the
12468 debugger and the disassembler. The linker knows to make them odd
12473 int ignore ATTRIBUTE_UNUSED
;
12475 mips16_mark_labels ();
12477 demand_empty_rest_of_line ();
12480 /* Handle a .stabn directive. We need these in order to mark a label
12481 as being a mips16 text label correctly. Sometimes the compiler
12482 will emit a label, followed by a .stabn, and then switch sections.
12483 If the label and .stabn are in mips16 mode, then the label is
12484 really a mips16 text label. */
12491 mips16_mark_labels ();
12496 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12500 s_mips_weakext (ignore
)
12501 int ignore ATTRIBUTE_UNUSED
;
12508 name
= input_line_pointer
;
12509 c
= get_symbol_end ();
12510 symbolP
= symbol_find_or_make (name
);
12511 S_SET_WEAK (symbolP
);
12512 *input_line_pointer
= c
;
12514 SKIP_WHITESPACE ();
12516 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12518 if (S_IS_DEFINED (symbolP
))
12520 as_bad ("ignoring attempt to redefine symbol %s",
12521 S_GET_NAME (symbolP
));
12522 ignore_rest_of_line ();
12526 if (*input_line_pointer
== ',')
12528 ++input_line_pointer
;
12529 SKIP_WHITESPACE ();
12533 if (exp
.X_op
!= O_symbol
)
12535 as_bad ("bad .weakext directive");
12536 ignore_rest_of_line ();
12539 symbol_set_value_expression (symbolP
, &exp
);
12542 demand_empty_rest_of_line ();
12545 /* Parse a register string into a number. Called from the ECOFF code
12546 to parse .frame. The argument is non-zero if this is the frame
12547 register, so that we can record it in mips_frame_reg. */
12550 tc_get_register (frame
)
12555 SKIP_WHITESPACE ();
12556 if (*input_line_pointer
++ != '$')
12558 as_warn (_("expected `$'"));
12561 else if (ISDIGIT (*input_line_pointer
))
12563 reg
= get_absolute_expression ();
12564 if (reg
< 0 || reg
>= 32)
12566 as_warn (_("Bad register number"));
12572 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12575 input_line_pointer
+= 2;
12577 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12580 input_line_pointer
+= 2;
12582 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12585 input_line_pointer
+= 2;
12587 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12590 input_line_pointer
+= 2;
12592 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12595 input_line_pointer
+= 2;
12597 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12600 input_line_pointer
+= 3;
12602 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12605 input_line_pointer
+= 3;
12607 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12610 input_line_pointer
+= 4;
12614 as_warn (_("Unrecognized register name"));
12616 while (ISALNUM(*input_line_pointer
))
12617 input_line_pointer
++;
12622 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12623 mips_frame_reg_valid
= 1;
12624 mips_cprestore_valid
= 0;
12630 md_section_align (seg
, addr
)
12634 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12637 /* We don't need to align ELF sections to the full alignment.
12638 However, Irix 5 may prefer that we align them at least to a 16
12639 byte boundary. We don't bother to align the sections if we are
12640 targeted for an embedded system. */
12641 if (strcmp (TARGET_OS
, "elf") == 0)
12647 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12650 /* Utility routine, called from above as well. If called while the
12651 input file is still being read, it's only an approximation. (For
12652 example, a symbol may later become defined which appeared to be
12653 undefined earlier.) */
12656 nopic_need_relax (sym
, before_relaxing
)
12658 int before_relaxing
;
12663 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12665 const char *symname
;
12668 /* Find out whether this symbol can be referenced off the $gp
12669 register. It can be if it is smaller than the -G size or if
12670 it is in the .sdata or .sbss section. Certain symbols can
12671 not be referenced off the $gp, although it appears as though
12673 symname
= S_GET_NAME (sym
);
12674 if (symname
!= (const char *) NULL
12675 && (strcmp (symname
, "eprol") == 0
12676 || strcmp (symname
, "etext") == 0
12677 || strcmp (symname
, "_gp") == 0
12678 || strcmp (symname
, "edata") == 0
12679 || strcmp (symname
, "_fbss") == 0
12680 || strcmp (symname
, "_fdata") == 0
12681 || strcmp (symname
, "_ftext") == 0
12682 || strcmp (symname
, "end") == 0
12683 || strcmp (symname
, "_gp_disp") == 0))
12685 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12687 #ifndef NO_ECOFF_DEBUGGING
12688 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12689 && (symbol_get_obj (sym
)->ecoff_extern_size
12690 <= g_switch_value
))
12692 /* We must defer this decision until after the whole
12693 file has been read, since there might be a .extern
12694 after the first use of this symbol. */
12695 || (before_relaxing
12696 #ifndef NO_ECOFF_DEBUGGING
12697 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12699 && S_GET_VALUE (sym
) == 0)
12700 || (S_GET_VALUE (sym
) != 0
12701 && S_GET_VALUE (sym
) <= g_switch_value
)))
12705 const char *segname
;
12707 segname
= segment_name (S_GET_SEGMENT (sym
));
12708 assert (strcmp (segname
, ".lit8") != 0
12709 && strcmp (segname
, ".lit4") != 0);
12710 change
= (strcmp (segname
, ".sdata") != 0
12711 && strcmp (segname
, ".sbss") != 0
12712 && strncmp (segname
, ".sdata.", 7) != 0
12713 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12718 /* We are not optimizing for the $gp register. */
12722 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12723 extended opcode. SEC is the section the frag is in. */
12726 mips16_extended_frag (fragp
, sec
, stretch
)
12732 register const struct mips16_immed_operand
*op
;
12734 int mintiny
, maxtiny
;
12738 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12740 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12743 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12744 op
= mips16_immed_operands
;
12745 while (op
->type
!= type
)
12748 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12753 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12756 maxtiny
= 1 << op
->nbits
;
12761 maxtiny
= (1 << op
->nbits
) - 1;
12766 mintiny
= - (1 << (op
->nbits
- 1));
12767 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12770 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12771 val
= S_GET_VALUE (fragp
->fr_symbol
);
12772 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12778 /* We won't have the section when we are called from
12779 mips_relax_frag. However, we will always have been called
12780 from md_estimate_size_before_relax first. If this is a
12781 branch to a different section, we mark it as such. If SEC is
12782 NULL, and the frag is not marked, then it must be a branch to
12783 the same section. */
12786 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12791 /* Must have been called from md_estimate_size_before_relax. */
12794 fragp
->fr_subtype
=
12795 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12797 /* FIXME: We should support this, and let the linker
12798 catch branches and loads that are out of range. */
12799 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12800 _("unsupported PC relative reference to different section"));
12804 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12805 /* Assume non-extended on the first relaxation pass.
12806 The address we have calculated will be bogus if this is
12807 a forward branch to another frag, as the forward frag
12808 will have fr_address == 0. */
12812 /* In this case, we know for sure that the symbol fragment is in
12813 the same section. If the relax_marker of the symbol fragment
12814 differs from the relax_marker of this fragment, we have not
12815 yet adjusted the symbol fragment fr_address. We want to add
12816 in STRETCH in order to get a better estimate of the address.
12817 This particularly matters because of the shift bits. */
12819 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12823 /* Adjust stretch for any alignment frag. Note that if have
12824 been expanding the earlier code, the symbol may be
12825 defined in what appears to be an earlier frag. FIXME:
12826 This doesn't handle the fr_subtype field, which specifies
12827 a maximum number of bytes to skip when doing an
12829 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12831 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12834 stretch
= - ((- stretch
)
12835 & ~ ((1 << (int) f
->fr_offset
) - 1));
12837 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12846 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12848 /* The base address rules are complicated. The base address of
12849 a branch is the following instruction. The base address of a
12850 PC relative load or add is the instruction itself, but if it
12851 is in a delay slot (in which case it can not be extended) use
12852 the address of the instruction whose delay slot it is in. */
12853 if (type
== 'p' || type
== 'q')
12857 /* If we are currently assuming that this frag should be
12858 extended, then, the current address is two bytes
12860 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12863 /* Ignore the low bit in the target, since it will be set
12864 for a text label. */
12865 if ((val
& 1) != 0)
12868 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12870 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12873 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12875 /* Branch offsets have an implicit 0 in the lowest bit. */
12876 if (type
== 'p' || type
== 'q')
12879 /* If any of the shifted bits are set, we must use an extended
12880 opcode. If the address depends on the size of this
12881 instruction, this can lead to a loop, so we arrange to always
12882 use an extended opcode. We only check this when we are in
12883 the main relaxation loop, when SEC is NULL. */
12884 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12886 fragp
->fr_subtype
=
12887 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12891 /* If we are about to mark a frag as extended because the value
12892 is precisely maxtiny + 1, then there is a chance of an
12893 infinite loop as in the following code:
12898 In this case when the la is extended, foo is 0x3fc bytes
12899 away, so the la can be shrunk, but then foo is 0x400 away, so
12900 the la must be extended. To avoid this loop, we mark the
12901 frag as extended if it was small, and is about to become
12902 extended with a value of maxtiny + 1. */
12903 if (val
== ((maxtiny
+ 1) << op
->shift
)
12904 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12907 fragp
->fr_subtype
=
12908 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12912 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12913 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12915 if ((val
& ((1 << op
->shift
) - 1)) != 0
12916 || val
< (mintiny
<< op
->shift
)
12917 || val
> (maxtiny
<< op
->shift
))
12923 /* Compute the length of a branch sequence, and adjust the
12924 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12925 worst-case length is computed, with UPDATE being used to indicate
12926 whether an unconditional (-1), branch-likely (+1) or regular (0)
12927 branch is to be computed. */
12929 relaxed_branch_length (fragp
, sec
, update
)
12934 bfd_boolean toofar
;
12938 && S_IS_DEFINED (fragp
->fr_symbol
)
12939 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12944 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12946 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12950 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12953 /* If the symbol is not defined or it's in a different segment,
12954 assume the user knows what's going on and emit a short
12960 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12962 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_RELOC_S2 (fragp
->fr_subtype
),
12963 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12964 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12965 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12971 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12974 if (mips_pic
!= NO_PIC
)
12976 /* Additional space for PIC loading of target address. */
12978 if (mips_opts
.isa
== ISA_MIPS1
)
12979 /* Additional space for $at-stabilizing nop. */
12983 /* If branch is conditional. */
12984 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12991 /* Estimate the size of a frag before relaxing. Unless this is the
12992 mips16, we are not really relaxing here, and the final size is
12993 encoded in the subtype information. For the mips16, we have to
12994 decide whether we are using an extended opcode or not. */
12997 md_estimate_size_before_relax (fragp
, segtype
)
13002 bfd_boolean linkonce
= FALSE
;
13004 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13007 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13009 return fragp
->fr_var
;
13012 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13013 /* We don't want to modify the EXTENDED bit here; it might get us
13014 into infinite loops. We change it only in mips_relax_frag(). */
13015 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13017 if (mips_pic
== NO_PIC
)
13019 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13021 else if (mips_pic
== SVR4_PIC
)
13026 sym
= fragp
->fr_symbol
;
13028 /* Handle the case of a symbol equated to another symbol. */
13029 while (symbol_equated_reloc_p (sym
))
13033 /* It's possible to get a loop here in a badly written
13035 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13041 symsec
= S_GET_SEGMENT (sym
);
13043 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13044 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
13046 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
13050 /* The GNU toolchain uses an extension for ELF: a section
13051 beginning with the magic string .gnu.linkonce is a linkonce
13053 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
13054 sizeof ".gnu.linkonce" - 1) == 0)
13058 /* This must duplicate the test in adjust_reloc_syms. */
13059 change
= (symsec
!= &bfd_und_section
13060 && symsec
!= &bfd_abs_section
13061 && ! bfd_is_com_section (symsec
)
13064 /* A global or weak symbol is treated as external. */
13065 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13066 || (! S_IS_WEAK (sym
)
13067 && (! S_IS_EXTERNAL (sym
)
13068 || mips_pic
== EMBEDDED_PIC
)))
13077 /* Record the offset to the first reloc in the fr_opcode field.
13078 This lets md_convert_frag and tc_gen_reloc know that the code
13079 must be expanded. */
13080 fragp
->fr_opcode
= (fragp
->fr_literal
13082 - RELAX_OLD (fragp
->fr_subtype
)
13083 + RELAX_RELOC1 (fragp
->fr_subtype
));
13084 /* FIXME: This really needs as_warn_where. */
13085 if (RELAX_WARN (fragp
->fr_subtype
))
13086 as_warn (_("AT used after \".set noat\" or macro used after "
13087 "\".set nomacro\""));
13089 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
13095 /* This is called to see whether a reloc against a defined symbol
13096 should be converted into a reloc against a section. Don't adjust
13097 MIPS16 jump relocations, so we don't have to worry about the format
13098 of the offset in the .o file. Don't adjust relocations against
13099 mips16 symbols, so that the linker can find them if it needs to set
13103 mips_fix_adjustable (fixp
)
13106 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13109 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13110 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13113 if (fixp
->fx_addsy
== NULL
)
13117 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13118 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13119 && fixp
->fx_subsy
== NULL
)
13126 /* Translate internal representation of relocation info to BFD target
13130 tc_gen_reloc (section
, fixp
)
13131 asection
*section ATTRIBUTE_UNUSED
;
13134 static arelent
*retval
[4];
13136 bfd_reloc_code_real_type code
;
13138 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
13141 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13142 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13143 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13145 if (mips_pic
== EMBEDDED_PIC
13146 && SWITCH_TABLE (fixp
))
13148 /* For a switch table entry we use a special reloc. The addend
13149 is actually the difference between the reloc address and the
13151 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13152 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13153 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13154 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13156 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
13158 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13159 reloc
->addend
= fixp
->fx_addnumber
;
13162 /* We use a special addend for an internal RELLO reloc. */
13163 if (symbol_section_p (fixp
->fx_addsy
))
13164 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13166 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13169 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13171 assert (fixp
->fx_next
!= NULL
13172 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13174 /* The reloc is relative to the RELLO; adjust the addend
13176 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13177 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
13180 /* We use a special addend for an internal RELHI reloc. */
13181 if (symbol_section_p (fixp
->fx_addsy
))
13182 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
13183 + fixp
->fx_next
->fx_where
13184 - S_GET_VALUE (fixp
->fx_subsy
));
13186 reloc
->addend
= (fixp
->fx_addnumber
13187 + fixp
->fx_next
->fx_frag
->fr_address
13188 + fixp
->fx_next
->fx_where
);
13191 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13192 reloc
->addend
= fixp
->fx_addnumber
;
13195 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13196 /* A gruesome hack which is a result of the gruesome gas reloc
13198 reloc
->addend
= reloc
->address
;
13200 reloc
->addend
= -reloc
->address
;
13203 /* If this is a variant frag, we may need to adjust the existing
13204 reloc and generate a new one. */
13205 if (fixp
->fx_frag
->fr_opcode
!= NULL
13206 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13208 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
13209 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
13210 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13211 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
13212 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13213 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
13218 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
13220 /* If this is not the last reloc in this frag, then we have two
13221 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13222 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13223 the second one handle all of them. */
13224 if (fixp
->fx_next
!= NULL
13225 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
13227 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13228 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
13229 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13230 && (fixp
->fx_next
->fx_r_type
13231 == BFD_RELOC_MIPS_GOT_LO16
))
13232 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13233 && (fixp
->fx_next
->fx_r_type
13234 == BFD_RELOC_MIPS_CALL_LO16
)));
13239 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
13240 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13241 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
13243 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13244 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13245 reloc2
->address
= (reloc
->address
13246 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
13247 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
13248 reloc2
->addend
= fixp
->fx_addnumber
;
13249 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
13250 assert (reloc2
->howto
!= NULL
);
13252 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
13256 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
13259 reloc3
->address
+= 4;
13262 if (mips_pic
== NO_PIC
)
13264 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
13265 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
13267 else if (mips_pic
== SVR4_PIC
)
13269 switch (fixp
->fx_r_type
)
13273 case BFD_RELOC_MIPS_GOT16
:
13275 case BFD_RELOC_MIPS_GOT_LO16
:
13276 case BFD_RELOC_MIPS_CALL_LO16
:
13277 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13279 case BFD_RELOC_MIPS_CALL16
:
13282 /* BFD_RELOC_MIPS_GOT16;*/
13283 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
13284 reloc2
->howto
= bfd_reloc_type_lookup
13285 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
13288 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13295 /* newabi uses R_MIPS_GOT_DISP for local symbols */
13296 if (HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
)
13298 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
13303 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13304 entry to be used in the relocation's section offset. */
13305 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13307 reloc
->address
= reloc
->addend
;
13311 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13312 fixup_segment converted a non-PC relative reloc into a PC
13313 relative reloc. In such a case, we need to convert the reloc
13315 code
= fixp
->fx_r_type
;
13316 if (fixp
->fx_pcrel
)
13321 code
= BFD_RELOC_8_PCREL
;
13324 code
= BFD_RELOC_16_PCREL
;
13327 code
= BFD_RELOC_32_PCREL
;
13330 code
= BFD_RELOC_64_PCREL
;
13332 case BFD_RELOC_8_PCREL
:
13333 case BFD_RELOC_16_PCREL
:
13334 case BFD_RELOC_32_PCREL
:
13335 case BFD_RELOC_64_PCREL
:
13336 case BFD_RELOC_16_PCREL_S2
:
13337 case BFD_RELOC_PCREL_HI16_S
:
13338 case BFD_RELOC_PCREL_LO16
:
13341 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13342 _("Cannot make %s relocation PC relative"),
13343 bfd_get_reloc_code_name (code
));
13348 /* md_apply_fix3 has a double-subtraction hack to get
13349 bfd_install_relocation to behave nicely. GPREL relocations are
13350 handled correctly without this hack, so undo it here. We can't
13351 stop md_apply_fix3 from subtracting twice in the first place since
13352 the fake addend is required for variant frags above. */
13353 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
13354 && (code
== BFD_RELOC_GPREL16
|| code
== BFD_RELOC_MIPS16_GPREL
)
13355 && reloc
->addend
!= 0
13356 && mips_need_elf_addend_fixup (fixp
))
13357 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
13360 /* To support a PC relative reloc when generating embedded PIC code
13361 for ECOFF, we use a Cygnus extension. We check for that here to
13362 make sure that we don't let such a reloc escape normally. */
13363 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13364 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13365 && code
== BFD_RELOC_16_PCREL_S2
13366 && mips_pic
!= EMBEDDED_PIC
)
13367 reloc
->howto
= NULL
;
13369 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13371 if (reloc
->howto
== NULL
)
13373 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13374 _("Can not represent %s relocation in this object file format"),
13375 bfd_get_reloc_code_name (code
));
13382 /* Relax a machine dependent frag. This returns the amount by which
13383 the current size of the frag should change. */
13386 mips_relax_frag (sec
, fragp
, stretch
)
13391 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13393 offsetT old_var
= fragp
->fr_var
;
13395 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13397 return fragp
->fr_var
- old_var
;
13400 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13403 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13405 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13407 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13412 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13414 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13421 /* Convert a machine dependent frag. */
13424 md_convert_frag (abfd
, asec
, fragp
)
13425 bfd
*abfd ATTRIBUTE_UNUSED
;
13432 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13435 unsigned long insn
;
13439 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13441 if (target_big_endian
)
13442 insn
= bfd_getb32 (buf
);
13444 insn
= bfd_getl32 (buf
);
13446 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13448 /* We generate a fixup instead of applying it right now
13449 because, if there are linker relaxations, we're going to
13450 need the relocations. */
13451 exp
.X_op
= O_symbol
;
13452 exp
.X_add_symbol
= fragp
->fr_symbol
;
13453 exp
.X_add_number
= fragp
->fr_offset
;
13455 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13457 RELAX_BRANCH_RELOC_S2 (fragp
->fr_subtype
)
13458 ? BFD_RELOC_16_PCREL_S2
13459 : BFD_RELOC_16_PCREL
);
13460 fixp
->fx_file
= fragp
->fr_file
;
13461 fixp
->fx_line
= fragp
->fr_line
;
13463 md_number_to_chars ((char *)buf
, insn
, 4);
13470 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13471 _("relaxed out-of-range branch into a jump"));
13473 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13476 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13478 /* Reverse the branch. */
13479 switch ((insn
>> 28) & 0xf)
13482 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13483 have the condition reversed by tweaking a single
13484 bit, and their opcodes all have 0x4???????. */
13485 assert ((insn
& 0xf1000000) == 0x41000000);
13486 insn
^= 0x00010000;
13490 /* bltz 0x04000000 bgez 0x04010000
13491 bltzal 0x04100000 bgezal 0x04110000 */
13492 assert ((insn
& 0xfc0e0000) == 0x04000000);
13493 insn
^= 0x00010000;
13497 /* beq 0x10000000 bne 0x14000000
13498 blez 0x18000000 bgtz 0x1c000000 */
13499 insn
^= 0x04000000;
13507 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13509 /* Clear the and-link bit. */
13510 assert ((insn
& 0xfc1c0000) == 0x04100000);
13512 /* bltzal 0x04100000 bgezal 0x04110000
13513 bltzall 0x04120000 bgezall 0x04130000 */
13514 insn
&= ~0x00100000;
13517 /* Branch over the branch (if the branch was likely) or the
13518 full jump (not likely case). Compute the offset from the
13519 current instruction to branch to. */
13520 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13524 /* How many bytes in instructions we've already emitted? */
13525 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13526 /* How many bytes in instructions from here to the end? */
13527 i
= fragp
->fr_var
- i
;
13529 /* Convert to instruction count. */
13531 /* Branch counts from the next instruction. */
13534 /* Branch over the jump. */
13535 md_number_to_chars ((char *)buf
, insn
, 4);
13539 md_number_to_chars ((char*)buf
, 0, 4);
13542 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13544 /* beql $0, $0, 2f */
13546 /* Compute the PC offset from the current instruction to
13547 the end of the variable frag. */
13548 /* How many bytes in instructions we've already emitted? */
13549 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13550 /* How many bytes in instructions from here to the end? */
13551 i
= fragp
->fr_var
- i
;
13552 /* Convert to instruction count. */
13554 /* Don't decrement i, because we want to branch over the
13558 md_number_to_chars ((char *)buf
, insn
, 4);
13561 md_number_to_chars ((char *)buf
, 0, 4);
13566 if (mips_pic
== NO_PIC
)
13569 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13570 ? 0x0c000000 : 0x08000000);
13571 exp
.X_op
= O_symbol
;
13572 exp
.X_add_symbol
= fragp
->fr_symbol
;
13573 exp
.X_add_number
= fragp
->fr_offset
;
13575 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13576 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13577 fixp
->fx_file
= fragp
->fr_file
;
13578 fixp
->fx_line
= fragp
->fr_line
;
13580 md_number_to_chars ((char*)buf
, insn
, 4);
13585 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13586 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13587 exp
.X_op
= O_symbol
;
13588 exp
.X_add_symbol
= fragp
->fr_symbol
;
13589 exp
.X_add_number
= fragp
->fr_offset
;
13591 if (fragp
->fr_offset
)
13593 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13594 exp
.X_add_number
= 0;
13597 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13598 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13599 fixp
->fx_file
= fragp
->fr_file
;
13600 fixp
->fx_line
= fragp
->fr_line
;
13602 md_number_to_chars ((char*)buf
, insn
, 4);
13605 if (mips_opts
.isa
== ISA_MIPS1
)
13608 md_number_to_chars ((char*)buf
, 0, 4);
13612 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13613 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13615 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13616 4, &exp
, 0, BFD_RELOC_LO16
);
13617 fixp
->fx_file
= fragp
->fr_file
;
13618 fixp
->fx_line
= fragp
->fr_line
;
13620 md_number_to_chars ((char*)buf
, insn
, 4);
13624 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13629 md_number_to_chars ((char*)buf
, insn
, 4);
13634 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13635 + fragp
->fr_fix
+ fragp
->fr_var
);
13637 fragp
->fr_fix
+= fragp
->fr_var
;
13642 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13645 register const struct mips16_immed_operand
*op
;
13646 bfd_boolean small
, ext
;
13649 unsigned long insn
;
13650 bfd_boolean use_extend
;
13651 unsigned short extend
;
13653 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13654 op
= mips16_immed_operands
;
13655 while (op
->type
!= type
)
13658 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13669 resolve_symbol_value (fragp
->fr_symbol
);
13670 val
= S_GET_VALUE (fragp
->fr_symbol
);
13675 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13677 /* The rules for the base address of a PC relative reloc are
13678 complicated; see mips16_extended_frag. */
13679 if (type
== 'p' || type
== 'q')
13684 /* Ignore the low bit in the target, since it will be
13685 set for a text label. */
13686 if ((val
& 1) != 0)
13689 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13691 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13694 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13697 /* Make sure the section winds up with the alignment we have
13700 record_alignment (asec
, op
->shift
);
13704 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13705 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13706 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13707 _("extended instruction in delay slot"));
13709 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13711 if (target_big_endian
)
13712 insn
= bfd_getb16 (buf
);
13714 insn
= bfd_getl16 (buf
);
13716 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13717 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13718 small
, ext
, &insn
, &use_extend
, &extend
);
13722 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13723 fragp
->fr_fix
+= 2;
13727 md_number_to_chars ((char *) buf
, insn
, 2);
13728 fragp
->fr_fix
+= 2;
13733 if (fragp
->fr_opcode
== NULL
)
13736 old
= RELAX_OLD (fragp
->fr_subtype
);
13737 new = RELAX_NEW (fragp
->fr_subtype
);
13738 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
13741 memcpy (fixptr
- old
, fixptr
, new);
13743 fragp
->fr_fix
+= new - old
;
13749 /* This function is called after the relocs have been generated.
13750 We've been storing mips16 text labels as odd. Here we convert them
13751 back to even for the convenience of the debugger. */
13754 mips_frob_file_after_relocs ()
13757 unsigned int count
, i
;
13759 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13762 syms
= bfd_get_outsymbols (stdoutput
);
13763 count
= bfd_get_symcount (stdoutput
);
13764 for (i
= 0; i
< count
; i
++, syms
++)
13766 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13767 && ((*syms
)->value
& 1) != 0)
13769 (*syms
)->value
&= ~1;
13770 /* If the symbol has an odd size, it was probably computed
13771 incorrectly, so adjust that as well. */
13772 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13773 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13780 /* This function is called whenever a label is defined. It is used
13781 when handling branch delays; if a branch has a label, we assume we
13782 can not move it. */
13785 mips_define_label (sym
)
13788 struct insn_label_list
*l
;
13790 if (free_insn_labels
== NULL
)
13791 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13794 l
= free_insn_labels
;
13795 free_insn_labels
= l
->next
;
13799 l
->next
= insn_labels
;
13803 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13805 /* Some special processing for a MIPS ELF file. */
13808 mips_elf_final_processing ()
13810 /* Write out the register information. */
13811 if (mips_abi
!= N64_ABI
)
13815 s
.ri_gprmask
= mips_gprmask
;
13816 s
.ri_cprmask
[0] = mips_cprmask
[0];
13817 s
.ri_cprmask
[1] = mips_cprmask
[1];
13818 s
.ri_cprmask
[2] = mips_cprmask
[2];
13819 s
.ri_cprmask
[3] = mips_cprmask
[3];
13820 /* The gp_value field is set by the MIPS ELF backend. */
13822 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13823 ((Elf32_External_RegInfo
*)
13824 mips_regmask_frag
));
13828 Elf64_Internal_RegInfo s
;
13830 s
.ri_gprmask
= mips_gprmask
;
13832 s
.ri_cprmask
[0] = mips_cprmask
[0];
13833 s
.ri_cprmask
[1] = mips_cprmask
[1];
13834 s
.ri_cprmask
[2] = mips_cprmask
[2];
13835 s
.ri_cprmask
[3] = mips_cprmask
[3];
13836 /* The gp_value field is set by the MIPS ELF backend. */
13838 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13839 ((Elf64_External_RegInfo
*)
13840 mips_regmask_frag
));
13843 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13844 sort of BFD interface for this. */
13845 if (mips_any_noreorder
)
13846 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13847 if (mips_pic
!= NO_PIC
)
13848 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13850 /* Set MIPS ELF flags for ASEs. */
13851 if (file_ase_mips16
)
13852 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13853 #if 0 /* XXX FIXME */
13854 if (file_ase_mips3d
)
13855 elf_elfheader (stdoutput
)->e_flags
|= ???;
13858 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13860 /* Set the MIPS ELF ABI flags. */
13861 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13862 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13863 else if (mips_abi
== O64_ABI
)
13864 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13865 else if (mips_abi
== EABI_ABI
)
13867 if (!file_mips_gp32
)
13868 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13870 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13872 else if (mips_abi
== N32_ABI
)
13873 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13875 /* Nothing to do for N64_ABI. */
13877 if (mips_32bitmode
)
13878 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13881 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13883 typedef struct proc
{
13885 unsigned long reg_mask
;
13886 unsigned long reg_offset
;
13887 unsigned long fpreg_mask
;
13888 unsigned long fpreg_offset
;
13889 unsigned long frame_offset
;
13890 unsigned long frame_reg
;
13891 unsigned long pc_reg
;
13894 static procS cur_proc
;
13895 static procS
*cur_proc_ptr
;
13896 static int numprocs
;
13898 /* Fill in an rs_align_code fragment. */
13901 mips_handle_align (fragp
)
13904 if (fragp
->fr_type
!= rs_align_code
)
13907 if (mips_opts
.mips16
)
13909 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13910 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13915 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13916 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13924 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13928 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13939 /* check for premature end, nesting errors, etc */
13941 as_warn (_("missing .end at end of assembly"));
13950 if (*input_line_pointer
== '-')
13952 ++input_line_pointer
;
13955 if (!ISDIGIT (*input_line_pointer
))
13956 as_bad (_("expected simple number"));
13957 if (input_line_pointer
[0] == '0')
13959 if (input_line_pointer
[1] == 'x')
13961 input_line_pointer
+= 2;
13962 while (ISXDIGIT (*input_line_pointer
))
13965 val
|= hex_value (*input_line_pointer
++);
13967 return negative
? -val
: val
;
13971 ++input_line_pointer
;
13972 while (ISDIGIT (*input_line_pointer
))
13975 val
|= *input_line_pointer
++ - '0';
13977 return negative
? -val
: val
;
13980 if (!ISDIGIT (*input_line_pointer
))
13982 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13983 *input_line_pointer
, *input_line_pointer
);
13984 as_warn (_("invalid number"));
13987 while (ISDIGIT (*input_line_pointer
))
13990 val
+= *input_line_pointer
++ - '0';
13992 return negative
? -val
: val
;
13995 /* The .file directive; just like the usual .file directive, but there
13996 is an initial number which is the ECOFF file index. In the non-ECOFF
13997 case .file implies DWARF-2. */
14001 int x ATTRIBUTE_UNUSED
;
14003 static int first_file_directive
= 0;
14005 if (ECOFF_DEBUGGING
)
14014 filename
= dwarf2_directive_file (0);
14016 /* Versions of GCC up to 3.1 start files with a ".file"
14017 directive even for stabs output. Make sure that this
14018 ".file" is handled. Note that you need a version of GCC
14019 after 3.1 in order to support DWARF-2 on MIPS. */
14020 if (filename
!= NULL
&& ! first_file_directive
)
14022 (void) new_logical_line (filename
, -1);
14023 s_app_file_string (filename
);
14025 first_file_directive
= 1;
14029 /* The .loc directive, implying DWARF-2. */
14033 int x ATTRIBUTE_UNUSED
;
14035 if (!ECOFF_DEBUGGING
)
14036 dwarf2_directive_loc (0);
14039 /* The .end directive. */
14043 int x ATTRIBUTE_UNUSED
;
14048 /* Following functions need their own .frame and .cprestore directives. */
14049 mips_frame_reg_valid
= 0;
14050 mips_cprestore_valid
= 0;
14052 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14055 demand_empty_rest_of_line ();
14060 #ifdef BFD_ASSEMBLER
14061 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14066 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14073 as_warn (_(".end not in text section"));
14077 as_warn (_(".end directive without a preceding .ent directive."));
14078 demand_empty_rest_of_line ();
14084 assert (S_GET_NAME (p
));
14085 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
14086 as_warn (_(".end symbol does not match .ent symbol."));
14088 if (debug_type
== DEBUG_STABS
)
14089 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14093 as_warn (_(".end directive missing or unknown symbol"));
14096 /* Generate a .pdr section. */
14097 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14099 segT saved_seg
= now_seg
;
14100 subsegT saved_subseg
= now_subseg
;
14105 dot
= frag_now_fix ();
14107 #ifdef md_flush_pending_output
14108 md_flush_pending_output ();
14112 subseg_set (pdr_seg
, 0);
14114 /* Write the symbol. */
14115 exp
.X_op
= O_symbol
;
14116 exp
.X_add_symbol
= p
;
14117 exp
.X_add_number
= 0;
14118 emit_expr (&exp
, 4);
14120 fragp
= frag_more (7 * 4);
14122 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
14123 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
14124 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
14125 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
14126 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
14127 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
14128 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
14130 subseg_set (saved_seg
, saved_subseg
);
14132 #endif /* OBJ_ELF */
14134 cur_proc_ptr
= NULL
;
14137 /* The .aent and .ent directives. */
14146 symbolP
= get_symbol ();
14147 if (*input_line_pointer
== ',')
14148 ++input_line_pointer
;
14149 SKIP_WHITESPACE ();
14150 if (ISDIGIT (*input_line_pointer
)
14151 || *input_line_pointer
== '-')
14154 #ifdef BFD_ASSEMBLER
14155 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14160 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14167 as_warn (_(".ent or .aent not in text section."));
14169 if (!aent
&& cur_proc_ptr
)
14170 as_warn (_("missing .end"));
14174 /* This function needs its own .frame and .cprestore directives. */
14175 mips_frame_reg_valid
= 0;
14176 mips_cprestore_valid
= 0;
14178 cur_proc_ptr
= &cur_proc
;
14179 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14181 cur_proc_ptr
->isym
= symbolP
;
14183 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14187 if (debug_type
== DEBUG_STABS
)
14188 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14189 S_GET_NAME (symbolP
));
14192 demand_empty_rest_of_line ();
14195 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14196 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14197 s_mips_frame is used so that we can set the PDR information correctly.
14198 We can't use the ecoff routines because they make reference to the ecoff
14199 symbol table (in the mdebug section). */
14202 s_mips_frame (ignore
)
14203 int ignore ATTRIBUTE_UNUSED
;
14206 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14210 if (cur_proc_ptr
== (procS
*) NULL
)
14212 as_warn (_(".frame outside of .ent"));
14213 demand_empty_rest_of_line ();
14217 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14219 SKIP_WHITESPACE ();
14220 if (*input_line_pointer
++ != ','
14221 || get_absolute_expression_and_terminator (&val
) != ',')
14223 as_warn (_("Bad .frame directive"));
14224 --input_line_pointer
;
14225 demand_empty_rest_of_line ();
14229 cur_proc_ptr
->frame_offset
= val
;
14230 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14232 demand_empty_rest_of_line ();
14235 #endif /* OBJ_ELF */
14239 /* The .fmask and .mask directives. If the mdebug section is present
14240 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14241 embedded targets, s_mips_mask is used so that we can set the PDR
14242 information correctly. We can't use the ecoff routines because they
14243 make reference to the ecoff symbol table (in the mdebug section). */
14246 s_mips_mask (reg_type
)
14250 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14254 if (cur_proc_ptr
== (procS
*) NULL
)
14256 as_warn (_(".mask/.fmask outside of .ent"));
14257 demand_empty_rest_of_line ();
14261 if (get_absolute_expression_and_terminator (&mask
) != ',')
14263 as_warn (_("Bad .mask/.fmask directive"));
14264 --input_line_pointer
;
14265 demand_empty_rest_of_line ();
14269 off
= get_absolute_expression ();
14271 if (reg_type
== 'F')
14273 cur_proc_ptr
->fpreg_mask
= mask
;
14274 cur_proc_ptr
->fpreg_offset
= off
;
14278 cur_proc_ptr
->reg_mask
= mask
;
14279 cur_proc_ptr
->reg_offset
= off
;
14282 demand_empty_rest_of_line ();
14285 #endif /* OBJ_ELF */
14286 s_ignore (reg_type
);
14289 /* The .loc directive. */
14300 assert (now_seg
== text_section
);
14302 lineno
= get_number ();
14303 addroff
= frag_now_fix ();
14305 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14306 S_SET_TYPE (symbolP
, N_SLINE
);
14307 S_SET_OTHER (symbolP
, 0);
14308 S_SET_DESC (symbolP
, lineno
);
14309 symbolP
->sy_segment
= now_seg
;
14313 /* A table describing all the processors gas knows about. Names are
14314 matched in the order listed.
14316 To ease comparison, please keep this table in the same order as
14317 gcc's mips_cpu_info_table[]. */
14318 static const struct mips_cpu_info mips_cpu_info_table
[] =
14320 /* Entries for generic ISAs */
14321 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14322 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14323 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14324 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14325 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14326 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14327 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14330 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14331 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14332 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14335 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14338 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14339 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14340 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14341 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14342 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14343 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14344 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14345 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14346 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14347 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14348 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14349 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14352 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14353 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14354 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14355 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14356 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14357 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14358 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14359 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14360 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14361 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14362 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14363 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
14366 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
14367 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14368 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14371 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14372 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14374 /* Broadcom SB-1 CPU core */
14375 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14382 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14383 with a final "000" replaced by "k". Ignore case.
14385 Note: this function is shared between GCC and GAS. */
14388 mips_strict_matching_cpu_name_p (canonical
, given
)
14389 const char *canonical
, *given
;
14391 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14392 given
++, canonical
++;
14394 return ((*given
== 0 && *canonical
== 0)
14395 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14399 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14400 CPU name. We've traditionally allowed a lot of variation here.
14402 Note: this function is shared between GCC and GAS. */
14405 mips_matching_cpu_name_p (canonical
, given
)
14406 const char *canonical
, *given
;
14408 /* First see if the name matches exactly, or with a final "000"
14409 turned into "k". */
14410 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14413 /* If not, try comparing based on numerical designation alone.
14414 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14415 if (TOLOWER (*given
) == 'r')
14417 if (!ISDIGIT (*given
))
14420 /* Skip over some well-known prefixes in the canonical name,
14421 hoping to find a number there too. */
14422 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14424 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14426 else if (TOLOWER (canonical
[0]) == 'r')
14429 return mips_strict_matching_cpu_name_p (canonical
, given
);
14433 /* Parse an option that takes the name of a processor as its argument.
14434 OPTION is the name of the option and CPU_STRING is the argument.
14435 Return the corresponding processor enumeration if the CPU_STRING is
14436 recognized, otherwise report an error and return null.
14438 A similar function exists in GCC. */
14440 static const struct mips_cpu_info
*
14441 mips_parse_cpu (option
, cpu_string
)
14442 const char *option
, *cpu_string
;
14444 const struct mips_cpu_info
*p
;
14446 /* 'from-abi' selects the most compatible architecture for the given
14447 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14448 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14449 version. Look first at the -mgp options, if given, otherwise base
14450 the choice on MIPS_DEFAULT_64BIT.
14452 Treat NO_ABI like the EABIs. One reason to do this is that the
14453 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14454 architecture. This code picks MIPS I for 'mips' and MIPS III for
14455 'mips64', just as we did in the days before 'from-abi'. */
14456 if (strcasecmp (cpu_string
, "from-abi") == 0)
14458 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14459 return mips_cpu_info_from_isa (ISA_MIPS1
);
14461 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14462 return mips_cpu_info_from_isa (ISA_MIPS3
);
14464 if (file_mips_gp32
>= 0)
14465 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14467 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14472 /* 'default' has traditionally been a no-op. Probably not very useful. */
14473 if (strcasecmp (cpu_string
, "default") == 0)
14476 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14477 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14480 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14484 /* Return the canonical processor information for ISA (a member of the
14485 ISA_MIPS* enumeration). */
14487 static const struct mips_cpu_info
*
14488 mips_cpu_info_from_isa (isa
)
14493 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14494 if (mips_cpu_info_table
[i
].is_isa
14495 && isa
== mips_cpu_info_table
[i
].isa
)
14496 return (&mips_cpu_info_table
[i
]);
14502 show (stream
, string
, col_p
, first_p
)
14504 const char *string
;
14510 fprintf (stream
, "%24s", "");
14515 fprintf (stream
, ", ");
14519 if (*col_p
+ strlen (string
) > 72)
14521 fprintf (stream
, "\n%24s", "");
14525 fprintf (stream
, "%s", string
);
14526 *col_p
+= strlen (string
);
14532 md_show_usage (stream
)
14538 fprintf (stream
, _("\
14540 -membedded-pic generate embedded position independent code\n\
14541 -EB generate big endian output\n\
14542 -EL generate little endian output\n\
14543 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14544 -G NUM allow referencing objects up to NUM bytes\n\
14545 implicitly with the gp register [default 8]\n"));
14546 fprintf (stream
, _("\
14547 -mips1 generate MIPS ISA I instructions\n\
14548 -mips2 generate MIPS ISA II instructions\n\
14549 -mips3 generate MIPS ISA III instructions\n\
14550 -mips4 generate MIPS ISA IV instructions\n\
14551 -mips5 generate MIPS ISA V instructions\n\
14552 -mips32 generate MIPS32 ISA instructions\n\
14553 -mips64 generate MIPS64 ISA instructions\n\
14554 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14558 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14559 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14560 show (stream
, "from-abi", &column
, &first
);
14561 fputc ('\n', stream
);
14563 fprintf (stream
, _("\
14564 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14565 -no-mCPU don't generate code specific to CPU.\n\
14566 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14570 show (stream
, "3900", &column
, &first
);
14571 show (stream
, "4010", &column
, &first
);
14572 show (stream
, "4100", &column
, &first
);
14573 show (stream
, "4650", &column
, &first
);
14574 fputc ('\n', stream
);
14576 fprintf (stream
, _("\
14577 -mips16 generate mips16 instructions\n\
14578 -no-mips16 do not generate mips16 instructions\n"));
14579 fprintf (stream
, _("\
14580 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14581 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14582 -O0 remove unneeded NOPs, do not swap branches\n\
14583 -O remove unneeded NOPs and swap branches\n\
14584 -n warn about NOPs generated from macros\n\
14585 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14586 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14587 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14589 fprintf (stream
, _("\
14590 -KPIC, -call_shared generate SVR4 position independent code\n\
14591 -non_shared do not generate position independent code\n\
14592 -xgot assume a 32 bit GOT\n\
14593 -mabi=ABI create ABI conformant object file for:\n"));
14597 show (stream
, "32", &column
, &first
);
14598 show (stream
, "o64", &column
, &first
);
14599 show (stream
, "n32", &column
, &first
);
14600 show (stream
, "64", &column
, &first
);
14601 show (stream
, "eabi", &column
, &first
);
14603 fputc ('\n', stream
);
14605 fprintf (stream
, _("\
14606 -32 create o32 ABI object file (default)\n\
14607 -n32 create n32 ABI object file\n\
14608 -64 create 64 ABI object file\n"));
14613 mips_dwarf2_format ()
14615 if (mips_abi
== N64_ABI
)
14616 return dwarf2_format_64bit_irix
;
14618 return dwarf2_format_32bit
;