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[binutils.git] / opcodes / cris-opc.c
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1 /* cris-opc.c -- Table of opcodes for the CRIS processor.
2 Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
3 Contributed by Axis Communications AB, Lund, Sweden.
4 Originally written for GAS 1.38.1 by Mikael Asker.
5 Reorganized by Hans-Peter Nilsson.
7 This file is part of GAS, GDB and the GNU binutils.
9 GAS, GDB, and GNU binutils is free software; you can redistribute it
10 and/or modify it under the terms of the GNU General Public License as
11 published by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GAS, GDB, and GNU binutils are distributed in the hope that they will be
15 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
23 #include "opcode/cris.h"
25 #ifndef NULL
26 #define NULL (0)
27 #endif
29 /* This table isn't used for CRISv32 and the size of immediate operands. */
30 const struct cris_spec_reg
31 cris_spec_regs[] =
33 {"bz", 0, 1, cris_ver_v32p, NULL},
34 {"p0", 0, 1, 0, NULL},
35 {"vr", 1, 1, 0, NULL},
36 {"p1", 1, 1, 0, NULL},
37 {"pid", 2, 1, cris_ver_v32p, NULL},
38 {"p2", 2, 1, cris_ver_v32p, NULL},
39 {"p2", 2, 1, cris_ver_warning, NULL},
40 {"srs", 3, 1, cris_ver_v32p, NULL},
41 {"p3", 3, 1, cris_ver_v32p, NULL},
42 {"p3", 3, 1, cris_ver_warning, NULL},
43 {"wz", 4, 2, cris_ver_v32p, NULL},
44 {"p4", 4, 2, 0, NULL},
45 {"ccr", 5, 2, cris_ver_v0_10, NULL},
46 {"exs", 5, 4, cris_ver_v32p, NULL},
47 {"p5", 5, 2, cris_ver_v0_10, NULL},
48 {"p5", 5, 4, cris_ver_v32p, NULL},
49 {"dcr0",6, 2, cris_ver_v0_3, NULL},
50 {"eda", 6, 4, cris_ver_v32p, NULL},
51 {"p6", 6, 2, cris_ver_v0_3, NULL},
52 {"p6", 6, 4, cris_ver_v32p, NULL},
53 {"dcr1/mof", 7, 4, cris_ver_v10p,
54 "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
55 {"dcr1/mof", 7, 2, cris_ver_v0_3,
56 "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"},
57 {"mof", 7, 4, cris_ver_v10p, NULL},
58 {"dcr1",7, 2, cris_ver_v0_3, NULL},
59 {"p7", 7, 4, cris_ver_v10p, NULL},
60 {"p7", 7, 2, cris_ver_v0_3, NULL},
61 {"dz", 8, 4, cris_ver_v32p, NULL},
62 {"p8", 8, 4, 0, NULL},
63 {"ibr", 9, 4, cris_ver_v0_10, NULL},
64 {"ebp", 9, 4, cris_ver_v32p, NULL},
65 {"p9", 9, 4, 0, NULL},
66 {"irp", 10, 4, cris_ver_v0_10, NULL},
67 {"erp", 10, 4, cris_ver_v32p, NULL},
68 {"p10", 10, 4, 0, NULL},
69 {"srp", 11, 4, 0, NULL},
70 {"p11", 11, 4, 0, NULL},
71 /* For disassembly use only. Accept at assembly with a warning. */
72 {"bar/dtp0", 12, 4, cris_ver_warning,
73 "Ambiguous register `bar/dtp0' specified"},
74 {"nrp", 12, 4, cris_ver_v32p, NULL},
75 {"bar", 12, 4, cris_ver_v8_10, NULL},
76 {"dtp0",12, 4, cris_ver_v0_3, NULL},
77 {"p12", 12, 4, 0, NULL},
78 /* For disassembly use only. Accept at assembly with a warning. */
79 {"dccr/dtp1",13, 4, cris_ver_warning,
80 "Ambiguous register `dccr/dtp1' specified"},
81 {"ccs", 13, 4, cris_ver_v32p, NULL},
82 {"dccr",13, 4, cris_ver_v8_10, NULL},
83 {"dtp1",13, 4, cris_ver_v0_3, NULL},
84 {"p13", 13, 4, 0, NULL},
85 {"brp", 14, 4, cris_ver_v3_10, NULL},
86 {"usp", 14, 4, cris_ver_v32p, NULL},
87 {"p14", 14, 4, cris_ver_v3p, NULL},
88 {"usp", 15, 4, cris_ver_v10, NULL},
89 {"spc", 15, 4, cris_ver_v32p, NULL},
90 {"p15", 15, 4, cris_ver_v10p, NULL},
91 {NULL, 0, 0, cris_ver_version_all, NULL}
94 /* Add version specifiers to this table when necessary.
95 The (now) regular coding of register names suggests a simpler
96 implementation. */
97 const struct cris_support_reg cris_support_regs[] =
99 {"s0", 0},
100 {"s1", 1},
101 {"s2", 2},
102 {"s3", 3},
103 {"s4", 4},
104 {"s5", 5},
105 {"s6", 6},
106 {"s7", 7},
107 {"s8", 8},
108 {"s9", 9},
109 {"s10", 10},
110 {"s11", 11},
111 {"s12", 12},
112 {"s13", 13},
113 {"s14", 14},
114 {"s15", 15},
115 {NULL, 0}
118 /* All CRIS opcodes are 16 bits.
120 - The match component is a mask saying which bits must match a
121 particular opcode in order for an instruction to be an instance
122 of that opcode.
124 - The args component is a string containing characters symbolically
125 matching the operands of an instruction. Used for both assembly
126 and disassembly.
128 Operand-matching characters:
129 [ ] , space
130 Verbatim.
131 A The string "ACR" (case-insensitive).
132 B Not really an operand. It causes a "BDAP -size,SP" prefix to be
133 output for the PUSH alias-instructions and recognizes a push-
134 prefix at disassembly. This letter isn't recognized for v32.
135 Must be followed by a R or P letter.
136 ! Non-match pattern, will not match if there's a prefix insn.
137 b Non-matching operand, used for branches with 16-bit
138 displacement. Only recognized by the disassembler.
139 c 5-bit unsigned immediate in bits <4:0>.
140 C 4-bit unsigned immediate in bits <3:0>.
141 d At assembly, optionally (as in put other cases before this one)
142 ".d" or ".D" at the start of the operands, followed by one space
143 character. At disassembly, nothing.
144 D General register in bits <15:12> and <3:0>.
145 f List of flags in bits <15:12> and <3:0>.
146 i 6-bit signed immediate in bits <5:0>.
147 I 6-bit unsigned immediate in bits <5:0>.
148 M Size modifier (B, W or D) for CLEAR instructions.
149 m Size modifier (B, W or D) in bits <5:4>
150 N A 32-bit dword, like in the difference between s and y.
151 This has no effect on bits in the opcode. Can also be expressed
152 as "[pc+]" in input.
153 n As N, but PC-relative (to the start of the instruction).
154 o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
155 branch instructions.
156 O [-128..127] offset in bits <7:0>. Also matches a comma and a
157 general register after the expression, in bits <15:12>. Used
158 only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
159 P Special register in bits <15:12>.
160 p Indicates that the insn is a prefix insn. Must be first
161 character.
162 Q As O, but don't relax; force an 8-bit offset.
163 R General register in bits <15:12>.
164 r General register in bits <3:0>.
165 S Source operand in bit <10> and a prefix; a 3-operand prefix
166 without side-effect.
167 s Source operand in bits <10> and <3:0>, optionally with a
168 side-effect prefix, except [pc] (the name, not R15 as in ACR)
169 isn't allowed for v32 and higher.
170 T Support register in bits <15:12>.
171 u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
172 U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
173 Not recognized at disassembly.
174 x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
175 y Like 's' but do not allow an integer at assembly.
176 Y The difference s-y; only an integer is allowed.
177 z Size modifier (B or W) in bit <4>. */
180 /* Please note the order of the opcodes in this table is significant.
181 The assembler requires that all instances of the same mnemonic must
182 be consecutive. If they aren't, the assembler might not recognize
183 them, or may indicate an internal error.
185 The disassembler should not normally care about the order of the
186 opcodes, but will prefer an earlier alternative if the "match-score"
187 (see cris-dis.c) is computed as equal.
189 It should not be significant for proper execution that this table is
190 in alphabetical order, but please follow that convention for an easy
191 overview. */
193 const struct cris_opcode
194 cris_opcodes[] =
196 {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0,
197 cris_abs_op},
199 {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0,
200 cris_reg_mode_add_sub_cmp_and_or_move_op},
202 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0,
203 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
205 {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE,
206 cris_ver_v0_10,
207 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
209 {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE,
210 cris_ver_v0_10,
211 cris_three_operand_add_sub_cmp_and_or_op},
213 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD,
214 cris_ver_v32p,
215 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
217 {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32,
218 cris_ver_v32p,
219 cris_not_implemented_op},
221 {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32,
222 cris_ver_v32p,
223 cris_not_implemented_op},
225 {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE,
226 cris_ver_v32p,
227 cris_addi_op},
229 {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0,
230 cris_addi_op},
232 /* This collates after "addo", but we want to disassemble as "addoq",
233 not "addo". */
234 {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE,
235 cris_ver_v32p,
236 cris_not_implemented_op},
238 {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED,
239 cris_ver_v32p,
240 cris_not_implemented_op},
242 /* This must be located after the insn above, lest we misinterpret
243 "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a
244 parser bug. */
245 {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE,
246 cris_ver_v32p,
247 cris_not_implemented_op},
249 {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0,
250 cris_quick_mode_add_sub_op},
252 {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0,
253 cris_reg_mode_add_sub_cmp_and_or_move_op},
255 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
256 {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0,
257 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
259 {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE,
260 cris_ver_v0_10,
261 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
263 {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE,
264 cris_ver_v0_10,
265 cris_three_operand_add_sub_cmp_and_or_op},
267 {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0,
268 cris_reg_mode_add_sub_cmp_and_or_move_op},
270 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
271 {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0,
272 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
274 {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE,
275 cris_ver_v0_10,
276 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
278 {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE,
279 cris_ver_v0_10,
280 cris_three_operand_add_sub_cmp_and_or_op},
282 {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0,
283 cris_reg_mode_add_sub_cmp_and_or_move_op},
285 {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0,
286 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
288 {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE,
289 cris_ver_v0_10,
290 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
292 {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE,
293 cris_ver_v0_10,
294 cris_three_operand_add_sub_cmp_and_or_op},
296 {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0,
297 cris_quick_mode_and_cmp_move_or_op},
299 {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0,
300 cris_asr_op},
302 {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0,
303 cris_asrq_op},
305 {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0,
306 cris_ax_ei_setf_op},
308 /* FIXME: Should use branch #defines. */
309 {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0,
310 cris_sixteen_bit_offset_branch_op},
312 {"ba",
313 BA_QUICK_OPCODE,
314 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0,
315 cris_eight_bit_offset_branch_op},
317 /* Needs to come after the usual "ba o", which might be relaxed to
318 this one. */
319 {"ba", BA_DWORD_OPCODE,
320 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32,
321 cris_ver_v32p,
322 cris_none_reg_mode_jump_op},
324 {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32,
325 cris_ver_v32p,
326 cris_none_reg_mode_jump_op},
328 {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32,
329 cris_ver_v32p,
330 cris_none_reg_mode_jump_op},
332 {"bcc",
333 BRANCH_QUICK_OPCODE+CC_CC*0x1000,
334 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0,
335 cris_eight_bit_offset_branch_op},
337 {"bcs",
338 BRANCH_QUICK_OPCODE+CC_CS*0x1000,
339 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0,
340 cris_eight_bit_offset_branch_op},
342 {"bdap",
343 BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED,
344 cris_ver_v0_10,
345 cris_bdap_prefix},
347 {"bdap",
348 BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE,
349 cris_ver_v0_10,
350 cris_quick_mode_bdap_prefix},
352 {"beq",
353 BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
354 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0,
355 cris_eight_bit_offset_branch_op},
357 /* This is deliberately put before "bext" to trump it, even though not
358 in alphabetical order, since we don't do excluding version checks
359 for v0..v10. */
360 {"bwf",
361 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
362 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
363 cris_ver_v10,
364 cris_eight_bit_offset_branch_op},
366 {"bext",
367 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
368 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
369 cris_ver_v0_3,
370 cris_eight_bit_offset_branch_op},
372 {"bge",
373 BRANCH_QUICK_OPCODE+CC_GE*0x1000,
374 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0,
375 cris_eight_bit_offset_branch_op},
377 {"bgt",
378 BRANCH_QUICK_OPCODE+CC_GT*0x1000,
379 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0,
380 cris_eight_bit_offset_branch_op},
382 {"bhi",
383 BRANCH_QUICK_OPCODE+CC_HI*0x1000,
384 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0,
385 cris_eight_bit_offset_branch_op},
387 {"bhs",
388 BRANCH_QUICK_OPCODE+CC_HS*0x1000,
389 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0,
390 cris_eight_bit_offset_branch_op},
392 {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE,
393 cris_ver_v0_10,
394 cris_biap_prefix},
396 {"ble",
397 BRANCH_QUICK_OPCODE+CC_LE*0x1000,
398 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0,
399 cris_eight_bit_offset_branch_op},
401 {"blo",
402 BRANCH_QUICK_OPCODE+CC_LO*0x1000,
403 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0,
404 cris_eight_bit_offset_branch_op},
406 {"bls",
407 BRANCH_QUICK_OPCODE+CC_LS*0x1000,
408 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0,
409 cris_eight_bit_offset_branch_op},
411 {"blt",
412 BRANCH_QUICK_OPCODE+CC_LT*0x1000,
413 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0,
414 cris_eight_bit_offset_branch_op},
416 {"bmi",
417 BRANCH_QUICK_OPCODE+CC_MI*0x1000,
418 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0,
419 cris_eight_bit_offset_branch_op},
421 {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32,
422 cris_ver_sim_v0_10,
423 cris_not_implemented_op},
425 {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE,
426 cris_ver_sim_v0_10,
427 cris_not_implemented_op},
429 {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE,
430 cris_ver_sim_v0_10,
431 cris_not_implemented_op},
433 {"bne",
434 BRANCH_QUICK_OPCODE+CC_NE*0x1000,
435 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0,
436 cris_eight_bit_offset_branch_op},
438 {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0,
439 cris_two_operand_bound_op},
440 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
441 {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD,
442 cris_ver_v0_10,
443 cris_two_operand_bound_op},
444 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
445 {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0,
446 cris_two_operand_bound_op},
447 {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE,
448 cris_ver_v0_10,
449 cris_two_operand_bound_op},
450 {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE,
451 cris_ver_v0_10,
452 cris_three_operand_bound_op},
454 {"bpl",
455 BRANCH_QUICK_OPCODE+CC_PL*0x1000,
456 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0,
457 cris_eight_bit_offset_branch_op},
459 {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE,
460 cris_ver_v3p,
461 cris_break_op},
463 {"bsb",
464 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
465 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
466 cris_ver_v32p,
467 cris_eight_bit_offset_branch_op},
469 {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32,
470 cris_ver_v32p,
471 cris_none_reg_mode_jump_op},
473 {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32,
474 cris_ver_v32p,
475 cris_none_reg_mode_jump_op},
477 {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32,
478 cris_ver_warning,
479 cris_not_implemented_op},
481 {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE,
482 cris_ver_warning,
483 cris_not_implemented_op},
485 {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE,
486 cris_ver_warning,
487 cris_not_implemented_op},
489 {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0,
490 cris_btst_nop_op},
491 {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0,
492 cris_btst_nop_op},
494 {"bvc",
495 BRANCH_QUICK_OPCODE+CC_VC*0x1000,
496 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0,
497 cris_eight_bit_offset_branch_op},
499 {"bvs",
500 BRANCH_QUICK_OPCODE+CC_VS*0x1000,
501 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0,
502 cris_eight_bit_offset_branch_op},
504 {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0,
505 cris_reg_mode_clear_op},
507 {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0,
508 cris_none_reg_mode_clear_test_op},
510 {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE,
511 cris_ver_v0_10,
512 cris_none_reg_mode_clear_test_op},
514 {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0,
515 cris_clearf_di_op},
517 {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0,
518 cris_reg_mode_add_sub_cmp_and_or_move_op},
520 {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0,
521 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
523 {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE,
524 cris_ver_v0_10,
525 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
527 {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0,
528 cris_quick_mode_and_cmp_move_or_op},
530 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
531 {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0,
532 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
534 {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE,
535 cris_ver_v0_10,
536 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
538 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
539 {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0,
540 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
542 {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE,
543 cris_ver_v0_10,
544 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
546 {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0,
547 cris_clearf_di_op},
549 {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32,
550 cris_ver_v0_10,
551 cris_dip_prefix},
553 {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0,
554 cris_not_implemented_op},
556 {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0,
557 cris_dstep_logshift_mstep_neg_not_op},
559 {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0,
560 cris_ax_ei_setf_op},
562 {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE,
563 cris_ver_v32p,
564 cris_not_implemented_op},
566 {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE,
567 cris_ver_v32p,
568 cris_not_implemented_op},
570 {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE,
571 cris_ver_v32p,
572 cris_not_implemented_op},
574 {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE,
575 cris_ver_v32p,
576 cris_not_implemented_op},
578 {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE,
579 cris_ver_v32p,
580 cris_not_implemented_op},
582 {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE,
583 cris_ver_v32p,
584 cris_reg_mode_jump_op},
586 {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32,
587 cris_ver_v32p,
588 cris_reg_mode_jump_op},
590 {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE,
591 cris_ver_v32p,
592 cris_reg_mode_jump_op},
594 {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32,
595 cris_ver_v32p,
596 cris_reg_mode_jump_op},
598 {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE,
599 cris_ver_v8_10,
600 cris_reg_mode_jump_op},
602 {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32,
603 cris_ver_v8_10,
604 cris_none_reg_mode_jump_op},
606 {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE,
607 cris_ver_v8_10,
608 cris_none_reg_mode_jump_op},
610 {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE,
611 cris_ver_v8_10,
612 cris_reg_mode_jump_op},
614 {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32,
615 cris_ver_v8_10,
616 cris_none_reg_mode_jump_op},
618 {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE,
619 cris_ver_v8_10,
620 cris_none_reg_mode_jump_op},
622 {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE,
623 cris_ver_v8_10,
624 cris_reg_mode_jump_op},
626 {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32,
627 cris_ver_v8_10,
628 cris_none_reg_mode_jump_op},
630 {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE,
631 cris_ver_v8_10,
632 cris_none_reg_mode_jump_op},
634 {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0,
635 cris_reg_mode_jump_op},
637 {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32,
638 cris_ver_v0_10,
639 cris_none_reg_mode_jump_op},
641 {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32,
642 cris_ver_v32p,
643 cris_none_reg_mode_jump_op},
645 {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE,
646 cris_ver_v0_10,
647 cris_none_reg_mode_jump_op},
649 {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE,
650 cris_ver_v8_10,
651 cris_reg_mode_jump_op},
653 {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32,
654 cris_ver_v8_10,
655 cris_none_reg_mode_jump_op},
657 {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE,
658 cris_ver_v8_10,
659 cris_none_reg_mode_jump_op},
661 {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE,
662 cris_ver_v32p,
663 cris_reg_mode_jump_op},
665 {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32,
666 cris_ver_v32p,
667 cris_reg_mode_jump_op},
669 {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0,
670 cris_reg_mode_jump_op},
672 {"jump",
673 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32,
674 cris_ver_v0_10,
675 cris_none_reg_mode_jump_op},
677 {"jump",
678 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE,
679 cris_ver_v0_10,
680 cris_none_reg_mode_jump_op},
682 {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE,
683 cris_ver_v32p,
684 cris_none_reg_mode_jump_op},
686 {"jump",
687 JUMP_PC_INCR_OPCODE_V32,
688 (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32,
689 cris_ver_v32p,
690 cris_none_reg_mode_jump_op},
692 {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32,
693 cris_ver_v10,
694 cris_none_reg_mode_jump_op},
696 {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE,
697 cris_ver_v10,
698 cris_none_reg_mode_jump_op},
700 {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE,
701 cris_ver_v32p,
702 cris_not_implemented_op},
704 {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32,
705 cris_ver_v32p,
706 cris_not_implemented_op},
708 {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE,
709 cris_ver_v32p,
710 cris_addi_op},
712 {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0,
713 cris_dstep_logshift_mstep_neg_not_op},
715 {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0,
716 cris_dstep_logshift_mstep_neg_not_op},
718 {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0,
719 cris_dstep_logshift_mstep_neg_not_op},
721 {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0,
722 cris_dstep_logshift_mstep_neg_not_op},
724 {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE,
725 cris_ver_v3p,
726 cris_not_implemented_op},
728 {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE,
729 cris_ver_v32p,
730 cris_not_implemented_op},
732 {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0,
733 cris_reg_mode_add_sub_cmp_and_or_move_op},
735 {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
736 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
738 {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE,
739 cris_ver_v0_10,
740 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
742 {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0,
743 cris_move_to_preg_op},
745 {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0,
746 cris_reg_mode_move_from_preg_op},
748 {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0,
749 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
751 {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE,
752 cris_ver_v0_10,
753 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
755 {"move",
756 MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
757 "s,P", 0, SIZE_SPEC_REG, 0,
758 cris_move_to_preg_op},
760 {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE,
761 cris_ver_v0_10,
762 cris_move_to_preg_op},
764 {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0,
765 cris_none_reg_mode_move_from_preg_op},
767 {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE,
768 cris_ver_v0_10,
769 cris_none_reg_mode_move_from_preg_op},
771 {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE,
772 cris_ver_v32p,
773 cris_not_implemented_op},
775 {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE,
776 cris_ver_v32p,
777 cris_not_implemented_op},
779 {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0,
780 cris_move_reg_to_mem_movem_op},
782 {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE,
783 cris_ver_v0_10,
784 cris_move_reg_to_mem_movem_op},
786 {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0,
787 cris_move_mem_to_reg_movem_op},
789 {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE,
790 cris_ver_v0_10,
791 cris_move_mem_to_reg_movem_op},
793 {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0,
794 cris_quick_mode_and_cmp_move_or_op},
796 {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0,
797 cris_reg_mode_add_sub_cmp_and_or_move_op},
799 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
800 {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0,
801 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
803 {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE,
804 cris_ver_v0_10,
805 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
807 {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0,
808 cris_reg_mode_add_sub_cmp_and_or_move_op},
810 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
811 {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0,
812 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
814 {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE,
815 cris_ver_v0_10,
816 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
818 {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE,
819 cris_ver_v0_10,
820 cris_dstep_logshift_mstep_neg_not_op},
822 {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
823 cris_ver_v10p,
824 cris_muls_op},
826 {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE,
827 cris_ver_v10p,
828 cris_mulu_op},
830 {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0,
831 cris_dstep_logshift_mstep_neg_not_op},
833 {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE,
834 cris_ver_v0_10,
835 cris_btst_nop_op},
837 {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE,
838 cris_ver_v32p,
839 cris_btst_nop_op},
841 {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0,
842 cris_dstep_logshift_mstep_neg_not_op},
844 {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0,
845 cris_reg_mode_add_sub_cmp_and_or_move_op},
847 {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0,
848 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
850 {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE,
851 cris_ver_v0_10,
852 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
854 {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE,
855 cris_ver_v0_10,
856 cris_three_operand_add_sub_cmp_and_or_op},
858 {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0,
859 cris_quick_mode_and_cmp_move_or_op},
861 {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE,
862 cris_ver_v0_10,
863 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
865 {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE,
866 cris_ver_v0_10,
867 cris_none_reg_mode_move_from_preg_op},
869 {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE,
870 cris_ver_v0_10,
871 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
873 {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE,
874 cris_ver_v0_10,
875 cris_move_to_preg_op},
877 {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE,
878 cris_ver_v10,
879 cris_not_implemented_op},
881 {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE,
882 cris_ver_v10,
883 cris_not_implemented_op},
885 {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE,
886 cris_ver_v32p,
887 cris_not_implemented_op},
889 {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE,
890 cris_ver_v32p,
891 cris_not_implemented_op},
893 {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE,
894 cris_ver_v32p,
895 cris_not_implemented_op},
897 {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE,
898 cris_ver_v0_10,
899 cris_reg_mode_move_from_preg_op},
901 {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE,
902 cris_ver_v32p,
903 cris_reg_mode_move_from_preg_op},
905 {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE,
906 cris_ver_v0_10,
907 cris_reg_mode_move_from_preg_op},
909 {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE,
910 cris_ver_v32p,
911 cris_reg_mode_move_from_preg_op},
913 {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE,
914 cris_ver_v0_10,
915 cris_reg_mode_move_from_preg_op},
917 {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE,
918 cris_ver_v32p,
919 cris_reg_mode_move_from_preg_op},
921 {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE,
922 cris_ver_v10,
923 cris_not_implemented_op},
925 {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE,
926 cris_ver_v10,
927 cris_not_implemented_op},
929 {"sa",
930 0x0530+CC_A*0x1000,
931 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0,
932 cris_scc_op},
934 {"ssb",
935 0x0530+CC_EXT*0x1000,
936 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
937 cris_ver_v32p,
938 cris_scc_op},
940 {"scc",
941 0x0530+CC_CC*0x1000,
942 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0,
943 cris_scc_op},
945 {"scs",
946 0x0530+CC_CS*0x1000,
947 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0,
948 cris_scc_op},
950 {"seq",
951 0x0530+CC_EQ*0x1000,
952 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0,
953 cris_scc_op},
955 {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0,
956 cris_ax_ei_setf_op},
958 {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE,
959 cris_ver_v32p,
960 cris_not_implemented_op},
962 /* Need to have "swf" in front of "sext" so it is the one displayed in
963 disassembly. */
964 {"swf",
965 0x0530+CC_EXT*0x1000,
966 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
967 cris_ver_v10,
968 cris_scc_op},
970 {"sext",
971 0x0530+CC_EXT*0x1000,
972 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
973 cris_ver_v0_3,
974 cris_scc_op},
976 {"sge",
977 0x0530+CC_GE*0x1000,
978 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0,
979 cris_scc_op},
981 {"sgt",
982 0x0530+CC_GT*0x1000,
983 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0,
984 cris_scc_op},
986 {"shi",
987 0x0530+CC_HI*0x1000,
988 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0,
989 cris_scc_op},
991 {"shs",
992 0x0530+CC_HS*0x1000,
993 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0,
994 cris_scc_op},
996 {"sle",
997 0x0530+CC_LE*0x1000,
998 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0,
999 cris_scc_op},
1001 {"slo",
1002 0x0530+CC_LO*0x1000,
1003 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0,
1004 cris_scc_op},
1006 {"sls",
1007 0x0530+CC_LS*0x1000,
1008 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0,
1009 cris_scc_op},
1011 {"slt",
1012 0x0530+CC_LT*0x1000,
1013 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0,
1014 cris_scc_op},
1016 {"smi",
1017 0x0530+CC_MI*0x1000,
1018 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0,
1019 cris_scc_op},
1021 {"sne",
1022 0x0530+CC_NE*0x1000,
1023 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0,
1024 cris_scc_op},
1026 {"spl",
1027 0x0530+CC_PL*0x1000,
1028 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0,
1029 cris_scc_op},
1031 {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0,
1032 cris_reg_mode_add_sub_cmp_and_or_move_op},
1034 {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0,
1035 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1037 {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE,
1038 cris_ver_v0_10,
1039 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1041 {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE,
1042 cris_ver_v0_10,
1043 cris_three_operand_add_sub_cmp_and_or_op},
1045 {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0,
1046 cris_quick_mode_add_sub_op},
1048 {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0,
1049 cris_reg_mode_add_sub_cmp_and_or_move_op},
1051 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
1052 {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0,
1053 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1055 {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE,
1056 cris_ver_v0_10,
1057 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1059 {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE,
1060 cris_ver_v0_10,
1061 cris_three_operand_add_sub_cmp_and_or_op},
1063 {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0,
1064 cris_reg_mode_add_sub_cmp_and_or_move_op},
1066 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
1067 {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0,
1068 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1070 {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE,
1071 cris_ver_v0_10,
1072 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1074 {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE,
1075 cris_ver_v0_10,
1076 cris_three_operand_add_sub_cmp_and_or_op},
1078 {"svc",
1079 0x0530+CC_VC*0x1000,
1080 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0,
1081 cris_scc_op},
1083 {"svs",
1084 0x0530+CC_VS*0x1000,
1085 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0,
1086 cris_scc_op},
1088 /* The insn "swapn" is the same as "not" and will be disassembled as
1089 such, but the swap* family of mnmonics are generally v8-and-higher
1090 only, so count it in. */
1091 {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE,
1092 cris_ver_v8p,
1093 cris_not_implemented_op},
1095 {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE,
1096 cris_ver_v8p,
1097 cris_not_implemented_op},
1099 {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE,
1100 cris_ver_v8p,
1101 cris_not_implemented_op},
1103 {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE,
1104 cris_ver_v8p,
1105 cris_not_implemented_op},
1107 {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE,
1108 cris_ver_v8p,
1109 cris_not_implemented_op},
1111 {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE,
1112 cris_ver_v8p,
1113 cris_not_implemented_op},
1115 {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE,
1116 cris_ver_v8p,
1117 cris_not_implemented_op},
1119 {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE,
1120 cris_ver_v8p,
1121 cris_not_implemented_op},
1123 {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE,
1124 cris_ver_v8p,
1125 cris_not_implemented_op},
1127 {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE,
1128 cris_ver_v8p,
1129 cris_not_implemented_op},
1131 {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE,
1132 cris_ver_v8p,
1133 cris_not_implemented_op},
1135 {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE,
1136 cris_ver_v8p,
1137 cris_not_implemented_op},
1139 {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE,
1140 cris_ver_v8p,
1141 cris_not_implemented_op},
1143 {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE,
1144 cris_ver_v8p,
1145 cris_not_implemented_op},
1147 {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE,
1148 cris_ver_v8p,
1149 cris_not_implemented_op},
1151 {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE,
1152 cris_ver_v0_10,
1153 cris_reg_mode_test_op},
1155 {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0,
1156 cris_none_reg_mode_clear_test_op},
1158 {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE,
1159 cris_ver_v0_10,
1160 cris_none_reg_mode_clear_test_op},
1162 {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0,
1163 cris_xor_op},
1165 {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
1168 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
1169 const char * const
1170 cris_cc_strings[] =
1172 "hs",
1173 "lo",
1174 "ne",
1175 "eq",
1176 "vc",
1177 "vs",
1178 "pl",
1179 "mi",
1180 "ls",
1181 "hi",
1182 "ge",
1183 "lt",
1184 "gt",
1185 "le",
1186 "a",
1187 /* This is a placeholder. In v0, this would be "ext". In v32, this
1188 is "sb". See cris_conds15. */
1189 "wf"
1192 /* Different names and semantics for condition 1111 (0xf). */
1193 const struct cris_cond15 cris_cond15s[] =
1195 /* FIXME: In what version did condition "ext" disappear? */
1196 {"ext", cris_ver_v0_3},
1197 {"wf", cris_ver_v10},
1198 {"sb", cris_ver_v32p},
1199 {NULL, 0}
1204 * Local variables:
1205 * eval: (c-set-style "gnu")
1206 * indent-tabs-mode: t
1207 * End: