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[binutils.git] / opcodes / i386-opc.h
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1 /* Declarations for Intel 80386 opcode table
2 Copyright 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
22 #include "opcode/i386.h"
23 #ifdef HAVE_LIMITS_H
24 #include <limits.h>
25 #endif
27 #ifndef CHAR_BIT
28 #define CHAR_BIT 8
29 #endif
31 /* Position of cpu flags bitfiled. */
33 enum
35 /* i186 or better required */
36 Cpu186 = 0,
37 /* i286 or better required */
38 Cpu286,
39 /* i386 or better required */
40 Cpu386,
41 /* i486 or better required */
42 Cpu486,
43 /* i585 or better required */
44 Cpu586,
45 /* i686 or better required */
46 Cpu686,
47 /* CLFLUSH Instruction support required */
48 CpuClflush,
49 /* NOP Instruction support required */
50 CpuNop,
51 /* SYSCALL Instructions support required */
52 CpuSYSCALL,
53 /* Floating point support required */
54 Cpu8087,
55 /* i287 support required */
56 Cpu287,
57 /* i387 support required */
58 Cpu387,
59 /* i686 and floating point support required */
60 Cpu687,
61 /* SSE3 and floating point support required */
62 CpuFISTTP,
63 /* MMX support required */
64 CpuMMX,
65 /* SSE support required */
66 CpuSSE,
67 /* SSE2 support required */
68 CpuSSE2,
69 /* 3dnow! support required */
70 Cpu3dnow,
71 /* 3dnow! Extensions support required */
72 Cpu3dnowA,
73 /* SSE3 support required */
74 CpuSSE3,
75 /* VIA PadLock required */
76 CpuPadLock,
77 /* AMD Secure Virtual Machine Ext-s required */
78 CpuSVME,
79 /* VMX Instructions required */
80 CpuVMX,
81 /* SMX Instructions required */
82 CpuSMX,
83 /* SSSE3 support required */
84 CpuSSSE3,
85 /* SSE4a support required */
86 CpuSSE4a,
87 /* ABM New Instructions required */
88 CpuABM,
89 /* SSE4.1 support required */
90 CpuSSE4_1,
91 /* SSE4.2 support required */
92 CpuSSE4_2,
93 /* AVX support required */
94 CpuAVX,
95 /* Intel L1OM support required */
96 CpuL1OM,
97 /* Xsave/xrstor New Instructions support required */
98 CpuXsave,
99 /* Xsaveopt New Instructions support required */
100 CpuXsaveopt,
101 /* AES support required */
102 CpuAES,
103 /* PCLMUL support required */
104 CpuPCLMUL,
105 /* FMA support required */
106 CpuFMA,
107 /* FMA4 support required */
108 CpuFMA4,
109 /* XOP support required */
110 CpuXOP,
111 /* LWP support required */
112 CpuLWP,
113 /* MOVBE Instruction support required */
114 CpuMovbe,
115 /* EPT Instructions required */
116 CpuEPT,
117 /* RDTSCP Instruction support required */
118 CpuRdtscp,
119 /* FSGSBASE Instructions required */
120 CpuFSGSBase,
121 /* RDRND Instructions required */
122 CpuRdRnd,
123 /* F16C Instructions required */
124 CpuF16C,
125 /* 64bit support available, used by -march= in assembler. */
126 CpuLM,
127 /* 64bit support required */
128 Cpu64,
129 /* Not supported in the 64bit mode */
130 CpuNo64,
131 /* The last bitfield in i386_cpu_flags. */
132 CpuMax = CpuNo64
135 #define CpuNumOfUints \
136 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
137 #define CpuNumOfBits \
138 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
140 /* If you get a compiler error for zero width of the unused field,
141 comment it out. */
142 #define CpuUnused (CpuMax + 1)
144 /* We can check if an instruction is available with array instead
145 of bitfield. */
146 typedef union i386_cpu_flags
148 struct
150 unsigned int cpui186:1;
151 unsigned int cpui286:1;
152 unsigned int cpui386:1;
153 unsigned int cpui486:1;
154 unsigned int cpui586:1;
155 unsigned int cpui686:1;
156 unsigned int cpuclflush:1;
157 unsigned int cpunop:1;
158 unsigned int cpusyscall:1;
159 unsigned int cpu8087:1;
160 unsigned int cpu287:1;
161 unsigned int cpu387:1;
162 unsigned int cpu687:1;
163 unsigned int cpufisttp:1;
164 unsigned int cpummx:1;
165 unsigned int cpusse:1;
166 unsigned int cpusse2:1;
167 unsigned int cpua3dnow:1;
168 unsigned int cpua3dnowa:1;
169 unsigned int cpusse3:1;
170 unsigned int cpupadlock:1;
171 unsigned int cpusvme:1;
172 unsigned int cpuvmx:1;
173 unsigned int cpusmx:1;
174 unsigned int cpussse3:1;
175 unsigned int cpusse4a:1;
176 unsigned int cpuabm:1;
177 unsigned int cpusse4_1:1;
178 unsigned int cpusse4_2:1;
179 unsigned int cpuavx:1;
180 unsigned int cpul1om:1;
181 unsigned int cpuxsave:1;
182 unsigned int cpuxsaveopt:1;
183 unsigned int cpuaes:1;
184 unsigned int cpupclmul:1;
185 unsigned int cpufma:1;
186 unsigned int cpufma4:1;
187 unsigned int cpuxop:1;
188 unsigned int cpulwp:1;
189 unsigned int cpumovbe:1;
190 unsigned int cpuept:1;
191 unsigned int cpurdtscp:1;
192 unsigned int cpufsgsbase:1;
193 unsigned int cpurdrnd:1;
194 unsigned int cpuf16c:1;
195 unsigned int cpulm:1;
196 unsigned int cpu64:1;
197 unsigned int cpuno64:1;
198 #ifdef CpuUnused
199 unsigned int unused:(CpuNumOfBits - CpuUnused);
200 #endif
201 } bitfield;
202 unsigned int array[CpuNumOfUints];
203 } i386_cpu_flags;
205 /* Position of opcode_modifier bits. */
207 enum
209 /* has direction bit. */
210 D = 0,
211 /* set if operands can be words or dwords encoded the canonical way */
213 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
214 operand in encoding. */
216 /* insn has a modrm byte. */
217 Modrm,
218 /* register is in low 3 bits of opcode */
219 ShortForm,
220 /* special case for jump insns. */
221 Jump,
222 /* call and jump */
223 JumpDword,
224 /* loop and jecxz */
225 JumpByte,
226 /* special case for intersegment leaps/calls */
227 JumpInterSegment,
228 /* FP insn memory format bit, sized by 0x4 */
229 FloatMF,
230 /* src/dest swap for floats. */
231 FloatR,
232 /* has float insn direction bit. */
233 FloatD,
234 /* needs size prefix if in 32-bit mode */
235 Size16,
236 /* needs size prefix if in 16-bit mode */
237 Size32,
238 /* needs size prefix if in 64-bit mode */
239 Size64,
240 /* instruction ignores operand size prefix and in Intel mode ignores
241 mnemonic size suffix check. */
242 IgnoreSize,
243 /* default insn size depends on mode */
244 DefaultSize,
245 /* b suffix on instruction illegal */
246 No_bSuf,
247 /* w suffix on instruction illegal */
248 No_wSuf,
249 /* l suffix on instruction illegal */
250 No_lSuf,
251 /* s suffix on instruction illegal */
252 No_sSuf,
253 /* q suffix on instruction illegal */
254 No_qSuf,
255 /* long double suffix on instruction illegal */
256 No_ldSuf,
257 /* instruction needs FWAIT */
258 FWait,
259 /* quick test for string instructions */
260 IsString,
261 /* quick test for lockable instructions */
262 IsLockable,
263 /* fake an extra reg operand for clr, imul and special register
264 processing for some instructions. */
265 RegKludge,
266 /* The first operand must be xmm0 */
267 FirstXmm0,
268 /* An implicit xmm0 as the first operand */
269 Implicit1stXmm0,
270 /* Convert to DWORD */
271 ToDword,
272 /* Convert to QWORD */
273 ToQword,
274 /* Address prefix changes operand 0 */
275 AddrPrefixOp0,
276 /* opcode is a prefix */
277 IsPrefix,
278 /* instruction has extension in 8 bit imm */
279 ImmExt,
280 /* instruction don't need Rex64 prefix. */
281 NoRex64,
282 /* instruction require Rex64 prefix. */
283 Rex64,
284 /* deprecated fp insn, gets a warning */
285 Ugh,
286 /* insn has VEX prefix:
287 1: 128bit VEX prefix.
288 2: 256bit VEX prefix.
289 3: Scalar VEX prefix.
291 #define VEX128 1
292 #define VEX256 2
293 #define VEXScalar 3
294 Vex,
295 /* How to encode VEX.vvvv:
296 0: VEX.vvvv must be 1111b.
297 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
298 the content of source registers will be preserved.
299 VEX.DDS. The second register operand is encoded in VEX.vvvv
300 where the content of first source register will be overwritten
301 by the result.
302 For assembler, there are no difference between VEX.NDS and
303 VEX.DDS.
304 2. VEX.NDD. Register destination is encoded in VEX.vvvv.
305 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
306 of the operands can access a memory location.
308 #define VEXXDS 1
309 #define VEXNDD 2
310 #define VEXLWP 3
311 VexVVVV,
312 /* How the VEX.W bit is used:
313 0: Set by the REX.W bit.
314 1: VEX.W0. Should always be 0.
315 2: VEX.W1. Should always be 1.
317 #define VEXW0 1
318 #define VEXW1 2
319 VexW,
320 /* VEX opcode prefix:
321 0: VEX 0x0F opcode prefix.
322 1: VEX 0x0F38 opcode prefix.
323 2: VEX 0x0F3A opcode prefix
324 3: XOP 0x08 opcode prefix.
325 4: XOP 0x09 opcode prefix
326 5: XOP 0x0A opcode prefix.
328 #define VEX0F 0
329 #define VEX0F38 1
330 #define VEX0F3A 2
331 #define XOP08 3
332 #define XOP09 4
333 #define XOP0A 5
334 VexOpcode,
335 /* number of VEX source operands:
336 0: <= 2 source operands.
337 1: 2 XOP source operands.
338 2: 3 source operands.
340 #define XOP2SOURCES 1
341 #define VEX3SOURCES 2
342 VexSources,
343 /* instruction has VEX 8 bit imm */
344 VexImmExt,
345 /* SSE to AVX support required */
346 SSE2AVX,
347 /* No AVX equivalent */
348 NoAVX,
349 /* Compatible with old (<= 2.8.1) versions of gcc */
350 OldGcc,
351 /* AT&T mnemonic. */
352 ATTMnemonic,
353 /* AT&T syntax. */
354 ATTSyntax,
355 /* Intel syntax. */
356 IntelSyntax,
357 /* The last bitfield in i386_opcode_modifier. */
358 Opcode_Modifier_Max
361 typedef struct i386_opcode_modifier
363 unsigned int d:1;
364 unsigned int w:1;
365 unsigned int s:1;
366 unsigned int modrm:1;
367 unsigned int shortform:1;
368 unsigned int jump:1;
369 unsigned int jumpdword:1;
370 unsigned int jumpbyte:1;
371 unsigned int jumpintersegment:1;
372 unsigned int floatmf:1;
373 unsigned int floatr:1;
374 unsigned int floatd:1;
375 unsigned int size16:1;
376 unsigned int size32:1;
377 unsigned int size64:1;
378 unsigned int ignoresize:1;
379 unsigned int defaultsize:1;
380 unsigned int no_bsuf:1;
381 unsigned int no_wsuf:1;
382 unsigned int no_lsuf:1;
383 unsigned int no_ssuf:1;
384 unsigned int no_qsuf:1;
385 unsigned int no_ldsuf:1;
386 unsigned int fwait:1;
387 unsigned int isstring:1;
388 unsigned int islockable:1;
389 unsigned int regkludge:1;
390 unsigned int firstxmm0:1;
391 unsigned int implicit1stxmm0:1;
392 unsigned int todword:1;
393 unsigned int toqword:1;
394 unsigned int addrprefixop0:1;
395 unsigned int isprefix:1;
396 unsigned int immext:1;
397 unsigned int norex64:1;
398 unsigned int rex64:1;
399 unsigned int ugh:1;
400 unsigned int vex:2;
401 unsigned int vexvvvv:2;
402 unsigned int vexw:2;
403 unsigned int vexopcode:3;
404 unsigned int vexsources:2;
405 unsigned int veximmext:1;
406 unsigned int sse2avx:1;
407 unsigned int noavx:1;
408 unsigned int oldgcc:1;
409 unsigned int attmnemonic:1;
410 unsigned int attsyntax:1;
411 unsigned int intelsyntax:1;
412 } i386_opcode_modifier;
414 /* Position of operand_type bits. */
416 enum
418 /* 8bit register */
419 Reg8 = 0,
420 /* 16bit register */
421 Reg16,
422 /* 32bit register */
423 Reg32,
424 /* 64bit register */
425 Reg64,
426 /* Floating pointer stack register */
427 FloatReg,
428 /* MMX register */
429 RegMMX,
430 /* SSE register */
431 RegXMM,
432 /* AVX registers */
433 RegYMM,
434 /* Control register */
435 Control,
436 /* Debug register */
437 Debug,
438 /* Test register */
439 Test,
440 /* 2 bit segment register */
441 SReg2,
442 /* 3 bit segment register */
443 SReg3,
444 /* 1 bit immediate */
445 Imm1,
446 /* 8 bit immediate */
447 Imm8,
448 /* 8 bit immediate sign extended */
449 Imm8S,
450 /* 16 bit immediate */
451 Imm16,
452 /* 32 bit immediate */
453 Imm32,
454 /* 32 bit immediate sign extended */
455 Imm32S,
456 /* 64 bit immediate */
457 Imm64,
458 /* 8bit/16bit/32bit displacements are used in different ways,
459 depending on the instruction. For jumps, they specify the
460 size of the PC relative displacement, for instructions with
461 memory operand, they specify the size of the offset relative
462 to the base register, and for instructions with memory offset
463 such as `mov 1234,%al' they specify the size of the offset
464 relative to the segment base. */
465 /* 8 bit displacement */
466 Disp8,
467 /* 16 bit displacement */
468 Disp16,
469 /* 32 bit displacement */
470 Disp32,
471 /* 32 bit signed displacement */
472 Disp32S,
473 /* 64 bit displacement */
474 Disp64,
475 /* Accumulator %al/%ax/%eax/%rax */
476 Acc,
477 /* Floating pointer top stack register %st(0) */
478 FloatAcc,
479 /* Register which can be used for base or index in memory operand. */
480 BaseIndex,
481 /* Register to hold in/out port addr = dx */
482 InOutPortReg,
483 /* Register to hold shift count = cl */
484 ShiftCount,
485 /* Absolute address for jump. */
486 JumpAbsolute,
487 /* String insn operand with fixed es segment */
488 EsSeg,
489 /* RegMem is for instructions with a modrm byte where the register
490 destination operand should be encoded in the mod and regmem fields.
491 Normally, it will be encoded in the reg field. We add a RegMem
492 flag to the destination register operand to indicate that it should
493 be encoded in the regmem field. */
494 RegMem,
495 /* Memory. */
496 Mem,
497 /* BYTE memory. */
498 Byte,
499 /* WORD memory. 2 byte */
500 Word,
501 /* DWORD memory. 4 byte */
502 Dword,
503 /* FWORD memory. 6 byte */
504 Fword,
505 /* QWORD memory. 8 byte */
506 Qword,
507 /* TBYTE memory. 10 byte */
508 Tbyte,
509 /* XMMWORD memory. */
510 Xmmword,
511 /* YMMWORD memory. */
512 Ymmword,
513 /* Unspecified memory size. */
514 Unspecified,
515 /* Any memory size. */
516 Anysize,
518 /* Vector 4 bit immediate. */
519 Vec_Imm4,
521 /* The last bitfield in i386_operand_type. */
522 OTMax
525 #define OTNumOfUints \
526 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
527 #define OTNumOfBits \
528 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
530 /* If you get a compiler error for zero width of the unused field,
531 comment it out. */
532 #define OTUnused (OTMax + 1)
534 typedef union i386_operand_type
536 struct
538 unsigned int reg8:1;
539 unsigned int reg16:1;
540 unsigned int reg32:1;
541 unsigned int reg64:1;
542 unsigned int floatreg:1;
543 unsigned int regmmx:1;
544 unsigned int regxmm:1;
545 unsigned int regymm:1;
546 unsigned int control:1;
547 unsigned int debug:1;
548 unsigned int test:1;
549 unsigned int sreg2:1;
550 unsigned int sreg3:1;
551 unsigned int imm1:1;
552 unsigned int imm8:1;
553 unsigned int imm8s:1;
554 unsigned int imm16:1;
555 unsigned int imm32:1;
556 unsigned int imm32s:1;
557 unsigned int imm64:1;
558 unsigned int disp8:1;
559 unsigned int disp16:1;
560 unsigned int disp32:1;
561 unsigned int disp32s:1;
562 unsigned int disp64:1;
563 unsigned int acc:1;
564 unsigned int floatacc:1;
565 unsigned int baseindex:1;
566 unsigned int inoutportreg:1;
567 unsigned int shiftcount:1;
568 unsigned int jumpabsolute:1;
569 unsigned int esseg:1;
570 unsigned int regmem:1;
571 unsigned int mem:1;
572 unsigned int byte:1;
573 unsigned int word:1;
574 unsigned int dword:1;
575 unsigned int fword:1;
576 unsigned int qword:1;
577 unsigned int tbyte:1;
578 unsigned int xmmword:1;
579 unsigned int ymmword:1;
580 unsigned int unspecified:1;
581 unsigned int anysize:1;
582 unsigned int vec_imm4:1;
583 #ifdef OTUnused
584 unsigned int unused:(OTNumOfBits - OTUnused);
585 #endif
586 } bitfield;
587 unsigned int array[OTNumOfUints];
588 } i386_operand_type;
590 typedef struct insn_template
592 /* instruction name sans width suffix ("mov" for movl insns) */
593 char *name;
595 /* how many operands */
596 unsigned int operands;
598 /* base_opcode is the fundamental opcode byte without optional
599 prefix(es). */
600 unsigned int base_opcode;
601 #define Opcode_D 0x2 /* Direction bit:
602 set if Reg --> Regmem;
603 unset if Regmem --> Reg. */
604 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
605 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
607 /* extension_opcode is the 3 bit extension for group <n> insns.
608 This field is also used to store the 8-bit opcode suffix for the
609 AMD 3DNow! instructions.
610 If this template has no extension opcode (the usual case) use None
611 Instructions */
612 unsigned int extension_opcode;
613 #define None 0xffff /* If no extension_opcode is possible. */
615 /* Opcode length. */
616 unsigned char opcode_length;
618 /* cpu feature flags */
619 i386_cpu_flags cpu_flags;
621 /* the bits in opcode_modifier are used to generate the final opcode from
622 the base_opcode. These bits also are used to detect alternate forms of
623 the same instruction */
624 i386_opcode_modifier opcode_modifier;
626 /* operand_types[i] describes the type of operand i. This is made
627 by OR'ing together all of the possible type masks. (e.g.
628 'operand_types[i] = Reg|Imm' specifies that operand i can be
629 either a register or an immediate operand. */
630 i386_operand_type operand_types[MAX_OPERANDS];
632 insn_template;
634 extern const insn_template i386_optab[];
636 /* these are for register name --> number & type hash lookup */
637 typedef struct
639 char *reg_name;
640 i386_operand_type reg_type;
641 unsigned char reg_flags;
642 #define RegRex 0x1 /* Extended register. */
643 #define RegRex64 0x2 /* Extended 8 bit register. */
644 unsigned char reg_num;
645 #define RegRip ((unsigned char ) ~0)
646 #define RegEip (RegRip - 1)
647 /* EIZ and RIZ are fake index registers. */
648 #define RegEiz (RegEip - 1)
649 #define RegRiz (RegEiz - 1)
650 /* FLAT is a fake segment register (Intel mode). */
651 #define RegFlat ((unsigned char) ~0)
652 signed char dw2_regnum[2];
653 #define Dw2Inval (-1)
655 reg_entry;
657 /* Entries in i386_regtab. */
658 #define REGNAM_AL 1
659 #define REGNAM_AX 25
660 #define REGNAM_EAX 41
662 extern const reg_entry i386_regtab[];
663 extern const unsigned int i386_regtab_size;
665 typedef struct
667 char *seg_name;
668 unsigned int seg_prefix;
670 seg_entry;
672 extern const seg_entry cs;
673 extern const seg_entry ds;
674 extern const seg_entry ss;
675 extern const seg_entry es;
676 extern const seg_entry fs;
677 extern const seg_entry gs;