Add tests of conditional branch instructions with probability postfixes
[binutils.git] / gas / testsuite / gas / ppc / astest2.d
blobf46a1e194c5251a13f0ae7ae310e0ab6665b5c01
1 #objdump: -Dr
2 #name: PowerPC test 2
4 .*: +file format elf32-powerpc
6 Disassembly of section \.text:
8 0+0000000 <foo>:
9 0: 60 00 00 00 nop
10 4: 60 00 00 00 nop
11 8: 60 00 00 00 nop
12 c: 48 00 00 04 b 10 <foo\+0x10>
13 10: 48 00 00 08 b 18 <foo\+0x18>
14 14: 48 00 00 00 b 14 <foo\+0x14>
15 14: R_PPC_REL24 x
16 18: 48 00 00 04 b 1c <foo\+0x1c>
17 18: R_PPC_REL24 \.data\+0x4
18 1c: 48 00 00 00 b 1c <foo\+0x1c>
19 1c: R_PPC_REL24 z
20 20: 48 00 00 14 b 34 <foo\+0x34>
21 20: R_PPC_REL24 z\+0x14
22 24: 48 00 00 04 b 28 <foo\+0x28>
23 28: 48 00 00 00 b 28 <foo\+0x28>
24 28: R_PPC_REL24 a
25 2c: 48 00 00 50 b 7c <apfour>
26 30: 48 00 00 04 b 34 <foo\+0x34>
27 30: R_PPC_REL24 a\+0x4
28 34: 48 00 00 4c b 80 <apfour\+0x4>
29 38: 48 00 00 00 b 38 <foo\+0x38>
30 38: R_PPC_LOCAL24PC a
31 3c: 48 00 00 40 b 7c <apfour>
33 40: 00 00 00 40 \.long 0x40
34 40: R_PPC_ADDR32 \.text\+0x40
36 44: 00 00 00 4c \.long 0x4c
37 44: R_PPC_ADDR32 \.text\+0x4c
38 48: 00 00 00 00 \.long 0x0
39 48: R_PPC_REL32 x
40 4c: 00 00 00 04 \.long 0x4
41 4c: R_PPC_REL32 x\+0x4
42 \.\.\.
43 50: R_PPC_REL32 z
44 54: R_PPC_REL32 y
45 58: R_PPC_ADDR32 x
46 5c: R_PPC_ADDR32 y
47 60: R_PPC_ADDR32 z
48 64: ff ff ff fc fnmsub f31,f31,f31,f31
49 64: R_PPC_ADDR32 x\+0xf+ffffffc
50 68: ff ff ff fc fnmsub f31,f31,f31,f31
51 68: R_PPC_ADDR32 y\+0xf+ffffffc
52 6c: ff ff ff fc fnmsub f31,f31,f31,f31
53 6c: R_PPC_ADDR32 z\+0xf+ffffffc
54 70: 00 00 00 08 \.long 0x8
55 74: 00 00 00 08 \.long 0x8
57 0+0000078 <a>:
58 78: 00 00 00 00 \.long 0x0
59 78: R_PPC_ADDR32 a
61 0+000007c <apfour>:
62 \.\.\.
63 7c: R_PPC_ADDR32 b
64 80: R_PPC_ADDR32 apfour
65 84: ff ff ff fc fnmsub f31,f31,f31,f31
66 88: 00 00 00 02 \.long 0x2
67 88: R_PPC_ADDR32 apfour\+0x2
68 8c: 00 00 00 00 \.long 0x0
69 90: 60 00 00 00 nop
70 94: 40 a5 ff fc ble- cr1,90 <apfour\+0x14>
71 98: 41 a9 ff f8 bgt- cr2,90 <apfour\+0x14>
72 9c: 40 8d ff f4 ble\+ cr3,90 <apfour\+0x14>
73 a0: 41 91 ff f0 bgt\+ cr4,90 <apfour\+0x14>
74 a4: 40 95 00 10 ble- cr5,b4 <nop>
75 a8: 41 99 00 0c bgt- cr6,b4 <nop>
76 ac: 40 bd 00 08 ble\+ cr7,b4 <nop>
77 b0: 41 a1 00 04 bgt\+ b4 <nop>
78 Disassembly of section \.data:
80 0+0000000 <x>:
81 0: 00 00 00 00 \.long 0x0
83 0+0000004 <y>:
84 4: 00 00 00 00 \.long 0x0