opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int, int);
  59 static void OP_E_extended (int, int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_EX_Vex (int, int);
  97 static void OP_XMM_Vex (int, int);
  98 static void OP_REG_VexI4 (int, int);
  99 static void PCLMUL_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void CMPXCHG8B_Fixup (int, int);
 112 static void XMM_Fixup (int, int);
 113 static void CRC32_Fixup (int, int);
 114 static void print_drex_arg (unsigned int, int, int);
 115 static void OP_DREX4 (int, int);
 116 static void OP_DREX3 (int, int);
 117 static void OP_DREX_ICMP (int, int);
 118 static void OP_DREX_FCMP (int, int);
 119 static void MOVBE_Fixup (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   jmp_buf bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Original REX prefix.  */
 147 static int rex_original;
 148 /* REX bits in original REX prefix ignored.  It may not be the same
 149    as rex_original since some bits may not be ignored.  */
 150 static int rex_ignored;
 151 /* Mark parts used in the REX prefix.  When we are testing for
 152    empty prefix (for 8bit register REX extension), just mask it
 153    out.  Otherwise test for REX bit is excuse for existence of REX
 154    only in case value is nonzero.  */
 155 #define USED_REX(value)                                 \
 156   {                                                     \
 157     if (value)                                          \
 158       {                                                 \
 159         if ((rex & value))                              \
 160           rex_used |= (value) | REX_OPCODE;             \
 161       }                                                 \
 162     else                                                \
 163       rex_used |= REX_OPCODE;                           \
 164   }
 165
 166 /* Special 'registers' for DREX handling */
 167 #define DREX_REG_UNKNOWN        1000    /* not initialized */
 168 #define DREX_REG_MEMORY         1001    /* use MODRM/SIB/OFFSET memory */
 169
 170 /* The DREX byte has the following fields:
 171    Bits 7-4 -- DREX.Dest, xmm destination register
 172    Bit 3    -- DREX.OC0, operand config bit defines operand order
 173    Bit 2    -- DREX.R, equivalent to REX_R bit, to extend ModRM register
 174    Bit 1    -- DREX.X, equivalent to REX_X bit, to extend SIB index field
 175    Bit 0    -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
 176                SIB base field, or opcode reg field.  */
 177 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
 178 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
 179
 180 /* Flags for prefixes which we somehow handled when printing the
 181    current instruction.  */
 182 static int used_prefixes;
 183
 184 /* Flags stored in PREFIXES.  */
 185 #define PREFIX_REPZ 1
 186 #define PREFIX_REPNZ 2
 187 #define PREFIX_LOCK 4
 188 #define PREFIX_CS 8
 189 #define PREFIX_SS 0x10
 190 #define PREFIX_DS 0x20
 191 #define PREFIX_ES 0x40
 192 #define PREFIX_FS 0x80
 193 #define PREFIX_GS 0x100
 194 #define PREFIX_DATA 0x200
 195 #define PREFIX_ADDR 0x400
 196 #define PREFIX_FWAIT 0x800
 197
 198 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 199    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 200    on error.  */
 201 #define FETCH_DATA(info, addr) \
 202   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 203    ? 1 : fetch_data ((info), (addr)))
 204
 205 static int
 206 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 207 {
 208   int status;
 209   struct dis_private *priv = (struct dis_private *) info->private_data;
 210   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 211
 212   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 213     status = (*info->read_memory_func) (start,
 214                                         priv->max_fetched,
 215                                         addr - priv->max_fetched,
 216                                         info);
 217   else
 218     status = -1;
 219   if (status != 0)
 220     {
 221       /* If we did manage to read at least one byte, then
 222          print_insn_i386 will do something sensible.  Otherwise, print
 223          an error.  We do that here because this is where we know
 224          STATUS.  */
 225       if (priv->max_fetched == priv->the_buffer)
 226         (*info->memory_error_func) (status, start, info);
 227       longjmp (priv->bailout, 1);
 228     }
 229   else
 230     priv->max_fetched = addr;
 231   return 1;
 232 }
 233
 234 #define XX { NULL, 0 }
 235
 236 #define Eb { OP_E, b_mode }
 237 #define EbS { OP_E, b_swap_mode }
 238 #define Ev { OP_E, v_mode }
 239 #define EvS { OP_E, v_swap_mode }
 240 #define Ed { OP_E, d_mode }
 241 #define Edq { OP_E, dq_mode }
 242 #define Edqw { OP_E, dqw_mode }
 243 #define Edqb { OP_E, dqb_mode }
 244 #define Edqd { OP_E, dqd_mode }
 245 #define Eq { OP_E, q_mode }
 246 #define indirEv { OP_indirE, stack_v_mode }
 247 #define indirEp { OP_indirE, f_mode }
 248 #define stackEv { OP_E, stack_v_mode }
 249 #define Em { OP_E, m_mode }
 250 #define Ew { OP_E, w_mode }
 251 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 252 #define Ma { OP_M, a_mode }
 253 #define Mb { OP_M, b_mode }
 254 #define Md { OP_M, d_mode }
 255 #define Mo { OP_M, o_mode }
 256 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 257 #define Mq { OP_M, q_mode }
 258 #define Mx { OP_M, x_mode }
 259 #define Mxmm { OP_M, xmm_mode }
 260 #define Gb { OP_G, b_mode }
 261 #define Gv { OP_G, v_mode }
 262 #define Gd { OP_G, d_mode }
 263 #define Gdq { OP_G, dq_mode }
 264 #define Gm { OP_G, m_mode }
 265 #define Gw { OP_G, w_mode }
 266 #define Rd { OP_R, d_mode }
 267 #define Rm { OP_R, m_mode }
 268 #define Ib { OP_I, b_mode }
 269 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 270 #define Iv { OP_I, v_mode }
 271 #define Iq { OP_I, q_mode }
 272 #define Iv64 { OP_I64, v_mode }
 273 #define Iw { OP_I, w_mode }
 274 #define I1 { OP_I, const_1_mode }
 275 #define Jb { OP_J, b_mode }
 276 #define Jv { OP_J, v_mode }
 277 #define Cm { OP_C, m_mode }
 278 #define Dm { OP_D, m_mode }
 279 #define Td { OP_T, d_mode }
 280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 281
 282 #define RMeAX { OP_REG, eAX_reg }
 283 #define RMeBX { OP_REG, eBX_reg }
 284 #define RMeCX { OP_REG, eCX_reg }
 285 #define RMeDX { OP_REG, eDX_reg }
 286 #define RMeSP { OP_REG, eSP_reg }
 287 #define RMeBP { OP_REG, eBP_reg }
 288 #define RMeSI { OP_REG, eSI_reg }
 289 #define RMeDI { OP_REG, eDI_reg }
 290 #define RMrAX { OP_REG, rAX_reg }
 291 #define RMrBX { OP_REG, rBX_reg }
 292 #define RMrCX { OP_REG, rCX_reg }
 293 #define RMrDX { OP_REG, rDX_reg }
 294 #define RMrSP { OP_REG, rSP_reg }
 295 #define RMrBP { OP_REG, rBP_reg }
 296 #define RMrSI { OP_REG, rSI_reg }
 297 #define RMrDI { OP_REG, rDI_reg }
 298 #define RMAL { OP_REG, al_reg }
 299 #define RMAL { OP_REG, al_reg }
 300 #define RMCL { OP_REG, cl_reg }
 301 #define RMDL { OP_REG, dl_reg }
 302 #define RMBL { OP_REG, bl_reg }
 303 #define RMAH { OP_REG, ah_reg }
 304 #define RMCH { OP_REG, ch_reg }
 305 #define RMDH { OP_REG, dh_reg }
 306 #define RMBH { OP_REG, bh_reg }
 307 #define RMAX { OP_REG, ax_reg }
 308 #define RMDX { OP_REG, dx_reg }
 309
 310 #define eAX { OP_IMREG, eAX_reg }
 311 #define eBX { OP_IMREG, eBX_reg }
 312 #define eCX { OP_IMREG, eCX_reg }
 313 #define eDX { OP_IMREG, eDX_reg }
 314 #define eSP { OP_IMREG, eSP_reg }
 315 #define eBP { OP_IMREG, eBP_reg }
 316 #define eSI { OP_IMREG, eSI_reg }
 317 #define eDI { OP_IMREG, eDI_reg }
 318 #define AL { OP_IMREG, al_reg }
 319 #define CL { OP_IMREG, cl_reg }
 320 #define DL { OP_IMREG, dl_reg }
 321 #define BL { OP_IMREG, bl_reg }
 322 #define AH { OP_IMREG, ah_reg }
 323 #define CH { OP_IMREG, ch_reg }
 324 #define DH { OP_IMREG, dh_reg }
 325 #define BH { OP_IMREG, bh_reg }
 326 #define AX { OP_IMREG, ax_reg }
 327 #define DX { OP_IMREG, dx_reg }
 328 #define zAX { OP_IMREG, z_mode_ax_reg }
 329 #define indirDX { OP_IMREG, indir_dx_reg }
 330
 331 #define Sw { OP_SEG, w_mode }
 332 #define Sv { OP_SEG, v_mode }
 333 #define Ap { OP_DIR, 0 }
 334 #define Ob { OP_OFF64, b_mode }
 335 #define Ov { OP_OFF64, v_mode }
 336 #define Xb { OP_DSreg, eSI_reg }
 337 #define Xv { OP_DSreg, eSI_reg }
 338 #define Xz { OP_DSreg, eSI_reg }
 339 #define Yb { OP_ESreg, eDI_reg }
 340 #define Yv { OP_ESreg, eDI_reg }
 341 #define DSBX { OP_DSreg, eBX_reg }
 342
 343 #define es { OP_REG, es_reg }
 344 #define ss { OP_REG, ss_reg }
 345 #define cs { OP_REG, cs_reg }
 346 #define ds { OP_REG, ds_reg }
 347 #define fs { OP_REG, fs_reg }
 348 #define gs { OP_REG, gs_reg }
 349
 350 #define MX { OP_MMX, 0 }
 351 #define XM { OP_XMM, 0 }
 352 #define XMM { OP_XMM, xmm_mode }
 353 #define EM { OP_EM, v_mode }
 354 #define EMS { OP_EM, v_swap_mode }
 355 #define EMd { OP_EM, d_mode }
 356 #define EMx { OP_EM, x_mode }
 357 #define EXw { OP_EX, w_mode }
 358 #define EXd { OP_EX, d_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXq { OP_EX, q_mode }
 361 #define EXqS { OP_EX, q_swap_mode }
 362 #define EXx { OP_EX, x_mode }
 363 #define EXxS { OP_EX, x_swap_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXxmmq { OP_EX, xmmq_mode }
 366 #define EXymmq { OP_EX, ymmq_mode }
 367 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 368 #define MS { OP_MS, v_mode }
 369 #define XS { OP_XS, v_mode }
 370 #define EMCq { OP_EMC, q_mode }
 371 #define MXC { OP_MXC, 0 }
 372 #define OPSUF { OP_3DNowSuffix, 0 }
 373 #define CMP { CMP_Fixup, 0 }
 374 #define XMM0 { XMM_Fixup, 0 }
 375
 376 #define Vex { OP_VEX, vex_mode }
 377 #define Vex128 { OP_VEX, vex128_mode }
 378 #define Vex256 { OP_VEX, vex256_mode }
 379 #define EXdVex { OP_EX_Vex, d_mode }
 380 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 381 #define EXqVex { OP_EX_Vex, q_mode }
 382 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 383 #define XMVex { OP_XMM_Vex, 0 }
 384 #define XMVexI4 { OP_REG_VexI4, x_mode }
 385 #define PCLMUL { PCLMUL_Fixup, 0 }
 386 #define VZERO { VZERO_Fixup, 0 }
 387 #define VCMP { VCMP_Fixup, 0 }
 388
 389 /* Used handle "rep" prefix for string instructions.  */
 390 #define Xbr { REP_Fixup, eSI_reg }
 391 #define Xvr { REP_Fixup, eSI_reg }
 392 #define Ybr { REP_Fixup, eDI_reg }
 393 #define Yvr { REP_Fixup, eDI_reg }
 394 #define Yzr { REP_Fixup, eDI_reg }
 395 #define indirDXr { REP_Fixup, indir_dx_reg }
 396 #define ALr { REP_Fixup, al_reg }
 397 #define eAXr { REP_Fixup, eAX_reg }
 398
 399 #define cond_jump_flag { NULL, cond_jump_mode }
 400 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 401
 402 /* bits in sizeflag */
 403 #define SUFFIX_ALWAYS 4
 404 #define AFLAG 2
 405 #define DFLAG 1
 406
 407 /* byte operand */
 408 #define b_mode                  1
 409 /* byte operand with operand swapped */
 410 #define b_swap_mode             (b_mode + 1)
 411 /* operand size depends on prefixes */
 412 #define v_mode                  (b_swap_mode + 1)
 413 /* operand size depends on prefixes with operand swapped */
 414 #define v_swap_mode             (v_mode + 1)
 415 /* word operand */
 416 #define w_mode                  (v_swap_mode + 1)
 417 /* double word operand  */
 418 #define d_mode                  (w_mode + 1)
 419 /* double word operand with operand swapped */
 420 #define d_swap_mode             (d_mode + 1)
 421 /* quad word operand */
 422 #define q_mode                  (d_swap_mode + 1)
 423 /* quad word operand with operand swapped */
 424 #define q_swap_mode             (q_mode + 1)
 425 /* ten-byte operand */
 426 #define t_mode                  (q_swap_mode + 1)
 427 /* 16-byte XMM or 32-byte YMM operand */
 428 #define x_mode                  (t_mode + 1)
 429 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 430 #define x_swap_mode             (x_mode + 1)
 431 /* 16-byte XMM operand */
 432 #define xmm_mode                (x_swap_mode + 1)
 433 /* 16-byte XMM or quad word operand */
 434 #define xmmq_mode               (xmm_mode + 1)
 435 /* 32-byte YMM or quad word operand */
 436 #define ymmq_mode               (xmmq_mode + 1)
 437 /* d_mode in 32bit, q_mode in 64bit mode.  */
 438 #define m_mode                  (ymmq_mode + 1)
 439 /* pair of v_mode operands */
 440 #define a_mode                  (m_mode + 1)
 441 #define cond_jump_mode          (a_mode + 1)
 442 #define loop_jcxz_mode          (cond_jump_mode + 1)
 443 /* operand size depends on REX prefixes.  */
 444 #define dq_mode                 (loop_jcxz_mode + 1)
 445 /* registers like dq_mode, memory like w_mode.  */
 446 #define dqw_mode                (dq_mode + 1)
 447 /* 4- or 6-byte pointer operand */
 448 #define f_mode                  (dqw_mode + 1)
 449 #define const_1_mode            (f_mode + 1)
 450 /* v_mode for stack-related opcodes.  */
 451 #define stack_v_mode            (const_1_mode + 1)
 452 /* non-quad operand size depends on prefixes */
 453 #define z_mode                  (stack_v_mode + 1)
 454 /* 16-byte operand */
 455 #define o_mode                  (z_mode + 1)
 456 /* registers like dq_mode, memory like b_mode.  */
 457 #define dqb_mode                (o_mode + 1)
 458 /* registers like dq_mode, memory like d_mode.  */
 459 #define dqd_mode                (dqb_mode + 1)
 460 /* normal vex mode */
 461 #define vex_mode                (dqd_mode + 1)
 462 /* 128bit vex mode */
 463 #define vex128_mode             (vex_mode + 1)
 464 /* 256bit vex mode */
 465 #define vex256_mode             (vex128_mode + 1)
 466 /* operand size depends on the VEX.W bit.  */
 467 #define vex_w_dq_mode           (vex256_mode + 1)
 468
 469 #define es_reg                  (vex_w_dq_mode + 1)
 470 #define cs_reg                  (es_reg + 1)
 471 #define ss_reg                  (cs_reg + 1)
 472 #define ds_reg                  (ss_reg + 1)
 473 #define fs_reg                  (ds_reg + 1)
 474 #define gs_reg                  (fs_reg + 1)
 475
 476 #define eAX_reg                 (gs_reg + 1)
 477 #define eCX_reg                 (eAX_reg + 1)
 478 #define eDX_reg                 (eCX_reg + 1)
 479 #define eBX_reg                 (eDX_reg + 1)
 480 #define eSP_reg                 (eBX_reg + 1)
 481 #define eBP_reg                 (eSP_reg + 1)
 482 #define eSI_reg                 (eBP_reg + 1)
 483 #define eDI_reg                 (eSI_reg + 1)
 484
 485 #define al_reg                  (eDI_reg + 1)
 486 #define cl_reg                  (al_reg + 1)
 487 #define dl_reg                  (cl_reg + 1)
 488 #define bl_reg                  (dl_reg + 1)
 489 #define ah_reg                  (bl_reg + 1)
 490 #define ch_reg                  (ah_reg + 1)
 491 #define dh_reg                  (ch_reg + 1)
 492 #define bh_reg                  (dh_reg + 1)
 493
 494 #define ax_reg                  (bh_reg + 1)
 495 #define cx_reg                  (ax_reg + 1)
 496 #define dx_reg                  (cx_reg + 1)
 497 #define bx_reg                  (dx_reg + 1)
 498 #define sp_reg                  (bx_reg + 1)
 499 #define bp_reg                  (sp_reg + 1)
 500 #define si_reg                  (bp_reg + 1)
 501 #define di_reg                  (si_reg + 1)
 502
 503 #define rAX_reg                 (di_reg + 1)
 504 #define rCX_reg                 (rAX_reg + 1)
 505 #define rDX_reg                 (rCX_reg + 1)
 506 #define rBX_reg                 (rDX_reg + 1)
 507 #define rSP_reg                 (rBX_reg + 1)
 508 #define rBP_reg                 (rSP_reg + 1)
 509 #define rSI_reg                 (rBP_reg + 1)
 510 #define rDI_reg                 (rSI_reg + 1)
 511
 512 #define z_mode_ax_reg           (rDI_reg + 1)
 513 #define indir_dx_reg            (z_mode_ax_reg + 1)
 514
 515 #define MAX_BYTEMODE    indir_dx_reg
 516
 517 /* Flags that are OR'ed into the bytemode field to pass extra
 518    information.  */
 519 #define DREX_OC1                0x10000 /* OC1 bit set */
 520 #define DREX_NO_OC0             0x20000 /* OC0 bit not used */
 521 #define DREX_MASK               0x40000 /* mask to delete */
 522
 523 #if MAX_BYTEMODE >= DREX_OC1
 524 #error MAX_BYTEMODE must be less than DREX_OC1
 525 #endif
 526
 527 #define FLOATCODE               1
 528 #define USE_REG_TABLE           (FLOATCODE + 1)
 529 #define USE_MOD_TABLE           (USE_REG_TABLE + 1)
 530 #define USE_RM_TABLE            (USE_MOD_TABLE + 1)
 531 #define USE_PREFIX_TABLE        (USE_RM_TABLE + 1)
 532 #define USE_X86_64_TABLE        (USE_PREFIX_TABLE + 1)
 533 #define USE_3BYTE_TABLE         (USE_X86_64_TABLE + 1)
 534 #define USE_VEX_C4_TABLE        (USE_3BYTE_TABLE + 1)
 535 #define USE_VEX_C5_TABLE        (USE_VEX_C4_TABLE + 1)
 536 #define USE_VEX_LEN_TABLE       (USE_VEX_C5_TABLE + 1)
 537
 538 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 539
 540 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 541 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 542 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 543 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 544 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 545 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 546 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 547 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 548 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 549 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 550
 551 #define REG_80                  0
 552 #define REG_81                  (REG_80 + 1)
 553 #define REG_82                  (REG_81 + 1)
 554 #define REG_8F                  (REG_82 + 1)
 555 #define REG_C0                  (REG_8F + 1)
 556 #define REG_C1                  (REG_C0 + 1)
 557 #define REG_C6                  (REG_C1 + 1)
 558 #define REG_C7                  (REG_C6 + 1)
 559 #define REG_D0                  (REG_C7 + 1)
 560 #define REG_D1                  (REG_D0 + 1)
 561 #define REG_D2                  (REG_D1 + 1)
 562 #define REG_D3                  (REG_D2 + 1)
 563 #define REG_F6                  (REG_D3 + 1)
 564 #define REG_F7                  (REG_F6 + 1)
 565 #define REG_FE                  (REG_F7 + 1)
 566 #define REG_FF                  (REG_FE + 1)
 567 #define REG_0F00                (REG_FF + 1)
 568 #define REG_0F01                (REG_0F00 + 1)
 569 #define REG_0F0D                (REG_0F01 + 1)
 570 #define REG_0F18                (REG_0F0D + 1)
 571 #define REG_0F71                (REG_0F18 + 1)
 572 #define REG_0F72                (REG_0F71 + 1)
 573 #define REG_0F73                (REG_0F72 + 1)
 574 #define REG_0FA6                (REG_0F73 + 1)
 575 #define REG_0FA7                (REG_0FA6 + 1)
 576 #define REG_0FAE                (REG_0FA7 + 1)
 577 #define REG_0FBA                (REG_0FAE + 1)
 578 #define REG_0FC7                (REG_0FBA + 1)
 579 #define REG_VEX_71              (REG_0FC7 + 1)
 580 #define REG_VEX_72              (REG_VEX_71 + 1)
 581 #define REG_VEX_73              (REG_VEX_72 + 1)
 582 #define REG_VEX_AE              (REG_VEX_73 + 1)
 583
 584 #define MOD_8D                  0
 585 #define MOD_0F01_REG_0          (MOD_8D + 1)
 586 #define MOD_0F01_REG_1          (MOD_0F01_REG_0 + 1)
 587 #define MOD_0F01_REG_2          (MOD_0F01_REG_1 + 1)
 588 #define MOD_0F01_REG_3          (MOD_0F01_REG_2 + 1)
 589 #define MOD_0F01_REG_7          (MOD_0F01_REG_3 + 1)
 590 #define MOD_0F12_PREFIX_0       (MOD_0F01_REG_7 + 1)
 591 #define MOD_0F13                (MOD_0F12_PREFIX_0 + 1)
 592 #define MOD_0F16_PREFIX_0       (MOD_0F13 + 1)
 593 #define MOD_0F17                (MOD_0F16_PREFIX_0 + 1)
 594 #define MOD_0F18_REG_0          (MOD_0F17 + 1)
 595 #define MOD_0F18_REG_1          (MOD_0F18_REG_0 + 1)
 596 #define MOD_0F18_REG_2          (MOD_0F18_REG_1 + 1)
 597 #define MOD_0F18_REG_3          (MOD_0F18_REG_2 + 1)
 598 #define MOD_0F20                (MOD_0F18_REG_3 + 1)
 599 #define MOD_0F21                (MOD_0F20 + 1)
 600 #define MOD_0F22                (MOD_0F21 + 1)
 601 #define MOD_0F23                (MOD_0F22 + 1)
 602 #define MOD_0F24                (MOD_0F23 + 1)
 603 #define MOD_0F26                (MOD_0F24 + 1)
 604 #define MOD_0F2B_PREFIX_0       (MOD_0F26 + 1)
 605 #define MOD_0F2B_PREFIX_1       (MOD_0F2B_PREFIX_0 + 1)
 606 #define MOD_0F2B_PREFIX_2       (MOD_0F2B_PREFIX_1 + 1)
 607 #define MOD_0F2B_PREFIX_3       (MOD_0F2B_PREFIX_2 + 1)
 608 #define MOD_0F51                (MOD_0F2B_PREFIX_3 + 1)
 609 #define MOD_0F71_REG_2          (MOD_0F51 + 1)
 610 #define MOD_0F71_REG_4          (MOD_0F71_REG_2 + 1)
 611 #define MOD_0F71_REG_6          (MOD_0F71_REG_4 + 1)
 612 #define MOD_0F72_REG_2          (MOD_0F71_REG_6 + 1)
 613 #define MOD_0F72_REG_4          (MOD_0F72_REG_2 + 1)
 614 #define MOD_0F72_REG_6          (MOD_0F72_REG_4 + 1)
 615 #define MOD_0F73_REG_2          (MOD_0F72_REG_6 + 1)
 616 #define MOD_0F73_REG_3          (MOD_0F73_REG_2 + 1)
 617 #define MOD_0F73_REG_6          (MOD_0F73_REG_3 + 1)
 618 #define MOD_0F73_REG_7          (MOD_0F73_REG_6 + 1)
 619 #define MOD_0FAE_REG_0          (MOD_0F73_REG_7 + 1)
 620 #define MOD_0FAE_REG_1          (MOD_0FAE_REG_0 + 1)
 621 #define MOD_0FAE_REG_2          (MOD_0FAE_REG_1 + 1)
 622 #define MOD_0FAE_REG_3          (MOD_0FAE_REG_2 + 1)
 623 #define MOD_0FAE_REG_4          (MOD_0FAE_REG_3 + 1)
 624 #define MOD_0FAE_REG_5          (MOD_0FAE_REG_4 + 1)
 625 #define MOD_0FAE_REG_6          (MOD_0FAE_REG_5 + 1)
 626 #define MOD_0FAE_REG_7          (MOD_0FAE_REG_6 + 1)
 627 #define MOD_0FB2                (MOD_0FAE_REG_7 + 1)
 628 #define MOD_0FB4                (MOD_0FB2 + 1)
 629 #define MOD_0FB5                (MOD_0FB4 + 1)
 630 #define MOD_0FC7_REG_6          (MOD_0FB5 + 1)
 631 #define MOD_0FC7_REG_7          (MOD_0FC7_REG_6 + 1)
 632 #define MOD_0FD7                (MOD_0FC7_REG_7 + 1)
 633 #define MOD_0FE7_PREFIX_2       (MOD_0FD7 + 1)
 634 #define MOD_0FF0_PREFIX_3       (MOD_0FE7_PREFIX_2 + 1)
 635 #define MOD_0F382A_PREFIX_2     (MOD_0FF0_PREFIX_3 + 1)
 636 #define MOD_62_32BIT            (MOD_0F382A_PREFIX_2 + 1)
 637 #define MOD_C4_32BIT            (MOD_62_32BIT + 1)
 638 #define MOD_C5_32BIT            (MOD_C4_32BIT + 1)
 639 #define MOD_VEX_12_PREFIX_0     (MOD_C5_32BIT + 1)
 640 #define MOD_VEX_13              (MOD_VEX_12_PREFIX_0 + 1)
 641 #define MOD_VEX_16_PREFIX_0     (MOD_VEX_13 + 1)
 642 #define MOD_VEX_17              (MOD_VEX_16_PREFIX_0 + 1)
 643 #define MOD_VEX_2B              (MOD_VEX_17 + 1)
 644 #define MOD_VEX_51              (MOD_VEX_2B + 1)
 645 #define MOD_VEX_71_REG_2        (MOD_VEX_51 + 1)
 646 #define MOD_VEX_71_REG_4        (MOD_VEX_71_REG_2 + 1)
 647 #define MOD_VEX_71_REG_6        (MOD_VEX_71_REG_4 + 1)
 648 #define MOD_VEX_72_REG_2        (MOD_VEX_71_REG_6 + 1)
 649 #define MOD_VEX_72_REG_4        (MOD_VEX_72_REG_2 + 1)
 650 #define MOD_VEX_72_REG_6        (MOD_VEX_72_REG_4 + 1)
 651 #define MOD_VEX_73_REG_2        (MOD_VEX_72_REG_6 + 1)
 652 #define MOD_VEX_73_REG_3        (MOD_VEX_73_REG_2 + 1)
 653 #define MOD_VEX_73_REG_6        (MOD_VEX_73_REG_3 + 1)
 654 #define MOD_VEX_73_REG_7        (MOD_VEX_73_REG_6 + 1)
 655 #define MOD_VEX_AE_REG_2        (MOD_VEX_73_REG_7 + 1)
 656 #define MOD_VEX_AE_REG_3        (MOD_VEX_AE_REG_2 + 1)
 657 #define MOD_VEX_D7_PREFIX_2     (MOD_VEX_AE_REG_3 + 1)
 658 #define MOD_VEX_E7_PREFIX_2     (MOD_VEX_D7_PREFIX_2 + 1)
 659 #define MOD_VEX_F0_PREFIX_3     (MOD_VEX_E7_PREFIX_2 + 1)
 660 #define MOD_VEX_3818_PREFIX_2   (MOD_VEX_F0_PREFIX_3 + 1)
 661 #define MOD_VEX_3819_PREFIX_2   (MOD_VEX_3818_PREFIX_2 + 1)
 662 #define MOD_VEX_381A_PREFIX_2   (MOD_VEX_3819_PREFIX_2 + 1)
 663 #define MOD_VEX_382A_PREFIX_2   (MOD_VEX_381A_PREFIX_2 + 1)
 664 #define MOD_VEX_382C_PREFIX_2   (MOD_VEX_382A_PREFIX_2 + 1)
 665 #define MOD_VEX_382D_PREFIX_2   (MOD_VEX_382C_PREFIX_2 + 1)
 666 #define MOD_VEX_382E_PREFIX_2   (MOD_VEX_382D_PREFIX_2 + 1)
 667 #define MOD_VEX_382F_PREFIX_2   (MOD_VEX_382E_PREFIX_2 + 1)
 668
 669 #define RM_0F01_REG_0           0
 670 #define RM_0F01_REG_1           (RM_0F01_REG_0 + 1)
 671 #define RM_0F01_REG_2           (RM_0F01_REG_1 + 1)
 672 #define RM_0F01_REG_3           (RM_0F01_REG_2 + 1)
 673 #define RM_0F01_REG_7           (RM_0F01_REG_3 + 1)
 674 #define RM_0FAE_REG_5           (RM_0F01_REG_7 + 1)
 675 #define RM_0FAE_REG_6           (RM_0FAE_REG_5 + 1)
 676 #define RM_0FAE_REG_7           (RM_0FAE_REG_6 + 1)
 677
 678 #define PREFIX_90               0
 679 #define PREFIX_0F10             (PREFIX_90 + 1)
 680 #define PREFIX_0F11             (PREFIX_0F10 + 1)
 681 #define PREFIX_0F12             (PREFIX_0F11 + 1)
 682 #define PREFIX_0F16             (PREFIX_0F12 + 1)
 683 #define PREFIX_0F2A             (PREFIX_0F16 + 1)
 684 #define PREFIX_0F2B             (PREFIX_0F2A + 1)
 685 #define PREFIX_0F2C             (PREFIX_0F2B + 1)
 686 #define PREFIX_0F2D             (PREFIX_0F2C + 1)
 687 #define PREFIX_0F2E             (PREFIX_0F2D + 1)
 688 #define PREFIX_0F2F             (PREFIX_0F2E + 1)
 689 #define PREFIX_0F51             (PREFIX_0F2F + 1)
 690 #define PREFIX_0F52             (PREFIX_0F51 + 1)
 691 #define PREFIX_0F53             (PREFIX_0F52 + 1)
 692 #define PREFIX_0F58             (PREFIX_0F53 + 1)
 693 #define PREFIX_0F59             (PREFIX_0F58 + 1)
 694 #define PREFIX_0F5A             (PREFIX_0F59 + 1)
 695 #define PREFIX_0F5B             (PREFIX_0F5A + 1)
 696 #define PREFIX_0F5C             (PREFIX_0F5B + 1)
 697 #define PREFIX_0F5D             (PREFIX_0F5C + 1)
 698 #define PREFIX_0F5E             (PREFIX_0F5D + 1)
 699 #define PREFIX_0F5F             (PREFIX_0F5E + 1)
 700 #define PREFIX_0F60             (PREFIX_0F5F + 1)
 701 #define PREFIX_0F61             (PREFIX_0F60 + 1)
 702 #define PREFIX_0F62             (PREFIX_0F61 + 1)
 703 #define PREFIX_0F6C             (PREFIX_0F62 + 1)
 704 #define PREFIX_0F6D             (PREFIX_0F6C + 1)
 705 #define PREFIX_0F6F             (PREFIX_0F6D + 1)
 706 #define PREFIX_0F70             (PREFIX_0F6F + 1)
 707 #define PREFIX_0F73_REG_3       (PREFIX_0F70 + 1)
 708 #define PREFIX_0F73_REG_7       (PREFIX_0F73_REG_3 + 1)
 709 #define PREFIX_0F78             (PREFIX_0F73_REG_7 + 1)
 710 #define PREFIX_0F79             (PREFIX_0F78 + 1)
 711 #define PREFIX_0F7C             (PREFIX_0F79 + 1)
 712 #define PREFIX_0F7D             (PREFIX_0F7C + 1)
 713 #define PREFIX_0F7E             (PREFIX_0F7D + 1)
 714 #define PREFIX_0F7F             (PREFIX_0F7E + 1)
 715 #define PREFIX_0FB8             (PREFIX_0F7F + 1)
 716 #define PREFIX_0FBD             (PREFIX_0FB8 + 1)
 717 #define PREFIX_0FC2             (PREFIX_0FBD + 1)
 718 #define PREFIX_0FC3             (PREFIX_0FC2 + 1)
 719 #define PREFIX_0FC7_REG_6       (PREFIX_0FC3 + 1)
 720 #define PREFIX_0FD0             (PREFIX_0FC7_REG_6 + 1)
 721 #define PREFIX_0FD6             (PREFIX_0FD0 + 1)
 722 #define PREFIX_0FE6             (PREFIX_0FD6 + 1)
 723 #define PREFIX_0FE7             (PREFIX_0FE6 + 1)
 724 #define PREFIX_0FF0             (PREFIX_0FE7 + 1)
 725 #define PREFIX_0FF7             (PREFIX_0FF0 + 1)
 726 #define PREFIX_0F3810           (PREFIX_0FF7 + 1)
 727 #define PREFIX_0F3814           (PREFIX_0F3810 + 1)
 728 #define PREFIX_0F3815           (PREFIX_0F3814 + 1)
 729 #define PREFIX_0F3817           (PREFIX_0F3815 + 1)
 730 #define PREFIX_0F3820           (PREFIX_0F3817 + 1)
 731 #define PREFIX_0F3821           (PREFIX_0F3820 + 1)
 732 #define PREFIX_0F3822           (PREFIX_0F3821 + 1)
 733 #define PREFIX_0F3823           (PREFIX_0F3822 + 1)
 734 #define PREFIX_0F3824           (PREFIX_0F3823 + 1)
 735 #define PREFIX_0F3825           (PREFIX_0F3824 + 1)
 736 #define PREFIX_0F3828           (PREFIX_0F3825 + 1)
 737 #define PREFIX_0F3829           (PREFIX_0F3828 + 1)
 738 #define PREFIX_0F382A           (PREFIX_0F3829 + 1)
 739 #define PREFIX_0F382B           (PREFIX_0F382A + 1)
 740 #define PREFIX_0F3830           (PREFIX_0F382B + 1)
 741 #define PREFIX_0F3831           (PREFIX_0F3830 + 1)
 742 #define PREFIX_0F3832           (PREFIX_0F3831 + 1)
 743 #define PREFIX_0F3833           (PREFIX_0F3832 + 1)
 744 #define PREFIX_0F3834           (PREFIX_0F3833 + 1)
 745 #define PREFIX_0F3835           (PREFIX_0F3834 + 1)
 746 #define PREFIX_0F3837           (PREFIX_0F3835 + 1)
 747 #define PREFIX_0F3838           (PREFIX_0F3837 + 1)
 748 #define PREFIX_0F3839           (PREFIX_0F3838 + 1)
 749 #define PREFIX_0F383A           (PREFIX_0F3839 + 1)
 750 #define PREFIX_0F383B           (PREFIX_0F383A + 1)
 751 #define PREFIX_0F383C           (PREFIX_0F383B + 1)
 752 #define PREFIX_0F383D           (PREFIX_0F383C + 1)
 753 #define PREFIX_0F383E           (PREFIX_0F383D + 1)
 754 #define PREFIX_0F383F           (PREFIX_0F383E + 1)
 755 #define PREFIX_0F3840           (PREFIX_0F383F + 1)
 756 #define PREFIX_0F3841           (PREFIX_0F3840 + 1)
 757 #define PREFIX_0F3880           (PREFIX_0F3841 + 1)
 758 #define PREFIX_0F3881           (PREFIX_0F3880 + 1)
 759 #define PREFIX_0F38DB           (PREFIX_0F3881 + 1)
 760 #define PREFIX_0F38DC           (PREFIX_0F38DB + 1)
 761 #define PREFIX_0F38DD           (PREFIX_0F38DC + 1)
 762 #define PREFIX_0F38DE           (PREFIX_0F38DD + 1)
 763 #define PREFIX_0F38DF           (PREFIX_0F38DE + 1)
 764 #define PREFIX_0F38F0           (PREFIX_0F38DF + 1)
 765 #define PREFIX_0F38F1           (PREFIX_0F38F0 + 1)
 766 #define PREFIX_0F3A08           (PREFIX_0F38F1 + 1)
 767 #define PREFIX_0F3A09           (PREFIX_0F3A08 + 1)
 768 #define PREFIX_0F3A0A           (PREFIX_0F3A09 + 1)
 769 #define PREFIX_0F3A0B           (PREFIX_0F3A0A + 1)
 770 #define PREFIX_0F3A0C           (PREFIX_0F3A0B + 1)
 771 #define PREFIX_0F3A0D           (PREFIX_0F3A0C + 1)
 772 #define PREFIX_0F3A0E           (PREFIX_0F3A0D + 1)
 773 #define PREFIX_0F3A14           (PREFIX_0F3A0E + 1)
 774 #define PREFIX_0F3A15           (PREFIX_0F3A14 + 1)
 775 #define PREFIX_0F3A16           (PREFIX_0F3A15 + 1)
 776 #define PREFIX_0F3A17           (PREFIX_0F3A16 + 1)
 777 #define PREFIX_0F3A20           (PREFIX_0F3A17 + 1)
 778 #define PREFIX_0F3A21           (PREFIX_0F3A20 + 1)
 779 #define PREFIX_0F3A22           (PREFIX_0F3A21 + 1)
 780 #define PREFIX_0F3A40           (PREFIX_0F3A22 + 1)
 781 #define PREFIX_0F3A41           (PREFIX_0F3A40 + 1)
 782 #define PREFIX_0F3A42           (PREFIX_0F3A41 + 1)
 783 #define PREFIX_0F3A44           (PREFIX_0F3A42 + 1)
 784 #define PREFIX_0F3A60           (PREFIX_0F3A44 + 1)
 785 #define PREFIX_0F3A61           (PREFIX_0F3A60 + 1)
 786 #define PREFIX_0F3A62           (PREFIX_0F3A61 + 1)
 787 #define PREFIX_0F3A63           (PREFIX_0F3A62 + 1)
 788 #define PREFIX_0F3ADF           (PREFIX_0F3A63 + 1)
 789 #define PREFIX_VEX_10           (PREFIX_0F3ADF + 1)
 790 #define PREFIX_VEX_11           (PREFIX_VEX_10 + 1)
 791 #define PREFIX_VEX_12           (PREFIX_VEX_11 + 1)
 792 #define PREFIX_VEX_16           (PREFIX_VEX_12 + 1)
 793 #define PREFIX_VEX_2A           (PREFIX_VEX_16 + 1)
 794 #define PREFIX_VEX_2C           (PREFIX_VEX_2A + 1)
 795 #define PREFIX_VEX_2D           (PREFIX_VEX_2C + 1)
 796 #define PREFIX_VEX_2E           (PREFIX_VEX_2D + 1)
 797 #define PREFIX_VEX_2F           (PREFIX_VEX_2E + 1)
 798 #define PREFIX_VEX_51           (PREFIX_VEX_2F + 1)
 799 #define PREFIX_VEX_52           (PREFIX_VEX_51 + 1)
 800 #define PREFIX_VEX_53           (PREFIX_VEX_52 + 1)
 801 #define PREFIX_VEX_58           (PREFIX_VEX_53 + 1)
 802 #define PREFIX_VEX_59           (PREFIX_VEX_58 + 1)
 803 #define PREFIX_VEX_5A           (PREFIX_VEX_59 + 1)
 804 #define PREFIX_VEX_5B           (PREFIX_VEX_5A + 1)
 805 #define PREFIX_VEX_5C           (PREFIX_VEX_5B + 1)
 806 #define PREFIX_VEX_5D           (PREFIX_VEX_5C + 1)
 807 #define PREFIX_VEX_5E           (PREFIX_VEX_5D + 1)
 808 #define PREFIX_VEX_5F           (PREFIX_VEX_5E + 1)
 809 #define PREFIX_VEX_60           (PREFIX_VEX_5F + 1)
 810 #define PREFIX_VEX_61           (PREFIX_VEX_60 + 1)
 811 #define PREFIX_VEX_62           (PREFIX_VEX_61 + 1)
 812 #define PREFIX_VEX_63           (PREFIX_VEX_62 + 1)
 813 #define PREFIX_VEX_64           (PREFIX_VEX_63 + 1)
 814 #define PREFIX_VEX_65           (PREFIX_VEX_64 + 1)
 815 #define PREFIX_VEX_66           (PREFIX_VEX_65 + 1)
 816 #define PREFIX_VEX_67           (PREFIX_VEX_66 + 1)
 817 #define PREFIX_VEX_68           (PREFIX_VEX_67 + 1)
 818 #define PREFIX_VEX_69           (PREFIX_VEX_68 + 1)
 819 #define PREFIX_VEX_6A           (PREFIX_VEX_69 + 1)
 820 #define PREFIX_VEX_6B           (PREFIX_VEX_6A + 1)
 821 #define PREFIX_VEX_6C           (PREFIX_VEX_6B + 1)
 822 #define PREFIX_VEX_6D           (PREFIX_VEX_6C + 1)
 823 #define PREFIX_VEX_6E           (PREFIX_VEX_6D + 1)
 824 #define PREFIX_VEX_6F           (PREFIX_VEX_6E + 1)
 825 #define PREFIX_VEX_70           (PREFIX_VEX_6F + 1)
 826 #define PREFIX_VEX_71_REG_2     (PREFIX_VEX_70 + 1)
 827 #define PREFIX_VEX_71_REG_4     (PREFIX_VEX_71_REG_2 + 1)
 828 #define PREFIX_VEX_71_REG_6     (PREFIX_VEX_71_REG_4 + 1)
 829 #define PREFIX_VEX_72_REG_2     (PREFIX_VEX_71_REG_6 + 1)
 830 #define PREFIX_VEX_72_REG_4     (PREFIX_VEX_72_REG_2 + 1)
 831 #define PREFIX_VEX_72_REG_6     (PREFIX_VEX_72_REG_4 + 1)
 832 #define PREFIX_VEX_73_REG_2     (PREFIX_VEX_72_REG_6 + 1)
 833 #define PREFIX_VEX_73_REG_3     (PREFIX_VEX_73_REG_2 + 1)
 834 #define PREFIX_VEX_73_REG_6     (PREFIX_VEX_73_REG_3 + 1)
 835 #define PREFIX_VEX_73_REG_7     (PREFIX_VEX_73_REG_6 + 1)
 836 #define PREFIX_VEX_74           (PREFIX_VEX_73_REG_7 + 1)
 837 #define PREFIX_VEX_75           (PREFIX_VEX_74 + 1)
 838 #define PREFIX_VEX_76           (PREFIX_VEX_75 + 1)
 839 #define PREFIX_VEX_77           (PREFIX_VEX_76 + 1)
 840 #define PREFIX_VEX_7C           (PREFIX_VEX_77 + 1)
 841 #define PREFIX_VEX_7D           (PREFIX_VEX_7C + 1)
 842 #define PREFIX_VEX_7E           (PREFIX_VEX_7D + 1)
 843 #define PREFIX_VEX_7F           (PREFIX_VEX_7E + 1)
 844 #define PREFIX_VEX_C2           (PREFIX_VEX_7F + 1)
 845 #define PREFIX_VEX_C4           (PREFIX_VEX_C2 + 1)
 846 #define PREFIX_VEX_C5           (PREFIX_VEX_C4 + 1)
 847 #define PREFIX_VEX_D0           (PREFIX_VEX_C5 + 1)
 848 #define PREFIX_VEX_D1           (PREFIX_VEX_D0 + 1)
 849 #define PREFIX_VEX_D2           (PREFIX_VEX_D1 + 1)
 850 #define PREFIX_VEX_D3           (PREFIX_VEX_D2 + 1)
 851 #define PREFIX_VEX_D4           (PREFIX_VEX_D3 + 1)
 852 #define PREFIX_VEX_D5           (PREFIX_VEX_D4 + 1)
 853 #define PREFIX_VEX_D6           (PREFIX_VEX_D5 + 1)
 854 #define PREFIX_VEX_D7           (PREFIX_VEX_D6 + 1)
 855 #define PREFIX_VEX_D8           (PREFIX_VEX_D7 + 1)
 856 #define PREFIX_VEX_D9           (PREFIX_VEX_D8 + 1)
 857 #define PREFIX_VEX_DA           (PREFIX_VEX_D9 + 1)
 858 #define PREFIX_VEX_DB           (PREFIX_VEX_DA + 1)
 859 #define PREFIX_VEX_DC           (PREFIX_VEX_DB + 1)
 860 #define PREFIX_VEX_DD           (PREFIX_VEX_DC + 1)
 861 #define PREFIX_VEX_DE           (PREFIX_VEX_DD + 1)
 862 #define PREFIX_VEX_DF           (PREFIX_VEX_DE + 1)
 863 #define PREFIX_VEX_E0           (PREFIX_VEX_DF + 1)
 864 #define PREFIX_VEX_E1           (PREFIX_VEX_E0 + 1)
 865 #define PREFIX_VEX_E2           (PREFIX_VEX_E1 + 1)
 866 #define PREFIX_VEX_E3           (PREFIX_VEX_E2 + 1)
 867 #define PREFIX_VEX_E4           (PREFIX_VEX_E3 + 1)
 868 #define PREFIX_VEX_E5           (PREFIX_VEX_E4 + 1)
 869 #define PREFIX_VEX_E6           (PREFIX_VEX_E5 + 1)
 870 #define PREFIX_VEX_E7           (PREFIX_VEX_E6 + 1)
 871 #define PREFIX_VEX_E8           (PREFIX_VEX_E7 + 1)
 872 #define PREFIX_VEX_E9           (PREFIX_VEX_E8 + 1)
 873 #define PREFIX_VEX_EA           (PREFIX_VEX_E9 + 1)
 874 #define PREFIX_VEX_EB           (PREFIX_VEX_EA + 1)
 875 #define PREFIX_VEX_EC           (PREFIX_VEX_EB + 1)
 876 #define PREFIX_VEX_ED           (PREFIX_VEX_EC + 1)
 877 #define PREFIX_VEX_EE           (PREFIX_VEX_ED + 1)
 878 #define PREFIX_VEX_EF           (PREFIX_VEX_EE + 1)
 879 #define PREFIX_VEX_F0           (PREFIX_VEX_EF + 1)
 880 #define PREFIX_VEX_F1           (PREFIX_VEX_F0 + 1)
 881 #define PREFIX_VEX_F2           (PREFIX_VEX_F1 + 1)
 882 #define PREFIX_VEX_F3           (PREFIX_VEX_F2 + 1)
 883 #define PREFIX_VEX_F4           (PREFIX_VEX_F3 + 1)
 884 #define PREFIX_VEX_F5           (PREFIX_VEX_F4 + 1)
 885 #define PREFIX_VEX_F6           (PREFIX_VEX_F5 + 1)
 886 #define PREFIX_VEX_F7           (PREFIX_VEX_F6 + 1)
 887 #define PREFIX_VEX_F8           (PREFIX_VEX_F7 + 1)
 888 #define PREFIX_VEX_F9           (PREFIX_VEX_F8 + 1)
 889 #define PREFIX_VEX_FA           (PREFIX_VEX_F9 + 1)
 890 #define PREFIX_VEX_FB           (PREFIX_VEX_FA + 1)
 891 #define PREFIX_VEX_FC           (PREFIX_VEX_FB + 1)
 892 #define PREFIX_VEX_FD           (PREFIX_VEX_FC + 1)
 893 #define PREFIX_VEX_FE           (PREFIX_VEX_FD + 1)
 894 #define PREFIX_VEX_3800         (PREFIX_VEX_FE + 1)
 895 #define PREFIX_VEX_3801         (PREFIX_VEX_3800 + 1)
 896 #define PREFIX_VEX_3802         (PREFIX_VEX_3801 + 1)
 897 #define PREFIX_VEX_3803         (PREFIX_VEX_3802 + 1)
 898 #define PREFIX_VEX_3804         (PREFIX_VEX_3803 + 1)
 899 #define PREFIX_VEX_3805         (PREFIX_VEX_3804 + 1)
 900 #define PREFIX_VEX_3806         (PREFIX_VEX_3805 + 1)
 901 #define PREFIX_VEX_3807         (PREFIX_VEX_3806 + 1)
 902 #define PREFIX_VEX_3808         (PREFIX_VEX_3807 + 1)
 903 #define PREFIX_VEX_3809         (PREFIX_VEX_3808 + 1)
 904 #define PREFIX_VEX_380A         (PREFIX_VEX_3809 + 1)
 905 #define PREFIX_VEX_380B         (PREFIX_VEX_380A + 1)
 906 #define PREFIX_VEX_380C         (PREFIX_VEX_380B + 1)
 907 #define PREFIX_VEX_380D         (PREFIX_VEX_380C + 1)
 908 #define PREFIX_VEX_380E         (PREFIX_VEX_380D + 1)
 909 #define PREFIX_VEX_380F         (PREFIX_VEX_380E + 1)
 910 #define PREFIX_VEX_3817         (PREFIX_VEX_380F + 1)
 911 #define PREFIX_VEX_3818         (PREFIX_VEX_3817 + 1)
 912 #define PREFIX_VEX_3819         (PREFIX_VEX_3818 + 1)
 913 #define PREFIX_VEX_381A         (PREFIX_VEX_3819 + 1)
 914 #define PREFIX_VEX_381C         (PREFIX_VEX_381A + 1)
 915 #define PREFIX_VEX_381D         (PREFIX_VEX_381C + 1)
 916 #define PREFIX_VEX_381E         (PREFIX_VEX_381D + 1)
 917 #define PREFIX_VEX_3820         (PREFIX_VEX_381E + 1)
 918 #define PREFIX_VEX_3821         (PREFIX_VEX_3820 + 1)
 919 #define PREFIX_VEX_3822         (PREFIX_VEX_3821 + 1)
 920 #define PREFIX_VEX_3823         (PREFIX_VEX_3822 + 1)
 921 #define PREFIX_VEX_3824         (PREFIX_VEX_3823 + 1)
 922 #define PREFIX_VEX_3825         (PREFIX_VEX_3824 + 1)
 923 #define PREFIX_VEX_3828         (PREFIX_VEX_3825 + 1)
 924 #define PREFIX_VEX_3829         (PREFIX_VEX_3828 + 1)
 925 #define PREFIX_VEX_382A         (PREFIX_VEX_3829 + 1)
 926 #define PREFIX_VEX_382B         (PREFIX_VEX_382A + 1)
 927 #define PREFIX_VEX_382C         (PREFIX_VEX_382B + 1)
 928 #define PREFIX_VEX_382D         (PREFIX_VEX_382C + 1)
 929 #define PREFIX_VEX_382E         (PREFIX_VEX_382D + 1)
 930 #define PREFIX_VEX_382F         (PREFIX_VEX_382E + 1)
 931 #define PREFIX_VEX_3830         (PREFIX_VEX_382F + 1)
 932 #define PREFIX_VEX_3831         (PREFIX_VEX_3830 + 1)
 933 #define PREFIX_VEX_3832         (PREFIX_VEX_3831 + 1)
 934 #define PREFIX_VEX_3833         (PREFIX_VEX_3832 + 1)
 935 #define PREFIX_VEX_3834         (PREFIX_VEX_3833 + 1)
 936 #define PREFIX_VEX_3835         (PREFIX_VEX_3834 + 1)
 937 #define PREFIX_VEX_3837         (PREFIX_VEX_3835 + 1)
 938 #define PREFIX_VEX_3838         (PREFIX_VEX_3837 + 1)
 939 #define PREFIX_VEX_3839         (PREFIX_VEX_3838 + 1)
 940 #define PREFIX_VEX_383A         (PREFIX_VEX_3839 + 1)
 941 #define PREFIX_VEX_383B         (PREFIX_VEX_383A + 1)
 942 #define PREFIX_VEX_383C         (PREFIX_VEX_383B + 1)
 943 #define PREFIX_VEX_383D         (PREFIX_VEX_383C + 1)
 944 #define PREFIX_VEX_383E         (PREFIX_VEX_383D + 1)
 945 #define PREFIX_VEX_383F         (PREFIX_VEX_383E + 1)
 946 #define PREFIX_VEX_3840         (PREFIX_VEX_383F + 1)
 947 #define PREFIX_VEX_3841         (PREFIX_VEX_3840 + 1)
 948 #define PREFIX_VEX_3896         (PREFIX_VEX_3841 + 1)
 949 #define PREFIX_VEX_3897         (PREFIX_VEX_3896 + 1)
 950 #define PREFIX_VEX_3898         (PREFIX_VEX_3897 + 1)
 951 #define PREFIX_VEX_3899         (PREFIX_VEX_3898 + 1)
 952 #define PREFIX_VEX_389A         (PREFIX_VEX_3899 + 1)
 953 #define PREFIX_VEX_389B         (PREFIX_VEX_389A + 1)
 954 #define PREFIX_VEX_389C         (PREFIX_VEX_389B + 1)
 955 #define PREFIX_VEX_389D         (PREFIX_VEX_389C + 1)
 956 #define PREFIX_VEX_389E         (PREFIX_VEX_389D + 1)
 957 #define PREFIX_VEX_389F         (PREFIX_VEX_389E + 1)
 958 #define PREFIX_VEX_38A6         (PREFIX_VEX_389F + 1)
 959 #define PREFIX_VEX_38A7         (PREFIX_VEX_38A6 + 1)
 960 #define PREFIX_VEX_38A8         (PREFIX_VEX_38A7 + 1)
 961 #define PREFIX_VEX_38A9         (PREFIX_VEX_38A8 + 1)
 962 #define PREFIX_VEX_38AA         (PREFIX_VEX_38A9 + 1)
 963 #define PREFIX_VEX_38AB         (PREFIX_VEX_38AA + 1)
 964 #define PREFIX_VEX_38AC         (PREFIX_VEX_38AB + 1)
 965 #define PREFIX_VEX_38AD         (PREFIX_VEX_38AC + 1)
 966 #define PREFIX_VEX_38AE         (PREFIX_VEX_38AD + 1)
 967 #define PREFIX_VEX_38AF         (PREFIX_VEX_38AE + 1)
 968 #define PREFIX_VEX_38B6         (PREFIX_VEX_38AF + 1)
 969 #define PREFIX_VEX_38B7         (PREFIX_VEX_38B6 + 1)
 970 #define PREFIX_VEX_38B8         (PREFIX_VEX_38B7 + 1)
 971 #define PREFIX_VEX_38B9         (PREFIX_VEX_38B8 + 1)
 972 #define PREFIX_VEX_38BA         (PREFIX_VEX_38B9 + 1)
 973 #define PREFIX_VEX_38BB         (PREFIX_VEX_38BA + 1)
 974 #define PREFIX_VEX_38BC         (PREFIX_VEX_38BB + 1)
 975 #define PREFIX_VEX_38BD         (PREFIX_VEX_38BC + 1)
 976 #define PREFIX_VEX_38BE         (PREFIX_VEX_38BD + 1)
 977 #define PREFIX_VEX_38BF         (PREFIX_VEX_38BE + 1)
 978 #define PREFIX_VEX_38DB         (PREFIX_VEX_38BF + 1)
 979 #define PREFIX_VEX_38DC         (PREFIX_VEX_38DB + 1)
 980 #define PREFIX_VEX_38DD         (PREFIX_VEX_38DC + 1)
 981 #define PREFIX_VEX_38DE         (PREFIX_VEX_38DD + 1)
 982 #define PREFIX_VEX_38DF         (PREFIX_VEX_38DE + 1)
 983 #define PREFIX_VEX_3A04         (PREFIX_VEX_38DF + 1)
 984 #define PREFIX_VEX_3A05         (PREFIX_VEX_3A04 + 1)
 985 #define PREFIX_VEX_3A06         (PREFIX_VEX_3A05 + 1)
 986 #define PREFIX_VEX_3A08         (PREFIX_VEX_3A06 + 1)
 987 #define PREFIX_VEX_3A09         (PREFIX_VEX_3A08 + 1)
 988 #define PREFIX_VEX_3A0A         (PREFIX_VEX_3A09 + 1)
 989 #define PREFIX_VEX_3A0B         (PREFIX_VEX_3A0A + 1)
 990 #define PREFIX_VEX_3A0C         (PREFIX_VEX_3A0B + 1)
 991 #define PREFIX_VEX_3A0D         (PREFIX_VEX_3A0C + 1)
 992 #define PREFIX_VEX_3A0E         (PREFIX_VEX_3A0D + 1)
 993 #define PREFIX_VEX_3A0F         (PREFIX_VEX_3A0E + 1)
 994 #define PREFIX_VEX_3A14         (PREFIX_VEX_3A0F + 1)
 995 #define PREFIX_VEX_3A15         (PREFIX_VEX_3A14 + 1)
 996 #define PREFIX_VEX_3A16         (PREFIX_VEX_3A15 + 1)
 997 #define PREFIX_VEX_3A17         (PREFIX_VEX_3A16 + 1)
 998 #define PREFIX_VEX_3A18         (PREFIX_VEX_3A17 + 1)
 999 #define PREFIX_VEX_3A19         (PREFIX_VEX_3A18 + 1)
1000 #define PREFIX_VEX_3A20         (PREFIX_VEX_3A19 + 1)
1001 #define PREFIX_VEX_3A21         (PREFIX_VEX_3A20 + 1)
1002 #define PREFIX_VEX_3A22         (PREFIX_VEX_3A21 + 1)
1003 #define PREFIX_VEX_3A40         (PREFIX_VEX_3A22 + 1)
1004 #define PREFIX_VEX_3A41         (PREFIX_VEX_3A40 + 1)
1005 #define PREFIX_VEX_3A42         (PREFIX_VEX_3A41 + 1)
1006 #define PREFIX_VEX_3A4A         (PREFIX_VEX_3A42 + 1)
1007 #define PREFIX_VEX_3A4B         (PREFIX_VEX_3A4A + 1)
1008 #define PREFIX_VEX_3A4C         (PREFIX_VEX_3A4B + 1)
1009 #define PREFIX_VEX_3A60         (PREFIX_VEX_3A4C + 1)
1010 #define PREFIX_VEX_3A61         (PREFIX_VEX_3A60 + 1)
1011 #define PREFIX_VEX_3A62         (PREFIX_VEX_3A61 + 1)
1012 #define PREFIX_VEX_3A63         (PREFIX_VEX_3A62 + 1)
1013 #define PREFIX_VEX_3ADF         (PREFIX_VEX_3A63 + 1)
1014
1015 #define X86_64_06               0
1016 #define X86_64_07               (X86_64_06 + 1)
1017 #define X86_64_0D               (X86_64_07 + 1)
1018 #define X86_64_16               (X86_64_0D + 1)
1019 #define X86_64_17               (X86_64_16 + 1)
1020 #define X86_64_1E               (X86_64_17 + 1)
1021 #define X86_64_1F               (X86_64_1E + 1)
1022 #define X86_64_27               (X86_64_1F + 1)
1023 #define X86_64_2F               (X86_64_27 + 1)
1024 #define X86_64_37               (X86_64_2F + 1)
1025 #define X86_64_3F               (X86_64_37 + 1)
1026 #define X86_64_60               (X86_64_3F + 1)
1027 #define X86_64_61               (X86_64_60 + 1)
1028 #define X86_64_62               (X86_64_61 + 1)
1029 #define X86_64_63               (X86_64_62 + 1)
1030 #define X86_64_6D               (X86_64_63 + 1)
1031 #define X86_64_6F               (X86_64_6D + 1)
1032 #define X86_64_9A               (X86_64_6F + 1)
1033 #define X86_64_C4               (X86_64_9A + 1)
1034 #define X86_64_C5               (X86_64_C4 + 1)
1035 #define X86_64_CE               (X86_64_C5 + 1)
1036 #define X86_64_D4               (X86_64_CE + 1)
1037 #define X86_64_D5               (X86_64_D4 + 1)
1038 #define X86_64_EA               (X86_64_D5 + 1)
1039 #define X86_64_0F01_REG_0       (X86_64_EA + 1)
1040 #define X86_64_0F01_REG_1       (X86_64_0F01_REG_0 + 1)
1041 #define X86_64_0F01_REG_2       (X86_64_0F01_REG_1 + 1)
1042 #define X86_64_0F01_REG_3       (X86_64_0F01_REG_2 + 1)
1043
1044 #define THREE_BYTE_0F24         0
1045 #define THREE_BYTE_0F25         (THREE_BYTE_0F24 + 1)
1046 #define THREE_BYTE_0F38         (THREE_BYTE_0F25 + 1)
1047 #define THREE_BYTE_0F3A         (THREE_BYTE_0F38 + 1)
1048 #define THREE_BYTE_0F7A         (THREE_BYTE_0F3A + 1)
1049 #define THREE_BYTE_0F7B         (THREE_BYTE_0F7A + 1)
1050
1051 #define VEX_0F                  0
1052 #define VEX_0F38                (VEX_0F + 1)
1053 #define VEX_0F3A                (VEX_0F38 + 1)
1054
1055 #define VEX_LEN_10_P_1  0
1056 #define VEX_LEN_10_P_3  (VEX_LEN_10_P_1 + 1)
1057 #define VEX_LEN_11_P_1  (VEX_LEN_10_P_3 + 1)
1058 #define VEX_LEN_11_P_3  (VEX_LEN_11_P_1 + 1)
1059 #define VEX_LEN_12_P_0_M_0      (VEX_LEN_11_P_3 + 1)
1060 #define VEX_LEN_12_P_0_M_1      (VEX_LEN_12_P_0_M_0 + 1)
1061 #define VEX_LEN_12_P_2  (VEX_LEN_12_P_0_M_1 + 1)
1062 #define VEX_LEN_13_M_0  (VEX_LEN_12_P_2 + 1)
1063 #define VEX_LEN_16_P_0_M_0      (VEX_LEN_13_M_0 + 1)
1064 #define VEX_LEN_16_P_0_M_1      (VEX_LEN_16_P_0_M_0 + 1)
1065 #define VEX_LEN_16_P_2  (VEX_LEN_16_P_0_M_1 + 1)
1066 #define VEX_LEN_17_M_0  (VEX_LEN_16_P_2 + 1)
1067 #define VEX_LEN_2A_P_1  (VEX_LEN_17_M_0 + 1)
1068 #define VEX_LEN_2A_P_3  (VEX_LEN_2A_P_1 + 1)
1069 #define VEX_LEN_2C_P_1  (VEX_LEN_2A_P_3 + 1)
1070 #define VEX_LEN_2C_P_3  (VEX_LEN_2C_P_1 + 1)
1071 #define VEX_LEN_2D_P_1  (VEX_LEN_2C_P_3 + 1)
1072 #define VEX_LEN_2D_P_3  (VEX_LEN_2D_P_1 + 1)
1073 #define VEX_LEN_2E_P_0  (VEX_LEN_2D_P_3 + 1)
1074 #define VEX_LEN_2E_P_2  (VEX_LEN_2E_P_0 + 1)
1075 #define VEX_LEN_2F_P_0  (VEX_LEN_2E_P_2 + 1)
1076 #define VEX_LEN_2F_P_2  (VEX_LEN_2F_P_0 + 1)
1077 #define VEX_LEN_51_P_1  (VEX_LEN_2F_P_2 + 1)
1078 #define VEX_LEN_51_P_3  (VEX_LEN_51_P_1 + 1)
1079 #define VEX_LEN_52_P_1  (VEX_LEN_51_P_3 + 1)
1080 #define VEX_LEN_53_P_1  (VEX_LEN_52_P_1 + 1)
1081 #define VEX_LEN_58_P_1  (VEX_LEN_53_P_1 + 1)
1082 #define VEX_LEN_58_P_3  (VEX_LEN_58_P_1 + 1)
1083 #define VEX_LEN_59_P_1  (VEX_LEN_58_P_3 + 1)
1084 #define VEX_LEN_59_P_3  (VEX_LEN_59_P_1 + 1)
1085 #define VEX_LEN_5A_P_1  (VEX_LEN_59_P_3 + 1)
1086 #define VEX_LEN_5A_P_3  (VEX_LEN_5A_P_1 + 1)
1087 #define VEX_LEN_5C_P_1  (VEX_LEN_5A_P_3 + 1)
1088 #define VEX_LEN_5C_P_3  (VEX_LEN_5C_P_1 + 1)
1089 #define VEX_LEN_5D_P_1  (VEX_LEN_5C_P_3 + 1)
1090 #define VEX_LEN_5D_P_3  (VEX_LEN_5D_P_1 + 1)
1091 #define VEX_LEN_5E_P_1  (VEX_LEN_5D_P_3 + 1)
1092 #define VEX_LEN_5E_P_3  (VEX_LEN_5E_P_1 + 1)
1093 #define VEX_LEN_5F_P_1  (VEX_LEN_5E_P_3 + 1)
1094 #define VEX_LEN_5F_P_3  (VEX_LEN_5F_P_1 + 1)
1095 #define VEX_LEN_60_P_2  (VEX_LEN_5F_P_3 + 1)
1096 #define VEX_LEN_61_P_2  (VEX_LEN_60_P_2 + 1)
1097 #define VEX_LEN_62_P_2  (VEX_LEN_61_P_2 + 1)
1098 #define VEX_LEN_63_P_2  (VEX_LEN_62_P_2 + 1)
1099 #define VEX_LEN_64_P_2  (VEX_LEN_63_P_2 + 1)
1100 #define VEX_LEN_65_P_2  (VEX_LEN_64_P_2 + 1)
1101 #define VEX_LEN_66_P_2  (VEX_LEN_65_P_2 + 1)
1102 #define VEX_LEN_67_P_2  (VEX_LEN_66_P_2 + 1)
1103 #define VEX_LEN_68_P_2  (VEX_LEN_67_P_2 + 1)
1104 #define VEX_LEN_69_P_2  (VEX_LEN_68_P_2 + 1)
1105 #define VEX_LEN_6A_P_2  (VEX_LEN_69_P_2 + 1)
1106 #define VEX_LEN_6B_P_2  (VEX_LEN_6A_P_2 + 1)
1107 #define VEX_LEN_6C_P_2  (VEX_LEN_6B_P_2 + 1)
1108 #define VEX_LEN_6D_P_2  (VEX_LEN_6C_P_2 + 1)
1109 #define VEX_LEN_6E_P_2  (VEX_LEN_6D_P_2 + 1)
1110 #define VEX_LEN_70_P_1  (VEX_LEN_6E_P_2 + 1)
1111 #define VEX_LEN_70_P_2  (VEX_LEN_70_P_1 + 1)
1112 #define VEX_LEN_70_P_3  (VEX_LEN_70_P_2 + 1)
1113 #define VEX_LEN_71_R_2_P_2      (VEX_LEN_70_P_3 + 1)
1114 #define VEX_LEN_71_R_4_P_2      (VEX_LEN_71_R_2_P_2 + 1)
1115 #define VEX_LEN_71_R_6_P_2      (VEX_LEN_71_R_4_P_2 + 1)
1116 #define VEX_LEN_72_R_2_P_2      (VEX_LEN_71_R_6_P_2 + 1)
1117 #define VEX_LEN_72_R_4_P_2      (VEX_LEN_72_R_2_P_2 + 1)
1118 #define VEX_LEN_72_R_6_P_2      (VEX_LEN_72_R_4_P_2 + 1)
1119 #define VEX_LEN_73_R_2_P_2      (VEX_LEN_72_R_6_P_2 + 1)
1120 #define VEX_LEN_73_R_3_P_2      (VEX_LEN_73_R_2_P_2 + 1)
1121 #define VEX_LEN_73_R_6_P_2      (VEX_LEN_73_R_3_P_2 + 1)
1122 #define VEX_LEN_73_R_7_P_2      (VEX_LEN_73_R_6_P_2 + 1)
1123 #define VEX_LEN_74_P_2  (VEX_LEN_73_R_7_P_2 + 1)
1124 #define VEX_LEN_75_P_2  (VEX_LEN_74_P_2 + 1)
1125 #define VEX_LEN_76_P_2  (VEX_LEN_75_P_2 + 1)
1126 #define VEX_LEN_7E_P_1  (VEX_LEN_76_P_2 + 1)
1127 #define VEX_LEN_7E_P_2  (VEX_LEN_7E_P_1 + 1)
1128 #define VEX_LEN_AE_R_2_M_0      (VEX_LEN_7E_P_2 + 1)
1129 #define VEX_LEN_AE_R_3_M_0      (VEX_LEN_AE_R_2_M_0 + 1)
1130 #define VEX_LEN_C2_P_1  (VEX_LEN_AE_R_3_M_0 + 1)
1131 #define VEX_LEN_C2_P_3  (VEX_LEN_C2_P_1 + 1)
1132 #define VEX_LEN_C4_P_2  (VEX_LEN_C2_P_3 + 1)
1133 #define VEX_LEN_C5_P_2  (VEX_LEN_C4_P_2 + 1)
1134 #define VEX_LEN_D1_P_2  (VEX_LEN_C5_P_2 + 1)
1135 #define VEX_LEN_D2_P_2  (VEX_LEN_D1_P_2 + 1)
1136 #define VEX_LEN_D3_P_2  (VEX_LEN_D2_P_2 + 1)
1137 #define VEX_LEN_D4_P_2  (VEX_LEN_D3_P_2 + 1)
1138 #define VEX_LEN_D5_P_2  (VEX_LEN_D4_P_2 + 1)
1139 #define VEX_LEN_D6_P_2  (VEX_LEN_D5_P_2 + 1)
1140 #define VEX_LEN_D7_P_2_M_1      (VEX_LEN_D6_P_2 + 1)
1141 #define VEX_LEN_D8_P_2  (VEX_LEN_D7_P_2_M_1 + 1)
1142 #define VEX_LEN_D9_P_2  (VEX_LEN_D8_P_2 + 1)
1143 #define VEX_LEN_DA_P_2  (VEX_LEN_D9_P_2 + 1)
1144 #define VEX_LEN_DB_P_2  (VEX_LEN_DA_P_2 + 1)
1145 #define VEX_LEN_DC_P_2  (VEX_LEN_DB_P_2 + 1)
1146 #define VEX_LEN_DD_P_2  (VEX_LEN_DC_P_2 + 1)
1147 #define VEX_LEN_DE_P_2  (VEX_LEN_DD_P_2 + 1)
1148 #define VEX_LEN_DF_P_2  (VEX_LEN_DE_P_2 + 1)
1149 #define VEX_LEN_E0_P_2  (VEX_LEN_DF_P_2 + 1)
1150 #define VEX_LEN_E1_P_2  (VEX_LEN_E0_P_2 + 1)
1151 #define VEX_LEN_E2_P_2  (VEX_LEN_E1_P_2 + 1)
1152 #define VEX_LEN_E3_P_2  (VEX_LEN_E2_P_2 + 1)
1153 #define VEX_LEN_E4_P_2  (VEX_LEN_E3_P_2 + 1)
1154 #define VEX_LEN_E5_P_2  (VEX_LEN_E4_P_2 + 1)
1155 #define VEX_LEN_E8_P_2  (VEX_LEN_E5_P_2 + 1)
1156 #define VEX_LEN_E9_P_2  (VEX_LEN_E8_P_2 + 1)
1157 #define VEX_LEN_EA_P_2  (VEX_LEN_E9_P_2 + 1)
1158 #define VEX_LEN_EB_P_2  (VEX_LEN_EA_P_2 + 1)
1159 #define VEX_LEN_EC_P_2  (VEX_LEN_EB_P_2 + 1)
1160 #define VEX_LEN_ED_P_2  (VEX_LEN_EC_P_2 + 1)
1161 #define VEX_LEN_EE_P_2  (VEX_LEN_ED_P_2 + 1)
1162 #define VEX_LEN_EF_P_2  (VEX_LEN_EE_P_2 + 1)
1163 #define VEX_LEN_F1_P_2  (VEX_LEN_EF_P_2 + 1)
1164 #define VEX_LEN_F2_P_2  (VEX_LEN_F1_P_2 + 1)
1165 #define VEX_LEN_F3_P_2  (VEX_LEN_F2_P_2 + 1)
1166 #define VEX_LEN_F4_P_2  (VEX_LEN_F3_P_2 + 1)
1167 #define VEX_LEN_F5_P_2  (VEX_LEN_F4_P_2 + 1)
1168 #define VEX_LEN_F6_P_2  (VEX_LEN_F5_P_2 + 1)
1169 #define VEX_LEN_F7_P_2  (VEX_LEN_F6_P_2 + 1)
1170 #define VEX_LEN_F8_P_2  (VEX_LEN_F7_P_2 + 1)
1171 #define VEX_LEN_F9_P_2  (VEX_LEN_F8_P_2 + 1)
1172 #define VEX_LEN_FA_P_2  (VEX_LEN_F9_P_2 + 1)
1173 #define VEX_LEN_FB_P_2  (VEX_LEN_FA_P_2 + 1)
1174 #define VEX_LEN_FC_P_2  (VEX_LEN_FB_P_2 + 1)
1175 #define VEX_LEN_FD_P_2  (VEX_LEN_FC_P_2 + 1)
1176 #define VEX_LEN_FE_P_2  (VEX_LEN_FD_P_2 + 1)
1177 #define VEX_LEN_3800_P_2        (VEX_LEN_FE_P_2 + 1)
1178 #define VEX_LEN_3801_P_2        (VEX_LEN_3800_P_2 + 1)
1179 #define VEX_LEN_3802_P_2        (VEX_LEN_3801_P_2 + 1)
1180 #define VEX_LEN_3803_P_2        (VEX_LEN_3802_P_2 + 1)
1181 #define VEX_LEN_3804_P_2        (VEX_LEN_3803_P_2 + 1)
1182 #define VEX_LEN_3805_P_2        (VEX_LEN_3804_P_2 + 1)
1183 #define VEX_LEN_3806_P_2        (VEX_LEN_3805_P_2 + 1)
1184 #define VEX_LEN_3807_P_2        (VEX_LEN_3806_P_2 + 1)
1185 #define VEX_LEN_3808_P_2        (VEX_LEN_3807_P_2 + 1)
1186 #define VEX_LEN_3809_P_2        (VEX_LEN_3808_P_2 + 1)
1187 #define VEX_LEN_380A_P_2        (VEX_LEN_3809_P_2 + 1)
1188 #define VEX_LEN_380B_P_2        (VEX_LEN_380A_P_2 + 1)
1189 #define VEX_LEN_3819_P_2_M_0    (VEX_LEN_380B_P_2 + 1)
1190 #define VEX_LEN_381A_P_2_M_0    (VEX_LEN_3819_P_2_M_0 + 1)
1191 #define VEX_LEN_381C_P_2        (VEX_LEN_381A_P_2_M_0 + 1)
1192 #define VEX_LEN_381D_P_2        (VEX_LEN_381C_P_2 + 1)
1193 #define VEX_LEN_381E_P_2        (VEX_LEN_381D_P_2 + 1)
1194 #define VEX_LEN_3820_P_2        (VEX_LEN_381E_P_2 + 1)
1195 #define VEX_LEN_3821_P_2        (VEX_LEN_3820_P_2 + 1)
1196 #define VEX_LEN_3822_P_2        (VEX_LEN_3821_P_2 + 1)
1197 #define VEX_LEN_3823_P_2        (VEX_LEN_3822_P_2 + 1)
1198 #define VEX_LEN_3824_P_2        (VEX_LEN_3823_P_2 + 1)
1199 #define VEX_LEN_3825_P_2        (VEX_LEN_3824_P_2 + 1)
1200 #define VEX_LEN_3828_P_2        (VEX_LEN_3825_P_2 + 1)
1201 #define VEX_LEN_3829_P_2        (VEX_LEN_3828_P_2 + 1)
1202 #define VEX_LEN_382A_P_2_M_0    (VEX_LEN_3829_P_2 + 1)
1203 #define VEX_LEN_382B_P_2        (VEX_LEN_382A_P_2_M_0 + 1)
1204 #define VEX_LEN_3830_P_2        (VEX_LEN_382B_P_2 + 1)
1205 #define VEX_LEN_3831_P_2        (VEX_LEN_3830_P_2 + 1)
1206 #define VEX_LEN_3832_P_2        (VEX_LEN_3831_P_2 + 1)
1207 #define VEX_LEN_3833_P_2        (VEX_LEN_3832_P_2 + 1)
1208 #define VEX_LEN_3834_P_2        (VEX_LEN_3833_P_2 + 1)
1209 #define VEX_LEN_3835_P_2        (VEX_LEN_3834_P_2 + 1)
1210 #define VEX_LEN_3837_P_2        (VEX_LEN_3835_P_2 + 1)
1211 #define VEX_LEN_3838_P_2        (VEX_LEN_3837_P_2 + 1)
1212 #define VEX_LEN_3839_P_2        (VEX_LEN_3838_P_2 + 1)
1213 #define VEX_LEN_383A_P_2        (VEX_LEN_3839_P_2 + 1)
1214 #define VEX_LEN_383B_P_2        (VEX_LEN_383A_P_2 + 1)
1215 #define VEX_LEN_383C_P_2        (VEX_LEN_383B_P_2 + 1)
1216 #define VEX_LEN_383D_P_2        (VEX_LEN_383C_P_2 + 1)
1217 #define VEX_LEN_383E_P_2        (VEX_LEN_383D_P_2 + 1)
1218 #define VEX_LEN_383F_P_2        (VEX_LEN_383E_P_2 + 1)
1219 #define VEX_LEN_3840_P_2        (VEX_LEN_383F_P_2 + 1)
1220 #define VEX_LEN_3841_P_2        (VEX_LEN_3840_P_2 + 1)
1221 #define VEX_LEN_38DB_P_2        (VEX_LEN_3841_P_2 + 1)
1222 #define VEX_LEN_38DC_P_2        (VEX_LEN_38DB_P_2 + 1)
1223 #define VEX_LEN_38DD_P_2        (VEX_LEN_38DC_P_2 + 1)
1224 #define VEX_LEN_38DE_P_2        (VEX_LEN_38DD_P_2 + 1)
1225 #define VEX_LEN_38DF_P_2        (VEX_LEN_38DE_P_2 + 1)
1226 #define VEX_LEN_3A06_P_2        (VEX_LEN_38DF_P_2 + 1)
1227 #define VEX_LEN_3A0A_P_2        (VEX_LEN_3A06_P_2 + 1)
1228 #define VEX_LEN_3A0B_P_2        (VEX_LEN_3A0A_P_2 + 1)
1229 #define VEX_LEN_3A0E_P_2        (VEX_LEN_3A0B_P_2 + 1)
1230 #define VEX_LEN_3A0F_P_2        (VEX_LEN_3A0E_P_2 + 1)
1231 #define VEX_LEN_3A14_P_2        (VEX_LEN_3A0F_P_2 + 1)
1232 #define VEX_LEN_3A15_P_2        (VEX_LEN_3A14_P_2 + 1)
1233 #define VEX_LEN_3A16_P_2        (VEX_LEN_3A15_P_2 + 1)
1234 #define VEX_LEN_3A17_P_2        (VEX_LEN_3A16_P_2 + 1)
1235 #define VEX_LEN_3A18_P_2        (VEX_LEN_3A17_P_2 + 1)
1236 #define VEX_LEN_3A19_P_2        (VEX_LEN_3A18_P_2 + 1)
1237 #define VEX_LEN_3A20_P_2        (VEX_LEN_3A19_P_2 + 1)
1238 #define VEX_LEN_3A21_P_2        (VEX_LEN_3A20_P_2 + 1)
1239 #define VEX_LEN_3A22_P_2        (VEX_LEN_3A21_P_2 + 1)
1240 #define VEX_LEN_3A41_P_2        (VEX_LEN_3A22_P_2 + 1)
1241 #define VEX_LEN_3A42_P_2        (VEX_LEN_3A41_P_2 + 1)
1242 #define VEX_LEN_3A4C_P_2        (VEX_LEN_3A42_P_2 + 1)
1243 #define VEX_LEN_3A60_P_2        (VEX_LEN_3A4C_P_2 + 1)
1244 #define VEX_LEN_3A61_P_2        (VEX_LEN_3A60_P_2 + 1)
1245 #define VEX_LEN_3A62_P_2        (VEX_LEN_3A61_P_2 + 1)
1246 #define VEX_LEN_3A63_P_2        (VEX_LEN_3A62_P_2 + 1)
1247 #define VEX_LEN_3ADF_P_2        (VEX_LEN_3A63_P_2 + 1)
1248
1249 typedef void (*op_rtn) (int bytemode, int sizeflag);
1250
1251 struct dis386 {
1252   const char *name;
1253   struct
1254     {
1255       op_rtn rtn;
1256       int bytemode;
1257     } op[MAX_OPERANDS];
1258 };
1259
1260 /* Upper case letters in the instruction names here are macros.
1261    'A' => print 'b' if no register operands or suffix_always is true
1262    'B' => print 'b' if suffix_always is true
1263    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1264           size prefix
1265    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1266           suffix_always is true
1267    'E' => print 'e' if 32-bit form of jcxz
1268    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1269    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1270    'H' => print ",pt" or ",pn" branch hint
1271    'I' => honor following macro letter even in Intel mode (implemented only
1272           for some of the macro letters)
1273    'J' => print 'l'
1274    'K' => print 'd' or 'q' if rex prefix is present.
1275    'L' => print 'l' if suffix_always is true
1276    'M' => print 'r' if intel_mnemonic is false.
1277    'N' => print 'n' if instruction has no wait "prefix"
1278    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1279    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1280           or suffix_always is true.  print 'q' if rex prefix is present.
1281    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1282           is true
1283    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1284    'S' => print 'w', 'l' or 'q' if suffix_always is true
1285    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1286    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1287    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1288    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1289    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1290    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1291           suffix_always is true.
1292    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1293    '!' => change condition from true to false or from false to true.
1294    '%' => add 1 upper case letter to the macro.
1295
1296    2 upper case letter macros:
1297    "XY" => print 'x' or 'y' if no register operands or suffix_always
1298            is true.
1299    'XW' => print 's', 'd' depending on the VEX.W bit (for FMA)
1300    'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1301            or suffix_always is true
1302
1303    Many of the above letters print nothing in Intel mode.  See "putop"
1304    for the details.
1305
1306    Braces '{' and '}', and vertical bars '|', indicate alternative
1307    mnemonic strings for AT&T and Intel.  */
1308
1309 static const struct dis386 dis386[] = {
1310   /* 00 */
1311   { "addB",             { Eb, Gb } },
1312   { "addS",             { Ev, Gv } },
1313   { "addB",             { Gb, EbS } },
1314   { "addS",             { Gv, EvS } },
1315   { "addB",             { AL, Ib } },
1316   { "addS",             { eAX, Iv } },
1317   { X86_64_TABLE (X86_64_06) },
1318   { X86_64_TABLE (X86_64_07) },
1319   /* 08 */
1320   { "orB",              { Eb, Gb } },
1321   { "orS",              { Ev, Gv } },
1322   { "orB",              { Gb, EbS } },
1323   { "orS",              { Gv, EvS } },
1324   { "orB",              { AL, Ib } },
1325   { "orS",              { eAX, Iv } },
1326   { X86_64_TABLE (X86_64_0D) },
1327   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1328   /* 10 */
1329   { "adcB",             { Eb, Gb } },
1330   { "adcS",             { Ev, Gv } },
1331   { "adcB",             { Gb, EbS } },
1332   { "adcS",             { Gv, EvS } },
1333   { "adcB",             { AL, Ib } },
1334   { "adcS",             { eAX, Iv } },
1335   { X86_64_TABLE (X86_64_16) },
1336   { X86_64_TABLE (X86_64_17) },
1337   /* 18 */
1338   { "sbbB",             { Eb, Gb } },
1339   { "sbbS",             { Ev, Gv } },
1340   { "sbbB",             { Gb, EbS } },
1341   { "sbbS",             { Gv, EvS } },
1342   { "sbbB",             { AL, Ib } },
1343   { "sbbS",             { eAX, Iv } },
1344   { X86_64_TABLE (X86_64_1E) },
1345   { X86_64_TABLE (X86_64_1F) },
1346   /* 20 */
1347   { "andB",             { Eb, Gb } },
1348   { "andS",             { Ev, Gv } },
1349   { "andB",             { Gb, EbS } },
1350   { "andS",             { Gv, EvS } },
1351   { "andB",             { AL, Ib } },
1352   { "andS",             { eAX, Iv } },
1353   { "(bad)",            { XX } },       /* SEG ES prefix */
1354   { X86_64_TABLE (X86_64_27) },
1355   /* 28 */
1356   { "subB",             { Eb, Gb } },
1357   { "subS",             { Ev, Gv } },
1358   { "subB",             { Gb, EbS } },
1359   { "subS",             { Gv, EvS } },
1360   { "subB",             { AL, Ib } },
1361   { "subS",             { eAX, Iv } },
1362   { "(bad)",            { XX } },       /* SEG CS prefix */
1363   { X86_64_TABLE (X86_64_2F) },
1364   /* 30 */
1365   { "xorB",             { Eb, Gb } },
1366   { "xorS",             { Ev, Gv } },
1367   { "xorB",             { Gb, EbS } },
1368   { "xorS",             { Gv, EvS } },
1369   { "xorB",             { AL, Ib } },
1370   { "xorS",             { eAX, Iv } },
1371   { "(bad)",            { XX } },       /* SEG SS prefix */
1372   { X86_64_TABLE (X86_64_37) },
1373   /* 38 */
1374   { "cmpB",             { Eb, Gb } },
1375   { "cmpS",             { Ev, Gv } },
1376   { "cmpB",             { Gb, EbS } },
1377   { "cmpS",             { Gv, EvS } },
1378   { "cmpB",             { AL, Ib } },
1379   { "cmpS",             { eAX, Iv } },
1380   { "(bad)",            { XX } },       /* SEG DS prefix */
1381   { X86_64_TABLE (X86_64_3F) },
1382   /* 40 */
1383   { "inc{S|}",          { RMeAX } },
1384   { "inc{S|}",          { RMeCX } },
1385   { "inc{S|}",          { RMeDX } },
1386   { "inc{S|}",          { RMeBX } },
1387   { "inc{S|}",          { RMeSP } },
1388   { "inc{S|}",          { RMeBP } },
1389   { "inc{S|}",          { RMeSI } },
1390   { "inc{S|}",          { RMeDI } },
1391   /* 48 */
1392   { "dec{S|}",          { RMeAX } },
1393   { "dec{S|}",          { RMeCX } },
1394   { "dec{S|}",          { RMeDX } },
1395   { "dec{S|}",          { RMeBX } },
1396   { "dec{S|}",          { RMeSP } },
1397   { "dec{S|}",          { RMeBP } },
1398   { "dec{S|}",          { RMeSI } },
1399   { "dec{S|}",          { RMeDI } },
1400   /* 50 */
1401   { "pushV",            { RMrAX } },
1402   { "pushV",            { RMrCX } },
1403   { "pushV",            { RMrDX } },
1404   { "pushV",            { RMrBX } },
1405   { "pushV",            { RMrSP } },
1406   { "pushV",            { RMrBP } },
1407   { "pushV",            { RMrSI } },
1408   { "pushV",            { RMrDI } },
1409   /* 58 */
1410   { "popV",             { RMrAX } },
1411   { "popV",             { RMrCX } },
1412   { "popV",             { RMrDX } },
1413   { "popV",             { RMrBX } },
1414   { "popV",             { RMrSP } },
1415   { "popV",             { RMrBP } },
1416   { "popV",             { RMrSI } },
1417   { "popV",             { RMrDI } },
1418   /* 60 */
1419   { X86_64_TABLE (X86_64_60) },
1420   { X86_64_TABLE (X86_64_61) },
1421   { X86_64_TABLE (X86_64_62) },
1422   { X86_64_TABLE (X86_64_63) },
1423   { "(bad)",            { XX } },       /* seg fs */
1424   { "(bad)",            { XX } },       /* seg gs */
1425   { "(bad)",            { XX } },       /* op size prefix */
1426   { "(bad)",            { XX } },       /* adr size prefix */
1427   /* 68 */
1428   { "pushT",            { Iq } },
1429   { "imulS",            { Gv, Ev, Iv } },
1430   { "pushT",            { sIb } },
1431   { "imulS",            { Gv, Ev, sIb } },
1432   { "ins{b|}",          { Ybr, indirDX } },
1433   { X86_64_TABLE (X86_64_6D) },
1434   { "outs{b|}",         { indirDXr, Xb } },
1435   { X86_64_TABLE (X86_64_6F) },
1436   /* 70 */
1437   { "joH",              { Jb, XX, cond_jump_flag } },
1438   { "jnoH",             { Jb, XX, cond_jump_flag } },
1439   { "jbH",              { Jb, XX, cond_jump_flag } },
1440   { "jaeH",             { Jb, XX, cond_jump_flag } },
1441   { "jeH",              { Jb, XX, cond_jump_flag } },
1442   { "jneH",             { Jb, XX, cond_jump_flag } },
1443   { "jbeH",             { Jb, XX, cond_jump_flag } },
1444   { "jaH",              { Jb, XX, cond_jump_flag } },
1445   /* 78 */
1446   { "jsH",              { Jb, XX, cond_jump_flag } },
1447   { "jnsH",             { Jb, XX, cond_jump_flag } },
1448   { "jpH",              { Jb, XX, cond_jump_flag } },
1449   { "jnpH",             { Jb, XX, cond_jump_flag } },
1450   { "jlH",              { Jb, XX, cond_jump_flag } },
1451   { "jgeH",             { Jb, XX, cond_jump_flag } },
1452   { "jleH",             { Jb, XX, cond_jump_flag } },
1453   { "jgH",              { Jb, XX, cond_jump_flag } },
1454   /* 80 */
1455   { REG_TABLE (REG_80) },
1456   { REG_TABLE (REG_81) },
1457   { "(bad)",            { XX } },
1458   { REG_TABLE (REG_82) },
1459   { "testB",            { Eb, Gb } },
1460   { "testS",            { Ev, Gv } },
1461   { "xchgB",            { Eb, Gb } },
1462   { "xchgS",            { Ev, Gv } },
1463   /* 88 */
1464   { "movB",             { Eb, Gb } },
1465   { "movS",             { Ev, Gv } },
1466   { "movB",             { Gb, EbS } },
1467   { "movS",             { Gv, EvS } },
1468   { "movD",             { Sv, Sw } },
1469   { MOD_TABLE (MOD_8D) },
1470   { "movD",             { Sw, Sv } },
1471   { REG_TABLE (REG_8F) },
1472   /* 90 */
1473   { PREFIX_TABLE (PREFIX_90) },
1474   { "xchgS",            { RMeCX, eAX } },
1475   { "xchgS",            { RMeDX, eAX } },
1476   { "xchgS",            { RMeBX, eAX } },
1477   { "xchgS",            { RMeSP, eAX } },
1478   { "xchgS",            { RMeBP, eAX } },
1479   { "xchgS",            { RMeSI, eAX } },
1480   { "xchgS",            { RMeDI, eAX } },
1481   /* 98 */
1482   { "cW{t|}R",          { XX } },
1483   { "cR{t|}O",          { XX } },
1484   { X86_64_TABLE (X86_64_9A) },
1485   { "(bad)",            { XX } },       /* fwait */
1486   { "pushfT",           { XX } },
1487   { "popfT",            { XX } },
1488   { "sahf",             { XX } },
1489   { "lahf",             { XX } },
1490   /* a0 */
1491   { "movB",             { AL, Ob } },
1492   { "movS",             { eAX, Ov } },
1493   { "movB",             { Ob, AL } },
1494   { "movS",             { Ov, eAX } },
1495   { "movs{b|}",         { Ybr, Xb } },
1496   { "movs{R|}",         { Yvr, Xv } },
1497   { "cmps{b|}",         { Xb, Yb } },
1498   { "cmps{R|}",         { Xv, Yv } },
1499   /* a8 */
1500   { "testB",            { AL, Ib } },
1501   { "testS",            { eAX, Iv } },
1502   { "stosB",            { Ybr, AL } },
1503   { "stosS",            { Yvr, eAX } },
1504   { "lodsB",            { ALr, Xb } },
1505   { "lodsS",            { eAXr, Xv } },
1506   { "scasB",            { AL, Yb } },
1507   { "scasS",            { eAX, Yv } },
1508   /* b0 */
1509   { "movB",             { RMAL, Ib } },
1510   { "movB",             { RMCL, Ib } },
1511   { "movB",             { RMDL, Ib } },
1512   { "movB",             { RMBL, Ib } },
1513   { "movB",             { RMAH, Ib } },
1514   { "movB",             { RMCH, Ib } },
1515   { "movB",             { RMDH, Ib } },
1516   { "movB",             { RMBH, Ib } },
1517   /* b8 */
1518   { "movS",             { RMeAX, Iv64 } },
1519   { "movS",             { RMeCX, Iv64 } },
1520   { "movS",             { RMeDX, Iv64 } },
1521   { "movS",             { RMeBX, Iv64 } },
1522   { "movS",             { RMeSP, Iv64 } },
1523   { "movS",             { RMeBP, Iv64 } },
1524   { "movS",             { RMeSI, Iv64 } },
1525   { "movS",             { RMeDI, Iv64 } },
1526   /* c0 */
1527   { REG_TABLE (REG_C0) },
1528   { REG_TABLE (REG_C1) },
1529   { "retT",             { Iw } },
1530   { "retT",             { XX } },
1531   { X86_64_TABLE (X86_64_C4) },
1532   { X86_64_TABLE (X86_64_C5) },
1533   { REG_TABLE (REG_C6) },
1534   { REG_TABLE (REG_C7) },
1535   /* c8 */
1536   { "enterT",           { Iw, Ib } },
1537   { "leaveT",           { XX } },
1538   { "Jret{|f}P",        { Iw } },
1539   { "Jret{|f}P",        { XX } },
1540   { "int3",             { XX } },
1541   { "int",              { Ib } },
1542   { X86_64_TABLE (X86_64_CE) },
1543   { "iretP",            { XX } },
1544   /* d0 */
1545   { REG_TABLE (REG_D0) },
1546   { REG_TABLE (REG_D1) },
1547   { REG_TABLE (REG_D2) },
1548   { REG_TABLE (REG_D3) },
1549   { X86_64_TABLE (X86_64_D4) },
1550   { X86_64_TABLE (X86_64_D5) },
1551   { "(bad)",            { XX } },
1552   { "xlat",             { DSBX } },
1553   /* d8 */
1554   { FLOAT },
1555   { FLOAT },
1556   { FLOAT },
1557   { FLOAT },
1558   { FLOAT },
1559   { FLOAT },
1560   { FLOAT },
1561   { FLOAT },
1562   /* e0 */
1563   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1564   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1565   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1566   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1567   { "inB",              { AL, Ib } },
1568   { "inG",              { zAX, Ib } },
1569   { "outB",             { Ib, AL } },
1570   { "outG",             { Ib, zAX } },
1571   /* e8 */
1572   { "callT",            { Jv } },
1573   { "jmpT",             { Jv } },
1574   { X86_64_TABLE (X86_64_EA) },
1575   { "jmp",              { Jb } },
1576   { "inB",              { AL, indirDX } },
1577   { "inG",              { zAX, indirDX } },
1578   { "outB",             { indirDX, AL } },
1579   { "outG",             { indirDX, zAX } },
1580   /* f0 */
1581   { "(bad)",            { XX } },       /* lock prefix */
1582   { "icebp",            { XX } },
1583   { "(bad)",            { XX } },       /* repne */
1584   { "(bad)",            { XX } },       /* repz */
1585   { "hlt",              { XX } },
1586   { "cmc",              { XX } },
1587   { REG_TABLE (REG_F6) },
1588   { REG_TABLE (REG_F7) },
1589   /* f8 */
1590   { "clc",              { XX } },
1591   { "stc",              { XX } },
1592   { "cli",              { XX } },
1593   { "sti",              { XX } },
1594   { "cld",              { XX } },
1595   { "std",              { XX } },
1596   { REG_TABLE (REG_FE) },
1597   { REG_TABLE (REG_FF) },
1598 };
1599
1600 static const struct dis386 dis386_twobyte[] = {
1601   /* 00 */
1602   { REG_TABLE (REG_0F00 ) },
1603   { REG_TABLE (REG_0F01 ) },
1604   { "larS",             { Gv, Ew } },
1605   { "lslS",             { Gv, Ew } },
1606   { "(bad)",            { XX } },
1607   { "syscall",          { XX } },
1608   { "clts",             { XX } },
1609   { "sysretP",          { XX } },
1610   /* 08 */
1611   { "invd",             { XX } },
1612   { "wbinvd",           { XX } },
1613   { "(bad)",            { XX } },
1614   { "ud2a",             { XX } },
1615   { "(bad)",            { XX } },
1616   { REG_TABLE (REG_0F0D) },
1617   { "femms",            { XX } },
1618   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1619   /* 10 */
1620   { PREFIX_TABLE (PREFIX_0F10) },
1621   { PREFIX_TABLE (PREFIX_0F11) },
1622   { PREFIX_TABLE (PREFIX_0F12) },
1623   { MOD_TABLE (MOD_0F13) },
1624   { "unpcklpX",         { XM, EXx } },
1625   { "unpckhpX",         { XM, EXx } },
1626   { PREFIX_TABLE (PREFIX_0F16) },
1627   { MOD_TABLE (MOD_0F17) },
1628   /* 18 */
1629   { REG_TABLE (REG_0F18) },
1630   { "nopQ",             { Ev } },
1631   { "nopQ",             { Ev } },
1632   { "nopQ",             { Ev } },
1633   { "nopQ",             { Ev } },
1634   { "nopQ",             { Ev } },
1635   { "nopQ",             { Ev } },
1636   { "nopQ",             { Ev } },
1637   /* 20 */
1638   { MOD_TABLE (MOD_0F20) },
1639   { MOD_TABLE (MOD_0F21) },
1640   { MOD_TABLE (MOD_0F22) },
1641   { MOD_TABLE (MOD_0F23) },
1642   { MOD_TABLE (MOD_0F24) },
1643   { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1644   { MOD_TABLE (MOD_0F26) },
1645   { "(bad)",            { XX } },
1646   /* 28 */
1647   { "movapX",           { XM, EXx } },
1648   { "movapX",           { EXxS, XM } },
1649   { PREFIX_TABLE (PREFIX_0F2A) },
1650   { PREFIX_TABLE (PREFIX_0F2B) },
1651   { PREFIX_TABLE (PREFIX_0F2C) },
1652   { PREFIX_TABLE (PREFIX_0F2D) },
1653   { PREFIX_TABLE (PREFIX_0F2E) },
1654   { PREFIX_TABLE (PREFIX_0F2F) },
1655   /* 30 */
1656   { "wrmsr",            { XX } },
1657   { "rdtsc",            { XX } },
1658   { "rdmsr",            { XX } },
1659   { "rdpmc",            { XX } },
1660   { "sysenter",         { XX } },
1661   { "sysexit",          { XX } },
1662   { "(bad)",            { XX } },
1663   { "getsec",           { XX } },
1664   /* 38 */
1665   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1666   { "(bad)",            { XX } },
1667   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1668   { "(bad)",            { XX } },
1669   { "(bad)",            { XX } },
1670   { "(bad)",            { XX } },
1671   { "(bad)",            { XX } },
1672   { "(bad)",            { XX } },
1673   /* 40 */
1674   { "cmovoS",           { Gv, Ev } },
1675   { "cmovnoS",          { Gv, Ev } },
1676   { "cmovbS",           { Gv, Ev } },
1677   { "cmovaeS",          { Gv, Ev } },
1678   { "cmoveS",           { Gv, Ev } },
1679   { "cmovneS",          { Gv, Ev } },
1680   { "cmovbeS",          { Gv, Ev } },
1681   { "cmovaS",           { Gv, Ev } },
1682   /* 48 */
1683   { "cmovsS",           { Gv, Ev } },
1684   { "cmovnsS",          { Gv, Ev } },
1685   { "cmovpS",           { Gv, Ev } },
1686   { "cmovnpS",          { Gv, Ev } },
1687   { "cmovlS",           { Gv, Ev } },
1688   { "cmovgeS",          { Gv, Ev } },
1689   { "cmovleS",          { Gv, Ev } },
1690   { "cmovgS",           { Gv, Ev } },
1691   /* 50 */
1692   { MOD_TABLE (MOD_0F51) },
1693   { PREFIX_TABLE (PREFIX_0F51) },
1694   { PREFIX_TABLE (PREFIX_0F52) },
1695   { PREFIX_TABLE (PREFIX_0F53) },
1696   { "andpX",            { XM, EXx } },
1697   { "andnpX",           { XM, EXx } },
1698   { "orpX",             { XM, EXx } },
1699   { "xorpX",            { XM, EXx } },
1700   /* 58 */
1701   { PREFIX_TABLE (PREFIX_0F58) },
1702   { PREFIX_TABLE (PREFIX_0F59) },
1703   { PREFIX_TABLE (PREFIX_0F5A) },
1704   { PREFIX_TABLE (PREFIX_0F5B) },
1705   { PREFIX_TABLE (PREFIX_0F5C) },
1706   { PREFIX_TABLE (PREFIX_0F5D) },
1707   { PREFIX_TABLE (PREFIX_0F5E) },
1708   { PREFIX_TABLE (PREFIX_0F5F) },
1709   /* 60 */
1710   { PREFIX_TABLE (PREFIX_0F60) },
1711   { PREFIX_TABLE (PREFIX_0F61) },
1712   { PREFIX_TABLE (PREFIX_0F62) },
1713   { "packsswb",         { MX, EM } },
1714   { "pcmpgtb",          { MX, EM } },
1715   { "pcmpgtw",          { MX, EM } },
1716   { "pcmpgtd",          { MX, EM } },
1717   { "packuswb",         { MX, EM } },
1718   /* 68 */
1719   { "punpckhbw",        { MX, EM } },
1720   { "punpckhwd",        { MX, EM } },
1721   { "punpckhdq",        { MX, EM } },
1722   { "packssdw",         { MX, EM } },
1723   { PREFIX_TABLE (PREFIX_0F6C) },
1724   { PREFIX_TABLE (PREFIX_0F6D) },
1725   { "movK",             { MX, Edq } },
1726   { PREFIX_TABLE (PREFIX_0F6F) },
1727   /* 70 */
1728   { PREFIX_TABLE (PREFIX_0F70) },
1729   { REG_TABLE (REG_0F71) },
1730   { REG_TABLE (REG_0F72) },
1731   { REG_TABLE (REG_0F73) },
1732   { "pcmpeqb",          { MX, EM } },
1733   { "pcmpeqw",          { MX, EM } },
1734   { "pcmpeqd",          { MX, EM } },
1735   { "emms",             { XX } },
1736   /* 78 */
1737   { PREFIX_TABLE (PREFIX_0F78) },
1738   { PREFIX_TABLE (PREFIX_0F79) },
1739   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1740   { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1741   { PREFIX_TABLE (PREFIX_0F7C) },
1742   { PREFIX_TABLE (PREFIX_0F7D) },
1743   { PREFIX_TABLE (PREFIX_0F7E) },
1744   { PREFIX_TABLE (PREFIX_0F7F) },
1745   /* 80 */
1746   { "joH",              { Jv, XX, cond_jump_flag } },
1747   { "jnoH",             { Jv, XX, cond_jump_flag } },
1748   { "jbH",              { Jv, XX, cond_jump_flag } },
1749   { "jaeH",             { Jv, XX, cond_jump_flag } },
1750   { "jeH",              { Jv, XX, cond_jump_flag } },
1751   { "jneH",             { Jv, XX, cond_jump_flag } },
1752   { "jbeH",             { Jv, XX, cond_jump_flag } },
1753   { "jaH",              { Jv, XX, cond_jump_flag } },
1754   /* 88 */
1755   { "jsH",              { Jv, XX, cond_jump_flag } },
1756   { "jnsH",             { Jv, XX, cond_jump_flag } },
1757   { "jpH",              { Jv, XX, cond_jump_flag } },
1758   { "jnpH",             { Jv, XX, cond_jump_flag } },
1759   { "jlH",              { Jv, XX, cond_jump_flag } },
1760   { "jgeH",             { Jv, XX, cond_jump_flag } },
1761   { "jleH",             { Jv, XX, cond_jump_flag } },
1762   { "jgH",              { Jv, XX, cond_jump_flag } },
1763   /* 90 */
1764   { "seto",             { Eb } },
1765   { "setno",            { Eb } },
1766   { "setb",             { Eb } },
1767   { "setae",            { Eb } },
1768   { "sete",             { Eb } },
1769   { "setne",            { Eb } },
1770   { "setbe",            { Eb } },
1771   { "seta",             { Eb } },
1772   /* 98 */
1773   { "sets",             { Eb } },
1774   { "setns",            { Eb } },
1775   { "setp",             { Eb } },
1776   { "setnp",            { Eb } },
1777   { "setl",             { Eb } },
1778   { "setge",            { Eb } },
1779   { "setle",            { Eb } },
1780   { "setg",             { Eb } },
1781   /* a0 */
1782   { "pushT",            { fs } },
1783   { "popT",             { fs } },
1784   { "cpuid",            { XX } },
1785   { "btS",              { Ev, Gv } },
1786   { "shldS",            { Ev, Gv, Ib } },
1787   { "shldS",            { Ev, Gv, CL } },
1788   { REG_TABLE (REG_0FA6) },
1789   { REG_TABLE (REG_0FA7) },
1790   /* a8 */
1791   { "pushT",            { gs } },
1792   { "popT",             { gs } },
1793   { "rsm",              { XX } },
1794   { "btsS",             { Ev, Gv } },
1795   { "shrdS",            { Ev, Gv, Ib } },
1796   { "shrdS",            { Ev, Gv, CL } },
1797   { REG_TABLE (REG_0FAE) },
1798   { "imulS",            { Gv, Ev } },
1799   /* b0 */
1800   { "cmpxchgB",         { Eb, Gb } },
1801   { "cmpxchgS",         { Ev, Gv } },
1802   { MOD_TABLE (MOD_0FB2) },
1803   { "btrS",             { Ev, Gv } },
1804   { MOD_TABLE (MOD_0FB4) },
1805   { MOD_TABLE (MOD_0FB5) },
1806   { "movz{bR|x}",       { Gv, Eb } },
1807   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1808   /* b8 */
1809   { PREFIX_TABLE (PREFIX_0FB8) },
1810   { "ud2b",             { XX } },
1811   { REG_TABLE (REG_0FBA) },
1812   { "btcS",             { Ev, Gv } },
1813   { "bsfS",             { Gv, Ev } },
1814   { PREFIX_TABLE (PREFIX_0FBD) },
1815   { "movs{bR|x}",       { Gv, Eb } },
1816   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1817   /* c0 */
1818   { "xaddB",            { Eb, Gb } },
1819   { "xaddS",            { Ev, Gv } },
1820   { PREFIX_TABLE (PREFIX_0FC2) },
1821   { PREFIX_TABLE (PREFIX_0FC3) },
1822   { "pinsrw",           { MX, Edqw, Ib } },
1823   { "pextrw",           { Gdq, MS, Ib } },
1824   { "shufpX",           { XM, EXx, Ib } },
1825   { REG_TABLE (REG_0FC7) },
1826   /* c8 */
1827   { "bswap",            { RMeAX } },
1828   { "bswap",            { RMeCX } },
1829   { "bswap",            { RMeDX } },
1830   { "bswap",            { RMeBX } },
1831   { "bswap",            { RMeSP } },
1832   { "bswap",            { RMeBP } },
1833   { "bswap",            { RMeSI } },
1834   { "bswap",            { RMeDI } },
1835   /* d0 */
1836   { PREFIX_TABLE (PREFIX_0FD0) },
1837   { "psrlw",            { MX, EM } },
1838   { "psrld",            { MX, EM } },
1839   { "psrlq",            { MX, EM } },
1840   { "paddq",            { MX, EM } },
1841   { "pmullw",           { MX, EM } },
1842   { PREFIX_TABLE (PREFIX_0FD6) },
1843   { MOD_TABLE (MOD_0FD7) },
1844   /* d8 */
1845   { "psubusb",          { MX, EM } },
1846   { "psubusw",          { MX, EM } },
1847   { "pminub",           { MX, EM } },
1848   { "pand",             { MX, EM } },
1849   { "paddusb",          { MX, EM } },
1850   { "paddusw",          { MX, EM } },
1851   { "pmaxub",           { MX, EM } },
1852   { "pandn",            { MX, EM } },
1853   /* e0 */
1854   { "pavgb",            { MX, EM } },
1855   { "psraw",            { MX, EM } },
1856   { "psrad",            { MX, EM } },
1857   { "pavgw",            { MX, EM } },
1858   { "pmulhuw",          { MX, EM } },
1859   { "pmulhw",           { MX, EM } },
1860   { PREFIX_TABLE (PREFIX_0FE6) },
1861   { PREFIX_TABLE (PREFIX_0FE7) },
1862   /* e8 */
1863   { "psubsb",           { MX, EM } },
1864   { "psubsw",           { MX, EM } },
1865   { "pminsw",           { MX, EM } },
1866   { "por",              { MX, EM } },
1867   { "paddsb",           { MX, EM } },
1868   { "paddsw",           { MX, EM } },
1869   { "pmaxsw",           { MX, EM } },
1870   { "pxor",             { MX, EM } },
1871   /* f0 */
1872   { PREFIX_TABLE (PREFIX_0FF0) },
1873   { "psllw",            { MX, EM } },
1874   { "pslld",            { MX, EM } },
1875   { "psllq",            { MX, EM } },
1876   { "pmuludq",          { MX, EM } },
1877   { "pmaddwd",          { MX, EM } },
1878   { "psadbw",           { MX, EM } },
1879   { PREFIX_TABLE (PREFIX_0FF7) },
1880   /* f8 */
1881   { "psubb",            { MX, EM } },
1882   { "psubw",            { MX, EM } },
1883   { "psubd",            { MX, EM } },
1884   { "psubq",            { MX, EM } },
1885   { "paddb",            { MX, EM } },
1886   { "paddw",            { MX, EM } },
1887   { "paddd",            { MX, EM } },
1888   { "(bad)",            { XX } },
1889 };
1890
1891 static const unsigned char onebyte_has_modrm[256] = {
1892   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1893   /*       -------------------------------        */
1894   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1895   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1896   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1897   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1898   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1899   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1900   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1901   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1902   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1903   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1904   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1905   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1906   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1907   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1908   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1909   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1910   /*       -------------------------------        */
1911   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1912 };
1913
1914 static const unsigned char twobyte_has_modrm[256] = {
1915   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1916   /*       -------------------------------        */
1917   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1918   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1919   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1920   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1921   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1922   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1923   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1924   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1925   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1926   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1927   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1928   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1929   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1930   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1931   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1932   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1933   /*       -------------------------------        */
1934   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1935 };
1936
1937 static char obuf[100];
1938 static char *obufp;
1939 static char *mnemonicendp;
1940 static char scratchbuf[100];
1941 static unsigned char *start_codep;
1942 static unsigned char *insn_codep;
1943 static unsigned char *codep;
1944 static const char *lock_prefix;
1945 static const char *data_prefix;
1946 static const char *addr_prefix;
1947 static const char *repz_prefix;
1948 static const char *repnz_prefix;
1949 static disassemble_info *the_info;
1950 static struct
1951   {
1952     int mod;
1953     int reg;
1954     int rm;
1955   }
1956 modrm;
1957 static unsigned char need_modrm;
1958 static struct
1959   {
1960     int register_specifier;
1961     int length;
1962     int prefix;
1963     int w;
1964   }
1965 vex;
1966 static unsigned char need_vex;
1967 static unsigned char need_vex_reg;
1968 static unsigned char vex_w_done;
1969
1970 struct op
1971   {
1972     const char *name;
1973     unsigned int len;
1974   };
1975
1976 /* If we are accessing mod/rm/reg without need_modrm set, then the
1977    values are stale.  Hitting this abort likely indicates that you
1978    need to update onebyte_has_modrm or twobyte_has_modrm.  */
1979 #define MODRM_CHECK  if (!need_modrm) abort ()
1980
1981 static const char **names64;
1982 static const char **names32;
1983 static const char **names16;
1984 static const char **names8;
1985 static const char **names8rex;
1986 static const char **names_seg;
1987 static const char *index64;
1988 static const char *index32;
1989 static const char **index16;
1990
1991 static const char *intel_names64[] = {
1992   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1993   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1994 };
1995 static const char *intel_names32[] = {
1996   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1997   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1998 };
1999 static const char *intel_names16[] = {
2000   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2001   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2002 };
2003 static const char *intel_names8[] = {
2004   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2005 };
2006 static const char *intel_names8rex[] = {
2007   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2008   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2009 };
2010 static const char *intel_names_seg[] = {
2011   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2012 };
2013 static const char *intel_index64 = "riz";
2014 static const char *intel_index32 = "eiz";
2015 static const char *intel_index16[] = {
2016   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2017 };
2018
2019 static const char *att_names64[] = {
2020   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2021   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2022 };
2023 static const char *att_names32[] = {
2024   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2025   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2026 };
2027 static const char *att_names16[] = {
2028   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2029   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2030 };
2031 static const char *att_names8[] = {
2032   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2033 };
2034 static const char *att_names8rex[] = {
2035   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2036   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2037 };
2038 static const char *att_names_seg[] = {
2039   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2040 };
2041 static const char *att_index64 = "%riz";
2042 static const char *att_index32 = "%eiz";
2043 static const char *att_index16[] = {
2044   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2045 };
2046
2047 static const struct dis386 reg_table[][8] = {
2048   /* REG_80 */
2049   {
2050     { "addA",   { Eb, Ib } },
2051     { "orA",    { Eb, Ib } },
2052     { "adcA",   { Eb, Ib } },
2053     { "sbbA",   { Eb, Ib } },
2054     { "andA",   { Eb, Ib } },
2055     { "subA",   { Eb, Ib } },
2056     { "xorA",   { Eb, Ib } },
2057     { "cmpA",   { Eb, Ib } },
2058   },
2059   /* REG_81 */
2060   {
2061     { "addQ",   { Ev, Iv } },
2062     { "orQ",    { Ev, Iv } },
2063     { "adcQ",   { Ev, Iv } },
2064     { "sbbQ",   { Ev, Iv } },
2065     { "andQ",   { Ev, Iv } },
2066     { "subQ",   { Ev, Iv } },
2067     { "xorQ",   { Ev, Iv } },
2068     { "cmpQ",   { Ev, Iv } },
2069   },
2070   /* REG_82 */
2071   {
2072     { "addQ",   { Ev, sIb } },
2073     { "orQ",    { Ev, sIb } },
2074     { "adcQ",   { Ev, sIb } },
2075     { "sbbQ",   { Ev, sIb } },
2076     { "andQ",   { Ev, sIb } },
2077     { "subQ",   { Ev, sIb } },
2078     { "xorQ",   { Ev, sIb } },
2079     { "cmpQ",   { Ev, sIb } },
2080   },
2081   /* REG_8F */
2082   {
2083     { "popU",   { stackEv } },
2084     { "(bad)",  { XX } },
2085     { "(bad)",  { XX } },
2086     { "(bad)",  { XX } },
2087     { "(bad)",  { XX } },
2088     { "(bad)",  { XX } },
2089     { "(bad)",  { XX } },
2090     { "(bad)",  { XX } },
2091   },
2092   /* REG_C0 */
2093   {
2094     { "rolA",   { Eb, Ib } },
2095     { "rorA",   { Eb, Ib } },
2096     { "rclA",   { Eb, Ib } },
2097     { "rcrA",   { Eb, Ib } },
2098     { "shlA",   { Eb, Ib } },
2099     { "shrA",   { Eb, Ib } },
2100     { "(bad)",  { XX } },
2101     { "sarA",   { Eb, Ib } },
2102   },
2103   /* REG_C1 */
2104   {
2105     { "rolQ",   { Ev, Ib } },
2106     { "rorQ",   { Ev, Ib } },
2107     { "rclQ",   { Ev, Ib } },
2108     { "rcrQ",   { Ev, Ib } },
2109     { "shlQ",   { Ev, Ib } },
2110     { "shrQ",   { Ev, Ib } },
2111     { "(bad)",  { XX } },
2112     { "sarQ",   { Ev, Ib } },
2113   },
2114   /* REG_C6 */
2115   {
2116     { "movA",   { Eb, Ib } },
2117     { "(bad)",  { XX } },
2118     { "(bad)",  { XX } },
2119     { "(bad)",  { XX } },
2120     { "(bad)",  { XX } },
2121     { "(bad)",  { XX } },
2122     { "(bad)",  { XX } },
2123     { "(bad)",  { XX } },
2124   },
2125   /* REG_C7 */
2126   {
2127     { "movQ",   { Ev, Iv } },
2128     { "(bad)",  { XX } },
2129     { "(bad)",  { XX } },
2130     { "(bad)",  { XX } },
2131     { "(bad)",  { XX } },
2132     { "(bad)",  { XX } },
2133     { "(bad)",  { XX } },
2134     { "(bad)",  { XX } },
2135   },
2136   /* REG_D0 */
2137   {
2138     { "rolA",   { Eb, I1 } },
2139     { "rorA",   { Eb, I1 } },
2140     { "rclA",   { Eb, I1 } },
2141     { "rcrA",   { Eb, I1 } },
2142     { "shlA",   { Eb, I1 } },
2143     { "shrA",   { Eb, I1 } },
2144     { "(bad)",  { XX } },
2145     { "sarA",   { Eb, I1 } },
2146   },
2147   /* REG_D1 */
2148   {
2149     { "rolQ",   { Ev, I1 } },
2150     { "rorQ",   { Ev, I1 } },
2151     { "rclQ",   { Ev, I1 } },
2152     { "rcrQ",   { Ev, I1 } },
2153     { "shlQ",   { Ev, I1 } },
2154     { "shrQ",   { Ev, I1 } },
2155     { "(bad)",  { XX } },
2156     { "sarQ",   { Ev, I1 } },
2157   },
2158   /* REG_D2 */
2159   {
2160     { "rolA",   { Eb, CL } },
2161     { "rorA",   { Eb, CL } },
2162     { "rclA",   { Eb, CL } },
2163     { "rcrA",   { Eb, CL } },
2164     { "shlA",   { Eb, CL } },
2165     { "shrA",   { Eb, CL } },
2166     { "(bad)",  { XX } },
2167     { "sarA",   { Eb, CL } },
2168   },
2169   /* REG_D3 */
2170   {
2171     { "rolQ",   { Ev, CL } },
2172     { "rorQ",   { Ev, CL } },
2173     { "rclQ",   { Ev, CL } },
2174     { "rcrQ",   { Ev, CL } },
2175     { "shlQ",   { Ev, CL } },
2176     { "shrQ",   { Ev, CL } },
2177     { "(bad)",  { XX } },
2178     { "sarQ",   { Ev, CL } },
2179   },
2180   /* REG_F6 */
2181   {
2182     { "testA",  { Eb, Ib } },
2183     { "(bad)",  { XX } },
2184     { "notA",   { Eb } },
2185     { "negA",   { Eb } },
2186     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2187     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2188     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2189     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2190   },
2191   /* REG_F7 */
2192   {
2193     { "testQ",  { Ev, Iv } },
2194     { "(bad)",  { XX } },
2195     { "notQ",   { Ev } },
2196     { "negQ",   { Ev } },
2197     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2198     { "imulQ",  { Ev } },
2199     { "divQ",   { Ev } },
2200     { "idivQ",  { Ev } },
2201   },
2202   /* REG_FE */
2203   {
2204     { "incA",   { Eb } },
2205     { "decA",   { Eb } },
2206     { "(bad)",  { XX } },
2207     { "(bad)",  { XX } },
2208     { "(bad)",  { XX } },
2209     { "(bad)",  { XX } },
2210     { "(bad)",  { XX } },
2211     { "(bad)",  { XX } },
2212   },
2213   /* REG_FF */
2214   {
2215     { "incQ",   { Ev } },
2216     { "decQ",   { Ev } },
2217     { "callT",  { indirEv } },
2218     { "JcallT", { indirEp } },
2219     { "jmpT",   { indirEv } },
2220     { "JjmpT",  { indirEp } },
2221     { "pushU",  { stackEv } },
2222     { "(bad)",  { XX } },
2223   },
2224   /* REG_0F00 */
2225   {
2226     { "sldtD",  { Sv } },
2227     { "strD",   { Sv } },
2228     { "lldt",   { Ew } },
2229     { "ltr",    { Ew } },
2230     { "verr",   { Ew } },
2231     { "verw",   { Ew } },
2232     { "(bad)",  { XX } },
2233     { "(bad)",  { XX } },
2234   },
2235   /* REG_0F01 */
2236   {
2237     { MOD_TABLE (MOD_0F01_REG_0) },
2238     { MOD_TABLE (MOD_0F01_REG_1) },
2239     { MOD_TABLE (MOD_0F01_REG_2) },
2240     { MOD_TABLE (MOD_0F01_REG_3) },
2241     { "smswD",  { Sv } },
2242     { "(bad)",  { XX } },
2243     { "lmsw",   { Ew } },
2244     { MOD_TABLE (MOD_0F01_REG_7) },
2245   },
2246   /* REG_0F0D */
2247   {
2248     { "prefetch",       { Eb } },
2249     { "prefetchw",      { Eb } },
2250     { "(bad)",          { XX } },
2251     { "(bad)",          { XX } },
2252     { "(bad)",          { XX } },
2253     { "(bad)",          { XX } },
2254     { "(bad)",          { XX } },
2255     { "(bad)",          { XX } },
2256   },
2257   /* REG_0F18 */
2258   {
2259     { MOD_TABLE (MOD_0F18_REG_0) },
2260     { MOD_TABLE (MOD_0F18_REG_1) },
2261     { MOD_TABLE (MOD_0F18_REG_2) },
2262     { MOD_TABLE (MOD_0F18_REG_3) },
2263     { "(bad)",  { XX } },
2264     { "(bad)",  { XX } },
2265     { "(bad)",  { XX } },
2266     { "(bad)",  { XX } },
2267   },
2268   /* REG_0F71 */
2269   {
2270     { "(bad)",  { XX } },
2271     { "(bad)",  { XX } },
2272     { MOD_TABLE (MOD_0F71_REG_2) },
2273     { "(bad)",  { XX } },
2274     { MOD_TABLE (MOD_0F71_REG_4) },
2275     { "(bad)",  { XX } },
2276     { MOD_TABLE (MOD_0F71_REG_6) },
2277     { "(bad)",  { XX } },
2278   },
2279   /* REG_0F72 */
2280   {
2281     { "(bad)",  { XX } },
2282     { "(bad)",  { XX } },
2283     { MOD_TABLE (MOD_0F72_REG_2) },
2284     { "(bad)",  { XX } },
2285     { MOD_TABLE (MOD_0F72_REG_4) },
2286     { "(bad)",  { XX } },
2287     { MOD_TABLE (MOD_0F72_REG_6) },
2288     { "(bad)",  { XX } },
2289   },
2290   /* REG_0F73 */
2291   {
2292     { "(bad)",  { XX } },
2293     { "(bad)",  { XX } },
2294     { MOD_TABLE (MOD_0F73_REG_2) },
2295     { MOD_TABLE (MOD_0F73_REG_3) },
2296     { "(bad)",  { XX } },
2297     { "(bad)",  { XX } },
2298     { MOD_TABLE (MOD_0F73_REG_6) },
2299     { MOD_TABLE (MOD_0F73_REG_7) },
2300   },
2301   /* REG_0FA6 */
2302   {
2303     { "montmul",        { { OP_0f07, 0 } } },
2304     { "xsha1",          { { OP_0f07, 0 } } },
2305     { "xsha256",        { { OP_0f07, 0 } } },
2306     { "(bad)",          { { OP_0f07, 0 } } },
2307     { "(bad)",          { { OP_0f07, 0 } } },
2308     { "(bad)",          { { OP_0f07, 0 } } },
2309     { "(bad)",          { { OP_0f07, 0 } } },
2310     { "(bad)",          { { OP_0f07, 0 } } },
2311   },
2312   /* REG_0FA7 */
2313   {
2314     { "xstore-rng",     { { OP_0f07, 0 } } },
2315     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2316     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2317     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2318     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2319     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2320     { "(bad)",          { { OP_0f07, 0 } } },
2321     { "(bad)",          { { OP_0f07, 0 } } },
2322   },
2323   /* REG_0FAE */
2324   {
2325     { MOD_TABLE (MOD_0FAE_REG_0) },
2326     { MOD_TABLE (MOD_0FAE_REG_1) },
2327     { MOD_TABLE (MOD_0FAE_REG_2) },
2328     { MOD_TABLE (MOD_0FAE_REG_3) },
2329     { MOD_TABLE (MOD_0FAE_REG_4) },
2330     { MOD_TABLE (MOD_0FAE_REG_5) },
2331     { MOD_TABLE (MOD_0FAE_REG_6) },
2332     { MOD_TABLE (MOD_0FAE_REG_7) },
2333   },
2334   /* REG_0FBA */
2335   {
2336     { "(bad)",  { XX } },
2337     { "(bad)",  { XX } },
2338     { "(bad)",  { XX } },
2339     { "(bad)",  { XX } },
2340     { "btQ",    { Ev, Ib } },
2341     { "btsQ",   { Ev, Ib } },
2342     { "btrQ",   { Ev, Ib } },
2343     { "btcQ",   { Ev, Ib } },
2344   },
2345   /* REG_0FC7 */
2346   {
2347     { "(bad)",  { XX } },
2348     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2349     { "(bad)",  { XX } },
2350     { "(bad)",  { XX } },
2351     { "(bad)",  { XX } },
2352     { "(bad)",  { XX } },
2353     { MOD_TABLE (MOD_0FC7_REG_6) },
2354     { MOD_TABLE (MOD_0FC7_REG_7) },
2355   },
2356   /* REG_VEX_71 */
2357   {
2358     { "(bad)",  { XX } },
2359     { "(bad)",  { XX } },
2360     { MOD_TABLE (MOD_VEX_71_REG_2) },
2361     { "(bad)",  { XX } },
2362     { MOD_TABLE (MOD_VEX_71_REG_4) },
2363     { "(bad)",  { XX } },
2364     { MOD_TABLE (MOD_VEX_71_REG_6) },
2365     { "(bad)",  { XX } },
2366   },
2367   /* REG_VEX_72 */
2368   {
2369     { "(bad)",  { XX } },
2370     { "(bad)",  { XX } },
2371     { MOD_TABLE (MOD_VEX_72_REG_2) },
2372     { "(bad)",  { XX } },
2373     { MOD_TABLE (MOD_VEX_72_REG_4) },
2374     { "(bad)",  { XX } },
2375     { MOD_TABLE (MOD_VEX_72_REG_6) },
2376     { "(bad)",  { XX } },
2377   },
2378   /* REG_VEX_73 */
2379   {
2380     { "(bad)",  { XX } },
2381     { "(bad)",  { XX } },
2382     { MOD_TABLE (MOD_VEX_73_REG_2) },
2383     { MOD_TABLE (MOD_VEX_73_REG_3) },
2384     { "(bad)",  { XX } },
2385     { "(bad)",  { XX } },
2386     { MOD_TABLE (MOD_VEX_73_REG_6) },
2387     { MOD_TABLE (MOD_VEX_73_REG_7) },
2388   },
2389   /* REG_VEX_AE */
2390   {
2391     { "(bad)",  { XX } },
2392     { "(bad)",  { XX } },
2393     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2394     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2395     { "(bad)",  { XX } },
2396     { "(bad)",  { XX } },
2397     { "(bad)",  { XX } },
2398     { "(bad)",  { XX } },
2399   },
2400 };
2401
2402 static const struct dis386 prefix_table[][4] = {
2403   /* PREFIX_90 */
2404   {
2405     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2406     { "pause", { XX } },
2407     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2408     { "(bad)", { XX } },
2409   },
2410
2411   /* PREFIX_0F10 */
2412   {
2413     { "movups", { XM, EXx } },
2414     { "movss",  { XM, EXd } },
2415     { "movupd", { XM, EXx } },
2416     { "movsd",  { XM, EXq } },
2417   },
2418
2419   /* PREFIX_0F11 */
2420   {
2421     { "movups", { EXxS, XM } },
2422     { "movss",  { EXdS, XM } },
2423     { "movupd", { EXxS, XM } },
2424     { "movsd",  { EXqS, XM } },
2425   },
2426
2427   /* PREFIX_0F12 */
2428   {
2429     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2430     { "movsldup", { XM, EXx } },
2431     { "movlpd", { XM, EXq } },
2432     { "movddup", { XM, EXq } },
2433   },
2434
2435   /* PREFIX_0F16 */
2436   {
2437     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2438     { "movshdup", { XM, EXx } },
2439     { "movhpd", { XM, EXq } },
2440     { "(bad)",  { XX } },
2441   },
2442
2443   /* PREFIX_0F2A */
2444   {
2445     { "cvtpi2ps", { XM, EMCq } },
2446     { "cvtsi2ss%LQ", { XM, Ev } },
2447     { "cvtpi2pd", { XM, EMCq } },
2448     { "cvtsi2sd%LQ", { XM, Ev } },
2449   },
2450
2451   /* PREFIX_0F2B */
2452   {
2453     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2454     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2455     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2456     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2457   },
2458
2459   /* PREFIX_0F2C */
2460   {
2461     { "cvttps2pi", { MXC, EXq } },
2462     { "cvttss2siY", { Gv, EXd } },
2463     { "cvttpd2pi", { MXC, EXx } },
2464     { "cvttsd2siY", { Gv, EXq } },
2465   },
2466
2467   /* PREFIX_0F2D */
2468   {
2469     { "cvtps2pi", { MXC, EXq } },
2470     { "cvtss2siY", { Gv, EXd } },
2471     { "cvtpd2pi", { MXC, EXx } },
2472     { "cvtsd2siY", { Gv, EXq } },
2473   },
2474
2475   /* PREFIX_0F2E */
2476   {
2477     { "ucomiss",{ XM, EXd } },
2478     { "(bad)",  { XX } },
2479     { "ucomisd",{ XM, EXq } },
2480     { "(bad)",  { XX } },
2481   },
2482
2483   /* PREFIX_0F2F */
2484   {
2485     { "comiss", { XM, EXd } },
2486     { "(bad)",  { XX } },
2487     { "comisd", { XM, EXq } },
2488     { "(bad)",  { XX } },
2489   },
2490
2491   /* PREFIX_0F51 */
2492   {
2493     { "sqrtps", { XM, EXx } },
2494     { "sqrtss", { XM, EXd } },
2495     { "sqrtpd", { XM, EXx } },
2496     { "sqrtsd", { XM, EXq } },
2497   },
2498
2499   /* PREFIX_0F52 */
2500   {
2501     { "rsqrtps",{ XM, EXx } },
2502     { "rsqrtss",{ XM, EXd } },
2503     { "(bad)",  { XX } },
2504     { "(bad)",  { XX } },
2505   },
2506
2507   /* PREFIX_0F53 */
2508   {
2509     { "rcpps",  { XM, EXx } },
2510     { "rcpss",  { XM, EXd } },
2511     { "(bad)",  { XX } },
2512     { "(bad)",  { XX } },
2513   },
2514
2515   /* PREFIX_0F58 */
2516   {
2517     { "addps", { XM, EXx } },
2518     { "addss", { XM, EXd } },
2519     { "addpd", { XM, EXx } },
2520     { "addsd", { XM, EXq } },
2521   },
2522
2523   /* PREFIX_0F59 */
2524   {
2525     { "mulps",  { XM, EXx } },
2526     { "mulss",  { XM, EXd } },
2527     { "mulpd",  { XM, EXx } },
2528     { "mulsd",  { XM, EXq } },
2529   },
2530
2531   /* PREFIX_0F5A */
2532   {
2533     { "cvtps2pd", { XM, EXq } },
2534     { "cvtss2sd", { XM, EXd } },
2535     { "cvtpd2ps", { XM, EXx } },
2536     { "cvtsd2ss", { XM, EXq } },
2537   },
2538
2539   /* PREFIX_0F5B */
2540   {
2541     { "cvtdq2ps", { XM, EXx } },
2542     { "cvttps2dq", { XM, EXx } },
2543     { "cvtps2dq", { XM, EXx } },
2544     { "(bad)",  { XX } },
2545   },
2546
2547   /* PREFIX_0F5C */
2548   {
2549     { "subps",  { XM, EXx } },
2550     { "subss",  { XM, EXd } },
2551     { "subpd",  { XM, EXx } },
2552     { "subsd",  { XM, EXq } },
2553   },
2554
2555   /* PREFIX_0F5D */
2556   {
2557     { "minps",  { XM, EXx } },
2558     { "minss",  { XM, EXd } },
2559     { "minpd",  { XM, EXx } },
2560     { "minsd",  { XM, EXq } },
2561   },
2562
2563   /* PREFIX_0F5E */
2564   {
2565     { "divps",  { XM, EXx } },
2566     { "divss",  { XM, EXd } },
2567     { "divpd",  { XM, EXx } },
2568     { "divsd",  { XM, EXq } },
2569   },
2570
2571   /* PREFIX_0F5F */
2572   {
2573     { "maxps",  { XM, EXx } },
2574     { "maxss",  { XM, EXd } },
2575     { "maxpd",  { XM, EXx } },
2576     { "maxsd",  { XM, EXq } },
2577   },
2578
2579   /* PREFIX_0F60 */
2580   {
2581     { "punpcklbw",{ MX, EMd } },
2582     { "(bad)",  { XX } },
2583     { "punpcklbw",{ MX, EMx } },
2584     { "(bad)",  { XX } },
2585   },
2586
2587   /* PREFIX_0F61 */
2588   {
2589     { "punpcklwd",{ MX, EMd } },
2590     { "(bad)",  { XX } },
2591     { "punpcklwd",{ MX, EMx } },
2592     { "(bad)",  { XX } },
2593   },
2594
2595   /* PREFIX_0F62 */
2596   {
2597     { "punpckldq",{ MX, EMd } },
2598     { "(bad)",  { XX } },
2599     { "punpckldq",{ MX, EMx } },
2600     { "(bad)",  { XX } },
2601   },
2602
2603   /* PREFIX_0F6C */
2604   {
2605     { "(bad)",  { XX } },
2606     { "(bad)",  { XX } },
2607     { "punpcklqdq", { XM, EXx } },
2608     { "(bad)",  { XX } },
2609   },
2610
2611   /* PREFIX_0F6D */
2612   {
2613     { "(bad)",  { XX } },
2614     { "(bad)",  { XX } },
2615     { "punpckhqdq", { XM, EXx } },
2616     { "(bad)",  { XX } },
2617   },
2618
2619   /* PREFIX_0F6F */
2620   {
2621     { "movq",   { MX, EM } },
2622     { "movdqu", { XM, EXx } },
2623     { "movdqa", { XM, EXx } },
2624     { "(bad)",  { XX } },
2625   },
2626
2627   /* PREFIX_0F70 */
2628   {
2629     { "pshufw", { MX, EM, Ib } },
2630     { "pshufhw",{ XM, EXx, Ib } },
2631     { "pshufd", { XM, EXx, Ib } },
2632     { "pshuflw",{ XM, EXx, Ib } },
2633   },
2634
2635   /* PREFIX_0F73_REG_3 */
2636   {
2637     { "(bad)",  { XX } },
2638     { "(bad)",  { XX } },
2639     { "psrldq", { XS, Ib } },
2640     { "(bad)",  { XX } },
2641   },
2642
2643   /* PREFIX_0F73_REG_7 */
2644   {
2645     { "(bad)",  { XX } },
2646     { "(bad)",  { XX } },
2647     { "pslldq", { XS, Ib } },
2648     { "(bad)",  { XX } },
2649   },
2650
2651   /* PREFIX_0F78 */
2652   {
2653     {"vmread",  { Em, Gm } },
2654     {"(bad)",   { XX } },
2655     {"extrq",   { XS, Ib, Ib } },
2656     {"insertq", { XM, XS, Ib, Ib } },
2657   },
2658
2659   /* PREFIX_0F79 */
2660   {
2661     {"vmwrite", { Gm, Em } },
2662     {"(bad)",   { XX } },
2663     {"extrq",   { XM, XS } },
2664     {"insertq", { XM, XS } },
2665   },
2666
2667   /* PREFIX_0F7C */
2668   {
2669     { "(bad)",  { XX } },
2670     { "(bad)",  { XX } },
2671     { "haddpd", { XM, EXx } },
2672     { "haddps", { XM, EXx } },
2673   },
2674
2675   /* PREFIX_0F7D */
2676   {
2677     { "(bad)",  { XX } },
2678     { "(bad)",  { XX } },
2679     { "hsubpd", { XM, EXx } },
2680     { "hsubps", { XM, EXx } },
2681   },
2682
2683   /* PREFIX_0F7E */
2684   {
2685     { "movK",   { Edq, MX } },
2686     { "movq",   { XM, EXq } },
2687     { "movK",   { Edq, XM } },
2688     { "(bad)",  { XX } },
2689   },
2690
2691   /* PREFIX_0F7F */
2692   {
2693     { "movq",   { EMS, MX } },
2694     { "movdqu", { EXxS, XM } },
2695     { "movdqa", { EXxS, XM } },
2696     { "(bad)",  { XX } },
2697   },
2698
2699   /* PREFIX_0FB8 */
2700   {
2701     { "(bad)", { XX } },
2702     { "popcntS", { Gv, Ev } },
2703     { "(bad)", { XX } },
2704     { "(bad)", { XX } },
2705   },
2706
2707   /* PREFIX_0FBD */
2708   {
2709     { "bsrS",   { Gv, Ev } },
2710     { "lzcntS", { Gv, Ev } },
2711     { "bsrS",   { Gv, Ev } },
2712     { "(bad)",  { XX } },
2713   },
2714
2715   /* PREFIX_0FC2 */
2716   {
2717     { "cmpps",  { XM, EXx, CMP } },
2718     { "cmpss",  { XM, EXd, CMP } },
2719     { "cmppd",  { XM, EXx, CMP } },
2720     { "cmpsd",  { XM, EXq, CMP } },
2721   },
2722
2723   /* PREFIX_0FC3 */
2724   {
2725     { "movntiS", { Ma, Gv } },
2726     { "(bad)",  { XX } },
2727     { "(bad)",  { XX } },
2728     { "(bad)",  { XX } },
2729   },
2730
2731   /* PREFIX_0FC7_REG_6 */
2732   {
2733     { "vmptrld",{ Mq } },
2734     { "vmxon",  { Mq } },
2735     { "vmclear",{ Mq } },
2736     { "(bad)",  { XX } },
2737   },
2738
2739   /* PREFIX_0FD0 */
2740   {
2741     { "(bad)",  { XX } },
2742     { "(bad)",  { XX } },
2743     { "addsubpd", { XM, EXx } },
2744     { "addsubps", { XM, EXx } },
2745   },
2746
2747   /* PREFIX_0FD6 */
2748   {
2749     { "(bad)",  { XX } },
2750     { "movq2dq",{ XM, MS } },
2751     { "movq",   { EXqS, XM } },
2752     { "movdq2q",{ MX, XS } },
2753   },
2754
2755   /* PREFIX_0FE6 */
2756   {
2757     { "(bad)",  { XX } },
2758     { "cvtdq2pd", { XM, EXq } },
2759     { "cvttpd2dq", { XM, EXx } },
2760     { "cvtpd2dq", { XM, EXx } },
2761   },
2762
2763   /* PREFIX_0FE7 */
2764   {
2765     { "movntq", { Mq, MX } },
2766     { "(bad)",  { XX } },
2767     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2768     { "(bad)",  { XX } },
2769   },
2770
2771   /* PREFIX_0FF0 */
2772   {
2773     { "(bad)",  { XX } },
2774     { "(bad)",  { XX } },
2775     { "(bad)",  { XX } },
2776     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2777   },
2778
2779   /* PREFIX_0FF7 */
2780   {
2781     { "maskmovq", { MX, MS } },
2782     { "(bad)",  { XX } },
2783     { "maskmovdqu", { XM, XS } },
2784     { "(bad)",  { XX } },
2785   },
2786
2787   /* PREFIX_0F3810 */
2788   {
2789     { "(bad)",  { XX } },
2790     { "(bad)",  { XX } },
2791     { "pblendvb", { XM, EXx, XMM0 } },
2792     { "(bad)",  { XX } },
2793   },
2794
2795   /* PREFIX_0F3814 */
2796   {
2797     { "(bad)",  { XX } },
2798     { "(bad)",  { XX } },
2799     { "blendvps", { XM, EXx, XMM0 } },
2800     { "(bad)",  { XX } },
2801   },
2802
2803   /* PREFIX_0F3815 */
2804   {
2805     { "(bad)",  { XX } },
2806     { "(bad)",  { XX } },
2807     { "blendvpd", { XM, EXx, XMM0 } },
2808     { "(bad)",  { XX } },
2809   },
2810
2811   /* PREFIX_0F3817 */
2812   {
2813     { "(bad)",  { XX } },
2814     { "(bad)",  { XX } },
2815     { "ptest",  { XM, EXx } },
2816     { "(bad)",  { XX } },
2817   },
2818
2819   /* PREFIX_0F3820 */
2820   {
2821     { "(bad)",  { XX } },
2822     { "(bad)",  { XX } },
2823     { "pmovsxbw", { XM, EXq } },
2824     { "(bad)",  { XX } },
2825   },
2826
2827   /* PREFIX_0F3821 */
2828   {
2829     { "(bad)",  { XX } },
2830     { "(bad)",  { XX } },
2831     { "pmovsxbd", { XM, EXd } },
2832     { "(bad)",  { XX } },
2833   },
2834
2835   /* PREFIX_0F3822 */
2836   {
2837     { "(bad)",  { XX } },
2838     { "(bad)",  { XX } },
2839     { "pmovsxbq", { XM, EXw } },
2840     { "(bad)",  { XX } },
2841   },
2842
2843   /* PREFIX_0F3823 */
2844   {
2845     { "(bad)",  { XX } },
2846     { "(bad)",  { XX } },
2847     { "pmovsxwd", { XM, EXq } },
2848     { "(bad)",  { XX } },
2849   },
2850
2851   /* PREFIX_0F3824 */
2852   {
2853     { "(bad)",  { XX } },
2854     { "(bad)",  { XX } },
2855     { "pmovsxwq", { XM, EXd } },
2856     { "(bad)",  { XX } },
2857   },
2858
2859   /* PREFIX_0F3825 */
2860   {
2861     { "(bad)",  { XX } },
2862     { "(bad)",  { XX } },
2863     { "pmovsxdq", { XM, EXq } },
2864     { "(bad)",  { XX } },
2865   },
2866
2867   /* PREFIX_0F3828 */
2868   {
2869     { "(bad)",  { XX } },
2870     { "(bad)",  { XX } },
2871     { "pmuldq", { XM, EXx } },
2872     { "(bad)",  { XX } },
2873   },
2874
2875   /* PREFIX_0F3829 */
2876   {
2877     { "(bad)",  { XX } },
2878     { "(bad)",  { XX } },
2879     { "pcmpeqq", { XM, EXx } },
2880     { "(bad)",  { XX } },
2881   },
2882
2883   /* PREFIX_0F382A */
2884   {
2885     { "(bad)",  { XX } },
2886     { "(bad)",  { XX } },
2887     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2888     { "(bad)",  { XX } },
2889   },
2890
2891   /* PREFIX_0F382B */
2892   {
2893     { "(bad)",  { XX } },
2894     { "(bad)",  { XX } },
2895     { "packusdw", { XM, EXx } },
2896     { "(bad)",  { XX } },
2897   },
2898
2899   /* PREFIX_0F3830 */
2900   {
2901     { "(bad)",  { XX } },
2902     { "(bad)",  { XX } },
2903     { "pmovzxbw", { XM, EXq } },
2904     { "(bad)",  { XX } },
2905   },
2906
2907   /* PREFIX_0F3831 */
2908   {
2909     { "(bad)",  { XX } },
2910     { "(bad)",  { XX } },
2911     { "pmovzxbd", { XM, EXd } },
2912     { "(bad)",  { XX } },
2913   },
2914
2915   /* PREFIX_0F3832 */
2916   {
2917     { "(bad)",  { XX } },
2918     { "(bad)",  { XX } },
2919     { "pmovzxbq", { XM, EXw } },
2920     { "(bad)",  { XX } },
2921   },
2922
2923   /* PREFIX_0F3833 */
2924   {
2925     { "(bad)",  { XX } },
2926     { "(bad)",  { XX } },
2927     { "pmovzxwd", { XM, EXq } },
2928     { "(bad)",  { XX } },
2929   },
2930
2931   /* PREFIX_0F3834 */
2932   {
2933     { "(bad)",  { XX } },
2934     { "(bad)",  { XX } },
2935     { "pmovzxwq", { XM, EXd } },
2936     { "(bad)",  { XX } },
2937   },
2938
2939   /* PREFIX_0F3835 */
2940   {
2941     { "(bad)",  { XX } },
2942     { "(bad)",  { XX } },
2943     { "pmovzxdq", { XM, EXq } },
2944     { "(bad)",  { XX } },
2945   },
2946
2947   /* PREFIX_0F3837 */
2948   {
2949     { "(bad)",  { XX } },
2950     { "(bad)",  { XX } },
2951     { "pcmpgtq", { XM, EXx } },
2952     { "(bad)",  { XX } },
2953   },
2954
2955   /* PREFIX_0F3838 */
2956   {
2957     { "(bad)",  { XX } },
2958     { "(bad)",  { XX } },
2959     { "pminsb", { XM, EXx } },
2960     { "(bad)",  { XX } },
2961   },
2962
2963   /* PREFIX_0F3839 */
2964   {
2965     { "(bad)",  { XX } },
2966     { "(bad)",  { XX } },
2967     { "pminsd", { XM, EXx } },
2968     { "(bad)",  { XX } },
2969   },
2970
2971   /* PREFIX_0F383A */
2972   {
2973     { "(bad)",  { XX } },
2974     { "(bad)",  { XX } },
2975     { "pminuw", { XM, EXx } },
2976     { "(bad)",  { XX } },
2977   },
2978
2979   /* PREFIX_0F383B */
2980   {
2981     { "(bad)",  { XX } },
2982     { "(bad)",  { XX } },
2983     { "pminud", { XM, EXx } },
2984     { "(bad)",  { XX } },
2985   },
2986
2987   /* PREFIX_0F383C */
2988   {
2989     { "(bad)",  { XX } },
2990     { "(bad)",  { XX } },
2991     { "pmaxsb", { XM, EXx } },
2992     { "(bad)",  { XX } },
2993   },
2994
2995   /* PREFIX_0F383D */
2996   {
2997     { "(bad)",  { XX } },
2998     { "(bad)",  { XX } },
2999     { "pmaxsd", { XM, EXx } },
3000     { "(bad)",  { XX } },
3001   },
3002
3003   /* PREFIX_0F383E */
3004   {
3005     { "(bad)",  { XX } },
3006     { "(bad)",  { XX } },
3007     { "pmaxuw", { XM, EXx } },
3008     { "(bad)",  { XX } },
3009   },
3010
3011   /* PREFIX_0F383F */
3012   {
3013     { "(bad)",  { XX } },
3014     { "(bad)",  { XX } },
3015     { "pmaxud", { XM, EXx } },
3016     { "(bad)",  { XX } },
3017   },
3018
3019   /* PREFIX_0F3840 */
3020   {
3021     { "(bad)",  { XX } },
3022     { "(bad)",  { XX } },
3023     { "pmulld", { XM, EXx } },
3024     { "(bad)",  { XX } },
3025   },
3026
3027   /* PREFIX_0F3841 */
3028   {
3029     { "(bad)",  { XX } },
3030     { "(bad)",  { XX } },
3031     { "phminposuw", { XM, EXx } },
3032     { "(bad)",  { XX } },
3033   },
3034
3035   /* PREFIX_0F3880 */
3036   {
3037     { "(bad)",  { XX } },
3038     { "(bad)",  { XX } },
3039     { "invept", { Gm, Mo } },
3040     { "(bad)",  { XX } },
3041   },
3042
3043   /* PREFIX_0F3881 */
3044   {
3045     { "(bad)",  { XX } },
3046     { "(bad)",  { XX } },
3047     { "invvpid", { Gm, Mo } },
3048     { "(bad)",  { XX } },
3049   },
3050
3051   /* PREFIX_0F38DB */
3052   {
3053     { "(bad)",  { XX } },
3054     { "(bad)",  { XX } },
3055     { "aesimc", { XM, EXx } },
3056     { "(bad)",  { XX } },
3057   },
3058
3059   /* PREFIX_0F38DC */
3060   {
3061     { "(bad)",  { XX } },
3062     { "(bad)",  { XX } },
3063     { "aesenc", { XM, EXx } },
3064     { "(bad)",  { XX } },
3065   },
3066
3067   /* PREFIX_0F38DD */
3068   {
3069     { "(bad)",  { XX } },
3070     { "(bad)",  { XX } },
3071     { "aesenclast", { XM, EXx } },
3072     { "(bad)",  { XX } },
3073   },
3074
3075   /* PREFIX_0F38DE */
3076   {
3077     { "(bad)",  { XX } },
3078     { "(bad)",  { XX } },
3079     { "aesdec", { XM, EXx } },
3080     { "(bad)",  { XX } },
3081   },
3082
3083   /* PREFIX_0F38DF */
3084   {
3085     { "(bad)",  { XX } },
3086     { "(bad)",  { XX } },
3087     { "aesdeclast", { XM, EXx } },
3088     { "(bad)",  { XX } },
3089   },
3090
3091   /* PREFIX_0F38F0 */
3092   {
3093     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3094     { "(bad)",  { XX } },
3095     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3096     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3097   },
3098
3099   /* PREFIX_0F38F1 */
3100   {
3101     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3102     { "(bad)",  { XX } },
3103     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3104     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3105   },
3106
3107   /* PREFIX_0F3A08 */
3108   {
3109     { "(bad)",  { XX } },
3110     { "(bad)",  { XX } },
3111     { "roundps", { XM, EXx, Ib } },
3112     { "(bad)",  { XX } },
3113   },
3114
3115   /* PREFIX_0F3A09 */
3116   {
3117     { "(bad)",  { XX } },
3118     { "(bad)",  { XX } },
3119     { "roundpd", { XM, EXx, Ib } },
3120     { "(bad)",  { XX } },
3121   },
3122
3123   /* PREFIX_0F3A0A */
3124   {
3125     { "(bad)",  { XX } },
3126     { "(bad)",  { XX } },
3127     { "roundss", { XM, EXd, Ib } },
3128     { "(bad)",  { XX } },
3129   },
3130
3131   /* PREFIX_0F3A0B */
3132   {
3133     { "(bad)",  { XX } },
3134     { "(bad)",  { XX } },
3135     { "roundsd", { XM, EXq, Ib } },
3136     { "(bad)",  { XX } },
3137   },
3138
3139   /* PREFIX_0F3A0C */
3140   {
3141     { "(bad)",  { XX } },
3142     { "(bad)",  { XX } },
3143     { "blendps", { XM, EXx, Ib } },
3144     { "(bad)",  { XX } },
3145   },
3146
3147   /* PREFIX_0F3A0D */
3148   {
3149     { "(bad)",  { XX } },
3150     { "(bad)",  { XX } },
3151     { "blendpd", { XM, EXx, Ib } },
3152     { "(bad)",  { XX } },
3153   },
3154
3155   /* PREFIX_0F3A0E */
3156   {
3157     { "(bad)",  { XX } },
3158     { "(bad)",  { XX } },
3159     { "pblendw", { XM, EXx, Ib } },
3160     { "(bad)",  { XX } },
3161   },
3162
3163   /* PREFIX_0F3A14 */
3164   {
3165     { "(bad)",  { XX } },
3166     { "(bad)",  { XX } },
3167     { "pextrb", { Edqb, XM, Ib } },
3168     { "(bad)",  { XX } },
3169   },
3170
3171   /* PREFIX_0F3A15 */
3172   {
3173     { "(bad)",  { XX } },
3174     { "(bad)",  { XX } },
3175     { "pextrw", { Edqw, XM, Ib } },
3176     { "(bad)",  { XX } },
3177   },
3178
3179   /* PREFIX_0F3A16 */
3180   {
3181     { "(bad)",  { XX } },
3182     { "(bad)",  { XX } },
3183     { "pextrK", { Edq, XM, Ib } },
3184     { "(bad)",  { XX } },
3185   },
3186
3187   /* PREFIX_0F3A17 */
3188   {
3189     { "(bad)",  { XX } },
3190     { "(bad)",  { XX } },
3191     { "extractps", { Edqd, XM, Ib } },
3192     { "(bad)",  { XX } },
3193   },
3194
3195   /* PREFIX_0F3A20 */
3196   {
3197     { "(bad)",  { XX } },
3198     { "(bad)",  { XX } },
3199     { "pinsrb", { XM, Edqb, Ib } },
3200     { "(bad)",  { XX } },
3201   },
3202
3203   /* PREFIX_0F3A21 */
3204   {
3205     { "(bad)",  { XX } },
3206     { "(bad)",  { XX } },
3207     { "insertps", { XM, EXd, Ib } },
3208     { "(bad)",  { XX } },
3209   },
3210
3211   /* PREFIX_0F3A22 */
3212   {
3213     { "(bad)",  { XX } },
3214     { "(bad)",  { XX } },
3215     { "pinsrK", { XM, Edq, Ib } },
3216     { "(bad)",  { XX } },
3217   },
3218
3219   /* PREFIX_0F3A40 */
3220   {
3221     { "(bad)",  { XX } },
3222     { "(bad)",  { XX } },
3223     { "dpps",   { XM, EXx, Ib } },
3224     { "(bad)",  { XX } },
3225   },
3226
3227   /* PREFIX_0F3A41 */
3228   {
3229     { "(bad)",  { XX } },
3230     { "(bad)",  { XX } },
3231     { "dppd",   { XM, EXx, Ib } },
3232     { "(bad)",  { XX } },
3233   },
3234
3235   /* PREFIX_0F3A42 */
3236   {
3237     { "(bad)",  { XX } },
3238     { "(bad)",  { XX } },
3239     { "mpsadbw", { XM, EXx, Ib } },
3240     { "(bad)",  { XX } },
3241   },
3242
3243   /* PREFIX_0F3A44 */
3244   {
3245     { "(bad)",  { XX } },
3246     { "(bad)",  { XX } },
3247     { "pclmulqdq", { XM, EXx, PCLMUL } },
3248     { "(bad)",  { XX } },
3249   },
3250
3251   /* PREFIX_0F3A60 */
3252   {
3253     { "(bad)",  { XX } },
3254     { "(bad)",  { XX } },
3255     { "pcmpestrm", { XM, EXx, Ib } },
3256     { "(bad)",  { XX } },
3257   },
3258
3259   /* PREFIX_0F3A61 */
3260   {
3261     { "(bad)",  { XX } },
3262     { "(bad)",  { XX } },
3263     { "pcmpestri", { XM, EXx, Ib } },
3264     { "(bad)",  { XX } },
3265   },
3266
3267   /* PREFIX_0F3A62 */
3268   {
3269     { "(bad)",  { XX } },
3270     { "(bad)",  { XX } },
3271     { "pcmpistrm", { XM, EXx, Ib } },
3272     { "(bad)",  { XX } },
3273   },
3274
3275   /* PREFIX_0F3A63 */
3276   {
3277     { "(bad)",  { XX } },
3278     { "(bad)",  { XX } },
3279     { "pcmpistri", { XM, EXx, Ib } },
3280     { "(bad)",  { XX } },
3281   },
3282
3283   /* PREFIX_0F3ADF */
3284   {
3285     { "(bad)",  { XX } },
3286     { "(bad)",  { XX } },
3287     { "aeskeygenassist", { XM, EXx, Ib } },
3288     { "(bad)",  { XX } },
3289   },
3290
3291   /* PREFIX_VEX_10 */
3292   {
3293     { "vmovups", { XM, EXx } },
3294     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3295     { "vmovupd", { XM, EXx } },
3296     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3297   },
3298
3299   /* PREFIX_VEX_11 */
3300   {
3301     { "vmovups", { EXxS, XM } },
3302     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3303     { "vmovupd", { EXxS, XM } },
3304     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3305   },
3306
3307   /* PREFIX_VEX_12 */
3308   {
3309     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3310     { "vmovsldup", { XM, EXx } },
3311     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3312     { "vmovddup", { XM, EXymmq } },
3313   },
3314
3315   /* PREFIX_VEX_16 */
3316   {
3317     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3318     { "vmovshdup", { XM, EXx } },
3319     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3320     { "(bad)",  { XX } },
3321   },
3322
3323   /* PREFIX_VEX_2A */
3324   {
3325     { "(bad)",  { XX } },
3326     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3327     { "(bad)",  { XX } },
3328     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3329   },
3330
3331   /* PREFIX_VEX_2C */
3332   {
3333     { "(bad)",  { XX } },
3334     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3335     { "(bad)",  { XX } },
3336     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3337   },
3338
3339   /* PREFIX_VEX_2D */
3340   {
3341     { "(bad)",  { XX } },
3342     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3343     { "(bad)",  { XX } },
3344     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3345   },
3346
3347   /* PREFIX_VEX_2E */
3348   {
3349     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3350     { "(bad)",  { XX } },
3351     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3352     { "(bad)",  { XX } },
3353   },
3354
3355   /* PREFIX_VEX_2F */
3356   {
3357     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3358     { "(bad)",  { XX } },
3359     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3360     { "(bad)",  { XX } },
3361   },
3362
3363   /* PREFIX_VEX_51 */
3364   {
3365     { "vsqrtps", { XM, EXx } },
3366     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3367     { "vsqrtpd", { XM, EXx } },
3368     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3369   },
3370
3371   /* PREFIX_VEX_52 */
3372   {
3373     { "vrsqrtps", { XM, EXx } },
3374     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3375     { "(bad)",  { XX } },
3376     { "(bad)",  { XX } },
3377   },
3378
3379   /* PREFIX_VEX_53 */
3380   {
3381     { "vrcpps", { XM, EXx } },
3382     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3383     { "(bad)",  { XX } },
3384     { "(bad)",  { XX } },
3385   },
3386
3387   /* PREFIX_VEX_58 */
3388   {
3389     { "vaddps", { XM, Vex, EXx } },
3390     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3391     { "vaddpd", { XM, Vex, EXx } },
3392     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3393   },
3394
3395   /* PREFIX_VEX_59 */
3396   {
3397     { "vmulps", { XM, Vex, EXx } },
3398     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3399     { "vmulpd", { XM, Vex, EXx } },
3400     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3401   },
3402
3403   /* PREFIX_VEX_5A */
3404   {
3405     { "vcvtps2pd", { XM, EXxmmq } },
3406     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3407     { "vcvtpd2ps%XY", { XMM, EXx } },
3408     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3409   },
3410
3411   /* PREFIX_VEX_5B */
3412   {
3413     { "vcvtdq2ps", { XM, EXx } },
3414     { "vcvttps2dq", { XM, EXx } },
3415     { "vcvtps2dq", { XM, EXx } },
3416     { "(bad)",  { XX } },
3417   },
3418
3419   /* PREFIX_VEX_5C */
3420   {
3421     { "vsubps", { XM, Vex, EXx } },
3422     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3423     { "vsubpd", { XM, Vex, EXx } },
3424     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3425   },
3426
3427   /* PREFIX_VEX_5D */
3428   {
3429     { "vminps", { XM, Vex, EXx } },
3430     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3431     { "vminpd", { XM, Vex, EXx } },
3432     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3433   },
3434
3435   /* PREFIX_VEX_5E */
3436   {
3437     { "vdivps", { XM, Vex, EXx } },
3438     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3439     { "vdivpd", { XM, Vex, EXx } },
3440     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3441   },
3442
3443   /* PREFIX_VEX_5F */
3444   {
3445     { "vmaxps", { XM, Vex, EXx } },
3446     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3447     { "vmaxpd", { XM, Vex, EXx } },
3448     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3449   },
3450
3451   /* PREFIX_VEX_60 */
3452   {
3453     { "(bad)",  { XX } },
3454     { "(bad)",  { XX } },
3455     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3456     { "(bad)",  { XX } },
3457   },
3458
3459   /* PREFIX_VEX_61 */
3460   {
3461     { "(bad)",  { XX } },
3462     { "(bad)",  { XX } },
3463     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3464     { "(bad)",  { XX } },
3465   },
3466
3467   /* PREFIX_VEX_62 */
3468   {
3469     { "(bad)",  { XX } },
3470     { "(bad)",  { XX } },
3471     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3472     { "(bad)",  { XX } },
3473   },
3474
3475   /* PREFIX_VEX_63 */
3476   {
3477     { "(bad)",  { XX } },
3478     { "(bad)",  { XX } },
3479     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3480     { "(bad)",  { XX } },
3481   },
3482
3483   /* PREFIX_VEX_64 */
3484   {
3485     { "(bad)",  { XX } },
3486     { "(bad)",  { XX } },
3487     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3488     { "(bad)",  { XX } },
3489   },
3490
3491   /* PREFIX_VEX_65 */
3492   {
3493     { "(bad)",  { XX } },
3494     { "(bad)",  { XX } },
3495     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3496     { "(bad)",  { XX } },
3497   },
3498
3499   /* PREFIX_VEX_66 */
3500   {
3501     { "(bad)",  { XX } },
3502     { "(bad)",  { XX } },
3503     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3504     { "(bad)",  { XX } },
3505   },
3506
3507   /* PREFIX_VEX_67 */
3508   {
3509     { "(bad)",  { XX } },
3510     { "(bad)",  { XX } },
3511     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3512     { "(bad)",  { XX } },
3513   },
3514
3515   /* PREFIX_VEX_68 */
3516   {
3517     { "(bad)",  { XX } },
3518     { "(bad)",  { XX } },
3519     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3520     { "(bad)",  { XX } },
3521   },
3522
3523   /* PREFIX_VEX_69 */
3524   {
3525     { "(bad)",  { XX } },
3526     { "(bad)",  { XX } },
3527     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3528     { "(bad)",  { XX } },
3529   },
3530
3531   /* PREFIX_VEX_6A */
3532   {
3533     { "(bad)",  { XX } },
3534     { "(bad)",  { XX } },
3535     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3536     { "(bad)",  { XX } },
3537   },
3538
3539   /* PREFIX_VEX_6B */
3540   {
3541     { "(bad)",  { XX } },
3542     { "(bad)",  { XX } },
3543     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3544     { "(bad)",  { XX } },
3545   },
3546
3547   /* PREFIX_VEX_6C */
3548   {
3549     { "(bad)",  { XX } },
3550     { "(bad)",  { XX } },
3551     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3552     { "(bad)",  { XX } },
3553   },
3554
3555   /* PREFIX_VEX_6D */
3556   {
3557     { "(bad)",  { XX } },
3558     { "(bad)",  { XX } },
3559     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3560     { "(bad)",  { XX } },
3561   },
3562
3563   /* PREFIX_VEX_6E */
3564   {
3565     { "(bad)",  { XX } },
3566     { "(bad)",  { XX } },
3567     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3568     { "(bad)",  { XX } },
3569   },
3570
3571   /* PREFIX_VEX_6F */
3572   {
3573     { "(bad)",  { XX } },
3574     { "vmovdqu", { XM, EXx } },
3575     { "vmovdqa", { XM, EXx } },
3576     { "(bad)",  { XX } },
3577   },
3578
3579   /* PREFIX_VEX_70 */
3580   {
3581     { "(bad)",  { XX } },
3582     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3583     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3584     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3585   },
3586
3587   /* PREFIX_VEX_71_REG_2 */
3588   {
3589     { "(bad)",  { XX } },
3590     { "(bad)",  { XX } },
3591     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3592     { "(bad)",  { XX } },
3593   },
3594
3595   /* PREFIX_VEX_71_REG_4 */
3596   {
3597     { "(bad)",  { XX } },
3598     { "(bad)",  { XX } },
3599     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3600     { "(bad)",  { XX } },
3601   },
3602
3603   /* PREFIX_VEX_71_REG_6 */
3604   {
3605     { "(bad)",  { XX } },
3606     { "(bad)",  { XX } },
3607     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3608     { "(bad)",  { XX } },
3609   },
3610
3611   /* PREFIX_VEX_72_REG_2 */
3612   {
3613     { "(bad)",  { XX } },
3614     { "(bad)",  { XX } },
3615     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3616     { "(bad)",  { XX } },
3617   },
3618
3619   /* PREFIX_VEX_72_REG_4 */
3620   {
3621     { "(bad)",  { XX } },
3622     { "(bad)",  { XX } },
3623     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3624     { "(bad)",  { XX } },
3625   },
3626
3627   /* PREFIX_VEX_72_REG_6 */
3628   {
3629     { "(bad)",  { XX } },
3630     { "(bad)",  { XX } },
3631     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3632     { "(bad)",  { XX } },
3633   },
3634
3635   /* PREFIX_VEX_73_REG_2 */
3636   {
3637     { "(bad)",  { XX } },
3638     { "(bad)",  { XX } },
3639     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3640     { "(bad)",  { XX } },
3641   },
3642
3643   /* PREFIX_VEX_73_REG_3 */
3644   {
3645     { "(bad)",  { XX } },
3646     { "(bad)",  { XX } },
3647     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3648     { "(bad)",  { XX } },
3649   },
3650
3651   /* PREFIX_VEX_73_REG_6 */
3652   {
3653     { "(bad)",  { XX } },
3654     { "(bad)",  { XX } },
3655     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3656     { "(bad)",  { XX } },
3657   },
3658
3659   /* PREFIX_VEX_73_REG_7 */
3660   {
3661     { "(bad)",  { XX } },
3662     { "(bad)",  { XX } },
3663     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3664     { "(bad)",  { XX } },
3665   },
3666
3667   /* PREFIX_VEX_74 */
3668   {
3669     { "(bad)",  { XX } },
3670     { "(bad)",  { XX } },
3671     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3672     { "(bad)",  { XX } },
3673   },
3674
3675   /* PREFIX_VEX_75 */
3676   {
3677     { "(bad)",  { XX } },
3678     { "(bad)",  { XX } },
3679     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3680     { "(bad)",  { XX } },
3681   },
3682
3683   /* PREFIX_VEX_76 */
3684   {
3685     { "(bad)",  { XX } },
3686     { "(bad)",  { XX } },
3687     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3688     { "(bad)",  { XX } },
3689   },
3690
3691   /* PREFIX_VEX_77 */
3692   {
3693     { "",       { VZERO } },
3694     { "(bad)",  { XX } },
3695     { "(bad)",  { XX } },
3696     { "(bad)",  { XX } },
3697   },
3698
3699   /* PREFIX_VEX_7C */
3700   {
3701     { "(bad)",  { XX } },
3702     { "(bad)",  { XX } },
3703     { "vhaddpd", { XM, Vex, EXx } },
3704     { "vhaddps", { XM, Vex, EXx } },
3705   },
3706
3707   /* PREFIX_VEX_7D */
3708   {
3709     { "(bad)",  { XX } },
3710     { "(bad)",  { XX } },
3711     { "vhsubpd", { XM, Vex, EXx } },
3712     { "vhsubps", { XM, Vex, EXx } },
3713   },
3714
3715   /* PREFIX_VEX_7E */
3716   {
3717     { "(bad)",  { XX } },
3718     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3719     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3720     { "(bad)",  { XX } },
3721   },
3722
3723   /* PREFIX_VEX_7F */
3724   {
3725     { "(bad)",  { XX } },
3726     { "vmovdqu", { EXxS, XM } },
3727     { "vmovdqa", { EXxS, XM } },
3728     { "(bad)",  { XX } },
3729   },
3730
3731   /* PREFIX_VEX_C2 */
3732   {
3733     { "vcmpps", { XM, Vex, EXx, VCMP } },
3734     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3735     { "vcmppd", { XM, Vex, EXx, VCMP } },
3736     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3737   },
3738
3739   /* PREFIX_VEX_C4 */
3740   {
3741     { "(bad)",  { XX } },
3742     { "(bad)",  { XX } },
3743     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3744     { "(bad)",  { XX } },
3745   },
3746
3747   /* PREFIX_VEX_C5 */
3748   {
3749     { "(bad)",  { XX } },
3750     { "(bad)",  { XX } },
3751     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3752     { "(bad)",  { XX } },
3753   },
3754
3755   /* PREFIX_VEX_D0 */
3756   {
3757     { "(bad)",  { XX } },
3758     { "(bad)",  { XX } },
3759     { "vaddsubpd", { XM, Vex, EXx } },
3760     { "vaddsubps", { XM, Vex, EXx } },
3761   },
3762
3763   /* PREFIX_VEX_D1 */
3764   {
3765     { "(bad)",  { XX } },
3766     { "(bad)",  { XX } },
3767     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3768     { "(bad)",  { XX } },
3769   },
3770
3771   /* PREFIX_VEX_D2 */
3772   {
3773     { "(bad)",  { XX } },
3774     { "(bad)",  { XX } },
3775     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3776     { "(bad)",  { XX } },
3777   },
3778
3779   /* PREFIX_VEX_D3 */
3780   {
3781     { "(bad)",  { XX } },
3782     { "(bad)",  { XX } },
3783     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3784     { "(bad)",  { XX } },
3785   },
3786
3787   /* PREFIX_VEX_D4 */
3788   {
3789     { "(bad)",  { XX } },
3790     { "(bad)",  { XX } },
3791     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3792     { "(bad)",  { XX } },
3793   },
3794
3795   /* PREFIX_VEX_D5 */
3796   {
3797     { "(bad)",  { XX } },
3798     { "(bad)",  { XX } },
3799     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3800     { "(bad)",  { XX } },
3801   },
3802
3803   /* PREFIX_VEX_D6 */
3804   {
3805     { "(bad)",  { XX } },
3806     { "(bad)",  { XX } },
3807     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3808     { "(bad)",  { XX } },
3809   },
3810
3811   /* PREFIX_VEX_D7 */
3812   {
3813     { "(bad)",  { XX } },
3814     { "(bad)",  { XX } },
3815     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3816     { "(bad)",  { XX } },
3817   },
3818
3819   /* PREFIX_VEX_D8 */
3820   {
3821     { "(bad)",  { XX } },
3822     { "(bad)",  { XX } },
3823     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3824     { "(bad)",  { XX } },
3825   },
3826
3827   /* PREFIX_VEX_D9 */
3828   {
3829     { "(bad)",  { XX } },
3830     { "(bad)",  { XX } },
3831     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3832     { "(bad)",  { XX } },
3833   },
3834
3835   /* PREFIX_VEX_DA */
3836   {
3837     { "(bad)",  { XX } },
3838     { "(bad)",  { XX } },
3839     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3840     { "(bad)",  { XX } },
3841   },
3842
3843   /* PREFIX_VEX_DB */
3844   {
3845     { "(bad)",  { XX } },
3846     { "(bad)",  { XX } },
3847     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3848     { "(bad)",  { XX } },
3849   },
3850
3851   /* PREFIX_VEX_DC */
3852   {
3853     { "(bad)",  { XX } },
3854     { "(bad)",  { XX } },
3855     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3856     { "(bad)",  { XX } },
3857   },
3858
3859   /* PREFIX_VEX_DD */
3860   {
3861     { "(bad)",  { XX } },
3862     { "(bad)",  { XX } },
3863     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3864     { "(bad)",  { XX } },
3865   },
3866
3867   /* PREFIX_VEX_DE */
3868   {
3869     { "(bad)",  { XX } },
3870     { "(bad)",  { XX } },
3871     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3872     { "(bad)",  { XX } },
3873   },
3874
3875   /* PREFIX_VEX_DF */
3876   {
3877     { "(bad)",  { XX } },
3878     { "(bad)",  { XX } },
3879     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3880     { "(bad)",  { XX } },
3881   },
3882
3883   /* PREFIX_VEX_E0 */
3884   {
3885     { "(bad)",  { XX } },
3886     { "(bad)",  { XX } },
3887     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3888     { "(bad)",  { XX } },
3889   },
3890
3891   /* PREFIX_VEX_E1 */
3892   {
3893     { "(bad)",  { XX } },
3894     { "(bad)",  { XX } },
3895     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3896     { "(bad)",  { XX } },
3897   },
3898
3899   /* PREFIX_VEX_E2 */
3900   {
3901     { "(bad)",  { XX } },
3902     { "(bad)",  { XX } },
3903     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3904     { "(bad)",  { XX } },
3905   },
3906
3907   /* PREFIX_VEX_E3 */
3908   {
3909     { "(bad)",  { XX } },
3910     { "(bad)",  { XX } },
3911     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3912     { "(bad)",  { XX } },
3913   },
3914
3915   /* PREFIX_VEX_E4 */
3916   {
3917     { "(bad)",  { XX } },
3918     { "(bad)",  { XX } },
3919     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3920     { "(bad)",  { XX } },
3921   },
3922
3923   /* PREFIX_VEX_E5 */
3924   {
3925     { "(bad)",  { XX } },
3926     { "(bad)",  { XX } },
3927     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3928     { "(bad)",  { XX } },
3929   },
3930
3931   /* PREFIX_VEX_E6 */
3932   {
3933     { "(bad)",  { XX } },
3934     { "vcvtdq2pd", { XM, EXxmmq } },
3935     { "vcvttpd2dq%XY", { XMM, EXx } },
3936     { "vcvtpd2dq%XY", { XMM, EXx } },
3937   },
3938
3939   /* PREFIX_VEX_E7 */
3940   {
3941     { "(bad)",  { XX } },
3942     { "(bad)",  { XX } },
3943     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3944     { "(bad)",  { XX } },
3945   },
3946
3947   /* PREFIX_VEX_E8 */
3948   {
3949     { "(bad)",  { XX } },
3950     { "(bad)",  { XX } },
3951     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3952     { "(bad)",  { XX } },
3953   },
3954
3955   /* PREFIX_VEX_E9 */
3956   {
3957     { "(bad)",  { XX } },
3958     { "(bad)",  { XX } },
3959     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3960     { "(bad)",  { XX } },
3961   },
3962
3963   /* PREFIX_VEX_EA */
3964   {
3965     { "(bad)",  { XX } },
3966     { "(bad)",  { XX } },
3967     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3968     { "(bad)",  { XX } },
3969   },
3970
3971   /* PREFIX_VEX_EB */
3972   {
3973     { "(bad)",  { XX } },
3974     { "(bad)",  { XX } },
3975     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3976     { "(bad)",  { XX } },
3977   },
3978
3979   /* PREFIX_VEX_EC */
3980   {
3981     { "(bad)",  { XX } },
3982     { "(bad)",  { XX } },
3983     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3984     { "(bad)",  { XX } },
3985   },
3986
3987   /* PREFIX_VEX_ED */
3988   {
3989     { "(bad)",  { XX } },
3990     { "(bad)",  { XX } },
3991     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
3992     { "(bad)",  { XX } },
3993   },
3994
3995   /* PREFIX_VEX_EE */
3996   {
3997     { "(bad)",  { XX } },
3998     { "(bad)",  { XX } },
3999     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4000     { "(bad)",  { XX } },
4001   },
4002
4003   /* PREFIX_VEX_EF */
4004   {
4005     { "(bad)",  { XX } },
4006     { "(bad)",  { XX } },
4007     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4008     { "(bad)",  { XX } },
4009   },
4010
4011   /* PREFIX_VEX_F0 */
4012   {
4013     { "(bad)",  { XX } },
4014     { "(bad)",  { XX } },
4015     { "(bad)",  { XX } },
4016     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4017   },
4018
4019   /* PREFIX_VEX_F1 */
4020   {
4021     { "(bad)",  { XX } },
4022     { "(bad)",  { XX } },
4023     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4024     { "(bad)",  { XX } },
4025   },
4026
4027   /* PREFIX_VEX_F2 */
4028   {
4029     { "(bad)",  { XX } },
4030     { "(bad)",  { XX } },
4031     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4032     { "(bad)",  { XX } },
4033   },
4034
4035   /* PREFIX_VEX_F3 */
4036   {
4037     { "(bad)",  { XX } },
4038     { "(bad)",  { XX } },
4039     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4040     { "(bad)",  { XX } },
4041   },
4042
4043   /* PREFIX_VEX_F4 */
4044   {
4045     { "(bad)",  { XX } },
4046     { "(bad)",  { XX } },
4047     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4048     { "(bad)",  { XX } },
4049   },
4050
4051   /* PREFIX_VEX_F5 */
4052   {
4053     { "(bad)",  { XX } },
4054     { "(bad)",  { XX } },
4055     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4056     { "(bad)",  { XX } },
4057   },
4058
4059   /* PREFIX_VEX_F6 */
4060   {
4061     { "(bad)",  { XX } },
4062     { "(bad)",  { XX } },
4063     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4064     { "(bad)",  { XX } },
4065   },
4066
4067   /* PREFIX_VEX_F7 */
4068   {
4069     { "(bad)",  { XX } },
4070     { "(bad)",  { XX } },
4071     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4072     { "(bad)",  { XX } },
4073   },
4074
4075   /* PREFIX_VEX_F8 */
4076   {
4077     { "(bad)",  { XX } },
4078     { "(bad)",  { XX } },
4079     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4080     { "(bad)",  { XX } },
4081   },
4082
4083   /* PREFIX_VEX_F9 */
4084   {
4085     { "(bad)",  { XX } },
4086     { "(bad)",  { XX } },
4087     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4088     { "(bad)",  { XX } },
4089   },
4090
4091   /* PREFIX_VEX_FA */
4092   {
4093     { "(bad)",  { XX } },
4094     { "(bad)",  { XX } },
4095     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4096     { "(bad)",  { XX } },
4097   },
4098
4099   /* PREFIX_VEX_FB */
4100   {
4101     { "(bad)",  { XX } },
4102     { "(bad)",  { XX } },
4103     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4104     { "(bad)",  { XX } },
4105   },
4106
4107   /* PREFIX_VEX_FC */
4108   {
4109     { "(bad)",  { XX } },
4110     { "(bad)",  { XX } },
4111     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4112     { "(bad)",  { XX } },
4113   },
4114
4115   /* PREFIX_VEX_FD */
4116   {
4117     { "(bad)",  { XX } },
4118     { "(bad)",  { XX } },
4119     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4120     { "(bad)",  { XX } },
4121   },
4122
4123   /* PREFIX_VEX_FE */
4124   {
4125     { "(bad)",  { XX } },
4126     { "(bad)",  { XX } },
4127     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4128     { "(bad)",  { XX } },
4129   },
4130
4131   /* PREFIX_VEX_3800 */
4132   {
4133     { "(bad)",  { XX } },
4134     { "(bad)",  { XX } },
4135     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4136     { "(bad)",  { XX } },
4137   },
4138
4139   /* PREFIX_VEX_3801 */
4140   {
4141     { "(bad)",  { XX } },
4142     { "(bad)",  { XX } },
4143     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4144     { "(bad)",  { XX } },
4145   },
4146
4147   /* PREFIX_VEX_3802 */
4148   {
4149     { "(bad)",  { XX } },
4150     { "(bad)",  { XX } },
4151     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4152     { "(bad)",  { XX } },
4153   },
4154
4155   /* PREFIX_VEX_3803 */
4156   {
4157     { "(bad)",  { XX } },
4158     { "(bad)",  { XX } },
4159     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4160     { "(bad)",  { XX } },
4161   },
4162
4163   /* PREFIX_VEX_3804 */
4164   {
4165     { "(bad)",  { XX } },
4166     { "(bad)",  { XX } },
4167     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4168     { "(bad)",  { XX } },
4169   },
4170
4171   /* PREFIX_VEX_3805 */
4172   {
4173     { "(bad)",  { XX } },
4174     { "(bad)",  { XX } },
4175     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4176     { "(bad)",  { XX } },
4177   },
4178
4179   /* PREFIX_VEX_3806 */
4180   {
4181     { "(bad)",  { XX } },
4182     { "(bad)",  { XX } },
4183     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4184     { "(bad)",  { XX } },
4185   },
4186
4187   /* PREFIX_VEX_3807 */
4188   {
4189     { "(bad)",  { XX } },
4190     { "(bad)",  { XX } },
4191     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4192     { "(bad)",  { XX } },
4193   },
4194
4195   /* PREFIX_VEX_3808 */
4196   {
4197     { "(bad)",  { XX } },
4198     { "(bad)",  { XX } },
4199     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4200     { "(bad)",  { XX } },
4201   },
4202
4203   /* PREFIX_VEX_3809 */
4204   {
4205     { "(bad)",  { XX } },
4206     { "(bad)",  { XX } },
4207     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4208     { "(bad)",  { XX } },
4209   },
4210
4211   /* PREFIX_VEX_380A */
4212   {
4213     { "(bad)",  { XX } },
4214     { "(bad)",  { XX } },
4215     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4216     { "(bad)",  { XX } },
4217   },
4218
4219   /* PREFIX_VEX_380B */
4220   {
4221     { "(bad)",  { XX } },
4222     { "(bad)",  { XX } },
4223     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4224     { "(bad)",  { XX } },
4225   },
4226
4227   /* PREFIX_VEX_380C */
4228   {
4229     { "(bad)",  { XX } },
4230     { "(bad)",  { XX } },
4231     { "vpermilps", { XM, Vex, EXx } },
4232     { "(bad)",  { XX } },
4233   },
4234
4235   /* PREFIX_VEX_380D */
4236   {
4237     { "(bad)",  { XX } },
4238     { "(bad)",  { XX } },
4239     { "vpermilpd", { XM, Vex, EXx } },
4240     { "(bad)",  { XX } },
4241   },
4242
4243   /* PREFIX_VEX_380E */
4244   {
4245     { "(bad)",  { XX } },
4246     { "(bad)",  { XX } },
4247     { "vtestps", { XM, EXx } },
4248     { "(bad)",  { XX } },
4249   },
4250
4251   /* PREFIX_VEX_380F */
4252   {
4253     { "(bad)",  { XX } },
4254     { "(bad)",  { XX } },
4255     { "vtestpd", { XM, EXx } },
4256     { "(bad)",  { XX } },
4257   },
4258
4259   /* PREFIX_VEX_3817 */
4260   {
4261     { "(bad)",  { XX } },
4262     { "(bad)",  { XX } },
4263     { "vptest", { XM, EXx } },
4264     { "(bad)",  { XX } },
4265   },
4266
4267   /* PREFIX_VEX_3818 */
4268   {
4269     { "(bad)",  { XX } },
4270     { "(bad)",  { XX } },
4271     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4272     { "(bad)",  { XX } },
4273   },
4274
4275   /* PREFIX_VEX_3819 */
4276   {
4277     { "(bad)",  { XX } },
4278     { "(bad)",  { XX } },
4279     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4280     { "(bad)",  { XX } },
4281   },
4282
4283   /* PREFIX_VEX_381A */
4284   {
4285     { "(bad)",  { XX } },
4286     { "(bad)",  { XX } },
4287     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4288     { "(bad)",  { XX } },
4289   },
4290
4291   /* PREFIX_VEX_381C */
4292   {
4293     { "(bad)",  { XX } },
4294     { "(bad)",  { XX } },
4295     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4296     { "(bad)",  { XX } },
4297   },
4298
4299   /* PREFIX_VEX_381D */
4300   {
4301     { "(bad)",  { XX } },
4302     { "(bad)",  { XX } },
4303     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4304     { "(bad)",  { XX } },
4305   },
4306
4307   /* PREFIX_VEX_381E */
4308   {
4309     { "(bad)",  { XX } },
4310     { "(bad)",  { XX } },
4311     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4312     { "(bad)",  { XX } },
4313   },
4314
4315   /* PREFIX_VEX_3820 */
4316   {
4317     { "(bad)",  { XX } },
4318     { "(bad)",  { XX } },
4319     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4320     { "(bad)",  { XX } },
4321   },
4322
4323   /* PREFIX_VEX_3821 */
4324   {
4325     { "(bad)",  { XX } },
4326     { "(bad)",  { XX } },
4327     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4328     { "(bad)",  { XX } },
4329   },
4330
4331   /* PREFIX_VEX_3822 */
4332   {
4333     { "(bad)",  { XX } },
4334     { "(bad)",  { XX } },
4335     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4336     { "(bad)",  { XX } },
4337   },
4338
4339   /* PREFIX_VEX_3823 */
4340   {
4341     { "(bad)",  { XX } },
4342     { "(bad)",  { XX } },
4343     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4344     { "(bad)",  { XX } },
4345   },
4346
4347   /* PREFIX_VEX_3824 */
4348   {
4349     { "(bad)",  { XX } },
4350     { "(bad)",  { XX } },
4351     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4352     { "(bad)",  { XX } },
4353   },
4354
4355   /* PREFIX_VEX_3825 */
4356   {
4357     { "(bad)",  { XX } },
4358     { "(bad)",  { XX } },
4359     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4360     { "(bad)",  { XX } },
4361   },
4362
4363   /* PREFIX_VEX_3828 */
4364   {
4365     { "(bad)",  { XX } },
4366     { "(bad)",  { XX } },
4367     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4368     { "(bad)",  { XX } },
4369   },
4370
4371   /* PREFIX_VEX_3829 */
4372   {
4373     { "(bad)",  { XX } },
4374     { "(bad)",  { XX } },
4375     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4376     { "(bad)",  { XX } },
4377   },
4378
4379   /* PREFIX_VEX_382A */
4380   {
4381     { "(bad)",  { XX } },
4382     { "(bad)",  { XX } },
4383     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4384     { "(bad)",  { XX } },
4385   },
4386
4387   /* PREFIX_VEX_382B */
4388   {
4389     { "(bad)",  { XX } },
4390     { "(bad)",  { XX } },
4391     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4392     { "(bad)",  { XX } },
4393   },
4394
4395   /* PREFIX_VEX_382C */
4396   {
4397     { "(bad)",  { XX } },
4398     { "(bad)",  { XX } },
4399      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4400     { "(bad)",  { XX } },
4401   },
4402
4403   /* PREFIX_VEX_382D */
4404   {
4405     { "(bad)",  { XX } },
4406     { "(bad)",  { XX } },
4407      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4408     { "(bad)",  { XX } },
4409   },
4410
4411   /* PREFIX_VEX_382E */
4412   {
4413     { "(bad)",  { XX } },
4414     { "(bad)",  { XX } },
4415      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4416     { "(bad)",  { XX } },
4417   },
4418
4419   /* PREFIX_VEX_382F */
4420   {
4421     { "(bad)",  { XX } },
4422     { "(bad)",  { XX } },
4423      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4424     { "(bad)",  { XX } },
4425   },
4426
4427   /* PREFIX_VEX_3830 */
4428   {
4429     { "(bad)",  { XX } },
4430     { "(bad)",  { XX } },
4431     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4432     { "(bad)",  { XX } },
4433   },
4434
4435   /* PREFIX_VEX_3831 */
4436   {
4437     { "(bad)",  { XX } },
4438     { "(bad)",  { XX } },
4439     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4440     { "(bad)",  { XX } },
4441   },
4442
4443   /* PREFIX_VEX_3832 */
4444   {
4445     { "(bad)",  { XX } },
4446     { "(bad)",  { XX } },
4447     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4448     { "(bad)",  { XX } },
4449   },
4450
4451   /* PREFIX_VEX_3833 */
4452   {
4453     { "(bad)",  { XX } },
4454     { "(bad)",  { XX } },
4455     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4456     { "(bad)",  { XX } },
4457   },
4458
4459   /* PREFIX_VEX_3834 */
4460   {
4461     { "(bad)",  { XX } },
4462     { "(bad)",  { XX } },
4463     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4464     { "(bad)",  { XX } },
4465   },
4466
4467   /* PREFIX_VEX_3835 */
4468   {
4469     { "(bad)",  { XX } },
4470     { "(bad)",  { XX } },
4471     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4472     { "(bad)",  { XX } },
4473   },
4474
4475   /* PREFIX_VEX_3837 */
4476   {
4477     { "(bad)",  { XX } },
4478     { "(bad)",  { XX } },
4479     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4480     { "(bad)",  { XX } },
4481   },
4482
4483   /* PREFIX_VEX_3838 */
4484   {
4485     { "(bad)",  { XX } },
4486     { "(bad)",  { XX } },
4487     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4488     { "(bad)",  { XX } },
4489   },
4490
4491   /* PREFIX_VEX_3839 */
4492   {
4493     { "(bad)",  { XX } },
4494     { "(bad)",  { XX } },
4495     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4496     { "(bad)",  { XX } },
4497   },
4498
4499   /* PREFIX_VEX_383A */
4500   {
4501     { "(bad)",  { XX } },
4502     { "(bad)",  { XX } },
4503     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4504     { "(bad)",  { XX } },
4505   },
4506
4507   /* PREFIX_VEX_383B */
4508   {
4509     { "(bad)",  { XX } },
4510     { "(bad)",  { XX } },
4511     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4512     { "(bad)",  { XX } },
4513   },
4514
4515   /* PREFIX_VEX_383C */
4516   {
4517     { "(bad)",  { XX } },
4518     { "(bad)",  { XX } },
4519     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4520     { "(bad)",  { XX } },
4521   },
4522
4523   /* PREFIX_VEX_383D */
4524   {
4525     { "(bad)",  { XX } },
4526     { "(bad)",  { XX } },
4527     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4528     { "(bad)",  { XX } },
4529   },
4530
4531   /* PREFIX_VEX_383E */
4532   {
4533     { "(bad)",  { XX } },
4534     { "(bad)",  { XX } },
4535     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4536     { "(bad)",  { XX } },
4537   },
4538
4539   /* PREFIX_VEX_383F */
4540   {
4541     { "(bad)",  { XX } },
4542     { "(bad)",  { XX } },
4543     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4544     { "(bad)",  { XX } },
4545   },
4546
4547   /* PREFIX_VEX_3840 */
4548   {
4549     { "(bad)",  { XX } },
4550     { "(bad)",  { XX } },
4551     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4552     { "(bad)",  { XX } },
4553   },
4554
4555   /* PREFIX_VEX_3841 */
4556   {
4557     { "(bad)",  { XX } },
4558     { "(bad)",  { XX } },
4559     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4560     { "(bad)",  { XX } },
4561   },
4562
4563   /* PREFIX_VEX_3896 */
4564   {
4565     { "(bad)",  { XX } },
4566     { "(bad)",  { XX } },
4567     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4568     { "(bad)",  { XX } },
4569   },
4570
4571   /* PREFIX_VEX_3897 */
4572   {
4573     { "(bad)",  { XX } },
4574     { "(bad)",  { XX } },
4575     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4576     { "(bad)",  { XX } },
4577   },
4578
4579   /* PREFIX_VEX_3898 */
4580   {
4581     { "(bad)",  { XX } },
4582     { "(bad)",  { XX } },
4583     { "vfmadd132p%XW", { XM, Vex, EXx } },
4584     { "(bad)",  { XX } },
4585   },
4586
4587   /* PREFIX_VEX_3899 */
4588   {
4589     { "(bad)",  { XX } },
4590     { "(bad)",  { XX } },
4591     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4592     { "(bad)",  { XX } },
4593   },
4594
4595   /* PREFIX_VEX_389A */
4596   {
4597     { "(bad)",  { XX } },
4598     { "(bad)",  { XX } },
4599     { "vfmsub132p%XW", { XM, Vex, EXx } },
4600     { "(bad)",  { XX } },
4601   },
4602
4603   /* PREFIX_VEX_389B */
4604   {
4605     { "(bad)",  { XX } },
4606     { "(bad)",  { XX } },
4607     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4608     { "(bad)",  { XX } },
4609   },
4610
4611   /* PREFIX_VEX_389C */
4612   {
4613     { "(bad)",  { XX } },
4614     { "(bad)",  { XX } },
4615     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4616     { "(bad)",  { XX } },
4617   },
4618
4619   /* PREFIX_VEX_389D */
4620   {
4621     { "(bad)",  { XX } },
4622     { "(bad)",  { XX } },
4623     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4624     { "(bad)",  { XX } },
4625   },
4626
4627   /* PREFIX_VEX_389E */
4628   {
4629     { "(bad)",  { XX } },
4630     { "(bad)",  { XX } },
4631     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4632     { "(bad)",  { XX } },
4633   },
4634
4635   /* PREFIX_VEX_389F */
4636   {
4637     { "(bad)",  { XX } },
4638     { "(bad)",  { XX } },
4639     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4640     { "(bad)",  { XX } },
4641   },
4642
4643   /* PREFIX_VEX_38A6 */
4644   {
4645     { "(bad)",  { XX } },
4646     { "(bad)",  { XX } },
4647     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4648     { "(bad)",  { XX } },
4649   },
4650
4651   /* PREFIX_VEX_38A7 */
4652   {
4653     { "(bad)",  { XX } },
4654     { "(bad)",  { XX } },
4655     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4656     { "(bad)",  { XX } },
4657   },
4658
4659   /* PREFIX_VEX_38A8 */
4660   {
4661     { "(bad)",  { XX } },
4662     { "(bad)",  { XX } },
4663     { "vfmadd213p%XW", { XM, Vex, EXx } },
4664     { "(bad)",  { XX } },
4665   },
4666
4667   /* PREFIX_VEX_38A9 */
4668   {
4669     { "(bad)",  { XX } },
4670     { "(bad)",  { XX } },
4671     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4672     { "(bad)",  { XX } },
4673   },
4674
4675   /* PREFIX_VEX_38AA */
4676   {
4677     { "(bad)",  { XX } },
4678     { "(bad)",  { XX } },
4679     { "vfmsub213p%XW", { XM, Vex, EXx } },
4680     { "(bad)",  { XX } },
4681   },
4682
4683   /* PREFIX_VEX_38AB */
4684   {
4685     { "(bad)",  { XX } },
4686     { "(bad)",  { XX } },
4687     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4688     { "(bad)",  { XX } },
4689   },
4690
4691   /* PREFIX_VEX_38AC */
4692   {
4693     { "(bad)",  { XX } },
4694     { "(bad)",  { XX } },
4695     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4696     { "(bad)",  { XX } },
4697   },
4698
4699   /* PREFIX_VEX_38AD */
4700   {
4701     { "(bad)",  { XX } },
4702     { "(bad)",  { XX } },
4703     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4704     { "(bad)",  { XX } },
4705   },
4706
4707   /* PREFIX_VEX_38AE */
4708   {
4709     { "(bad)",  { XX } },
4710     { "(bad)",  { XX } },
4711     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4712     { "(bad)",  { XX } },
4713   },
4714
4715   /* PREFIX_VEX_38AF */
4716   {
4717     { "(bad)",  { XX } },
4718     { "(bad)",  { XX } },
4719     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4720     { "(bad)",  { XX } },
4721   },
4722
4723   /* PREFIX_VEX_38B6 */
4724   {
4725     { "(bad)",  { XX } },
4726     { "(bad)",  { XX } },
4727     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4728     { "(bad)",  { XX } },
4729   },
4730
4731   /* PREFIX_VEX_38B7 */
4732   {
4733     { "(bad)",  { XX } },
4734     { "(bad)",  { XX } },
4735     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4736     { "(bad)",  { XX } },
4737   },
4738
4739   /* PREFIX_VEX_38B8 */
4740   {
4741     { "(bad)",  { XX } },
4742     { "(bad)",  { XX } },
4743     { "vfmadd231p%XW", { XM, Vex, EXx } },
4744     { "(bad)",  { XX } },
4745   },
4746
4747   /* PREFIX_VEX_38B9 */
4748   {
4749     { "(bad)",  { XX } },
4750     { "(bad)",  { XX } },
4751     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4752     { "(bad)",  { XX } },
4753   },
4754
4755   /* PREFIX_VEX_38BA */
4756   {
4757     { "(bad)",  { XX } },
4758     { "(bad)",  { XX } },
4759     { "vfmsub231p%XW", { XM, Vex, EXx } },
4760     { "(bad)",  { XX } },
4761   },
4762
4763   /* PREFIX_VEX_38BB */
4764   {
4765     { "(bad)",  { XX } },
4766     { "(bad)",  { XX } },
4767     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4768     { "(bad)",  { XX } },
4769   },
4770
4771   /* PREFIX_VEX_38BC */
4772   {
4773     { "(bad)",  { XX } },
4774     { "(bad)",  { XX } },
4775     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4776     { "(bad)",  { XX } },
4777   },
4778
4779   /* PREFIX_VEX_38BD */
4780   {
4781     { "(bad)",  { XX } },
4782     { "(bad)",  { XX } },
4783     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4784     { "(bad)",  { XX } },
4785   },
4786
4787   /* PREFIX_VEX_38BE */
4788   {
4789     { "(bad)",  { XX } },
4790     { "(bad)",  { XX } },
4791     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4792     { "(bad)",  { XX } },
4793   },
4794
4795   /* PREFIX_VEX_38BF */
4796   {
4797     { "(bad)",  { XX } },
4798     { "(bad)",  { XX } },
4799     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4800     { "(bad)",  { XX } },
4801   },
4802
4803   /* PREFIX_VEX_38DB */
4804   {
4805     { "(bad)",  { XX } },
4806     { "(bad)",  { XX } },
4807     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4808     { "(bad)",  { XX } },
4809   },
4810
4811   /* PREFIX_VEX_38DC */
4812   {
4813     { "(bad)",  { XX } },
4814     { "(bad)",  { XX } },
4815     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4816     { "(bad)",  { XX } },
4817   },
4818
4819   /* PREFIX_VEX_38DD */
4820   {
4821     { "(bad)",  { XX } },
4822     { "(bad)",  { XX } },
4823     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4824     { "(bad)",  { XX } },
4825   },
4826
4827   /* PREFIX_VEX_38DE */
4828   {
4829     { "(bad)",  { XX } },
4830     { "(bad)",  { XX } },
4831     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4832     { "(bad)",  { XX } },
4833   },
4834
4835   /* PREFIX_VEX_38DF */
4836   {
4837     { "(bad)",  { XX } },
4838     { "(bad)",  { XX } },
4839     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4840     { "(bad)",  { XX } },
4841   },
4842
4843   /* PREFIX_VEX_3A04 */
4844   {
4845     { "(bad)",  { XX } },
4846     { "(bad)",  { XX } },
4847     { "vpermilps", { XM, EXx, Ib } },
4848     { "(bad)",  { XX } },
4849   },
4850
4851   /* PREFIX_VEX_3A05 */
4852   {
4853     { "(bad)",  { XX } },
4854     { "(bad)",  { XX } },
4855     { "vpermilpd", { XM, EXx, Ib } },
4856     { "(bad)",  { XX } },
4857   },
4858
4859   /* PREFIX_VEX_3A06 */
4860   {
4861     { "(bad)",  { XX } },
4862     { "(bad)",  { XX } },
4863     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4864     { "(bad)",  { XX } },
4865   },
4866
4867   /* PREFIX_VEX_3A08 */
4868   {
4869     { "(bad)",  { XX } },
4870     { "(bad)",  { XX } },
4871     { "vroundps", { XM, EXx, Ib } },
4872     { "(bad)",  { XX } },
4873   },
4874
4875   /* PREFIX_VEX_3A09 */
4876   {
4877     { "(bad)",  { XX } },
4878     { "(bad)",  { XX } },
4879     { "vroundpd", { XM, EXx, Ib } },
4880     { "(bad)",  { XX } },
4881   },
4882
4883   /* PREFIX_VEX_3A0A */
4884   {
4885     { "(bad)",  { XX } },
4886     { "(bad)",  { XX } },
4887     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4888     { "(bad)",  { XX } },
4889   },
4890
4891   /* PREFIX_VEX_3A0B */
4892   {
4893     { "(bad)",  { XX } },
4894     { "(bad)",  { XX } },
4895     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4896     { "(bad)",  { XX } },
4897   },
4898
4899   /* PREFIX_VEX_3A0C */
4900   {
4901     { "(bad)",  { XX } },
4902     { "(bad)",  { XX } },
4903     { "vblendps", { XM, Vex, EXx, Ib } },
4904     { "(bad)",  { XX } },
4905   },
4906
4907   /* PREFIX_VEX_3A0D */
4908   {
4909     { "(bad)",  { XX } },
4910     { "(bad)",  { XX } },
4911     { "vblendpd", { XM, Vex, EXx, Ib } },
4912     { "(bad)",  { XX } },
4913   },
4914
4915   /* PREFIX_VEX_3A0E */
4916   {
4917     { "(bad)",  { XX } },
4918     { "(bad)",  { XX } },
4919     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4920     { "(bad)",  { XX } },
4921   },
4922
4923   /* PREFIX_VEX_3A0F */
4924   {
4925     { "(bad)",  { XX } },
4926     { "(bad)",  { XX } },
4927     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4928     { "(bad)",  { XX } },
4929   },
4930
4931   /* PREFIX_VEX_3A14 */
4932   {
4933     { "(bad)",  { XX } },
4934     { "(bad)",  { XX } },
4935     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4936     { "(bad)",  { XX } },
4937   },
4938
4939   /* PREFIX_VEX_3A15 */
4940   {
4941     { "(bad)",  { XX } },
4942     { "(bad)",  { XX } },
4943     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4944     { "(bad)",  { XX } },
4945   },
4946
4947   /* PREFIX_VEX_3A16 */
4948   {
4949     { "(bad)",  { XX } },
4950     { "(bad)",  { XX } },
4951     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4952     { "(bad)",  { XX } },
4953   },
4954
4955   /* PREFIX_VEX_3A17 */
4956   {
4957     { "(bad)",  { XX } },
4958     { "(bad)",  { XX } },
4959     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4960     { "(bad)",  { XX } },
4961   },
4962
4963   /* PREFIX_VEX_3A18 */
4964   {
4965     { "(bad)",  { XX } },
4966     { "(bad)",  { XX } },
4967     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4968     { "(bad)",  { XX } },
4969   },
4970
4971   /* PREFIX_VEX_3A19 */
4972   {
4973     { "(bad)",  { XX } },
4974     { "(bad)",  { XX } },
4975     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4976     { "(bad)",  { XX } },
4977   },
4978
4979   /* PREFIX_VEX_3A20 */
4980   {
4981     { "(bad)",  { XX } },
4982     { "(bad)",  { XX } },
4983     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4984     { "(bad)",  { XX } },
4985   },
4986
4987   /* PREFIX_VEX_3A21 */
4988   {
4989     { "(bad)",  { XX } },
4990     { "(bad)",  { XX } },
4991     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4992     { "(bad)",  { XX } },
4993   },
4994
4995   /* PREFIX_VEX_3A22 */
4996   {
4997     { "(bad)",  { XX } },
4998     { "(bad)",  { XX } },
4999     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5000     { "(bad)",  { XX } },
5001   },
5002
5003   /* PREFIX_VEX_3A40 */
5004   {
5005     { "(bad)",  { XX } },
5006     { "(bad)",  { XX } },
5007     { "vdpps",  { XM, Vex, EXx, Ib } },
5008     { "(bad)",  { XX } },
5009   },
5010
5011   /* PREFIX_VEX_3A41 */
5012   {
5013     { "(bad)",  { XX } },
5014     { "(bad)",  { XX } },
5015     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5016     { "(bad)",  { XX } },
5017   },
5018
5019   /* PREFIX_VEX_3A42 */
5020   {
5021     { "(bad)",  { XX } },
5022     { "(bad)",  { XX } },
5023     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5024     { "(bad)",  { XX } },
5025   },
5026
5027   /* PREFIX_VEX_3A4A */
5028   {
5029     { "(bad)",  { XX } },
5030     { "(bad)",  { XX } },
5031     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5032     { "(bad)",  { XX } },
5033   },
5034
5035   /* PREFIX_VEX_3A4B */
5036   {
5037     { "(bad)",  { XX } },
5038     { "(bad)",  { XX } },
5039     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5040     { "(bad)",  { XX } },
5041   },
5042
5043   /* PREFIX_VEX_3A4C */
5044   {
5045     { "(bad)",  { XX } },
5046     { "(bad)",  { XX } },
5047     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5048     { "(bad)",  { XX } },
5049   },
5050
5051   /* PREFIX_VEX_3A60 */
5052   {
5053     { "(bad)",  { XX } },
5054     { "(bad)",  { XX } },
5055     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5056     { "(bad)",  { XX } },
5057   },
5058
5059   /* PREFIX_VEX_3A61 */
5060   {
5061     { "(bad)",  { XX } },
5062     { "(bad)",  { XX } },
5063     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5064     { "(bad)",  { XX } },
5065   },
5066
5067   /* PREFIX_VEX_3A62 */
5068   {
5069     { "(bad)",  { XX } },
5070     { "(bad)",  { XX } },
5071     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5072     { "(bad)",  { XX } },
5073   },
5074
5075   /* PREFIX_VEX_3A63 */
5076   {
5077     { "(bad)",  { XX } },
5078     { "(bad)",  { XX } },
5079     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5080     { "(bad)",  { XX } },
5081   },
5082
5083   /* PREFIX_VEX_3ADF */
5084   {
5085     { "(bad)",  { XX } },
5086     { "(bad)",  { XX } },
5087     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5088     { "(bad)",  { XX } },
5089   },
5090 };
5091
5092 static const struct dis386 x86_64_table[][2] = {
5093   /* X86_64_06 */
5094   {
5095     { "push{T|}", { es } },
5096     { "(bad)", { XX } },
5097   },
5098
5099   /* X86_64_07 */
5100   {
5101     { "pop{T|}", { es } },
5102     { "(bad)", { XX } },
5103   },
5104
5105   /* X86_64_0D */
5106   {
5107     { "push{T|}", { cs } },
5108     { "(bad)", { XX } },
5109   },
5110
5111   /* X86_64_16 */
5112   {
5113     { "push{T|}", { ss } },
5114     { "(bad)", { XX } },
5115   },
5116
5117   /* X86_64_17 */
5118   {
5119     { "pop{T|}", { ss } },
5120     { "(bad)", { XX } },
5121   },
5122
5123   /* X86_64_1E */
5124   {
5125     { "push{T|}", { ds } },
5126     { "(bad)", { XX } },
5127   },
5128
5129   /* X86_64_1F */
5130   {
5131     { "pop{T|}", { ds } },
5132     { "(bad)", { XX } },
5133   },
5134
5135   /* X86_64_27 */
5136   {
5137     { "daa", { XX } },
5138     { "(bad)", { XX } },
5139   },
5140
5141   /* X86_64_2F */
5142   {
5143     { "das", { XX } },
5144     { "(bad)", { XX } },
5145   },
5146
5147   /* X86_64_37 */
5148   {
5149     { "aaa", { XX } },
5150     { "(bad)", { XX } },
5151   },
5152
5153   /* X86_64_3F */
5154   {
5155     { "aas", { XX } },
5156     { "(bad)", { XX } },
5157   },
5158
5159   /* X86_64_60 */
5160   {
5161     { "pusha{P|}", { XX } },
5162     { "(bad)", { XX } },
5163   },
5164
5165   /* X86_64_61 */
5166   {
5167     { "popa{P|}", { XX } },
5168     { "(bad)", { XX } },
5169   },
5170
5171   /* X86_64_62 */
5172   {
5173     { MOD_TABLE (MOD_62_32BIT) },
5174     { "(bad)", { XX } },
5175   },
5176
5177   /* X86_64_63 */
5178   {
5179     { "arpl", { Ew, Gw } },
5180     { "movs{lq|xd}", { Gv, Ed } },
5181   },
5182
5183   /* X86_64_6D */
5184   {
5185     { "ins{R|}", { Yzr, indirDX } },
5186     { "ins{G|}", { Yzr, indirDX } },
5187   },
5188
5189   /* X86_64_6F */
5190   {
5191     { "outs{R|}", { indirDXr, Xz } },
5192     { "outs{G|}", { indirDXr, Xz } },
5193   },
5194
5195   /* X86_64_9A */
5196   {
5197     { "Jcall{T|}", { Ap } },
5198     { "(bad)", { XX } },
5199   },
5200
5201   /* X86_64_C4 */
5202   {
5203     { MOD_TABLE (MOD_C4_32BIT) },
5204     { VEX_C4_TABLE (VEX_0F) },
5205   },
5206
5207   /* X86_64_C5 */
5208   {
5209     { MOD_TABLE (MOD_C5_32BIT) },
5210     { VEX_C5_TABLE (VEX_0F) },
5211   },
5212
5213   /* X86_64_CE */
5214   {
5215     { "into", { XX } },
5216     { "(bad)", { XX } },
5217   },
5218
5219   /* X86_64_D4 */
5220   {
5221     { "aam", { sIb } },
5222     { "(bad)", { XX } },
5223   },
5224
5225   /* X86_64_D5 */
5226   {
5227     { "aad", { sIb } },
5228     { "(bad)", { XX } },
5229   },
5230
5231   /* X86_64_EA */
5232   {
5233     { "Jjmp{T|}", { Ap } },
5234     { "(bad)", { XX } },
5235   },
5236
5237   /* X86_64_0F01_REG_0 */
5238   {
5239     { "sgdt{Q|IQ}", { M } },
5240     { "sgdt", { M } },
5241   },
5242
5243   /* X86_64_0F01_REG_1 */
5244   {
5245     { "sidt{Q|IQ}", { M } },
5246     { "sidt", { M } },
5247   },
5248
5249   /* X86_64_0F01_REG_2 */
5250   {
5251     { "lgdt{Q|Q}", { M } },
5252     { "lgdt", { M } },
5253   },
5254
5255   /* X86_64_0F01_REG_3 */
5256   {
5257     { "lidt{Q|Q}", { M } },
5258     { "lidt", { M } },
5259   },
5260 };
5261
5262 static const struct dis386 three_byte_table[][256] = {
5263   /* THREE_BYTE_0F24 */
5264   {
5265     /* 00 */
5266     { "fmaddps",        { { OP_DREX4, q_mode } } },
5267     { "fmaddpd",        { { OP_DREX4, q_mode } } },
5268     { "fmaddss",        { { OP_DREX4, w_mode } } },
5269     { "fmaddsd",        { { OP_DREX4, d_mode } } },
5270     { "fmaddps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5271     { "fmaddpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5272     { "fmaddss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5273     { "fmaddsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5274     /* 08 */
5275     { "fmsubps",        { { OP_DREX4, q_mode } } },
5276     { "fmsubpd",        { { OP_DREX4, q_mode } } },
5277     { "fmsubss",        { { OP_DREX4, w_mode } } },
5278     { "fmsubsd",        { { OP_DREX4, d_mode } } },
5279     { "fmsubps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5280     { "fmsubpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5281     { "fmsubss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5282     { "fmsubsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5283     /* 10 */
5284     { "fnmaddps",       { { OP_DREX4, q_mode } } },
5285     { "fnmaddpd",       { { OP_DREX4, q_mode } } },
5286     { "fnmaddss",       { { OP_DREX4, w_mode } } },
5287     { "fnmaddsd",       { { OP_DREX4, d_mode } } },
5288     { "fnmaddps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5289     { "fnmaddpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5290     { "fnmaddss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5291     { "fnmaddsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5292     /* 18 */
5293     { "fnmsubps",       { { OP_DREX4, q_mode } } },
5294     { "fnmsubpd",       { { OP_DREX4, q_mode } } },
5295     { "fnmsubss",       { { OP_DREX4, w_mode } } },
5296     { "fnmsubsd",       { { OP_DREX4, d_mode } } },
5297     { "fnmsubps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5298     { "fnmsubpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5299     { "fnmsubss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5300     { "fnmsubsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5301     /* 20 */
5302     { "permps",         { { OP_DREX4, q_mode } } },
5303     { "permpd",         { { OP_DREX4, q_mode } } },
5304     { "pcmov",          { { OP_DREX4, q_mode } } },
5305     { "pperm",          { { OP_DREX4, q_mode } } },
5306     { "permps",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5307     { "permpd",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5308     { "pcmov",          { { OP_DREX4, DREX_OC1 + w_mode } } },
5309     { "pperm",          { { OP_DREX4, DREX_OC1 + d_mode } } },
5310     /* 28 */
5311     { "(bad)",          { XX } },
5312     { "(bad)",          { XX } },
5313     { "(bad)",          { XX } },
5314     { "(bad)",          { XX } },
5315     { "(bad)",          { XX } },
5316     { "(bad)",          { XX } },
5317     { "(bad)",          { XX } },
5318     { "(bad)",          { XX } },
5319     /* 30 */
5320     { "(bad)",          { XX } },
5321     { "(bad)",          { XX } },
5322     { "(bad)",          { XX } },
5323     { "(bad)",          { XX } },
5324     { "(bad)",          { XX } },
5325     { "(bad)",          { XX } },
5326     { "(bad)",          { XX } },
5327     { "(bad)",          { XX } },
5328     /* 38 */
5329     { "(bad)",          { XX } },
5330     { "(bad)",          { XX } },
5331     { "(bad)",          { XX } },
5332     { "(bad)",          { XX } },
5333     { "(bad)",          { XX } },
5334     { "(bad)",          { XX } },
5335     { "(bad)",          { XX } },
5336     { "(bad)",          { XX } },
5337     /* 40 */
5338     { "protb",          { { OP_DREX3, q_mode } } },
5339     { "protw",          { { OP_DREX3, q_mode } } },
5340     { "protd",          { { OP_DREX3, q_mode } } },
5341     { "protq",          { { OP_DREX3, q_mode } } },
5342     { "pshlb",          { { OP_DREX3, q_mode } } },
5343     { "pshlw",          { { OP_DREX3, q_mode } } },
5344     { "pshld",          { { OP_DREX3, q_mode } } },
5345     { "pshlq",          { { OP_DREX3, q_mode } } },
5346     /* 48 */
5347     { "pshab",          { { OP_DREX3, q_mode } } },
5348     { "pshaw",          { { OP_DREX3, q_mode } } },
5349     { "pshad",          { { OP_DREX3, q_mode } } },
5350     { "pshaq",          { { OP_DREX3, q_mode } } },
5351     { "(bad)",          { XX } },
5352     { "(bad)",          { XX } },
5353     { "(bad)",          { XX } },
5354     { "(bad)",          { XX } },
5355     /* 50 */
5356     { "(bad)",          { XX } },
5357     { "(bad)",          { XX } },
5358     { "(bad)",          { XX } },
5359     { "(bad)",          { XX } },
5360     { "(bad)",          { XX } },
5361     { "(bad)",          { XX } },
5362     { "(bad)",          { XX } },
5363     { "(bad)",          { XX } },
5364     /* 58 */
5365     { "(bad)",          { XX } },
5366     { "(bad)",          { XX } },
5367     { "(bad)",          { XX } },
5368     { "(bad)",          { XX } },
5369     { "(bad)",          { XX } },
5370     { "(bad)",          { XX } },
5371     { "(bad)",          { XX } },
5372     { "(bad)",          { XX } },
5373     /* 60 */
5374     { "(bad)",          { XX } },
5375     { "(bad)",          { XX } },
5376     { "(bad)",          { XX } },
5377     { "(bad)",          { XX } },
5378     { "(bad)",          { XX } },
5379     { "(bad)",          { XX } },
5380     { "(bad)",          { XX } },
5381     { "(bad)",          { XX } },
5382     /* 68 */
5383     { "(bad)",          { XX } },
5384     { "(bad)",          { XX } },
5385     { "(bad)",          { XX } },
5386     { "(bad)",          { XX } },
5387     { "(bad)",          { XX } },
5388     { "(bad)",          { XX } },
5389     { "(bad)",          { XX } },
5390     { "(bad)",          { XX } },
5391     /* 70 */
5392     { "(bad)",          { XX } },
5393     { "(bad)",          { XX } },
5394     { "(bad)",          { XX } },
5395     { "(bad)",          { XX } },
5396     { "(bad)",          { XX } },
5397     { "(bad)",          { XX } },
5398     { "(bad)",          { XX } },
5399     { "(bad)",          { XX } },
5400     /* 78 */
5401     { "(bad)",          { XX } },
5402     { "(bad)",          { XX } },
5403     { "(bad)",          { XX } },
5404     { "(bad)",          { XX } },
5405     { "(bad)",          { XX } },
5406     { "(bad)",          { XX } },
5407     { "(bad)",          { XX } },
5408     { "(bad)",          { XX } },
5409     /* 80 */
5410     { "(bad)",          { XX } },
5411     { "(bad)",          { XX } },
5412     { "(bad)",          { XX } },
5413     { "(bad)",          { XX } },
5414     { "(bad)",          { XX } },
5415     { "pmacssww",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5416     { "pmacsswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5417     { "pmacssdql",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5418     /* 88 */
5419     { "(bad)",          { XX } },
5420     { "(bad)",          { XX } },
5421     { "(bad)",          { XX } },
5422     { "(bad)",          { XX } },
5423     { "(bad)",          { XX } },
5424     { "(bad)",          { XX } },
5425     { "pmacssdd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5426     { "pmacssdqh",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5427     /* 90 */
5428     { "(bad)",          { XX } },
5429     { "(bad)",          { XX } },
5430     { "(bad)",          { XX } },
5431     { "(bad)",          { XX } },
5432     { "(bad)",          { XX } },
5433     { "pmacsww",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5434     { "pmacswd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5435     { "pmacsdql",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5436     /* 98 */
5437     { "(bad)",          { XX } },
5438     { "(bad)",          { XX } },
5439     { "(bad)",          { XX } },
5440     { "(bad)",          { XX } },
5441     { "(bad)",          { XX } },
5442     { "(bad)",          { XX } },
5443     { "pmacsdd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5444     { "pmacsdqh",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5445     /* a0 */
5446     { "(bad)",          { XX } },
5447     { "(bad)",          { XX } },
5448     { "(bad)",          { XX } },
5449     { "(bad)",          { XX } },
5450     { "(bad)",          { XX } },
5451     { "(bad)",          { XX } },
5452     { "pmadcsswd",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5453     { "(bad)",          { XX } },
5454     /* a8 */
5455     { "(bad)",          { XX } },
5456     { "(bad)",          { XX } },
5457     { "(bad)",          { XX } },
5458     { "(bad)",          { XX } },
5459     { "(bad)",          { XX } },
5460     { "(bad)",          { XX } },
5461     { "(bad)",          { XX } },
5462     { "(bad)",          { XX } },
5463     /* b0 */
5464     { "(bad)",          { XX } },
5465     { "(bad)",          { XX } },
5466     { "(bad)",          { XX } },
5467     { "(bad)",          { XX } },
5468     { "(bad)",          { XX } },
5469     { "(bad)",          { XX } },
5470     { "pmadcswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5471     { "(bad)",          { XX } },
5472     /* b8 */
5473     { "(bad)",          { XX } },
5474     { "(bad)",          { XX } },
5475     { "(bad)",          { XX } },
5476     { "(bad)",          { XX } },
5477     { "(bad)",          { XX } },
5478     { "(bad)",          { XX } },
5479     { "(bad)",          { XX } },
5480     { "(bad)",          { XX } },
5481     /* c0 */
5482     { "(bad)",          { XX } },
5483     { "(bad)",          { XX } },
5484     { "(bad)",          { XX } },
5485     { "(bad)",          { XX } },
5486     { "(bad)",          { XX } },
5487     { "(bad)",          { XX } },
5488     { "(bad)",          { XX } },
5489     { "(bad)",          { XX } },
5490     /* c8 */
5491     { "(bad)",          { XX } },
5492     { "(bad)",          { XX } },
5493     { "(bad)",          { XX } },
5494     { "(bad)",          { XX } },
5495     { "(bad)",          { XX } },
5496     { "(bad)",          { XX } },
5497     { "(bad)",          { XX } },
5498     { "(bad)",          { XX } },
5499     /* d0 */
5500     { "(bad)",          { XX } },
5501     { "(bad)",          { XX } },
5502     { "(bad)",          { XX } },
5503     { "(bad)",          { XX } },
5504     { "(bad)",          { XX } },
5505     { "(bad)",          { XX } },
5506     { "(bad)",          { XX } },
5507     { "(bad)",          { XX } },
5508     /* d8 */
5509     { "(bad)",          { XX } },
5510     { "(bad)",          { XX } },
5511     { "(bad)",          { XX } },
5512     { "(bad)",          { XX } },
5513     { "(bad)",          { XX } },
5514     { "(bad)",          { XX } },
5515     { "(bad)",          { XX } },
5516     { "(bad)",          { XX } },
5517     /* e0 */
5518     { "(bad)",          { XX } },
5519     { "(bad)",          { XX } },
5520     { "(bad)",          { XX } },
5521     { "(bad)",          { XX } },
5522     { "(bad)",          { XX } },
5523     { "(bad)",          { XX } },
5524     { "(bad)",          { XX } },
5525     { "(bad)",          { XX } },
5526     /* e8 */
5527     { "(bad)",          { XX } },
5528     { "(bad)",          { XX } },
5529     { "(bad)",          { XX } },
5530     { "(bad)",          { XX } },
5531     { "(bad)",          { XX } },
5532     { "(bad)",          { XX } },
5533     { "(bad)",          { XX } },
5534     { "(bad)",          { XX } },
5535     /* f0 */
5536     { "(bad)",          { XX } },
5537     { "(bad)",          { XX } },
5538     { "(bad)",          { XX } },
5539     { "(bad)",          { XX } },
5540     { "(bad)",          { XX } },
5541     { "(bad)",          { XX } },
5542     { "(bad)",          { XX } },
5543     { "(bad)",          { XX } },
5544     /* f8 */
5545     { "(bad)",          { XX } },
5546     { "(bad)",          { XX } },
5547     { "(bad)",          { XX } },
5548     { "(bad)",          { XX } },
5549     { "(bad)",          { XX } },
5550     { "(bad)",          { XX } },
5551     { "(bad)",          { XX } },
5552     { "(bad)",          { XX } },
5553   },
5554   /* THREE_BYTE_0F25 */
5555   {
5556     /* 00 */
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     { "(bad)",          { XX } },
5562     { "(bad)",          { XX } },
5563     { "(bad)",          { XX } },
5564     { "(bad)",          { XX } },
5565     /* 08 */
5566     { "(bad)",          { XX } },
5567     { "(bad)",          { XX } },
5568     { "(bad)",          { XX } },
5569     { "(bad)",          { XX } },
5570     { "(bad)",          { XX } },
5571     { "(bad)",          { XX } },
5572     { "(bad)",          { XX } },
5573     { "(bad)",          { XX } },
5574     /* 10 */
5575     { "(bad)",          { XX } },
5576     { "(bad)",          { XX } },
5577     { "(bad)",          { XX } },
5578     { "(bad)",          { XX } },
5579     { "(bad)",          { XX } },
5580     { "(bad)",          { XX } },
5581     { "(bad)",          { XX } },
5582     { "(bad)",          { XX } },
5583     /* 18 */
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     { "(bad)",          { XX } },
5587     { "(bad)",          { XX } },
5588     { "(bad)",          { XX } },
5589     { "(bad)",          { XX } },
5590     { "(bad)",          { XX } },
5591     { "(bad)",          { XX } },
5592     /* 20 */
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     { "(bad)",          { XX } },
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     /* 28 */
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     { "comps",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5607     { "compd",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5608     { "comss",          { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5609     { "comsd",          { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5610     /* 30 */
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     { "(bad)",          { XX } },
5617     { "(bad)",          { XX } },
5618     { "(bad)",          { XX } },
5619     /* 38 */
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     { "(bad)",          { XX } },
5625     { "(bad)",          { XX } },
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     /* 40 */
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     { "(bad)",          { XX } },
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     /* 48 */
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     { "pcomb",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5643     { "pcomw",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5644     { "pcomd",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5645     { "pcomq",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5646     /* 50 */
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     { "(bad)",          { XX } },
5653     { "(bad)",          { XX } },
5654     { "(bad)",          { XX } },
5655     /* 58 */
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     { "(bad)",          { XX } },
5662     { "(bad)",          { XX } },
5663     { "(bad)",          { XX } },
5664     /* 60 */
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     { "(bad)",          { XX } },
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     /* 68 */
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     { "pcomub",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5679     { "pcomuw",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5680     { "pcomud",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5681     { "pcomuq",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5682     /* 70 */
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     { "(bad)",          { XX } },
5688     { "(bad)",          { XX } },
5689     { "(bad)",          { XX } },
5690     { "(bad)",          { XX } },
5691     /* 78 */
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     { "(bad)",          { XX } },
5697     { "(bad)",          { XX } },
5698     { "(bad)",          { XX } },
5699     { "(bad)",          { XX } },
5700     /* 80 */
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     { "(bad)",          { XX } },
5706     { "(bad)",          { XX } },
5707     { "(bad)",          { XX } },
5708     { "(bad)",          { XX } },
5709     /* 88 */
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     { "(bad)",          { XX } },
5715     { "(bad)",          { XX } },
5716     { "(bad)",          { XX } },
5717     { "(bad)",          { XX } },
5718     /* 90 */
5719     { "(bad)",          { XX } },
5720     { "(bad)",          { XX } },
5721     { "(bad)",          { XX } },
5722     { "(bad)",          { XX } },
5723     { "(bad)",          { XX } },
5724     { "(bad)",          { XX } },
5725     { "(bad)",          { XX } },
5726     { "(bad)",          { XX } },
5727     /* 98 */
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     { "(bad)",          { XX } },
5733     { "(bad)",          { XX } },
5734     { "(bad)",          { XX } },
5735     { "(bad)",          { XX } },
5736     /* a0 */
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     { "(bad)",          { XX } },
5742     { "(bad)",          { XX } },
5743     { "(bad)",          { XX } },
5744     { "(bad)",          { XX } },
5745     /* a8 */
5746     { "(bad)",          { XX } },
5747     { "(bad)",          { XX } },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     { "(bad)",          { XX } },
5751     { "(bad)",          { XX } },
5752     { "(bad)",          { XX } },
5753     { "(bad)",          { XX } },
5754     /* b0 */
5755     { "(bad)",          { XX } },
5756     { "(bad)",          { XX } },
5757     { "(bad)",          { XX } },
5758     { "(bad)",          { XX } },
5759     { "(bad)",          { XX } },
5760     { "(bad)",          { XX } },
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763     /* b8 */
5764     { "(bad)",          { XX } },
5765     { "(bad)",          { XX } },
5766     { "(bad)",          { XX } },
5767     { "(bad)",          { XX } },
5768     { "(bad)",          { XX } },
5769     { "(bad)",          { XX } },
5770     { "(bad)",          { XX } },
5771     { "(bad)",          { XX } },
5772     /* c0 */
5773     { "(bad)",          { XX } },
5774     { "(bad)",          { XX } },
5775     { "(bad)",          { XX } },
5776     { "(bad)",          { XX } },
5777     { "(bad)",          { XX } },
5778     { "(bad)",          { XX } },
5779     { "(bad)",          { XX } },
5780     { "(bad)",          { XX } },
5781     /* c8 */
5782     { "(bad)",          { XX } },
5783     { "(bad)",          { XX } },
5784     { "(bad)",          { XX } },
5785     { "(bad)",          { XX } },
5786     { "(bad)",          { XX } },
5787     { "(bad)",          { XX } },
5788     { "(bad)",          { XX } },
5789     { "(bad)",          { XX } },
5790     /* d0 */
5791     { "(bad)",          { XX } },
5792     { "(bad)",          { XX } },
5793     { "(bad)",          { XX } },
5794     { "(bad)",          { XX } },
5795     { "(bad)",          { XX } },
5796     { "(bad)",          { XX } },
5797     { "(bad)",          { XX } },
5798     { "(bad)",          { XX } },
5799     /* d8 */
5800     { "(bad)",          { XX } },
5801     { "(bad)",          { XX } },
5802     { "(bad)",          { XX } },
5803     { "(bad)",          { XX } },
5804     { "(bad)",          { XX } },
5805     { "(bad)",          { XX } },
5806     { "(bad)",          { XX } },
5807     { "(bad)",          { XX } },
5808     /* e0 */
5809     { "(bad)",          { XX } },
5810     { "(bad)",          { XX } },
5811     { "(bad)",          { XX } },
5812     { "(bad)",          { XX } },
5813     { "(bad)",          { XX } },
5814     { "(bad)",          { XX } },
5815     { "(bad)",          { XX } },
5816     { "(bad)",          { XX } },
5817     /* e8 */
5818     { "(bad)",          { XX } },
5819     { "(bad)",          { XX } },
5820     { "(bad)",          { XX } },
5821     { "(bad)",          { XX } },
5822     { "(bad)",          { XX } },
5823     { "(bad)",          { XX } },
5824     { "(bad)",          { XX } },
5825     { "(bad)",          { XX } },
5826     /* f0 */
5827     { "(bad)",          { XX } },
5828     { "(bad)",          { XX } },
5829     { "(bad)",          { XX } },
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     { "(bad)",          { XX } },
5833     { "(bad)",          { XX } },
5834     { "(bad)",          { XX } },
5835     /* f8 */
5836     { "(bad)",          { XX } },
5837     { "(bad)",          { XX } },
5838     { "(bad)",          { XX } },
5839     { "(bad)",          { XX } },
5840     { "(bad)",          { XX } },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     { "(bad)",          { XX } },
5844   },
5845   /* THREE_BYTE_0F38 */
5846   {
5847     /* 00 */
5848     { "pshufb",         { MX, EM } },
5849     { "phaddw",         { MX, EM } },
5850     { "phaddd",         { MX, EM } },
5851     { "phaddsw",        { MX, EM } },
5852     { "pmaddubsw",      { MX, EM } },
5853     { "phsubw",         { MX, EM } },
5854     { "phsubd",         { MX, EM } },
5855     { "phsubsw",        { MX, EM } },
5856     /* 08 */
5857     { "psignb",         { MX, EM } },
5858     { "psignw",         { MX, EM } },
5859     { "psignd",         { MX, EM } },
5860     { "pmulhrsw",       { MX, EM } },
5861     { "(bad)",          { XX } },
5862     { "(bad)",          { XX } },
5863     { "(bad)",          { XX } },
5864     { "(bad)",          { XX } },
5865     /* 10 */
5866     { PREFIX_TABLE (PREFIX_0F3810) },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     { PREFIX_TABLE (PREFIX_0F3814) },
5871     { PREFIX_TABLE (PREFIX_0F3815) },
5872     { "(bad)",          { XX } },
5873     { PREFIX_TABLE (PREFIX_0F3817) },
5874     /* 18 */
5875     { "(bad)",          { XX } },
5876     { "(bad)",          { XX } },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     { "pabsb",          { MX, EM } },
5880     { "pabsw",          { MX, EM } },
5881     { "pabsd",          { MX, EM } },
5882     { "(bad)",          { XX } },
5883     /* 20 */
5884     { PREFIX_TABLE (PREFIX_0F3820) },
5885     { PREFIX_TABLE (PREFIX_0F3821) },
5886     { PREFIX_TABLE (PREFIX_0F3822) },
5887     { PREFIX_TABLE (PREFIX_0F3823) },
5888     { PREFIX_TABLE (PREFIX_0F3824) },
5889     { PREFIX_TABLE (PREFIX_0F3825) },
5890     { "(bad)",          { XX } },
5891     { "(bad)",          { XX } },
5892     /* 28 */
5893     { PREFIX_TABLE (PREFIX_0F3828) },
5894     { PREFIX_TABLE (PREFIX_0F3829) },
5895     { PREFIX_TABLE (PREFIX_0F382A) },
5896     { PREFIX_TABLE (PREFIX_0F382B) },
5897     { "(bad)",          { XX } },
5898     { "(bad)",          { XX } },
5899     { "(bad)",          { XX } },
5900     { "(bad)",          { XX } },
5901     /* 30 */
5902     { PREFIX_TABLE (PREFIX_0F3830) },
5903     { PREFIX_TABLE (PREFIX_0F3831) },
5904     { PREFIX_TABLE (PREFIX_0F3832) },
5905     { PREFIX_TABLE (PREFIX_0F3833) },
5906     { PREFIX_TABLE (PREFIX_0F3834) },
5907     { PREFIX_TABLE (PREFIX_0F3835) },
5908     { "(bad)",          { XX } },
5909     { PREFIX_TABLE (PREFIX_0F3837) },
5910     /* 38 */
5911     { PREFIX_TABLE (PREFIX_0F3838) },
5912     { PREFIX_TABLE (PREFIX_0F3839) },
5913     { PREFIX_TABLE (PREFIX_0F383A) },
5914     { PREFIX_TABLE (PREFIX_0F383B) },
5915     { PREFIX_TABLE (PREFIX_0F383C) },
5916     { PREFIX_TABLE (PREFIX_0F383D) },
5917     { PREFIX_TABLE (PREFIX_0F383E) },
5918     { PREFIX_TABLE (PREFIX_0F383F) },
5919     /* 40 */
5920     { PREFIX_TABLE (PREFIX_0F3840) },
5921     { PREFIX_TABLE (PREFIX_0F3841) },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     { "(bad)",          { XX } },
5925     { "(bad)",          { XX } },
5926     { "(bad)",          { XX } },
5927     { "(bad)",          { XX } },
5928     /* 48 */
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     { "(bad)",          { XX } },
5934     { "(bad)",          { XX } },
5935     { "(bad)",          { XX } },
5936     { "(bad)",          { XX } },
5937     /* 50 */
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     { "(bad)",          { XX } },
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     /* 58 */
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     { "(bad)",          { XX } },
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     /* 60 */
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     { "(bad)",          { XX } },
5961     { "(bad)",          { XX } },
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     /* 68 */
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     { "(bad)",          { XX } },
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973     /* 70 */
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     { "(bad)",          { XX } },
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     /* 78 */
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     { "(bad)",          { XX } },
5988     { "(bad)",          { XX } },
5989     { "(bad)",          { XX } },
5990     { "(bad)",          { XX } },
5991     /* 80 */
5992     { PREFIX_TABLE (PREFIX_0F3880) },
5993     { PREFIX_TABLE (PREFIX_0F3881) },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     { "(bad)",          { XX } },
5998     { "(bad)",          { XX } },
5999     { "(bad)",          { XX } },
6000     /* 88 */
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     { "(bad)",          { XX } },
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     /* 90 */
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     { "(bad)",          { XX } },
6015     { "(bad)",          { XX } },
6016     { "(bad)",          { XX } },
6017     { "(bad)",          { XX } },
6018     /* 98 */
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     { "(bad)",          { XX } },
6025     { "(bad)",          { XX } },
6026     { "(bad)",          { XX } },
6027     /* a0 */
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     { "(bad)",          { XX } },
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     /* a8 */
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     { "(bad)",          { XX } },
6040     { "(bad)",          { XX } },
6041     { "(bad)",          { XX } },
6042     { "(bad)",          { XX } },
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     /* b0 */
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     { "(bad)",          { XX } },
6051     { "(bad)",          { XX } },
6052     { "(bad)",          { XX } },
6053     { "(bad)",          { XX } },
6054     /* b8 */
6055     { "(bad)",          { XX } },
6056     { "(bad)",          { XX } },
6057     { "(bad)",          { XX } },
6058     { "(bad)",          { XX } },
6059     { "(bad)",          { XX } },
6060     { "(bad)",          { XX } },
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     /* c0 */
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     { "(bad)",          { XX } },
6069     { "(bad)",          { XX } },
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     /* c8 */
6073     { "(bad)",          { XX } },
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     { "(bad)",          { XX } },
6077     { "(bad)",          { XX } },
6078     { "(bad)",          { XX } },
6079     { "(bad)",          { XX } },
6080     { "(bad)",          { XX } },
6081     /* d0 */
6082     { "(bad)",          { XX } },
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     { "(bad)",          { XX } },
6086     { "(bad)",          { XX } },
6087     { "(bad)",          { XX } },
6088     { "(bad)",          { XX } },
6089     { "(bad)",          { XX } },
6090     /* d8 */
6091     { "(bad)",          { XX } },
6092     { "(bad)",          { XX } },
6093     { "(bad)",          { XX } },
6094     { PREFIX_TABLE (PREFIX_0F38DB) },
6095     { PREFIX_TABLE (PREFIX_0F38DC) },
6096     { PREFIX_TABLE (PREFIX_0F38DD) },
6097     { PREFIX_TABLE (PREFIX_0F38DE) },
6098     { PREFIX_TABLE (PREFIX_0F38DF) },
6099     /* e0 */
6100     { "(bad)",          { XX } },
6101     { "(bad)",          { XX } },
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     { "(bad)",          { XX } },
6108     /* e8 */
6109     { "(bad)",          { XX } },
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     /* f0 */
6118     { PREFIX_TABLE (PREFIX_0F38F0) },
6119     { PREFIX_TABLE (PREFIX_0F38F1) },
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     /* f8 */
6127     { "(bad)",          { XX } },
6128     { "(bad)",          { XX } },
6129     { "(bad)",          { XX } },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135   },
6136   /* THREE_BYTE_0F3A */
6137   {
6138     /* 00 */
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     { "(bad)",          { XX } },
6145     { "(bad)",          { XX } },
6146     { "(bad)",          { XX } },
6147     /* 08 */
6148     { PREFIX_TABLE (PREFIX_0F3A08) },
6149     { PREFIX_TABLE (PREFIX_0F3A09) },
6150     { PREFIX_TABLE (PREFIX_0F3A0A) },
6151     { PREFIX_TABLE (PREFIX_0F3A0B) },
6152     { PREFIX_TABLE (PREFIX_0F3A0C) },
6153     { PREFIX_TABLE (PREFIX_0F3A0D) },
6154     { PREFIX_TABLE (PREFIX_0F3A0E) },
6155     { "palignr",        { MX, EM, Ib } },
6156     /* 10 */
6157     { "(bad)",          { XX } },
6158     { "(bad)",          { XX } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     { PREFIX_TABLE (PREFIX_0F3A14) },
6162     { PREFIX_TABLE (PREFIX_0F3A15) },
6163     { PREFIX_TABLE (PREFIX_0F3A16) },
6164     { PREFIX_TABLE (PREFIX_0F3A17) },
6165     /* 18 */
6166     { "(bad)",          { XX } },
6167     { "(bad)",          { XX } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     { "(bad)",          { XX } },
6171     { "(bad)",          { XX } },
6172     { "(bad)",          { XX } },
6173     { "(bad)",          { XX } },
6174     /* 20 */
6175     { PREFIX_TABLE (PREFIX_0F3A20) },
6176     { PREFIX_TABLE (PREFIX_0F3A21) },
6177     { PREFIX_TABLE (PREFIX_0F3A22) },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     { "(bad)",          { XX } },
6181     { "(bad)",          { XX } },
6182     { "(bad)",          { XX } },
6183     /* 28 */
6184     { "(bad)",          { XX } },
6185     { "(bad)",          { XX } },
6186     { "(bad)",          { XX } },
6187     { "(bad)",          { XX } },
6188     { "(bad)",          { XX } },
6189     { "(bad)",          { XX } },
6190     { "(bad)",          { XX } },
6191     { "(bad)",          { XX } },
6192     /* 30 */
6193     { "(bad)",          { XX } },
6194     { "(bad)",          { XX } },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "(bad)",          { XX } },
6199     { "(bad)",          { XX } },
6200     { "(bad)",          { XX } },
6201     /* 38 */
6202     { "(bad)",          { XX } },
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     { "(bad)",          { XX } },
6209     { "(bad)",          { XX } },
6210     /* 40 */
6211     { PREFIX_TABLE (PREFIX_0F3A40) },
6212     { PREFIX_TABLE (PREFIX_0F3A41) },
6213     { PREFIX_TABLE (PREFIX_0F3A42) },
6214     { "(bad)",          { XX } },
6215     { PREFIX_TABLE (PREFIX_0F3A44) },
6216     { "(bad)",          { XX } },
6217     { "(bad)",          { XX } },
6218     { "(bad)",          { XX } },
6219     /* 48 */
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     { "(bad)",          { XX } },
6226     { "(bad)",          { XX } },
6227     { "(bad)",          { XX } },
6228     /* 50 */
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     { "(bad)",          { XX } },
6236     { "(bad)",          { XX } },
6237     /* 58 */
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     { "(bad)",          { XX } },
6245     { "(bad)",          { XX } },
6246     /* 60 */
6247     { PREFIX_TABLE (PREFIX_0F3A60) },
6248     { PREFIX_TABLE (PREFIX_0F3A61) },
6249     { PREFIX_TABLE (PREFIX_0F3A62) },
6250     { PREFIX_TABLE (PREFIX_0F3A63) },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     { "(bad)",          { XX } },
6254     { "(bad)",          { XX } },
6255     /* 68 */
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     { "(bad)",          { XX } },
6262     { "(bad)",          { XX } },
6263     { "(bad)",          { XX } },
6264     /* 70 */
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     { "(bad)",          { XX } },
6272     { "(bad)",          { XX } },
6273     /* 78 */
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     { "(bad)",          { XX } },
6281     { "(bad)",          { XX } },
6282     /* 80 */
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     { "(bad)",          { XX } },
6289     { "(bad)",          { XX } },
6290     { "(bad)",          { XX } },
6291     /* 88 */
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     { "(bad)",          { XX } },
6299     { "(bad)",          { XX } },
6300     /* 90 */
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     { "(bad)",          { XX } },
6308     { "(bad)",          { XX } },
6309     /* 98 */
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     { "(bad)",          { XX } },
6316     { "(bad)",          { XX } },
6317     { "(bad)",          { XX } },
6318     /* a0 */
6319     { "(bad)",          { XX } },
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     { "(bad)",          { XX } },
6325     { "(bad)",          { XX } },
6326     { "(bad)",          { XX } },
6327     /* a8 */
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { "(bad)",          { XX } },
6334     { "(bad)",          { XX } },
6335     { "(bad)",          { XX } },
6336     /* b0 */
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     { "(bad)",          { XX } },
6343     { "(bad)",          { XX } },
6344     { "(bad)",          { XX } },
6345     /* b8 */
6346     { "(bad)",          { XX } },
6347     { "(bad)",          { XX } },
6348     { "(bad)",          { XX } },
6349     { "(bad)",          { XX } },
6350     { "(bad)",          { XX } },
6351     { "(bad)",          { XX } },
6352     { "(bad)",          { XX } },
6353     { "(bad)",          { XX } },
6354     /* c0 */
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     { "(bad)",          { XX } },
6361     { "(bad)",          { XX } },
6362     { "(bad)",          { XX } },
6363     /* c8 */
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     { "(bad)",          { XX } },
6370     { "(bad)",          { XX } },
6371     { "(bad)",          { XX } },
6372     /* d0 */
6373     { "(bad)",          { XX } },
6374     { "(bad)",          { XX } },
6375     { "(bad)",          { XX } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378     { "(bad)",          { XX } },
6379     { "(bad)",          { XX } },
6380     { "(bad)",          { XX } },
6381     /* d8 */
6382     { "(bad)",          { XX } },
6383     { "(bad)",          { XX } },
6384     { "(bad)",          { XX } },
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389     { PREFIX_TABLE (PREFIX_0F3ADF) },
6390     /* e0 */
6391     { "(bad)",          { XX } },
6392     { "(bad)",          { XX } },
6393     { "(bad)",          { XX } },
6394     { "(bad)",          { XX } },
6395     { "(bad)",          { XX } },
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     { "(bad)",          { XX } },
6399     /* e8 */
6400     { "(bad)",          { XX } },
6401     { "(bad)",          { XX } },
6402     { "(bad)",          { XX } },
6403     { "(bad)",          { XX } },
6404     { "(bad)",          { XX } },
6405     { "(bad)",          { XX } },
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     /* f0 */
6409     { "(bad)",          { XX } },
6410     { "(bad)",          { XX } },
6411     { "(bad)",          { XX } },
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     /* f8 */
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     { "(bad)",          { XX } },
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426   },
6427   /* THREE_BYTE_0F7A */
6428   {
6429     /* 00 */
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     { "(bad)",          { XX } },
6438     /* 08 */
6439     { "(bad)",          { XX } },
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     { "(bad)",          { XX } },
6446     { "(bad)",          { XX } },
6447     /* 10 */
6448     { "frczps",         { XM, EXq } },
6449     { "frczpd",         { XM, EXq } },
6450     { "frczss",         { XM, EXq } },
6451     { "frczsd",         { XM, EXq } },
6452     { "(bad)",          { XX } },
6453     { "(bad)",          { XX } },
6454     { "(bad)",          { XX } },
6455     { "(bad)",          { XX } },
6456     /* 18 */
6457     { "(bad)",          { XX } },
6458     { "(bad)",          { XX } },
6459     { "(bad)",          { XX } },
6460     { "(bad)",          { XX } },
6461     { "(bad)",          { XX } },
6462     { "(bad)",          { XX } },
6463     { "(bad)",          { XX } },
6464     { "(bad)",          { XX } },
6465     /* 20 */
6466     { "ptest",          { XX } },
6467     { "(bad)",          { XX } },
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     { "(bad)",          { XX } },
6471     { "(bad)",          { XX } },
6472     { "(bad)",          { XX } },
6473     { "(bad)",          { XX } },
6474     /* 28 */
6475     { "(bad)",          { XX } },
6476     { "(bad)",          { XX } },
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     { "(bad)",          { XX } },
6483     /* 30 */
6484     { "cvtph2ps",       { XM, EXd } },
6485     { "cvtps2ph",       { EXd, XM } },
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     /* 38 */
6493     { "(bad)",          { XX } },
6494     { "(bad)",          { XX } },
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     /* 40 */
6502     { "(bad)",          { XX } },
6503     { "phaddbw",        { XM, EXq } },
6504     { "phaddbd",        { XM, EXq } },
6505     { "phaddbq",        { XM, EXq } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "phaddwd",        { XM, EXq } },
6509     { "phaddwq",        { XM, EXq } },
6510     /* 48 */
6511     { "(bad)",          { XX } },
6512     { "(bad)",          { XX } },
6513     { "(bad)",          { XX } },
6514     { "phadddq",        { XM, EXq } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     /* 50 */
6520     { "(bad)",          { XX } },
6521     { "phaddubw",       { XM, EXq } },
6522     { "phaddubd",       { XM, EXq } },
6523     { "phaddubq",       { XM, EXq } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     { "phadduwd",       { XM, EXq } },
6527     { "phadduwq",       { XM, EXq } },
6528     /* 58 */
6529     { "(bad)",          { XX } },
6530     { "(bad)",          { XX } },
6531     { "(bad)",          { XX } },
6532     { "phaddudq",       { XM, EXq } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     /* 60 */
6538     { "(bad)",          { XX } },
6539     { "phsubbw",        { XM, EXq } },
6540     { "phsubbd",        { XM, EXq } },
6541     { "phsubbq",        { XM, EXq } },
6542     { "(bad)",          { XX } },
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "(bad)",          { XX } },
6546     /* 68 */
6547     { "(bad)",          { XX } },
6548     { "(bad)",          { XX } },
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555     /* 70 */
6556     { "(bad)",          { XX } },
6557     { "(bad)",          { XX } },
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "(bad)",          { XX } },
6564     /* 78 */
6565     { "(bad)",          { XX } },
6566     { "(bad)",          { XX } },
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     { "(bad)",          { XX } },
6573     /* 80 */
6574     { "(bad)",          { XX } },
6575     { "(bad)",          { XX } },
6576     { "(bad)",          { XX } },
6577     { "(bad)",          { XX } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     /* 88 */
6583     { "(bad)",          { XX } },
6584     { "(bad)",          { XX } },
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     /* 90 */
6592     { "(bad)",          { XX } },
6593     { "(bad)",          { XX } },
6594     { "(bad)",          { XX } },
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     { "(bad)",          { XX } },
6599     { "(bad)",          { XX } },
6600     /* 98 */
6601     { "(bad)",          { XX } },
6602     { "(bad)",          { XX } },
6603     { "(bad)",          { XX } },
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     /* a0 */
6610     { "(bad)",          { XX } },
6611     { "(bad)",          { XX } },
6612     { "(bad)",          { XX } },
6613     { "(bad)",          { XX } },
6614     { "(bad)",          { XX } },
6615     { "(bad)",          { XX } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     /* a8 */
6619     { "(bad)",          { XX } },
6620     { "(bad)",          { XX } },
6621     { "(bad)",          { XX } },
6622     { "(bad)",          { XX } },
6623     { "(bad)",          { XX } },
6624     { "(bad)",          { XX } },
6625     { "(bad)",          { XX } },
6626     { "(bad)",          { XX } },
6627     /* b0 */
6628     { "(bad)",          { XX } },
6629     { "(bad)",          { XX } },
6630     { "(bad)",          { XX } },
6631     { "(bad)",          { XX } },
6632     { "(bad)",          { XX } },
6633     { "(bad)",          { XX } },
6634     { "(bad)",          { XX } },
6635     { "(bad)",          { XX } },
6636     /* b8 */
6637     { "(bad)",          { XX } },
6638     { "(bad)",          { XX } },
6639     { "(bad)",          { XX } },
6640     { "(bad)",          { XX } },
6641     { "(bad)",          { XX } },
6642     { "(bad)",          { XX } },
6643     { "(bad)",          { XX } },
6644     { "(bad)",          { XX } },
6645     /* c0 */
6646     { "(bad)",          { XX } },
6647     { "(bad)",          { XX } },
6648     { "(bad)",          { XX } },
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     { "(bad)",          { XX } },
6653     { "(bad)",          { XX } },
6654     /* c8 */
6655     { "(bad)",          { XX } },
6656     { "(bad)",          { XX } },
6657     { "(bad)",          { XX } },
6658     { "(bad)",          { XX } },
6659     { "(bad)",          { XX } },
6660     { "(bad)",          { XX } },
6661     { "(bad)",          { XX } },
6662     { "(bad)",          { XX } },
6663     /* d0 */
6664     { "(bad)",          { XX } },
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672     /* d8 */
6673     { "(bad)",          { XX } },
6674     { "(bad)",          { XX } },
6675     { "(bad)",          { XX } },
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681     /* e0 */
6682     { "(bad)",          { XX } },
6683     { "(bad)",          { XX } },
6684     { "(bad)",          { XX } },
6685     { "(bad)",          { XX } },
6686     { "(bad)",          { XX } },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     /* e8 */
6691     { "(bad)",          { XX } },
6692     { "(bad)",          { XX } },
6693     { "(bad)",          { XX } },
6694     { "(bad)",          { XX } },
6695     { "(bad)",          { XX } },
6696     { "(bad)",          { XX } },
6697     { "(bad)",          { XX } },
6698     { "(bad)",          { XX } },
6699     /* f0 */
6700     { "(bad)",          { XX } },
6701     { "(bad)",          { XX } },
6702     { "(bad)",          { XX } },
6703     { "(bad)",          { XX } },
6704     { "(bad)",          { XX } },
6705     { "(bad)",          { XX } },
6706     { "(bad)",          { XX } },
6707     { "(bad)",          { XX } },
6708     /* f8 */
6709     { "(bad)",          { XX } },
6710     { "(bad)",          { XX } },
6711     { "(bad)",          { XX } },
6712     { "(bad)",          { XX } },
6713     { "(bad)",          { XX } },
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717   },
6718   /* THREE_BYTE_0F7B */
6719   {
6720     /* 00 */
6721     { "(bad)",          { XX } },
6722     { "(bad)",          { XX } },
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727     { "(bad)",          { XX } },
6728     { "(bad)",          { XX } },
6729     /* 08 */
6730     { "(bad)",          { XX } },
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     /* 10 */
6739     { "(bad)",          { XX } },
6740     { "(bad)",          { XX } },
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     /* 18 */
6748     { "(bad)",          { XX } },
6749     { "(bad)",          { XX } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     /* 20 */
6757     { "(bad)",          { XX } },
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     /* 28 */
6766     { "(bad)",          { XX } },
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     /* 30 */
6775     { "(bad)",          { XX } },
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     /* 38 */
6784     { "(bad)",          { XX } },
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     /* 40 */
6793     { "protb",          { XM, EXq, Ib } },
6794     { "protw",          { XM, EXq, Ib } },
6795     { "protd",          { XM, EXq, Ib } },
6796     { "protq",          { XM, EXq, Ib } },
6797     { "pshlb",          { XM, EXq, Ib } },
6798     { "pshlw",          { XM, EXq, Ib } },
6799     { "pshld",          { XM, EXq, Ib } },
6800     { "pshlq",          { XM, EXq, Ib } },
6801     /* 48 */
6802     { "pshab",          { XM, EXq, Ib } },
6803     { "pshaw",          { XM, EXq, Ib } },
6804     { "pshad",          { XM, EXq, Ib } },
6805     { "pshaq",          { XM, EXq, Ib } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     /* 50 */
6811     { "(bad)",          { XX } },
6812     { "(bad)",          { XX } },
6813     { "(bad)",          { XX } },
6814     { "(bad)",          { XX } },
6815     { "(bad)",          { XX } },
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     { "(bad)",          { XX } },
6819     /* 58 */
6820     { "(bad)",          { XX } },
6821     { "(bad)",          { XX } },
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     /* 60 */
6829     { "(bad)",          { XX } },
6830     { "(bad)",          { XX } },
6831     { "(bad)",          { XX } },
6832     { "(bad)",          { XX } },
6833     { "(bad)",          { XX } },
6834     { "(bad)",          { XX } },
6835     { "(bad)",          { XX } },
6836     { "(bad)",          { XX } },
6837     /* 68 */
6838     { "(bad)",          { XX } },
6839     { "(bad)",          { XX } },
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     /* 70 */
6847     { "(bad)",          { XX } },
6848     { "(bad)",          { XX } },
6849     { "(bad)",          { XX } },
6850     { "(bad)",          { XX } },
6851     { "(bad)",          { XX } },
6852     { "(bad)",          { XX } },
6853     { "(bad)",          { XX } },
6854     { "(bad)",          { XX } },
6855     /* 78 */
6856     { "(bad)",          { XX } },
6857     { "(bad)",          { XX } },
6858     { "(bad)",          { XX } },
6859     { "(bad)",          { XX } },
6860     { "(bad)",          { XX } },
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     /* 80 */
6865     { "(bad)",          { XX } },
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     /* 88 */
6874     { "(bad)",          { XX } },
6875     { "(bad)",          { XX } },
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     { "(bad)",          { XX } },
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     /* 90 */
6883     { "(bad)",          { XX } },
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     /* 98 */
6892     { "(bad)",          { XX } },
6893     { "(bad)",          { XX } },
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     /* a0 */
6901     { "(bad)",          { XX } },
6902     { "(bad)",          { XX } },
6903     { "(bad)",          { XX } },
6904     { "(bad)",          { XX } },
6905     { "(bad)",          { XX } },
6906     { "(bad)",          { XX } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     /* a8 */
6910     { "(bad)",          { XX } },
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     { "(bad)",          { XX } },
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     /* b0 */
6919     { "(bad)",          { XX } },
6920     { "(bad)",          { XX } },
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     { "(bad)",          { XX } },
6924     { "(bad)",          { XX } },
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     /* b8 */
6928     { "(bad)",          { XX } },
6929     { "(bad)",          { XX } },
6930     { "(bad)",          { XX } },
6931     { "(bad)",          { XX } },
6932     { "(bad)",          { XX } },
6933     { "(bad)",          { XX } },
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     /* c0 */
6937     { "(bad)",          { XX } },
6938     { "(bad)",          { XX } },
6939     { "(bad)",          { XX } },
6940     { "(bad)",          { XX } },
6941     { "(bad)",          { XX } },
6942     { "(bad)",          { XX } },
6943     { "(bad)",          { XX } },
6944     { "(bad)",          { XX } },
6945     /* c8 */
6946     { "(bad)",          { XX } },
6947     { "(bad)",          { XX } },
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     { "(bad)",          { XX } },
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     /* d0 */
6955     { "(bad)",          { XX } },
6956     { "(bad)",          { XX } },
6957     { "(bad)",          { XX } },
6958     { "(bad)",          { XX } },
6959     { "(bad)",          { XX } },
6960     { "(bad)",          { XX } },
6961     { "(bad)",          { XX } },
6962     { "(bad)",          { XX } },
6963     /* d8 */
6964     { "(bad)",          { XX } },
6965     { "(bad)",          { XX } },
6966     { "(bad)",          { XX } },
6967     { "(bad)",          { XX } },
6968     { "(bad)",          { XX } },
6969     { "(bad)",          { XX } },
6970     { "(bad)",          { XX } },
6971     { "(bad)",          { XX } },
6972     /* e0 */
6973     { "(bad)",          { XX } },
6974     { "(bad)",          { XX } },
6975     { "(bad)",          { XX } },
6976     { "(bad)",          { XX } },
6977     { "(bad)",          { XX } },
6978     { "(bad)",          { XX } },
6979     { "(bad)",          { XX } },
6980     { "(bad)",          { XX } },
6981     /* e8 */
6982     { "(bad)",          { XX } },
6983     { "(bad)",          { XX } },
6984     { "(bad)",          { XX } },
6985     { "(bad)",          { XX } },
6986     { "(bad)",          { XX } },
6987     { "(bad)",          { XX } },
6988     { "(bad)",          { XX } },
6989     { "(bad)",          { XX } },
6990     /* f0 */
6991     { "(bad)",          { XX } },
6992     { "(bad)",          { XX } },
6993     { "(bad)",          { XX } },
6994     { "(bad)",          { XX } },
6995     { "(bad)",          { XX } },
6996     { "(bad)",          { XX } },
6997     { "(bad)",          { XX } },
6998     { "(bad)",          { XX } },
6999     /* f8 */
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     { "(bad)",          { XX } },
7005     { "(bad)",          { XX } },
7006     { "(bad)",          { XX } },
7007     { "(bad)",          { XX } },
7008   },
7009 };
7010
7011 static const struct dis386 vex_table[][256] = {
7012   /* VEX_0F */
7013   {
7014     /* 00 */
7015     { "(bad)",          { XX } },
7016     { "(bad)",          { XX } },
7017     { "(bad)",          { XX } },
7018     { "(bad)",          { XX } },
7019     { "(bad)",          { XX } },
7020     { "(bad)",          { XX } },
7021     { "(bad)",          { XX } },
7022     { "(bad)",          { XX } },
7023     /* 08 */
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     { "(bad)",          { XX } },
7032     /* 10 */
7033     { PREFIX_TABLE (PREFIX_VEX_10) },
7034     { PREFIX_TABLE (PREFIX_VEX_11) },
7035     { PREFIX_TABLE (PREFIX_VEX_12) },
7036     { MOD_TABLE (MOD_VEX_13) },
7037     { "vunpcklpX",      { XM, Vex, EXx } },
7038     { "vunpckhpX",      { XM, Vex, EXx } },
7039     { PREFIX_TABLE (PREFIX_VEX_16) },
7040     { MOD_TABLE (MOD_VEX_17) },
7041     /* 18 */
7042     { "(bad)",          { XX } },
7043     { "(bad)",          { XX } },
7044     { "(bad)",          { XX } },
7045     { "(bad)",          { XX } },
7046     { "(bad)",          { XX } },
7047     { "(bad)",          { XX } },
7048     { "(bad)",          { XX } },
7049     { "(bad)",          { XX } },
7050     /* 20 */
7051     { "(bad)",          { XX } },
7052     { "(bad)",          { XX } },
7053     { "(bad)",          { XX } },
7054     { "(bad)",          { XX } },
7055     { "(bad)",          { XX } },
7056     { "(bad)",          { XX } },
7057     { "(bad)",          { XX } },
7058     { "(bad)",          { XX } },
7059     /* 28 */
7060     { "vmovapX",        { XM, EXx } },
7061     { "vmovapX",        { EXxS, XM } },
7062     { PREFIX_TABLE (PREFIX_VEX_2A) },
7063     { MOD_TABLE (MOD_VEX_2B) },
7064     { PREFIX_TABLE (PREFIX_VEX_2C) },
7065     { PREFIX_TABLE (PREFIX_VEX_2D) },
7066     { PREFIX_TABLE (PREFIX_VEX_2E) },
7067     { PREFIX_TABLE (PREFIX_VEX_2F) },
7068     /* 30 */
7069     { "(bad)",          { XX } },
7070     { "(bad)",          { XX } },
7071     { "(bad)",          { XX } },
7072     { "(bad)",          { XX } },
7073     { "(bad)",          { XX } },
7074     { "(bad)",          { XX } },
7075     { "(bad)",          { XX } },
7076     { "(bad)",          { XX } },
7077     /* 38 */
7078     { "(bad)",          { XX } },
7079     { "(bad)",          { XX } },
7080     { "(bad)",          { XX } },
7081     { "(bad)",          { XX } },
7082     { "(bad)",          { XX } },
7083     { "(bad)",          { XX } },
7084     { "(bad)",          { XX } },
7085     { "(bad)",          { XX } },
7086     /* 40 */
7087     { "(bad)",          { XX } },
7088     { "(bad)",          { XX } },
7089     { "(bad)",          { XX } },
7090     { "(bad)",          { XX } },
7091     { "(bad)",          { XX } },
7092     { "(bad)",          { XX } },
7093     { "(bad)",          { XX } },
7094     { "(bad)",          { XX } },
7095     /* 48 */
7096     { "(bad)",          { XX } },
7097     { "(bad)",          { XX } },
7098     { "(bad)",          { XX } },
7099     { "(bad)",          { XX } },
7100     { "(bad)",          { XX } },
7101     { "(bad)",          { XX } },
7102     { "(bad)",          { XX } },
7103     { "(bad)",          { XX } },
7104     /* 50 */
7105     { MOD_TABLE (MOD_VEX_51) },
7106     { PREFIX_TABLE (PREFIX_VEX_51) },
7107     { PREFIX_TABLE (PREFIX_VEX_52) },
7108     { PREFIX_TABLE (PREFIX_VEX_53) },
7109     { "vandpX",         { XM, Vex, EXx } },
7110     { "vandnpX",        { XM, Vex, EXx } },
7111     { "vorpX",          { XM, Vex, EXx } },
7112     { "vxorpX",         { XM, Vex, EXx } },
7113     /* 58 */
7114     { PREFIX_TABLE (PREFIX_VEX_58) },
7115     { PREFIX_TABLE (PREFIX_VEX_59) },
7116     { PREFIX_TABLE (PREFIX_VEX_5A) },
7117     { PREFIX_TABLE (PREFIX_VEX_5B) },
7118     { PREFIX_TABLE (PREFIX_VEX_5C) },
7119     { PREFIX_TABLE (PREFIX_VEX_5D) },
7120     { PREFIX_TABLE (PREFIX_VEX_5E) },
7121     { PREFIX_TABLE (PREFIX_VEX_5F) },
7122     /* 60 */
7123     { PREFIX_TABLE (PREFIX_VEX_60) },
7124     { PREFIX_TABLE (PREFIX_VEX_61) },
7125     { PREFIX_TABLE (PREFIX_VEX_62) },
7126     { PREFIX_TABLE (PREFIX_VEX_63) },
7127     { PREFIX_TABLE (PREFIX_VEX_64) },
7128     { PREFIX_TABLE (PREFIX_VEX_65) },
7129     { PREFIX_TABLE (PREFIX_VEX_66) },
7130     { PREFIX_TABLE (PREFIX_VEX_67) },
7131     /* 68 */
7132     { PREFIX_TABLE (PREFIX_VEX_68) },
7133     { PREFIX_TABLE (PREFIX_VEX_69) },
7134     { PREFIX_TABLE (PREFIX_VEX_6A) },
7135     { PREFIX_TABLE (PREFIX_VEX_6B) },
7136     { PREFIX_TABLE (PREFIX_VEX_6C) },
7137     { PREFIX_TABLE (PREFIX_VEX_6D) },
7138     { PREFIX_TABLE (PREFIX_VEX_6E) },
7139     { PREFIX_TABLE (PREFIX_VEX_6F) },
7140     /* 70 */
7141     { PREFIX_TABLE (PREFIX_VEX_70) },
7142     { REG_TABLE (REG_VEX_71) },
7143     { REG_TABLE (REG_VEX_72) },
7144     { REG_TABLE (REG_VEX_73) },
7145     { PREFIX_TABLE (PREFIX_VEX_74) },
7146     { PREFIX_TABLE (PREFIX_VEX_75) },
7147     { PREFIX_TABLE (PREFIX_VEX_76) },
7148     { PREFIX_TABLE (PREFIX_VEX_77) },
7149     /* 78 */
7150     { "(bad)",          { XX } },
7151     { "(bad)",          { XX } },
7152     { "(bad)",          { XX } },
7153     { "(bad)",          { XX } },
7154     { PREFIX_TABLE (PREFIX_VEX_7C) },
7155     { PREFIX_TABLE (PREFIX_VEX_7D) },
7156     { PREFIX_TABLE (PREFIX_VEX_7E) },
7157     { PREFIX_TABLE (PREFIX_VEX_7F) },
7158     /* 80 */
7159     { "(bad)",          { XX } },
7160     { "(bad)",          { XX } },
7161     { "(bad)",          { XX } },
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { "(bad)",          { XX } },
7165     { "(bad)",          { XX } },
7166     { "(bad)",          { XX } },
7167     /* 88 */
7168     { "(bad)",          { XX } },
7169     { "(bad)",          { XX } },
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     { "(bad)",          { XX } },
7174     { "(bad)",          { XX } },
7175     { "(bad)",          { XX } },
7176     /* 90 */
7177     { "(bad)",          { XX } },
7178     { "(bad)",          { XX } },
7179     { "(bad)",          { XX } },
7180     { "(bad)",          { XX } },
7181     { "(bad)",          { XX } },
7182     { "(bad)",          { XX } },
7183     { "(bad)",          { XX } },
7184     { "(bad)",          { XX } },
7185     /* 98 */
7186     { "(bad)",          { XX } },
7187     { "(bad)",          { XX } },
7188     { "(bad)",          { XX } },
7189     { "(bad)",          { XX } },
7190     { "(bad)",          { XX } },
7191     { "(bad)",          { XX } },
7192     { "(bad)",          { XX } },
7193     { "(bad)",          { XX } },
7194     /* a0 */
7195     { "(bad)",          { XX } },
7196     { "(bad)",          { XX } },
7197     { "(bad)",          { XX } },
7198     { "(bad)",          { XX } },
7199     { "(bad)",          { XX } },
7200     { "(bad)",          { XX } },
7201     { "(bad)",          { XX } },
7202     { "(bad)",          { XX } },
7203     /* a8 */
7204     { "(bad)",          { XX } },
7205     { "(bad)",          { XX } },
7206     { "(bad)",          { XX } },
7207     { "(bad)",          { XX } },
7208     { "(bad)",          { XX } },
7209     { "(bad)",          { XX } },
7210     { REG_TABLE (REG_VEX_AE) },
7211     { "(bad)",          { XX } },
7212     /* b0 */
7213     { "(bad)",          { XX } },
7214     { "(bad)",          { XX } },
7215     { "(bad)",          { XX } },
7216     { "(bad)",          { XX } },
7217     { "(bad)",          { XX } },
7218     { "(bad)",          { XX } },
7219     { "(bad)",          { XX } },
7220     { "(bad)",          { XX } },
7221     /* b8 */
7222     { "(bad)",          { XX } },
7223     { "(bad)",          { XX } },
7224     { "(bad)",          { XX } },
7225     { "(bad)",          { XX } },
7226     { "(bad)",          { XX } },
7227     { "(bad)",          { XX } },
7228     { "(bad)",          { XX } },
7229     { "(bad)",          { XX } },
7230     /* c0 */
7231     { "(bad)",          { XX } },
7232     { "(bad)",          { XX } },
7233     { PREFIX_TABLE (PREFIX_VEX_C2) },
7234     { "(bad)",          { XX } },
7235     { PREFIX_TABLE (PREFIX_VEX_C4) },
7236     { PREFIX_TABLE (PREFIX_VEX_C5) },
7237     { "vshufpX",        { XM, Vex, EXx, Ib } },
7238     { "(bad)",          { XX } },
7239     /* c8 */
7240     { "(bad)",          { XX } },
7241     { "(bad)",          { XX } },
7242     { "(bad)",          { XX } },
7243     { "(bad)",          { XX } },
7244     { "(bad)",          { XX } },
7245     { "(bad)",          { XX } },
7246     { "(bad)",          { XX } },
7247     { "(bad)",          { XX } },
7248     /* d0 */
7249     { PREFIX_TABLE (PREFIX_VEX_D0) },
7250     { PREFIX_TABLE (PREFIX_VEX_D1) },
7251     { PREFIX_TABLE (PREFIX_VEX_D2) },
7252     { PREFIX_TABLE (PREFIX_VEX_D3) },
7253     { PREFIX_TABLE (PREFIX_VEX_D4) },
7254     { PREFIX_TABLE (PREFIX_VEX_D5) },
7255     { PREFIX_TABLE (PREFIX_VEX_D6) },
7256     { PREFIX_TABLE (PREFIX_VEX_D7) },
7257     /* d8 */
7258     { PREFIX_TABLE (PREFIX_VEX_D8) },
7259     { PREFIX_TABLE (PREFIX_VEX_D9) },
7260     { PREFIX_TABLE (PREFIX_VEX_DA) },
7261     { PREFIX_TABLE (PREFIX_VEX_DB) },
7262     { PREFIX_TABLE (PREFIX_VEX_DC) },
7263     { PREFIX_TABLE (PREFIX_VEX_DD) },
7264     { PREFIX_TABLE (PREFIX_VEX_DE) },
7265     { PREFIX_TABLE (PREFIX_VEX_DF) },
7266     /* e0 */
7267     { PREFIX_TABLE (PREFIX_VEX_E0) },
7268     { PREFIX_TABLE (PREFIX_VEX_E1) },
7269     { PREFIX_TABLE (PREFIX_VEX_E2) },
7270     { PREFIX_TABLE (PREFIX_VEX_E3) },
7271     { PREFIX_TABLE (PREFIX_VEX_E4) },
7272     { PREFIX_TABLE (PREFIX_VEX_E5) },
7273     { PREFIX_TABLE (PREFIX_VEX_E6) },
7274     { PREFIX_TABLE (PREFIX_VEX_E7) },
7275     /* e8 */
7276     { PREFIX_TABLE (PREFIX_VEX_E8) },
7277     { PREFIX_TABLE (PREFIX_VEX_E9) },
7278     { PREFIX_TABLE (PREFIX_VEX_EA) },
7279     { PREFIX_TABLE (PREFIX_VEX_EB) },
7280     { PREFIX_TABLE (PREFIX_VEX_EC) },
7281     { PREFIX_TABLE (PREFIX_VEX_ED) },
7282     { PREFIX_TABLE (PREFIX_VEX_EE) },
7283     { PREFIX_TABLE (PREFIX_VEX_EF) },
7284     /* f0 */
7285     { PREFIX_TABLE (PREFIX_VEX_F0) },
7286     { PREFIX_TABLE (PREFIX_VEX_F1) },
7287     { PREFIX_TABLE (PREFIX_VEX_F2) },
7288     { PREFIX_TABLE (PREFIX_VEX_F3) },
7289     { PREFIX_TABLE (PREFIX_VEX_F4) },
7290     { PREFIX_TABLE (PREFIX_VEX_F5) },
7291     { PREFIX_TABLE (PREFIX_VEX_F6) },
7292     { PREFIX_TABLE (PREFIX_VEX_F7) },
7293     /* f8 */
7294     { PREFIX_TABLE (PREFIX_VEX_F8) },
7295     { PREFIX_TABLE (PREFIX_VEX_F9) },
7296     { PREFIX_TABLE (PREFIX_VEX_FA) },
7297     { PREFIX_TABLE (PREFIX_VEX_FB) },
7298     { PREFIX_TABLE (PREFIX_VEX_FC) },
7299     { PREFIX_TABLE (PREFIX_VEX_FD) },
7300     { PREFIX_TABLE (PREFIX_VEX_FE) },
7301     { "(bad)",          { XX } },
7302   },
7303   /* VEX_0F38 */
7304   {
7305     /* 00 */
7306     { PREFIX_TABLE (PREFIX_VEX_3800) },
7307     { PREFIX_TABLE (PREFIX_VEX_3801) },
7308     { PREFIX_TABLE (PREFIX_VEX_3802) },
7309     { PREFIX_TABLE (PREFIX_VEX_3803) },
7310     { PREFIX_TABLE (PREFIX_VEX_3804) },
7311     { PREFIX_TABLE (PREFIX_VEX_3805) },
7312     { PREFIX_TABLE (PREFIX_VEX_3806) },
7313     { PREFIX_TABLE (PREFIX_VEX_3807) },
7314     /* 08 */
7315     { PREFIX_TABLE (PREFIX_VEX_3808) },
7316     { PREFIX_TABLE (PREFIX_VEX_3809) },
7317     { PREFIX_TABLE (PREFIX_VEX_380A) },
7318     { PREFIX_TABLE (PREFIX_VEX_380B) },
7319     { PREFIX_TABLE (PREFIX_VEX_380C) },
7320     { PREFIX_TABLE (PREFIX_VEX_380D) },
7321     { PREFIX_TABLE (PREFIX_VEX_380E) },
7322     { PREFIX_TABLE (PREFIX_VEX_380F) },
7323     /* 10 */
7324     { "(bad)",          { XX } },
7325     { "(bad)",          { XX } },
7326     { "(bad)",          { XX } },
7327     { "(bad)",          { XX } },
7328     { "(bad)",          { XX } },
7329     { "(bad)",          { XX } },
7330     { "(bad)",          { XX } },
7331     { PREFIX_TABLE (PREFIX_VEX_3817) },
7332     /* 18 */
7333     { PREFIX_TABLE (PREFIX_VEX_3818) },
7334     { PREFIX_TABLE (PREFIX_VEX_3819) },
7335     { PREFIX_TABLE (PREFIX_VEX_381A) },
7336     { "(bad)",          { XX } },
7337     { PREFIX_TABLE (PREFIX_VEX_381C) },
7338     { PREFIX_TABLE (PREFIX_VEX_381D) },
7339     { PREFIX_TABLE (PREFIX_VEX_381E) },
7340     { "(bad)",          { XX } },
7341     /* 20 */
7342     { PREFIX_TABLE (PREFIX_VEX_3820) },
7343     { PREFIX_TABLE (PREFIX_VEX_3821) },
7344     { PREFIX_TABLE (PREFIX_VEX_3822) },
7345     { PREFIX_TABLE (PREFIX_VEX_3823) },
7346     { PREFIX_TABLE (PREFIX_VEX_3824) },
7347     { PREFIX_TABLE (PREFIX_VEX_3825) },
7348     { "(bad)",          { XX } },
7349     { "(bad)",          { XX } },
7350     /* 28 */
7351     { PREFIX_TABLE (PREFIX_VEX_3828) },
7352     { PREFIX_TABLE (PREFIX_VEX_3829) },
7353     { PREFIX_TABLE (PREFIX_VEX_382A) },
7354     { PREFIX_TABLE (PREFIX_VEX_382B) },
7355     { PREFIX_TABLE (PREFIX_VEX_382C) },
7356     { PREFIX_TABLE (PREFIX_VEX_382D) },
7357     { PREFIX_TABLE (PREFIX_VEX_382E) },
7358     { PREFIX_TABLE (PREFIX_VEX_382F) },
7359     /* 30 */
7360     { PREFIX_TABLE (PREFIX_VEX_3830) },
7361     { PREFIX_TABLE (PREFIX_VEX_3831) },
7362     { PREFIX_TABLE (PREFIX_VEX_3832) },
7363     { PREFIX_TABLE (PREFIX_VEX_3833) },
7364     { PREFIX_TABLE (PREFIX_VEX_3834) },
7365     { PREFIX_TABLE (PREFIX_VEX_3835) },
7366     { "(bad)",          { XX } },
7367     { PREFIX_TABLE (PREFIX_VEX_3837) },
7368     /* 38 */
7369     { PREFIX_TABLE (PREFIX_VEX_3838) },
7370     { PREFIX_TABLE (PREFIX_VEX_3839) },
7371     { PREFIX_TABLE (PREFIX_VEX_383A) },
7372     { PREFIX_TABLE (PREFIX_VEX_383B) },
7373     { PREFIX_TABLE (PREFIX_VEX_383C) },
7374     { PREFIX_TABLE (PREFIX_VEX_383D) },
7375     { PREFIX_TABLE (PREFIX_VEX_383E) },
7376     { PREFIX_TABLE (PREFIX_VEX_383F) },
7377     /* 40 */
7378     { PREFIX_TABLE (PREFIX_VEX_3840) },
7379     { PREFIX_TABLE (PREFIX_VEX_3841) },
7380     { "(bad)",          { XX } },
7381     { "(bad)",          { XX } },
7382     { "(bad)",          { XX } },
7383     { "(bad)",          { XX } },
7384     { "(bad)",          { XX } },
7385     { "(bad)",          { XX } },
7386     /* 48 */
7387     { "(bad)",          { XX } },
7388     { "(bad)",          { XX } },
7389     { "(bad)",          { XX } },
7390     { "(bad)",          { XX } },
7391     { "(bad)",          { XX } },
7392     { "(bad)",          { XX } },
7393     { "(bad)",          { XX } },
7394     { "(bad)",          { XX } },
7395     /* 50 */
7396     { "(bad)",          { XX } },
7397     { "(bad)",          { XX } },
7398     { "(bad)",          { XX } },
7399     { "(bad)",          { XX } },
7400     { "(bad)",          { XX } },
7401     { "(bad)",          { XX } },
7402     { "(bad)",          { XX } },
7403     { "(bad)",          { XX } },
7404     /* 58 */
7405     { "(bad)",          { XX } },
7406     { "(bad)",          { XX } },
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     { "(bad)",          { XX } },
7410     { "(bad)",          { XX } },
7411     { "(bad)",          { XX } },
7412     { "(bad)",          { XX } },
7413     /* 60 */
7414     { "(bad)",          { XX } },
7415     { "(bad)",          { XX } },
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     { "(bad)",          { XX } },
7422     /* 68 */
7423     { "(bad)",          { XX } },
7424     { "(bad)",          { XX } },
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     { "(bad)",          { XX } },
7430     { "(bad)",          { XX } },
7431     /* 70 */
7432     { "(bad)",          { XX } },
7433     { "(bad)",          { XX } },
7434     { "(bad)",          { XX } },
7435     { "(bad)",          { XX } },
7436     { "(bad)",          { XX } },
7437     { "(bad)",          { XX } },
7438     { "(bad)",          { XX } },
7439     { "(bad)",          { XX } },
7440     /* 78 */
7441     { "(bad)",          { XX } },
7442     { "(bad)",          { XX } },
7443     { "(bad)",          { XX } },
7444     { "(bad)",          { XX } },
7445     { "(bad)",          { XX } },
7446     { "(bad)",          { XX } },
7447     { "(bad)",          { XX } },
7448     { "(bad)",          { XX } },
7449     /* 80 */
7450     { "(bad)",          { XX } },
7451     { "(bad)",          { XX } },
7452     { "(bad)",          { XX } },
7453     { "(bad)",          { XX } },
7454     { "(bad)",          { XX } },
7455     { "(bad)",          { XX } },
7456     { "(bad)",          { XX } },
7457     { "(bad)",          { XX } },
7458     /* 88 */
7459     { "(bad)",          { XX } },
7460     { "(bad)",          { XX } },
7461     { "(bad)",          { XX } },
7462     { "(bad)",          { XX } },
7463     { "(bad)",          { XX } },
7464     { "(bad)",          { XX } },
7465     { "(bad)",          { XX } },
7466     { "(bad)",          { XX } },
7467     /* 90 */
7468     { "(bad)",          { XX } },
7469     { "(bad)",          { XX } },
7470     { "(bad)",          { XX } },
7471     { "(bad)",          { XX } },
7472     { "(bad)",          { XX } },
7473     { "(bad)",          { XX } },
7474     { PREFIX_TABLE (PREFIX_VEX_3896) },
7475     { PREFIX_TABLE (PREFIX_VEX_3897) },
7476     /* 98 */
7477     { PREFIX_TABLE (PREFIX_VEX_3898) },
7478     { PREFIX_TABLE (PREFIX_VEX_3899) },
7479     { PREFIX_TABLE (PREFIX_VEX_389A) },
7480     { PREFIX_TABLE (PREFIX_VEX_389B) },
7481     { PREFIX_TABLE (PREFIX_VEX_389C) },
7482     { PREFIX_TABLE (PREFIX_VEX_389D) },
7483     { PREFIX_TABLE (PREFIX_VEX_389E) },
7484     { PREFIX_TABLE (PREFIX_VEX_389F) },
7485     /* a0 */
7486     { "(bad)",          { XX } },
7487     { "(bad)",          { XX } },
7488     { "(bad)",          { XX } },
7489     { "(bad)",          { XX } },
7490     { "(bad)",          { XX } },
7491     { "(bad)",          { XX } },
7492     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7493     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7494     /* a8 */
7495     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7496     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7497     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7498     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7499     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7500     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7501     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7502     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7503     /* b0 */
7504     { "(bad)",          { XX } },
7505     { "(bad)",          { XX } },
7506     { "(bad)",          { XX } },
7507     { "(bad)",          { XX } },
7508     { "(bad)",          { XX } },
7509     { "(bad)",          { XX } },
7510     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7511     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7512     /* b8 */
7513     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7514     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7515     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7516     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7517     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7518     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7519     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7520     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7521     /* c0 */
7522     { "(bad)",          { XX } },
7523     { "(bad)",          { XX } },
7524     { "(bad)",          { XX } },
7525     { "(bad)",          { XX } },
7526     { "(bad)",          { XX } },
7527     { "(bad)",          { XX } },
7528     { "(bad)",          { XX } },
7529     { "(bad)",          { XX } },
7530     /* c8 */
7531     { "(bad)",          { XX } },
7532     { "(bad)",          { XX } },
7533     { "(bad)",          { XX } },
7534     { "(bad)",          { XX } },
7535     { "(bad)",          { XX } },
7536     { "(bad)",          { XX } },
7537     { "(bad)",          { XX } },
7538     { "(bad)",          { XX } },
7539     /* d0 */
7540     { "(bad)",          { XX } },
7541     { "(bad)",          { XX } },
7542     { "(bad)",          { XX } },
7543     { "(bad)",          { XX } },
7544     { "(bad)",          { XX } },
7545     { "(bad)",          { XX } },
7546     { "(bad)",          { XX } },
7547     { "(bad)",          { XX } },
7548     /* d8 */
7549     { "(bad)",          { XX } },
7550     { "(bad)",          { XX } },
7551     { "(bad)",          { XX } },
7552     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7553     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7554     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7555     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7556     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7557     /* e0 */
7558     { "(bad)",          { XX } },
7559     { "(bad)",          { XX } },
7560     { "(bad)",          { XX } },
7561     { "(bad)",          { XX } },
7562     { "(bad)",          { XX } },
7563     { "(bad)",          { XX } },
7564     { "(bad)",          { XX } },
7565     { "(bad)",          { XX } },
7566     /* e8 */
7567     { "(bad)",          { XX } },
7568     { "(bad)",          { XX } },
7569     { "(bad)",          { XX } },
7570     { "(bad)",          { XX } },
7571     { "(bad)",          { XX } },
7572     { "(bad)",          { XX } },
7573     { "(bad)",          { XX } },
7574     { "(bad)",          { XX } },
7575     /* f0 */
7576     { "(bad)",          { XX } },
7577     { "(bad)",          { XX } },
7578     { "(bad)",          { XX } },
7579     { "(bad)",          { XX } },
7580     { "(bad)",          { XX } },
7581     { "(bad)",          { XX } },
7582     { "(bad)",          { XX } },
7583     { "(bad)",          { XX } },
7584     /* f8 */
7585     { "(bad)",          { XX } },
7586     { "(bad)",          { XX } },
7587     { "(bad)",          { XX } },
7588     { "(bad)",          { XX } },
7589     { "(bad)",          { XX } },
7590     { "(bad)",          { XX } },
7591     { "(bad)",          { XX } },
7592     { "(bad)",          { XX } },
7593   },
7594   /* VEX_0F3A */
7595   {
7596     /* 00 */
7597     { "(bad)",          { XX } },
7598     { "(bad)",          { XX } },
7599     { "(bad)",          { XX } },
7600     { "(bad)",          { XX } },
7601     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7602     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7603     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7604     { "(bad)",          { XX } },
7605     /* 08 */
7606     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7607     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7608     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7609     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7610     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7611     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7612     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7613     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7614     /* 10 */
7615     { "(bad)",          { XX } },
7616     { "(bad)",          { XX } },
7617     { "(bad)",          { XX } },
7618     { "(bad)",          { XX } },
7619     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7620     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7621     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7622     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7623     /* 18 */
7624     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7625     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7626     { "(bad)",          { XX } },
7627     { "(bad)",          { XX } },
7628     { "(bad)",          { XX } },
7629     { "(bad)",          { XX } },
7630     { "(bad)",          { XX } },
7631     { "(bad)",          { XX } },
7632     /* 20 */
7633     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7634     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7635     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7636     { "(bad)",          { XX } },
7637     { "(bad)",          { XX } },
7638     { "(bad)",          { XX } },
7639     { "(bad)",          { XX } },
7640     { "(bad)",          { XX } },
7641     /* 28 */
7642     { "(bad)",          { XX } },
7643     { "(bad)",          { XX } },
7644     { "(bad)",          { XX } },
7645     { "(bad)",          { XX } },
7646     { "(bad)",          { XX } },
7647     { "(bad)",          { XX } },
7648     { "(bad)",          { XX } },
7649     { "(bad)",          { XX } },
7650     /* 30 */
7651     { "(bad)",          { XX } },
7652     { "(bad)",          { XX } },
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     { "(bad)",          { XX } },
7656     { "(bad)",          { XX } },
7657     { "(bad)",          { XX } },
7658     { "(bad)",          { XX } },
7659     /* 38 */
7660     { "(bad)",          { XX } },
7661     { "(bad)",          { XX } },
7662     { "(bad)",          { XX } },
7663     { "(bad)",          { XX } },
7664     { "(bad)",          { XX } },
7665     { "(bad)",          { XX } },
7666     { "(bad)",          { XX } },
7667     { "(bad)",          { XX } },
7668     /* 40 */
7669     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7670     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7671     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7672     { "(bad)",          { XX } },
7673     { "(bad)",          { XX } },
7674     { "(bad)",          { XX } },
7675     { "(bad)",          { XX } },
7676     { "(bad)",          { XX } },
7677     /* 48 */
7678     { "(bad)",          { XX } },
7679     { "(bad)",          { XX } },
7680     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7681     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7682     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7683     { "(bad)",          { XX } },
7684     { "(bad)",          { XX } },
7685     { "(bad)",          { XX } },
7686     /* 50 */
7687     { "(bad)",          { XX } },
7688     { "(bad)",          { XX } },
7689     { "(bad)",          { XX } },
7690     { "(bad)",          { XX } },
7691     { "(bad)",          { XX } },
7692     { "(bad)",          { XX } },
7693     { "(bad)",          { XX } },
7694     { "(bad)",          { XX } },
7695     /* 58 */
7696     { "(bad)",          { XX } },
7697     { "(bad)",          { XX } },
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     { "(bad)",          { XX } },
7704     /* 60 */
7705     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7706     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7707     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7708     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     { "(bad)",          { XX } },
7713     /* 68 */
7714     { "(bad)",          { XX } },
7715     { "(bad)",          { XX } },
7716     { "(bad)",          { XX } },
7717     { "(bad)",          { XX } },
7718     { "(bad)",          { XX } },
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     { "(bad)",          { XX } },
7722     /* 70 */
7723     { "(bad)",          { XX } },
7724     { "(bad)",          { XX } },
7725     { "(bad)",          { XX } },
7726     { "(bad)",          { XX } },
7727     { "(bad)",          { XX } },
7728     { "(bad)",          { XX } },
7729     { "(bad)",          { XX } },
7730     { "(bad)",          { XX } },
7731     /* 78 */
7732     { "(bad)",          { XX } },
7733     { "(bad)",          { XX } },
7734     { "(bad)",          { XX } },
7735     { "(bad)",          { XX } },
7736     { "(bad)",          { XX } },
7737     { "(bad)",          { XX } },
7738     { "(bad)",          { XX } },
7739     { "(bad)",          { XX } },
7740     /* 80 */
7741     { "(bad)",          { XX } },
7742     { "(bad)",          { XX } },
7743     { "(bad)",          { XX } },
7744     { "(bad)",          { XX } },
7745     { "(bad)",          { XX } },
7746     { "(bad)",          { XX } },
7747     { "(bad)",          { XX } },
7748     { "(bad)",          { XX } },
7749     /* 88 */
7750     { "(bad)",          { XX } },
7751     { "(bad)",          { XX } },
7752     { "(bad)",          { XX } },
7753     { "(bad)",          { XX } },
7754     { "(bad)",          { XX } },
7755     { "(bad)",          { XX } },
7756     { "(bad)",          { XX } },
7757     { "(bad)",          { XX } },
7758     /* 90 */
7759     { "(bad)",          { XX } },
7760     { "(bad)",          { XX } },
7761     { "(bad)",          { XX } },
7762     { "(bad)",          { XX } },
7763     { "(bad)",          { XX } },
7764     { "(bad)",          { XX } },
7765     { "(bad)",          { XX } },
7766     { "(bad)",          { XX } },
7767     /* 98 */
7768     { "(bad)",          { XX } },
7769     { "(bad)",          { XX } },
7770     { "(bad)",          { XX } },
7771     { "(bad)",          { XX } },
7772     { "(bad)",          { XX } },
7773     { "(bad)",          { XX } },
7774     { "(bad)",          { XX } },
7775     { "(bad)",          { XX } },
7776     /* a0 */
7777     { "(bad)",          { XX } },
7778     { "(bad)",          { XX } },
7779     { "(bad)",          { XX } },
7780     { "(bad)",          { XX } },
7781     { "(bad)",          { XX } },
7782     { "(bad)",          { XX } },
7783     { "(bad)",          { XX } },
7784     { "(bad)",          { XX } },
7785     /* a8 */
7786     { "(bad)",          { XX } },
7787     { "(bad)",          { XX } },
7788     { "(bad)",          { XX } },
7789     { "(bad)",          { XX } },
7790     { "(bad)",          { XX } },
7791     { "(bad)",          { XX } },
7792     { "(bad)",          { XX } },
7793     { "(bad)",          { XX } },
7794     /* b0 */
7795     { "(bad)",          { XX } },
7796     { "(bad)",          { XX } },
7797     { "(bad)",          { XX } },
7798     { "(bad)",          { XX } },
7799     { "(bad)",          { XX } },
7800     { "(bad)",          { XX } },
7801     { "(bad)",          { XX } },
7802     { "(bad)",          { XX } },
7803     /* b8 */
7804     { "(bad)",          { XX } },
7805     { "(bad)",          { XX } },
7806     { "(bad)",          { XX } },
7807     { "(bad)",          { XX } },
7808     { "(bad)",          { XX } },
7809     { "(bad)",          { XX } },
7810     { "(bad)",          { XX } },
7811     { "(bad)",          { XX } },
7812     /* c0 */
7813     { "(bad)",          { XX } },
7814     { "(bad)",          { XX } },
7815     { "(bad)",          { XX } },
7816     { "(bad)",          { XX } },
7817     { "(bad)",          { XX } },
7818     { "(bad)",          { XX } },
7819     { "(bad)",          { XX } },
7820     { "(bad)",          { XX } },
7821     /* c8 */
7822     { "(bad)",          { XX } },
7823     { "(bad)",          { XX } },
7824     { "(bad)",          { XX } },
7825     { "(bad)",          { XX } },
7826     { "(bad)",          { XX } },
7827     { "(bad)",          { XX } },
7828     { "(bad)",          { XX } },
7829     { "(bad)",          { XX } },
7830     /* d0 */
7831     { "(bad)",          { XX } },
7832     { "(bad)",          { XX } },
7833     { "(bad)",          { XX } },
7834     { "(bad)",          { XX } },
7835     { "(bad)",          { XX } },
7836     { "(bad)",          { XX } },
7837     { "(bad)",          { XX } },
7838     { "(bad)",          { XX } },
7839     /* d8 */
7840     { "(bad)",          { XX } },
7841     { "(bad)",          { XX } },
7842     { "(bad)",          { XX } },
7843     { "(bad)",          { XX } },
7844     { "(bad)",          { XX } },
7845     { "(bad)",          { XX } },
7846     { "(bad)",          { XX } },
7847     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7848     /* e0 */
7849     { "(bad)",          { XX } },
7850     { "(bad)",          { XX } },
7851     { "(bad)",          { XX } },
7852     { "(bad)",          { XX } },
7853     { "(bad)",          { XX } },
7854     { "(bad)",          { XX } },
7855     { "(bad)",          { XX } },
7856     { "(bad)",          { XX } },
7857     /* e8 */
7858     { "(bad)",          { XX } },
7859     { "(bad)",          { XX } },
7860     { "(bad)",          { XX } },
7861     { "(bad)",          { XX } },
7862     { "(bad)",          { XX } },
7863     { "(bad)",          { XX } },
7864     { "(bad)",          { XX } },
7865     { "(bad)",          { XX } },
7866     /* f0 */
7867     { "(bad)",          { XX } },
7868     { "(bad)",          { XX } },
7869     { "(bad)",          { XX } },
7870     { "(bad)",          { XX } },
7871     { "(bad)",          { XX } },
7872     { "(bad)",          { XX } },
7873     { "(bad)",          { XX } },
7874     { "(bad)",          { XX } },
7875     /* f8 */
7876     { "(bad)",          { XX } },
7877     { "(bad)",          { XX } },
7878     { "(bad)",          { XX } },
7879     { "(bad)",          { XX } },
7880     { "(bad)",          { XX } },
7881     { "(bad)",          { XX } },
7882     { "(bad)",          { XX } },
7883     { "(bad)",          { XX } },
7884   },
7885 };
7886
7887 static const struct dis386 vex_len_table[][2] = {
7888   /* VEX_LEN_10_P_1 */
7889   {
7890     { "vmovss",         { XMVex, Vex128, EXd } },
7891     { "(bad)",          { XX } },
7892   },
7893
7894   /* VEX_LEN_10_P_3 */
7895   {
7896     { "vmovsd",         { XMVex, Vex128, EXq } },
7897     { "(bad)",          { XX } },
7898   },
7899
7900   /* VEX_LEN_11_P_1 */
7901   {
7902     { "vmovss",         { EXdVexS, Vex128, XM } },
7903     { "(bad)",          { XX } },
7904   },
7905
7906   /* VEX_LEN_11_P_3 */
7907   {
7908     { "vmovsd",         { EXqVexS, Vex128, XM } },
7909     { "(bad)",          { XX } },
7910   },
7911
7912   /* VEX_LEN_12_P_0_M_0 */
7913   {
7914     { "vmovlps",        { XM, Vex128, EXq } },
7915     { "(bad)",          { XX } },
7916   },
7917
7918   /* VEX_LEN_12_P_0_M_1 */
7919   {
7920     { "vmovhlps",       { XM, Vex128, EXq } },
7921     { "(bad)",          { XX } },
7922   },
7923
7924   /* VEX_LEN_12_P_2 */
7925   {
7926     { "vmovlpd",        { XM, Vex128, EXq } },
7927     { "(bad)",          { XX } },
7928   },
7929
7930   /* VEX_LEN_13_M_0 */
7931   {
7932     { "vmovlpX",        { EXq, XM } },
7933     { "(bad)",          { XX } },
7934   },
7935
7936   /* VEX_LEN_16_P_0_M_0 */
7937   {
7938     { "vmovhps",        { XM, Vex128, EXq } },
7939     { "(bad)",          { XX } },
7940   },
7941
7942   /* VEX_LEN_16_P_0_M_1 */
7943   {
7944     { "vmovlhps",       { XM, Vex128, EXq } },
7945     { "(bad)",          { XX } },
7946   },
7947
7948   /* VEX_LEN_16_P_2 */
7949   {
7950     { "vmovhpd",        { XM, Vex128, EXq } },
7951     { "(bad)",          { XX } },
7952   },
7953
7954   /* VEX_LEN_17_M_0 */
7955   {
7956     { "vmovhpX",        { EXq, XM } },
7957     { "(bad)",          { XX } },
7958   },
7959
7960   /* VEX_LEN_2A_P_1 */
7961   {
7962     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7963     { "(bad)",          { XX } },
7964   },
7965
7966   /* VEX_LEN_2A_P_3 */
7967   {
7968     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7969     { "(bad)",          { XX } },
7970   },
7971
7972   /* VEX_LEN_2C_P_1 */
7973   {
7974     { "vcvttss2siY",    { Gv, EXd } },
7975     { "(bad)",          { XX } },
7976   },
7977
7978   /* VEX_LEN_2C_P_3 */
7979   {
7980     { "vcvttsd2siY",    { Gv, EXq } },
7981     { "(bad)",          { XX } },
7982   },
7983
7984   /* VEX_LEN_2D_P_1 */
7985   {
7986     { "vcvtss2siY",     { Gv, EXd } },
7987     { "(bad)",          { XX } },
7988   },
7989
7990   /* VEX_LEN_2D_P_3 */
7991   {
7992     { "vcvtsd2siY",     { Gv, EXq } },
7993     { "(bad)",          { XX } },
7994   },
7995
7996   /* VEX_LEN_2E_P_0 */
7997   {
7998     { "vucomiss",       { XM, EXd } },
7999     { "(bad)",          { XX } },
8000   },
8001
8002   /* VEX_LEN_2E_P_2 */
8003   {
8004     { "vucomisd",       { XM, EXq } },
8005     { "(bad)",          { XX } },
8006   },
8007
8008   /* VEX_LEN_2F_P_0 */
8009   {
8010     { "vcomiss",        { XM, EXd } },
8011     { "(bad)",          { XX } },
8012   },
8013
8014   /* VEX_LEN_2F_P_2 */
8015   {
8016     { "vcomisd",        { XM, EXq } },
8017     { "(bad)",          { XX } },
8018   },
8019
8020   /* VEX_LEN_51_P_1 */
8021   {
8022     { "vsqrtss",        { XM, Vex128, EXd } },
8023     { "(bad)",          { XX } },
8024   },
8025
8026   /* VEX_LEN_51_P_3 */
8027   {
8028     { "vsqrtsd",        { XM, Vex128, EXq } },
8029     { "(bad)",          { XX } },
8030   },
8031
8032   /* VEX_LEN_52_P_1 */
8033   {
8034     { "vrsqrtss",       { XM, Vex128, EXd } },
8035     { "(bad)",          { XX } },
8036   },
8037
8038   /* VEX_LEN_53_P_1 */
8039   {
8040     { "vrcpss",         { XM, Vex128, EXd } },
8041     { "(bad)",          { XX } },
8042   },
8043
8044   /* VEX_LEN_58_P_1 */
8045   {
8046     { "vaddss",         { XM, Vex128, EXd } },
8047     { "(bad)",          { XX } },
8048   },
8049
8050   /* VEX_LEN_58_P_3 */
8051   {
8052     { "vaddsd",         { XM, Vex128, EXq } },
8053     { "(bad)",          { XX } },
8054   },
8055
8056   /* VEX_LEN_59_P_1 */
8057   {
8058     { "vmulss",         { XM, Vex128, EXd } },
8059     { "(bad)",          { XX } },
8060   },
8061
8062   /* VEX_LEN_59_P_3 */
8063   {
8064     { "vmulsd",         { XM, Vex128, EXq } },
8065     { "(bad)",          { XX } },
8066   },
8067
8068   /* VEX_LEN_5A_P_1 */
8069   {
8070     { "vcvtss2sd",      { XM, Vex128, EXd } },
8071     { "(bad)",          { XX } },
8072   },
8073
8074   /* VEX_LEN_5A_P_3 */
8075   {
8076     { "vcvtsd2ss",      { XM, Vex128, EXq } },
8077     { "(bad)",          { XX } },
8078   },
8079
8080   /* VEX_LEN_5C_P_1 */
8081   {
8082     { "vsubss",         { XM, Vex128, EXd } },
8083     { "(bad)",          { XX } },
8084   },
8085
8086   /* VEX_LEN_5C_P_3 */
8087   {
8088     { "vsubsd",         { XM, Vex128, EXq } },
8089     { "(bad)",          { XX } },
8090   },
8091
8092   /* VEX_LEN_5D_P_1 */
8093   {
8094     { "vminss",         { XM, Vex128, EXd } },
8095     { "(bad)",          { XX } },
8096   },
8097
8098   /* VEX_LEN_5D_P_3 */
8099   {
8100     { "vminsd",         { XM, Vex128, EXq } },
8101     { "(bad)",          { XX } },
8102   },
8103
8104   /* VEX_LEN_5E_P_1 */
8105   {
8106     { "vdivss",         { XM, Vex128, EXd } },
8107     { "(bad)",          { XX } },
8108   },
8109
8110   /* VEX_LEN_5E_P_3 */
8111   {
8112     { "vdivsd",         { XM, Vex128, EXq } },
8113     { "(bad)",          { XX } },
8114   },
8115
8116   /* VEX_LEN_5F_P_1 */
8117   {
8118     { "vmaxss",         { XM, Vex128, EXd } },
8119     { "(bad)",          { XX } },
8120   },
8121
8122   /* VEX_LEN_5F_P_3 */
8123   {
8124     { "vmaxsd",         { XM, Vex128, EXq } },
8125     { "(bad)",          { XX } },
8126   },
8127
8128   /* VEX_LEN_60_P_2 */
8129   {
8130     { "vpunpcklbw",     { XM, Vex128, EXx } },
8131     { "(bad)",          { XX } },
8132   },
8133
8134   /* VEX_LEN_61_P_2 */
8135   {
8136     { "vpunpcklwd",     { XM, Vex128, EXx } },
8137     { "(bad)",          { XX } },
8138   },
8139
8140   /* VEX_LEN_62_P_2 */
8141   {
8142     { "vpunpckldq",     { XM, Vex128, EXx } },
8143     { "(bad)",          { XX } },
8144   },
8145
8146   /* VEX_LEN_63_P_2 */
8147   {
8148     { "vpacksswb",      { XM, Vex128, EXx } },
8149     { "(bad)",          { XX } },
8150   },
8151
8152   /* VEX_LEN_64_P_2 */
8153   {
8154     { "vpcmpgtb",       { XM, Vex128, EXx } },
8155     { "(bad)",          { XX } },
8156   },
8157
8158   /* VEX_LEN_65_P_2 */
8159   {
8160     { "vpcmpgtw",       { XM, Vex128, EXx } },
8161     { "(bad)",          { XX } },
8162   },
8163
8164   /* VEX_LEN_66_P_2 */
8165   {
8166     { "vpcmpgtd",       { XM, Vex128, EXx } },
8167     { "(bad)",          { XX } },
8168   },
8169
8170   /* VEX_LEN_67_P_2 */
8171   {
8172     { "vpackuswb",      { XM, Vex128, EXx } },
8173     { "(bad)",          { XX } },
8174   },
8175
8176   /* VEX_LEN_68_P_2 */
8177   {
8178     { "vpunpckhbw",     { XM, Vex128, EXx } },
8179     { "(bad)",          { XX } },
8180   },
8181
8182   /* VEX_LEN_69_P_2 */
8183   {
8184     { "vpunpckhwd",     { XM, Vex128, EXx } },
8185     { "(bad)",          { XX } },
8186   },
8187
8188   /* VEX_LEN_6A_P_2 */
8189   {
8190     { "vpunpckhdq",     { XM, Vex128, EXx } },
8191     { "(bad)",          { XX } },
8192   },
8193
8194   /* VEX_LEN_6B_P_2 */
8195   {
8196     { "vpackssdw",      { XM, Vex128, EXx } },
8197     { "(bad)",          { XX } },
8198   },
8199
8200   /* VEX_LEN_6C_P_2 */
8201   {
8202     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8203     { "(bad)",          { XX } },
8204   },
8205
8206   /* VEX_LEN_6D_P_2 */
8207   {
8208     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8209     { "(bad)",          { XX } },
8210   },
8211
8212   /* VEX_LEN_6E_P_2 */
8213   {
8214     { "vmovK",          { XM, Edq } },
8215     { "(bad)",          { XX } },
8216   },
8217
8218   /* VEX_LEN_70_P_1 */
8219   {
8220     { "vpshufhw",       { XM, EXx, Ib } },
8221     { "(bad)",          { XX } },
8222   },
8223
8224   /* VEX_LEN_70_P_2 */
8225   {
8226     { "vpshufd",        { XM, EXx, Ib } },
8227     { "(bad)",          { XX } },
8228   },
8229
8230   /* VEX_LEN_70_P_3 */
8231   {
8232     { "vpshuflw",       { XM, EXx, Ib } },
8233     { "(bad)",          { XX } },
8234   },
8235
8236   /* VEX_LEN_71_R_2_P_2 */
8237   {
8238     { "vpsrlw",         { Vex128, XS, Ib } },
8239     { "(bad)",          { XX } },
8240   },
8241
8242   /* VEX_LEN_71_R_4_P_2 */
8243   {
8244     { "vpsraw",         { Vex128, XS, Ib } },
8245     { "(bad)",          { XX } },
8246   },
8247
8248   /* VEX_LEN_71_R_6_P_2 */
8249   {
8250     { "vpsllw",         { Vex128, XS, Ib } },
8251     { "(bad)",          { XX } },
8252   },
8253
8254   /* VEX_LEN_72_R_2_P_2 */
8255   {
8256     { "vpsrld",         { Vex128, XS, Ib } },
8257     { "(bad)",          { XX } },
8258   },
8259
8260   /* VEX_LEN_72_R_4_P_2 */
8261   {
8262     { "vpsrad",         { Vex128, XS, Ib } },
8263     { "(bad)",          { XX } },
8264   },
8265
8266   /* VEX_LEN_72_R_6_P_2 */
8267   {
8268     { "vpslld",         { Vex128, XS, Ib } },
8269     { "(bad)",          { XX } },
8270   },
8271
8272   /* VEX_LEN_73_R_2_P_2 */
8273   {
8274     { "vpsrlq",         { Vex128, XS, Ib } },
8275     { "(bad)",          { XX } },
8276   },
8277
8278   /* VEX_LEN_73_R_3_P_2 */
8279   {
8280     { "vpsrldq",        { Vex128, XS, Ib } },
8281     { "(bad)",          { XX } },
8282   },
8283
8284   /* VEX_LEN_73_R_6_P_2 */
8285   {
8286     { "vpsllq",         { Vex128, XS, Ib } },
8287     { "(bad)",          { XX } },
8288   },
8289
8290   /* VEX_LEN_73_R_7_P_2 */
8291   {
8292     { "vpslldq",        { Vex128, XS, Ib } },
8293     { "(bad)",          { XX } },
8294   },
8295
8296   /* VEX_LEN_74_P_2 */
8297   {
8298     { "vpcmpeqb",       { XM, Vex128, EXx } },
8299     { "(bad)",          { XX } },
8300   },
8301
8302   /* VEX_LEN_75_P_2 */
8303   {
8304     { "vpcmpeqw",       { XM, Vex128, EXx } },
8305     { "(bad)",          { XX } },
8306   },
8307
8308   /* VEX_LEN_76_P_2 */
8309   {
8310     { "vpcmpeqd",       { XM, Vex128, EXx } },
8311     { "(bad)",          { XX } },
8312   },
8313
8314   /* VEX_LEN_7E_P_1 */
8315   {
8316     { "vmovq",          { XM, EXq } },
8317     { "(bad)",          { XX } },
8318   },
8319
8320   /* VEX_LEN_7E_P_2 */
8321   {
8322     { "vmovK",          { Edq, XM } },
8323     { "(bad)",          { XX } },
8324   },
8325
8326   /* VEX_LEN_AE_R_2_M0 */
8327   {
8328     { "vldmxcsr",       { Md } },
8329     { "(bad)",          { XX } },
8330   },
8331
8332   /* VEX_LEN_AE_R_3_M0 */
8333   {
8334     { "vstmxcsr",       { Md } },
8335     { "(bad)",          { XX } },
8336   },
8337
8338   /* VEX_LEN_C2_P_1 */
8339   {
8340     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8341     { "(bad)",          { XX } },
8342   },
8343
8344   /* VEX_LEN_C2_P_3 */
8345   {
8346     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8347     { "(bad)",          { XX } },
8348   },
8349
8350   /* VEX_LEN_C4_P_2 */
8351   {
8352     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8353     { "(bad)",          { XX } },
8354   },
8355
8356   /* VEX_LEN_C5_P_2 */
8357   {
8358     { "vpextrw",        { Gdq, XS, Ib } },
8359     { "(bad)",          { XX } },
8360   },
8361
8362   /* VEX_LEN_D1_P_2 */
8363   {
8364     { "vpsrlw",         { XM, Vex128, EXx } },
8365     { "(bad)",          { XX } },
8366   },
8367
8368   /* VEX_LEN_D2_P_2 */
8369   {
8370     { "vpsrld",         { XM, Vex128, EXx } },
8371     { "(bad)",          { XX } },
8372   },
8373
8374   /* VEX_LEN_D3_P_2 */
8375   {
8376     { "vpsrlq",         { XM, Vex128, EXx } },
8377     { "(bad)",          { XX } },
8378   },
8379
8380   /* VEX_LEN_D4_P_2 */
8381   {
8382     { "vpaddq",         { XM, Vex128, EXx } },
8383     { "(bad)",          { XX } },
8384   },
8385
8386   /* VEX_LEN_D5_P_2 */
8387   {
8388     { "vpmullw",        { XM, Vex128, EXx } },
8389     { "(bad)",          { XX } },
8390   },
8391
8392   /* VEX_LEN_D6_P_2 */
8393   {
8394     { "vmovq",          { EXqS, XM } },
8395     { "(bad)",          { XX } },
8396   },
8397
8398   /* VEX_LEN_D7_P_2_M_1 */
8399   {
8400     { "vpmovmskb",      { Gdq, XS } },
8401     { "(bad)",          { XX } },
8402   },
8403
8404   /* VEX_LEN_D8_P_2 */
8405   {
8406     { "vpsubusb",       { XM, Vex128, EXx } },
8407     { "(bad)",          { XX } },
8408   },
8409
8410   /* VEX_LEN_D9_P_2 */
8411   {
8412     { "vpsubusw",       { XM, Vex128, EXx } },
8413     { "(bad)",          { XX } },
8414   },
8415
8416   /* VEX_LEN_DA_P_2 */
8417   {
8418     { "vpminub",        { XM, Vex128, EXx } },
8419     { "(bad)",          { XX } },
8420   },
8421
8422   /* VEX_LEN_DB_P_2 */
8423   {
8424     { "vpand",          { XM, Vex128, EXx } },
8425     { "(bad)",          { XX } },
8426   },
8427
8428   /* VEX_LEN_DC_P_2 */
8429   {
8430     { "vpaddusb",       { XM, Vex128, EXx } },
8431     { "(bad)",          { XX } },
8432   },
8433
8434   /* VEX_LEN_DD_P_2 */
8435   {
8436     { "vpaddusw",       { XM, Vex128, EXx } },
8437     { "(bad)",          { XX } },
8438   },
8439
8440   /* VEX_LEN_DE_P_2 */
8441   {
8442     { "vpmaxub",        { XM, Vex128, EXx } },
8443     { "(bad)",          { XX } },
8444   },
8445
8446   /* VEX_LEN_DF_P_2 */
8447   {
8448     { "vpandn",         { XM, Vex128, EXx } },
8449     { "(bad)",          { XX } },
8450   },
8451
8452   /* VEX_LEN_E0_P_2 */
8453   {
8454     { "vpavgb",         { XM, Vex128, EXx } },
8455     { "(bad)",          { XX } },
8456   },
8457
8458   /* VEX_LEN_E1_P_2 */
8459   {
8460     { "vpsraw",         { XM, Vex128, EXx } },
8461     { "(bad)",          { XX } },
8462   },
8463
8464   /* VEX_LEN_E2_P_2 */
8465   {
8466     { "vpsrad",         { XM, Vex128, EXx } },
8467     { "(bad)",          { XX } },
8468   },
8469
8470   /* VEX_LEN_E3_P_2 */
8471   {
8472     { "vpavgw",         { XM, Vex128, EXx } },
8473     { "(bad)",          { XX } },
8474   },
8475
8476   /* VEX_LEN_E4_P_2 */
8477   {
8478     { "vpmulhuw",       { XM, Vex128, EXx } },
8479     { "(bad)",          { XX } },
8480   },
8481
8482   /* VEX_LEN_E5_P_2 */
8483   {
8484     { "vpmulhw",        { XM, Vex128, EXx } },
8485     { "(bad)",          { XX } },
8486   },
8487
8488   /* VEX_LEN_E8_P_2 */
8489   {
8490     { "vpsubsb",        { XM, Vex128, EXx } },
8491     { "(bad)",          { XX } },
8492   },
8493
8494   /* VEX_LEN_E9_P_2 */
8495   {
8496     { "vpsubsw",        { XM, Vex128, EXx } },
8497     { "(bad)",          { XX } },
8498   },
8499
8500   /* VEX_LEN_EA_P_2 */
8501   {
8502     { "vpminsw",        { XM, Vex128, EXx } },
8503     { "(bad)",          { XX } },
8504   },
8505
8506   /* VEX_LEN_EB_P_2 */
8507   {
8508     { "vpor",           { XM, Vex128, EXx } },
8509     { "(bad)",          { XX } },
8510   },
8511
8512   /* VEX_LEN_EC_P_2 */
8513   {
8514     { "vpaddsb",        { XM, Vex128, EXx } },
8515     { "(bad)",          { XX } },
8516   },
8517
8518   /* VEX_LEN_ED_P_2 */
8519   {
8520     { "vpaddsw",        { XM, Vex128, EXx } },
8521     { "(bad)",          { XX } },
8522   },
8523
8524   /* VEX_LEN_EE_P_2 */
8525   {
8526     { "vpmaxsw",        { XM, Vex128, EXx } },
8527     { "(bad)",          { XX } },
8528   },
8529
8530   /* VEX_LEN_EF_P_2 */
8531   {
8532     { "vpxor",          { XM, Vex128, EXx } },
8533     { "(bad)",          { XX } },
8534   },
8535
8536   /* VEX_LEN_F1_P_2 */
8537   {
8538     { "vpsllw",         { XM, Vex128, EXx } },
8539     { "(bad)",          { XX } },
8540   },
8541
8542   /* VEX_LEN_F2_P_2 */
8543   {
8544     { "vpslld",         { XM, Vex128, EXx } },
8545     { "(bad)",          { XX } },
8546   },
8547
8548   /* VEX_LEN_F3_P_2 */
8549   {
8550     { "vpsllq",         { XM, Vex128, EXx } },
8551     { "(bad)",          { XX } },
8552   },
8553
8554   /* VEX_LEN_F4_P_2 */
8555   {
8556     { "vpmuludq",       { XM, Vex128, EXx } },
8557     { "(bad)",          { XX } },
8558   },
8559
8560   /* VEX_LEN_F5_P_2 */
8561   {
8562     { "vpmaddwd",       { XM, Vex128, EXx } },
8563     { "(bad)",          { XX } },
8564   },
8565
8566   /* VEX_LEN_F6_P_2 */
8567   {
8568     { "vpsadbw",        { XM, Vex128, EXx } },
8569     { "(bad)",          { XX } },
8570   },
8571
8572   /* VEX_LEN_F7_P_2 */
8573   {
8574     { "vmaskmovdqu",    { XM, XS } },
8575     { "(bad)",          { XX } },
8576   },
8577
8578   /* VEX_LEN_F8_P_2 */
8579   {
8580     { "vpsubb",         { XM, Vex128, EXx } },
8581     { "(bad)",          { XX } },
8582   },
8583
8584   /* VEX_LEN_F9_P_2 */
8585   {
8586     { "vpsubw",         { XM, Vex128, EXx } },
8587     { "(bad)",          { XX } },
8588   },
8589
8590   /* VEX_LEN_FA_P_2 */
8591   {
8592     { "vpsubd",         { XM, Vex128, EXx } },
8593     { "(bad)",          { XX } },
8594   },
8595
8596   /* VEX_LEN_FB_P_2 */
8597   {
8598     { "vpsubq",         { XM, Vex128, EXx } },
8599     { "(bad)",          { XX } },
8600   },
8601
8602   /* VEX_LEN_FC_P_2 */
8603   {
8604     { "vpaddb",         { XM, Vex128, EXx } },
8605     { "(bad)",          { XX } },
8606   },
8607
8608   /* VEX_LEN_FD_P_2 */
8609   {
8610     { "vpaddw",         { XM, Vex128, EXx } },
8611     { "(bad)",          { XX } },
8612   },
8613
8614   /* VEX_LEN_FE_P_2 */
8615   {
8616     { "vpaddd",         { XM, Vex128, EXx } },
8617     { "(bad)",          { XX } },
8618   },
8619
8620   /* VEX_LEN_3800_P_2 */
8621   {
8622     { "vpshufb",        { XM, Vex128, EXx } },
8623     { "(bad)",          { XX } },
8624   },
8625
8626   /* VEX_LEN_3801_P_2 */
8627   {
8628     { "vphaddw",        { XM, Vex128, EXx } },
8629     { "(bad)",          { XX } },
8630   },
8631
8632   /* VEX_LEN_3802_P_2 */
8633   {
8634     { "vphaddd",        { XM, Vex128, EXx } },
8635     { "(bad)",          { XX } },
8636   },
8637
8638   /* VEX_LEN_3803_P_2 */
8639   {
8640     { "vphaddsw",       { XM, Vex128, EXx } },
8641     { "(bad)",          { XX } },
8642   },
8643
8644   /* VEX_LEN_3804_P_2 */
8645   {
8646     { "vpmaddubsw",     { XM, Vex128, EXx } },
8647     { "(bad)",          { XX } },
8648   },
8649
8650   /* VEX_LEN_3805_P_2 */
8651   {
8652     { "vphsubw",        { XM, Vex128, EXx } },
8653     { "(bad)",          { XX } },
8654   },
8655
8656   /* VEX_LEN_3806_P_2 */
8657   {
8658     { "vphsubd",        { XM, Vex128, EXx } },
8659     { "(bad)",          { XX } },
8660   },
8661
8662   /* VEX_LEN_3807_P_2 */
8663   {
8664     { "vphsubsw",       { XM, Vex128, EXx } },
8665     { "(bad)",          { XX } },
8666   },
8667
8668   /* VEX_LEN_3808_P_2 */
8669   {
8670     { "vpsignb",        { XM, Vex128, EXx } },
8671     { "(bad)",          { XX } },
8672   },
8673
8674   /* VEX_LEN_3809_P_2 */
8675   {
8676     { "vpsignw",        { XM, Vex128, EXx } },
8677     { "(bad)",          { XX } },
8678   },
8679
8680   /* VEX_LEN_380A_P_2 */
8681   {
8682     { "vpsignd",        { XM, Vex128, EXx } },
8683     { "(bad)",          { XX } },
8684   },
8685
8686   /* VEX_LEN_380B_P_2 */
8687   {
8688     { "vpmulhrsw",      { XM, Vex128, EXx } },
8689     { "(bad)",          { XX } },
8690   },
8691
8692   /* VEX_LEN_3819_P_2_M_0 */
8693   {
8694     { "(bad)",          { XX } },
8695     { "vbroadcastsd",   { XM, Mq } },
8696   },
8697
8698   /* VEX_LEN_381A_P_2_M_0 */
8699   {
8700     { "(bad)",          { XX } },
8701     { "vbroadcastf128", { XM, Mxmm } },
8702   },
8703
8704   /* VEX_LEN_381C_P_2 */
8705   {
8706     { "vpabsb",         { XM, EXx } },
8707     { "(bad)",          { XX } },
8708   },
8709
8710   /* VEX_LEN_381D_P_2 */
8711   {
8712     { "vpabsw",         { XM, EXx } },
8713     { "(bad)",          { XX } },
8714   },
8715
8716   /* VEX_LEN_381E_P_2 */
8717   {
8718     { "vpabsd",         { XM, EXx } },
8719     { "(bad)",          { XX } },
8720   },
8721
8722   /* VEX_LEN_3820_P_2 */
8723   {
8724     { "vpmovsxbw",      { XM, EXq } },
8725     { "(bad)",          { XX } },
8726   },
8727
8728   /* VEX_LEN_3821_P_2 */
8729   {
8730     { "vpmovsxbd",      { XM, EXd } },
8731     { "(bad)",          { XX } },
8732   },
8733
8734   /* VEX_LEN_3822_P_2 */
8735   {
8736     { "vpmovsxbq",      { XM, EXw } },
8737     { "(bad)",          { XX } },
8738   },
8739
8740   /* VEX_LEN_3823_P_2 */
8741   {
8742     { "vpmovsxwd",      { XM, EXq } },
8743     { "(bad)",          { XX } },
8744   },
8745
8746   /* VEX_LEN_3824_P_2 */
8747   {
8748     { "vpmovsxwq",      { XM, EXd } },
8749     { "(bad)",          { XX } },
8750   },
8751
8752   /* VEX_LEN_3825_P_2 */
8753   {
8754     { "vpmovsxdq",      { XM, EXq } },
8755     { "(bad)",          { XX } },
8756   },
8757
8758   /* VEX_LEN_3828_P_2 */
8759   {
8760     { "vpmuldq",        { XM, Vex128, EXx } },
8761     { "(bad)",          { XX } },
8762   },
8763
8764   /* VEX_LEN_3829_P_2 */
8765   {
8766     { "vpcmpeqq",       { XM, Vex128, EXx } },
8767     { "(bad)",          { XX } },
8768   },
8769
8770   /* VEX_LEN_382A_P_2_M_0 */
8771   {
8772     { "vmovntdqa",      { XM, Mx } },
8773     { "(bad)",          { XX } },
8774   },
8775
8776   /* VEX_LEN_382B_P_2 */
8777   {
8778     { "vpackusdw",      { XM, Vex128, EXx } },
8779     { "(bad)",          { XX } },
8780   },
8781
8782   /* VEX_LEN_3830_P_2 */
8783   {
8784     { "vpmovzxbw",      { XM, EXq } },
8785     { "(bad)",          { XX } },
8786   },
8787
8788   /* VEX_LEN_3831_P_2 */
8789   {
8790     { "vpmovzxbd",      { XM, EXd } },
8791     { "(bad)",          { XX } },
8792   },
8793
8794   /* VEX_LEN_3832_P_2 */
8795   {
8796     { "vpmovzxbq",      { XM, EXw } },
8797     { "(bad)",          { XX } },
8798   },
8799
8800   /* VEX_LEN_3833_P_2 */
8801   {
8802     { "vpmovzxwd",      { XM, EXq } },
8803     { "(bad)",          { XX } },
8804   },
8805
8806   /* VEX_LEN_3834_P_2 */
8807   {
8808     { "vpmovzxwq",      { XM, EXd } },
8809     { "(bad)",          { XX } },
8810   },
8811
8812   /* VEX_LEN_3835_P_2 */
8813   {
8814     { "vpmovzxdq",      { XM, EXq } },
8815     { "(bad)",          { XX } },
8816   },
8817
8818   /* VEX_LEN_3837_P_2 */
8819   {
8820     { "vpcmpgtq",       { XM, Vex128, EXx } },
8821     { "(bad)",          { XX } },
8822   },
8823
8824   /* VEX_LEN_3838_P_2 */
8825   {
8826     { "vpminsb",        { XM, Vex128, EXx } },
8827     { "(bad)",          { XX } },
8828   },
8829
8830   /* VEX_LEN_3839_P_2 */
8831   {
8832     { "vpminsd",        { XM, Vex128, EXx } },
8833     { "(bad)",          { XX } },
8834   },
8835
8836   /* VEX_LEN_383A_P_2 */
8837   {
8838     { "vpminuw",        { XM, Vex128, EXx } },
8839     { "(bad)",          { XX } },
8840   },
8841
8842   /* VEX_LEN_383B_P_2 */
8843   {
8844     { "vpminud",        { XM, Vex128, EXx } },
8845     { "(bad)",          { XX } },
8846   },
8847
8848   /* VEX_LEN_383C_P_2 */
8849   {
8850     { "vpmaxsb",        { XM, Vex128, EXx } },
8851     { "(bad)",          { XX } },
8852   },
8853
8854   /* VEX_LEN_383D_P_2 */
8855   {
8856     { "vpmaxsd",        { XM, Vex128, EXx } },
8857     { "(bad)",          { XX } },
8858   },
8859
8860   /* VEX_LEN_383E_P_2 */
8861   {
8862     { "vpmaxuw",        { XM, Vex128, EXx } },
8863     { "(bad)",          { XX } },
8864   },
8865
8866   /* VEX_LEN_383F_P_2 */
8867   {
8868     { "vpmaxud",        { XM, Vex128, EXx } },
8869     { "(bad)",          { XX } },
8870   },
8871
8872   /* VEX_LEN_3840_P_2 */
8873   {
8874     { "vpmulld",        { XM, Vex128, EXx } },
8875     { "(bad)",          { XX } },
8876   },
8877
8878   /* VEX_LEN_3841_P_2 */
8879   {
8880     { "vphminposuw",    { XM, EXx } },
8881     { "(bad)",          { XX } },
8882   },
8883
8884   /* VEX_LEN_38DB_P_2 */
8885   {
8886     { "vaesimc",        { XM, EXx } },
8887     { "(bad)",          { XX } },
8888   },
8889
8890   /* VEX_LEN_38DC_P_2 */
8891   {
8892     { "vaesenc",        { XM, Vex128, EXx } },
8893     { "(bad)",          { XX } },
8894   },
8895
8896   /* VEX_LEN_38DD_P_2 */
8897   {
8898     { "vaesenclast",    { XM, Vex128, EXx } },
8899     { "(bad)",          { XX } },
8900   },
8901
8902   /* VEX_LEN_38DE_P_2 */
8903   {
8904     { "vaesdec",        { XM, Vex128, EXx } },
8905     { "(bad)",          { XX } },
8906   },
8907
8908   /* VEX_LEN_38DF_P_2 */
8909   {
8910     { "vaesdeclast",    { XM, Vex128, EXx } },
8911     { "(bad)",          { XX } },
8912   },
8913
8914   /* VEX_LEN_3A06_P_2 */
8915   {
8916     { "(bad)",          { XX } },
8917     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8918   },
8919
8920   /* VEX_LEN_3A0A_P_2 */
8921   {
8922     { "vroundss",       { XM, Vex128, EXd, Ib } },
8923     { "(bad)",          { XX } },
8924   },
8925
8926   /* VEX_LEN_3A0B_P_2 */
8927   {
8928     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8929     { "(bad)",          { XX } },
8930   },
8931
8932   /* VEX_LEN_3A0E_P_2 */
8933   {
8934     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8935     { "(bad)",          { XX } },
8936   },
8937
8938   /* VEX_LEN_3A0F_P_2 */
8939   {
8940     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8941     { "(bad)",          { XX } },
8942   },
8943
8944   /* VEX_LEN_3A14_P_2 */
8945   {
8946     { "vpextrb",        { Edqb, XM, Ib } },
8947     { "(bad)",          { XX } },
8948   },
8949
8950   /* VEX_LEN_3A15_P_2 */
8951   {
8952     { "vpextrw",        { Edqw, XM, Ib } },
8953     { "(bad)",          { XX } },
8954   },
8955
8956   /* VEX_LEN_3A16_P_2  */
8957   {
8958     { "vpextrK",        { Edq, XM, Ib } },
8959     { "(bad)",          { XX } },
8960   },
8961
8962   /* VEX_LEN_3A17_P_2 */
8963   {
8964     { "vextractps",     { Edqd, XM, Ib } },
8965     { "(bad)",          { XX } },
8966   },
8967
8968   /* VEX_LEN_3A18_P_2 */
8969   {
8970     { "(bad)",          { XX } },
8971     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8972   },
8973
8974   /* VEX_LEN_3A19_P_2 */
8975   {
8976     { "(bad)",          { XX } },
8977     { "vextractf128",   { EXxmm, XM, Ib } },
8978   },
8979
8980   /* VEX_LEN_3A20_P_2 */
8981   {
8982     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8983     { "(bad)",          { XX } },
8984   },
8985
8986   /* VEX_LEN_3A21_P_2 */
8987   {
8988     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8989     { "(bad)",          { XX } },
8990   },
8991
8992   /* VEX_LEN_3A22_P_2 */
8993   {
8994     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8995     { "(bad)",          { XX } },
8996   },
8997
8998   /* VEX_LEN_3A41_P_2 */
8999   {
9000     { "vdppd",          { XM, Vex128, EXx, Ib } },
9001     { "(bad)",          { XX } },
9002   },
9003
9004   /* VEX_LEN_3A42_P_2 */
9005   {
9006     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
9007     { "(bad)",          { XX } },
9008   },
9009
9010   /* VEX_LEN_3A4C_P_2 */
9011   {
9012     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
9013     { "(bad)",          { XX } },
9014   },
9015
9016   /* VEX_LEN_3A60_P_2 */
9017   {
9018     { "vpcmpestrm",     { XM, EXx, Ib } },
9019     { "(bad)",          { XX } },
9020   },
9021
9022   /* VEX_LEN_3A61_P_2 */
9023   {
9024     { "vpcmpestri",     { XM, EXx, Ib } },
9025     { "(bad)",          { XX } },
9026   },
9027
9028   /* VEX_LEN_3A62_P_2 */
9029   {
9030     { "vpcmpistrm",     { XM, EXx, Ib } },
9031     { "(bad)",          { XX } },
9032   },
9033
9034   /* VEX_LEN_3A63_P_2 */
9035   {
9036     { "vpcmpistri",     { XM, EXx, Ib } },
9037     { "(bad)",          { XX } },
9038   },
9039
9040   /* VEX_LEN_3ADF_P_2 */
9041   {
9042     { "vaeskeygenassist", { XM, EXx, Ib } },
9043     { "(bad)",          { XX } },
9044   },
9045 };
9046
9047 static const struct dis386 mod_table[][2] = {
9048   {
9049     /* MOD_8D */
9050     { "leaS",           { Gv, M } },
9051     { "(bad)",          { XX } },
9052   },
9053   {
9054     /* MOD_0F01_REG_0 */
9055     { X86_64_TABLE (X86_64_0F01_REG_0) },
9056     { RM_TABLE (RM_0F01_REG_0) },
9057   },
9058   {
9059     /* MOD_0F01_REG_1 */
9060     { X86_64_TABLE (X86_64_0F01_REG_1) },
9061     { RM_TABLE (RM_0F01_REG_1) },
9062   },
9063   {
9064     /* MOD_0F01_REG_2 */
9065     { X86_64_TABLE (X86_64_0F01_REG_2) },
9066     { RM_TABLE (RM_0F01_REG_2) },
9067   },
9068   {
9069     /* MOD_0F01_REG_3 */
9070     { X86_64_TABLE (X86_64_0F01_REG_3) },
9071     { RM_TABLE (RM_0F01_REG_3) },
9072   },
9073   {
9074     /* MOD_0F01_REG_7 */
9075     { "invlpg",         { Mb } },
9076     { RM_TABLE (RM_0F01_REG_7) },
9077   },
9078   {
9079     /* MOD_0F12_PREFIX_0 */
9080     { "movlps",         { XM, EXq } },
9081     { "movhlps",        { XM, EXq } },
9082   },
9083   {
9084     /* MOD_0F13 */
9085     { "movlpX",         { EXq, XM } },
9086     { "(bad)",          { XX } },
9087   },
9088   {
9089     /* MOD_0F16_PREFIX_0 */
9090     { "movhps",         { XM, EXq } },
9091     { "movlhps",        { XM, EXq } },
9092   },
9093   {
9094     /* MOD_0F17 */
9095     { "movhpX",         { EXq, XM } },
9096     { "(bad)",          { XX } },
9097   },
9098   {
9099     /* MOD_0F18_REG_0 */
9100     { "prefetchnta",    { Mb } },
9101     { "(bad)",          { XX } },
9102   },
9103   {
9104     /* MOD_0F18_REG_1 */
9105     { "prefetcht0",     { Mb } },
9106     { "(bad)",          { XX } },
9107   },
9108   {
9109     /* MOD_0F18_REG_2 */
9110     { "prefetcht1",     { Mb } },
9111     { "(bad)",          { XX } },
9112   },
9113   {
9114     /* MOD_0F18_REG_3 */
9115     { "prefetcht2",     { Mb } },
9116     { "(bad)",          { XX } },
9117   },
9118   {
9119     /* MOD_0F20 */
9120     { "(bad)",          { XX } },
9121     { "movZ",           { Rm, Cm } },
9122   },
9123   {
9124     /* MOD_0F21 */
9125     { "(bad)",          { XX } },
9126     { "movZ",           { Rm, Dm } },
9127   },
9128   {
9129     /* MOD_0F22 */
9130     { "(bad)",          { XX } },
9131     { "movZ",           { Cm, Rm } },
9132   },
9133   {
9134     /* MOD_0F23 */
9135     { "(bad)",          { XX } },
9136     { "movZ",           { Dm, Rm } },
9137   },
9138   {
9139     /* MOD_0F24 */
9140     { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9141     { "movL",           { Rd, Td } },
9142   },
9143   {
9144     /* MOD_0F26 */
9145     { "(bad)",          { XX } },
9146     { "movL",           { Td, Rd } },
9147   },
9148   {
9149     /* MOD_0F2B_PREFIX_0 */
9150     {"movntps",         { Mx, XM } },
9151     { "(bad)",          { XX } },
9152   },
9153   {
9154     /* MOD_0F2B_PREFIX_1 */
9155     {"movntss",         { Md, XM } },
9156     { "(bad)",          { XX } },
9157   },
9158   {
9159     /* MOD_0F2B_PREFIX_2 */
9160     {"movntpd",         { Mx, XM } },
9161     { "(bad)",          { XX } },
9162   },
9163   {
9164     /* MOD_0F2B_PREFIX_3 */
9165     {"movntsd",         { Mq, XM } },
9166     { "(bad)",          { XX } },
9167   },
9168   {
9169     /* MOD_0F51 */
9170     { "(bad)",          { XX } },
9171     { "movmskpX",       { Gdq, XS } },
9172   },
9173   {
9174     /* MOD_0F71_REG_2 */
9175     { "(bad)",          { XX } },
9176     { "psrlw",          { MS, Ib } },
9177   },
9178   {
9179     /* MOD_0F71_REG_4 */
9180     { "(bad)",          { XX } },
9181     { "psraw",          { MS, Ib } },
9182   },
9183   {
9184     /* MOD_0F71_REG_6 */
9185     { "(bad)",          { XX } },
9186     { "psllw",          { MS, Ib } },
9187   },
9188   {
9189     /* MOD_0F72_REG_2 */
9190     { "(bad)",          { XX } },
9191     { "psrld",          { MS, Ib } },
9192   },
9193   {
9194     /* MOD_0F72_REG_4 */
9195     { "(bad)",          { XX } },
9196     { "psrad",          { MS, Ib } },
9197   },
9198   {
9199     /* MOD_0F72_REG_6 */
9200     { "(bad)",          { XX } },
9201     { "pslld",          { MS, Ib } },
9202   },
9203   {
9204     /* MOD_0F73_REG_2 */
9205     { "(bad)",          { XX } },
9206     { "psrlq",          { MS, Ib } },
9207   },
9208   {
9209     /* MOD_0F73_REG_3 */
9210     { "(bad)",          { XX } },
9211     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9212   },
9213   {
9214     /* MOD_0F73_REG_6 */
9215     { "(bad)",          { XX } },
9216     { "psllq",          { MS, Ib } },
9217   },
9218   {
9219     /* MOD_0F73_REG_7 */
9220     { "(bad)",          { XX } },
9221     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9222   },
9223   {
9224     /* MOD_0FAE_REG_0 */
9225     { "fxsave",         { M } },
9226     { "(bad)",          { XX } },
9227   },
9228   {
9229     /* MOD_0FAE_REG_1 */
9230     { "fxrstor",        { M } },
9231     { "(bad)",          { XX } },
9232   },
9233   {
9234     /* MOD_0FAE_REG_2 */
9235     { "ldmxcsr",        { Md } },
9236     { "(bad)",          { XX } },
9237   },
9238   {
9239     /* MOD_0FAE_REG_3 */
9240     { "stmxcsr",        { Md } },
9241     { "(bad)",          { XX } },
9242   },
9243   {
9244     /* MOD_0FAE_REG_4 */
9245     { "xsave",          { M } },
9246     { "(bad)",          { XX } },
9247   },
9248   {
9249     /* MOD_0FAE_REG_5 */
9250     { "xrstor",         { M } },
9251     { RM_TABLE (RM_0FAE_REG_5) },
9252   },
9253   {
9254     /* MOD_0FAE_REG_6 */
9255     { "xsaveopt",       { M } },
9256     { RM_TABLE (RM_0FAE_REG_6) },
9257   },
9258   {
9259     /* MOD_0FAE_REG_7 */
9260     { "clflush",        { Mb } },
9261     { RM_TABLE (RM_0FAE_REG_7) },
9262   },
9263   {
9264     /* MOD_0FB2 */
9265     { "lssS",           { Gv, Mp } },
9266     { "(bad)",          { XX } },
9267   },
9268   {
9269     /* MOD_0FB4 */
9270     { "lfsS",           { Gv, Mp } },
9271     { "(bad)",          { XX } },
9272   },
9273   {
9274     /* MOD_0FB5 */
9275     { "lgsS",           { Gv, Mp } },
9276     { "(bad)",          { XX } },
9277   },
9278   {
9279     /* MOD_0FC7_REG_6 */
9280     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9281     { "(bad)",          { XX } },
9282   },
9283   {
9284     /* MOD_0FC7_REG_7 */
9285     { "vmptrst",        { Mq } },
9286     { "(bad)",          { XX } },
9287   },
9288   {
9289     /* MOD_0FD7 */
9290     { "(bad)",          { XX } },
9291     { "pmovmskb",       { Gdq, MS } },
9292   },
9293   {
9294     /* MOD_0FE7_PREFIX_2 */
9295     { "movntdq",        { Mx, XM } },
9296     { "(bad)",          { XX } },
9297   },
9298   {
9299     /* MOD_0FF0_PREFIX_3 */
9300     { "lddqu",          { XM, M } },
9301     { "(bad)",          { XX } },
9302   },
9303   {
9304     /* MOD_0F382A_PREFIX_2 */
9305     { "movntdqa",       { XM, Mx } },
9306     { "(bad)",          { XX } },
9307   },
9308   {
9309     /* MOD_62_32BIT */
9310     { "bound{S|}",      { Gv, Ma } },
9311     { "(bad)",          { XX } },
9312   },
9313   {
9314     /* MOD_C4_32BIT */
9315     { "lesS",           { Gv, Mp } },
9316     { VEX_C4_TABLE (VEX_0F) },
9317   },
9318   {
9319     /* MOD_C5_32BIT */
9320     { "ldsS",           { Gv, Mp } },
9321     { VEX_C5_TABLE (VEX_0F) },
9322   },
9323   {
9324     /* MOD_VEX_12_PREFIX_0 */
9325     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9326     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9327   },
9328   {
9329     /* MOD_VEX_13 */
9330     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9331     { "(bad)",          { XX } },
9332   },
9333   {
9334     /* MOD_VEX_16_PREFIX_0 */
9335     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9336     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9337   },
9338   {
9339     /* MOD_VEX_17 */
9340     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9341     { "(bad)",          { XX } },
9342   },
9343   {
9344     /* MOD_VEX_2B */
9345     { "vmovntpX",       { Mx, XM } },
9346     { "(bad)",          { XX } },
9347   },
9348   {
9349     /* MOD_VEX_51 */
9350     { "(bad)",          { XX } },
9351     { "vmovmskpX",      { Gdq, XS } },
9352   },
9353   {
9354     /* MOD_VEX_71_REG_2 */
9355     { "(bad)",          { XX } },
9356     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9357   },
9358   {
9359     /* MOD_VEX_71_REG_4 */
9360     { "(bad)",          { XX } },
9361     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9362   },
9363   {
9364     /* MOD_VEX_71_REG_6 */
9365     { "(bad)",          { XX } },
9366     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9367   },
9368   {
9369     /* MOD_VEX_72_REG_2 */
9370     { "(bad)",          { XX } },
9371     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9372   },
9373   {
9374     /* MOD_VEX_72_REG_4 */
9375     { "(bad)",          { XX } },
9376     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9377   },
9378   {
9379     /* MOD_VEX_72_REG_6 */
9380     { "(bad)",          { XX } },
9381     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9382   },
9383   {
9384     /* MOD_VEX_73_REG_2 */
9385     { "(bad)",          { XX } },
9386     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9387   },
9388   {
9389     /* MOD_VEX_73_REG_3 */
9390     { "(bad)",          { XX } },
9391     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9392   },
9393   {
9394     /* MOD_VEX_73_REG_6 */
9395     { "(bad)",          { XX } },
9396     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9397   },
9398   {
9399     /* MOD_VEX_73_REG_7 */
9400     { "(bad)",          { XX } },
9401     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9402   },
9403   {
9404     /* MOD_VEX_AE_REG_2 */
9405     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9406     { "(bad)",          { XX } },
9407   },
9408   {
9409     /* MOD_VEX_AE_REG_3 */
9410     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9411     { "(bad)",          { XX } },
9412   },
9413   {
9414     /* MOD_VEX_D7_PREFIX_2 */
9415     { "(bad)",          { XX } },
9416     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9417   },
9418   {
9419     /* MOD_VEX_E7_PREFIX_2 */
9420     { "vmovntdq",       { Mx, XM } },
9421     { "(bad)",          { XX } },
9422   },
9423   {
9424     /* MOD_VEX_F0_PREFIX_3 */
9425     { "vlddqu",         { XM, M } },
9426     { "(bad)",          { XX } },
9427   },
9428   {
9429     /* MOD_VEX_3818_PREFIX_2 */
9430     { "vbroadcastss",   { XM, Md } },
9431     { "(bad)",          { XX } },
9432   },
9433   {
9434     /* MOD_VEX_3819_PREFIX_2 */
9435     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9436     { "(bad)",          { XX } },
9437   },
9438   {
9439     /* MOD_VEX_381A_PREFIX_2 */
9440     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9441     { "(bad)",          { XX } },
9442   },
9443   {
9444     /* MOD_VEX_382A_PREFIX_2 */
9445     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9446     { "(bad)",          { XX } },
9447   },
9448   {
9449     /* MOD_VEX_382C_PREFIX_2 */
9450     { "vmaskmovps",     { XM, Vex, Mx } },
9451     { "(bad)",          { XX } },
9452   },
9453   {
9454     /* MOD_VEX_382D_PREFIX_2 */
9455     { "vmaskmovpd",     { XM, Vex, Mx } },
9456     { "(bad)",          { XX } },
9457   },
9458   {
9459     /* MOD_VEX_382E_PREFIX_2 */
9460     { "vmaskmovps",     { Mx, Vex, XM } },
9461     { "(bad)",          { XX } },
9462   },
9463   {
9464     /* MOD_VEX_382F_PREFIX_2 */
9465     { "vmaskmovpd",     { Mx, Vex, XM } },
9466     { "(bad)",          { XX } },
9467   },
9468 };
9469
9470 static const struct dis386 rm_table[][8] = {
9471   {
9472     /* RM_0F01_REG_0 */
9473     { "(bad)",          { XX } },
9474     { "vmcall",         { Skip_MODRM } },
9475     { "vmlaunch",       { Skip_MODRM } },
9476     { "vmresume",       { Skip_MODRM } },
9477     { "vmxoff",         { Skip_MODRM } },
9478     { "(bad)",          { XX } },
9479     { "(bad)",          { XX } },
9480     { "(bad)",          { XX } },
9481   },
9482   {
9483     /* RM_0F01_REG_1 */
9484     { "monitor",        { { OP_Monitor, 0 } } },
9485     { "mwait",          { { OP_Mwait, 0 } } },
9486     { "(bad)",          { XX } },
9487     { "(bad)",          { XX } },
9488     { "(bad)",          { XX } },
9489     { "(bad)",          { XX } },
9490     { "(bad)",          { XX } },
9491     { "(bad)",          { XX } },
9492   },
9493   {
9494     /* RM_0F01_REG_2 */
9495     { "xgetbv",         { Skip_MODRM } },
9496     { "xsetbv",         { Skip_MODRM } },
9497     { "(bad)",          { XX } },
9498     { "(bad)",          { XX } },
9499     { "(bad)",          { XX } },
9500     { "(bad)",          { XX } },
9501     { "(bad)",          { XX } },
9502     { "(bad)",          { XX } },
9503   },
9504   {
9505     /* RM_0F01_REG_3 */
9506     { "vmrun",          { Skip_MODRM } },
9507     { "vmmcall",        { Skip_MODRM } },
9508     { "vmload",         { Skip_MODRM } },
9509     { "vmsave",         { Skip_MODRM } },
9510     { "stgi",           { Skip_MODRM } },
9511     { "clgi",           { Skip_MODRM } },
9512     { "skinit",         { Skip_MODRM } },
9513     { "invlpga",        { Skip_MODRM } },
9514   },
9515   {
9516     /* RM_0F01_REG_7 */
9517     { "swapgs",         { Skip_MODRM } },
9518     { "rdtscp",         { Skip_MODRM } },
9519     { "(bad)",          { XX } },
9520     { "(bad)",          { XX } },
9521     { "(bad)",          { XX } },
9522     { "(bad)",          { XX } },
9523     { "(bad)",          { XX } },
9524     { "(bad)",          { XX } },
9525   },
9526   {
9527     /* RM_0FAE_REG_5 */
9528     { "lfence",         { Skip_MODRM } },
9529     { "(bad)",          { XX } },
9530     { "(bad)",          { XX } },
9531     { "(bad)",          { XX } },
9532     { "(bad)",          { XX } },
9533     { "(bad)",          { XX } },
9534     { "(bad)",          { XX } },
9535     { "(bad)",          { XX } },
9536   },
9537   {
9538     /* RM_0FAE_REG_6 */
9539     { "mfence",         { Skip_MODRM } },
9540     { "(bad)",          { XX } },
9541     { "(bad)",          { XX } },
9542     { "(bad)",          { XX } },
9543     { "(bad)",          { XX } },
9544     { "(bad)",          { XX } },
9545     { "(bad)",          { XX } },
9546     { "(bad)",          { XX } },
9547   },
9548   {
9549     /* RM_0FAE_REG_7 */
9550     { "sfence",         { Skip_MODRM } },
9551     { "(bad)",          { XX } },
9552     { "(bad)",          { XX } },
9553     { "(bad)",          { XX } },
9554     { "(bad)",          { XX } },
9555     { "(bad)",          { XX } },
9556     { "(bad)",          { XX } },
9557     { "(bad)",          { XX } },
9558   },
9559 };
9560
9561 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9562
9563 static void
9564 ckprefix (void)
9565 {
9566   int newrex;
9567   rex = 0;
9568   rex_original = 0;
9569   rex_ignored = 0;
9570   prefixes = 0;
9571   used_prefixes = 0;
9572   rex_used = 0;
9573   while (1)
9574     {
9575       FETCH_DATA (the_info, codep + 1);
9576       newrex = 0;
9577       switch (*codep)
9578         {
9579         /* REX prefixes family.  */
9580         case 0x40:
9581         case 0x41:
9582         case 0x42:
9583         case 0x43:
9584         case 0x44:
9585         case 0x45:
9586         case 0x46:
9587         case 0x47:
9588         case 0x48:
9589         case 0x49:
9590         case 0x4a:
9591         case 0x4b:
9592         case 0x4c:
9593         case 0x4d:
9594         case 0x4e:
9595         case 0x4f:
9596             if (address_mode == mode_64bit)
9597               newrex = *codep;
9598             else
9599               return;
9600           break;
9601         case 0xf3:
9602           prefixes |= PREFIX_REPZ;
9603           break;
9604         case 0xf2:
9605           prefixes |= PREFIX_REPNZ;
9606           break;
9607         case 0xf0:
9608           prefixes |= PREFIX_LOCK;
9609           break;
9610         case 0x2e:
9611           prefixes |= PREFIX_CS;
9612           break;
9613         case 0x36:
9614           prefixes |= PREFIX_SS;
9615           break;
9616         case 0x3e:
9617           prefixes |= PREFIX_DS;
9618           break;
9619         case 0x26:
9620           prefixes |= PREFIX_ES;
9621           break;
9622         case 0x64:
9623           prefixes |= PREFIX_FS;
9624           break;
9625         case 0x65:
9626           prefixes |= PREFIX_GS;
9627           break;
9628         case 0x66:
9629           prefixes |= PREFIX_DATA;
9630           break;
9631         case 0x67:
9632           prefixes |= PREFIX_ADDR;
9633           break;
9634         case FWAIT_OPCODE:
9635           /* fwait is really an instruction.  If there are prefixes
9636              before the fwait, they belong to the fwait, *not* to the
9637              following instruction.  */
9638           if (prefixes || rex)
9639             {
9640               prefixes |= PREFIX_FWAIT;
9641               codep++;
9642               return;
9643             }
9644           prefixes = PREFIX_FWAIT;
9645           break;
9646         default:
9647           return;
9648         }
9649       /* Rex is ignored when followed by another prefix.  */
9650       if (rex)
9651         {
9652           rex_used = rex;
9653           return;
9654         }
9655       rex = newrex;
9656       rex_original = rex;
9657       codep++;
9658     }
9659 }
9660
9661 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9662    prefix byte.  */
9663
9664 static const char *
9665 prefix_name (int pref, int sizeflag)
9666 {
9667   static const char *rexes [16] =
9668     {
9669       "rex",            /* 0x40 */
9670       "rex.B",          /* 0x41 */
9671       "rex.X",          /* 0x42 */
9672       "rex.XB",         /* 0x43 */
9673       "rex.R",          /* 0x44 */
9674       "rex.RB",         /* 0x45 */
9675       "rex.RX",         /* 0x46 */
9676       "rex.RXB",        /* 0x47 */
9677       "rex.W",          /* 0x48 */
9678       "rex.WB",         /* 0x49 */
9679       "rex.WX",         /* 0x4a */
9680       "rex.WXB",        /* 0x4b */
9681       "rex.WR",         /* 0x4c */
9682       "rex.WRB",        /* 0x4d */
9683       "rex.WRX",        /* 0x4e */
9684       "rex.WRXB",       /* 0x4f */
9685     };
9686
9687   switch (pref)
9688     {
9689     /* REX prefixes family.  */
9690     case 0x40:
9691     case 0x41:
9692     case 0x42:
9693     case 0x43:
9694     case 0x44:
9695     case 0x45:
9696     case 0x46:
9697     case 0x47:
9698     case 0x48:
9699     case 0x49:
9700     case 0x4a:
9701     case 0x4b:
9702     case 0x4c:
9703     case 0x4d:
9704     case 0x4e:
9705     case 0x4f:
9706       return rexes [pref - 0x40];
9707     case 0xf3:
9708       return "repz";
9709     case 0xf2:
9710       return "repnz";
9711     case 0xf0:
9712       return "lock";
9713     case 0x2e:
9714       return "cs";
9715     case 0x36:
9716       return "ss";
9717     case 0x3e:
9718       return "ds";
9719     case 0x26:
9720       return "es";
9721     case 0x64:
9722       return "fs";
9723     case 0x65:
9724       return "gs";
9725     case 0x66:
9726       return (sizeflag & DFLAG) ? "data16" : "data32";
9727     case 0x67:
9728       if (address_mode == mode_64bit)
9729         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9730       else
9731         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9732     case FWAIT_OPCODE:
9733       return "fwait";
9734     default:
9735       return NULL;
9736     }
9737 }
9738
9739 static char op_out[MAX_OPERANDS][100];
9740 static int op_ad, op_index[MAX_OPERANDS];
9741 static int two_source_ops;
9742 static bfd_vma op_address[MAX_OPERANDS];
9743 static bfd_vma op_riprel[MAX_OPERANDS];
9744 static bfd_vma start_pc;
9745
9746 /*
9747  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9748  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9749  *   section of the "Virtual 8086 Mode" chapter.)
9750  * 'pc' should be the address of this instruction, it will
9751  *   be used to print the target address if this is a relative jump or call
9752  * The function returns the length of this instruction in bytes.
9753  */
9754
9755 static char intel_syntax;
9756 static char intel_mnemonic = !SYSV386_COMPAT;
9757 static char open_char;
9758 static char close_char;
9759 static char separator_char;
9760 static char scale_char;
9761
9762 /* Here for backwards compatibility.  When gdb stops using
9763    print_insn_i386_att and print_insn_i386_intel these functions can
9764    disappear, and print_insn_i386 be merged into print_insn.  */
9765 int
9766 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9767 {
9768   intel_syntax = 0;
9769
9770   return print_insn (pc, info);
9771 }
9772
9773 int
9774 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9775 {
9776   intel_syntax = 1;
9777
9778   return print_insn (pc, info);
9779 }
9780
9781 int
9782 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9783 {
9784   intel_syntax = -1;
9785
9786   return print_insn (pc, info);
9787 }
9788
9789 void
9790 print_i386_disassembler_options (FILE *stream)
9791 {
9792   fprintf (stream, _("\n\
9793 The following i386/x86-64 specific disassembler options are supported for use\n\
9794 with the -M switch (multiple options should be separated by commas):\n"));
9795
9796   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9797   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9798   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9799   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9800   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9801   fprintf (stream, _("  att-mnemonic\n"
9802                      "              Display instruction in AT&T mnemonic\n"));
9803   fprintf (stream, _("  intel-mnemonic\n"
9804                      "              Display instruction in Intel mnemonic\n"));
9805   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9806   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9807   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9808   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9809   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9810   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9811 }
9812
9813 /* Get a pointer to struct dis386 with a valid name.  */
9814
9815 static const struct dis386 *
9816 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9817 {
9818   int index, vex_table_index;
9819
9820   if (dp->name != NULL)
9821     return dp;
9822
9823   switch (dp->op[0].bytemode)
9824     {
9825     case USE_REG_TABLE:
9826       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9827       break;
9828
9829     case USE_MOD_TABLE:
9830       index = modrm.mod == 0x3 ? 1 : 0;
9831       dp = &mod_table[dp->op[1].bytemode][index];
9832       break;
9833
9834     case USE_RM_TABLE:
9835       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9836       break;
9837
9838     case USE_PREFIX_TABLE:
9839       if (need_vex)
9840         {
9841           /* The prefix in VEX is implicit.  */
9842           switch (vex.prefix)
9843             {
9844             case 0:
9845               index = 0;
9846               break;
9847             case REPE_PREFIX_OPCODE:
9848               index = 1;
9849               break;
9850             case DATA_PREFIX_OPCODE:
9851               index = 2;
9852               break;
9853             case REPNE_PREFIX_OPCODE:
9854               index = 3;
9855               break;
9856             default:
9857               abort ();
9858               break;
9859             }
9860         }
9861       else
9862         {
9863           index = 0;
9864           used_prefixes |= (prefixes & PREFIX_REPZ);
9865           if (prefixes & PREFIX_REPZ)
9866             {
9867               index = 1;
9868               repz_prefix = NULL;
9869             }
9870           else
9871             {
9872               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9873                  PREFIX_DATA.  */
9874               used_prefixes |= (prefixes & PREFIX_REPNZ);
9875               if (prefixes & PREFIX_REPNZ)
9876                 {
9877                   index = 3;
9878                   repnz_prefix = NULL;
9879                 }
9880               else
9881                 {
9882                   used_prefixes |= (prefixes & PREFIX_DATA);
9883                   if (prefixes & PREFIX_DATA)
9884                     {
9885                       index = 2;
9886                       data_prefix = NULL;
9887                     }
9888                 }
9889             }
9890         }
9891       dp = &prefix_table[dp->op[1].bytemode][index];
9892       break;
9893
9894     case USE_X86_64_TABLE:
9895       index = address_mode == mode_64bit ? 1 : 0;
9896       dp = &x86_64_table[dp->op[1].bytemode][index];
9897       break;
9898
9899     case USE_3BYTE_TABLE:
9900       FETCH_DATA (info, codep + 2);
9901       index = *codep++;
9902       dp = &three_byte_table[dp->op[1].bytemode][index];
9903       modrm.mod = (*codep >> 6) & 3;
9904       modrm.reg = (*codep >> 3) & 7;
9905       modrm.rm = *codep & 7;
9906       break;
9907
9908     case USE_VEX_LEN_TABLE:
9909       if (!need_vex)
9910         abort ();
9911
9912       switch (vex.length)
9913         {
9914         case 128:
9915           index = 0;
9916           break;
9917         case 256:
9918           index = 1;
9919           break;
9920         default:
9921           abort ();
9922           break;
9923         }
9924
9925       dp = &vex_len_table[dp->op[1].bytemode][index];
9926       break;
9927
9928     case USE_VEX_C4_TABLE:
9929       FETCH_DATA (info, codep + 3);
9930       /* All bits in the REX prefix are ignored.  */
9931       rex_ignored = rex;
9932       rex = ~(*codep >> 5) & 0x7;
9933       switch ((*codep & 0x1f))
9934         {
9935         default:
9936           BadOp ();
9937         case 0x1:
9938           vex_table_index = 0;
9939           break;
9940         case 0x2:
9941           vex_table_index = 1;
9942           break;
9943         case 0x3:
9944           vex_table_index = 2;
9945           break;
9946         }
9947       codep++;
9948       vex.w = *codep & 0x80;
9949       if (vex.w && address_mode == mode_64bit)
9950         rex |= REX_W;
9951
9952       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9953       if (address_mode != mode_64bit
9954           && vex.register_specifier > 0x7)
9955         BadOp ();
9956
9957       vex.length = (*codep & 0x4) ? 256 : 128;
9958       switch ((*codep & 0x3))
9959         {
9960         case 0:
9961           vex.prefix = 0;
9962           break;
9963         case 1:
9964           vex.prefix = DATA_PREFIX_OPCODE;
9965           break;
9966         case 2:
9967           vex.prefix = REPE_PREFIX_OPCODE;
9968           break;
9969         case 3:
9970           vex.prefix = REPNE_PREFIX_OPCODE;
9971           break;
9972         }
9973       need_vex = 1;
9974       need_vex_reg = 1;
9975       codep++;
9976       index = *codep++;
9977       dp = &vex_table[vex_table_index][index];
9978       /* There is no MODRM byte for VEX [82|77].  */
9979       if (index != 0x77 && index != 0x82)
9980         {
9981           FETCH_DATA (info, codep + 1);
9982           modrm.mod = (*codep >> 6) & 3;
9983           modrm.reg = (*codep >> 3) & 7;
9984           modrm.rm = *codep & 7;
9985         }
9986       break;
9987
9988     case USE_VEX_C5_TABLE:
9989       FETCH_DATA (info, codep + 2);
9990       /* All bits in the REX prefix are ignored.  */
9991       rex_ignored = rex;
9992       rex = (*codep & 0x80) ? 0 : REX_R;
9993
9994       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9995       if (address_mode != mode_64bit
9996           && vex.register_specifier > 0x7)
9997         BadOp ();
9998
9999       vex.length = (*codep & 0x4) ? 256 : 128;
10000       switch ((*codep & 0x3))
10001         {
10002         case 0:
10003           vex.prefix = 0;
10004           break;
10005         case 1:
10006           vex.prefix = DATA_PREFIX_OPCODE;
10007           break;
10008         case 2:
10009           vex.prefix = REPE_PREFIX_OPCODE;
10010           break;
10011         case 3:
10012           vex.prefix = REPNE_PREFIX_OPCODE;
10013           break;
10014         }
10015       need_vex = 1;
10016       need_vex_reg = 1;
10017       codep++;
10018       index = *codep++;
10019       dp = &vex_table[dp->op[1].bytemode][index];
10020       /* There is no MODRM byte for VEX [82|77].  */
10021       if (index != 0x77 && index != 0x82)
10022         {
10023           FETCH_DATA (info, codep + 1);
10024           modrm.mod = (*codep >> 6) & 3;
10025           modrm.reg = (*codep >> 3) & 7;
10026           modrm.rm = *codep & 7;
10027         }
10028       break;
10029
10030     default:
10031       oappend (INTERNAL_DISASSEMBLER_ERROR);
10032       return NULL;
10033     }
10034
10035   if (dp->name != NULL)
10036     return dp;
10037   else
10038     return get_valid_dis386 (dp, info);
10039 }
10040
10041 static int
10042 print_insn (bfd_vma pc, disassemble_info *info)
10043 {
10044   const struct dis386 *dp;
10045   int i;
10046   char *op_txt[MAX_OPERANDS];
10047   int needcomma;
10048   int sizeflag;
10049   const char *p;
10050   struct dis_private priv;
10051   unsigned char op;
10052   char prefix_obuf[32];
10053   char *prefix_obufp;
10054
10055   if (info->mach == bfd_mach_x86_64_intel_syntax
10056       || info->mach == bfd_mach_x86_64)
10057     address_mode = mode_64bit;
10058   else
10059     address_mode = mode_32bit;
10060
10061   if (intel_syntax == (char) -1)
10062     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10063                     || info->mach == bfd_mach_x86_64_intel_syntax);
10064
10065   if (info->mach == bfd_mach_i386_i386
10066       || info->mach == bfd_mach_x86_64
10067       || info->mach == bfd_mach_i386_i386_intel_syntax
10068       || info->mach == bfd_mach_x86_64_intel_syntax)
10069     priv.orig_sizeflag = AFLAG | DFLAG;
10070   else if (info->mach == bfd_mach_i386_i8086)
10071     priv.orig_sizeflag = 0;
10072   else
10073     abort ();
10074
10075   for (p = info->disassembler_options; p != NULL; )
10076     {
10077       if (CONST_STRNEQ (p, "x86-64"))
10078         {
10079           address_mode = mode_64bit;
10080           priv.orig_sizeflag = AFLAG | DFLAG;
10081         }
10082       else if (CONST_STRNEQ (p, "i386"))
10083         {
10084           address_mode = mode_32bit;
10085           priv.orig_sizeflag = AFLAG | DFLAG;
10086         }
10087       else if (CONST_STRNEQ (p, "i8086"))
10088         {
10089           address_mode = mode_16bit;
10090           priv.orig_sizeflag = 0;
10091         }
10092       else if (CONST_STRNEQ (p, "intel"))
10093         {
10094           intel_syntax = 1;
10095           if (CONST_STRNEQ (p + 5, "-mnemonic"))
10096             intel_mnemonic = 1;
10097         }
10098       else if (CONST_STRNEQ (p, "att"))
10099         {
10100           intel_syntax = 0;
10101           if (CONST_STRNEQ (p + 3, "-mnemonic"))
10102             intel_mnemonic = 0;
10103         }
10104       else if (CONST_STRNEQ (p, "addr"))
10105         {
10106           if (address_mode == mode_64bit)
10107             {
10108               if (p[4] == '3' && p[5] == '2')
10109                 priv.orig_sizeflag &= ~AFLAG;
10110               else if (p[4] == '6' && p[5] == '4')
10111                 priv.orig_sizeflag |= AFLAG;
10112             }
10113           else
10114             {
10115               if (p[4] == '1' && p[5] == '6')
10116                 priv.orig_sizeflag &= ~AFLAG;
10117               else if (p[4] == '3' && p[5] == '2')
10118                 priv.orig_sizeflag |= AFLAG;
10119             }
10120         }
10121       else if (CONST_STRNEQ (p, "data"))
10122         {
10123           if (p[4] == '1' && p[5] == '6')
10124             priv.orig_sizeflag &= ~DFLAG;
10125           else if (p[4] == '3' && p[5] == '2')
10126             priv.orig_sizeflag |= DFLAG;
10127         }
10128       else if (CONST_STRNEQ (p, "suffix"))
10129         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10130
10131       p = strchr (p, ',');
10132       if (p != NULL)
10133         p++;
10134     }
10135
10136   if (intel_syntax)
10137     {
10138       names64 = intel_names64;
10139       names32 = intel_names32;
10140       names16 = intel_names16;
10141       names8 = intel_names8;
10142       names8rex = intel_names8rex;
10143       names_seg = intel_names_seg;
10144       index64 = intel_index64;
10145       index32 = intel_index32;
10146       index16 = intel_index16;
10147       open_char = '[';
10148       close_char = ']';
10149       separator_char = '+';
10150       scale_char = '*';
10151     }
10152   else
10153     {
10154       names64 = att_names64;
10155       names32 = att_names32;
10156       names16 = att_names16;
10157       names8 = att_names8;
10158       names8rex = att_names8rex;
10159       names_seg = att_names_seg;
10160       index64 = att_index64;
10161       index32 = att_index32;
10162       index16 = att_index16;
10163       open_char = '(';
10164       close_char =  ')';
10165       separator_char = ',';
10166       scale_char = ',';
10167     }
10168
10169   /* The output looks better if we put 7 bytes on a line, since that
10170      puts most long word instructions on a single line.  */
10171   info->bytes_per_line = 7;
10172
10173   info->private_data = &priv;
10174   priv.max_fetched = priv.the_buffer;
10175   priv.insn_start = pc;
10176
10177   obuf[0] = 0;
10178   for (i = 0; i < MAX_OPERANDS; ++i)
10179     {
10180       op_out[i][0] = 0;
10181       op_index[i] = -1;
10182     }
10183
10184   the_info = info;
10185   start_pc = pc;
10186   start_codep = priv.the_buffer;
10187   codep = priv.the_buffer;
10188
10189   if (setjmp (priv.bailout) != 0)
10190     {
10191       const char *name;
10192
10193       /* Getting here means we tried for data but didn't get it.  That
10194          means we have an incomplete instruction of some sort.  Just
10195          print the first byte as a prefix or a .byte pseudo-op.  */
10196       if (codep > priv.the_buffer)
10197         {
10198           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10199           if (name != NULL)
10200             (*info->fprintf_func) (info->stream, "%s", name);
10201           else
10202             {
10203               /* Just print the first byte as a .byte instruction.  */
10204               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10205                                      (unsigned int) priv.the_buffer[0]);
10206             }
10207
10208           return 1;
10209         }
10210
10211       return -1;
10212     }
10213
10214   obufp = obuf;
10215   ckprefix ();
10216
10217   insn_codep = codep;
10218   sizeflag = priv.orig_sizeflag;
10219
10220   FETCH_DATA (info, codep + 1);
10221   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10222
10223   if (((prefixes & PREFIX_FWAIT)
10224        && ((*codep < 0xd8) || (*codep > 0xdf)))
10225       || (rex && rex_used))
10226     {
10227       const char *name;
10228
10229       /* fwait not followed by floating point instruction, or rex followed
10230          by other prefixes.  Print the first prefix.  */
10231       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10232       if (name == NULL)
10233         name = INTERNAL_DISASSEMBLER_ERROR;
10234       (*info->fprintf_func) (info->stream, "%s", name);
10235       return 1;
10236     }
10237
10238   op = 0;
10239   if (*codep == 0x0f)
10240     {
10241       unsigned char threebyte;
10242       FETCH_DATA (info, codep + 2);
10243       threebyte = *++codep;
10244       dp = &dis386_twobyte[threebyte];
10245       need_modrm = twobyte_has_modrm[*codep];
10246       codep++;
10247     }
10248   else
10249     {
10250       dp = &dis386[*codep];
10251       need_modrm = onebyte_has_modrm[*codep];
10252       codep++;
10253     }
10254
10255   if ((prefixes & PREFIX_REPZ))
10256     {
10257       repz_prefix = "repz ";
10258       used_prefixes |= PREFIX_REPZ;
10259     }
10260   else
10261     repz_prefix = NULL;
10262
10263   if ((prefixes & PREFIX_REPNZ))
10264     {
10265       repnz_prefix = "repnz ";
10266       used_prefixes |= PREFIX_REPNZ;
10267     }
10268   else
10269     repnz_prefix = NULL;
10270
10271   if ((prefixes & PREFIX_LOCK))
10272     {
10273       lock_prefix = "lock ";
10274       used_prefixes |= PREFIX_LOCK;
10275     }
10276   else
10277     lock_prefix = NULL;
10278
10279   addr_prefix = NULL;
10280   if (prefixes & PREFIX_ADDR)
10281     {
10282       sizeflag ^= AFLAG;
10283       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10284         {
10285           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10286             addr_prefix = "addr32 ";
10287           else
10288             addr_prefix = "addr16 ";
10289           used_prefixes |= PREFIX_ADDR;
10290         }
10291     }
10292
10293   data_prefix = NULL;
10294   if ((prefixes & PREFIX_DATA))
10295     {
10296       sizeflag ^= DFLAG;
10297       if (dp->op[2].bytemode == cond_jump_mode
10298           && dp->op[0].bytemode == v_mode
10299           && !intel_syntax)
10300         {
10301           if (sizeflag & DFLAG)
10302             data_prefix = "data32 ";
10303           else
10304             data_prefix = "data16 ";
10305           used_prefixes |= PREFIX_DATA;
10306         }
10307     }
10308
10309   if (need_modrm)
10310     {
10311       FETCH_DATA (info, codep + 1);
10312       modrm.mod = (*codep >> 6) & 3;
10313       modrm.reg = (*codep >> 3) & 7;
10314       modrm.rm = *codep & 7;
10315     }
10316
10317   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10318     {
10319       dofloat (sizeflag);
10320     }
10321   else
10322     {
10323       need_vex = 0;
10324       need_vex_reg = 0;
10325       vex_w_done = 0;
10326       dp = get_valid_dis386 (dp, info);
10327       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10328         {
10329           for (i = 0; i < MAX_OPERANDS; ++i)
10330             {
10331               obufp = op_out[i];
10332               op_ad = MAX_OPERANDS - 1 - i;
10333               if (dp->op[i].rtn)
10334                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10335             }
10336         }
10337     }
10338
10339   /* See if any prefixes were not used.  If so, print the first one
10340      separately.  If we don't do this, we'll wind up printing an
10341      instruction stream which does not precisely correspond to the
10342      bytes we are disassembling.  */
10343   if ((prefixes & ~used_prefixes) != 0)
10344     {
10345       const char *name;
10346
10347       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10348       if (name == NULL)
10349         name = INTERNAL_DISASSEMBLER_ERROR;
10350       (*info->fprintf_func) (info->stream, "%s", name);
10351       return 1;
10352     }
10353   if ((rex_original & ~rex_used) || rex_ignored)
10354     {
10355       const char *name;
10356       name = prefix_name (rex_original, priv.orig_sizeflag);
10357       if (name == NULL)
10358         name = INTERNAL_DISASSEMBLER_ERROR;
10359       (*info->fprintf_func) (info->stream, "%s ", name);
10360     }
10361
10362   prefix_obuf[0] = 0;
10363   prefix_obufp = prefix_obuf;
10364   if (lock_prefix)
10365     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10366   if (repz_prefix)
10367     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10368   if (repnz_prefix)
10369     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10370   if (addr_prefix)
10371     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10372   if (data_prefix)
10373     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10374
10375   if (prefix_obuf[0] != 0)
10376     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10377
10378   obufp = mnemonicendp;
10379   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10380     oappend (" ");
10381   oappend (" ");
10382   (*info->fprintf_func) (info->stream, "%s", obuf);
10383
10384   /* The enter and bound instructions are printed with operands in the same
10385      order as the intel book; everything else is printed in reverse order.  */
10386   if (intel_syntax || two_source_ops)
10387     {
10388       bfd_vma riprel;
10389
10390       for (i = 0; i < MAX_OPERANDS; ++i)
10391         op_txt[i] = op_out[i];
10392
10393       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10394         {
10395           op_ad = op_index[i];
10396           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10397           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10398           riprel = op_riprel[i];
10399           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10400           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10401         }
10402     }
10403   else
10404     {
10405       for (i = 0; i < MAX_OPERANDS; ++i)
10406         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10407     }
10408
10409   needcomma = 0;
10410   for (i = 0; i < MAX_OPERANDS; ++i)
10411     if (*op_txt[i])
10412       {
10413         if (needcomma)
10414           (*info->fprintf_func) (info->stream, ",");
10415         if (op_index[i] != -1 && !op_riprel[i])
10416           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10417         else
10418           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10419         needcomma = 1;
10420       }
10421
10422   for (i = 0; i < MAX_OPERANDS; i++)
10423     if (op_index[i] != -1 && op_riprel[i])
10424       {
10425         (*info->fprintf_func) (info->stream, "        # ");
10426         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10427                                                 + op_address[op_index[i]]), info);
10428         break;
10429       }
10430   return codep - priv.the_buffer;
10431 }
10432
10433 static const char *float_mem[] = {
10434   /* d8 */
10435   "fadd{s|}",
10436   "fmul{s|}",
10437   "fcom{s|}",
10438   "fcomp{s|}",
10439   "fsub{s|}",
10440   "fsubr{s|}",
10441   "fdiv{s|}",
10442   "fdivr{s|}",
10443   /* d9 */
10444   "fld{s|}",
10445   "(bad)",
10446   "fst{s|}",
10447   "fstp{s|}",
10448   "fldenvIC",
10449   "fldcw",
10450   "fNstenvIC",
10451   "fNstcw",
10452   /* da */
10453   "fiadd{l|}",
10454   "fimul{l|}",
10455   "ficom{l|}",
10456   "ficomp{l|}",
10457   "fisub{l|}",
10458   "fisubr{l|}",
10459   "fidiv{l|}",
10460   "fidivr{l|}",
10461   /* db */
10462   "fild{l|}",
10463   "fisttp{l|}",
10464   "fist{l|}",
10465   "fistp{l|}",
10466   "(bad)",
10467   "fld{t||t|}",
10468   "(bad)",
10469   "fstp{t||t|}",
10470   /* dc */
10471   "fadd{l|}",
10472   "fmul{l|}",
10473   "fcom{l|}",
10474   "fcomp{l|}",
10475   "fsub{l|}",
10476   "fsubr{l|}",
10477   "fdiv{l|}",
10478   "fdivr{l|}",
10479   /* dd */
10480   "fld{l|}",
10481   "fisttp{ll|}",
10482   "fst{l||}",
10483   "fstp{l|}",
10484   "frstorIC",
10485   "(bad)",
10486   "fNsaveIC",
10487   "fNstsw",
10488   /* de */
10489   "fiadd",
10490   "fimul",
10491   "ficom",
10492   "ficomp",
10493   "fisub",
10494   "fisubr",
10495   "fidiv",
10496   "fidivr",
10497   /* df */
10498   "fild",
10499   "fisttp",
10500   "fist",
10501   "fistp",
10502   "fbld",
10503   "fild{ll|}",
10504   "fbstp",
10505   "fistp{ll|}",
10506 };
10507
10508 static const unsigned char float_mem_mode[] = {
10509   /* d8 */
10510   d_mode,
10511   d_mode,
10512   d_mode,
10513   d_mode,
10514   d_mode,
10515   d_mode,
10516   d_mode,
10517   d_mode,
10518   /* d9 */
10519   d_mode,
10520   0,
10521   d_mode,
10522   d_mode,
10523   0,
10524   w_mode,
10525   0,
10526   w_mode,
10527   /* da */
10528   d_mode,
10529   d_mode,
10530   d_mode,
10531   d_mode,
10532   d_mode,
10533   d_mode,
10534   d_mode,
10535   d_mode,
10536   /* db */
10537   d_mode,
10538   d_mode,
10539   d_mode,
10540   d_mode,
10541   0,
10542   t_mode,
10543   0,
10544   t_mode,
10545   /* dc */
10546   q_mode,
10547   q_mode,
10548   q_mode,
10549   q_mode,
10550   q_mode,
10551   q_mode,
10552   q_mode,
10553   q_mode,
10554   /* dd */
10555   q_mode,
10556   q_mode,
10557   q_mode,
10558   q_mode,
10559   0,
10560   0,
10561   0,
10562   w_mode,
10563   /* de */
10564   w_mode,
10565   w_mode,
10566   w_mode,
10567   w_mode,
10568   w_mode,
10569   w_mode,
10570   w_mode,
10571   w_mode,
10572   /* df */
10573   w_mode,
10574   w_mode,
10575   w_mode,
10576   w_mode,
10577   t_mode,
10578   q_mode,
10579   t_mode,
10580   q_mode
10581 };
10582
10583 #define ST { OP_ST, 0 }
10584 #define STi { OP_STi, 0 }
10585
10586 #define FGRPd9_2 NULL, { { NULL, 0 } }
10587 #define FGRPd9_4 NULL, { { NULL, 1 } }
10588 #define FGRPd9_5 NULL, { { NULL, 2 } }
10589 #define FGRPd9_6 NULL, { { NULL, 3 } }
10590 #define FGRPd9_7 NULL, { { NULL, 4 } }
10591 #define FGRPda_5 NULL, { { NULL, 5 } }
10592 #define FGRPdb_4 NULL, { { NULL, 6 } }
10593 #define FGRPde_3 NULL, { { NULL, 7 } }
10594 #define FGRPdf_4 NULL, { { NULL, 8 } }
10595
10596 static const struct dis386 float_reg[][8] = {
10597   /* d8 */
10598   {
10599     { "fadd",   { ST, STi } },
10600     { "fmul",   { ST, STi } },
10601     { "fcom",   { STi } },
10602     { "fcomp",  { STi } },
10603     { "fsub",   { ST, STi } },
10604     { "fsubr",  { ST, STi } },
10605     { "fdiv",   { ST, STi } },
10606     { "fdivr",  { ST, STi } },
10607   },
10608   /* d9 */
10609   {
10610     { "fld",    { STi } },
10611     { "fxch",   { STi } },
10612     { FGRPd9_2 },
10613     { "(bad)",  { XX } },
10614     { FGRPd9_4 },
10615     { FGRPd9_5 },
10616     { FGRPd9_6 },
10617     { FGRPd9_7 },
10618   },
10619   /* da */
10620   {
10621     { "fcmovb", { ST, STi } },
10622     { "fcmove", { ST, STi } },
10623     { "fcmovbe",{ ST, STi } },
10624     { "fcmovu", { ST, STi } },
10625     { "(bad)",  { XX } },
10626     { FGRPda_5 },
10627     { "(bad)",  { XX } },
10628     { "(bad)",  { XX } },
10629   },
10630   /* db */
10631   {
10632     { "fcmovnb",{ ST, STi } },
10633     { "fcmovne",{ ST, STi } },
10634     { "fcmovnbe",{ ST, STi } },
10635     { "fcmovnu",{ ST, STi } },
10636     { FGRPdb_4 },
10637     { "fucomi", { ST, STi } },
10638     { "fcomi",  { ST, STi } },
10639     { "(bad)",  { XX } },
10640   },
10641   /* dc */
10642   {
10643     { "fadd",   { STi, ST } },
10644     { "fmul",   { STi, ST } },
10645     { "(bad)",  { XX } },
10646     { "(bad)",  { XX } },
10647     { "fsub!M", { STi, ST } },
10648     { "fsubM",  { STi, ST } },
10649     { "fdiv!M", { STi, ST } },
10650     { "fdivM",  { STi, ST } },
10651   },
10652   /* dd */
10653   {
10654     { "ffree",  { STi } },
10655     { "(bad)",  { XX } },
10656     { "fst",    { STi } },
10657     { "fstp",   { STi } },
10658     { "fucom",  { STi } },
10659     { "fucomp", { STi } },
10660     { "(bad)",  { XX } },
10661     { "(bad)",  { XX } },
10662   },
10663   /* de */
10664   {
10665     { "faddp",  { STi, ST } },
10666     { "fmulp",  { STi, ST } },
10667     { "(bad)",  { XX } },
10668     { FGRPde_3 },
10669     { "fsub!Mp", { STi, ST } },
10670     { "fsubMp", { STi, ST } },
10671     { "fdiv!Mp", { STi, ST } },
10672     { "fdivMp", { STi, ST } },
10673   },
10674   /* df */
10675   {
10676     { "ffreep", { STi } },
10677     { "(bad)",  { XX } },
10678     { "(bad)",  { XX } },
10679     { "(bad)",  { XX } },
10680     { FGRPdf_4 },
10681     { "fucomip", { ST, STi } },
10682     { "fcomip", { ST, STi } },
10683     { "(bad)",  { XX } },
10684   },
10685 };
10686
10687 static char *fgrps[][8] = {
10688   /* d9_2  0 */
10689   {
10690     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10691   },
10692
10693   /* d9_4  1 */
10694   {
10695     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10696   },
10697
10698   /* d9_5  2 */
10699   {
10700     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10701   },
10702
10703   /* d9_6  3 */
10704   {
10705     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10706   },
10707
10708   /* d9_7  4 */
10709   {
10710     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10711   },
10712
10713   /* da_5  5 */
10714   {
10715     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10716   },
10717
10718   /* db_4  6 */
10719   {
10720     "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10721     "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10722   },
10723
10724   /* de_3  7 */
10725   {
10726     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10727   },
10728
10729   /* df_4  8 */
10730   {
10731     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10732   },
10733 };
10734
10735 static void
10736 swap_operand (void)
10737 {
10738   mnemonicendp[0] = '.';
10739   mnemonicendp[1] = 's';
10740   mnemonicendp += 2;
10741 }
10742
10743 static void
10744 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10745                int sizeflag ATTRIBUTE_UNUSED)
10746 {
10747   /* Skip mod/rm byte.  */
10748   MODRM_CHECK;
10749   codep++;
10750 }
10751
10752 static void
10753 dofloat (int sizeflag)
10754 {
10755   const struct dis386 *dp;
10756   unsigned char floatop;
10757
10758   floatop = codep[-1];
10759
10760   if (modrm.mod != 3)
10761     {
10762       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10763
10764       putop (float_mem[fp_indx], sizeflag);
10765       obufp = op_out[0];
10766       op_ad = 2;
10767       OP_E (float_mem_mode[fp_indx], sizeflag);
10768       return;
10769     }
10770   /* Skip mod/rm byte.  */
10771   MODRM_CHECK;
10772   codep++;
10773
10774   dp = &float_reg[floatop - 0xd8][modrm.reg];
10775   if (dp->name == NULL)
10776     {
10777       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10778
10779       /* Instruction fnstsw is only one with strange arg.  */
10780       if (floatop == 0xdf && codep[-1] == 0xe0)
10781         strcpy (op_out[0], names16[0]);
10782     }
10783   else
10784     {
10785       putop (dp->name, sizeflag);
10786
10787       obufp = op_out[0];
10788       op_ad = 2;
10789       if (dp->op[0].rtn)
10790         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10791
10792       obufp = op_out[1];
10793       op_ad = 1;
10794       if (dp->op[1].rtn)
10795         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10796     }
10797 }
10798
10799 static void
10800 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10801 {
10802   oappend ("%st" + intel_syntax);
10803 }
10804
10805 static void
10806 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10807 {
10808   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10809   oappend (scratchbuf + intel_syntax);
10810 }
10811
10812 /* Capital letters in template are macros.  */
10813 static int
10814 putop (const char *template, int sizeflag)
10815 {
10816   const char *p;
10817   int alt = 0;
10818   int cond = 1;
10819   unsigned int l = 0, len = 1;
10820   char last[4];
10821
10822 #define SAVE_LAST(c)                    \
10823   if (l < len && l < sizeof (last))     \
10824     last[l++] = c;                      \
10825   else                                  \
10826     abort ();
10827
10828   for (p = template; *p; p++)
10829     {
10830       switch (*p)
10831         {
10832         default:
10833           *obufp++ = *p;
10834           break;
10835         case '%':
10836           len++;
10837           break;
10838         case '!':
10839           cond = 0;
10840           break;
10841         case '{':
10842           alt = 0;
10843           if (intel_syntax)
10844             {
10845               while (*++p != '|')
10846                 if (*p == '}' || *p == '\0')
10847                   abort ();
10848             }
10849           /* Fall through.  */
10850         case 'I':
10851           alt = 1;
10852           continue;
10853         case '|':
10854           while (*++p != '}')
10855             {
10856               if (*p == '\0')
10857                 abort ();
10858             }
10859           break;
10860         case '}':
10861           break;
10862         case 'A':
10863           if (intel_syntax)
10864             break;
10865           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10866             *obufp++ = 'b';
10867           break;
10868         case 'B':
10869           if (intel_syntax)
10870             break;
10871           if (sizeflag & SUFFIX_ALWAYS)
10872             *obufp++ = 'b';
10873           break;
10874         case 'C':
10875           if (intel_syntax && !alt)
10876             break;
10877           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10878             {
10879               if (sizeflag & DFLAG)
10880                 *obufp++ = intel_syntax ? 'd' : 'l';
10881               else
10882                 *obufp++ = intel_syntax ? 'w' : 's';
10883               used_prefixes |= (prefixes & PREFIX_DATA);
10884             }
10885           break;
10886         case 'D':
10887           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10888             break;
10889           USED_REX (REX_W);
10890           if (modrm.mod == 3)
10891             {
10892               if (rex & REX_W)
10893                 *obufp++ = 'q';
10894               else if (sizeflag & DFLAG)
10895                 *obufp++ = intel_syntax ? 'd' : 'l';
10896               else
10897                 *obufp++ = 'w';
10898               used_prefixes |= (prefixes & PREFIX_DATA);
10899             }
10900           else
10901             *obufp++ = 'w';
10902           break;
10903         case 'E':               /* For jcxz/jecxz */
10904           if (address_mode == mode_64bit)
10905             {
10906               if (sizeflag & AFLAG)
10907                 *obufp++ = 'r';
10908               else
10909                 *obufp++ = 'e';
10910             }
10911           else
10912             if (sizeflag & AFLAG)
10913               *obufp++ = 'e';
10914           used_prefixes |= (prefixes & PREFIX_ADDR);
10915           break;
10916         case 'F':
10917           if (intel_syntax)
10918             break;
10919           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10920             {
10921               if (sizeflag & AFLAG)
10922                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10923               else
10924                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10925               used_prefixes |= (prefixes & PREFIX_ADDR);
10926             }
10927           break;
10928         case 'G':
10929           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10930             break;
10931           if ((rex & REX_W) || (sizeflag & DFLAG))
10932             *obufp++ = 'l';
10933           else
10934             *obufp++ = 'w';
10935           if (!(rex & REX_W))
10936             used_prefixes |= (prefixes & PREFIX_DATA);
10937           break;
10938         case 'H':
10939           if (intel_syntax)
10940             break;
10941           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10942               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10943             {
10944               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10945               *obufp++ = ',';
10946               *obufp++ = 'p';
10947               if (prefixes & PREFIX_DS)
10948                 *obufp++ = 't';
10949               else
10950                 *obufp++ = 'n';
10951             }
10952           break;
10953         case 'J':
10954           if (intel_syntax)
10955             break;
10956           *obufp++ = 'l';
10957           break;
10958         case 'K':
10959           USED_REX (REX_W);
10960           if (rex & REX_W)
10961             *obufp++ = 'q';
10962           else
10963             *obufp++ = 'd';
10964           break;
10965         case 'Z':
10966           if (intel_syntax)
10967             break;
10968           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10969             {
10970               *obufp++ = 'q';
10971               break;
10972             }
10973           /* Fall through.  */
10974           goto case_L;
10975         case 'L':
10976           if (l != 0 || len != 1)
10977             {
10978               SAVE_LAST (*p);
10979               break;
10980             }
10981 case_L:
10982           if (intel_syntax)
10983             break;
10984           if (sizeflag & SUFFIX_ALWAYS)
10985             *obufp++ = 'l';
10986           break;
10987         case 'M':
10988           if (intel_mnemonic != cond)
10989             *obufp++ = 'r';
10990           break;
10991         case 'N':
10992           if ((prefixes & PREFIX_FWAIT) == 0)
10993             *obufp++ = 'n';
10994           else
10995             used_prefixes |= PREFIX_FWAIT;
10996           break;
10997         case 'O':
10998           USED_REX (REX_W);
10999           if (rex & REX_W)
11000             *obufp++ = 'o';
11001           else if (intel_syntax && (sizeflag & DFLAG))
11002             *obufp++ = 'q';
11003           else
11004             *obufp++ = 'd';
11005           if (!(rex & REX_W))
11006             used_prefixes |= (prefixes & PREFIX_DATA);
11007           break;
11008         case 'T':
11009           if (intel_syntax)
11010             break;
11011           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11012             {
11013               *obufp++ = 'q';
11014               break;
11015             }
11016           /* Fall through.  */
11017         case 'P':
11018           if (intel_syntax)
11019             break;
11020           if ((prefixes & PREFIX_DATA)
11021               || (rex & REX_W)
11022               || (sizeflag & SUFFIX_ALWAYS))
11023             {
11024               USED_REX (REX_W);
11025               if (rex & REX_W)
11026                 *obufp++ = 'q';
11027               else
11028                 {
11029                    if (sizeflag & DFLAG)
11030                       *obufp++ = 'l';
11031                    else
11032                      *obufp++ = 'w';
11033                 }
11034               used_prefixes |= (prefixes & PREFIX_DATA);
11035             }
11036           break;
11037         case 'U':
11038           if (intel_syntax)
11039             break;
11040           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11041             {
11042               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11043                 *obufp++ = 'q';
11044               break;
11045             }
11046           /* Fall through.  */
11047           goto case_Q;
11048         case 'Q':
11049           if (l == 0 && len == 1)
11050             {
11051 case_Q:
11052               if (intel_syntax && !alt)
11053                 break;
11054               USED_REX (REX_W);
11055               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11056                 {
11057                   if (rex & REX_W)
11058                     *obufp++ = 'q';
11059                   else
11060                     {
11061                       if (sizeflag & DFLAG)
11062                         *obufp++ = intel_syntax ? 'd' : 'l';
11063                       else
11064                         *obufp++ = 'w';
11065                     }
11066                   used_prefixes |= (prefixes & PREFIX_DATA);
11067                 }
11068             }
11069           else
11070             {
11071               if (l != 1 || len != 2 || last[0] != 'L')
11072                 {
11073                   SAVE_LAST (*p);
11074                   break;
11075                 }
11076               if (intel_syntax
11077                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11078                 break;
11079               if ((rex & REX_W))
11080                 {
11081                   USED_REX (REX_W);
11082                   *obufp++ = 'q';
11083                 }
11084               else
11085                 *obufp++ = 'l';
11086             }
11087           break;
11088         case 'R':
11089           USED_REX (REX_W);
11090           if (rex & REX_W)
11091             *obufp++ = 'q';
11092           else if (sizeflag & DFLAG)
11093             {
11094               if (intel_syntax)
11095                   *obufp++ = 'd';
11096               else
11097                   *obufp++ = 'l';
11098             }
11099           else
11100             *obufp++ = 'w';
11101           if (intel_syntax && !p[1]
11102               && ((rex & REX_W) || (sizeflag & DFLAG)))
11103             *obufp++ = 'e';
11104           if (!(rex & REX_W))
11105             used_prefixes |= (prefixes & PREFIX_DATA);
11106           break;
11107         case 'V':
11108           if (intel_syntax)
11109             break;
11110           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11111             {
11112               if (sizeflag & SUFFIX_ALWAYS)
11113                 *obufp++ = 'q';
11114               break;
11115             }
11116           /* Fall through.  */
11117         case 'S':
11118           if (intel_syntax)
11119             break;
11120           if (sizeflag & SUFFIX_ALWAYS)
11121             {
11122               if (rex & REX_W)
11123                 *obufp++ = 'q';
11124               else
11125                 {
11126                   if (sizeflag & DFLAG)
11127                     *obufp++ = 'l';
11128                   else
11129                     *obufp++ = 'w';
11130                   used_prefixes |= (prefixes & PREFIX_DATA);
11131                 }
11132             }
11133           break;
11134         case 'X':
11135           if (l != 0 || len != 1)
11136             {
11137               SAVE_LAST (*p);
11138               break;
11139             }
11140           if (need_vex && vex.prefix)
11141             {
11142               if (vex.prefix == DATA_PREFIX_OPCODE)
11143                 *obufp++ = 'd';
11144               else
11145                 *obufp++ = 's';
11146             }
11147           else if (prefixes & PREFIX_DATA)
11148             *obufp++ = 'd';
11149           else
11150             *obufp++ = 's';
11151           used_prefixes |= (prefixes & PREFIX_DATA);
11152           break;
11153         case 'Y':
11154           if (l == 0 && len == 1)
11155             {
11156               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11157                 break;
11158               if (rex & REX_W)
11159                 {
11160                   USED_REX (REX_W);
11161                   *obufp++ = 'q';
11162                 }
11163               break;
11164             }
11165           else
11166             {
11167               if (l != 1 || len != 2 || last[0] != 'X')
11168                 {
11169                   SAVE_LAST (*p);
11170                   break;
11171                 }
11172               if (!need_vex)
11173                 abort ();
11174               if (intel_syntax
11175                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11176                 break;
11177               switch (vex.length)
11178                 {
11179                 case 128:
11180                   *obufp++ = 'x';
11181                   break;
11182                 case 256:
11183                   *obufp++ = 'y';
11184                   break;
11185                 default:
11186                   abort ();
11187                 }
11188             }
11189           break;
11190         case 'W':
11191           if (l == 0 && len == 1)
11192             {
11193               /* operand size flag for cwtl, cbtw */
11194               USED_REX (REX_W);
11195               if (rex & REX_W)
11196                 {
11197                   if (intel_syntax)
11198                     *obufp++ = 'd';
11199                   else
11200                     *obufp++ = 'l';
11201                 }
11202               else if (sizeflag & DFLAG)
11203                 *obufp++ = 'w';
11204               else
11205                 *obufp++ = 'b';
11206               if (!(rex & REX_W))
11207                 used_prefixes |= (prefixes & PREFIX_DATA);
11208             }
11209           else
11210             {
11211               if (l != 1 || len != 2 || last[0] != 'X')
11212                 {
11213                   SAVE_LAST (*p);
11214                   break;
11215                 }
11216               if (!need_vex)
11217                 abort ();
11218               *obufp++ = vex.w ? 'd': 's';
11219             }
11220           break;
11221         }
11222       alt = 0;
11223     }
11224   *obufp = 0;
11225   mnemonicendp = obufp;
11226   return 0;
11227 }
11228
11229 static void
11230 oappend (const char *s)
11231 {
11232   obufp = stpcpy (obufp, s);
11233 }
11234
11235 static void
11236 append_seg (void)
11237 {
11238   if (prefixes & PREFIX_CS)
11239     {
11240       used_prefixes |= PREFIX_CS;
11241       oappend ("%cs:" + intel_syntax);
11242     }
11243   if (prefixes & PREFIX_DS)
11244     {
11245       used_prefixes |= PREFIX_DS;
11246       oappend ("%ds:" + intel_syntax);
11247     }
11248   if (prefixes & PREFIX_SS)
11249     {
11250       used_prefixes |= PREFIX_SS;
11251       oappend ("%ss:" + intel_syntax);
11252     }
11253   if (prefixes & PREFIX_ES)
11254     {
11255       used_prefixes |= PREFIX_ES;
11256       oappend ("%es:" + intel_syntax);
11257     }
11258   if (prefixes & PREFIX_FS)
11259     {
11260       used_prefixes |= PREFIX_FS;
11261       oappend ("%fs:" + intel_syntax);
11262     }
11263   if (prefixes & PREFIX_GS)
11264     {
11265       used_prefixes |= PREFIX_GS;
11266       oappend ("%gs:" + intel_syntax);
11267     }
11268 }
11269
11270 static void
11271 OP_indirE (int bytemode, int sizeflag)
11272 {
11273   if (!intel_syntax)
11274     oappend ("*");
11275   OP_E (bytemode, sizeflag);
11276 }
11277
11278 static void
11279 print_operand_value (char *buf, int hex, bfd_vma disp)
11280 {
11281   if (address_mode == mode_64bit)
11282     {
11283       if (hex)
11284         {
11285           char tmp[30];
11286           int i;
11287           buf[0] = '0';
11288           buf[1] = 'x';
11289           sprintf_vma (tmp, disp);
11290           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11291           strcpy (buf + 2, tmp + i);
11292         }
11293       else
11294         {
11295           bfd_signed_vma v = disp;
11296           char tmp[30];
11297           int i;
11298           if (v < 0)
11299             {
11300               *(buf++) = '-';
11301               v = -disp;
11302               /* Check for possible overflow on 0x8000000000000000.  */
11303               if (v < 0)
11304                 {
11305                   strcpy (buf, "9223372036854775808");
11306                   return;
11307                 }
11308             }
11309           if (!v)
11310             {
11311               strcpy (buf, "0");
11312               return;
11313             }
11314
11315           i = 0;
11316           tmp[29] = 0;
11317           while (v)
11318             {
11319               tmp[28 - i] = (v % 10) + '0';
11320               v /= 10;
11321               i++;
11322             }
11323           strcpy (buf, tmp + 29 - i);
11324         }
11325     }
11326   else
11327     {
11328       if (hex)
11329         sprintf (buf, "0x%x", (unsigned int) disp);
11330       else
11331         sprintf (buf, "%d", (int) disp);
11332     }
11333 }
11334
11335 /* Put DISP in BUF as signed hex number.  */
11336
11337 static void
11338 print_displacement (char *buf, bfd_vma disp)
11339 {
11340   bfd_signed_vma val = disp;
11341   char tmp[30];
11342   int i, j = 0;
11343
11344   if (val < 0)
11345     {
11346       buf[j++] = '-';
11347       val = -disp;
11348
11349       /* Check for possible overflow.  */
11350       if (val < 0)
11351         {
11352           switch (address_mode)
11353             {
11354             case mode_64bit:
11355               strcpy (buf + j, "0x8000000000000000");
11356               break;
11357             case mode_32bit:
11358               strcpy (buf + j, "0x80000000");
11359               break;
11360             case mode_16bit:
11361               strcpy (buf + j, "0x8000");
11362               break;
11363             }
11364           return;
11365         }
11366     }
11367
11368   buf[j++] = '0';
11369   buf[j++] = 'x';
11370
11371   sprintf_vma (tmp, (bfd_vma) val);
11372   for (i = 0; tmp[i] == '0'; i++)
11373     continue;
11374   if (tmp[i] == '\0')
11375     i--;
11376   strcpy (buf + j, tmp + i);
11377 }
11378
11379 static void
11380 intel_operand_size (int bytemode, int sizeflag)
11381 {
11382   switch (bytemode)
11383     {
11384     case b_mode:
11385     case b_swap_mode:
11386     case dqb_mode:
11387       oappend ("BYTE PTR ");
11388       break;
11389     case w_mode:
11390     case dqw_mode:
11391       oappend ("WORD PTR ");
11392       break;
11393     case stack_v_mode:
11394       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11395         {
11396           oappend ("QWORD PTR ");
11397           used_prefixes |= (prefixes & PREFIX_DATA);
11398           break;
11399         }
11400       /* FALLTHRU */
11401     case v_mode:
11402     case v_swap_mode:
11403     case dq_mode:
11404       USED_REX (REX_W);
11405       if (rex & REX_W)
11406         oappend ("QWORD PTR ");
11407       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11408         oappend ("DWORD PTR ");
11409       else
11410         oappend ("WORD PTR ");
11411       used_prefixes |= (prefixes & PREFIX_DATA);
11412       break;
11413     case z_mode:
11414       if ((rex & REX_W) || (sizeflag & DFLAG))
11415         *obufp++ = 'D';
11416       oappend ("WORD PTR ");
11417       if (!(rex & REX_W))
11418         used_prefixes |= (prefixes & PREFIX_DATA);
11419       break;
11420     case a_mode:
11421       if (sizeflag & DFLAG)
11422         oappend ("QWORD PTR ");
11423       else
11424         oappend ("DWORD PTR ");
11425       used_prefixes |= (prefixes & PREFIX_DATA);
11426       break;
11427     case d_mode:
11428     case d_swap_mode:
11429     case dqd_mode:
11430       oappend ("DWORD PTR ");
11431       break;
11432     case q_mode:
11433     case q_swap_mode:
11434       oappend ("QWORD PTR ");
11435       break;
11436     case m_mode:
11437       if (address_mode == mode_64bit)
11438         oappend ("QWORD PTR ");
11439       else
11440         oappend ("DWORD PTR ");
11441       break;
11442     case f_mode:
11443       if (sizeflag & DFLAG)
11444         oappend ("FWORD PTR ");
11445       else
11446         oappend ("DWORD PTR ");
11447       used_prefixes |= (prefixes & PREFIX_DATA);
11448       break;
11449     case t_mode:
11450       oappend ("TBYTE PTR ");
11451       break;
11452     case x_mode:
11453     case x_swap_mode:
11454       if (need_vex)
11455         {
11456           switch (vex.length)
11457             {
11458             case 128:
11459               oappend ("XMMWORD PTR ");
11460               break;
11461             case 256:
11462               oappend ("YMMWORD PTR ");
11463               break;
11464             default:
11465               abort ();
11466             }
11467         }
11468       else
11469         oappend ("XMMWORD PTR ");
11470       break;
11471     case xmm_mode:
11472       oappend ("XMMWORD PTR ");
11473       break;
11474     case xmmq_mode:
11475       if (!need_vex)
11476         abort ();
11477
11478       switch (vex.length)
11479         {
11480         case 128:
11481           oappend ("QWORD PTR ");
11482           break;
11483         case 256:
11484           oappend ("XMMWORD PTR ");
11485           break;
11486         default:
11487           abort ();
11488         }
11489       break;
11490     case ymmq_mode:
11491       if (!need_vex)
11492         abort ();
11493
11494       switch (vex.length)
11495         {
11496         case 128:
11497           oappend ("QWORD PTR ");
11498           break;
11499         case 256:
11500           oappend ("YMMWORD PTR ");
11501           break;
11502         default:
11503           abort ();
11504         }
11505       break;
11506     case o_mode:
11507       oappend ("OWORD PTR ");
11508       break;
11509     case vex_w_dq_mode:
11510       if (!need_vex)
11511         abort ();
11512
11513       if (vex.w)
11514         oappend ("QWORD PTR ");
11515       else
11516         oappend ("DWORD PTR ");
11517       break;
11518     default:
11519       break;
11520     }
11521 }
11522
11523 static void
11524 OP_E_register (int bytemode, int sizeflag)
11525 {
11526   int reg = modrm.rm;
11527   const char **names;
11528
11529   USED_REX (REX_B);
11530   if ((rex & REX_B))
11531     reg += 8;
11532
11533   if ((sizeflag & SUFFIX_ALWAYS)
11534       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11535     swap_operand ();
11536
11537   switch (bytemode)
11538     {
11539     case b_mode:
11540     case b_swap_mode:
11541       USED_REX (0);
11542       if (rex)
11543         names = names8rex;
11544       else
11545         names = names8;
11546       break;
11547     case w_mode:
11548       names = names16;
11549       break;
11550     case d_mode:
11551       names = names32;
11552       break;
11553     case q_mode:
11554       names = names64;
11555       break;
11556     case m_mode:
11557       names = address_mode == mode_64bit ? names64 : names32;
11558       break;
11559     case stack_v_mode:
11560       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11561         {
11562           names = names64;
11563           used_prefixes |= (prefixes & PREFIX_DATA);
11564           break;
11565         }
11566       bytemode = v_mode;
11567       /* FALLTHRU */
11568     case v_mode:
11569     case v_swap_mode:
11570     case dq_mode:
11571     case dqb_mode:
11572     case dqd_mode:
11573     case dqw_mode:
11574       USED_REX (REX_W);
11575       if (rex & REX_W)
11576         names = names64;
11577       else if ((sizeflag & DFLAG)
11578                || (bytemode != v_mode
11579                    && bytemode != v_swap_mode))
11580         names = names32;
11581       else
11582         names = names16;
11583       used_prefixes |= (prefixes & PREFIX_DATA);
11584       break;
11585     case 0:
11586       return;
11587     default:
11588       oappend (INTERNAL_DISASSEMBLER_ERROR);
11589       return;
11590     }
11591   oappend (names[reg]);
11592 }
11593
11594 static void
11595 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11596 {
11597   bfd_vma disp = 0;
11598   int add = (rex & REX_B) ? 8 : 0;
11599   int riprel = 0;
11600
11601   USED_REX (REX_B);
11602   if (intel_syntax)
11603     intel_operand_size (bytemode, sizeflag);
11604   append_seg ();
11605
11606   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11607     {
11608       /* 32/64 bit address mode */
11609       int havedisp;
11610       int havesib;
11611       int havebase;
11612       int haveindex;
11613       int needindex;
11614       int base, rbase;
11615       int index = 0;
11616       int scale = 0;
11617
11618       havesib = 0;
11619       havebase = 1;
11620       haveindex = 0;
11621       base = modrm.rm;
11622
11623       if (base == 4)
11624         {
11625           havesib = 1;
11626           FETCH_DATA (the_info, codep + 1);
11627           index = (*codep >> 3) & 7;
11628           scale = (*codep >> 6) & 3;
11629           base = *codep & 7;
11630           USED_REX (REX_X);
11631           if (rex & REX_X)
11632             index += 8;
11633           haveindex = index != 4;
11634           codep++;
11635         }
11636       rbase = base + add;
11637
11638       /* If we have a DREX byte, skip it now
11639          (it has already been handled) */
11640       if (has_drex)
11641         {
11642           FETCH_DATA (the_info, codep + 1);
11643           codep++;
11644         }
11645
11646       switch (modrm.mod)
11647         {
11648         case 0:
11649           if (base == 5)
11650             {
11651               havebase = 0;
11652               if (address_mode == mode_64bit && !havesib)
11653                 riprel = 1;
11654               disp = get32s ();
11655             }
11656           break;
11657         case 1:
11658           FETCH_DATA (the_info, codep + 1);
11659           disp = *codep++;
11660           if ((disp & 0x80) != 0)
11661             disp -= 0x100;
11662           break;
11663         case 2:
11664           disp = get32s ();
11665           break;
11666         }
11667
11668       /* In 32bit mode, we need index register to tell [offset] from
11669          [eiz*1 + offset].  */
11670       needindex = (havesib
11671                    && !havebase
11672                    && !haveindex
11673                    && address_mode == mode_32bit);
11674       havedisp = (havebase
11675                   || needindex
11676                   || (havesib && (haveindex || scale != 0)));
11677
11678       if (!intel_syntax)
11679         if (modrm.mod != 0 || base == 5)
11680           {
11681             if (havedisp || riprel)
11682               print_displacement (scratchbuf, disp);
11683             else
11684               print_operand_value (scratchbuf, 1, disp);
11685             oappend (scratchbuf);
11686             if (riprel)
11687               {
11688                 set_op (disp, 1);
11689                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11690               }
11691           }
11692
11693       if (havebase || haveindex || riprel)
11694         used_prefixes |= PREFIX_ADDR;
11695
11696       if (havedisp || (intel_syntax && riprel))
11697         {
11698           *obufp++ = open_char;
11699           if (intel_syntax && riprel)
11700             {
11701               set_op (disp, 1);
11702               oappend (sizeflag & AFLAG ? "rip" : "eip");
11703             }
11704           *obufp = '\0';
11705           if (havebase)
11706             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11707                      ? names64[rbase] : names32[rbase]);
11708           if (havesib)
11709             {
11710               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11711                  print index to tell base + index from base.  */
11712               if (scale != 0
11713                   || needindex
11714                   || haveindex
11715                   || (havebase && base != ESP_REG_NUM))
11716                 {
11717                   if (!intel_syntax || havebase)
11718                     {
11719                       *obufp++ = separator_char;
11720                       *obufp = '\0';
11721                     }
11722                   if (haveindex)
11723                     oappend (address_mode == mode_64bit
11724                              && (sizeflag & AFLAG)
11725                              ? names64[index] : names32[index]);
11726                   else
11727                     oappend (address_mode == mode_64bit
11728                              && (sizeflag & AFLAG)
11729                              ? index64 : index32);
11730
11731                   *obufp++ = scale_char;
11732                   *obufp = '\0';
11733                   sprintf (scratchbuf, "%d", 1 << scale);
11734                   oappend (scratchbuf);
11735                 }
11736             }
11737           if (intel_syntax
11738               && (disp || modrm.mod != 0 || base == 5))
11739             {
11740               if (!havedisp || (bfd_signed_vma) disp >= 0)
11741                 {
11742                   *obufp++ = '+';
11743                   *obufp = '\0';
11744                 }
11745               else if (modrm.mod != 1)
11746                 {
11747                   *obufp++ = '-';
11748                   *obufp = '\0';
11749                   disp = - (bfd_signed_vma) disp;
11750                 }
11751
11752               if (havedisp)
11753                 print_displacement (scratchbuf, disp);
11754               else
11755                 print_operand_value (scratchbuf, 1, disp);
11756               oappend (scratchbuf);
11757             }
11758
11759           *obufp++ = close_char;
11760           *obufp = '\0';
11761         }
11762       else if (intel_syntax)
11763         {
11764           if (modrm.mod != 0 || base == 5)
11765             {
11766               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11767                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11768                 ;
11769               else
11770                 {
11771                   oappend (names_seg[ds_reg - es_reg]);
11772                   oappend (":");
11773                 }
11774               print_operand_value (scratchbuf, 1, disp);
11775               oappend (scratchbuf);
11776             }
11777         }
11778     }
11779   else
11780     { /* 16 bit address mode */
11781       switch (modrm.mod)
11782         {
11783         case 0:
11784           if (modrm.rm == 6)
11785             {
11786               disp = get16 ();
11787               if ((disp & 0x8000) != 0)
11788                 disp -= 0x10000;
11789             }
11790           break;
11791         case 1:
11792           FETCH_DATA (the_info, codep + 1);
11793           disp = *codep++;
11794           if ((disp & 0x80) != 0)
11795             disp -= 0x100;
11796           break;
11797         case 2:
11798           disp = get16 ();
11799           if ((disp & 0x8000) != 0)
11800             disp -= 0x10000;
11801           break;
11802         }
11803
11804       if (!intel_syntax)
11805         if (modrm.mod != 0 || modrm.rm == 6)
11806           {
11807             print_displacement (scratchbuf, disp);
11808             oappend (scratchbuf);
11809           }
11810
11811       if (modrm.mod != 0 || modrm.rm != 6)
11812         {
11813           *obufp++ = open_char;
11814           *obufp = '\0';
11815           oappend (index16[modrm.rm]);
11816           if (intel_syntax
11817               && (disp || modrm.mod != 0 || modrm.rm == 6))
11818             {
11819               if ((bfd_signed_vma) disp >= 0)
11820                 {
11821                   *obufp++ = '+';
11822                   *obufp = '\0';
11823                 }
11824               else if (modrm.mod != 1)
11825                 {
11826                   *obufp++ = '-';
11827                   *obufp = '\0';
11828                   disp = - (bfd_signed_vma) disp;
11829                 }
11830
11831               print_displacement (scratchbuf, disp);
11832               oappend (scratchbuf);
11833             }
11834
11835           *obufp++ = close_char;
11836           *obufp = '\0';
11837         }
11838       else if (intel_syntax)
11839         {
11840           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11841                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11842             ;
11843           else
11844             {
11845               oappend (names_seg[ds_reg - es_reg]);
11846               oappend (":");
11847             }
11848           print_operand_value (scratchbuf, 1, disp & 0xffff);
11849           oappend (scratchbuf);
11850         }
11851     }
11852 }
11853
11854 static void
11855 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11856 {
11857   /* Skip mod/rm byte.  */
11858   MODRM_CHECK;
11859   codep++;
11860
11861   if (modrm.mod == 3)
11862     OP_E_register (bytemode, sizeflag);
11863   else
11864     OP_E_memory (bytemode, sizeflag, has_drex);
11865 }
11866
11867 static void
11868 OP_E (int bytemode, int sizeflag)
11869 {
11870   OP_E_extended (bytemode, sizeflag, 0);
11871 }
11872
11873
11874 static void
11875 OP_G (int bytemode, int sizeflag)
11876 {
11877   int add = 0;
11878   USED_REX (REX_R);
11879   if (rex & REX_R)
11880     add += 8;
11881   switch (bytemode)
11882     {
11883     case b_mode:
11884       USED_REX (0);
11885       if (rex)
11886         oappend (names8rex[modrm.reg + add]);
11887       else
11888         oappend (names8[modrm.reg + add]);
11889       break;
11890     case w_mode:
11891       oappend (names16[modrm.reg + add]);
11892       break;
11893     case d_mode:
11894       oappend (names32[modrm.reg + add]);
11895       break;
11896     case q_mode:
11897       oappend (names64[modrm.reg + add]);
11898       break;
11899     case v_mode:
11900     case dq_mode:
11901     case dqb_mode:
11902     case dqd_mode:
11903     case dqw_mode:
11904       USED_REX (REX_W);
11905       if (rex & REX_W)
11906         oappend (names64[modrm.reg + add]);
11907       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11908         oappend (names32[modrm.reg + add]);
11909       else
11910         oappend (names16[modrm.reg + add]);
11911       used_prefixes |= (prefixes & PREFIX_DATA);
11912       break;
11913     case m_mode:
11914       if (address_mode == mode_64bit)
11915         oappend (names64[modrm.reg + add]);
11916       else
11917         oappend (names32[modrm.reg + add]);
11918       break;
11919     default:
11920       oappend (INTERNAL_DISASSEMBLER_ERROR);
11921       break;
11922     }
11923 }
11924
11925 static bfd_vma
11926 get64 (void)
11927 {
11928   bfd_vma x;
11929 #ifdef BFD64
11930   unsigned int a;
11931   unsigned int b;
11932
11933   FETCH_DATA (the_info, codep + 8);
11934   a = *codep++ & 0xff;
11935   a |= (*codep++ & 0xff) << 8;
11936   a |= (*codep++ & 0xff) << 16;
11937   a |= (*codep++ & 0xff) << 24;
11938   b = *codep++ & 0xff;
11939   b |= (*codep++ & 0xff) << 8;
11940   b |= (*codep++ & 0xff) << 16;
11941   b |= (*codep++ & 0xff) << 24;
11942   x = a + ((bfd_vma) b << 32);
11943 #else
11944   abort ();
11945   x = 0;
11946 #endif
11947   return x;
11948 }
11949
11950 static bfd_signed_vma
11951 get32 (void)
11952 {
11953   bfd_signed_vma x = 0;
11954
11955   FETCH_DATA (the_info, codep + 4);
11956   x = *codep++ & (bfd_signed_vma) 0xff;
11957   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11958   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11959   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11960   return x;
11961 }
11962
11963 static bfd_signed_vma
11964 get32s (void)
11965 {
11966   bfd_signed_vma x = 0;
11967
11968   FETCH_DATA (the_info, codep + 4);
11969   x = *codep++ & (bfd_signed_vma) 0xff;
11970   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11971   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11972   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11973
11974   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11975
11976   return x;
11977 }
11978
11979 static int
11980 get16 (void)
11981 {
11982   int x = 0;
11983
11984   FETCH_DATA (the_info, codep + 2);
11985   x = *codep++ & 0xff;
11986   x |= (*codep++ & 0xff) << 8;
11987   return x;
11988 }
11989
11990 static void
11991 set_op (bfd_vma op, int riprel)
11992 {
11993   op_index[op_ad] = op_ad;
11994   if (address_mode == mode_64bit)
11995     {
11996       op_address[op_ad] = op;
11997       op_riprel[op_ad] = riprel;
11998     }
11999   else
12000     {
12001       /* Mask to get a 32-bit address.  */
12002       op_address[op_ad] = op & 0xffffffff;
12003       op_riprel[op_ad] = riprel & 0xffffffff;
12004     }
12005 }
12006
12007 static void
12008 OP_REG (int code, int sizeflag)
12009 {
12010   const char *s;
12011   int add;
12012   USED_REX (REX_B);
12013   if (rex & REX_B)
12014     add = 8;
12015   else
12016     add = 0;
12017
12018   switch (code)
12019     {
12020     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12021     case sp_reg: case bp_reg: case si_reg: case di_reg:
12022       s = names16[code - ax_reg + add];
12023       break;
12024     case es_reg: case ss_reg: case cs_reg:
12025     case ds_reg: case fs_reg: case gs_reg:
12026       s = names_seg[code - es_reg + add];
12027       break;
12028     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12029     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12030       USED_REX (0);
12031       if (rex)
12032         s = names8rex[code - al_reg + add];
12033       else
12034         s = names8[code - al_reg];
12035       break;
12036     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12037     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12038       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12039         {
12040           s = names64[code - rAX_reg + add];
12041           break;
12042         }
12043       code += eAX_reg - rAX_reg;
12044       /* Fall through.  */
12045     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12046     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12047       USED_REX (REX_W);
12048       if (rex & REX_W)
12049         s = names64[code - eAX_reg + add];
12050       else if (sizeflag & DFLAG)
12051         s = names32[code - eAX_reg + add];
12052       else
12053         s = names16[code - eAX_reg + add];
12054       used_prefixes |= (prefixes & PREFIX_DATA);
12055       break;
12056     default:
12057       s = INTERNAL_DISASSEMBLER_ERROR;
12058       break;
12059     }
12060   oappend (s);
12061 }
12062
12063 static void
12064 OP_IMREG (int code, int sizeflag)
12065 {
12066   const char *s;
12067
12068   switch (code)
12069     {
12070     case indir_dx_reg:
12071       if (intel_syntax)
12072         s = "dx";
12073       else
12074         s = "(%dx)";
12075       break;
12076     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12077     case sp_reg: case bp_reg: case si_reg: case di_reg:
12078       s = names16[code - ax_reg];
12079       break;
12080     case es_reg: case ss_reg: case cs_reg:
12081     case ds_reg: case fs_reg: case gs_reg:
12082       s = names_seg[code - es_reg];
12083       break;
12084     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12085     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12086       USED_REX (0);
12087       if (rex)
12088         s = names8rex[code - al_reg];
12089       else
12090         s = names8[code - al_reg];
12091       break;
12092     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12093     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12094       USED_REX (REX_W);
12095       if (rex & REX_W)
12096         s = names64[code - eAX_reg];
12097       else if (sizeflag & DFLAG)
12098         s = names32[code - eAX_reg];
12099       else
12100         s = names16[code - eAX_reg];
12101       used_prefixes |= (prefixes & PREFIX_DATA);
12102       break;
12103     case z_mode_ax_reg:
12104       if ((rex & REX_W) || (sizeflag & DFLAG))
12105         s = *names32;
12106       else
12107         s = *names16;
12108       if (!(rex & REX_W))
12109         used_prefixes |= (prefixes & PREFIX_DATA);
12110       break;
12111     default:
12112       s = INTERNAL_DISASSEMBLER_ERROR;
12113       break;
12114     }
12115   oappend (s);
12116 }
12117
12118 static void
12119 OP_I (int bytemode, int sizeflag)
12120 {
12121   bfd_signed_vma op;
12122   bfd_signed_vma mask = -1;
12123
12124   switch (bytemode)
12125     {
12126     case b_mode:
12127       FETCH_DATA (the_info, codep + 1);
12128       op = *codep++;
12129       mask = 0xff;
12130       break;
12131     case q_mode:
12132       if (address_mode == mode_64bit)
12133         {
12134           op = get32s ();
12135           break;
12136         }
12137       /* Fall through.  */
12138     case v_mode:
12139       USED_REX (REX_W);
12140       if (rex & REX_W)
12141         op = get32s ();
12142       else if (sizeflag & DFLAG)
12143         {
12144           op = get32 ();
12145           mask = 0xffffffff;
12146         }
12147       else
12148         {
12149           op = get16 ();
12150           mask = 0xfffff;
12151         }
12152       used_prefixes |= (prefixes & PREFIX_DATA);
12153       break;
12154     case w_mode:
12155       mask = 0xfffff;
12156       op = get16 ();
12157       break;
12158     case const_1_mode:
12159       if (intel_syntax)
12160         oappend ("1");
12161       return;
12162     default:
12163       oappend (INTERNAL_DISASSEMBLER_ERROR);
12164       return;
12165     }
12166
12167   op &= mask;
12168   scratchbuf[0] = '$';
12169   print_operand_value (scratchbuf + 1, 1, op);
12170   oappend (scratchbuf + intel_syntax);
12171   scratchbuf[0] = '\0';
12172 }
12173
12174 static void
12175 OP_I64 (int bytemode, int sizeflag)
12176 {
12177   bfd_signed_vma op;
12178   bfd_signed_vma mask = -1;
12179
12180   if (address_mode != mode_64bit)
12181     {
12182       OP_I (bytemode, sizeflag);
12183       return;
12184     }
12185
12186   switch (bytemode)
12187     {
12188     case b_mode:
12189       FETCH_DATA (the_info, codep + 1);
12190       op = *codep++;
12191       mask = 0xff;
12192       break;
12193     case v_mode:
12194       USED_REX (REX_W);
12195       if (rex & REX_W)
12196         op = get64 ();
12197       else if (sizeflag & DFLAG)
12198         {
12199           op = get32 ();
12200           mask = 0xffffffff;
12201         }
12202       else
12203         {
12204           op = get16 ();
12205           mask = 0xfffff;
12206         }
12207       used_prefixes |= (prefixes & PREFIX_DATA);
12208       break;
12209     case w_mode:
12210       mask = 0xfffff;
12211       op = get16 ();
12212       break;
12213     default:
12214       oappend (INTERNAL_DISASSEMBLER_ERROR);
12215       return;
12216     }
12217
12218   op &= mask;
12219   scratchbuf[0] = '$';
12220   print_operand_value (scratchbuf + 1, 1, op);
12221   oappend (scratchbuf + intel_syntax);
12222   scratchbuf[0] = '\0';
12223 }
12224
12225 static void
12226 OP_sI (int bytemode, int sizeflag)
12227 {
12228   bfd_signed_vma op;
12229   bfd_signed_vma mask = -1;
12230
12231   switch (bytemode)
12232     {
12233     case b_mode:
12234       FETCH_DATA (the_info, codep + 1);
12235       op = *codep++;
12236       if ((op & 0x80) != 0)
12237         op -= 0x100;
12238       mask = 0xffffffff;
12239       break;
12240     case v_mode:
12241       USED_REX (REX_W);
12242       if (rex & REX_W)
12243         op = get32s ();
12244       else if (sizeflag & DFLAG)
12245         {
12246           op = get32s ();
12247           mask = 0xffffffff;
12248         }
12249       else
12250         {
12251           mask = 0xffffffff;
12252           op = get16 ();
12253           if ((op & 0x8000) != 0)
12254             op -= 0x10000;
12255         }
12256       used_prefixes |= (prefixes & PREFIX_DATA);
12257       break;
12258     case w_mode:
12259       op = get16 ();
12260       mask = 0xffffffff;
12261       if ((op & 0x8000) != 0)
12262         op -= 0x10000;
12263       break;
12264     default:
12265       oappend (INTERNAL_DISASSEMBLER_ERROR);
12266       return;
12267     }
12268
12269   scratchbuf[0] = '$';
12270   print_operand_value (scratchbuf + 1, 1, op);
12271   oappend (scratchbuf + intel_syntax);
12272 }
12273
12274 static void
12275 OP_J (int bytemode, int sizeflag)
12276 {
12277   bfd_vma disp;
12278   bfd_vma mask = -1;
12279   bfd_vma segment = 0;
12280
12281   switch (bytemode)
12282     {
12283     case b_mode:
12284       FETCH_DATA (the_info, codep + 1);
12285       disp = *codep++;
12286       if ((disp & 0x80) != 0)
12287         disp -= 0x100;
12288       break;
12289     case v_mode:
12290       if ((sizeflag & DFLAG) || (rex & REX_W))
12291         disp = get32s ();
12292       else
12293         {
12294           disp = get16 ();
12295           if ((disp & 0x8000) != 0)
12296             disp -= 0x10000;
12297           /* In 16bit mode, address is wrapped around at 64k within
12298              the same segment.  Otherwise, a data16 prefix on a jump
12299              instruction means that the pc is masked to 16 bits after
12300              the displacement is added!  */
12301           mask = 0xffff;
12302           if ((prefixes & PREFIX_DATA) == 0)
12303             segment = ((start_pc + codep - start_codep)
12304                        & ~((bfd_vma) 0xffff));
12305         }
12306       used_prefixes |= (prefixes & PREFIX_DATA);
12307       break;
12308     default:
12309       oappend (INTERNAL_DISASSEMBLER_ERROR);
12310       return;
12311     }
12312   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12313   set_op (disp, 0);
12314   print_operand_value (scratchbuf, 1, disp);
12315   oappend (scratchbuf);
12316 }
12317
12318 static void
12319 OP_SEG (int bytemode, int sizeflag)
12320 {
12321   if (bytemode == w_mode)
12322     oappend (names_seg[modrm.reg]);
12323   else
12324     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12325 }
12326
12327 static void
12328 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12329 {
12330   int seg, offset;
12331
12332   if (sizeflag & DFLAG)
12333     {
12334       offset = get32 ();
12335       seg = get16 ();
12336     }
12337   else
12338     {
12339       offset = get16 ();
12340       seg = get16 ();
12341     }
12342   used_prefixes |= (prefixes & PREFIX_DATA);
12343   if (intel_syntax)
12344     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12345   else
12346     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12347   oappend (scratchbuf);
12348 }
12349
12350 static void
12351 OP_OFF (int bytemode, int sizeflag)
12352 {
12353   bfd_vma off;
12354
12355   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12356     intel_operand_size (bytemode, sizeflag);
12357   append_seg ();
12358
12359   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12360     off = get32 ();
12361   else
12362     off = get16 ();
12363
12364   if (intel_syntax)
12365     {
12366       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12367                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12368         {
12369           oappend (names_seg[ds_reg - es_reg]);
12370           oappend (":");
12371         }
12372     }
12373   print_operand_value (scratchbuf, 1, off);
12374   oappend (scratchbuf);
12375 }
12376
12377 static void
12378 OP_OFF64 (int bytemode, int sizeflag)
12379 {
12380   bfd_vma off;
12381
12382   if (address_mode != mode_64bit
12383       || (prefixes & PREFIX_ADDR))
12384     {
12385       OP_OFF (bytemode, sizeflag);
12386       return;
12387     }
12388
12389   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12390     intel_operand_size (bytemode, sizeflag);
12391   append_seg ();
12392
12393   off = get64 ();
12394
12395   if (intel_syntax)
12396     {
12397       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12398                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12399         {
12400           oappend (names_seg[ds_reg - es_reg]);
12401           oappend (":");
12402         }
12403     }
12404   print_operand_value (scratchbuf, 1, off);
12405   oappend (scratchbuf);
12406 }
12407
12408 static void
12409 ptr_reg (int code, int sizeflag)
12410 {
12411   const char *s;
12412
12413   *obufp++ = open_char;
12414   used_prefixes |= (prefixes & PREFIX_ADDR);
12415   if (address_mode == mode_64bit)
12416     {
12417       if (!(sizeflag & AFLAG))
12418         s = names32[code - eAX_reg];
12419       else
12420         s = names64[code - eAX_reg];
12421     }
12422   else if (sizeflag & AFLAG)
12423     s = names32[code - eAX_reg];
12424   else
12425     s = names16[code - eAX_reg];
12426   oappend (s);
12427   *obufp++ = close_char;
12428   *obufp = 0;
12429 }
12430
12431 static void
12432 OP_ESreg (int code, int sizeflag)
12433 {
12434   if (intel_syntax)
12435     {
12436       switch (codep[-1])
12437         {
12438         case 0x6d:      /* insw/insl */
12439           intel_operand_size (z_mode, sizeflag);
12440           break;
12441         case 0xa5:      /* movsw/movsl/movsq */
12442         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12443         case 0xab:      /* stosw/stosl */
12444         case 0xaf:      /* scasw/scasl */
12445           intel_operand_size (v_mode, sizeflag);
12446           break;
12447         default:
12448           intel_operand_size (b_mode, sizeflag);
12449         }
12450     }
12451   oappend ("%es:" + intel_syntax);
12452   ptr_reg (code, sizeflag);
12453 }
12454
12455 static void
12456 OP_DSreg (int code, int sizeflag)
12457 {
12458   if (intel_syntax)
12459     {
12460       switch (codep[-1])
12461         {
12462         case 0x6f:      /* outsw/outsl */
12463           intel_operand_size (z_mode, sizeflag);
12464           break;
12465         case 0xa5:      /* movsw/movsl/movsq */
12466         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12467         case 0xad:      /* lodsw/lodsl/lodsq */
12468           intel_operand_size (v_mode, sizeflag);
12469           break;
12470         default:
12471           intel_operand_size (b_mode, sizeflag);
12472         }
12473     }
12474   if ((prefixes
12475        & (PREFIX_CS
12476           | PREFIX_DS
12477           | PREFIX_SS
12478           | PREFIX_ES
12479           | PREFIX_FS
12480           | PREFIX_GS)) == 0)
12481     prefixes |= PREFIX_DS;
12482   append_seg ();
12483   ptr_reg (code, sizeflag);
12484 }
12485
12486 static void
12487 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12488 {
12489   int add;
12490   if (rex & REX_R)
12491     {
12492       USED_REX (REX_R);
12493       add = 8;
12494     }
12495   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12496     {
12497       lock_prefix = NULL;
12498       used_prefixes |= PREFIX_LOCK;
12499       add = 8;
12500     }
12501   else
12502     add = 0;
12503   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12504   oappend (scratchbuf + intel_syntax);
12505 }
12506
12507 static void
12508 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12509 {
12510   int add;
12511   USED_REX (REX_R);
12512   if (rex & REX_R)
12513     add = 8;
12514   else
12515     add = 0;
12516   if (intel_syntax)
12517     sprintf (scratchbuf, "db%d", modrm.reg + add);
12518   else
12519     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12520   oappend (scratchbuf);
12521 }
12522
12523 static void
12524 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12525 {
12526   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12527   oappend (scratchbuf + intel_syntax);
12528 }
12529
12530 static void
12531 OP_R (int bytemode, int sizeflag)
12532 {
12533   if (modrm.mod == 3)
12534     OP_E (bytemode, sizeflag);
12535   else
12536     BadOp ();
12537 }
12538
12539 static void
12540 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12541 {
12542   used_prefixes |= (prefixes & PREFIX_DATA);
12543   if (prefixes & PREFIX_DATA)
12544     {
12545       int add;
12546       USED_REX (REX_R);
12547       if (rex & REX_R)
12548         add = 8;
12549       else
12550         add = 0;
12551       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12552     }
12553   else
12554     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12555   oappend (scratchbuf + intel_syntax);
12556 }
12557
12558 static void
12559 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12560 {
12561   int add;
12562   USED_REX (REX_R);
12563   if (rex & REX_R)
12564     add = 8;
12565   else
12566     add = 0;
12567   if (need_vex && bytemode != xmm_mode)
12568     {
12569       switch (vex.length)
12570         {
12571         case 128:
12572           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12573           break;
12574         case 256:
12575           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12576           break;
12577         default:
12578           abort ();
12579         }
12580     }
12581   else
12582     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12583   oappend (scratchbuf + intel_syntax);
12584 }
12585
12586 static void
12587 OP_EM (int bytemode, int sizeflag)
12588 {
12589   if (modrm.mod != 3)
12590     {
12591       if (intel_syntax
12592           && (bytemode == v_mode || bytemode == v_swap_mode))
12593         {
12594           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12595           used_prefixes |= (prefixes & PREFIX_DATA);
12596         }
12597       OP_E (bytemode, sizeflag);
12598       return;
12599     }
12600
12601   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12602     swap_operand ();
12603
12604   /* Skip mod/rm byte.  */
12605   MODRM_CHECK;
12606   codep++;
12607   used_prefixes |= (prefixes & PREFIX_DATA);
12608   if (prefixes & PREFIX_DATA)
12609     {
12610       int add;
12611
12612       USED_REX (REX_B);
12613       if (rex & REX_B)
12614         add = 8;
12615       else
12616         add = 0;
12617       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12618     }
12619   else
12620     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12621   oappend (scratchbuf + intel_syntax);
12622 }
12623
12624 /* cvt* are the only instructions in sse2 which have
12625    both SSE and MMX operands and also have 0x66 prefix
12626    in their opcode. 0x66 was originally used to differentiate
12627    between SSE and MMX instruction(operands). So we have to handle the
12628    cvt* separately using OP_EMC and OP_MXC */
12629 static void
12630 OP_EMC (int bytemode, int sizeflag)
12631 {
12632   if (modrm.mod != 3)
12633     {
12634       if (intel_syntax && bytemode == v_mode)
12635         {
12636           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12637           used_prefixes |= (prefixes & PREFIX_DATA);
12638         }
12639       OP_E (bytemode, sizeflag);
12640       return;
12641     }
12642
12643   /* Skip mod/rm byte.  */
12644   MODRM_CHECK;
12645   codep++;
12646   used_prefixes |= (prefixes & PREFIX_DATA);
12647   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12648   oappend (scratchbuf + intel_syntax);
12649 }
12650
12651 static void
12652 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12653 {
12654   used_prefixes |= (prefixes & PREFIX_DATA);
12655   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12656   oappend (scratchbuf + intel_syntax);
12657 }
12658
12659 static void
12660 OP_EX (int bytemode, int sizeflag)
12661 {
12662   int add;
12663   if (modrm.mod != 3)
12664     {
12665       OP_E (bytemode, sizeflag);
12666       return;
12667     }
12668   USED_REX (REX_B);
12669   if (rex & REX_B)
12670     add = 8;
12671   else
12672     add = 0;
12673
12674   if ((sizeflag & SUFFIX_ALWAYS)
12675       && (bytemode == x_swap_mode
12676           || bytemode == d_swap_mode
12677           || bytemode == q_swap_mode))
12678     swap_operand ();
12679
12680   /* Skip mod/rm byte.  */
12681   MODRM_CHECK;
12682   codep++;
12683   if (need_vex
12684       && bytemode != xmm_mode
12685       && bytemode != xmmq_mode)
12686     {
12687       switch (vex.length)
12688         {
12689         case 128:
12690           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12691           break;
12692         case 256:
12693           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12694           break;
12695         default:
12696           abort ();
12697         }
12698     }
12699   else
12700     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12701   oappend (scratchbuf + intel_syntax);
12702 }
12703
12704 static void
12705 OP_MS (int bytemode, int sizeflag)
12706 {
12707   if (modrm.mod == 3)
12708     OP_EM (bytemode, sizeflag);
12709   else
12710     BadOp ();
12711 }
12712
12713 static void
12714 OP_XS (int bytemode, int sizeflag)
12715 {
12716   if (modrm.mod == 3)
12717     OP_EX (bytemode, sizeflag);
12718   else
12719     BadOp ();
12720 }
12721
12722 static void
12723 OP_M (int bytemode, int sizeflag)
12724 {
12725   if (modrm.mod == 3)
12726     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12727     BadOp ();
12728   else
12729     OP_E (bytemode, sizeflag);
12730 }
12731
12732 static void
12733 OP_0f07 (int bytemode, int sizeflag)
12734 {
12735   if (modrm.mod != 3 || modrm.rm != 0)
12736     BadOp ();
12737   else
12738     OP_E (bytemode, sizeflag);
12739 }
12740
12741 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12742    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12743
12744 static void
12745 NOP_Fixup1 (int bytemode, int sizeflag)
12746 {
12747   if ((prefixes & PREFIX_DATA) != 0
12748       || (rex != 0
12749           && rex != 0x48
12750           && address_mode == mode_64bit))
12751     OP_REG (bytemode, sizeflag);
12752   else
12753     strcpy (obuf, "nop");
12754 }
12755
12756 static void
12757 NOP_Fixup2 (int bytemode, int sizeflag)
12758 {
12759   if ((prefixes & PREFIX_DATA) != 0
12760       || (rex != 0
12761           && rex != 0x48
12762           && address_mode == mode_64bit))
12763     OP_IMREG (bytemode, sizeflag);
12764 }
12765
12766 static const char *const Suffix3DNow[] = {
12767 /* 00 */        NULL,           NULL,           NULL,           NULL,
12768 /* 04 */        NULL,           NULL,           NULL,           NULL,
12769 /* 08 */        NULL,           NULL,           NULL,           NULL,
12770 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12771 /* 10 */        NULL,           NULL,           NULL,           NULL,
12772 /* 14 */        NULL,           NULL,           NULL,           NULL,
12773 /* 18 */        NULL,           NULL,           NULL,           NULL,
12774 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12775 /* 20 */        NULL,           NULL,           NULL,           NULL,
12776 /* 24 */        NULL,           NULL,           NULL,           NULL,
12777 /* 28 */        NULL,           NULL,           NULL,           NULL,
12778 /* 2C */        NULL,           NULL,           NULL,           NULL,
12779 /* 30 */        NULL,           NULL,           NULL,           NULL,
12780 /* 34 */        NULL,           NULL,           NULL,           NULL,
12781 /* 38 */        NULL,           NULL,           NULL,           NULL,
12782 /* 3C */        NULL,           NULL,           NULL,           NULL,
12783 /* 40 */        NULL,           NULL,           NULL,           NULL,
12784 /* 44 */        NULL,           NULL,           NULL,           NULL,
12785 /* 48 */        NULL,           NULL,           NULL,           NULL,
12786 /* 4C */        NULL,           NULL,           NULL,           NULL,
12787 /* 50 */        NULL,           NULL,           NULL,           NULL,
12788 /* 54 */        NULL,           NULL,           NULL,           NULL,
12789 /* 58 */        NULL,           NULL,           NULL,           NULL,
12790 /* 5C */        NULL,           NULL,           NULL,           NULL,
12791 /* 60 */        NULL,           NULL,           NULL,           NULL,
12792 /* 64 */        NULL,           NULL,           NULL,           NULL,
12793 /* 68 */        NULL,           NULL,           NULL,           NULL,
12794 /* 6C */        NULL,           NULL,           NULL,           NULL,
12795 /* 70 */        NULL,           NULL,           NULL,           NULL,
12796 /* 74 */        NULL,           NULL,           NULL,           NULL,
12797 /* 78 */        NULL,           NULL,           NULL,           NULL,
12798 /* 7C */        NULL,           NULL,           NULL,           NULL,
12799 /* 80 */        NULL,           NULL,           NULL,           NULL,
12800 /* 84 */        NULL,           NULL,           NULL,           NULL,
12801 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12802 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12803 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12804 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12805 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12806 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12807 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12808 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12809 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12810 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12811 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12812 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12813 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12814 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12815 /* C0 */        NULL,           NULL,           NULL,           NULL,
12816 /* C4 */        NULL,           NULL,           NULL,           NULL,
12817 /* C8 */        NULL,           NULL,           NULL,           NULL,
12818 /* CC */        NULL,           NULL,           NULL,           NULL,
12819 /* D0 */        NULL,           NULL,           NULL,           NULL,
12820 /* D4 */        NULL,           NULL,           NULL,           NULL,
12821 /* D8 */        NULL,           NULL,           NULL,           NULL,
12822 /* DC */        NULL,           NULL,           NULL,           NULL,
12823 /* E0 */        NULL,           NULL,           NULL,           NULL,
12824 /* E4 */        NULL,           NULL,           NULL,           NULL,
12825 /* E8 */        NULL,           NULL,           NULL,           NULL,
12826 /* EC */        NULL,           NULL,           NULL,           NULL,
12827 /* F0 */        NULL,           NULL,           NULL,           NULL,
12828 /* F4 */        NULL,           NULL,           NULL,           NULL,
12829 /* F8 */        NULL,           NULL,           NULL,           NULL,
12830 /* FC */        NULL,           NULL,           NULL,           NULL,
12831 };
12832
12833 static void
12834 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12835 {
12836   const char *mnemonic;
12837
12838   FETCH_DATA (the_info, codep + 1);
12839   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12840      place where an 8-bit immediate would normally go.  ie. the last
12841      byte of the instruction.  */
12842   obufp = mnemonicendp;
12843   mnemonic = Suffix3DNow[*codep++ & 0xff];
12844   if (mnemonic)
12845     oappend (mnemonic);
12846   else
12847     {
12848       /* Since a variable sized modrm/sib chunk is between the start
12849          of the opcode (0x0f0f) and the opcode suffix, we need to do
12850          all the modrm processing first, and don't know until now that
12851          we have a bad opcode.  This necessitates some cleaning up.  */
12852       op_out[0][0] = '\0';
12853       op_out[1][0] = '\0';
12854       BadOp ();
12855     }
12856   mnemonicendp = obufp;
12857 }
12858
12859 static struct op simd_cmp_op[] =
12860 {
12861   { STRING_COMMA_LEN ("eq") },
12862   { STRING_COMMA_LEN ("lt") },
12863   { STRING_COMMA_LEN ("le") },
12864   { STRING_COMMA_LEN ("unord") },
12865   { STRING_COMMA_LEN ("neq") },
12866   { STRING_COMMA_LEN ("nlt") },
12867   { STRING_COMMA_LEN ("nle") },
12868   { STRING_COMMA_LEN ("ord") }
12869 };
12870
12871 static void
12872 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12873 {
12874   unsigned int cmp_type;
12875
12876   FETCH_DATA (the_info, codep + 1);
12877   cmp_type = *codep++ & 0xff;
12878   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12879     {
12880       char suffix [3];
12881       char *p = mnemonicendp - 2;
12882       suffix[0] = p[0];
12883       suffix[1] = p[1];
12884       suffix[2] = '\0';
12885       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12886       mnemonicendp += simd_cmp_op[cmp_type].len;
12887     }
12888   else
12889     {
12890       /* We have a reserved extension byte.  Output it directly.  */
12891       scratchbuf[0] = '$';
12892       print_operand_value (scratchbuf + 1, 1, cmp_type);
12893       oappend (scratchbuf + intel_syntax);
12894       scratchbuf[0] = '\0';
12895     }
12896 }
12897
12898 static void
12899 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12900           int sizeflag ATTRIBUTE_UNUSED)
12901 {
12902   /* mwait %eax,%ecx  */
12903   if (!intel_syntax)
12904     {
12905       const char **names = (address_mode == mode_64bit
12906                             ? names64 : names32);
12907       strcpy (op_out[0], names[0]);
12908       strcpy (op_out[1], names[1]);
12909       two_source_ops = 1;
12910     }
12911   /* Skip mod/rm byte.  */
12912   MODRM_CHECK;
12913   codep++;
12914 }
12915
12916 static void
12917 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12918             int sizeflag ATTRIBUTE_UNUSED)
12919 {
12920   /* monitor %eax,%ecx,%edx"  */
12921   if (!intel_syntax)
12922     {
12923       const char **op1_names;
12924       const char **names = (address_mode == mode_64bit
12925                             ? names64 : names32);
12926
12927       if (!(prefixes & PREFIX_ADDR))
12928         op1_names = (address_mode == mode_16bit
12929                      ? names16 : names);
12930       else
12931         {
12932           /* Remove "addr16/addr32".  */
12933           addr_prefix = NULL;
12934           op1_names = (address_mode != mode_32bit
12935                        ? names32 : names16);
12936           used_prefixes |= PREFIX_ADDR;
12937         }
12938       strcpy (op_out[0], op1_names[0]);
12939       strcpy (op_out[1], names[1]);
12940       strcpy (op_out[2], names[2]);
12941       two_source_ops = 1;
12942     }
12943   /* Skip mod/rm byte.  */
12944   MODRM_CHECK;
12945   codep++;
12946 }
12947
12948 static void
12949 BadOp (void)
12950 {
12951   /* Throw away prefixes and 1st. opcode byte.  */
12952   codep = insn_codep + 1;
12953   oappend ("(bad)");
12954 }
12955
12956 static void
12957 REP_Fixup (int bytemode, int sizeflag)
12958 {
12959   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12960      lods and stos.  */
12961   if (prefixes & PREFIX_REPZ)
12962     repz_prefix = "rep ";
12963
12964   switch (bytemode)
12965     {
12966     case al_reg:
12967     case eAX_reg:
12968     case indir_dx_reg:
12969       OP_IMREG (bytemode, sizeflag);
12970       break;
12971     case eDI_reg:
12972       OP_ESreg (bytemode, sizeflag);
12973       break;
12974     case eSI_reg:
12975       OP_DSreg (bytemode, sizeflag);
12976       break;
12977     default:
12978       abort ();
12979       break;
12980     }
12981 }
12982
12983 static void
12984 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12985 {
12986   USED_REX (REX_W);
12987   if (rex & REX_W)
12988     {
12989       /* Change cmpxchg8b to cmpxchg16b.  */
12990       char *p = mnemonicendp - 2;
12991       mnemonicendp = stpcpy (p, "16b");
12992       bytemode = o_mode;
12993     }
12994   OP_M (bytemode, sizeflag);
12995 }
12996
12997 static void
12998 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12999 {
13000   if (need_vex)
13001     {
13002       switch (vex.length)
13003         {
13004         case 128:
13005           sprintf (scratchbuf, "%%xmm%d", reg);
13006           break;
13007         case 256:
13008           sprintf (scratchbuf, "%%ymm%d", reg);
13009           break;
13010         default:
13011           abort ();
13012         }
13013     }
13014   else
13015     sprintf (scratchbuf, "%%xmm%d", reg);
13016   oappend (scratchbuf + intel_syntax);
13017 }
13018
13019 static void
13020 CRC32_Fixup (int bytemode, int sizeflag)
13021 {
13022   /* Add proper suffix to "crc32".  */
13023   char *p = mnemonicendp;
13024
13025   switch (bytemode)
13026     {
13027     case b_mode:
13028       if (intel_syntax)
13029         goto skip;
13030
13031       *p++ = 'b';
13032       break;
13033     case v_mode:
13034       if (intel_syntax)
13035         goto skip;
13036
13037       USED_REX (REX_W);
13038       if (rex & REX_W)
13039         *p++ = 'q';
13040       else if (sizeflag & DFLAG)
13041         *p++ = 'l';
13042       else
13043         *p++ = 'w';
13044       used_prefixes |= (prefixes & PREFIX_DATA);
13045       break;
13046     default:
13047       oappend (INTERNAL_DISASSEMBLER_ERROR);
13048       break;
13049     }
13050   mnemonicendp = p;
13051   *p = '\0';
13052
13053 skip:
13054   if (modrm.mod == 3)
13055     {
13056       int add;
13057
13058       /* Skip mod/rm byte.  */
13059       MODRM_CHECK;
13060       codep++;
13061
13062       USED_REX (REX_B);
13063       add = (rex & REX_B) ? 8 : 0;
13064       if (bytemode == b_mode)
13065         {
13066           USED_REX (0);
13067           if (rex)
13068             oappend (names8rex[modrm.rm + add]);
13069           else
13070             oappend (names8[modrm.rm + add]);
13071         }
13072       else
13073         {
13074           USED_REX (REX_W);
13075           if (rex & REX_W)
13076             oappend (names64[modrm.rm + add]);
13077           else if ((prefixes & PREFIX_DATA))
13078             oappend (names16[modrm.rm + add]);
13079           else
13080             oappend (names32[modrm.rm + add]);
13081         }
13082     }
13083   else
13084     OP_E (bytemode, sizeflag);
13085 }
13086
13087 /* Print a DREX argument as either a register or memory operation.  */
13088 static void
13089 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
13090 {
13091   if (reg == DREX_REG_UNKNOWN)
13092     BadOp ();
13093
13094   else if (reg != DREX_REG_MEMORY)
13095     {
13096       sprintf (scratchbuf, "%%xmm%d", reg);
13097       oappend (scratchbuf + intel_syntax);
13098     }
13099
13100   else
13101     OP_E_extended (bytemode, sizeflag, 1);
13102 }
13103
13104 /* SSE5 instructions that have 4 arguments are encoded as:
13105    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
13106
13107    The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
13108    the DREX field (0x8) to determine how the arguments are laid out.
13109    The destination register must be the same register as one of the
13110    inputs, and it is encoded in the DREX byte.  No REX prefix is used
13111    for these instructions, since the DREX field contains the 3 extension
13112    bits provided by the REX prefix.
13113
13114    The bytemode argument adds 2 extra bits for passing extra information:
13115         DREX_OC1        -- Set the OC1 bit to indicate dest == 1st arg
13116         DREX_NO_OC0     -- OC0 in DREX is invalid
13117         (but pretend it is set).  */
13118
13119 static void
13120 OP_DREX4 (int flag_bytemode, int sizeflag)
13121 {
13122   unsigned int drex_byte;
13123   unsigned int regs[4];
13124   unsigned int modrm_regmem;
13125   unsigned int modrm_reg;
13126   unsigned int drex_reg;
13127   int bytemode;
13128   int rex_save = rex;
13129   int rex_used_save = rex_used;
13130   int has_sib = 0;
13131   int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
13132   int oc0;
13133   int i;
13134
13135   bytemode = flag_bytemode & ~ DREX_MASK;
13136
13137   for (i = 0; i < 4; i++)
13138     regs[i] = DREX_REG_UNKNOWN;
13139
13140   /* Determine if we have a SIB byte in addition to MODRM before the
13141      DREX byte.  */
13142   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13143       && (modrm.mod != 3)
13144       && (modrm.rm == 4))
13145     has_sib = 1;
13146
13147   /* Get the DREX byte.  */
13148   FETCH_DATA (the_info, codep + 2 + has_sib);
13149   drex_byte = codep[has_sib+1];
13150   drex_reg = DREX_XMM (drex_byte);
13151   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13152
13153   /* Is OC0 legal?  If not, hardwire oc0 == 1.  */
13154   if (flag_bytemode & DREX_NO_OC0)
13155     {
13156       oc0 = 1;
13157       if (DREX_OC0 (drex_byte))
13158         BadOp ();
13159     }
13160   else
13161     oc0 = DREX_OC0 (drex_byte);
13162
13163   if (modrm.mod == 3)
13164     {
13165       /* regmem == register  */
13166       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13167       rex = rex_used = 0;
13168       /* skip modrm/drex since we don't call OP_E_extended  */
13169       codep += 2;
13170     }
13171   else
13172     {
13173       /* regmem == memory, fill in appropriate REX bits  */
13174       modrm_regmem = DREX_REG_MEMORY;
13175       rex = drex_byte & (REX_B | REX_X | REX_R);
13176       if (rex)
13177         rex |= REX_OPCODE;
13178       rex_used = rex;
13179     }
13180
13181   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13182      order.  */
13183   switch (oc0 + oc1)
13184     {
13185     default:
13186       BadOp ();
13187       return;
13188
13189     case 0:
13190       regs[0] = modrm_regmem;
13191       regs[1] = modrm_reg;
13192       regs[2] = drex_reg;
13193       regs[3] = drex_reg;
13194       break;
13195
13196     case 1:
13197       regs[0] = modrm_reg;
13198       regs[1] = modrm_regmem;
13199       regs[2] = drex_reg;
13200       regs[3] = drex_reg;
13201       break;
13202
13203     case 2:
13204       regs[0] = drex_reg;
13205       regs[1] = modrm_regmem;
13206       regs[2] = modrm_reg;
13207       regs[3] = drex_reg;
13208       break;
13209
13210     case 3:
13211       regs[0] = drex_reg;
13212       regs[1] = modrm_reg;
13213       regs[2] = modrm_regmem;
13214       regs[3] = drex_reg;
13215       break;
13216     }
13217
13218   /* Print out the arguments.  */
13219   for (i = 0; i < 4; i++)
13220     {
13221       int j = (intel_syntax) ? 3 - i : i;
13222       if (i > 0)
13223         {
13224           *obufp++ = ',';
13225           *obufp = '\0';
13226         }
13227
13228       print_drex_arg (regs[j], bytemode, sizeflag);
13229     }
13230
13231   rex = rex_save;
13232   rex_used = rex_used_save;
13233 }
13234
13235 /* SSE5 instructions that have 3 arguments, and are encoded as:
13236    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>    (or)
13237    0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13238
13239    The DREX field has 1 bit (0x8) to determine how the arguments are
13240    laid out. The destination register is encoded in the DREX byte.
13241    No REX prefix is used for these instructions, since the DREX field
13242    contains the 3 extension bits provided by the REX prefix.  */
13243
13244 static void
13245 OP_DREX3 (int flag_bytemode, int sizeflag)
13246 {
13247   unsigned int drex_byte;
13248   unsigned int regs[3];
13249   unsigned int modrm_regmem;
13250   unsigned int modrm_reg;
13251   unsigned int drex_reg;
13252   int bytemode;
13253   int rex_save = rex;
13254   int rex_used_save = rex_used;
13255   int has_sib = 0;
13256   int oc0;
13257   int i;
13258
13259   bytemode = flag_bytemode & ~ DREX_MASK;
13260
13261   for (i = 0; i < 3; i++)
13262     regs[i] = DREX_REG_UNKNOWN;
13263
13264   /* Determine if we have a SIB byte in addition to MODRM before the
13265      DREX byte.  */
13266   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13267       && (modrm.mod != 3)
13268       && (modrm.rm == 4))
13269     has_sib = 1;
13270
13271   /* Get the DREX byte.  */
13272   FETCH_DATA (the_info, codep + 2 + has_sib);
13273   drex_byte = codep[has_sib+1];
13274   drex_reg = DREX_XMM (drex_byte);
13275   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13276
13277   /* Is OC0 legal?  If not, hardwire oc0 == 0 */
13278   oc0 = DREX_OC0 (drex_byte);
13279   if ((flag_bytemode & DREX_NO_OC0) && oc0)
13280     BadOp ();
13281
13282   if (modrm.mod == 3)
13283     {
13284       /* regmem == register */
13285       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13286       rex = rex_used = 0;
13287       /* skip modrm/drex since we don't call OP_E_extended.  */
13288       codep += 2;
13289     }
13290   else
13291     {
13292       /* regmem == memory, fill in appropriate REX bits.  */
13293       modrm_regmem = DREX_REG_MEMORY;
13294       rex = drex_byte & (REX_B | REX_X | REX_R);
13295       if (rex)
13296         rex |= REX_OPCODE;
13297       rex_used = rex;
13298     }
13299
13300   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13301      order.  */
13302   switch (oc0)
13303     {
13304     default:
13305       BadOp ();
13306       return;
13307
13308     case 0:
13309       regs[0] = modrm_regmem;
13310       regs[1] = modrm_reg;
13311       regs[2] = drex_reg;
13312       break;
13313
13314     case 1:
13315       regs[0] = modrm_reg;
13316       regs[1] = modrm_regmem;
13317       regs[2] = drex_reg;
13318       break;
13319     }
13320
13321   /* Print out the arguments.  */
13322   for (i = 0; i < 3; i++)
13323     {
13324       int j = (intel_syntax) ? 2 - i : i;
13325       if (i > 0)
13326         {
13327           *obufp++ = ',';
13328           *obufp = '\0';
13329         }
13330
13331       print_drex_arg (regs[j], bytemode, sizeflag);
13332     }
13333
13334   rex = rex_save;
13335   rex_used = rex_used_save;
13336 }
13337
13338 /* Emit a floating point comparison for comp<xx> instructions.  */
13339
13340 static void
13341 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13342               int sizeflag ATTRIBUTE_UNUSED)
13343 {
13344   unsigned char byte;
13345
13346   static const char *const cmp_test[] = {
13347     "eq",
13348     "lt",
13349     "le",
13350     "unord",
13351     "ne",
13352     "nlt",
13353     "nle",
13354     "ord",
13355     "ueq",
13356     "ult",
13357     "ule",
13358     "false",
13359     "une",
13360     "unlt",
13361     "unle",
13362     "true"
13363   };
13364
13365   FETCH_DATA (the_info, codep + 1);
13366   byte = *codep & 0xff;
13367
13368   if (byte >= ARRAY_SIZE (cmp_test)
13369       || obuf[0] != 'c'
13370       || obuf[1] != 'o'
13371       || obuf[2] != 'm')
13372     {
13373       /* The instruction isn't one we know about, so just append the
13374          extension byte as a numeric value.  */
13375       OP_I (b_mode, 0);
13376     }
13377
13378   else
13379     {
13380       sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13381       mnemonicendp = stpcpy (obuf, scratchbuf);
13382       codep++;
13383     }
13384 }
13385
13386 /* Emit an integer point comparison for pcom<xx> instructions,
13387    rewriting the instruction to have the test inside of it.  */
13388
13389 static void
13390 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13391               int sizeflag ATTRIBUTE_UNUSED)
13392 {
13393   unsigned char byte;
13394
13395   static const char *const cmp_test[] = {
13396     "lt",
13397     "le",
13398     "gt",
13399     "ge",
13400     "eq",
13401     "ne",
13402     "false",
13403     "true"
13404   };
13405
13406   FETCH_DATA (the_info, codep + 1);
13407   byte = *codep & 0xff;
13408
13409   if (byte >= ARRAY_SIZE (cmp_test)
13410       || obuf[0] != 'p'
13411       || obuf[1] != 'c'
13412       || obuf[2] != 'o'
13413       || obuf[3] != 'm')
13414     {
13415       /* The instruction isn't one we know about, so just print the
13416          comparison test byte as a numeric value.  */
13417       OP_I (b_mode, 0);
13418     }
13419
13420   else
13421     {
13422       sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13423       mnemonicendp = stpcpy (obuf, scratchbuf);
13424       codep++;
13425     }
13426 }
13427
13428 /* Display the destination register operand for instructions with
13429    VEX. */
13430
13431 static void
13432 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13433 {
13434   if (!need_vex)
13435     abort ();
13436
13437   if (!need_vex_reg)
13438     return;
13439
13440   switch (vex.length)
13441     {
13442     case 128:
13443       switch (bytemode)
13444         {
13445         case vex_mode:
13446         case vex128_mode:
13447           break;
13448         default:
13449           abort ();
13450           return;
13451         }
13452
13453       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13454       break;
13455     case 256:
13456       switch (bytemode)
13457         {
13458         case vex_mode:
13459         case vex256_mode:
13460           break;
13461         default:
13462           abort ();
13463           return;
13464         }
13465
13466       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13467       break;
13468     default:
13469       abort ();
13470       break;
13471     }
13472   oappend (scratchbuf + intel_syntax);
13473 }
13474
13475 static void
13476 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13477 {
13478   int reg;
13479   FETCH_DATA (the_info, codep + 1);
13480   reg = *codep++;
13481
13482   if (bytemode != x_mode)
13483     abort ();
13484
13485   if (reg & 0xf)
13486       BadOp ();
13487
13488   reg >>= 4;
13489   if (reg > 7 && address_mode != mode_64bit)
13490     BadOp ();
13491
13492   switch (vex.length)
13493     {
13494     case 128:
13495       sprintf (scratchbuf, "%%xmm%d", reg);
13496       break;
13497     case 256:
13498       sprintf (scratchbuf, "%%ymm%d", reg);
13499       break;
13500     default:
13501       abort ();
13502     }
13503   oappend (scratchbuf + intel_syntax);
13504 }
13505
13506 static void
13507 OP_EX_Vex (int bytemode, int sizeflag)
13508 {
13509   if (modrm.mod != 3)
13510     {
13511       if (vex.register_specifier != 0)
13512         BadOp ();
13513       need_vex_reg = 0;
13514     }
13515   OP_EX (bytemode, sizeflag);
13516 }
13517
13518 static void
13519 OP_XMM_Vex (int bytemode, int sizeflag)
13520 {
13521   if (modrm.mod != 3)
13522     {
13523       if (vex.register_specifier != 0)
13524         BadOp ();
13525       need_vex_reg = 0;
13526     }
13527   OP_XMM (bytemode, sizeflag);
13528 }
13529
13530 static void
13531 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13532 {
13533   switch (vex.length)
13534     {
13535     case 128:
13536       mnemonicendp = stpcpy (obuf, "vzeroupper");
13537       break;
13538     case 256:
13539       mnemonicendp = stpcpy (obuf, "vzeroall");
13540       break;
13541     default:
13542       abort ();
13543     }
13544 }
13545
13546 static struct op vex_cmp_op[] =
13547 {
13548   { STRING_COMMA_LEN ("eq") },
13549   { STRING_COMMA_LEN ("lt") },
13550   { STRING_COMMA_LEN ("le") },
13551   { STRING_COMMA_LEN ("unord") },
13552   { STRING_COMMA_LEN ("neq") },
13553   { STRING_COMMA_LEN ("nlt") },
13554   { STRING_COMMA_LEN ("nle") },
13555   { STRING_COMMA_LEN ("ord") },
13556   { STRING_COMMA_LEN ("eq_uq") },
13557   { STRING_COMMA_LEN ("nge") },
13558   { STRING_COMMA_LEN ("ngt") },
13559   { STRING_COMMA_LEN ("false") },
13560   { STRING_COMMA_LEN ("neq_oq") },
13561   { STRING_COMMA_LEN ("ge") },
13562   { STRING_COMMA_LEN ("gt") },
13563   { STRING_COMMA_LEN ("true") },
13564   { STRING_COMMA_LEN ("eq_os") },
13565   { STRING_COMMA_LEN ("lt_oq") },
13566   { STRING_COMMA_LEN ("le_oq") },
13567   { STRING_COMMA_LEN ("unord_s") },
13568   { STRING_COMMA_LEN ("neq_us") },
13569   { STRING_COMMA_LEN ("nlt_uq") },
13570   { STRING_COMMA_LEN ("nle_uq") },
13571   { STRING_COMMA_LEN ("ord_s") },
13572   { STRING_COMMA_LEN ("eq_us") },
13573   { STRING_COMMA_LEN ("nge_uq") },
13574   { STRING_COMMA_LEN ("ngt_uq") },
13575   { STRING_COMMA_LEN ("false_os") },
13576   { STRING_COMMA_LEN ("neq_os") },
13577   { STRING_COMMA_LEN ("ge_oq") },
13578   { STRING_COMMA_LEN ("gt_oq") },
13579   { STRING_COMMA_LEN ("true_us") },
13580 };
13581
13582 static void
13583 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13584 {
13585   unsigned int cmp_type;
13586
13587   FETCH_DATA (the_info, codep + 1);
13588   cmp_type = *codep++ & 0xff;
13589   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13590     {
13591       char suffix [3];
13592       char *p = mnemonicendp - 2;
13593       suffix[0] = p[0];
13594       suffix[1] = p[1];
13595       suffix[2] = '\0';
13596       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13597       mnemonicendp += vex_cmp_op[cmp_type].len;
13598     }
13599   else
13600     {
13601       /* We have a reserved extension byte.  Output it directly.  */
13602       scratchbuf[0] = '$';
13603       print_operand_value (scratchbuf + 1, 1, cmp_type);
13604       oappend (scratchbuf + intel_syntax);
13605       scratchbuf[0] = '\0';
13606     }
13607 }
13608
13609 static const struct op pclmul_op[] =
13610 {
13611   { STRING_COMMA_LEN ("lql") },
13612   { STRING_COMMA_LEN ("hql") },
13613   { STRING_COMMA_LEN ("lqh") },
13614   { STRING_COMMA_LEN ("hqh") }
13615 };
13616
13617 static void
13618 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13619               int sizeflag ATTRIBUTE_UNUSED)
13620 {
13621   unsigned int pclmul_type;
13622
13623   FETCH_DATA (the_info, codep + 1);
13624   pclmul_type = *codep++ & 0xff;
13625   switch (pclmul_type)
13626     {
13627     case 0x10:
13628       pclmul_type = 2;
13629       break;
13630     case 0x11:
13631       pclmul_type = 3;
13632       break;
13633     default:
13634       break;
13635     }
13636   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13637     {
13638       char suffix [4];
13639       char *p = mnemonicendp - 3;
13640       suffix[0] = p[0];
13641       suffix[1] = p[1];
13642       suffix[2] = p[2];
13643       suffix[3] = '\0';
13644       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13645       mnemonicendp += pclmul_op[pclmul_type].len;
13646     }
13647   else
13648     {
13649       /* We have a reserved extension byte.  Output it directly.  */
13650       scratchbuf[0] = '$';
13651       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13652       oappend (scratchbuf + intel_syntax);
13653       scratchbuf[0] = '\0';
13654     }
13655 }
13656
13657 static void
13658 MOVBE_Fixup (int bytemode, int sizeflag)
13659 {
13660   /* Add proper suffix to "movbe".  */
13661   char *p = mnemonicendp;
13662
13663   switch (bytemode)
13664     {
13665     case v_mode:
13666       if (intel_syntax)
13667         goto skip;
13668
13669       USED_REX (REX_W);
13670       if (sizeflag & SUFFIX_ALWAYS)
13671         {
13672           if (rex & REX_W)
13673             *p++ = 'q';
13674           else if (sizeflag & DFLAG)
13675             *p++ = 'l';
13676           else
13677             *p++ = 'w';
13678         }
13679       used_prefixes |= (prefixes & PREFIX_DATA);
13680       break;
13681     default:
13682       oappend (INTERNAL_DISASSEMBLER_ERROR);
13683       break;
13684     }
13685   mnemonicendp = p;
13686   *p = '\0';
13687
13688 skip:
13689   OP_M (bytemode, sizeflag);
13690 }