1 2005-02-07 Jim Blandy <jimb@redhat.com>
3 * Makefile.am (CGEN): Load guile.scm before calling the main
5 * Makefile.in: Regenerated.
6 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
7 Simply pass the cgen-opc.scm path to ${cgen} as its first
8 argument; ${cgen} itself now contains the '-s', or whatever is
9 appropriate for the Scheme being used.
11 2005-01-31 Andrew Cagney <cagney@gnu.org>
13 * configure: Regenerate to track ../gettext.m4.
15 2005-01-31 Jan Beulich <jbeulich@novell.com>
17 * ia64-gen.c (NELEMS): Define.
18 (shrink): Generate alias with missing second predicate register when
19 opcode has two outputs and these are both predicates.
20 * ia64-opc-i.c (FULL17): Define.
21 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
22 here to generate output template.
23 (TBITCM, TNATCM): Undefine after use.
24 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
25 first input. Add ld16 aliases without ar.csd as second output. Add
26 st16 aliases without ar.csd as second input. Add cmpxchg aliases
27 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
28 ar.ccv as third/fourth inputs. Consolidate through...
29 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
30 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
31 * ia64-asmtab.c: Regenerate.
33 2005-01-27 Andrew Cagney <cagney@gnu.org>
35 * configure: Regenerate to track ../gettext.m4 change.
37 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
39 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
41 * frv-desc.c: Rebuilt.
42 * frv-desc.h: Rebuilt.
44 * frv-ibld.c: Rebuilt.
48 2005-01-24 Andrew Cagney <cagney@gnu.org>
50 * configure: Regenerate, ../gettext.m4 was updated.
52 2005-01-21 Fred Fish <fnf@specifixinc.com>
54 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
55 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
56 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
59 2005-01-20 Alan Modra <amodra@bigpond.net.au>
61 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
63 2005-01-19 Fred Fish <fnf@specifixinc.com>
65 * mips-dis.c (no_aliases): New disassembly option flag.
66 (set_default_mips_dis_options): Init no_aliases to zero.
67 (parse_mips_dis_option): Handle no-aliases option.
68 (print_insn_mips): Ignore table entries that are aliases
70 (print_insn_mips16): Ditto.
71 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
72 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
73 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
74 * mips16-opc.c (mips16_opcodes): Ditto.
76 2005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
78 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
79 (inheritance diagram): Add missing edge.
80 (arch_sh1_up): Rename arch_sh_up to match external name to make life
81 easier for the testsuite.
82 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
83 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
84 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
85 arch_sh2a_or_sh4_up child.
86 (sh_table): Do renaming as above.
87 Correct comment for ldc.l for gas testsuite to read.
88 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
89 Correct comments for movy.w and movy.l for gas testsuite to read.
90 Correct comments for fmov.d and fmov.s for gas testsuite to read.
92 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
94 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
96 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
98 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
100 2005-01-10 Andreas Schwab <schwab@suse.de>
102 * disassemble.c (disassemble_init_for_target) <case
103 bfd_arch_ia64>: Set skip_zeroes to 16.
104 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
106 2004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
108 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
110 2004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
112 * avr-dis.c: Prettyprint. Added printing of symbol names in all
113 memory references. Convert avr_operand() to C90 formatting.
115 2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
117 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
119 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
121 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
122 (no_op_insn): Initialize array with instructions that have no
124 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
126 2004-11-29 Richard Earnshaw <rearnsha@arm.com>
128 * arm-dis.c: Correct top-level comment.
130 2004-11-27 Richard Earnshaw <rearnsha@arm.com>
132 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
133 architecuture defining the insn.
134 (arm_opcodes, thumb_opcodes): Delete. Move to ...
135 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
137 Also include opcode/arm.h.
138 * Makefile.am (arm-dis.lo): Update dependency list.
139 * Makefile.in: Regenerate.
141 2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
143 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
144 reflect the change to the short immediate syntax.
146 2004-11-19 Alan Modra <amodra@bigpond.net.au>
148 * or32-opc.c (debug): Warning fix.
149 * po/POTFILES.in: Regenerate.
151 * maxq-dis.c: Formatting.
152 (print_insn): Warning fix.
154 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
156 * arm-dis.c (WORD_ADDRESS): Define.
157 (print_insn): Use it. Correct big-endian end-of-section handling.
159 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
160 Vineet Sharma <vineets@noida.hcltech.com>
162 * maxq-dis.c: New file.
163 * disassemble.c (ARCH_maxq): Define.
164 (disassembler): Add 'print_insn_maxq_little' for handling maxq
166 * configure.in: Add case for bfd_maxq_arch.
167 * configure: Regenerate.
168 * Makefile.am: Add support for maxq-dis.c
169 * Makefile.in: Regenerate.
170 * aclocal.m4: Regenerate.
172 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
174 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
176 * crx-dis.c: Likewise.
178 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
180 Generally, handle CRISv32.
181 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
182 (struct cris_disasm_data): New type.
183 (format_reg, format_hex, cris_constraint, print_flags)
184 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
186 (format_sup_reg, print_insn_crisv32_with_register_prefix)
187 (print_insn_crisv32_without_register_prefix)
188 (print_insn_crisv10_v32_with_register_prefix)
189 (print_insn_crisv10_v32_without_register_prefix)
190 (cris_parse_disassembler_options): New functions.
191 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
192 parameter. All callers changed.
193 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
195 (cris_constraint) <case 'Y', 'U'>: New cases.
196 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
198 (print_with_operands) <case 'Y'>: New case.
199 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
200 <case 'N', 'Y', 'Q'>: New cases.
201 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
202 (print_insn_cris_with_register_prefix)
203 (print_insn_cris_without_register_prefix): Call
204 cris_parse_disassembler_options.
205 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
206 for CRISv32 and the size of immediate operands. New v32-only
207 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
208 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
209 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
210 Change brp to be v3..v10.
211 (cris_support_regs): New vector.
212 (cris_opcodes): Update head comment. New format characters '[',
213 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
214 Add new opcodes for v32 and adjust existing opcodes to accommodate
215 differences to earlier variants.
216 (cris_cond15s): New vector.
218 2004-11-04 Jan Beulich <jbeulich@novell.com>
220 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
222 (Mp): Use f_mode rather than none at all.
223 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
224 replaces what previously was x_mode; x_mode now means 128-bit SSE
226 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
227 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
228 pinsrw's second operand is Edqw.
229 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
230 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
231 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
232 mode when an operand size override is present or always suffixing.
233 More instructions will need to be added to this group.
234 (putop): Handle new macro chars 'C' (short/long suffix selector),
235 'I' (Intel mode override for following macro char), and 'J' (for
236 adding the 'l' prefix to far branches in AT&T mode). When an
237 alternative was specified in the template, honor macro character when
238 specified for Intel mode.
239 (OP_E): Handle new *_mode values. Correct pointer specifications for
240 memory operands. Consolidate output of index register.
241 (OP_G): Handle new *_mode values.
242 (OP_I): Handle const_1_mode.
243 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
244 respective opcode prefix bits have been consumed.
245 (OP_EM, OP_EX): Provide some default handling for generating pointer
248 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
250 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
253 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
255 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
256 (getregliststring): Support HI/LO and user registers.
257 * crx-opc.c (crx_instruction): Update data structure according to the
258 rearrangement done in CRX opcode header file.
259 (crx_regtab): Likewise.
260 (crx_optab): Likewise.
261 (crx_instruction): Reorder load/stor instructions, remove unsupported
263 support new Co-Processor instruction 'cpi'.
265 2004-10-27 Nick Clifton <nickc@redhat.com>
267 * opcodes/iq2000-asm.c: Regenerate.
268 * opcodes/iq2000-desc.c: Regenerate.
269 * opcodes/iq2000-desc.h: Regenerate.
270 * opcodes/iq2000-dis.c: Regenerate.
271 * opcodes/iq2000-ibld.c: Regenerate.
272 * opcodes/iq2000-opc.c: Regenerate.
273 * opcodes/iq2000-opc.h: Regenerate.
275 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
277 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
278 us4, us5 (respectively).
279 Remove unsupported 'popa' instruction.
280 Reverse operands order in store co-processor instructions.
282 2004-10-15 Alan Modra <amodra@bigpond.net.au>
284 * Makefile.am: Run "make dep-am"
285 * Makefile.in: Regenerate.
287 2004-10-12 Bob Wilson <bob.wilson@acm.org>
289 * xtensa-dis.c: Use ISO C90 formatting.
291 2004-10-09 Alan Modra <amodra@bigpond.net.au>
293 * ppc-opc.c: Revert 2004-09-09 change.
295 2004-10-07 Bob Wilson <bob.wilson@acm.org>
297 * xtensa-dis.c (state_names): Delete.
298 (fetch_data): Use xtensa_isa_maxlength.
299 (print_xtensa_operand): Replace operand parameter with opcode/operand
300 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
301 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
302 instruction bundles. Use xmalloc instead of malloc.
304 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
306 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
309 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
311 * crx-opc.c (crx_instruction): Support Co-processor insns.
312 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
313 (getregliststring): Change function to use the above enum.
314 (print_arg): Handle CO-Processor insns.
315 (crx_cinvs): Add 'b' option to invalidate the branch-target
318 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
320 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
321 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
322 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
323 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
324 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
326 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
328 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
331 2004-09-30 Paul Brook <paul@codesourcery.com>
333 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
334 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
336 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
338 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
339 (CONFIG_STATUS_DEPENDENCIES): New.
341 (config.status): Likewise.
342 * Makefile.in: Regenerated.
344 2004-09-17 Alan Modra <amodra@bigpond.net.au>
346 * Makefile.am: Run "make dep-am".
347 * Makefile.in: Regenerate.
348 * aclocal.m4: Regenerate.
349 * configure: Regenerate.
350 * po/POTFILES.in: Regenerate.
351 * po/opcodes.pot: Regenerate.
353 2004-09-11 Andreas Schwab <schwab@suse.de>
355 * configure: Rebuild.
357 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
359 * ppc-opc.c (L): Make this field not optional.
361 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
363 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
364 Fix parameter to 'm[t|f]csr' insns.
366 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
368 * configure.in: Autoupdate to autoconf 2.59.
369 * aclocal.m4: Rebuild with aclocal 1.4p6.
370 * configure: Rebuild with autoconf 2.59.
371 * Makefile.in: Rebuild with automake 1.4p6 (picking up
372 bfd changes for autoconf 2.59 on the way).
373 * config.in: Rebuild with autoheader 2.59.
375 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
377 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
379 2004-07-30 Michal Ludvig <mludvig@suse.cz>
381 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
382 (GRPPADLCK2): New define.
383 (twobyte_has_modrm): True for 0xA6.
384 (grps): GRPPADLCK2 for opcode 0xA6.
386 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
388 Introduce SH2a support.
389 * sh-opc.h (arch_sh2a_base): Renumber.
390 (arch_sh2a_nofpu_base): Remove.
391 (arch_sh_base_mask): Adjust.
392 (arch_opann_mask): New.
393 (arch_sh2a, arch_sh2a_nofpu): Adjust.
394 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
395 (sh_table): Adjust whitespace.
396 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
397 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
398 instruction list throughout.
399 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
400 of arch_sh2a in instruction list throughout.
401 (arch_sh2e_up): Accomodate above changes.
402 (arch_sh2_up): Ditto.
403 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
404 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
405 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
406 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
407 * sh-opc.h (arch_sh2a_nofpu): New.
408 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
409 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
411 2004-01-20 DJ Delorie <dj@redhat.com>
412 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
413 2003-12-29 DJ Delorie <dj@redhat.com>
414 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
415 sh_opcode_info, sh_table): Add sh2a support.
416 (arch_op32): New, to tag 32-bit opcodes.
417 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
418 2003-12-02 Michael Snyder <msnyder@redhat.com>
419 * sh-opc.h (arch_sh2a): Add.
420 * sh-dis.c (arch_sh2a): Handle.
421 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
423 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
425 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
427 2004-07-22 Nick Clifton <nickc@redhat.com>
430 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
431 insns - this is done by objdump itself.
432 * h8500-dis.c (print_insn_h8500): Likewise.
434 2004-07-21 Jan Beulich <jbeulich@novell.com>
436 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
437 regardless of address size prefix in effect.
438 (ptr_reg): Size or address registers does not depend on rex64, but
439 on the presence of an address size override.
440 (OP_MMX): Use rex.x only for xmm registers.
441 (OP_EM): Use rex.z only for xmm registers.
443 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
445 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
446 move/branch operations to the bottom so that VR5400 multimedia
447 instructions take precedence in disassembly.
449 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
451 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
452 ISA-specific "break" encoding.
454 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
456 * arm-opc.h: Fix typo in comment.
458 2004-07-11 Andreas Schwab <schwab@suse.de>
460 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
462 2004-07-09 Andreas Schwab <schwab@suse.de>
464 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
466 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
468 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
469 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
470 (crx-dis.lo): New target.
471 (crx-opc.lo): Likewise.
472 * Makefile.in: Regenerate.
473 * configure.in: Handle bfd_crx_arch.
474 * configure: Regenerate.
475 * crx-dis.c: New file.
476 * crx-opc.c: New file.
477 * disassemble.c (ARCH_crx): Define.
478 (disassembler): Handle ARCH_crx.
480 2004-06-29 James E Wilson <wilson@specifixinc.com>
482 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
483 * ia64-asmtab.c: Regnerate.
485 2004-06-28 Alan Modra <amodra@bigpond.net.au>
487 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
488 (extract_fxm): Don't test dialect.
489 (XFXFXM_MASK): Include the power4 bit.
490 (XFXM): Add p4 param.
491 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
493 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
495 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
496 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
498 2004-06-26 Alan Modra <amodra@bigpond.net.au>
500 * ppc-opc.c (BH, XLBH_MASK): Define.
501 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
503 2004-06-24 Alan Modra <amodra@bigpond.net.au>
505 * i386-dis.c (x_mode): Comment.
506 (two_source_ops): File scope.
507 (float_mem): Correct fisttpll and fistpll.
508 (float_mem_mode): New table.
510 (OP_E): Correct intel mode PTR output.
511 (ptr_reg): Use open_char and close_char.
512 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
513 operands. Set two_source_ops.
515 2004-06-15 Alan Modra <amodra@bigpond.net.au>
517 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
518 instead of _raw_size.
520 2004-06-08 Jakub Jelinek <jakub@redhat.com>
522 * ia64-gen.c (in_iclass): Handle more postinc st
524 * ia64-asmtab.c: Rebuilt.
526 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
528 * s390-opc.txt: Correct architecture mask for some opcodes.
529 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
530 in the esa mode as well.
532 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
534 * sh-dis.c (target_arch): Make unsigned.
535 (print_insn_sh): Replace (most of) switch with a call to
536 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
537 * sh-opc.h: Redefine architecture flags values.
538 Add sh3-nommu architecture.
539 Reorganise <arch>_up macros so they make more visual sense.
540 (SH_MERGE_ARCH_SET): Define new macro.
541 (SH_VALID_BASE_ARCH_SET): Likewise.
542 (SH_VALID_MMU_ARCH_SET): Likewise.
543 (SH_VALID_CO_ARCH_SET): Likewise.
544 (SH_VALID_ARCH_SET): Likewise.
545 (SH_MERGE_ARCH_SET_VALID): Likewise.
546 (SH_ARCH_SET_HAS_FPU): Likewise.
547 (SH_ARCH_SET_HAS_DSP): Likewise.
548 (SH_ARCH_UNKNOWN_ARCH): Likewise.
549 (sh_get_arch_from_bfd_mach): Add prototype.
550 (sh_get_arch_up_from_bfd_mach): Likewise.
551 (sh_get_bfd_mach_from_arch_set): Likewise.
552 (sh_merge_bfd_arc): Likewise.
554 2004-05-24 Peter Barada <peter@the-baradas.com>
556 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
557 into new match_insn_m68k function. Loop over canidate
558 matches and select first that completely matches.
559 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
560 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
561 to verify addressing for MAC/EMAC.
562 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
563 reigster halves since 'fpu' and 'spl' look misleading.
564 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
565 * m68k-opc.c: Rearragne mac/emac cases to use longest for
566 first, tighten up match masks.
567 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
568 'size' from special case code in print_insn_m68k to
569 determine decode size of insns.
571 2004-05-19 Alan Modra <amodra@bigpond.net.au>
573 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
574 well as when -mpower4.
576 2004-05-13 Nick Clifton <nickc@redhat.com>
578 * po/fr.po: Updated French translation.
580 2004-05-05 Peter Barada <peter@the-baradas.com>
582 * m68k-dis.c(print_insn_m68k): Add new chips, use core
583 variants in arch_mask. Only set m68881/68851 for 68k chips.
584 * m68k-op.c: Switch from ColdFire chips to core variants.
586 2004-05-05 Alan Modra <amodra@bigpond.net.au>
589 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
591 2004-04-29 Ben Elliston <bje@au.ibm.com>
593 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
594 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
596 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
598 * sh-dis.c (print_insn_sh): Print the value in constant pool
599 as a symbol if it looks like a symbol.
601 2004-04-22 Peter Barada <peter@the-baradas.com>
603 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
604 appropriate ColdFire architectures.
605 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
607 Add EMAC instructions, fix MAC instructions. Remove
608 macmw/macml/msacmw/msacml instructions since mask addressing now
611 2004-04-20 Jakub Jelinek <jakub@redhat.com>
613 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
614 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
615 suffix. Use fmov*x macros, create all 3 fpsize variants in one
616 macro. Adjust all users.
618 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
620 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
623 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
625 * m32r-asm.c: Regenerate.
627 2004-03-29 Stan Shebs <shebs@apple.com>
629 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
632 2004-03-19 Alan Modra <amodra@bigpond.net.au>
634 * aclocal.m4: Regenerate.
635 * config.in: Regenerate.
636 * configure: Regenerate.
637 * po/POTFILES.in: Regenerate.
638 * po/opcodes.pot: Regenerate.
640 2004-03-16 Alan Modra <amodra@bigpond.net.au>
642 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
644 * ppc-opc.c (RA0): Define.
645 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
646 (RAOPT): Rename from RAO. Update all uses.
647 (powerpc_opcodes): Use RA0 as appropriate.
649 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
651 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
653 2004-03-15 Alan Modra <amodra@bigpond.net.au>
655 * sparc-dis.c (print_insn_sparc): Update getword prototype.
657 2004-03-12 Michal Ludvig <mludvig@suse.cz>
659 * i386-dis.c (GRPPLOCK): Delete.
660 (grps): Delete GRPPLOCK entry.
662 2004-03-12 Alan Modra <amodra@bigpond.net.au>
664 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
666 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
668 (dis386): Use NOP_Fixup on "nop".
669 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
670 (twobyte_has_modrm): Set for 0xa7.
671 (padlock_table): Delete. Move to..
672 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
674 (print_insn): Revert PADLOCK_SPECIAL code.
675 (OP_E): Delete sfence, lfence, mfence checks.
677 2004-03-12 Jakub Jelinek <jakub@redhat.com>
679 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
680 (INVLPG_Fixup): New function.
681 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
683 2004-03-12 Michal Ludvig <mludvig@suse.cz>
685 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
686 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
687 (padlock_table): New struct with PadLock instructions.
688 (print_insn): Handle PADLOCK_SPECIAL.
690 2004-03-12 Alan Modra <amodra@bigpond.net.au>
692 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
693 (OP_E): Twiddle clflush to sfence here.
695 2004-03-08 Nick Clifton <nickc@redhat.com>
697 * po/de.po: Updated German translation.
699 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
701 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
702 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
703 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
706 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
708 * frv-asm.c: Regenerate.
709 * frv-desc.c: Regenerate.
710 * frv-desc.h: Regenerate.
711 * frv-dis.c: Regenerate.
712 * frv-ibld.c: Regenerate.
713 * frv-opc.c: Regenerate.
714 * frv-opc.h: Regenerate.
716 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
718 * frv-desc.c, frv-opc.c: Regenerate.
720 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
722 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
724 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
726 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
727 Also correct mistake in the comment.
729 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
731 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
732 ensure that double registers have even numbers.
733 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
734 that reserved instruction 0xfffd does not decode the same
736 * sh-opc.h: Add REG_N_D nibble type and use it whereever
737 REG_N refers to a double register.
738 Add REG_N_B01 nibble type and use it instead of REG_NM
740 Adjust the bit patterns in a few comments.
742 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
744 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
746 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
748 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
750 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
752 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
754 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
756 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
757 mtivor32, mtivor33, mtivor34.
759 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
761 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
763 2004-02-10 Petko Manolov <petkan@nucleusys.com>
765 * arm-opc.h Maverick accumulator register opcode fixes.
767 2004-02-13 Ben Elliston <bje@wasabisystems.com>
769 * m32r-dis.c: Regenerate.
771 2004-01-27 Michael Snyder <msnyder@redhat.com>
773 * sh-opc.h (sh_table): "fsrra", not "fssra".
775 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
777 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
780 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
782 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
784 2004-01-19 Alan Modra <amodra@bigpond.net.au>
786 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
787 1. Don't print scale factor on AT&T mode when index missing.
789 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
791 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
792 when loaded into XR registers.
794 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
796 * frv-desc.h: Regenerate.
797 * frv-desc.c: Regenerate.
798 * frv-opc.c: Regenerate.
800 2004-01-13 Michael Snyder <msnyder@redhat.com>
802 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
804 2004-01-09 Paul Brook <paul@codesourcery.com>
806 * arm-opc.h (arm_opcodes): Move generic mcrr after known
809 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
811 * Makefile.am (libopcodes_la_DEPENDENCIES)
812 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
813 comment about the problem.
814 * Makefile.in: Regenerate.
816 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
818 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
819 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
820 cut&paste errors in shifting/truncating numerical operands.
821 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
822 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
823 (parse_uslo16): Likewise.
824 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
825 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
826 (parse_s12): Likewise.
827 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
828 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
829 (parse_uslo16): Likewise.
830 (parse_uhi16): Parse gothi and gotfuncdeschi.
831 (parse_d12): Parse got12 and gotfuncdesc12.
832 (parse_s12): Likewise.
834 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
836 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
837 instruction which looks similar to an 'rla' instruction.
839 For older changes see ChangeLog-0203
845 version-control: never