opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* SSE support required */
  54 #define CpuSSE          (CpuMMX + 1)
  55 /* SSE2 support required */
  56 #define CpuSSE2         (CpuSSE + 1)
  57 /* 3dnow! support required */
  58 #define Cpu3dnow        (CpuSSE2 + 1)
  59 /* 3dnow! Extensions support required */
  60 #define Cpu3dnowA       (Cpu3dnow + 1)
  61 /* SSE3 support required */
  62 #define CpuSSE3         (Cpu3dnowA + 1)
  63 /* VIA PadLock required */
  64 #define CpuPadLock      (CpuSSE3 + 1)
  65 /* AMD Secure Virtual Machine Ext-s required */
  66 #define CpuSVME         (CpuPadLock + 1)
  67 /* VMX Instructions required */
  68 #define CpuVMX          (CpuSVME + 1)
  69 /* SMX Instructions required */
  70 #define CpuSMX          (CpuVMX + 1)
  71 /* SSSE3 support required */
  72 #define CpuSSSE3        (CpuSMX + 1)
  73 /* SSE4a support required */
  74 #define CpuSSE4a        (CpuSSSE3 + 1)
  75 /* ABM New Instructions required */
  76 #define CpuABM          (CpuSSE4a + 1)
  77 /* SSE4.1 support required */
  78 #define CpuSSE4_1       (CpuABM + 1)
  79 /* SSE4.2 support required */
  80 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  81 /* SSE5 support required */
  82 #define CpuSSE5         (CpuSSE4_2 + 1)
  83 /* AVX support required */
  84 #define CpuAVX          (CpuSSE5 + 1)
  85 /* Xsave/xrstor New Instuctions support required */
  86 #define CpuXsave        (CpuAVX + 1)
  87 /* AES support required */
  88 #define CpuAES          (CpuXsave + 1)
  89 /* PCLMUL support required */
  90 #define CpuPCLMUL       (CpuAES + 1)
  91 /* FMA support required */
  92 #define CpuFMA          (CpuPCLMUL + 1)
  93 /* MOVBE Instuction support required */
  94 #define CpuMovbe        (CpuFMA + 1)
  95 /* EPT Instructions required */
  96 #define CpuEPT          (CpuMovbe + 1)
  97 /* RDTSCP Instuction support required */
  98 #define CpuRdtscp       (CpuEPT + 1)
  99 /* 64bit support available, used by -march= in assembler.  */
 100 #define CpuLM           (CpuRdtscp + 1)
 101 /* 64bit support required  */
 102 #define Cpu64           (CpuLM + 1)
 103 /* Not supported in the 64bit mode  */
 104 #define CpuNo64         (Cpu64 + 1)
 105 /* The last bitfield in i386_cpu_flags.  */
 106 #define CpuMax          CpuNo64
 107
 108 #define CpuNumOfUints \
 109   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 110 #define CpuNumOfBits \
 111   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 112
 113 /* If you get a compiler error for zero width of the unused field,
 114    comment it out.  */
 115 #define CpuUnused       (CpuMax + 1)
 116
 117 /* We can check if an instruction is available with array instead
 118    of bitfield. */
 119 typedef union i386_cpu_flags
 120 {
 121   struct
 122     {
 123       unsigned int cpui186:1;
 124       unsigned int cpui286:1;
 125       unsigned int cpui386:1;
 126       unsigned int cpui486:1;
 127       unsigned int cpui586:1;
 128       unsigned int cpui686:1;
 129       unsigned int cpup4:1;
 130       unsigned int cpuk6:1;
 131       unsigned int cpuk8:1;
 132       unsigned int cpummx:1;
 133       unsigned int cpusse:1;
 134       unsigned int cpusse2:1;
 135       unsigned int cpua3dnow:1;
 136       unsigned int cpua3dnowa:1;
 137       unsigned int cpusse3:1;
 138       unsigned int cpupadlock:1;
 139       unsigned int cpusvme:1;
 140       unsigned int cpuvmx:1;
 141       unsigned int cpusmx:1;
 142       unsigned int cpussse3:1;
 143       unsigned int cpusse4a:1;
 144       unsigned int cpuabm:1;
 145       unsigned int cpusse4_1:1;
 146       unsigned int cpusse4_2:1;
 147       unsigned int cpusse5:1;
 148       unsigned int cpuavx:1;
 149       unsigned int cpuxsave:1;
 150       unsigned int cpuaes:1;
 151       unsigned int cpupclmul:1;
 152       unsigned int cpufma:1;
 153       unsigned int cpumovbe:1;
 154       unsigned int cpuept:1;
 155       unsigned int cpurdtscp:1;
 156       unsigned int cpulm:1;
 157       unsigned int cpu64:1;
 158       unsigned int cpuno64:1;
 159 #ifdef CpuUnused
 160       unsigned int unused:(CpuNumOfBits - CpuUnused);
 161 #endif
 162     } bitfield;
 163   unsigned int array[CpuNumOfUints];
 164 } i386_cpu_flags;
 165
 166 /* Position of opcode_modifier bits.  */
 167
 168 /* has direction bit. */
 169 #define D                       0
 170 /* set if operands can be words or dwords encoded the canonical way */
 171 #define W                       (D + 1)
 172 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 173    operand in encoding.  */
 174 #define S                       (W + 1)
 175 /* insn has a modrm byte. */
 176 #define Modrm                   (S + 1)
 177 /* register is in low 3 bits of opcode */
 178 #define ShortForm               (Modrm + 1)
 179 /* special case for jump insns.  */
 180 #define Jump                    (ShortForm + 1)
 181 /* call and jump */
 182 #define JumpDword               (Jump + 1)
 183 /* loop and jecxz */
 184 #define JumpByte                (JumpDword + 1)
 185 /* special case for intersegment leaps/calls */
 186 #define JumpInterSegment        (JumpByte + 1)
 187 /* FP insn memory format bit, sized by 0x4 */
 188 #define FloatMF                 (JumpInterSegment + 1)
 189 /* src/dest swap for floats. */
 190 #define FloatR                  (FloatMF + 1)
 191 /* has float insn direction bit. */
 192 #define FloatD                  (FloatR + 1)
 193 /* needs size prefix if in 32-bit mode */
 194 #define Size16                  (FloatD + 1)
 195 /* needs size prefix if in 16-bit mode */
 196 #define Size32                  (Size16 + 1)
 197 /* needs size prefix if in 64-bit mode */
 198 #define Size64                  (Size32 + 1)
 199 /* instruction ignores operand size prefix and in Intel mode ignores
 200    mnemonic size suffix check.  */
 201 #define IgnoreSize              (Size64 + 1)
 202 /* default insn size depends on mode */
 203 #define DefaultSize             (IgnoreSize + 1)
 204 /* b suffix on instruction illegal */
 205 #define No_bSuf                 (DefaultSize + 1)
 206 /* w suffix on instruction illegal */
 207 #define No_wSuf                 (No_bSuf + 1)
 208 /* l suffix on instruction illegal */
 209 #define No_lSuf                 (No_wSuf + 1)
 210 /* s suffix on instruction illegal */
 211 #define No_sSuf                 (No_lSuf + 1)
 212 /* q suffix on instruction illegal */
 213 #define No_qSuf                 (No_sSuf + 1)
 214 /* long double suffix on instruction illegal */
 215 #define No_ldSuf                (No_qSuf + 1)
 216 /* instruction needs FWAIT */
 217 #define FWait                   (No_ldSuf + 1)
 218 /* quick test for string instructions */
 219 #define IsString                (FWait + 1)
 220 /* fake an extra reg operand for clr, imul and special register
 221    processing for some instructions.  */
 222 #define RegKludge               (IsString + 1)
 223 /* The first operand must be xmm0 */
 224 #define FirstXmm0               (RegKludge + 1)
 225 /* An implicit xmm0 as the first operand */
 226 #define Implicit1stXmm0         (FirstXmm0 + 1)
 227 /* BYTE is OK in Intel syntax. */
 228 #define ByteOkIntel             (Implicit1stXmm0 + 1)
 229 /* Convert to DWORD */
 230 #define ToDword                 (ByteOkIntel + 1)
 231 /* Convert to QWORD */
 232 #define ToQword                 (ToDword + 1)
 233 /* Address prefix changes operand 0 */
 234 #define AddrPrefixOp0           (ToQword + 1)
 235 /* opcode is a prefix */
 236 #define IsPrefix                (AddrPrefixOp0 + 1)
 237 /* instruction has extension in 8 bit imm */
 238 #define ImmExt                  (IsPrefix + 1)
 239 /* instruction don't need Rex64 prefix.  */
 240 #define NoRex64                 (ImmExt + 1)
 241 /* instruction require Rex64 prefix.  */
 242 #define Rex64                   (NoRex64 + 1)
 243 /* deprecated fp insn, gets a warning */
 244 #define Ugh                     (Rex64 + 1)
 245 #define Drex                    (Ugh + 1)
 246 /* instruction needs DREX with multiple encodings for memory ops */
 247 #define Drexv                   (Drex + 1)
 248 /* special DREX for comparisons */
 249 #define Drexc                   (Drexv + 1)
 250 /* insn has VEX prefix. */
 251 #define Vex                     (Drexc + 1)
 252 /* insn has 256bit VEX prefix. */
 253 #define Vex256                  (Vex + 1)
 254 /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
 255    We use VexNDS on insns with VEX DDS since the register-only source
 256    is the second source register.  */
 257 #define VexNDS                  (Vex256 + 1)
 258 /* insn has VEX NDD. Register destination is encoded in Vex
 259    prefix. */
 260 #define VexNDD                  (VexNDS + 1)
 261 /* insn has VEX W0. */
 262 #define VexW0                   (VexNDD + 1)
 263 /* insn has VEX W1. */
 264 #define VexW1                   (VexW0 + 1)
 265 /* insn has VEX 0x0F opcode prefix. */
 266 #define Vex0F                   (VexW1 + 1)
 267 /* insn has VEX 0x0F38 opcode prefix. */
 268 #define Vex0F38                 (Vex0F + 1)
 269 /* insn has VEX 0x0F3A opcode prefix. */
 270 #define Vex0F3A                 (Vex0F38 + 1)
 271 /* insn has VEX prefix with 3 soures. */
 272 #define Vex3Sources             (Vex0F3A + 1)
 273 /* instruction has VEX 8 bit imm */
 274 #define VexImmExt               (Vex3Sources + 1)
 275 /* SSE to AVX support required */
 276 #define SSE2AVX                 (VexImmExt + 1)
 277 /* No AVX equivalent */
 278 #define NoAVX                   (SSE2AVX + 1)
 279 /* Compatible with old (<= 2.8.1) versions of gcc  */
 280 #define OldGcc                  (NoAVX + 1)
 281 /* AT&T mnemonic.  */
 282 #define ATTMnemonic             (OldGcc + 1)
 283 /* AT&T syntax.  */
 284 #define ATTSyntax               (ATTMnemonic + 1)
 285 /* Intel syntax.  */
 286 #define IntelSyntax             (ATTSyntax + 1)
 287 /* The last bitfield in i386_opcode_modifier.  */
 288 #define Opcode_Modifier_Max     IntelSyntax
 289
 290 typedef struct i386_opcode_modifier
 291 {
 292   unsigned int d:1;
 293   unsigned int w:1;
 294   unsigned int s:1;
 295   unsigned int modrm:1;
 296   unsigned int shortform:1;
 297   unsigned int jump:1;
 298   unsigned int jumpdword:1;
 299   unsigned int jumpbyte:1;
 300   unsigned int jumpintersegment:1;
 301   unsigned int floatmf:1;
 302   unsigned int floatr:1;
 303   unsigned int floatd:1;
 304   unsigned int size16:1;
 305   unsigned int size32:1;
 306   unsigned int size64:1;
 307   unsigned int ignoresize:1;
 308   unsigned int defaultsize:1;
 309   unsigned int no_bsuf:1;
 310   unsigned int no_wsuf:1;
 311   unsigned int no_lsuf:1;
 312   unsigned int no_ssuf:1;
 313   unsigned int no_qsuf:1;
 314   unsigned int no_ldsuf:1;
 315   unsigned int fwait:1;
 316   unsigned int isstring:1;
 317   unsigned int regkludge:1;
 318   unsigned int firstxmm0:1;
 319   unsigned int implicit1stxmm0:1;
 320   unsigned int byteokintel:1;
 321   unsigned int todword:1;
 322   unsigned int toqword:1;
 323   unsigned int addrprefixop0:1;
 324   unsigned int isprefix:1;
 325   unsigned int immext:1;
 326   unsigned int norex64:1;
 327   unsigned int rex64:1;
 328   unsigned int ugh:1;
 329   unsigned int drex:1;
 330   unsigned int drexv:1;
 331   unsigned int drexc:1;
 332   unsigned int vex:1;
 333   unsigned int vex256:1;
 334   unsigned int vexnds:1;
 335   unsigned int vexndd:1;
 336   unsigned int vexw0:1;
 337   unsigned int vexw1:1;
 338   unsigned int vex0f:1;
 339   unsigned int vex0f38:1;
 340   unsigned int vex0f3a:1;
 341   unsigned int vex3sources:1;
 342   unsigned int veximmext:1;
 343   unsigned int sse2avx:1;
 344   unsigned int noavx:1;
 345   unsigned int oldgcc:1;
 346   unsigned int attmnemonic:1;
 347   unsigned int attsyntax:1;
 348   unsigned int intelsyntax:1;
 349 } i386_opcode_modifier;
 350
 351 /* Position of operand_type bits.  */
 352
 353 /* 8bit register */
 354 #define Reg8                    0
 355 /* 16bit register */
 356 #define Reg16                   (Reg8 + 1)
 357 /* 32bit register */
 358 #define Reg32                   (Reg16 + 1)
 359 /* 64bit register */
 360 #define Reg64                   (Reg32 + 1)
 361 /* Floating pointer stack register */
 362 #define FloatReg                (Reg64 + 1)
 363 /* MMX register */
 364 #define RegMMX                  (FloatReg + 1)
 365 /* SSE register */
 366 #define RegXMM                  (RegMMX + 1)
 367 /* AVX registers */
 368 #define RegYMM                  (RegXMM + 1)
 369 /* Control register */
 370 #define Control                 (RegYMM + 1)
 371 /* Debug register */
 372 #define Debug                   (Control + 1)
 373 /* Test register */
 374 #define Test                    (Debug + 1)
 375 /* 2 bit segment register */
 376 #define SReg2                   (Test + 1)
 377 /* 3 bit segment register */
 378 #define SReg3                   (SReg2 + 1)
 379 /* 1 bit immediate */
 380 #define Imm1                    (SReg3 + 1)
 381 /* 8 bit immediate */
 382 #define Imm8                    (Imm1 + 1)
 383 /* 8 bit immediate sign extended */
 384 #define Imm8S                   (Imm8 + 1)
 385 /* 16 bit immediate */
 386 #define Imm16                   (Imm8S + 1)
 387 /* 32 bit immediate */
 388 #define Imm32                   (Imm16 + 1)
 389 /* 32 bit immediate sign extended */
 390 #define Imm32S                  (Imm32 + 1)
 391 /* 64 bit immediate */
 392 #define Imm64                   (Imm32S + 1)
 393 /* 8bit/16bit/32bit displacements are used in different ways,
 394    depending on the instruction.  For jumps, they specify the
 395    size of the PC relative displacement, for instructions with
 396    memory operand, they specify the size of the offset relative
 397    to the base register, and for instructions with memory offset
 398    such as `mov 1234,%al' they specify the size of the offset
 399    relative to the segment base.  */
 400 /* 8 bit displacement */
 401 #define Disp8                   (Imm64 + 1)
 402 /* 16 bit displacement */
 403 #define Disp16                  (Disp8 + 1)
 404 /* 32 bit displacement */
 405 #define Disp32                  (Disp16 + 1)
 406 /* 32 bit signed displacement */
 407 #define Disp32S                 (Disp32 + 1)
 408 /* 64 bit displacement */
 409 #define Disp64                  (Disp32S + 1)
 410 /* Accumulator %al/%ax/%eax/%rax */
 411 #define Acc                     (Disp64 + 1)
 412 /* Floating pointer top stack register %st(0) */
 413 #define FloatAcc                (Acc + 1)
 414 /* Register which can be used for base or index in memory operand.  */
 415 #define BaseIndex               (FloatAcc + 1)
 416 /* Register to hold in/out port addr = dx */
 417 #define InOutPortReg            (BaseIndex + 1)
 418 /* Register to hold shift count = cl */
 419 #define ShiftCount              (InOutPortReg + 1)
 420 /* Absolute address for jump.  */
 421 #define JumpAbsolute            (ShiftCount + 1)
 422 /* String insn operand with fixed es segment */
 423 #define EsSeg                   (JumpAbsolute + 1)
 424 /* RegMem is for instructions with a modrm byte where the register
 425    destination operand should be encoded in the mod and regmem fields.
 426    Normally, it will be encoded in the reg field. We add a RegMem
 427    flag to the destination register operand to indicate that it should
 428    be encoded in the regmem field.  */
 429 #define RegMem                  (EsSeg + 1)
 430 /* Memory.  */
 431 #define Mem                     (RegMem + 1)
 432 /* BYTE memory. */
 433 #define Byte                    (Mem + 1)
 434 /* WORD memory. 2 byte */
 435 #define Word                    (Byte + 1)
 436 /* DWORD memory. 4 byte */
 437 #define Dword                   (Word + 1)
 438 /* FWORD memory. 6 byte */
 439 #define Fword                   (Dword + 1)
 440 /* QWORD memory. 8 byte */
 441 #define Qword                   (Fword + 1)
 442 /* TBYTE memory. 10 byte */
 443 #define Tbyte                   (Qword + 1)
 444 /* XMMWORD memory. */
 445 #define Xmmword                 (Tbyte + 1)
 446 /* YMMWORD memory. */
 447 #define Ymmword                 (Xmmword + 1)
 448 /* Unspecified memory size.  */
 449 #define Unspecified             (Ymmword + 1)
 450 /* Any memory size.  */
 451 #define Anysize                 (Unspecified  + 1)
 452
 453 /* VEX 4 bit immediate */
 454 #define Vex_Imm4                (Anysize + 1)
 455
 456 /* The last bitfield in i386_operand_type.  */
 457 #define OTMax                   Vex_Imm4
 458
 459 #define OTNumOfUints \
 460   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 461 #define OTNumOfBits \
 462   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 463
 464 /* If you get a compiler error for zero width of the unused field,
 465    comment it out.  */
 466 #define OTUnused                (OTMax + 1)
 467
 468 typedef union i386_operand_type
 469 {
 470   struct
 471     {
 472       unsigned int reg8:1;
 473       unsigned int reg16:1;
 474       unsigned int reg32:1;
 475       unsigned int reg64:1;
 476       unsigned int floatreg:1;
 477       unsigned int regmmx:1;
 478       unsigned int regxmm:1;
 479       unsigned int regymm:1;
 480       unsigned int control:1;
 481       unsigned int debug:1;
 482       unsigned int test:1;
 483       unsigned int sreg2:1;
 484       unsigned int sreg3:1;
 485       unsigned int imm1:1;
 486       unsigned int imm8:1;
 487       unsigned int imm8s:1;
 488       unsigned int imm16:1;
 489       unsigned int imm32:1;
 490       unsigned int imm32s:1;
 491       unsigned int imm64:1;
 492       unsigned int disp8:1;
 493       unsigned int disp16:1;
 494       unsigned int disp32:1;
 495       unsigned int disp32s:1;
 496       unsigned int disp64:1;
 497       unsigned int acc:1;
 498       unsigned int floatacc:1;
 499       unsigned int baseindex:1;
 500       unsigned int inoutportreg:1;
 501       unsigned int shiftcount:1;
 502       unsigned int jumpabsolute:1;
 503       unsigned int esseg:1;
 504       unsigned int regmem:1;
 505       unsigned int mem:1;
 506       unsigned int byte:1;
 507       unsigned int word:1;
 508       unsigned int dword:1;
 509       unsigned int fword:1;
 510       unsigned int qword:1;
 511       unsigned int tbyte:1;
 512       unsigned int xmmword:1;
 513       unsigned int ymmword:1;
 514       unsigned int unspecified:1;
 515       unsigned int anysize:1;
 516       unsigned int vex_imm4:1;
 517 #ifdef OTUnused
 518       unsigned int unused:(OTNumOfBits - OTUnused);
 519 #endif
 520     } bitfield;
 521   unsigned int array[OTNumOfUints];
 522 } i386_operand_type;
 523
 524 typedef struct template
 525 {
 526   /* instruction name sans width suffix ("mov" for movl insns) */
 527   char *name;
 528
 529   /* how many operands */
 530   unsigned int operands;
 531
 532   /* base_opcode is the fundamental opcode byte without optional
 533      prefix(es).  */
 534   unsigned int base_opcode;
 535 #define Opcode_D        0x2 /* Direction bit:
 536                                set if Reg --> Regmem;
 537                                unset if Regmem --> Reg. */
 538 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 539 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 540
 541   /* extension_opcode is the 3 bit extension for group <n> insns.
 542      This field is also used to store the 8-bit opcode suffix for the
 543      AMD 3DNow! instructions.
 544      If this template has no extension opcode (the usual case) use None
 545      Instructions with Drex use this to specify 2 bits for OC */
 546   unsigned int extension_opcode;
 547 #define None 0xffff             /* If no extension_opcode is possible.  */
 548
 549   /* Opcode length.  */
 550   unsigned char opcode_length;
 551
 552   /* cpu feature flags */
 553   i386_cpu_flags cpu_flags;
 554
 555   /* the bits in opcode_modifier are used to generate the final opcode from
 556      the base_opcode.  These bits also are used to detect alternate forms of
 557      the same instruction */
 558   i386_opcode_modifier opcode_modifier;
 559
 560   /* operand_types[i] describes the type of operand i.  This is made
 561      by OR'ing together all of the possible type masks.  (e.g.
 562      'operand_types[i] = Reg|Imm' specifies that operand i can be
 563      either a register or an immediate operand.  */
 564   i386_operand_type operand_types[MAX_OPERANDS];
 565 }
 566 template;
 567
 568 extern const template i386_optab[];
 569
 570 /* these are for register name --> number & type hash lookup */
 571 typedef struct
 572 {
 573   char *reg_name;
 574   i386_operand_type reg_type;
 575   unsigned char reg_flags;
 576 #define RegRex      0x1  /* Extended register.  */
 577 #define RegRex64    0x2  /* Extended 8 bit register.  */
 578   unsigned char reg_num;
 579 #define RegRip  ((unsigned char ) ~0)
 580 #define RegEip  (RegRip - 1)
 581 /* EIZ and RIZ are fake index registers.  */
 582 #define RegEiz  (RegEip - 1)
 583 #define RegRiz  (RegEiz - 1)
 584 /* FLAT is a fake segment register (Intel mode).  */
 585 #define RegFlat     ((unsigned char) ~0)
 586   signed char dw2_regnum[2];
 587 #define Dw2Inval (-1)
 588 }
 589 reg_entry;
 590
 591 /* Entries in i386_regtab.  */
 592 #define REGNAM_AL 1
 593 #define REGNAM_AX 25
 594 #define REGNAM_EAX 41
 595
 596 extern const reg_entry i386_regtab[];
 597 extern const unsigned int i386_regtab_size;
 598
 599 typedef struct
 600 {
 601   char *seg_name;
 602   unsigned int seg_prefix;
 603 }
 604 seg_entry;
 605
 606 extern const seg_entry cs;
 607 extern const seg_entry ds;
 608 extern const seg_entry ss;
 609 extern const seg_entry es;
 610 extern const seg_entry fs;
 611 extern const seg_entry gs;