* elf32-spu.c (build_stub): Fix malloc under-allocation.
[binutils.git] / opcodes / microblaze-opcm.h
blob10acacfee29efb442a42a73a4a8006f2cf4a6b27
1 /* microblaze-opcm.h -- Header used in microblaze-opc.h
3 Copyright 2009 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #ifndef MICROBLAZE_OPCM
24 #define MICROBLAZE_OPCM
26 enum microblaze_instr
28 add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu,
29 addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
30 mulh, mulhu, mulhsu,
31 idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
32 ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
33 andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
34 wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd,
35 brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
36 bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
37 imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
38 brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
39 bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
40 sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
41 fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
42 fint, fsqrt,
43 tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
44 eget, ecget, neget, necget, eput, ecput, neput, necput,
45 teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
46 aget, caget, naget, ncaget, aput, caput, naput, ncaput,
47 taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
48 eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
49 teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
50 getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
51 putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
52 egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
53 eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
54 agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
55 aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
56 eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
57 eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
58 invalid_inst
61 enum microblaze_instr_type
63 arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst,
64 return_inst, immediate_inst, special_inst, memory_load_inst,
65 memory_store_inst, barrel_shift_inst, anyware_inst
68 #define INST_WORD_SIZE 4
70 /* Gen purpose regs go from 0 to 31. */
71 /* Mask is reg num - max_reg_num, ie reg_num - 32 in this case. */
73 #define REG_PC_MASK 0x8000
74 #define REG_MSR_MASK 0x8001
75 #define REG_EAR_MASK 0x8003
76 #define REG_ESR_MASK 0x8005
77 #define REG_FSR_MASK 0x8007
78 #define REG_BTR_MASK 0x800b
79 #define REG_EDR_MASK 0x800d
80 #define REG_PVR_MASK 0xa000
82 #define REG_PID_MASK 0x9000
83 #define REG_ZPR_MASK 0x9001
84 #define REG_TLBX_MASK 0x9002
85 #define REG_TLBLO_MASK 0x9003
86 #define REG_TLBHI_MASK 0x9004
87 #define REG_TLBSX_MASK 0x9005
89 #define MIN_REGNUM 0
90 #define MAX_REGNUM 31
92 #define MIN_PVR_REGNUM 0
93 #define MAX_PVR_REGNUM 15
95 #define REG_PC 32 /* PC. */
96 #define REG_MSR 33 /* Machine status reg. */
97 #define REG_EAR 35 /* Exception reg. */
98 #define REG_ESR 37 /* Exception reg. */
99 #define REG_FSR 39 /* FPU Status reg. */
100 #define REG_BTR 43 /* Branch Target reg. */
101 #define REG_EDR 45 /* Exception reg. */
102 #define REG_PVR 40960 /* Program Verification reg. */
104 #define REG_PID 36864 /* MMU: Process ID reg. */
105 #define REG_ZPR 36865 /* MMU: Zone Protect reg. */
106 #define REG_TLBX 36866 /* MMU: TLB Index reg. */
107 #define REG_TLBLO 36867 /* MMU: TLB Low reg. */
108 #define REG_TLBHI 36868 /* MMU: TLB High reg. */
109 #define REG_TLBSX 36869 /* MMU: TLB Search Index reg. */
111 /* Alternate names for gen purpose regs. */
112 #define REG_SP 1 /* stack pointer. */
113 #define REG_ROSDP 2 /* read-only small data pointer. */
114 #define REG_RWSDP 13 /* read-write small data pointer. */
116 /* Assembler Register - Used in Delay Slot Optimization. */
117 #define REG_AS 18
118 #define REG_ZERO 0
120 #define RD_LOW 21 /* Low bit for RD. */
121 #define RA_LOW 16 /* Low bit for RA. */
122 #define RB_LOW 11 /* Low bit for RB. */
123 #define IMM_LOW 0 /* Low bit for immediate. */
125 #define RD_MASK 0x03E00000
126 #define RA_MASK 0x001F0000
127 #define RB_MASK 0x0000F800
128 #define IMM_MASK 0x0000FFFF
130 /* Imm mask for barrel shifts. */
131 #define IMM5_MASK 0x0000001F
133 /* FSL imm mask for get, put instructions. */
134 #define RFSL_MASK 0x000000F
136 /* Imm mask for msrset, msrclr instructions. */
137 #define IMM15_MASK 0x00007FFF
139 #endif /* MICROBLAZE-OPCM */