* elf32-spu.c (build_stub): Fix malloc under-allocation.
[binutils.git] / ld / testsuite / ld-arm / tls-descrelax-be8.d
blob1b2159c37bba0d45044618fa3e6690b745cf6695
1 .*: file format elf32-.*
2 architecture: arm, flags 0x[0-9a-f]+:
3 EXEC_P, HAS_SYMS, D_PAGED
4 start address 0x[0-9a-f]+
6 Disassembly of section .text:
8 00008000 <foo>:
9 8000: e59f0004 ldr r0, \[pc, #4\] ; 800c <foo\+0xc>
10 8004: e79f0000 ldr r0, \[pc, r0\]
11 8008: e320f000 nop \{0\}
12 800c: 00008138 .word 0x00008138
13 8010: e59f0004 ldr r0, \[pc, #4\] ; 801c <foo\+0x1c>
14 8014: e79f0000 ldr r0, \[pc, r0\]
15 8018: e320f000 nop \{0\}
16 801c: 00008128 .word 0x00008128
17 8020: e59f0004 ldr r0, \[pc, #4\] ; 802c <foo\+0x2c>
18 8024: e320f000 nop \{0\}
19 8028: e320f000 nop \{0\}
20 802c: 0000000c .word 0x0000000c
21 8030: e59f0004 ldr r0, \[pc, #4\] ; 803c <foo\+0x3c>
22 8034: e1a00000 nop ; .*
23 8038: e320f000 nop \{0\}
24 803c: 0000000c .word 0x0000000c
25 8040: e59f000c ldr r0, \[pc, #12\] ; 8054 <foo\+0x54>
26 8044: e08f0000 add r0, pc, r0
27 8048: e5901000 ldr r1, \[r0\]
28 804c: e1a00001 mov r0, r1
29 8050: e320f000 nop \{0\}
30 8054: 000080f8 .word 0x000080f8
31 8058: e59f000c ldr r0, \[pc, #12\] ; 806c <foo\+0x6c>
32 805c: e08f0000 add r0, pc, r0
33 8060: e5901000 ldr r1, \[r0\]
34 8064: e1a00001 mov r0, r1
35 8068: e320f000 nop \{0\}
36 806c: 000080e0 .word 0x000080e0
37 8070: e59f000c ldr r0, \[pc, #12\] ; 8084 <foo\+0x84>
38 8074: e320f000 nop \{0\}
39 8078: e320f000 nop \{0\}
40 807c: e320f000 nop \{0\}
41 8080: e320f000 nop \{0\}
42 8084: 0000000c .word 0x0000000c
43 8088: e59f000c ldr r0, \[pc, #12\] ; 809c <foo\+0x9c>
44 808c: e1a00000 nop ; .*
45 8090: e1a00000 nop ; .*
46 8094: e1a00000 nop ; .*
47 8098: e320f000 nop \{0\}
48 809c: 0000000c .word 0x0000000c
50 000080a0 <bar>:
51 80a0: 4801 ldr r0, \[pc, #4\] ; \(80a8 <bar\+0x8>\)
52 80a2: 4478 add r0, pc
53 80a4: 6800 ldr r0, \[r0, #0\]
54 80a6: 46c0 nop ; .*
55 80a8: 0000809e .word 0x0000809e
56 80ac: 4801 ldr r0, \[pc, #4\] ; \(80b4 <bar\+0x14>\)
57 80ae: 4478 add r0, pc
58 80b0: 6800 ldr r0, \[r0, #0\]
59 80b2: 46c0 nop ; \(mov r8, r8\)
60 80b4: 00008092 .word 0x00008092
61 80b8: 4801 ldr r0, \[pc, #4\] ; \(80c0 <bar\+0x20>\)
62 80ba: 4478 add r0, pc
63 80bc: 6800 ldr r0, \[r0, #0\]
64 80be: 46c0 nop ; \(mov r8, r8\)
65 80c0: 0000808a .word 0x0000808a
66 80c4: 4801 ldr r0, \[pc, #4\] ; \(80cc <bar\+0x2c>\)
67 80c6: 46c0 nop ; \(mov r8, r8\)
68 80c8: 46c0 nop ; \(mov r8, r8\)
69 80ca: bf00 nop
70 80cc: 0000000c .word 0x0000000c
71 80d0: 4801 ldr r0, \[pc, #4\] ; \(80d8 <bar\+0x38>\)
72 80d2: (f3af 8000)|(bf00 ) nop(.w)?
73 #...
74 80d6: 46c0 nop ; \(mov r8, r8\)
75 80d8: 0000000c .word 0x0000000c
76 80dc: 4801 ldr r0, \[pc, #4\] ; \(80e4 <bar\+0x44>\)
77 80de: (f3af 8000)|(bf00 ) nop(.w)?
78 #...
79 80e2: 46c0 nop ; \(mov r8, r8\)
80 80e4: 00000014 .word 0x00000014
81 80e8: 4802 ldr r0, \[pc, #8\] ; \(80f4 <bar\+0x54>\)
82 80ea: 4478 add r0, pc
83 80ec: 6801 ldr r1, \[r0, #0\]
84 80ee: 1c08 adds r0, r1, #0
85 80f0: 46c0 nop ; \(mov r8, r8\)
86 80f2: bf00 nop
87 80f4: 00008056 .word 0x00008056
88 80f8: 4802 ldr r0, \[pc, #8\] ; \(8104 <bar\+0x64>\)
89 80fa: 4478 add r0, pc
90 80fc: 6801 ldr r1, \[r0, #0\]
91 80fe: 4608 mov r0, r1
92 8100: 46c0 nop ; \(mov r8, r8\)
93 8102: bf00 nop
94 8104: 00008046 .word 0x00008046
95 8108: 4802 ldr r0, \[pc, #8\] ; \(8114 <bar\+0x74>\)
96 810a: 46c0 nop ; \(mov r8, r8\)
97 810c: 46c0 nop ; \(mov r8, r8\)
98 810e: 46c0 nop ; \(mov r8, r8\)
99 8110: 46c0 nop ; \(mov r8, r8\)
100 8112: bf00 nop
101 8114: 0000000c .word 0x0000000c
102 8118: 4802 ldr r0, \[pc, #8\] ; \(8124 <bar\+0x84>\)
103 811a: 46c0 nop ; \(mov r8, r8\)
104 811c: 46c0 nop ; \(mov r8, r8\)
105 811e: 46c0 nop ; \(mov r8, r8\)
106 8120: 46c0 nop ; \(mov r8, r8\)
107 8122: bf00 nop
108 8124: 0000000c .word 0x0000000c