1 @ VFP Instructions for D variants
(Double precision
)
2 @ Same as vfp1.s
, but for Thumb-
2
8 @ First we test the basic syntax
and bit patterns of the opcodes.
9 @ Most of these tests deliberatly use d0
/r0 to avoid setting
10 @ any more bits than necessary.
12 @ Comparison operations
19 @ Monadic data operations
26 @ Dyadic data operations
38 @ Load
/store operations
43 @ Load
/store multiple operations
59 @ Conversion operations
72 @ ARM from VFP operations
77 @ VFP From ARM operations
82 @ Now we test that the register fields are updated correctly for
83 @ each class of instruction.
85 @ Single register operations
(compare-zero
):
91 @ Two register comparison operations
:
101 @ Two register data operations
(monadic
)
111 @ Three register data operations
(dyadic
)
124 @ Conversion operations
139 @ Move to VFP from ARM
152 @ Move to ARM from VFP
165 @ Load
/store operations
171 fldd d0
, [r0, #-1020]
175 fstd d12
, [r12, #804]
177 @ Load
/store multiple operations
187 fldmiad
r0, {d14-d15
}
191 @ Check that we assemble all the register names correctly
210 @ Now we check the placement of the conditional execution substring.
211 @ On VFP this is always at the end of the instruction.
213 @ Comparison operations
221 @ Monadic data operations
229 @ Dyadic data operations
244 @ Load
/store operations
249 @ Load
/store multiple operations
264 fstmeadeq
r10!, {d12
}
265 fstmdbdeq
r11!, {d11
}
266 fstmfddeq
r12!, {d10
}
268 @ Conversion operations
283 @ ARM from VFP operations
289 @ VFP From ARM operations
294 # Add three nop instructions to ensure that the
295 # output is 32-byte aligned as required for arm-aout.