gas/testsuite/gas/arm/vfp1_t2.s

   1 @ VFP Instructions for D variants (Double precision)
   2 @ Same as vfp1.s, but for Thumb-2
   3         .syntax unified
   4         .thumb
   5         .text
   6         .global F
   7 F:
   8         @ First we test the basic syntax and bit patterns of the opcodes.
   9         @ Most of these tests deliberatly use d0/r0 to avoid setting
  10         @ any more bits than necessary.
  11
  12         @ Comparison operations
  13
  14         fcmped  d0, d0
  15         fcmpezd d0
  16         fcmpd   d0, d0
  17         fcmpzd  d0
  18
  19         @ Monadic data operations
  20
  21         fabsd   d0, d0
  22         fcpyd   d0, d0
  23         fnegd   d0, d0
  24         fsqrtd  d0, d0
  25
  26         @ Dyadic data operations
  27
  28         faddd   d0, d0, d0
  29         fdivd   d0, d0, d0
  30         fmacd   d0, d0, d0
  31         fmscd   d0, d0, d0
  32         fmuld   d0, d0, d0
  33         fnmacd  d0, d0, d0
  34         fnmscd  d0, d0, d0
  35         fnmuld  d0, d0, d0
  36         fsubd   d0, d0, d0
  37
  38         @ Load/store operations
  39
  40         fldd    d0, [r0]
  41         fstd    d0, [r0]
  42
  43         @ Load/store multiple operations
  44
  45         fldmiad r0, {d0}
  46         fldmfdd r0, {d0}
  47         fldmiad r0!, {d0}
  48         fldmfdd r0!, {d0}
  49         fldmdbd r0!, {d0}
  50         fldmead r0!, {d0}
  51
  52         fstmiad r0, {d0}
  53         fstmead r0, {d0}
  54         fstmiad r0!, {d0}
  55         fstmead r0!, {d0}
  56         fstmdbd r0!, {d0}
  57         fstmfdd r0!, {d0}
  58
  59         @ Conversion operations
  60
  61         fsitod  d0, s0
  62         fuitod  d0, s0
  63
  64         ftosid  s0, d0
  65         ftosizd s0, d0
  66         ftouid  s0, d0
  67         ftouizd s0, d0
  68
  69         fcvtds  d0, s0
  70         fcvtsd  s0, d0
  71
  72         @ ARM from VFP operations
  73
  74         fmrdh   r0, d0
  75         fmrdl   r0, d0
  76
  77         @ VFP From ARM operations
  78
  79         fmdhr   d0, r0
  80         fmdlr   d0, r0
  81
  82         @ Now we test that the register fields are updated correctly for
  83         @ each class of instruction.
  84
  85         @ Single register operations (compare-zero):
  86
  87         fcmpzd  d1
  88         fcmpzd  d2
  89         fcmpzd  d15
  90
  91         @ Two register comparison operations:
  92
  93         fcmpd   d0, d1
  94         fcmpd   d0, d2
  95         fcmpd   d0, d15
  96         fcmpd   d1, d0
  97         fcmpd   d2, d0
  98         fcmpd   d15, d0
  99         fcmpd   d5, d12
 100
 101         @ Two register data operations (monadic)
 102
 103         fnegd   d0, d1
 104         fnegd   d0, d2
 105         fnegd   d0, d15
 106         fnegd   d1, d0
 107         fnegd   d2, d0
 108         fnegd   d15, d0
 109         fnegd   d12, d5
 110
 111         @ Three register data operations (dyadic)
 112
 113         faddd   d0, d0, d1
 114         faddd   d0, d0, d2
 115         faddd   d0, d0, d15
 116         faddd   d0, d1, d0
 117         faddd   d0, d2, d0
 118         faddd   d0, d15, d0
 119         faddd   d1, d0, d0
 120         faddd   d2, d0, d0
 121         faddd   d15, d0, d0
 122         faddd   d12, d9, d5
 123
 124         @ Conversion operations
 125
 126         fcvtds  d0, s1
 127         fcvtds  d0, s2
 128         fcvtds  d0, s31
 129         fcvtds  d1, s0
 130         fcvtds  d2, s0
 131         fcvtds  d15, s0
 132         fcvtsd  s1, d0
 133         fcvtsd  s2, d0
 134         fcvtsd  s31, d0
 135         fcvtsd  s0, d1
 136         fcvtsd  s0, d2
 137         fcvtsd  s0, d15
 138
 139         @ Move to VFP from ARM
 140
 141         fmrdh   r1, d0
 142         fmrdh   r14, d0
 143         fmrdh   r0, d1
 144         fmrdh   r0, d2
 145         fmrdh   r0, d15
 146         fmrdl   r1, d0
 147         fmrdl   r14, d0
 148         fmrdl   r0, d1
 149         fmrdl   r0, d2
 150         fmrdl   r0, d15
 151
 152         @ Move to ARM from VFP
 153
 154         fmdhr   d0, r1
 155         fmdhr   d0, r14
 156         fmdhr   d1, r0
 157         fmdhr   d2, r0
 158         fmdhr   d15, r0
 159         fmdlr   d0, r1
 160         fmdlr   d0, r14
 161         fmdlr   d1, r0
 162         fmdlr   d2, r0
 163         fmdlr   d15, r0
 164
 165         @ Load/store operations
 166
 167         fldd    d0, [r1]
 168         fldd    d0, [r14]
 169         fldd    d0, [r0, #0]
 170         fldd    d0, [r0, #1020]
 171         fldd    d0, [r0, #-1020]
 172         fldd    d1, [r0]
 173         fldd    d2, [r0]
 174         fldd    d15, [r0]
 175         fstd    d12, [r12, #804]
 176
 177         @ Load/store multiple operations
 178
 179         fldmiad r0, {d1}
 180         fldmiad r0, {d2}
 181         fldmiad r0, {d15}
 182         fldmiad r0, {d0-d1}
 183         fldmiad r0, {d0-d2}
 184         fldmiad r0, {d0-d15}
 185         fldmiad r0, {d1-d15}
 186         fldmiad r0, {d2-d15}
 187         fldmiad r0, {d14-d15}
 188         fldmiad r1, {d0}
 189         fldmiad r14, {d0}
 190
 191         @ Check that we assemble all the register names correctly
 192
 193         fcmpzd  d0
 194         fcmpzd  d1
 195         fcmpzd  d2
 196         fcmpzd  d3
 197         fcmpzd  d4
 198         fcmpzd  d5
 199         fcmpzd  d6
 200         fcmpzd  d7
 201         fcmpzd  d8
 202         fcmpzd  d9
 203         fcmpzd  d10
 204         fcmpzd  d11
 205         fcmpzd  d12
 206         fcmpzd  d13
 207         fcmpzd  d14
 208         fcmpzd  d15
 209
 210         @ Now we check the placement of the conditional execution substring.
 211         @ On VFP this is always at the end of the instruction.
 212
 213         @ Comparison operations
 214
 215         itttt eq
 216         fcmpedeq        d1, d15
 217         fcmpezdeq       d2
 218         fcmpdeq d3, d14
 219         fcmpzdeq        d4
 220
 221         @ Monadic data operations
 222
 223         itttt eq
 224         fabsdeq d5, d13
 225         fcpydeq d6, d12
 226         fnegdeq d7, d11
 227         fsqrtdeq        d8, d10
 228
 229         @ Dyadic data operations
 230
 231         itttt eq
 232         fadddeq d9, d1, d15
 233         fdivdeq d2, d3, d14
 234         fmacdeq d4, d13, d12
 235         fmscdeq d5, d6, d11
 236         itttt eq
 237         fmuldeq d7, d10, d9
 238         fnmacdeq        d8, d9, d10
 239         fnmscdeq        d7, d6, d11
 240         fnmuldeq        d5, d4, d12
 241         ittt eq
 242         fsubdeq d3, d13, d14
 243
 244         @ Load/store operations
 245
 246         flddeq  d2, [r5]
 247         fstdeq  d1, [r12]
 248
 249         @ Load/store multiple operations
 250
 251         itttt eq
 252         fldmiadeq       r1, {d1}
 253         fldmfddeq       r2, {d2}
 254         fldmiadeq       r3!, {d3}
 255         fldmfddeq       r4!, {d4}
 256         itttt eq
 257         fldmdbdeq       r5!, {d5}
 258         fldmeadeq       r6!, {d6}
 259
 260         fstmiadeq       r7, {d15}
 261         fstmeadeq       r8, {d14}
 262         itttt eq
 263         fstmiadeq       r9!, {d13}
 264         fstmeadeq       r10!, {d12}
 265         fstmdbdeq       r11!, {d11}
 266         fstmfddeq       r12!, {d10}
 267
 268         @ Conversion operations
 269
 270         itttt eq
 271         fsitodeq        d15, s1
 272         fuitodeq        d1, s31
 273
 274         ftosideq        s1, d15
 275         ftosizdeq       s31, d2
 276         itttt eq
 277         ftouideq        s15, d2
 278         ftouizdeq       s11, d3
 279
 280         fcvtdseq        d1, s10
 281         fcvtsdeq        s11, d1
 282
 283         @ ARM from VFP operations
 284
 285         itttt eq
 286         fmrdheq r8, d1
 287         fmrdleq r7, d15
 288
 289         @ VFP From ARM operations
 290
 291         fmdhreq d1, r15
 292         fmdlreq d15, r1
 293
 294         # Add three nop instructions to ensure that the
 295         # output is 32-byte aligned as required for arm-aout.
 296         nop
 297         nop
 298         nop