* elf32-spu.c (build_stub): Fix malloc under-allocation.
[binutils.git] / gas / testsuite / gas / arm / ldr-t.d
blob1b50837eac7e1cf07852148781f289f006d0767a
1 # name: ldr - thumb
2 #objdump: -dr --prefix-address --show-raw-insn
4 .*: +file format .*arm.*
6 Disassembly of section [^>]+:
7 0+00 <[^>]+> f8d1 1005 ldr.w r1, \[r1, #5\]
8 0+04 <[^>]+> f852 1f05 ldr.w r1, \[r2, #5\]!
9 0+08 <[^>]+> f8df 1005 ldr.w r1, \[pc, #5\] ; 0+11 <[^>]+0x11>
10 0+0c <[^>]+> f8d1 f005 ldr.w pc, \[r1, #5\]
11 0+10 <[^>]+> f8df f004 ldr.w pc, \[pc, #4\] ; 0+18 <[^>]+0x18>
12 0+14 <[^>]+> bfa2 ittt ge
13 0+16 <[^>]+> 4901 ldrge r1, \[pc, #4\] ; \(0+1c <[^>]+0x1c>\)
14 0+18 <[^>]+> 46c0 nopge ; \(mov r8, r8\)
15 0+1a <[^>]+> 46c0 nopge ; \(mov r8, r8\)
16 0+1c <[^>]+> bfa8 it ge
17 0+1e <[^>]+> f8df f004 ldrge.w pc, \[pc, #4\] ; 0+24 <[^>]+0x24>
18 0+22 <[^>]+> bfa2 ittt ge
19 0+24 <[^>]+> f85f 1ab8 ldrge.w r1, \[pc, #-2744\] ; fffff570 <[^>]+>
20 0+28 <[^>]+> 46c0 nopge ; \(mov r8, r8\)
21 0+2a <[^>]+> 46c0 nopge ; \(mov r8, r8\)
22 0+2c <[^>]+> bfa8 it ge
23 0+2e <[^>]+> f85f fab6 ldrge.w pc, \[pc, #-2742\] ; fffff57a <[^>]+>
24 0+32 <[^>]+> f85f 1ab9 ldr.w r1, \[pc, #-2745\] ; fffff57b <[^>]+>
25 0+36 <[^>]+> f85f fab6 ldr.w pc, \[pc, #-2742\] ; fffff582 <[^>]+>
26 0+3a <[^>]+> bfa2 ittt ge
27 0+3c <[^>]+> 5851 ldrge r1, \[r2, r1\]
28 0+3e <[^>]+> 46c0 nopge ; \(mov r8, r8\)
29 0+40 <[^>]+> 46c0 nopge ; \(mov r8, r8\)
30 0+42 <[^>]+> bfa8 it ge
31 0+44 <[^>]+> f852 f001 ldrge.w pc, \[r2, r1\]
32 0+48 <[^>]+> 58d1 ldr r1, \[r2, r3\]
33 0+4a <[^>]+> f8c2 100a str.w r1, \[r2, #10\]
34 0+4e <[^>]+> f8c1 100a str.w r1, \[r1, #10\]
35 0+52 <[^>]+> f842 1f0a str.w r1, \[r2, #10\]!
36 0+56 <[^>]+> 50d1 str r1, \[r2, r3\]