opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instuction support required */
  48   CpuClflush,
  49   /* SYSCALL Instuctions support required */
  50   CpuSYSCALL,
  51   /* Floating point support required */
  52   Cpu8087,
  53   /* i287 support required */
  54   Cpu287,
  55   /* i387 support required */
  56   Cpu387,
  57   /* i686 and floating point support required */
  58   Cpu687,
  59   /* SSE3 and floating point support required */
  60   CpuFISTTP,
  61   /* MMX support required */
  62   CpuMMX,
  63   /* SSE support required */
  64   CpuSSE,
  65   /* SSE2 support required */
  66   CpuSSE2,
  67   /* 3dnow! support required */
  68   Cpu3dnow,
  69   /* 3dnow! Extensions support required */
  70   Cpu3dnowA,
  71   /* SSE3 support required */
  72   CpuSSE3,
  73   /* VIA PadLock required */
  74   CpuPadLock,
  75   /* AMD Secure Virtual Machine Ext-s required */
  76   CpuSVME,
  77   /* VMX Instructions required */
  78   CpuVMX,
  79   /* SMX Instructions required */
  80   CpuSMX,
  81   /* SSSE3 support required */
  82   CpuSSSE3,
  83   /* SSE4a support required */
  84   CpuSSE4a,
  85   /* ABM New Instructions required */
  86   CpuABM,
  87   /* SSE4.1 support required */
  88   CpuSSE4_1,
  89   /* SSE4.2 support required */
  90   CpuSSE4_2,
  91   /* AVX support required */
  92   CpuAVX,
  93   /* Intel L1OM support required */
  94   CpuL1OM,
  95   /* Xsave/xrstor New Instuctions support required */
  96   CpuXsave,
  97   /* AES support required */
  98   CpuAES,
  99   /* PCLMUL support required */
 100   CpuPCLMUL,
 101   /* FMA support required */
 102   CpuFMA,
 103   /* FMA4 support required */
 104   CpuFMA4,
 105   /* LWP support required */
 106   CpuLWP,
 107   /* MOVBE Instuction support required */
 108   CpuMovbe,
 109   /* EPT Instructions required */
 110   CpuEPT,
 111   /* RDTSCP Instuction support required */
 112   CpuRdtscp,
 113   /* 64bit support available, used by -march= in assembler.  */
 114   CpuLM,
 115   /* 64bit support required  */
 116   Cpu64,
 117   /* Not supported in the 64bit mode  */
 118   CpuNo64,
 119   /* The last bitfield in i386_cpu_flags.  */
 120   CpuMax = CpuNo64
 121 };
 122
 123 #define CpuNumOfUints \
 124   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 125 #define CpuNumOfBits \
 126   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 127
 128 /* If you get a compiler error for zero width of the unused field,
 129    comment it out.  */
 130 #define CpuUnused       (CpuMax + 1)
 131
 132 /* We can check if an instruction is available with array instead
 133    of bitfield. */
 134 typedef union i386_cpu_flags
 135 {
 136   struct
 137     {
 138       unsigned int cpui186:1;
 139       unsigned int cpui286:1;
 140       unsigned int cpui386:1;
 141       unsigned int cpui486:1;
 142       unsigned int cpui586:1;
 143       unsigned int cpui686:1;
 144       unsigned int cpuclflush:1;
 145       unsigned int cpusyscall:1;
 146       unsigned int cpu8087:1;
 147       unsigned int cpu287:1;
 148       unsigned int cpu387:1;
 149       unsigned int cpu687:1;
 150       unsigned int cpufisttp:1;
 151       unsigned int cpummx:1;
 152       unsigned int cpusse:1;
 153       unsigned int cpusse2:1;
 154       unsigned int cpua3dnow:1;
 155       unsigned int cpua3dnowa:1;
 156       unsigned int cpusse3:1;
 157       unsigned int cpupadlock:1;
 158       unsigned int cpusvme:1;
 159       unsigned int cpuvmx:1;
 160       unsigned int cpusmx:1;
 161       unsigned int cpussse3:1;
 162       unsigned int cpusse4a:1;
 163       unsigned int cpuabm:1;
 164       unsigned int cpusse4_1:1;
 165       unsigned int cpusse4_2:1;
 166       unsigned int cpuavx:1;
 167       unsigned int cpul1om:1;
 168       unsigned int cpuxsave:1;
 169       unsigned int cpuaes:1;
 170       unsigned int cpupclmul:1;
 171       unsigned int cpufma:1;
 172       unsigned int cpufma4:1;
 173       unsigned int cpulwp:1;
 174       unsigned int cpumovbe:1;
 175       unsigned int cpuept:1;
 176       unsigned int cpurdtscp:1;
 177       unsigned int cpulm:1;
 178       unsigned int cpu64:1;
 179       unsigned int cpuno64:1;
 180 #ifdef CpuUnused
 181       unsigned int unused:(CpuNumOfBits - CpuUnused);
 182 #endif
 183     } bitfield;
 184   unsigned int array[CpuNumOfUints];
 185 } i386_cpu_flags;
 186
 187 /* Position of opcode_modifier bits.  */
 188
 189 enum
 190 {
 191   /* has direction bit. */
 192   D = 0,
 193   /* set if operands can be words or dwords encoded the canonical way */
 194   W,
 195   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 196      operand in encoding.  */
 197   S,
 198   /* insn has a modrm byte. */
 199   Modrm,
 200   /* register is in low 3 bits of opcode */
 201   ShortForm,
 202   /* special case for jump insns.  */
 203   Jump,
 204   /* call and jump */
 205   JumpDword,
 206   /* loop and jecxz */
 207   JumpByte,
 208   /* special case for intersegment leaps/calls */
 209   JumpInterSegment,
 210   /* FP insn memory format bit, sized by 0x4 */
 211   FloatMF,
 212   /* src/dest swap for floats. */
 213   FloatR,
 214   /* has float insn direction bit. */
 215   FloatD,
 216   /* needs size prefix if in 32-bit mode */
 217   Size16,
 218   /* needs size prefix if in 16-bit mode */
 219   Size32,
 220   /* needs size prefix if in 64-bit mode */
 221   Size64,
 222   /* instruction ignores operand size prefix and in Intel mode ignores
 223      mnemonic size suffix check.  */
 224   IgnoreSize,
 225   /* default insn size depends on mode */
 226   DefaultSize,
 227   /* b suffix on instruction illegal */
 228   No_bSuf,
 229   /* w suffix on instruction illegal */
 230   No_wSuf,
 231   /* l suffix on instruction illegal */
 232   No_lSuf,
 233   /* s suffix on instruction illegal */
 234   No_sSuf,
 235   /* q suffix on instruction illegal */
 236   No_qSuf,
 237   /* long double suffix on instruction illegal */
 238   No_ldSuf,
 239   /* instruction needs FWAIT */
 240   FWait,
 241   /* quick test for string instructions */
 242   IsString,
 243   /* fake an extra reg operand for clr, imul and special register
 244      processing for some instructions.  */
 245   RegKludge,
 246   /* The first operand must be xmm0 */
 247   FirstXmm0,
 248   /* An implicit xmm0 as the first operand */
 249   Implicit1stXmm0,
 250   /* BYTE is OK in Intel syntax. */
 251   ByteOkIntel,
 252   /* Convert to DWORD */
 253   ToDword,
 254   /* Convert to QWORD */
 255   ToQword,
 256   /* Address prefix changes operand 0 */
 257   AddrPrefixOp0,
 258   /* opcode is a prefix */
 259   IsPrefix,
 260   /* instruction has extension in 8 bit imm */
 261   ImmExt,
 262   /* instruction don't need Rex64 prefix.  */
 263   NoRex64,
 264   /* instruction require Rex64 prefix.  */
 265   Rex64,
 266   /* deprecated fp insn, gets a warning */
 267   Ugh,
 268   /* insn has VEX prefix:
 269         1: 128bit VEX prefix.
 270         2: 256bit VEX prefix.
 271    */
 272   Vex,
 273   /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
 274      We use VexNDS on insns with VEX DDS since the register-only source
 275      is the second source register.  */
 276   VexNDS,
 277   /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
 278   VexNDD,
 279   /* insn has VEX NDD. Register destination is encoded in Vex prefix
 280      and one of the operands can access a memory location.  */
 281   VexLWP,
 282   /* insn has VEX W0. */
 283   VexW0,
 284   /* insn has VEX W1. */
 285   VexW1,
 286   /* insn has VEX 0x0F opcode prefix. */
 287   Vex0F,
 288   /* insn has VEX 0x0F38 opcode prefix. */
 289   Vex0F38,
 290   /* insn has VEX 0x0F3A opcode prefix. */
 291   Vex0F3A,
 292   /* insn has XOP 0x09 opcode prefix. */
 293   XOP09,
 294   /* insn has XOP 0x0A opcode prefix. */
 295   XOP0A,
 296   /* insn has VEX prefix with 3 soures. */
 297   Vex3Sources,
 298   /* instruction has VEX 8 bit imm */
 299   VexImmExt,
 300   /* SSE to AVX support required */
 301   SSE2AVX,
 302   /* No AVX equivalent */
 303   NoAVX,
 304   /* Compatible with old (<= 2.8.1) versions of gcc  */
 305   OldGcc,
 306   /* AT&T mnemonic.  */
 307   ATTMnemonic,
 308   /* AT&T syntax.  */
 309   ATTSyntax,
 310   /* Intel syntax.  */
 311   IntelSyntax,
 312   /* The last bitfield in i386_opcode_modifier.  */
 313   Opcode_Modifier_Max
 314 };
 315
 316 typedef struct i386_opcode_modifier
 317 {
 318   unsigned int d:1;
 319   unsigned int w:1;
 320   unsigned int s:1;
 321   unsigned int modrm:1;
 322   unsigned int shortform:1;
 323   unsigned int jump:1;
 324   unsigned int jumpdword:1;
 325   unsigned int jumpbyte:1;
 326   unsigned int jumpintersegment:1;
 327   unsigned int floatmf:1;
 328   unsigned int floatr:1;
 329   unsigned int floatd:1;
 330   unsigned int size16:1;
 331   unsigned int size32:1;
 332   unsigned int size64:1;
 333   unsigned int ignoresize:1;
 334   unsigned int defaultsize:1;
 335   unsigned int no_bsuf:1;
 336   unsigned int no_wsuf:1;
 337   unsigned int no_lsuf:1;
 338   unsigned int no_ssuf:1;
 339   unsigned int no_qsuf:1;
 340   unsigned int no_ldsuf:1;
 341   unsigned int fwait:1;
 342   unsigned int isstring:1;
 343   unsigned int regkludge:1;
 344   unsigned int firstxmm0:1;
 345   unsigned int implicit1stxmm0:1;
 346   unsigned int byteokintel:1;
 347   unsigned int todword:1;
 348   unsigned int toqword:1;
 349   unsigned int addrprefixop0:1;
 350   unsigned int isprefix:1;
 351   unsigned int immext:1;
 352   unsigned int norex64:1;
 353   unsigned int rex64:1;
 354   unsigned int ugh:1;
 355   unsigned int vex:2;
 356   unsigned int vexnds:1;
 357   unsigned int vexndd:1;
 358   unsigned int vexlwp:1;
 359   unsigned int vexw0:1;
 360   unsigned int vexw1:1;
 361   unsigned int vex0f:1;
 362   unsigned int vex0f38:1;
 363   unsigned int vex0f3a:1;
 364   unsigned int xop09:1;
 365   unsigned int xop0a:1;
 366   unsigned int vex3sources:1;
 367   unsigned int veximmext:1;
 368   unsigned int sse2avx:1;
 369   unsigned int noavx:1;
 370   unsigned int oldgcc:1;
 371   unsigned int attmnemonic:1;
 372   unsigned int attsyntax:1;
 373   unsigned int intelsyntax:1;
 374 } i386_opcode_modifier;
 375
 376 /* Position of operand_type bits.  */
 377
 378 enum
 379 {
 380   /* 8bit register */
 381   Reg8 = 0,
 382   /* 16bit register */
 383   Reg16,
 384   /* 32bit register */
 385   Reg32,
 386   /* 64bit register */
 387   Reg64,
 388   /* Floating pointer stack register */
 389   FloatReg,
 390   /* MMX register */
 391   RegMMX,
 392   /* SSE register */
 393   RegXMM,
 394   /* AVX registers */
 395   RegYMM,
 396   /* Control register */
 397   Control,
 398   /* Debug register */
 399   Debug,
 400   /* Test register */
 401   Test,
 402   /* 2 bit segment register */
 403   SReg2,
 404   /* 3 bit segment register */
 405   SReg3,
 406   /* 1 bit immediate */
 407   Imm1,
 408   /* 8 bit immediate */
 409   Imm8,
 410   /* 8 bit immediate sign extended */
 411   Imm8S,
 412   /* 16 bit immediate */
 413   Imm16,
 414   /* 32 bit immediate */
 415   Imm32,
 416   /* 32 bit immediate sign extended */
 417   Imm32S,
 418   /* 64 bit immediate */
 419   Imm64,
 420   /* 8bit/16bit/32bit displacements are used in different ways,
 421      depending on the instruction.  For jumps, they specify the
 422      size of the PC relative displacement, for instructions with
 423      memory operand, they specify the size of the offset relative
 424      to the base register, and for instructions with memory offset
 425      such as `mov 1234,%al' they specify the size of the offset
 426      relative to the segment base.  */
 427   /* 8 bit displacement */
 428   Disp8,
 429   /* 16 bit displacement */
 430   Disp16,
 431   /* 32 bit displacement */
 432   Disp32,
 433   /* 32 bit signed displacement */
 434   Disp32S,
 435   /* 64 bit displacement */
 436   Disp64,
 437   /* Accumulator %al/%ax/%eax/%rax */
 438   Acc,
 439   /* Floating pointer top stack register %st(0) */
 440   FloatAcc,
 441   /* Register which can be used for base or index in memory operand.  */
 442   BaseIndex,
 443   /* Register to hold in/out port addr = dx */
 444   InOutPortReg,
 445   /* Register to hold shift count = cl */
 446   ShiftCount,
 447   /* Absolute address for jump.  */
 448   JumpAbsolute,
 449   /* String insn operand with fixed es segment */
 450   EsSeg,
 451   /* RegMem is for instructions with a modrm byte where the register
 452      destination operand should be encoded in the mod and regmem fields.
 453      Normally, it will be encoded in the reg field. We add a RegMem
 454      flag to the destination register operand to indicate that it should
 455      be encoded in the regmem field.  */
 456   RegMem,
 457   /* Memory.  */
 458   Mem,
 459   /* BYTE memory. */
 460   Byte,
 461   /* WORD memory. 2 byte */
 462   Word,
 463   /* DWORD memory. 4 byte */
 464   Dword,
 465   /* FWORD memory. 6 byte */
 466   Fword,
 467   /* QWORD memory. 8 byte */
 468   Qword,
 469   /* TBYTE memory. 10 byte */
 470   Tbyte,
 471   /* XMMWORD memory. */
 472   Xmmword,
 473   /* YMMWORD memory. */
 474   Ymmword,
 475   /* Unspecified memory size.  */
 476   Unspecified,
 477   /* Any memory size.  */
 478   Anysize,
 479
 480   /* The last bitfield in i386_operand_type.  */
 481   OTMax
 482 };
 483
 484 #define OTNumOfUints \
 485   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 486 #define OTNumOfBits \
 487   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 488
 489 /* If you get a compiler error for zero width of the unused field,
 490    comment it out.  */
 491 #define OTUnused                (OTMax + 1)
 492
 493 typedef union i386_operand_type
 494 {
 495   struct
 496     {
 497       unsigned int reg8:1;
 498       unsigned int reg16:1;
 499       unsigned int reg32:1;
 500       unsigned int reg64:1;
 501       unsigned int floatreg:1;
 502       unsigned int regmmx:1;
 503       unsigned int regxmm:1;
 504       unsigned int regymm:1;
 505       unsigned int control:1;
 506       unsigned int debug:1;
 507       unsigned int test:1;
 508       unsigned int sreg2:1;
 509       unsigned int sreg3:1;
 510       unsigned int imm1:1;
 511       unsigned int imm8:1;
 512       unsigned int imm8s:1;
 513       unsigned int imm16:1;
 514       unsigned int imm32:1;
 515       unsigned int imm32s:1;
 516       unsigned int imm64:1;
 517       unsigned int disp8:1;
 518       unsigned int disp16:1;
 519       unsigned int disp32:1;
 520       unsigned int disp32s:1;
 521       unsigned int disp64:1;
 522       unsigned int acc:1;
 523       unsigned int floatacc:1;
 524       unsigned int baseindex:1;
 525       unsigned int inoutportreg:1;
 526       unsigned int shiftcount:1;
 527       unsigned int jumpabsolute:1;
 528       unsigned int esseg:1;
 529       unsigned int regmem:1;
 530       unsigned int mem:1;
 531       unsigned int byte:1;
 532       unsigned int word:1;
 533       unsigned int dword:1;
 534       unsigned int fword:1;
 535       unsigned int qword:1;
 536       unsigned int tbyte:1;
 537       unsigned int xmmword:1;
 538       unsigned int ymmword:1;
 539       unsigned int unspecified:1;
 540       unsigned int anysize:1;
 541 #ifdef OTUnused
 542       unsigned int unused:(OTNumOfBits - OTUnused);
 543 #endif
 544     } bitfield;
 545   unsigned int array[OTNumOfUints];
 546 } i386_operand_type;
 547
 548 typedef struct insn_template
 549 {
 550   /* instruction name sans width suffix ("mov" for movl insns) */
 551   char *name;
 552
 553   /* how many operands */
 554   unsigned int operands;
 555
 556   /* base_opcode is the fundamental opcode byte without optional
 557      prefix(es).  */
 558   unsigned int base_opcode;
 559 #define Opcode_D        0x2 /* Direction bit:
 560                                set if Reg --> Regmem;
 561                                unset if Regmem --> Reg. */
 562 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 563 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 564
 565   /* extension_opcode is the 3 bit extension for group <n> insns.
 566      This field is also used to store the 8-bit opcode suffix for the
 567      AMD 3DNow! instructions.
 568      If this template has no extension opcode (the usual case) use None
 569      Instructions */
 570   unsigned int extension_opcode;
 571 #define None 0xffff             /* If no extension_opcode is possible.  */
 572
 573   /* Opcode length.  */
 574   unsigned char opcode_length;
 575
 576   /* cpu feature flags */
 577   i386_cpu_flags cpu_flags;
 578
 579   /* the bits in opcode_modifier are used to generate the final opcode from
 580      the base_opcode.  These bits also are used to detect alternate forms of
 581      the same instruction */
 582   i386_opcode_modifier opcode_modifier;
 583
 584   /* operand_types[i] describes the type of operand i.  This is made
 585      by OR'ing together all of the possible type masks.  (e.g.
 586      'operand_types[i] = Reg|Imm' specifies that operand i can be
 587      either a register or an immediate operand.  */
 588   i386_operand_type operand_types[MAX_OPERANDS];
 589 }
 590 insn_template;
 591
 592 extern const insn_template i386_optab[];
 593
 594 /* these are for register name --> number & type hash lookup */
 595 typedef struct
 596 {
 597   char *reg_name;
 598   i386_operand_type reg_type;
 599   unsigned char reg_flags;
 600 #define RegRex      0x1  /* Extended register.  */
 601 #define RegRex64    0x2  /* Extended 8 bit register.  */
 602   unsigned char reg_num;
 603 #define RegRip  ((unsigned char ) ~0)
 604 #define RegEip  (RegRip - 1)
 605 /* EIZ and RIZ are fake index registers.  */
 606 #define RegEiz  (RegEip - 1)
 607 #define RegRiz  (RegEiz - 1)
 608 /* FLAT is a fake segment register (Intel mode).  */
 609 #define RegFlat     ((unsigned char) ~0)
 610   signed char dw2_regnum[2];
 611 #define Dw2Inval (-1)
 612 }
 613 reg_entry;
 614
 615 /* Entries in i386_regtab.  */
 616 #define REGNAM_AL 1
 617 #define REGNAM_AX 25
 618 #define REGNAM_EAX 41
 619
 620 extern const reg_entry i386_regtab[];
 621 extern const unsigned int i386_regtab_size;
 622
 623 typedef struct
 624 {
 625   char *seg_name;
 626   unsigned int seg_prefix;
 627 }
 628 seg_entry;
 629
 630 extern const seg_entry cs;
 631 extern const seg_entry ds;
 632 extern const seg_entry ss;
 633 extern const seg_entry es;
 634 extern const seg_entry fs;
 635 extern const seg_entry gs;