opcodes/xstormy16-desc.h

   1 /* CPU data header for xstormy16.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef XSTORMY16_CPU_H
  26 #define XSTORMY16_CPU_H
  27
  28 #include "opcode/cgen-bitset.h"
  29
  30 #define CGEN_ARCH xstormy16
  31
  32 /* Given symbol S, return xstormy16_cgen_<S>.  */
  33 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  34 #define CGEN_SYM(s) xstormy16##_cgen_##s
  35 #else
  36 #define CGEN_SYM(s) xstormy16/**/_cgen_/**/s
  37 #endif
  38
  39
  40 /* Selected cpu families.  */
  41 #define HAVE_CPU_XSTORMY16
  42
  43 #define CGEN_INSN_LSB0_P 0
  44
  45 /* Minimum size of any insn (in bytes).  */
  46 #define CGEN_MIN_INSN_SIZE 2
  47
  48 /* Maximum size of any insn (in bytes).  */
  49 #define CGEN_MAX_INSN_SIZE 4
  50
  51 #define CGEN_INT_INSN_P 1
  52
  53 /* Maximum number of syntax elements in an instruction.  */
  54 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
  55
  56 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  57    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  58    we can't hash on everything up to the space.  */
  59 #define CGEN_MNEMONIC_OPERANDS
  60
  61 /* Maximum number of fields in an instruction.  */
  62 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
  63
  64 /* Enums.  */
  65
  66 /* Enum declaration for .  */
  67 typedef enum gr_names {
  68   H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
  69  , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
  70  , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
  71  , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
  72  , H_GR_PSW = 14, H_GR_SP = 15
  73 } GR_NAMES;
  74
  75 /* Enum declaration for .  */
  76 typedef enum gr_rb_names {
  77   H_RBJ_R8 = 0, H_RBJ_R9 = 1, H_RBJ_R10 = 2, H_RBJ_R11 = 3
  78  , H_RBJ_R12 = 4, H_RBJ_R13 = 5, H_RBJ_R14 = 6, H_RBJ_R15 = 7
  79  , H_RBJ_PSW = 6, H_RBJ_SP = 7
  80 } GR_RB_NAMES;
  81
  82 /* Enum declaration for insn op enums.  */
  83 typedef enum insn_op1 {
  84   OP1_0, OP1_1, OP1_2, OP1_3
  85  , OP1_4, OP1_5, OP1_6, OP1_7
  86  , OP1_8, OP1_9, OP1_A, OP1_B
  87  , OP1_C, OP1_D, OP1_E, OP1_F
  88 } INSN_OP1;
  89
  90 /* Enum declaration for insn op enums.  */
  91 typedef enum insn_op2 {
  92   OP2_0, OP2_1, OP2_2, OP2_3
  93  , OP2_4, OP2_5, OP2_6, OP2_7
  94  , OP2_8, OP2_9, OP2_A, OP2_B
  95  , OP2_C, OP2_D, OP2_E, OP2_F
  96 } INSN_OP2;
  97
  98 /* Enum declaration for insn op enums.  */
  99 typedef enum insn_op2a {
 100   OP2A_0, OP2A_2, OP2A_4, OP2A_6
 101  , OP2A_8, OP2A_A, OP2A_C, OP2A_E
 102 } INSN_OP2A;
 103
 104 /* Enum declaration for insn op enums.  */
 105 typedef enum insn_op2m {
 106   OP2M_0, OP2M_1
 107 } INSN_OP2M;
 108
 109 /* Enum declaration for insn op enums.  */
 110 typedef enum insn_op3 {
 111   OP3_0, OP3_1, OP3_2, OP3_3
 112  , OP3_4, OP3_5, OP3_6, OP3_7
 113  , OP3_8, OP3_9, OP3_A, OP3_B
 114  , OP3_C, OP3_D, OP3_E, OP3_F
 115 } INSN_OP3;
 116
 117 /* Enum declaration for insn op enums.  */
 118 typedef enum insn_op3a {
 119   OP3A_0, OP3A_1, OP3A_2, OP3A_3
 120 } INSN_OP3A;
 121
 122 /* Enum declaration for insn op enums.  */
 123 typedef enum insn_op3b {
 124   OP3B_0, OP3B_2, OP3B_4, OP3B_6
 125  , OP3B_8, OP3B_A, OP3B_C, OP3B_E
 126 } INSN_OP3B;
 127
 128 /* Enum declaration for insn op enums.  */
 129 typedef enum insn_op4 {
 130   OP4_0, OP4_1, OP4_2, OP4_3
 131  , OP4_4, OP4_5, OP4_6, OP4_7
 132  , OP4_8, OP4_9, OP4_A, OP4_B
 133  , OP4_C, OP4_D, OP4_E, OP4_F
 134 } INSN_OP4;
 135
 136 /* Enum declaration for insn op enums.  */
 137 typedef enum insn_op4m {
 138   OP4M_0, OP4M_1
 139 } INSN_OP4M;
 140
 141 /* Enum declaration for insn op enums.  */
 142 typedef enum insn_op4b {
 143   OP4B_0, OP4B_1
 144 } INSN_OP4B;
 145
 146 /* Enum declaration for insn op enums.  */
 147 typedef enum insn_op5 {
 148   OP5_0, OP5_1, OP5_2, OP5_3
 149  , OP5_4, OP5_5, OP5_6, OP5_7
 150  , OP5_8, OP5_9, OP5_A, OP5_B
 151  , OP5_C, OP5_D, OP5_E, OP5_F
 152 } INSN_OP5;
 153
 154 /* Enum declaration for insn op enums.  */
 155 typedef enum insn_op5a {
 156   OP5A_0, OP5A_1
 157 } INSN_OP5A;
 158
 159 /* Attributes.  */
 160
 161 /* Enum declaration for machine type selection.  */
 162 typedef enum mach_attr {
 163   MACH_BASE, MACH_XSTORMY16, MACH_MAX
 164 } MACH_ATTR;
 165
 166 /* Enum declaration for instruction set selection.  */
 167 typedef enum isa_attr {
 168   ISA_XSTORMY16, ISA_MAX
 169 } ISA_ATTR;
 170
 171 /* Number of architecture variants.  */
 172 #define MAX_ISAS  1
 173 #define MAX_MACHS ((int) MACH_MAX)
 174
 175 /* Ifield support.  */
 176
 177 /* Ifield attribute indices.  */
 178
 179 /* Enum declaration for cgen_ifld attrs.  */
 180 typedef enum cgen_ifld_attr {
 181   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 182  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 183  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 184 } CGEN_IFLD_ATTR;
 185
 186 /* Number of non-boolean elements in cgen_ifld_attr.  */
 187 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 188
 189 /* cgen_ifld attribute accessor macros.  */
 190 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 191 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 192 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 193 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 194 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
 195 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 196 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
 197
 198 /* Enum declaration for xstormy16 ifield types.  */
 199 typedef enum ifield_type {
 200   XSTORMY16_F_NIL, XSTORMY16_F_ANYOF, XSTORMY16_F_RD, XSTORMY16_F_RDM
 201  , XSTORMY16_F_RM, XSTORMY16_F_RS, XSTORMY16_F_RB, XSTORMY16_F_RBJ
 202  , XSTORMY16_F_OP1, XSTORMY16_F_OP2, XSTORMY16_F_OP2A, XSTORMY16_F_OP2M
 203  , XSTORMY16_F_OP3, XSTORMY16_F_OP3A, XSTORMY16_F_OP3B, XSTORMY16_F_OP4
 204  , XSTORMY16_F_OP4M, XSTORMY16_F_OP4B, XSTORMY16_F_OP5, XSTORMY16_F_OP5A
 205  , XSTORMY16_F_OP, XSTORMY16_F_IMM2, XSTORMY16_F_IMM3, XSTORMY16_F_IMM3B
 206  , XSTORMY16_F_IMM4, XSTORMY16_F_IMM8, XSTORMY16_F_IMM12, XSTORMY16_F_IMM16
 207  , XSTORMY16_F_LMEM8, XSTORMY16_F_HMEM8, XSTORMY16_F_REL8_2, XSTORMY16_F_REL8_4
 208  , XSTORMY16_F_REL12, XSTORMY16_F_REL12A, XSTORMY16_F_ABS24_1, XSTORMY16_F_ABS24_2
 209  , XSTORMY16_F_ABS24, XSTORMY16_F_MAX
 210 } IFIELD_TYPE;
 211
 212 #define MAX_IFLD ((int) XSTORMY16_F_MAX)
 213
 214 /* Hardware attribute indices.  */
 215
 216 /* Enum declaration for cgen_hw attrs.  */
 217 typedef enum cgen_hw_attr {
 218   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 219  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 220 } CGEN_HW_ATTR;
 221
 222 /* Number of non-boolean elements in cgen_hw_attr.  */
 223 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 224
 225 /* cgen_hw attribute accessor macros.  */
 226 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 227 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
 228 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 229 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
 230 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
 231
 232 /* Enum declaration for xstormy16 hardware types.  */
 233 typedef enum cgen_hw_type {
 234   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 235  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_RB
 236  , HW_H_RBJ, HW_H_RPSW, HW_H_Z8, HW_H_Z16
 237  , HW_H_CY, HW_H_HC, HW_H_OV, HW_H_PT
 238  , HW_H_S, HW_H_BRANCHCOND, HW_H_WORDSIZE, HW_MAX
 239 } CGEN_HW_TYPE;
 240
 241 #define MAX_HW ((int) HW_MAX)
 242
 243 /* Operand attribute indices.  */
 244
 245 /* Enum declaration for cgen_operand attrs.  */
 246 typedef enum cgen_operand_attr {
 247   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 248  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 249  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 250 } CGEN_OPERAND_ATTR;
 251
 252 /* Number of non-boolean elements in cgen_operand_attr.  */
 253 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 254
 255 /* cgen_operand attribute accessor macros.  */
 256 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 257 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 258 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 259 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 260 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 261 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
 262 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 263 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
 264 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 265
 266 /* Enum declaration for xstormy16 operand types.  */
 267 typedef enum cgen_operand_type {
 268   XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8, XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY
 269  , XSTORMY16_OPERAND_PSW_HC, XSTORMY16_OPERAND_PSW_OV, XSTORMY16_OPERAND_PSW_PT, XSTORMY16_OPERAND_PSW_S
 270  , XSTORMY16_OPERAND_RD, XSTORMY16_OPERAND_RDM, XSTORMY16_OPERAND_RM, XSTORMY16_OPERAND_RS
 271  , XSTORMY16_OPERAND_RB, XSTORMY16_OPERAND_RBJ, XSTORMY16_OPERAND_BCOND2, XSTORMY16_OPERAND_WS2
 272  , XSTORMY16_OPERAND_BCOND5, XSTORMY16_OPERAND_IMM2, XSTORMY16_OPERAND_IMM3, XSTORMY16_OPERAND_IMM3B
 273  , XSTORMY16_OPERAND_IMM4, XSTORMY16_OPERAND_IMM8, XSTORMY16_OPERAND_IMM8SMALL, XSTORMY16_OPERAND_IMM12
 274  , XSTORMY16_OPERAND_IMM16, XSTORMY16_OPERAND_LMEM8, XSTORMY16_OPERAND_HMEM8, XSTORMY16_OPERAND_REL8_2
 275  , XSTORMY16_OPERAND_REL8_4, XSTORMY16_OPERAND_REL12, XSTORMY16_OPERAND_REL12A, XSTORMY16_OPERAND_ABS24
 276  , XSTORMY16_OPERAND_PSW, XSTORMY16_OPERAND_RPSW, XSTORMY16_OPERAND_SP, XSTORMY16_OPERAND_R0
 277  , XSTORMY16_OPERAND_R1, XSTORMY16_OPERAND_R2, XSTORMY16_OPERAND_R8, XSTORMY16_OPERAND_MAX
 278 } CGEN_OPERAND_TYPE;
 279
 280 /* Number of operands types.  */
 281 #define MAX_OPERANDS 39
 282
 283 /* Maximum number of operands referenced by any insn.  */
 284 #define MAX_OPERAND_INSTANCES 8
 285
 286 /* Insn attribute indices.  */
 287
 288 /* Enum declaration for cgen_insn attrs.  */
 289 typedef enum cgen_insn_attr {
 290   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 291  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 292  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
 293  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 294 } CGEN_INSN_ATTR;
 295
 296 /* Number of non-boolean elements in cgen_insn_attr.  */
 297 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 298
 299 /* cgen_insn attribute accessor macros.  */
 300 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 301 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
 302 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
 303 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 304 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
 305 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 306 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 307 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
 308 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
 309 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
 310 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
 311
 312 /* cgen.h uses things we just defined.  */
 313 #include "opcode/cgen.h"
 314
 315 extern const struct cgen_ifld xstormy16_cgen_ifld_table[];
 316
 317 /* Attributes.  */
 318 extern const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[];
 319 extern const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[];
 320 extern const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[];
 321 extern const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[];
 322
 323 /* Hardware decls.  */
 324
 325 extern CGEN_KEYWORD xstormy16_cgen_opval_gr_names;
 326 extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names;
 327 extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names;
 328 extern CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond;
 329 extern CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize;
 330
 331 extern const CGEN_HW_ENTRY xstormy16_cgen_hw_table[];
 332
 333
 334
 335 #endif /* XSTORMY16_CPU_H */