Remove extra breack.
[binutils.git] / opcodes / i386-dis.c
blobfef9185e5f20e3b64d3c2a9b582d9e217391bb14
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 July 1988
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
37 #include "sysdep.h"
38 #include "dis-asm.h"
39 #include "opintl.h"
40 #include "opcode/i386.h"
41 #include "libiberty.h"
43 #include <setjmp.h>
45 static int print_insn (bfd_vma, disassemble_info *);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma get64 (void);
60 static bfd_signed_vma get32 (void);
61 static bfd_signed_vma get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void CMPXCHG8B_Fixup (int, int);
112 static void XMM_Fixup (int, int);
113 static void CRC32_Fixup (int, int);
114 static void FXSAVE_Fixup (int, int);
115 static void OP_LWPCB_E (int, int);
116 static void OP_LWP_E (int, int);
117 static void OP_Vex_2src_1 (int, int);
118 static void OP_Vex_2src_2 (int, int);
120 static void MOVBE_Fixup (int, int);
122 struct dis_private {
123 /* Points to first byte not fetched. */
124 bfd_byte *max_fetched;
125 bfd_byte the_buffer[MAX_MNEM_SIZE];
126 bfd_vma insn_start;
127 int orig_sizeflag;
128 jmp_buf bailout;
131 enum address_mode
133 mode_16bit,
134 mode_32bit,
135 mode_64bit
138 enum address_mode address_mode;
140 /* Flags for the prefixes for the current instruction. See below. */
141 static int prefixes;
143 /* REX prefix the current instruction. See below. */
144 static int rex;
145 /* Bits of REX we've already used. */
146 static int rex_used;
147 /* REX bits in original REX prefix ignored. */
148 static int rex_ignored;
149 /* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153 #define USED_REX(value) \
155 if (value) \
157 if ((rex & value)) \
158 rex_used |= (value) | REX_OPCODE; \
160 else \
161 rex_used |= REX_OPCODE; \
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
172 #define PREFIX_CS 8
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
189 static int
190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
192 int status;
193 struct dis_private *priv = (struct dis_private *) info->private_data;
194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
203 if (status != 0)
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
209 if (priv->max_fetched == priv->the_buffer)
210 (*info->memory_error_func) (status, start, info);
211 longjmp (priv->bailout, 1);
213 else
214 priv->max_fetched = addr;
215 return 1;
218 #define XX { NULL, 0 }
219 #define Bad_Opcode NULL, { { NULL, 0 } }
221 #define Eb { OP_E, b_mode }
222 #define EbS { OP_E, b_swap_mode }
223 #define Ev { OP_E, v_mode }
224 #define EvS { OP_E, v_swap_mode }
225 #define Ed { OP_E, d_mode }
226 #define Edq { OP_E, dq_mode }
227 #define Edqw { OP_E, dqw_mode }
228 #define Edqb { OP_E, dqb_mode }
229 #define Edqd { OP_E, dqd_mode }
230 #define Eq { OP_E, q_mode }
231 #define indirEv { OP_indirE, stack_v_mode }
232 #define indirEp { OP_indirE, f_mode }
233 #define stackEv { OP_E, stack_v_mode }
234 #define Em { OP_E, m_mode }
235 #define Ew { OP_E, w_mode }
236 #define M { OP_M, 0 } /* lea, lgdt, etc. */
237 #define Ma { OP_M, a_mode }
238 #define Mb { OP_M, b_mode }
239 #define Md { OP_M, d_mode }
240 #define Mo { OP_M, o_mode }
241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242 #define Mq { OP_M, q_mode }
243 #define Mx { OP_M, x_mode }
244 #define Mxmm { OP_M, xmm_mode }
245 #define Gb { OP_G, b_mode }
246 #define Gv { OP_G, v_mode }
247 #define Gd { OP_G, d_mode }
248 #define Gdq { OP_G, dq_mode }
249 #define Gm { OP_G, m_mode }
250 #define Gw { OP_G, w_mode }
251 #define Rd { OP_R, d_mode }
252 #define Rm { OP_R, m_mode }
253 #define Ib { OP_I, b_mode }
254 #define sIb { OP_sI, b_mode } /* sign extened byte */
255 #define Iv { OP_I, v_mode }
256 #define Iq { OP_I, q_mode }
257 #define Iv64 { OP_I64, v_mode }
258 #define Iw { OP_I, w_mode }
259 #define I1 { OP_I, const_1_mode }
260 #define Jb { OP_J, b_mode }
261 #define Jv { OP_J, v_mode }
262 #define Cm { OP_C, m_mode }
263 #define Dm { OP_D, m_mode }
264 #define Td { OP_T, d_mode }
265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
267 #define RMeAX { OP_REG, eAX_reg }
268 #define RMeBX { OP_REG, eBX_reg }
269 #define RMeCX { OP_REG, eCX_reg }
270 #define RMeDX { OP_REG, eDX_reg }
271 #define RMeSP { OP_REG, eSP_reg }
272 #define RMeBP { OP_REG, eBP_reg }
273 #define RMeSI { OP_REG, eSI_reg }
274 #define RMeDI { OP_REG, eDI_reg }
275 #define RMrAX { OP_REG, rAX_reg }
276 #define RMrBX { OP_REG, rBX_reg }
277 #define RMrCX { OP_REG, rCX_reg }
278 #define RMrDX { OP_REG, rDX_reg }
279 #define RMrSP { OP_REG, rSP_reg }
280 #define RMrBP { OP_REG, rBP_reg }
281 #define RMrSI { OP_REG, rSI_reg }
282 #define RMrDI { OP_REG, rDI_reg }
283 #define RMAL { OP_REG, al_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMCL { OP_REG, cl_reg }
286 #define RMDL { OP_REG, dl_reg }
287 #define RMBL { OP_REG, bl_reg }
288 #define RMAH { OP_REG, ah_reg }
289 #define RMCH { OP_REG, ch_reg }
290 #define RMDH { OP_REG, dh_reg }
291 #define RMBH { OP_REG, bh_reg }
292 #define RMAX { OP_REG, ax_reg }
293 #define RMDX { OP_REG, dx_reg }
295 #define eAX { OP_IMREG, eAX_reg }
296 #define eBX { OP_IMREG, eBX_reg }
297 #define eCX { OP_IMREG, eCX_reg }
298 #define eDX { OP_IMREG, eDX_reg }
299 #define eSP { OP_IMREG, eSP_reg }
300 #define eBP { OP_IMREG, eBP_reg }
301 #define eSI { OP_IMREG, eSI_reg }
302 #define eDI { OP_IMREG, eDI_reg }
303 #define AL { OP_IMREG, al_reg }
304 #define CL { OP_IMREG, cl_reg }
305 #define DL { OP_IMREG, dl_reg }
306 #define BL { OP_IMREG, bl_reg }
307 #define AH { OP_IMREG, ah_reg }
308 #define CH { OP_IMREG, ch_reg }
309 #define DH { OP_IMREG, dh_reg }
310 #define BH { OP_IMREG, bh_reg }
311 #define AX { OP_IMREG, ax_reg }
312 #define DX { OP_IMREG, dx_reg }
313 #define zAX { OP_IMREG, z_mode_ax_reg }
314 #define indirDX { OP_IMREG, indir_dx_reg }
316 #define Sw { OP_SEG, w_mode }
317 #define Sv { OP_SEG, v_mode }
318 #define Ap { OP_DIR, 0 }
319 #define Ob { OP_OFF64, b_mode }
320 #define Ov { OP_OFF64, v_mode }
321 #define Xb { OP_DSreg, eSI_reg }
322 #define Xv { OP_DSreg, eSI_reg }
323 #define Xz { OP_DSreg, eSI_reg }
324 #define Yb { OP_ESreg, eDI_reg }
325 #define Yv { OP_ESreg, eDI_reg }
326 #define DSBX { OP_DSreg, eBX_reg }
328 #define es { OP_REG, es_reg }
329 #define ss { OP_REG, ss_reg }
330 #define cs { OP_REG, cs_reg }
331 #define ds { OP_REG, ds_reg }
332 #define fs { OP_REG, fs_reg }
333 #define gs { OP_REG, gs_reg }
335 #define MX { OP_MMX, 0 }
336 #define XM { OP_XMM, 0 }
337 #define XMScalar { OP_XMM, scalar_mode }
338 #define XMM { OP_XMM, xmm_mode }
339 #define EM { OP_EM, v_mode }
340 #define EMS { OP_EM, v_swap_mode }
341 #define EMd { OP_EM, d_mode }
342 #define EMx { OP_EM, x_mode }
343 #define EXw { OP_EX, w_mode }
344 #define EXd { OP_EX, d_mode }
345 #define EXdScalar { OP_EX, d_scalar_mode }
346 #define EXdS { OP_EX, d_swap_mode }
347 #define EXq { OP_EX, q_mode }
348 #define EXqScalar { OP_EX, q_scalar_mode }
349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
350 #define EXqS { OP_EX, q_swap_mode }
351 #define EXx { OP_EX, x_mode }
352 #define EXxS { OP_EX, x_swap_mode }
353 #define EXxmm { OP_EX, xmm_mode }
354 #define EXxmmq { OP_EX, xmmq_mode }
355 #define EXymmq { OP_EX, ymmq_mode }
356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
358 #define MS { OP_MS, v_mode }
359 #define XS { OP_XS, v_mode }
360 #define EMCq { OP_EMC, q_mode }
361 #define MXC { OP_MXC, 0 }
362 #define OPSUF { OP_3DNowSuffix, 0 }
363 #define CMP { CMP_Fixup, 0 }
364 #define XMM0 { XMM_Fixup, 0 }
365 #define FXSAVE { FXSAVE_Fixup, 0 }
366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
369 #define Vex { OP_VEX, vex_mode }
370 #define VexScalar { OP_VEX, vex_scalar_mode }
371 #define Vex128 { OP_VEX, vex128_mode }
372 #define Vex256 { OP_VEX, vex256_mode }
373 #define VexI4 { VEXI4_Fixup, 0}
374 #define EXdVex { OP_EX_Vex, d_mode }
375 #define EXdVexS { OP_EX_Vex, d_swap_mode }
376 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
377 #define EXqVex { OP_EX_Vex, q_mode }
378 #define EXqVexS { OP_EX_Vex, q_swap_mode }
379 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
380 #define EXVexW { OP_EX_VexW, x_mode }
381 #define EXdVexW { OP_EX_VexW, d_mode }
382 #define EXqVexW { OP_EX_VexW, q_mode }
383 #define EXVexImmW { OP_EX_VexImmW, x_mode }
384 #define XMVex { OP_XMM_Vex, 0 }
385 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
386 #define XMVexW { OP_XMM_VexW, 0 }
387 #define XMVexI4 { OP_REG_VexI4, x_mode }
388 #define PCLMUL { PCLMUL_Fixup, 0 }
389 #define VZERO { VZERO_Fixup, 0 }
390 #define VCMP { VCMP_Fixup, 0 }
392 /* Used handle "rep" prefix for string instructions. */
393 #define Xbr { REP_Fixup, eSI_reg }
394 #define Xvr { REP_Fixup, eSI_reg }
395 #define Ybr { REP_Fixup, eDI_reg }
396 #define Yvr { REP_Fixup, eDI_reg }
397 #define Yzr { REP_Fixup, eDI_reg }
398 #define indirDXr { REP_Fixup, indir_dx_reg }
399 #define ALr { REP_Fixup, al_reg }
400 #define eAXr { REP_Fixup, eAX_reg }
402 #define cond_jump_flag { NULL, cond_jump_mode }
403 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
405 /* bits in sizeflag */
406 #define SUFFIX_ALWAYS 4
407 #define AFLAG 2
408 #define DFLAG 1
410 enum
412 /* byte operand */
413 b_mode = 1,
414 /* byte operand with operand swapped */
415 b_swap_mode,
416 /* operand size depends on prefixes */
417 v_mode,
418 /* operand size depends on prefixes with operand swapped */
419 v_swap_mode,
420 /* word operand */
421 w_mode,
422 /* double word operand */
423 d_mode,
424 /* double word operand with operand swapped */
425 d_swap_mode,
426 /* quad word operand */
427 q_mode,
428 /* quad word operand with operand swapped */
429 q_swap_mode,
430 /* ten-byte operand */
431 t_mode,
432 /* 16-byte XMM or 32-byte YMM operand */
433 x_mode,
434 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
435 x_swap_mode,
436 /* 16-byte XMM operand */
437 xmm_mode,
438 /* 16-byte XMM or quad word operand */
439 xmmq_mode,
440 /* 32-byte YMM or quad word operand */
441 ymmq_mode,
442 /* d_mode in 32bit, q_mode in 64bit mode. */
443 m_mode,
444 /* pair of v_mode operands */
445 a_mode,
446 cond_jump_mode,
447 loop_jcxz_mode,
448 /* operand size depends on REX prefixes. */
449 dq_mode,
450 /* registers like dq_mode, memory like w_mode. */
451 dqw_mode,
452 /* 4- or 6-byte pointer operand */
453 f_mode,
454 const_1_mode,
455 /* v_mode for stack-related opcodes. */
456 stack_v_mode,
457 /* non-quad operand size depends on prefixes */
458 z_mode,
459 /* 16-byte operand */
460 o_mode,
461 /* registers like dq_mode, memory like b_mode. */
462 dqb_mode,
463 /* registers like dq_mode, memory like d_mode. */
464 dqd_mode,
465 /* normal vex mode */
466 vex_mode,
467 /* 128bit vex mode */
468 vex128_mode,
469 /* 256bit vex mode */
470 vex256_mode,
471 /* operand size depends on the VEX.W bit. */
472 vex_w_dq_mode,
474 /* scalar, ignore vector length. */
475 scalar_mode,
476 /* like d_mode, ignore vector length. */
477 d_scalar_mode,
478 /* like d_swap_mode, ignore vector length. */
479 d_scalar_swap_mode,
480 /* like q_mode, ignore vector length. */
481 q_scalar_mode,
482 /* like q_swap_mode, ignore vector length. */
483 q_scalar_swap_mode,
484 /* like vex_mode, ignore vector length. */
485 vex_scalar_mode,
486 /* like vex_w_dq_mode, ignore vector length. */
487 vex_scalar_w_dq_mode,
489 es_reg,
490 cs_reg,
491 ss_reg,
492 ds_reg,
493 fs_reg,
494 gs_reg,
496 eAX_reg,
497 eCX_reg,
498 eDX_reg,
499 eBX_reg,
500 eSP_reg,
501 eBP_reg,
502 eSI_reg,
503 eDI_reg,
505 al_reg,
506 cl_reg,
507 dl_reg,
508 bl_reg,
509 ah_reg,
510 ch_reg,
511 dh_reg,
512 bh_reg,
514 ax_reg,
515 cx_reg,
516 dx_reg,
517 bx_reg,
518 sp_reg,
519 bp_reg,
520 si_reg,
521 di_reg,
523 rAX_reg,
524 rCX_reg,
525 rDX_reg,
526 rBX_reg,
527 rSP_reg,
528 rBP_reg,
529 rSI_reg,
530 rDI_reg,
532 z_mode_ax_reg,
533 indir_dx_reg
536 enum
538 FLOATCODE = 1,
539 USE_REG_TABLE,
540 USE_MOD_TABLE,
541 USE_RM_TABLE,
542 USE_PREFIX_TABLE,
543 USE_X86_64_TABLE,
544 USE_3BYTE_TABLE,
545 USE_XOP_8F_TABLE,
546 USE_VEX_C4_TABLE,
547 USE_VEX_C5_TABLE,
548 USE_VEX_LEN_TABLE,
549 USE_VEX_W_TABLE
552 #define FLOAT NULL, { { NULL, FLOATCODE } }
554 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
555 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
556 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
557 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
558 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
559 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
560 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
561 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
562 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
563 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
564 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
565 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
567 enum
569 REG_80 = 0,
570 REG_81,
571 REG_82,
572 REG_8F,
573 REG_C0,
574 REG_C1,
575 REG_C6,
576 REG_C7,
577 REG_D0,
578 REG_D1,
579 REG_D2,
580 REG_D3,
581 REG_F6,
582 REG_F7,
583 REG_FE,
584 REG_FF,
585 REG_0F00,
586 REG_0F01,
587 REG_0F0D,
588 REG_0F18,
589 REG_0F71,
590 REG_0F72,
591 REG_0F73,
592 REG_0FA6,
593 REG_0FA7,
594 REG_0FAE,
595 REG_0FBA,
596 REG_0FC7,
597 REG_VEX_71,
598 REG_VEX_72,
599 REG_VEX_73,
600 REG_VEX_AE,
601 REG_XOP_LWPCB,
602 REG_XOP_LWP
605 enum
607 MOD_8D = 0,
608 MOD_0F01_REG_0,
609 MOD_0F01_REG_1,
610 MOD_0F01_REG_2,
611 MOD_0F01_REG_3,
612 MOD_0F01_REG_7,
613 MOD_0F12_PREFIX_0,
614 MOD_0F13,
615 MOD_0F16_PREFIX_0,
616 MOD_0F17,
617 MOD_0F18_REG_0,
618 MOD_0F18_REG_1,
619 MOD_0F18_REG_2,
620 MOD_0F18_REG_3,
621 MOD_0F20,
622 MOD_0F21,
623 MOD_0F22,
624 MOD_0F23,
625 MOD_0F24,
626 MOD_0F26,
627 MOD_0F2B_PREFIX_0,
628 MOD_0F2B_PREFIX_1,
629 MOD_0F2B_PREFIX_2,
630 MOD_0F2B_PREFIX_3,
631 MOD_0F51,
632 MOD_0F71_REG_2,
633 MOD_0F71_REG_4,
634 MOD_0F71_REG_6,
635 MOD_0F72_REG_2,
636 MOD_0F72_REG_4,
637 MOD_0F72_REG_6,
638 MOD_0F73_REG_2,
639 MOD_0F73_REG_3,
640 MOD_0F73_REG_6,
641 MOD_0F73_REG_7,
642 MOD_0FAE_REG_0,
643 MOD_0FAE_REG_1,
644 MOD_0FAE_REG_2,
645 MOD_0FAE_REG_3,
646 MOD_0FAE_REG_4,
647 MOD_0FAE_REG_5,
648 MOD_0FAE_REG_6,
649 MOD_0FAE_REG_7,
650 MOD_0FB2,
651 MOD_0FB4,
652 MOD_0FB5,
653 MOD_0FC7_REG_6,
654 MOD_0FC7_REG_7,
655 MOD_0FD7,
656 MOD_0FE7_PREFIX_2,
657 MOD_0FF0_PREFIX_3,
658 MOD_0F382A_PREFIX_2,
659 MOD_62_32BIT,
660 MOD_C4_32BIT,
661 MOD_C5_32BIT,
662 MOD_VEX_12_PREFIX_0,
663 MOD_VEX_13,
664 MOD_VEX_16_PREFIX_0,
665 MOD_VEX_17,
666 MOD_VEX_2B,
667 MOD_VEX_50,
668 MOD_VEX_71_REG_2,
669 MOD_VEX_71_REG_4,
670 MOD_VEX_71_REG_6,
671 MOD_VEX_72_REG_2,
672 MOD_VEX_72_REG_4,
673 MOD_VEX_72_REG_6,
674 MOD_VEX_73_REG_2,
675 MOD_VEX_73_REG_3,
676 MOD_VEX_73_REG_6,
677 MOD_VEX_73_REG_7,
678 MOD_VEX_AE_REG_2,
679 MOD_VEX_AE_REG_3,
680 MOD_VEX_D7_PREFIX_2,
681 MOD_VEX_E7_PREFIX_2,
682 MOD_VEX_F0_PREFIX_3,
683 MOD_VEX_3818_PREFIX_2,
684 MOD_VEX_3819_PREFIX_2,
685 MOD_VEX_381A_PREFIX_2,
686 MOD_VEX_382A_PREFIX_2,
687 MOD_VEX_382C_PREFIX_2,
688 MOD_VEX_382D_PREFIX_2,
689 MOD_VEX_382E_PREFIX_2,
690 MOD_VEX_382F_PREFIX_2
693 enum
695 RM_0F01_REG_0 = 0,
696 RM_0F01_REG_1,
697 RM_0F01_REG_2,
698 RM_0F01_REG_3,
699 RM_0F01_REG_7,
700 RM_0FAE_REG_5,
701 RM_0FAE_REG_6,
702 RM_0FAE_REG_7
705 enum
707 PREFIX_90 = 0,
708 PREFIX_0F10,
709 PREFIX_0F11,
710 PREFIX_0F12,
711 PREFIX_0F16,
712 PREFIX_0F2A,
713 PREFIX_0F2B,
714 PREFIX_0F2C,
715 PREFIX_0F2D,
716 PREFIX_0F2E,
717 PREFIX_0F2F,
718 PREFIX_0F51,
719 PREFIX_0F52,
720 PREFIX_0F53,
721 PREFIX_0F58,
722 PREFIX_0F59,
723 PREFIX_0F5A,
724 PREFIX_0F5B,
725 PREFIX_0F5C,
726 PREFIX_0F5D,
727 PREFIX_0F5E,
728 PREFIX_0F5F,
729 PREFIX_0F60,
730 PREFIX_0F61,
731 PREFIX_0F62,
732 PREFIX_0F6C,
733 PREFIX_0F6D,
734 PREFIX_0F6F,
735 PREFIX_0F70,
736 PREFIX_0F73_REG_3,
737 PREFIX_0F73_REG_7,
738 PREFIX_0F78,
739 PREFIX_0F79,
740 PREFIX_0F7C,
741 PREFIX_0F7D,
742 PREFIX_0F7E,
743 PREFIX_0F7F,
744 PREFIX_0FB8,
745 PREFIX_0FBD,
746 PREFIX_0FC2,
747 PREFIX_0FC3,
748 PREFIX_0FC7_REG_6,
749 PREFIX_0FD0,
750 PREFIX_0FD6,
751 PREFIX_0FE6,
752 PREFIX_0FE7,
753 PREFIX_0FF0,
754 PREFIX_0FF7,
755 PREFIX_0F3810,
756 PREFIX_0F3814,
757 PREFIX_0F3815,
758 PREFIX_0F3817,
759 PREFIX_0F3820,
760 PREFIX_0F3821,
761 PREFIX_0F3822,
762 PREFIX_0F3823,
763 PREFIX_0F3824,
764 PREFIX_0F3825,
765 PREFIX_0F3828,
766 PREFIX_0F3829,
767 PREFIX_0F382A,
768 PREFIX_0F382B,
769 PREFIX_0F3830,
770 PREFIX_0F3831,
771 PREFIX_0F3832,
772 PREFIX_0F3833,
773 PREFIX_0F3834,
774 PREFIX_0F3835,
775 PREFIX_0F3837,
776 PREFIX_0F3838,
777 PREFIX_0F3839,
778 PREFIX_0F383A,
779 PREFIX_0F383B,
780 PREFIX_0F383C,
781 PREFIX_0F383D,
782 PREFIX_0F383E,
783 PREFIX_0F383F,
784 PREFIX_0F3840,
785 PREFIX_0F3841,
786 PREFIX_0F3880,
787 PREFIX_0F3881,
788 PREFIX_0F38DB,
789 PREFIX_0F38DC,
790 PREFIX_0F38DD,
791 PREFIX_0F38DE,
792 PREFIX_0F38DF,
793 PREFIX_0F38F0,
794 PREFIX_0F38F1,
795 PREFIX_0F3A08,
796 PREFIX_0F3A09,
797 PREFIX_0F3A0A,
798 PREFIX_0F3A0B,
799 PREFIX_0F3A0C,
800 PREFIX_0F3A0D,
801 PREFIX_0F3A0E,
802 PREFIX_0F3A14,
803 PREFIX_0F3A15,
804 PREFIX_0F3A16,
805 PREFIX_0F3A17,
806 PREFIX_0F3A20,
807 PREFIX_0F3A21,
808 PREFIX_0F3A22,
809 PREFIX_0F3A40,
810 PREFIX_0F3A41,
811 PREFIX_0F3A42,
812 PREFIX_0F3A44,
813 PREFIX_0F3A60,
814 PREFIX_0F3A61,
815 PREFIX_0F3A62,
816 PREFIX_0F3A63,
817 PREFIX_0F3ADF,
818 PREFIX_VEX_10,
819 PREFIX_VEX_11,
820 PREFIX_VEX_12,
821 PREFIX_VEX_16,
822 PREFIX_VEX_2A,
823 PREFIX_VEX_2C,
824 PREFIX_VEX_2D,
825 PREFIX_VEX_2E,
826 PREFIX_VEX_2F,
827 PREFIX_VEX_51,
828 PREFIX_VEX_52,
829 PREFIX_VEX_53,
830 PREFIX_VEX_58,
831 PREFIX_VEX_59,
832 PREFIX_VEX_5A,
833 PREFIX_VEX_5B,
834 PREFIX_VEX_5C,
835 PREFIX_VEX_5D,
836 PREFIX_VEX_5E,
837 PREFIX_VEX_5F,
838 PREFIX_VEX_60,
839 PREFIX_VEX_61,
840 PREFIX_VEX_62,
841 PREFIX_VEX_63,
842 PREFIX_VEX_64,
843 PREFIX_VEX_65,
844 PREFIX_VEX_66,
845 PREFIX_VEX_67,
846 PREFIX_VEX_68,
847 PREFIX_VEX_69,
848 PREFIX_VEX_6A,
849 PREFIX_VEX_6B,
850 PREFIX_VEX_6C,
851 PREFIX_VEX_6D,
852 PREFIX_VEX_6E,
853 PREFIX_VEX_6F,
854 PREFIX_VEX_70,
855 PREFIX_VEX_71_REG_2,
856 PREFIX_VEX_71_REG_4,
857 PREFIX_VEX_71_REG_6,
858 PREFIX_VEX_72_REG_2,
859 PREFIX_VEX_72_REG_4,
860 PREFIX_VEX_72_REG_6,
861 PREFIX_VEX_73_REG_2,
862 PREFIX_VEX_73_REG_3,
863 PREFIX_VEX_73_REG_6,
864 PREFIX_VEX_73_REG_7,
865 PREFIX_VEX_74,
866 PREFIX_VEX_75,
867 PREFIX_VEX_76,
868 PREFIX_VEX_77,
869 PREFIX_VEX_7C,
870 PREFIX_VEX_7D,
871 PREFIX_VEX_7E,
872 PREFIX_VEX_7F,
873 PREFIX_VEX_C2,
874 PREFIX_VEX_C4,
875 PREFIX_VEX_C5,
876 PREFIX_VEX_D0,
877 PREFIX_VEX_D1,
878 PREFIX_VEX_D2,
879 PREFIX_VEX_D3,
880 PREFIX_VEX_D4,
881 PREFIX_VEX_D5,
882 PREFIX_VEX_D6,
883 PREFIX_VEX_D7,
884 PREFIX_VEX_D8,
885 PREFIX_VEX_D9,
886 PREFIX_VEX_DA,
887 PREFIX_VEX_DB,
888 PREFIX_VEX_DC,
889 PREFIX_VEX_DD,
890 PREFIX_VEX_DE,
891 PREFIX_VEX_DF,
892 PREFIX_VEX_E0,
893 PREFIX_VEX_E1,
894 PREFIX_VEX_E2,
895 PREFIX_VEX_E3,
896 PREFIX_VEX_E4,
897 PREFIX_VEX_E5,
898 PREFIX_VEX_E6,
899 PREFIX_VEX_E7,
900 PREFIX_VEX_E8,
901 PREFIX_VEX_E9,
902 PREFIX_VEX_EA,
903 PREFIX_VEX_EB,
904 PREFIX_VEX_EC,
905 PREFIX_VEX_ED,
906 PREFIX_VEX_EE,
907 PREFIX_VEX_EF,
908 PREFIX_VEX_F0,
909 PREFIX_VEX_F1,
910 PREFIX_VEX_F2,
911 PREFIX_VEX_F3,
912 PREFIX_VEX_F4,
913 PREFIX_VEX_F5,
914 PREFIX_VEX_F6,
915 PREFIX_VEX_F7,
916 PREFIX_VEX_F8,
917 PREFIX_VEX_F9,
918 PREFIX_VEX_FA,
919 PREFIX_VEX_FB,
920 PREFIX_VEX_FC,
921 PREFIX_VEX_FD,
922 PREFIX_VEX_FE,
923 PREFIX_VEX_3800,
924 PREFIX_VEX_3801,
925 PREFIX_VEX_3802,
926 PREFIX_VEX_3803,
927 PREFIX_VEX_3804,
928 PREFIX_VEX_3805,
929 PREFIX_VEX_3806,
930 PREFIX_VEX_3807,
931 PREFIX_VEX_3808,
932 PREFIX_VEX_3809,
933 PREFIX_VEX_380A,
934 PREFIX_VEX_380B,
935 PREFIX_VEX_380C,
936 PREFIX_VEX_380D,
937 PREFIX_VEX_380E,
938 PREFIX_VEX_380F,
939 PREFIX_VEX_3817,
940 PREFIX_VEX_3818,
941 PREFIX_VEX_3819,
942 PREFIX_VEX_381A,
943 PREFIX_VEX_381C,
944 PREFIX_VEX_381D,
945 PREFIX_VEX_381E,
946 PREFIX_VEX_3820,
947 PREFIX_VEX_3821,
948 PREFIX_VEX_3822,
949 PREFIX_VEX_3823,
950 PREFIX_VEX_3824,
951 PREFIX_VEX_3825,
952 PREFIX_VEX_3828,
953 PREFIX_VEX_3829,
954 PREFIX_VEX_382A,
955 PREFIX_VEX_382B,
956 PREFIX_VEX_382C,
957 PREFIX_VEX_382D,
958 PREFIX_VEX_382E,
959 PREFIX_VEX_382F,
960 PREFIX_VEX_3830,
961 PREFIX_VEX_3831,
962 PREFIX_VEX_3832,
963 PREFIX_VEX_3833,
964 PREFIX_VEX_3834,
965 PREFIX_VEX_3835,
966 PREFIX_VEX_3837,
967 PREFIX_VEX_3838,
968 PREFIX_VEX_3839,
969 PREFIX_VEX_383A,
970 PREFIX_VEX_383B,
971 PREFIX_VEX_383C,
972 PREFIX_VEX_383D,
973 PREFIX_VEX_383E,
974 PREFIX_VEX_383F,
975 PREFIX_VEX_3840,
976 PREFIX_VEX_3841,
977 PREFIX_VEX_3896,
978 PREFIX_VEX_3897,
979 PREFIX_VEX_3898,
980 PREFIX_VEX_3899,
981 PREFIX_VEX_389A,
982 PREFIX_VEX_389B,
983 PREFIX_VEX_389C,
984 PREFIX_VEX_389D,
985 PREFIX_VEX_389E,
986 PREFIX_VEX_389F,
987 PREFIX_VEX_38A6,
988 PREFIX_VEX_38A7,
989 PREFIX_VEX_38A8,
990 PREFIX_VEX_38A9,
991 PREFIX_VEX_38AA,
992 PREFIX_VEX_38AB,
993 PREFIX_VEX_38AC,
994 PREFIX_VEX_38AD,
995 PREFIX_VEX_38AE,
996 PREFIX_VEX_38AF,
997 PREFIX_VEX_38B6,
998 PREFIX_VEX_38B7,
999 PREFIX_VEX_38B8,
1000 PREFIX_VEX_38B9,
1001 PREFIX_VEX_38BA,
1002 PREFIX_VEX_38BB,
1003 PREFIX_VEX_38BC,
1004 PREFIX_VEX_38BD,
1005 PREFIX_VEX_38BE,
1006 PREFIX_VEX_38BF,
1007 PREFIX_VEX_38DB,
1008 PREFIX_VEX_38DC,
1009 PREFIX_VEX_38DD,
1010 PREFIX_VEX_38DE,
1011 PREFIX_VEX_38DF,
1012 PREFIX_VEX_3A04,
1013 PREFIX_VEX_3A05,
1014 PREFIX_VEX_3A06,
1015 PREFIX_VEX_3A08,
1016 PREFIX_VEX_3A09,
1017 PREFIX_VEX_3A0A,
1018 PREFIX_VEX_3A0B,
1019 PREFIX_VEX_3A0C,
1020 PREFIX_VEX_3A0D,
1021 PREFIX_VEX_3A0E,
1022 PREFIX_VEX_3A0F,
1023 PREFIX_VEX_3A14,
1024 PREFIX_VEX_3A15,
1025 PREFIX_VEX_3A16,
1026 PREFIX_VEX_3A17,
1027 PREFIX_VEX_3A18,
1028 PREFIX_VEX_3A19,
1029 PREFIX_VEX_3A20,
1030 PREFIX_VEX_3A21,
1031 PREFIX_VEX_3A22,
1032 PREFIX_VEX_3A40,
1033 PREFIX_VEX_3A41,
1034 PREFIX_VEX_3A42,
1035 PREFIX_VEX_3A44,
1036 PREFIX_VEX_3A48,
1037 PREFIX_VEX_3A49,
1038 PREFIX_VEX_3A4A,
1039 PREFIX_VEX_3A4B,
1040 PREFIX_VEX_3A4C,
1041 PREFIX_VEX_3A5C,
1042 PREFIX_VEX_3A5D,
1043 PREFIX_VEX_3A5E,
1044 PREFIX_VEX_3A5F,
1045 PREFIX_VEX_3A60,
1046 PREFIX_VEX_3A61,
1047 PREFIX_VEX_3A62,
1048 PREFIX_VEX_3A63,
1049 PREFIX_VEX_3A68,
1050 PREFIX_VEX_3A69,
1051 PREFIX_VEX_3A6A,
1052 PREFIX_VEX_3A6B,
1053 PREFIX_VEX_3A6C,
1054 PREFIX_VEX_3A6D,
1055 PREFIX_VEX_3A6E,
1056 PREFIX_VEX_3A6F,
1057 PREFIX_VEX_3A78,
1058 PREFIX_VEX_3A79,
1059 PREFIX_VEX_3A7A,
1060 PREFIX_VEX_3A7B,
1061 PREFIX_VEX_3A7C,
1062 PREFIX_VEX_3A7D,
1063 PREFIX_VEX_3A7E,
1064 PREFIX_VEX_3A7F,
1065 PREFIX_VEX_3ADF
1068 enum
1070 X86_64_06 = 0,
1071 X86_64_07,
1072 X86_64_0D,
1073 X86_64_16,
1074 X86_64_17,
1075 X86_64_1E,
1076 X86_64_1F,
1077 X86_64_27,
1078 X86_64_2F,
1079 X86_64_37,
1080 X86_64_3F,
1081 X86_64_60,
1082 X86_64_61,
1083 X86_64_62,
1084 X86_64_63,
1085 X86_64_6D,
1086 X86_64_6F,
1087 X86_64_9A,
1088 X86_64_C4,
1089 X86_64_C5,
1090 X86_64_CE,
1091 X86_64_D4,
1092 X86_64_D5,
1093 X86_64_EA,
1094 X86_64_0F01_REG_0,
1095 X86_64_0F01_REG_1,
1096 X86_64_0F01_REG_2,
1097 X86_64_0F01_REG_3
1100 enum
1102 THREE_BYTE_0F38 = 0,
1103 THREE_BYTE_0F3A,
1104 THREE_BYTE_0F7A
1107 enum
1109 XOP_08 = 0,
1110 XOP_09,
1111 XOP_0A
1114 enum
1116 VEX_0F = 0,
1117 VEX_0F38,
1118 VEX_0F3A
1121 enum
1123 VEX_LEN_10_P_1 = 0,
1124 VEX_LEN_10_P_3,
1125 VEX_LEN_11_P_1,
1126 VEX_LEN_11_P_3,
1127 VEX_LEN_12_P_0_M_0,
1128 VEX_LEN_12_P_0_M_1,
1129 VEX_LEN_12_P_2,
1130 VEX_LEN_13_M_0,
1131 VEX_LEN_16_P_0_M_0,
1132 VEX_LEN_16_P_0_M_1,
1133 VEX_LEN_16_P_2,
1134 VEX_LEN_17_M_0,
1135 VEX_LEN_2A_P_1,
1136 VEX_LEN_2A_P_3,
1137 VEX_LEN_2C_P_1,
1138 VEX_LEN_2C_P_3,
1139 VEX_LEN_2D_P_1,
1140 VEX_LEN_2D_P_3,
1141 VEX_LEN_2E_P_0,
1142 VEX_LEN_2E_P_2,
1143 VEX_LEN_2F_P_0,
1144 VEX_LEN_2F_P_2,
1145 VEX_LEN_51_P_1,
1146 VEX_LEN_51_P_3,
1147 VEX_LEN_52_P_1,
1148 VEX_LEN_53_P_1,
1149 VEX_LEN_58_P_1,
1150 VEX_LEN_58_P_3,
1151 VEX_LEN_59_P_1,
1152 VEX_LEN_59_P_3,
1153 VEX_LEN_5A_P_1,
1154 VEX_LEN_5A_P_3,
1155 VEX_LEN_5C_P_1,
1156 VEX_LEN_5C_P_3,
1157 VEX_LEN_5D_P_1,
1158 VEX_LEN_5D_P_3,
1159 VEX_LEN_5E_P_1,
1160 VEX_LEN_5E_P_3,
1161 VEX_LEN_5F_P_1,
1162 VEX_LEN_5F_P_3,
1163 VEX_LEN_60_P_2,
1164 VEX_LEN_61_P_2,
1165 VEX_LEN_62_P_2,
1166 VEX_LEN_63_P_2,
1167 VEX_LEN_64_P_2,
1168 VEX_LEN_65_P_2,
1169 VEX_LEN_66_P_2,
1170 VEX_LEN_67_P_2,
1171 VEX_LEN_68_P_2,
1172 VEX_LEN_69_P_2,
1173 VEX_LEN_6A_P_2,
1174 VEX_LEN_6B_P_2,
1175 VEX_LEN_6C_P_2,
1176 VEX_LEN_6D_P_2,
1177 VEX_LEN_6E_P_2,
1178 VEX_LEN_70_P_1,
1179 VEX_LEN_70_P_2,
1180 VEX_LEN_70_P_3,
1181 VEX_LEN_71_R_2_P_2,
1182 VEX_LEN_71_R_4_P_2,
1183 VEX_LEN_71_R_6_P_2,
1184 VEX_LEN_72_R_2_P_2,
1185 VEX_LEN_72_R_4_P_2,
1186 VEX_LEN_72_R_6_P_2,
1187 VEX_LEN_73_R_2_P_2,
1188 VEX_LEN_73_R_3_P_2,
1189 VEX_LEN_73_R_6_P_2,
1190 VEX_LEN_73_R_7_P_2,
1191 VEX_LEN_74_P_2,
1192 VEX_LEN_75_P_2,
1193 VEX_LEN_76_P_2,
1194 VEX_LEN_7E_P_1,
1195 VEX_LEN_7E_P_2,
1196 VEX_LEN_AE_R_2_M_0,
1197 VEX_LEN_AE_R_3_M_0,
1198 VEX_LEN_C2_P_1,
1199 VEX_LEN_C2_P_3,
1200 VEX_LEN_C4_P_2,
1201 VEX_LEN_C5_P_2,
1202 VEX_LEN_D1_P_2,
1203 VEX_LEN_D2_P_2,
1204 VEX_LEN_D3_P_2,
1205 VEX_LEN_D4_P_2,
1206 VEX_LEN_D5_P_2,
1207 VEX_LEN_D6_P_2,
1208 VEX_LEN_D7_P_2_M_1,
1209 VEX_LEN_D8_P_2,
1210 VEX_LEN_D9_P_2,
1211 VEX_LEN_DA_P_2,
1212 VEX_LEN_DB_P_2,
1213 VEX_LEN_DC_P_2,
1214 VEX_LEN_DD_P_2,
1215 VEX_LEN_DE_P_2,
1216 VEX_LEN_DF_P_2,
1217 VEX_LEN_E0_P_2,
1218 VEX_LEN_E1_P_2,
1219 VEX_LEN_E2_P_2,
1220 VEX_LEN_E3_P_2,
1221 VEX_LEN_E4_P_2,
1222 VEX_LEN_E5_P_2,
1223 VEX_LEN_E8_P_2,
1224 VEX_LEN_E9_P_2,
1225 VEX_LEN_EA_P_2,
1226 VEX_LEN_EB_P_2,
1227 VEX_LEN_EC_P_2,
1228 VEX_LEN_ED_P_2,
1229 VEX_LEN_EE_P_2,
1230 VEX_LEN_EF_P_2,
1231 VEX_LEN_F1_P_2,
1232 VEX_LEN_F2_P_2,
1233 VEX_LEN_F3_P_2,
1234 VEX_LEN_F4_P_2,
1235 VEX_LEN_F5_P_2,
1236 VEX_LEN_F6_P_2,
1237 VEX_LEN_F7_P_2,
1238 VEX_LEN_F8_P_2,
1239 VEX_LEN_F9_P_2,
1240 VEX_LEN_FA_P_2,
1241 VEX_LEN_FB_P_2,
1242 VEX_LEN_FC_P_2,
1243 VEX_LEN_FD_P_2,
1244 VEX_LEN_FE_P_2,
1245 VEX_LEN_3800_P_2,
1246 VEX_LEN_3801_P_2,
1247 VEX_LEN_3802_P_2,
1248 VEX_LEN_3803_P_2,
1249 VEX_LEN_3804_P_2,
1250 VEX_LEN_3805_P_2,
1251 VEX_LEN_3806_P_2,
1252 VEX_LEN_3807_P_2,
1253 VEX_LEN_3808_P_2,
1254 VEX_LEN_3809_P_2,
1255 VEX_LEN_380A_P_2,
1256 VEX_LEN_380B_P_2,
1257 VEX_LEN_3819_P_2_M_0,
1258 VEX_LEN_381A_P_2_M_0,
1259 VEX_LEN_381C_P_2,
1260 VEX_LEN_381D_P_2,
1261 VEX_LEN_381E_P_2,
1262 VEX_LEN_3820_P_2,
1263 VEX_LEN_3821_P_2,
1264 VEX_LEN_3822_P_2,
1265 VEX_LEN_3823_P_2,
1266 VEX_LEN_3824_P_2,
1267 VEX_LEN_3825_P_2,
1268 VEX_LEN_3828_P_2,
1269 VEX_LEN_3829_P_2,
1270 VEX_LEN_382A_P_2_M_0,
1271 VEX_LEN_382B_P_2,
1272 VEX_LEN_3830_P_2,
1273 VEX_LEN_3831_P_2,
1274 VEX_LEN_3832_P_2,
1275 VEX_LEN_3833_P_2,
1276 VEX_LEN_3834_P_2,
1277 VEX_LEN_3835_P_2,
1278 VEX_LEN_3837_P_2,
1279 VEX_LEN_3838_P_2,
1280 VEX_LEN_3839_P_2,
1281 VEX_LEN_383A_P_2,
1282 VEX_LEN_383B_P_2,
1283 VEX_LEN_383C_P_2,
1284 VEX_LEN_383D_P_2,
1285 VEX_LEN_383E_P_2,
1286 VEX_LEN_383F_P_2,
1287 VEX_LEN_3840_P_2,
1288 VEX_LEN_3841_P_2,
1289 VEX_LEN_38DB_P_2,
1290 VEX_LEN_38DC_P_2,
1291 VEX_LEN_38DD_P_2,
1292 VEX_LEN_38DE_P_2,
1293 VEX_LEN_38DF_P_2,
1294 VEX_LEN_3A06_P_2,
1295 VEX_LEN_3A0A_P_2,
1296 VEX_LEN_3A0B_P_2,
1297 VEX_LEN_3A0E_P_2,
1298 VEX_LEN_3A0F_P_2,
1299 VEX_LEN_3A14_P_2,
1300 VEX_LEN_3A15_P_2,
1301 VEX_LEN_3A16_P_2,
1302 VEX_LEN_3A17_P_2,
1303 VEX_LEN_3A18_P_2,
1304 VEX_LEN_3A19_P_2,
1305 VEX_LEN_3A20_P_2,
1306 VEX_LEN_3A21_P_2,
1307 VEX_LEN_3A22_P_2,
1308 VEX_LEN_3A41_P_2,
1309 VEX_LEN_3A42_P_2,
1310 VEX_LEN_3A44_P_2,
1311 VEX_LEN_3A4C_P_2,
1312 VEX_LEN_3A60_P_2,
1313 VEX_LEN_3A61_P_2,
1314 VEX_LEN_3A62_P_2,
1315 VEX_LEN_3A63_P_2,
1316 VEX_LEN_3A6A_P_2,
1317 VEX_LEN_3A6B_P_2,
1318 VEX_LEN_3A6E_P_2,
1319 VEX_LEN_3A6F_P_2,
1320 VEX_LEN_3A7A_P_2,
1321 VEX_LEN_3A7B_P_2,
1322 VEX_LEN_3A7E_P_2,
1323 VEX_LEN_3A7F_P_2,
1324 VEX_LEN_3ADF_P_2,
1325 VEX_LEN_XOP_09_80,
1326 VEX_LEN_XOP_09_81
1329 enum
1331 VEX_W_10_P_0 = 0,
1332 VEX_W_10_P_1,
1333 VEX_W_10_P_2,
1334 VEX_W_10_P_3,
1335 VEX_W_11_P_0,
1336 VEX_W_11_P_1,
1337 VEX_W_11_P_2,
1338 VEX_W_11_P_3,
1339 VEX_W_12_P_0_M_0,
1340 VEX_W_12_P_0_M_1,
1341 VEX_W_12_P_1,
1342 VEX_W_12_P_2,
1343 VEX_W_12_P_3,
1344 VEX_W_13_M_0,
1345 VEX_W_14,
1346 VEX_W_15,
1347 VEX_W_16_P_0_M_0,
1348 VEX_W_16_P_0_M_1,
1349 VEX_W_16_P_1,
1350 VEX_W_16_P_2,
1351 VEX_W_17_M_0,
1352 VEX_W_28,
1353 VEX_W_29,
1354 VEX_W_2B_M_0,
1355 VEX_W_2E_P_0,
1356 VEX_W_2E_P_2,
1357 VEX_W_2F_P_0,
1358 VEX_W_2F_P_2,
1359 VEX_W_50_M_0,
1360 VEX_W_51_P_0,
1361 VEX_W_51_P_1,
1362 VEX_W_51_P_2,
1363 VEX_W_51_P_3,
1364 VEX_W_52_P_0,
1365 VEX_W_52_P_1,
1366 VEX_W_53_P_0,
1367 VEX_W_53_P_1,
1368 VEX_W_58_P_0,
1369 VEX_W_58_P_1,
1370 VEX_W_58_P_2,
1371 VEX_W_58_P_3,
1372 VEX_W_59_P_0,
1373 VEX_W_59_P_1,
1374 VEX_W_59_P_2,
1375 VEX_W_59_P_3,
1376 VEX_W_5A_P_0,
1377 VEX_W_5A_P_1,
1378 VEX_W_5A_P_3,
1379 VEX_W_5B_P_0,
1380 VEX_W_5B_P_1,
1381 VEX_W_5B_P_2,
1382 VEX_W_5C_P_0,
1383 VEX_W_5C_P_1,
1384 VEX_W_5C_P_2,
1385 VEX_W_5C_P_3,
1386 VEX_W_5D_P_0,
1387 VEX_W_5D_P_1,
1388 VEX_W_5D_P_2,
1389 VEX_W_5D_P_3,
1390 VEX_W_5E_P_0,
1391 VEX_W_5E_P_1,
1392 VEX_W_5E_P_2,
1393 VEX_W_5E_P_3,
1394 VEX_W_5F_P_0,
1395 VEX_W_5F_P_1,
1396 VEX_W_5F_P_2,
1397 VEX_W_5F_P_3,
1398 VEX_W_60_P_2,
1399 VEX_W_61_P_2,
1400 VEX_W_62_P_2,
1401 VEX_W_63_P_2,
1402 VEX_W_64_P_2,
1403 VEX_W_65_P_2,
1404 VEX_W_66_P_2,
1405 VEX_W_67_P_2,
1406 VEX_W_68_P_2,
1407 VEX_W_69_P_2,
1408 VEX_W_6A_P_2,
1409 VEX_W_6B_P_2,
1410 VEX_W_6C_P_2,
1411 VEX_W_6D_P_2,
1412 VEX_W_6F_P_1,
1413 VEX_W_6F_P_2,
1414 VEX_W_70_P_1,
1415 VEX_W_70_P_2,
1416 VEX_W_70_P_3,
1417 VEX_W_71_R_2_P_2,
1418 VEX_W_71_R_4_P_2,
1419 VEX_W_71_R_6_P_2,
1420 VEX_W_72_R_2_P_2,
1421 VEX_W_72_R_4_P_2,
1422 VEX_W_72_R_6_P_2,
1423 VEX_W_73_R_2_P_2,
1424 VEX_W_73_R_3_P_2,
1425 VEX_W_73_R_6_P_2,
1426 VEX_W_73_R_7_P_2,
1427 VEX_W_74_P_2,
1428 VEX_W_75_P_2,
1429 VEX_W_76_P_2,
1430 VEX_W_77_P_0,
1431 VEX_W_7C_P_2,
1432 VEX_W_7C_P_3,
1433 VEX_W_7D_P_2,
1434 VEX_W_7D_P_3,
1435 VEX_W_7E_P_1,
1436 VEX_W_7F_P_1,
1437 VEX_W_7F_P_2,
1438 VEX_W_AE_R_2_M_0,
1439 VEX_W_AE_R_3_M_0,
1440 VEX_W_C2_P_0,
1441 VEX_W_C2_P_1,
1442 VEX_W_C2_P_2,
1443 VEX_W_C2_P_3,
1444 VEX_W_C4_P_2,
1445 VEX_W_C5_P_2,
1446 VEX_W_D0_P_2,
1447 VEX_W_D0_P_3,
1448 VEX_W_D1_P_2,
1449 VEX_W_D2_P_2,
1450 VEX_W_D3_P_2,
1451 VEX_W_D4_P_2,
1452 VEX_W_D5_P_2,
1453 VEX_W_D6_P_2,
1454 VEX_W_D7_P_2_M_1,
1455 VEX_W_D8_P_2,
1456 VEX_W_D9_P_2,
1457 VEX_W_DA_P_2,
1458 VEX_W_DB_P_2,
1459 VEX_W_DC_P_2,
1460 VEX_W_DD_P_2,
1461 VEX_W_DE_P_2,
1462 VEX_W_DF_P_2,
1463 VEX_W_E0_P_2,
1464 VEX_W_E1_P_2,
1465 VEX_W_E2_P_2,
1466 VEX_W_E3_P_2,
1467 VEX_W_E4_P_2,
1468 VEX_W_E5_P_2,
1469 VEX_W_E6_P_1,
1470 VEX_W_E6_P_2,
1471 VEX_W_E6_P_3,
1472 VEX_W_E7_P_2_M_0,
1473 VEX_W_E8_P_2,
1474 VEX_W_E9_P_2,
1475 VEX_W_EA_P_2,
1476 VEX_W_EB_P_2,
1477 VEX_W_EC_P_2,
1478 VEX_W_ED_P_2,
1479 VEX_W_EE_P_2,
1480 VEX_W_EF_P_2,
1481 VEX_W_F0_P_3_M_0,
1482 VEX_W_F1_P_2,
1483 VEX_W_F2_P_2,
1484 VEX_W_F3_P_2,
1485 VEX_W_F4_P_2,
1486 VEX_W_F5_P_2,
1487 VEX_W_F6_P_2,
1488 VEX_W_F7_P_2,
1489 VEX_W_F8_P_2,
1490 VEX_W_F9_P_2,
1491 VEX_W_FA_P_2,
1492 VEX_W_FB_P_2,
1493 VEX_W_FC_P_2,
1494 VEX_W_FD_P_2,
1495 VEX_W_FE_P_2,
1496 VEX_W_3800_P_2,
1497 VEX_W_3801_P_2,
1498 VEX_W_3802_P_2,
1499 VEX_W_3803_P_2,
1500 VEX_W_3804_P_2,
1501 VEX_W_3805_P_2,
1502 VEX_W_3806_P_2,
1503 VEX_W_3807_P_2,
1504 VEX_W_3808_P_2,
1505 VEX_W_3809_P_2,
1506 VEX_W_380A_P_2,
1507 VEX_W_380B_P_2,
1508 VEX_W_380C_P_2,
1509 VEX_W_380D_P_2,
1510 VEX_W_380E_P_2,
1511 VEX_W_380F_P_2,
1512 VEX_W_3817_P_2,
1513 VEX_W_3818_P_2_M_0,
1514 VEX_W_3819_P_2_M_0,
1515 VEX_W_381A_P_2_M_0,
1516 VEX_W_381C_P_2,
1517 VEX_W_381D_P_2,
1518 VEX_W_381E_P_2,
1519 VEX_W_3820_P_2,
1520 VEX_W_3821_P_2,
1521 VEX_W_3822_P_2,
1522 VEX_W_3823_P_2,
1523 VEX_W_3824_P_2,
1524 VEX_W_3825_P_2,
1525 VEX_W_3828_P_2,
1526 VEX_W_3829_P_2,
1527 VEX_W_382A_P_2_M_0,
1528 VEX_W_382B_P_2,
1529 VEX_W_382C_P_2_M_0,
1530 VEX_W_382D_P_2_M_0,
1531 VEX_W_382E_P_2_M_0,
1532 VEX_W_382F_P_2_M_0,
1533 VEX_W_3830_P_2,
1534 VEX_W_3831_P_2,
1535 VEX_W_3832_P_2,
1536 VEX_W_3833_P_2,
1537 VEX_W_3834_P_2,
1538 VEX_W_3835_P_2,
1539 VEX_W_3837_P_2,
1540 VEX_W_3838_P_2,
1541 VEX_W_3839_P_2,
1542 VEX_W_383A_P_2,
1543 VEX_W_383B_P_2,
1544 VEX_W_383C_P_2,
1545 VEX_W_383D_P_2,
1546 VEX_W_383E_P_2,
1547 VEX_W_383F_P_2,
1548 VEX_W_3840_P_2,
1549 VEX_W_3841_P_2,
1550 VEX_W_38DB_P_2,
1551 VEX_W_38DC_P_2,
1552 VEX_W_38DD_P_2,
1553 VEX_W_38DE_P_2,
1554 VEX_W_38DF_P_2,
1555 VEX_W_3A04_P_2,
1556 VEX_W_3A05_P_2,
1557 VEX_W_3A06_P_2,
1558 VEX_W_3A08_P_2,
1559 VEX_W_3A09_P_2,
1560 VEX_W_3A0A_P_2,
1561 VEX_W_3A0B_P_2,
1562 VEX_W_3A0C_P_2,
1563 VEX_W_3A0D_P_2,
1564 VEX_W_3A0E_P_2,
1565 VEX_W_3A0F_P_2,
1566 VEX_W_3A14_P_2,
1567 VEX_W_3A15_P_2,
1568 VEX_W_3A18_P_2,
1569 VEX_W_3A19_P_2,
1570 VEX_W_3A20_P_2,
1571 VEX_W_3A21_P_2,
1572 VEX_W_3A40_P_2,
1573 VEX_W_3A41_P_2,
1574 VEX_W_3A42_P_2,
1575 VEX_W_3A44_P_2,
1576 VEX_W_3A48_P_2,
1577 VEX_W_3A49_P_2,
1578 VEX_W_3A4A_P_2,
1579 VEX_W_3A4B_P_2,
1580 VEX_W_3A4C_P_2,
1581 VEX_W_3A60_P_2,
1582 VEX_W_3A61_P_2,
1583 VEX_W_3A62_P_2,
1584 VEX_W_3A63_P_2,
1585 VEX_W_3ADF_P_2
1588 typedef void (*op_rtn) (int bytemode, int sizeflag);
1590 struct dis386 {
1591 const char *name;
1592 struct
1594 op_rtn rtn;
1595 int bytemode;
1596 } op[MAX_OPERANDS];
1599 /* Upper case letters in the instruction names here are macros.
1600 'A' => print 'b' if no register operands or suffix_always is true
1601 'B' => print 'b' if suffix_always is true
1602 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1603 size prefix
1604 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1605 suffix_always is true
1606 'E' => print 'e' if 32-bit form of jcxz
1607 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1608 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1609 'H' => print ",pt" or ",pn" branch hint
1610 'I' => honor following macro letter even in Intel mode (implemented only
1611 for some of the macro letters)
1612 'J' => print 'l'
1613 'K' => print 'd' or 'q' if rex prefix is present.
1614 'L' => print 'l' if suffix_always is true
1615 'M' => print 'r' if intel_mnemonic is false.
1616 'N' => print 'n' if instruction has no wait "prefix"
1617 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1618 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1619 or suffix_always is true. print 'q' if rex prefix is present.
1620 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1621 is true
1622 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1623 'S' => print 'w', 'l' or 'q' if suffix_always is true
1624 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1625 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1626 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1627 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1628 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1629 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1630 suffix_always is true.
1631 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1632 '!' => change condition from true to false or from false to true.
1633 '%' => add 1 upper case letter to the macro.
1635 2 upper case letter macros:
1636 "XY" => print 'x' or 'y' if no register operands or suffix_always
1637 is true.
1638 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1639 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1640 or suffix_always is true
1641 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1642 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1643 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1645 Many of the above letters print nothing in Intel mode. See "putop"
1646 for the details.
1648 Braces '{' and '}', and vertical bars '|', indicate alternative
1649 mnemonic strings for AT&T and Intel. */
1651 static const struct dis386 dis386[] = {
1652 /* 00 */
1653 { "addB", { Eb, Gb } },
1654 { "addS", { Ev, Gv } },
1655 { "addB", { Gb, EbS } },
1656 { "addS", { Gv, EvS } },
1657 { "addB", { AL, Ib } },
1658 { "addS", { eAX, Iv } },
1659 { X86_64_TABLE (X86_64_06) },
1660 { X86_64_TABLE (X86_64_07) },
1661 /* 08 */
1662 { "orB", { Eb, Gb } },
1663 { "orS", { Ev, Gv } },
1664 { "orB", { Gb, EbS } },
1665 { "orS", { Gv, EvS } },
1666 { "orB", { AL, Ib } },
1667 { "orS", { eAX, Iv } },
1668 { X86_64_TABLE (X86_64_0D) },
1669 { Bad_Opcode }, /* 0x0f extended opcode escape */
1670 /* 10 */
1671 { "adcB", { Eb, Gb } },
1672 { "adcS", { Ev, Gv } },
1673 { "adcB", { Gb, EbS } },
1674 { "adcS", { Gv, EvS } },
1675 { "adcB", { AL, Ib } },
1676 { "adcS", { eAX, Iv } },
1677 { X86_64_TABLE (X86_64_16) },
1678 { X86_64_TABLE (X86_64_17) },
1679 /* 18 */
1680 { "sbbB", { Eb, Gb } },
1681 { "sbbS", { Ev, Gv } },
1682 { "sbbB", { Gb, EbS } },
1683 { "sbbS", { Gv, EvS } },
1684 { "sbbB", { AL, Ib } },
1685 { "sbbS", { eAX, Iv } },
1686 { X86_64_TABLE (X86_64_1E) },
1687 { X86_64_TABLE (X86_64_1F) },
1688 /* 20 */
1689 { "andB", { Eb, Gb } },
1690 { "andS", { Ev, Gv } },
1691 { "andB", { Gb, EbS } },
1692 { "andS", { Gv, EvS } },
1693 { "andB", { AL, Ib } },
1694 { "andS", { eAX, Iv } },
1695 { Bad_Opcode }, /* SEG ES prefix */
1696 { X86_64_TABLE (X86_64_27) },
1697 /* 28 */
1698 { "subB", { Eb, Gb } },
1699 { "subS", { Ev, Gv } },
1700 { "subB", { Gb, EbS } },
1701 { "subS", { Gv, EvS } },
1702 { "subB", { AL, Ib } },
1703 { "subS", { eAX, Iv } },
1704 { Bad_Opcode }, /* SEG CS prefix */
1705 { X86_64_TABLE (X86_64_2F) },
1706 /* 30 */
1707 { "xorB", { Eb, Gb } },
1708 { "xorS", { Ev, Gv } },
1709 { "xorB", { Gb, EbS } },
1710 { "xorS", { Gv, EvS } },
1711 { "xorB", { AL, Ib } },
1712 { "xorS", { eAX, Iv } },
1713 { Bad_Opcode }, /* SEG SS prefix */
1714 { X86_64_TABLE (X86_64_37) },
1715 /* 38 */
1716 { "cmpB", { Eb, Gb } },
1717 { "cmpS", { Ev, Gv } },
1718 { "cmpB", { Gb, EbS } },
1719 { "cmpS", { Gv, EvS } },
1720 { "cmpB", { AL, Ib } },
1721 { "cmpS", { eAX, Iv } },
1722 { Bad_Opcode }, /* SEG DS prefix */
1723 { X86_64_TABLE (X86_64_3F) },
1724 /* 40 */
1725 { "inc{S|}", { RMeAX } },
1726 { "inc{S|}", { RMeCX } },
1727 { "inc{S|}", { RMeDX } },
1728 { "inc{S|}", { RMeBX } },
1729 { "inc{S|}", { RMeSP } },
1730 { "inc{S|}", { RMeBP } },
1731 { "inc{S|}", { RMeSI } },
1732 { "inc{S|}", { RMeDI } },
1733 /* 48 */
1734 { "dec{S|}", { RMeAX } },
1735 { "dec{S|}", { RMeCX } },
1736 { "dec{S|}", { RMeDX } },
1737 { "dec{S|}", { RMeBX } },
1738 { "dec{S|}", { RMeSP } },
1739 { "dec{S|}", { RMeBP } },
1740 { "dec{S|}", { RMeSI } },
1741 { "dec{S|}", { RMeDI } },
1742 /* 50 */
1743 { "pushV", { RMrAX } },
1744 { "pushV", { RMrCX } },
1745 { "pushV", { RMrDX } },
1746 { "pushV", { RMrBX } },
1747 { "pushV", { RMrSP } },
1748 { "pushV", { RMrBP } },
1749 { "pushV", { RMrSI } },
1750 { "pushV", { RMrDI } },
1751 /* 58 */
1752 { "popV", { RMrAX } },
1753 { "popV", { RMrCX } },
1754 { "popV", { RMrDX } },
1755 { "popV", { RMrBX } },
1756 { "popV", { RMrSP } },
1757 { "popV", { RMrBP } },
1758 { "popV", { RMrSI } },
1759 { "popV", { RMrDI } },
1760 /* 60 */
1761 { X86_64_TABLE (X86_64_60) },
1762 { X86_64_TABLE (X86_64_61) },
1763 { X86_64_TABLE (X86_64_62) },
1764 { X86_64_TABLE (X86_64_63) },
1765 { Bad_Opcode }, /* seg fs */
1766 { Bad_Opcode }, /* seg gs */
1767 { Bad_Opcode }, /* op size prefix */
1768 { Bad_Opcode }, /* adr size prefix */
1769 /* 68 */
1770 { "pushT", { Iq } },
1771 { "imulS", { Gv, Ev, Iv } },
1772 { "pushT", { sIb } },
1773 { "imulS", { Gv, Ev, sIb } },
1774 { "ins{b|}", { Ybr, indirDX } },
1775 { X86_64_TABLE (X86_64_6D) },
1776 { "outs{b|}", { indirDXr, Xb } },
1777 { X86_64_TABLE (X86_64_6F) },
1778 /* 70 */
1779 { "joH", { Jb, XX, cond_jump_flag } },
1780 { "jnoH", { Jb, XX, cond_jump_flag } },
1781 { "jbH", { Jb, XX, cond_jump_flag } },
1782 { "jaeH", { Jb, XX, cond_jump_flag } },
1783 { "jeH", { Jb, XX, cond_jump_flag } },
1784 { "jneH", { Jb, XX, cond_jump_flag } },
1785 { "jbeH", { Jb, XX, cond_jump_flag } },
1786 { "jaH", { Jb, XX, cond_jump_flag } },
1787 /* 78 */
1788 { "jsH", { Jb, XX, cond_jump_flag } },
1789 { "jnsH", { Jb, XX, cond_jump_flag } },
1790 { "jpH", { Jb, XX, cond_jump_flag } },
1791 { "jnpH", { Jb, XX, cond_jump_flag } },
1792 { "jlH", { Jb, XX, cond_jump_flag } },
1793 { "jgeH", { Jb, XX, cond_jump_flag } },
1794 { "jleH", { Jb, XX, cond_jump_flag } },
1795 { "jgH", { Jb, XX, cond_jump_flag } },
1796 /* 80 */
1797 { REG_TABLE (REG_80) },
1798 { REG_TABLE (REG_81) },
1799 { Bad_Opcode },
1800 { REG_TABLE (REG_82) },
1801 { "testB", { Eb, Gb } },
1802 { "testS", { Ev, Gv } },
1803 { "xchgB", { Eb, Gb } },
1804 { "xchgS", { Ev, Gv } },
1805 /* 88 */
1806 { "movB", { Eb, Gb } },
1807 { "movS", { Ev, Gv } },
1808 { "movB", { Gb, EbS } },
1809 { "movS", { Gv, EvS } },
1810 { "movD", { Sv, Sw } },
1811 { MOD_TABLE (MOD_8D) },
1812 { "movD", { Sw, Sv } },
1813 { REG_TABLE (REG_8F) },
1814 /* 90 */
1815 { PREFIX_TABLE (PREFIX_90) },
1816 { "xchgS", { RMeCX, eAX } },
1817 { "xchgS", { RMeDX, eAX } },
1818 { "xchgS", { RMeBX, eAX } },
1819 { "xchgS", { RMeSP, eAX } },
1820 { "xchgS", { RMeBP, eAX } },
1821 { "xchgS", { RMeSI, eAX } },
1822 { "xchgS", { RMeDI, eAX } },
1823 /* 98 */
1824 { "cW{t|}R", { XX } },
1825 { "cR{t|}O", { XX } },
1826 { X86_64_TABLE (X86_64_9A) },
1827 { Bad_Opcode }, /* fwait */
1828 { "pushfT", { XX } },
1829 { "popfT", { XX } },
1830 { "sahf", { XX } },
1831 { "lahf", { XX } },
1832 /* a0 */
1833 { "mov%LB", { AL, Ob } },
1834 { "mov%LS", { eAX, Ov } },
1835 { "mov%LB", { Ob, AL } },
1836 { "mov%LS", { Ov, eAX } },
1837 { "movs{b|}", { Ybr, Xb } },
1838 { "movs{R|}", { Yvr, Xv } },
1839 { "cmps{b|}", { Xb, Yb } },
1840 { "cmps{R|}", { Xv, Yv } },
1841 /* a8 */
1842 { "testB", { AL, Ib } },
1843 { "testS", { eAX, Iv } },
1844 { "stosB", { Ybr, AL } },
1845 { "stosS", { Yvr, eAX } },
1846 { "lodsB", { ALr, Xb } },
1847 { "lodsS", { eAXr, Xv } },
1848 { "scasB", { AL, Yb } },
1849 { "scasS", { eAX, Yv } },
1850 /* b0 */
1851 { "movB", { RMAL, Ib } },
1852 { "movB", { RMCL, Ib } },
1853 { "movB", { RMDL, Ib } },
1854 { "movB", { RMBL, Ib } },
1855 { "movB", { RMAH, Ib } },
1856 { "movB", { RMCH, Ib } },
1857 { "movB", { RMDH, Ib } },
1858 { "movB", { RMBH, Ib } },
1859 /* b8 */
1860 { "mov%LV", { RMeAX, Iv64 } },
1861 { "mov%LV", { RMeCX, Iv64 } },
1862 { "mov%LV", { RMeDX, Iv64 } },
1863 { "mov%LV", { RMeBX, Iv64 } },
1864 { "mov%LV", { RMeSP, Iv64 } },
1865 { "mov%LV", { RMeBP, Iv64 } },
1866 { "mov%LV", { RMeSI, Iv64 } },
1867 { "mov%LV", { RMeDI, Iv64 } },
1868 /* c0 */
1869 { REG_TABLE (REG_C0) },
1870 { REG_TABLE (REG_C1) },
1871 { "retT", { Iw } },
1872 { "retT", { XX } },
1873 { X86_64_TABLE (X86_64_C4) },
1874 { X86_64_TABLE (X86_64_C5) },
1875 { REG_TABLE (REG_C6) },
1876 { REG_TABLE (REG_C7) },
1877 /* c8 */
1878 { "enterT", { Iw, Ib } },
1879 { "leaveT", { XX } },
1880 { "Jret{|f}P", { Iw } },
1881 { "Jret{|f}P", { XX } },
1882 { "int3", { XX } },
1883 { "int", { Ib } },
1884 { X86_64_TABLE (X86_64_CE) },
1885 { "iretP", { XX } },
1886 /* d0 */
1887 { REG_TABLE (REG_D0) },
1888 { REG_TABLE (REG_D1) },
1889 { REG_TABLE (REG_D2) },
1890 { REG_TABLE (REG_D3) },
1891 { X86_64_TABLE (X86_64_D4) },
1892 { X86_64_TABLE (X86_64_D5) },
1893 { Bad_Opcode },
1894 { "xlat", { DSBX } },
1895 /* d8 */
1896 { FLOAT },
1897 { FLOAT },
1898 { FLOAT },
1899 { FLOAT },
1900 { FLOAT },
1901 { FLOAT },
1902 { FLOAT },
1903 { FLOAT },
1904 /* e0 */
1905 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1906 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1907 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1908 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1909 { "inB", { AL, Ib } },
1910 { "inG", { zAX, Ib } },
1911 { "outB", { Ib, AL } },
1912 { "outG", { Ib, zAX } },
1913 /* e8 */
1914 { "callT", { Jv } },
1915 { "jmpT", { Jv } },
1916 { X86_64_TABLE (X86_64_EA) },
1917 { "jmp", { Jb } },
1918 { "inB", { AL, indirDX } },
1919 { "inG", { zAX, indirDX } },
1920 { "outB", { indirDX, AL } },
1921 { "outG", { indirDX, zAX } },
1922 /* f0 */
1923 { Bad_Opcode }, /* lock prefix */
1924 { "icebp", { XX } },
1925 { Bad_Opcode }, /* repne */
1926 { Bad_Opcode }, /* repz */
1927 { "hlt", { XX } },
1928 { "cmc", { XX } },
1929 { REG_TABLE (REG_F6) },
1930 { REG_TABLE (REG_F7) },
1931 /* f8 */
1932 { "clc", { XX } },
1933 { "stc", { XX } },
1934 { "cli", { XX } },
1935 { "sti", { XX } },
1936 { "cld", { XX } },
1937 { "std", { XX } },
1938 { REG_TABLE (REG_FE) },
1939 { REG_TABLE (REG_FF) },
1942 static const struct dis386 dis386_twobyte[] = {
1943 /* 00 */
1944 { REG_TABLE (REG_0F00 ) },
1945 { REG_TABLE (REG_0F01 ) },
1946 { "larS", { Gv, Ew } },
1947 { "lslS", { Gv, Ew } },
1948 { Bad_Opcode },
1949 { "syscall", { XX } },
1950 { "clts", { XX } },
1951 { "sysretP", { XX } },
1952 /* 08 */
1953 { "invd", { XX } },
1954 { "wbinvd", { XX } },
1955 { Bad_Opcode },
1956 { "ud2a", { XX } },
1957 { Bad_Opcode },
1958 { REG_TABLE (REG_0F0D) },
1959 { "femms", { XX } },
1960 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1961 /* 10 */
1962 { PREFIX_TABLE (PREFIX_0F10) },
1963 { PREFIX_TABLE (PREFIX_0F11) },
1964 { PREFIX_TABLE (PREFIX_0F12) },
1965 { MOD_TABLE (MOD_0F13) },
1966 { "unpcklpX", { XM, EXx } },
1967 { "unpckhpX", { XM, EXx } },
1968 { PREFIX_TABLE (PREFIX_0F16) },
1969 { MOD_TABLE (MOD_0F17) },
1970 /* 18 */
1971 { REG_TABLE (REG_0F18) },
1972 { "nopQ", { Ev } },
1973 { "nopQ", { Ev } },
1974 { "nopQ", { Ev } },
1975 { "nopQ", { Ev } },
1976 { "nopQ", { Ev } },
1977 { "nopQ", { Ev } },
1978 { "nopQ", { Ev } },
1979 /* 20 */
1980 { MOD_TABLE (MOD_0F20) },
1981 { MOD_TABLE (MOD_0F21) },
1982 { MOD_TABLE (MOD_0F22) },
1983 { MOD_TABLE (MOD_0F23) },
1984 { MOD_TABLE (MOD_0F24) },
1985 { Bad_Opcode },
1986 { MOD_TABLE (MOD_0F26) },
1987 { Bad_Opcode },
1988 /* 28 */
1989 { "movapX", { XM, EXx } },
1990 { "movapX", { EXxS, XM } },
1991 { PREFIX_TABLE (PREFIX_0F2A) },
1992 { PREFIX_TABLE (PREFIX_0F2B) },
1993 { PREFIX_TABLE (PREFIX_0F2C) },
1994 { PREFIX_TABLE (PREFIX_0F2D) },
1995 { PREFIX_TABLE (PREFIX_0F2E) },
1996 { PREFIX_TABLE (PREFIX_0F2F) },
1997 /* 30 */
1998 { "wrmsr", { XX } },
1999 { "rdtsc", { XX } },
2000 { "rdmsr", { XX } },
2001 { "rdpmc", { XX } },
2002 { "sysenter", { XX } },
2003 { "sysexit", { XX } },
2004 { Bad_Opcode },
2005 { "getsec", { XX } },
2006 /* 38 */
2007 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2008 { Bad_Opcode },
2009 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2010 { Bad_Opcode },
2011 { Bad_Opcode },
2012 { Bad_Opcode },
2013 { Bad_Opcode },
2014 { Bad_Opcode },
2015 /* 40 */
2016 { "cmovoS", { Gv, Ev } },
2017 { "cmovnoS", { Gv, Ev } },
2018 { "cmovbS", { Gv, Ev } },
2019 { "cmovaeS", { Gv, Ev } },
2020 { "cmoveS", { Gv, Ev } },
2021 { "cmovneS", { Gv, Ev } },
2022 { "cmovbeS", { Gv, Ev } },
2023 { "cmovaS", { Gv, Ev } },
2024 /* 48 */
2025 { "cmovsS", { Gv, Ev } },
2026 { "cmovnsS", { Gv, Ev } },
2027 { "cmovpS", { Gv, Ev } },
2028 { "cmovnpS", { Gv, Ev } },
2029 { "cmovlS", { Gv, Ev } },
2030 { "cmovgeS", { Gv, Ev } },
2031 { "cmovleS", { Gv, Ev } },
2032 { "cmovgS", { Gv, Ev } },
2033 /* 50 */
2034 { MOD_TABLE (MOD_0F51) },
2035 { PREFIX_TABLE (PREFIX_0F51) },
2036 { PREFIX_TABLE (PREFIX_0F52) },
2037 { PREFIX_TABLE (PREFIX_0F53) },
2038 { "andpX", { XM, EXx } },
2039 { "andnpX", { XM, EXx } },
2040 { "orpX", { XM, EXx } },
2041 { "xorpX", { XM, EXx } },
2042 /* 58 */
2043 { PREFIX_TABLE (PREFIX_0F58) },
2044 { PREFIX_TABLE (PREFIX_0F59) },
2045 { PREFIX_TABLE (PREFIX_0F5A) },
2046 { PREFIX_TABLE (PREFIX_0F5B) },
2047 { PREFIX_TABLE (PREFIX_0F5C) },
2048 { PREFIX_TABLE (PREFIX_0F5D) },
2049 { PREFIX_TABLE (PREFIX_0F5E) },
2050 { PREFIX_TABLE (PREFIX_0F5F) },
2051 /* 60 */
2052 { PREFIX_TABLE (PREFIX_0F60) },
2053 { PREFIX_TABLE (PREFIX_0F61) },
2054 { PREFIX_TABLE (PREFIX_0F62) },
2055 { "packsswb", { MX, EM } },
2056 { "pcmpgtb", { MX, EM } },
2057 { "pcmpgtw", { MX, EM } },
2058 { "pcmpgtd", { MX, EM } },
2059 { "packuswb", { MX, EM } },
2060 /* 68 */
2061 { "punpckhbw", { MX, EM } },
2062 { "punpckhwd", { MX, EM } },
2063 { "punpckhdq", { MX, EM } },
2064 { "packssdw", { MX, EM } },
2065 { PREFIX_TABLE (PREFIX_0F6C) },
2066 { PREFIX_TABLE (PREFIX_0F6D) },
2067 { "movK", { MX, Edq } },
2068 { PREFIX_TABLE (PREFIX_0F6F) },
2069 /* 70 */
2070 { PREFIX_TABLE (PREFIX_0F70) },
2071 { REG_TABLE (REG_0F71) },
2072 { REG_TABLE (REG_0F72) },
2073 { REG_TABLE (REG_0F73) },
2074 { "pcmpeqb", { MX, EM } },
2075 { "pcmpeqw", { MX, EM } },
2076 { "pcmpeqd", { MX, EM } },
2077 { "emms", { XX } },
2078 /* 78 */
2079 { PREFIX_TABLE (PREFIX_0F78) },
2080 { PREFIX_TABLE (PREFIX_0F79) },
2081 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2082 { Bad_Opcode },
2083 { PREFIX_TABLE (PREFIX_0F7C) },
2084 { PREFIX_TABLE (PREFIX_0F7D) },
2085 { PREFIX_TABLE (PREFIX_0F7E) },
2086 { PREFIX_TABLE (PREFIX_0F7F) },
2087 /* 80 */
2088 { "joH", { Jv, XX, cond_jump_flag } },
2089 { "jnoH", { Jv, XX, cond_jump_flag } },
2090 { "jbH", { Jv, XX, cond_jump_flag } },
2091 { "jaeH", { Jv, XX, cond_jump_flag } },
2092 { "jeH", { Jv, XX, cond_jump_flag } },
2093 { "jneH", { Jv, XX, cond_jump_flag } },
2094 { "jbeH", { Jv, XX, cond_jump_flag } },
2095 { "jaH", { Jv, XX, cond_jump_flag } },
2096 /* 88 */
2097 { "jsH", { Jv, XX, cond_jump_flag } },
2098 { "jnsH", { Jv, XX, cond_jump_flag } },
2099 { "jpH", { Jv, XX, cond_jump_flag } },
2100 { "jnpH", { Jv, XX, cond_jump_flag } },
2101 { "jlH", { Jv, XX, cond_jump_flag } },
2102 { "jgeH", { Jv, XX, cond_jump_flag } },
2103 { "jleH", { Jv, XX, cond_jump_flag } },
2104 { "jgH", { Jv, XX, cond_jump_flag } },
2105 /* 90 */
2106 { "seto", { Eb } },
2107 { "setno", { Eb } },
2108 { "setb", { Eb } },
2109 { "setae", { Eb } },
2110 { "sete", { Eb } },
2111 { "setne", { Eb } },
2112 { "setbe", { Eb } },
2113 { "seta", { Eb } },
2114 /* 98 */
2115 { "sets", { Eb } },
2116 { "setns", { Eb } },
2117 { "setp", { Eb } },
2118 { "setnp", { Eb } },
2119 { "setl", { Eb } },
2120 { "setge", { Eb } },
2121 { "setle", { Eb } },
2122 { "setg", { Eb } },
2123 /* a0 */
2124 { "pushT", { fs } },
2125 { "popT", { fs } },
2126 { "cpuid", { XX } },
2127 { "btS", { Ev, Gv } },
2128 { "shldS", { Ev, Gv, Ib } },
2129 { "shldS", { Ev, Gv, CL } },
2130 { REG_TABLE (REG_0FA6) },
2131 { REG_TABLE (REG_0FA7) },
2132 /* a8 */
2133 { "pushT", { gs } },
2134 { "popT", { gs } },
2135 { "rsm", { XX } },
2136 { "btsS", { Ev, Gv } },
2137 { "shrdS", { Ev, Gv, Ib } },
2138 { "shrdS", { Ev, Gv, CL } },
2139 { REG_TABLE (REG_0FAE) },
2140 { "imulS", { Gv, Ev } },
2141 /* b0 */
2142 { "cmpxchgB", { Eb, Gb } },
2143 { "cmpxchgS", { Ev, Gv } },
2144 { MOD_TABLE (MOD_0FB2) },
2145 { "btrS", { Ev, Gv } },
2146 { MOD_TABLE (MOD_0FB4) },
2147 { MOD_TABLE (MOD_0FB5) },
2148 { "movz{bR|x}", { Gv, Eb } },
2149 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2150 /* b8 */
2151 { PREFIX_TABLE (PREFIX_0FB8) },
2152 { "ud2b", { XX } },
2153 { REG_TABLE (REG_0FBA) },
2154 { "btcS", { Ev, Gv } },
2155 { "bsfS", { Gv, Ev } },
2156 { PREFIX_TABLE (PREFIX_0FBD) },
2157 { "movs{bR|x}", { Gv, Eb } },
2158 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2159 /* c0 */
2160 { "xaddB", { Eb, Gb } },
2161 { "xaddS", { Ev, Gv } },
2162 { PREFIX_TABLE (PREFIX_0FC2) },
2163 { PREFIX_TABLE (PREFIX_0FC3) },
2164 { "pinsrw", { MX, Edqw, Ib } },
2165 { "pextrw", { Gdq, MS, Ib } },
2166 { "shufpX", { XM, EXx, Ib } },
2167 { REG_TABLE (REG_0FC7) },
2168 /* c8 */
2169 { "bswap", { RMeAX } },
2170 { "bswap", { RMeCX } },
2171 { "bswap", { RMeDX } },
2172 { "bswap", { RMeBX } },
2173 { "bswap", { RMeSP } },
2174 { "bswap", { RMeBP } },
2175 { "bswap", { RMeSI } },
2176 { "bswap", { RMeDI } },
2177 /* d0 */
2178 { PREFIX_TABLE (PREFIX_0FD0) },
2179 { "psrlw", { MX, EM } },
2180 { "psrld", { MX, EM } },
2181 { "psrlq", { MX, EM } },
2182 { "paddq", { MX, EM } },
2183 { "pmullw", { MX, EM } },
2184 { PREFIX_TABLE (PREFIX_0FD6) },
2185 { MOD_TABLE (MOD_0FD7) },
2186 /* d8 */
2187 { "psubusb", { MX, EM } },
2188 { "psubusw", { MX, EM } },
2189 { "pminub", { MX, EM } },
2190 { "pand", { MX, EM } },
2191 { "paddusb", { MX, EM } },
2192 { "paddusw", { MX, EM } },
2193 { "pmaxub", { MX, EM } },
2194 { "pandn", { MX, EM } },
2195 /* e0 */
2196 { "pavgb", { MX, EM } },
2197 { "psraw", { MX, EM } },
2198 { "psrad", { MX, EM } },
2199 { "pavgw", { MX, EM } },
2200 { "pmulhuw", { MX, EM } },
2201 { "pmulhw", { MX, EM } },
2202 { PREFIX_TABLE (PREFIX_0FE6) },
2203 { PREFIX_TABLE (PREFIX_0FE7) },
2204 /* e8 */
2205 { "psubsb", { MX, EM } },
2206 { "psubsw", { MX, EM } },
2207 { "pminsw", { MX, EM } },
2208 { "por", { MX, EM } },
2209 { "paddsb", { MX, EM } },
2210 { "paddsw", { MX, EM } },
2211 { "pmaxsw", { MX, EM } },
2212 { "pxor", { MX, EM } },
2213 /* f0 */
2214 { PREFIX_TABLE (PREFIX_0FF0) },
2215 { "psllw", { MX, EM } },
2216 { "pslld", { MX, EM } },
2217 { "psllq", { MX, EM } },
2218 { "pmuludq", { MX, EM } },
2219 { "pmaddwd", { MX, EM } },
2220 { "psadbw", { MX, EM } },
2221 { PREFIX_TABLE (PREFIX_0FF7) },
2222 /* f8 */
2223 { "psubb", { MX, EM } },
2224 { "psubw", { MX, EM } },
2225 { "psubd", { MX, EM } },
2226 { "psubq", { MX, EM } },
2227 { "paddb", { MX, EM } },
2228 { "paddw", { MX, EM } },
2229 { "paddd", { MX, EM } },
2230 { Bad_Opcode },
2233 static const unsigned char onebyte_has_modrm[256] = {
2234 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2235 /* ------------------------------- */
2236 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2237 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2238 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2239 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2240 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2241 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2242 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2243 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2244 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2245 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2246 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2247 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2248 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2249 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2250 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2251 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2252 /* ------------------------------- */
2253 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2256 static const unsigned char twobyte_has_modrm[256] = {
2257 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2258 /* ------------------------------- */
2259 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2260 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2261 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2262 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2263 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2264 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2265 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2266 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2267 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2268 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2269 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2270 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2271 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2272 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2273 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2274 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2275 /* ------------------------------- */
2276 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2279 static char obuf[100];
2280 static char *obufp;
2281 static char *mnemonicendp;
2282 static char scratchbuf[100];
2283 static unsigned char *start_codep;
2284 static unsigned char *insn_codep;
2285 static unsigned char *codep;
2286 static int last_lock_prefix;
2287 static int last_repz_prefix;
2288 static int last_repnz_prefix;
2289 static int last_data_prefix;
2290 static int last_addr_prefix;
2291 static int last_rex_prefix;
2292 static int last_seg_prefix;
2293 #define MAX_CODE_LENGTH 15
2294 /* We can up to 14 prefixes since the maximum instruction length is
2295 15bytes. */
2296 static int all_prefixes[MAX_CODE_LENGTH - 1];
2297 static disassemble_info *the_info;
2298 static struct
2300 int mod;
2301 int reg;
2302 int rm;
2304 modrm;
2305 static unsigned char need_modrm;
2306 static struct
2308 int register_specifier;
2309 int length;
2310 int prefix;
2311 int w;
2313 vex;
2314 static unsigned char need_vex;
2315 static unsigned char need_vex_reg;
2316 static unsigned char vex_w_done;
2318 struct op
2320 const char *name;
2321 unsigned int len;
2324 /* If we are accessing mod/rm/reg without need_modrm set, then the
2325 values are stale. Hitting this abort likely indicates that you
2326 need to update onebyte_has_modrm or twobyte_has_modrm. */
2327 #define MODRM_CHECK if (!need_modrm) abort ()
2329 static const char **names64;
2330 static const char **names32;
2331 static const char **names16;
2332 static const char **names8;
2333 static const char **names8rex;
2334 static const char **names_seg;
2335 static const char *index64;
2336 static const char *index32;
2337 static const char **index16;
2339 static const char *intel_names64[] = {
2340 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2341 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2343 static const char *intel_names32[] = {
2344 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2345 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2347 static const char *intel_names16[] = {
2348 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2349 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2351 static const char *intel_names8[] = {
2352 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2354 static const char *intel_names8rex[] = {
2355 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2356 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2358 static const char *intel_names_seg[] = {
2359 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2361 static const char *intel_index64 = "riz";
2362 static const char *intel_index32 = "eiz";
2363 static const char *intel_index16[] = {
2364 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2367 static const char *att_names64[] = {
2368 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2369 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2371 static const char *att_names32[] = {
2372 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2373 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2375 static const char *att_names16[] = {
2376 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2377 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2379 static const char *att_names8[] = {
2380 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2382 static const char *att_names8rex[] = {
2383 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2384 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2386 static const char *att_names_seg[] = {
2387 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2389 static const char *att_index64 = "%riz";
2390 static const char *att_index32 = "%eiz";
2391 static const char *att_index16[] = {
2392 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2395 static const char **names_mm;
2396 static const char *intel_names_mm[] = {
2397 "mm0", "mm1", "mm2", "mm3",
2398 "mm4", "mm5", "mm6", "mm7"
2400 static const char *att_names_mm[] = {
2401 "%mm0", "%mm1", "%mm2", "%mm3",
2402 "%mm4", "%mm5", "%mm6", "%mm7"
2405 static const char **names_xmm;
2406 static const char *intel_names_xmm[] = {
2407 "xmm0", "xmm1", "xmm2", "xmm3",
2408 "xmm4", "xmm5", "xmm6", "xmm7",
2409 "xmm8", "xmm9", "xmm10", "xmm11",
2410 "xmm12", "xmm13", "xmm14", "xmm15"
2412 static const char *att_names_xmm[] = {
2413 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2414 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2415 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2416 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2419 static const char **names_ymm;
2420 static const char *intel_names_ymm[] = {
2421 "ymm0", "ymm1", "ymm2", "ymm3",
2422 "ymm4", "ymm5", "ymm6", "ymm7",
2423 "ymm8", "ymm9", "ymm10", "ymm11",
2424 "ymm12", "ymm13", "ymm14", "ymm15"
2426 static const char *att_names_ymm[] = {
2427 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2428 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2429 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2430 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2433 static const struct dis386 reg_table[][8] = {
2434 /* REG_80 */
2436 { "addA", { Eb, Ib } },
2437 { "orA", { Eb, Ib } },
2438 { "adcA", { Eb, Ib } },
2439 { "sbbA", { Eb, Ib } },
2440 { "andA", { Eb, Ib } },
2441 { "subA", { Eb, Ib } },
2442 { "xorA", { Eb, Ib } },
2443 { "cmpA", { Eb, Ib } },
2445 /* REG_81 */
2447 { "addQ", { Ev, Iv } },
2448 { "orQ", { Ev, Iv } },
2449 { "adcQ", { Ev, Iv } },
2450 { "sbbQ", { Ev, Iv } },
2451 { "andQ", { Ev, Iv } },
2452 { "subQ", { Ev, Iv } },
2453 { "xorQ", { Ev, Iv } },
2454 { "cmpQ", { Ev, Iv } },
2456 /* REG_82 */
2458 { "addQ", { Ev, sIb } },
2459 { "orQ", { Ev, sIb } },
2460 { "adcQ", { Ev, sIb } },
2461 { "sbbQ", { Ev, sIb } },
2462 { "andQ", { Ev, sIb } },
2463 { "subQ", { Ev, sIb } },
2464 { "xorQ", { Ev, sIb } },
2465 { "cmpQ", { Ev, sIb } },
2467 /* REG_8F */
2469 { "popU", { stackEv } },
2470 { XOP_8F_TABLE (XOP_09) },
2471 { Bad_Opcode },
2472 { Bad_Opcode },
2473 { Bad_Opcode },
2474 { XOP_8F_TABLE (XOP_09) },
2476 /* REG_C0 */
2478 { "rolA", { Eb, Ib } },
2479 { "rorA", { Eb, Ib } },
2480 { "rclA", { Eb, Ib } },
2481 { "rcrA", { Eb, Ib } },
2482 { "shlA", { Eb, Ib } },
2483 { "shrA", { Eb, Ib } },
2484 { Bad_Opcode },
2485 { "sarA", { Eb, Ib } },
2487 /* REG_C1 */
2489 { "rolQ", { Ev, Ib } },
2490 { "rorQ", { Ev, Ib } },
2491 { "rclQ", { Ev, Ib } },
2492 { "rcrQ", { Ev, Ib } },
2493 { "shlQ", { Ev, Ib } },
2494 { "shrQ", { Ev, Ib } },
2495 { Bad_Opcode },
2496 { "sarQ", { Ev, Ib } },
2498 /* REG_C6 */
2500 { "movA", { Eb, Ib } },
2502 /* REG_C7 */
2504 { "movQ", { Ev, Iv } },
2506 /* REG_D0 */
2508 { "rolA", { Eb, I1 } },
2509 { "rorA", { Eb, I1 } },
2510 { "rclA", { Eb, I1 } },
2511 { "rcrA", { Eb, I1 } },
2512 { "shlA", { Eb, I1 } },
2513 { "shrA", { Eb, I1 } },
2514 { Bad_Opcode },
2515 { "sarA", { Eb, I1 } },
2517 /* REG_D1 */
2519 { "rolQ", { Ev, I1 } },
2520 { "rorQ", { Ev, I1 } },
2521 { "rclQ", { Ev, I1 } },
2522 { "rcrQ", { Ev, I1 } },
2523 { "shlQ", { Ev, I1 } },
2524 { "shrQ", { Ev, I1 } },
2525 { Bad_Opcode },
2526 { "sarQ", { Ev, I1 } },
2528 /* REG_D2 */
2530 { "rolA", { Eb, CL } },
2531 { "rorA", { Eb, CL } },
2532 { "rclA", { Eb, CL } },
2533 { "rcrA", { Eb, CL } },
2534 { "shlA", { Eb, CL } },
2535 { "shrA", { Eb, CL } },
2536 { Bad_Opcode },
2537 { "sarA", { Eb, CL } },
2539 /* REG_D3 */
2541 { "rolQ", { Ev, CL } },
2542 { "rorQ", { Ev, CL } },
2543 { "rclQ", { Ev, CL } },
2544 { "rcrQ", { Ev, CL } },
2545 { "shlQ", { Ev, CL } },
2546 { "shrQ", { Ev, CL } },
2547 { Bad_Opcode },
2548 { "sarQ", { Ev, CL } },
2550 /* REG_F6 */
2552 { "testA", { Eb, Ib } },
2553 { Bad_Opcode },
2554 { "notA", { Eb } },
2555 { "negA", { Eb } },
2556 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2557 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2558 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2559 { "idivA", { Eb } }, /* and idiv for consistency. */
2561 /* REG_F7 */
2563 { "testQ", { Ev, Iv } },
2564 { Bad_Opcode },
2565 { "notQ", { Ev } },
2566 { "negQ", { Ev } },
2567 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2568 { "imulQ", { Ev } },
2569 { "divQ", { Ev } },
2570 { "idivQ", { Ev } },
2572 /* REG_FE */
2574 { "incA", { Eb } },
2575 { "decA", { Eb } },
2577 /* REG_FF */
2579 { "incQ", { Ev } },
2580 { "decQ", { Ev } },
2581 { "callT", { indirEv } },
2582 { "JcallT", { indirEp } },
2583 { "jmpT", { indirEv } },
2584 { "JjmpT", { indirEp } },
2585 { "pushU", { stackEv } },
2586 { Bad_Opcode },
2588 /* REG_0F00 */
2590 { "sldtD", { Sv } },
2591 { "strD", { Sv } },
2592 { "lldt", { Ew } },
2593 { "ltr", { Ew } },
2594 { "verr", { Ew } },
2595 { "verw", { Ew } },
2596 { Bad_Opcode },
2597 { Bad_Opcode },
2599 /* REG_0F01 */
2601 { MOD_TABLE (MOD_0F01_REG_0) },
2602 { MOD_TABLE (MOD_0F01_REG_1) },
2603 { MOD_TABLE (MOD_0F01_REG_2) },
2604 { MOD_TABLE (MOD_0F01_REG_3) },
2605 { "smswD", { Sv } },
2606 { Bad_Opcode },
2607 { "lmsw", { Ew } },
2608 { MOD_TABLE (MOD_0F01_REG_7) },
2610 /* REG_0F0D */
2612 { "prefetch", { Eb } },
2613 { "prefetchw", { Eb } },
2615 /* REG_0F18 */
2617 { MOD_TABLE (MOD_0F18_REG_0) },
2618 { MOD_TABLE (MOD_0F18_REG_1) },
2619 { MOD_TABLE (MOD_0F18_REG_2) },
2620 { MOD_TABLE (MOD_0F18_REG_3) },
2622 /* REG_0F71 */
2624 { Bad_Opcode },
2625 { Bad_Opcode },
2626 { MOD_TABLE (MOD_0F71_REG_2) },
2627 { Bad_Opcode },
2628 { MOD_TABLE (MOD_0F71_REG_4) },
2629 { Bad_Opcode },
2630 { MOD_TABLE (MOD_0F71_REG_6) },
2632 /* REG_0F72 */
2634 { Bad_Opcode },
2635 { Bad_Opcode },
2636 { MOD_TABLE (MOD_0F72_REG_2) },
2637 { Bad_Opcode },
2638 { MOD_TABLE (MOD_0F72_REG_4) },
2639 { Bad_Opcode },
2640 { MOD_TABLE (MOD_0F72_REG_6) },
2642 /* REG_0F73 */
2644 { Bad_Opcode },
2645 { Bad_Opcode },
2646 { MOD_TABLE (MOD_0F73_REG_2) },
2647 { MOD_TABLE (MOD_0F73_REG_3) },
2648 { Bad_Opcode },
2649 { Bad_Opcode },
2650 { MOD_TABLE (MOD_0F73_REG_6) },
2651 { MOD_TABLE (MOD_0F73_REG_7) },
2653 /* REG_0FA6 */
2655 { "montmul", { { OP_0f07, 0 } } },
2656 { "xsha1", { { OP_0f07, 0 } } },
2657 { "xsha256", { { OP_0f07, 0 } } },
2659 /* REG_0FA7 */
2661 { "xstore-rng", { { OP_0f07, 0 } } },
2662 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2663 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2664 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2665 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2666 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2668 /* REG_0FAE */
2670 { MOD_TABLE (MOD_0FAE_REG_0) },
2671 { MOD_TABLE (MOD_0FAE_REG_1) },
2672 { MOD_TABLE (MOD_0FAE_REG_2) },
2673 { MOD_TABLE (MOD_0FAE_REG_3) },
2674 { MOD_TABLE (MOD_0FAE_REG_4) },
2675 { MOD_TABLE (MOD_0FAE_REG_5) },
2676 { MOD_TABLE (MOD_0FAE_REG_6) },
2677 { MOD_TABLE (MOD_0FAE_REG_7) },
2679 /* REG_0FBA */
2681 { Bad_Opcode },
2682 { Bad_Opcode },
2683 { Bad_Opcode },
2684 { Bad_Opcode },
2685 { "btQ", { Ev, Ib } },
2686 { "btsQ", { Ev, Ib } },
2687 { "btrQ", { Ev, Ib } },
2688 { "btcQ", { Ev, Ib } },
2690 /* REG_0FC7 */
2692 { Bad_Opcode },
2693 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2694 { Bad_Opcode },
2695 { Bad_Opcode },
2696 { Bad_Opcode },
2697 { Bad_Opcode },
2698 { MOD_TABLE (MOD_0FC7_REG_6) },
2699 { MOD_TABLE (MOD_0FC7_REG_7) },
2701 /* REG_VEX_71 */
2703 { Bad_Opcode },
2704 { Bad_Opcode },
2705 { MOD_TABLE (MOD_VEX_71_REG_2) },
2706 { Bad_Opcode },
2707 { MOD_TABLE (MOD_VEX_71_REG_4) },
2708 { Bad_Opcode },
2709 { MOD_TABLE (MOD_VEX_71_REG_6) },
2711 /* REG_VEX_72 */
2713 { Bad_Opcode },
2714 { Bad_Opcode },
2715 { MOD_TABLE (MOD_VEX_72_REG_2) },
2716 { Bad_Opcode },
2717 { MOD_TABLE (MOD_VEX_72_REG_4) },
2718 { Bad_Opcode },
2719 { MOD_TABLE (MOD_VEX_72_REG_6) },
2721 /* REG_VEX_73 */
2723 { Bad_Opcode },
2724 { Bad_Opcode },
2725 { MOD_TABLE (MOD_VEX_73_REG_2) },
2726 { MOD_TABLE (MOD_VEX_73_REG_3) },
2727 { Bad_Opcode },
2728 { Bad_Opcode },
2729 { MOD_TABLE (MOD_VEX_73_REG_6) },
2730 { MOD_TABLE (MOD_VEX_73_REG_7) },
2732 /* REG_VEX_AE */
2734 { Bad_Opcode },
2735 { Bad_Opcode },
2736 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2737 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2739 /* REG_XOP_LWPCB */
2741 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2742 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2744 /* REG_XOP_LWP */
2746 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2747 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2751 static const struct dis386 prefix_table[][4] = {
2752 /* PREFIX_90 */
2754 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2755 { "pause", { XX } },
2756 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2759 /* PREFIX_0F10 */
2761 { "movups", { XM, EXx } },
2762 { "movss", { XM, EXd } },
2763 { "movupd", { XM, EXx } },
2764 { "movsd", { XM, EXq } },
2767 /* PREFIX_0F11 */
2769 { "movups", { EXxS, XM } },
2770 { "movss", { EXdS, XM } },
2771 { "movupd", { EXxS, XM } },
2772 { "movsd", { EXqS, XM } },
2775 /* PREFIX_0F12 */
2777 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2778 { "movsldup", { XM, EXx } },
2779 { "movlpd", { XM, EXq } },
2780 { "movddup", { XM, EXq } },
2783 /* PREFIX_0F16 */
2785 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2786 { "movshdup", { XM, EXx } },
2787 { "movhpd", { XM, EXq } },
2790 /* PREFIX_0F2A */
2792 { "cvtpi2ps", { XM, EMCq } },
2793 { "cvtsi2ss%LQ", { XM, Ev } },
2794 { "cvtpi2pd", { XM, EMCq } },
2795 { "cvtsi2sd%LQ", { XM, Ev } },
2798 /* PREFIX_0F2B */
2800 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2801 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2802 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2803 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2806 /* PREFIX_0F2C */
2808 { "cvttps2pi", { MXC, EXq } },
2809 { "cvttss2siY", { Gv, EXd } },
2810 { "cvttpd2pi", { MXC, EXx } },
2811 { "cvttsd2siY", { Gv, EXq } },
2814 /* PREFIX_0F2D */
2816 { "cvtps2pi", { MXC, EXq } },
2817 { "cvtss2siY", { Gv, EXd } },
2818 { "cvtpd2pi", { MXC, EXx } },
2819 { "cvtsd2siY", { Gv, EXq } },
2822 /* PREFIX_0F2E */
2824 { "ucomiss",{ XM, EXd } },
2825 { Bad_Opcode },
2826 { "ucomisd",{ XM, EXq } },
2829 /* PREFIX_0F2F */
2831 { "comiss", { XM, EXd } },
2832 { Bad_Opcode },
2833 { "comisd", { XM, EXq } },
2836 /* PREFIX_0F51 */
2838 { "sqrtps", { XM, EXx } },
2839 { "sqrtss", { XM, EXd } },
2840 { "sqrtpd", { XM, EXx } },
2841 { "sqrtsd", { XM, EXq } },
2844 /* PREFIX_0F52 */
2846 { "rsqrtps",{ XM, EXx } },
2847 { "rsqrtss",{ XM, EXd } },
2850 /* PREFIX_0F53 */
2852 { "rcpps", { XM, EXx } },
2853 { "rcpss", { XM, EXd } },
2856 /* PREFIX_0F58 */
2858 { "addps", { XM, EXx } },
2859 { "addss", { XM, EXd } },
2860 { "addpd", { XM, EXx } },
2861 { "addsd", { XM, EXq } },
2864 /* PREFIX_0F59 */
2866 { "mulps", { XM, EXx } },
2867 { "mulss", { XM, EXd } },
2868 { "mulpd", { XM, EXx } },
2869 { "mulsd", { XM, EXq } },
2872 /* PREFIX_0F5A */
2874 { "cvtps2pd", { XM, EXq } },
2875 { "cvtss2sd", { XM, EXd } },
2876 { "cvtpd2ps", { XM, EXx } },
2877 { "cvtsd2ss", { XM, EXq } },
2880 /* PREFIX_0F5B */
2882 { "cvtdq2ps", { XM, EXx } },
2883 { "cvttps2dq", { XM, EXx } },
2884 { "cvtps2dq", { XM, EXx } },
2887 /* PREFIX_0F5C */
2889 { "subps", { XM, EXx } },
2890 { "subss", { XM, EXd } },
2891 { "subpd", { XM, EXx } },
2892 { "subsd", { XM, EXq } },
2895 /* PREFIX_0F5D */
2897 { "minps", { XM, EXx } },
2898 { "minss", { XM, EXd } },
2899 { "minpd", { XM, EXx } },
2900 { "minsd", { XM, EXq } },
2903 /* PREFIX_0F5E */
2905 { "divps", { XM, EXx } },
2906 { "divss", { XM, EXd } },
2907 { "divpd", { XM, EXx } },
2908 { "divsd", { XM, EXq } },
2911 /* PREFIX_0F5F */
2913 { "maxps", { XM, EXx } },
2914 { "maxss", { XM, EXd } },
2915 { "maxpd", { XM, EXx } },
2916 { "maxsd", { XM, EXq } },
2919 /* PREFIX_0F60 */
2921 { "punpcklbw",{ MX, EMd } },
2922 { Bad_Opcode },
2923 { "punpcklbw",{ MX, EMx } },
2926 /* PREFIX_0F61 */
2928 { "punpcklwd",{ MX, EMd } },
2929 { Bad_Opcode },
2930 { "punpcklwd",{ MX, EMx } },
2933 /* PREFIX_0F62 */
2935 { "punpckldq",{ MX, EMd } },
2936 { Bad_Opcode },
2937 { "punpckldq",{ MX, EMx } },
2940 /* PREFIX_0F6C */
2942 { Bad_Opcode },
2943 { Bad_Opcode },
2944 { "punpcklqdq", { XM, EXx } },
2947 /* PREFIX_0F6D */
2949 { Bad_Opcode },
2950 { Bad_Opcode },
2951 { "punpckhqdq", { XM, EXx } },
2954 /* PREFIX_0F6F */
2956 { "movq", { MX, EM } },
2957 { "movdqu", { XM, EXx } },
2958 { "movdqa", { XM, EXx } },
2961 /* PREFIX_0F70 */
2963 { "pshufw", { MX, EM, Ib } },
2964 { "pshufhw",{ XM, EXx, Ib } },
2965 { "pshufd", { XM, EXx, Ib } },
2966 { "pshuflw",{ XM, EXx, Ib } },
2969 /* PREFIX_0F73_REG_3 */
2971 { Bad_Opcode },
2972 { Bad_Opcode },
2973 { "psrldq", { XS, Ib } },
2976 /* PREFIX_0F73_REG_7 */
2978 { Bad_Opcode },
2979 { Bad_Opcode },
2980 { "pslldq", { XS, Ib } },
2983 /* PREFIX_0F78 */
2985 {"vmread", { Em, Gm } },
2986 { Bad_Opcode },
2987 {"extrq", { XS, Ib, Ib } },
2988 {"insertq", { XM, XS, Ib, Ib } },
2991 /* PREFIX_0F79 */
2993 {"vmwrite", { Gm, Em } },
2994 { Bad_Opcode },
2995 {"extrq", { XM, XS } },
2996 {"insertq", { XM, XS } },
2999 /* PREFIX_0F7C */
3001 { Bad_Opcode },
3002 { Bad_Opcode },
3003 { "haddpd", { XM, EXx } },
3004 { "haddps", { XM, EXx } },
3007 /* PREFIX_0F7D */
3009 { Bad_Opcode },
3010 { Bad_Opcode },
3011 { "hsubpd", { XM, EXx } },
3012 { "hsubps", { XM, EXx } },
3015 /* PREFIX_0F7E */
3017 { "movK", { Edq, MX } },
3018 { "movq", { XM, EXq } },
3019 { "movK", { Edq, XM } },
3022 /* PREFIX_0F7F */
3024 { "movq", { EMS, MX } },
3025 { "movdqu", { EXxS, XM } },
3026 { "movdqa", { EXxS, XM } },
3029 /* PREFIX_0FB8 */
3031 { Bad_Opcode },
3032 { "popcntS", { Gv, Ev } },
3035 /* PREFIX_0FBD */
3037 { "bsrS", { Gv, Ev } },
3038 { "lzcntS", { Gv, Ev } },
3039 { "bsrS", { Gv, Ev } },
3042 /* PREFIX_0FC2 */
3044 { "cmpps", { XM, EXx, CMP } },
3045 { "cmpss", { XM, EXd, CMP } },
3046 { "cmppd", { XM, EXx, CMP } },
3047 { "cmpsd", { XM, EXq, CMP } },
3050 /* PREFIX_0FC3 */
3052 { "movntiS", { Ma, Gv } },
3055 /* PREFIX_0FC7_REG_6 */
3057 { "vmptrld",{ Mq } },
3058 { "vmxon", { Mq } },
3059 { "vmclear",{ Mq } },
3062 /* PREFIX_0FD0 */
3064 { Bad_Opcode },
3065 { Bad_Opcode },
3066 { "addsubpd", { XM, EXx } },
3067 { "addsubps", { XM, EXx } },
3070 /* PREFIX_0FD6 */
3072 { Bad_Opcode },
3073 { "movq2dq",{ XM, MS } },
3074 { "movq", { EXqS, XM } },
3075 { "movdq2q",{ MX, XS } },
3078 /* PREFIX_0FE6 */
3080 { Bad_Opcode },
3081 { "cvtdq2pd", { XM, EXq } },
3082 { "cvttpd2dq", { XM, EXx } },
3083 { "cvtpd2dq", { XM, EXx } },
3086 /* PREFIX_0FE7 */
3088 { "movntq", { Mq, MX } },
3089 { Bad_Opcode },
3090 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3093 /* PREFIX_0FF0 */
3095 { Bad_Opcode },
3096 { Bad_Opcode },
3097 { Bad_Opcode },
3098 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3101 /* PREFIX_0FF7 */
3103 { "maskmovq", { MX, MS } },
3104 { Bad_Opcode },
3105 { "maskmovdqu", { XM, XS } },
3108 /* PREFIX_0F3810 */
3110 { Bad_Opcode },
3111 { Bad_Opcode },
3112 { "pblendvb", { XM, EXx, XMM0 } },
3115 /* PREFIX_0F3814 */
3117 { Bad_Opcode },
3118 { Bad_Opcode },
3119 { "blendvps", { XM, EXx, XMM0 } },
3122 /* PREFIX_0F3815 */
3124 { Bad_Opcode },
3125 { Bad_Opcode },
3126 { "blendvpd", { XM, EXx, XMM0 } },
3129 /* PREFIX_0F3817 */
3131 { Bad_Opcode },
3132 { Bad_Opcode },
3133 { "ptest", { XM, EXx } },
3136 /* PREFIX_0F3820 */
3138 { Bad_Opcode },
3139 { Bad_Opcode },
3140 { "pmovsxbw", { XM, EXq } },
3143 /* PREFIX_0F3821 */
3145 { Bad_Opcode },
3146 { Bad_Opcode },
3147 { "pmovsxbd", { XM, EXd } },
3150 /* PREFIX_0F3822 */
3152 { Bad_Opcode },
3153 { Bad_Opcode },
3154 { "pmovsxbq", { XM, EXw } },
3157 /* PREFIX_0F3823 */
3159 { Bad_Opcode },
3160 { Bad_Opcode },
3161 { "pmovsxwd", { XM, EXq } },
3164 /* PREFIX_0F3824 */
3166 { Bad_Opcode },
3167 { Bad_Opcode },
3168 { "pmovsxwq", { XM, EXd } },
3171 /* PREFIX_0F3825 */
3173 { Bad_Opcode },
3174 { Bad_Opcode },
3175 { "pmovsxdq", { XM, EXq } },
3178 /* PREFIX_0F3828 */
3180 { Bad_Opcode },
3181 { Bad_Opcode },
3182 { "pmuldq", { XM, EXx } },
3185 /* PREFIX_0F3829 */
3187 { Bad_Opcode },
3188 { Bad_Opcode },
3189 { "pcmpeqq", { XM, EXx } },
3192 /* PREFIX_0F382A */
3194 { Bad_Opcode },
3195 { Bad_Opcode },
3196 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3199 /* PREFIX_0F382B */
3201 { Bad_Opcode },
3202 { Bad_Opcode },
3203 { "packusdw", { XM, EXx } },
3206 /* PREFIX_0F3830 */
3208 { Bad_Opcode },
3209 { Bad_Opcode },
3210 { "pmovzxbw", { XM, EXq } },
3213 /* PREFIX_0F3831 */
3215 { Bad_Opcode },
3216 { Bad_Opcode },
3217 { "pmovzxbd", { XM, EXd } },
3220 /* PREFIX_0F3832 */
3222 { Bad_Opcode },
3223 { Bad_Opcode },
3224 { "pmovzxbq", { XM, EXw } },
3227 /* PREFIX_0F3833 */
3229 { Bad_Opcode },
3230 { Bad_Opcode },
3231 { "pmovzxwd", { XM, EXq } },
3234 /* PREFIX_0F3834 */
3236 { Bad_Opcode },
3237 { Bad_Opcode },
3238 { "pmovzxwq", { XM, EXd } },
3241 /* PREFIX_0F3835 */
3243 { Bad_Opcode },
3244 { Bad_Opcode },
3245 { "pmovzxdq", { XM, EXq } },
3248 /* PREFIX_0F3837 */
3250 { Bad_Opcode },
3251 { Bad_Opcode },
3252 { "pcmpgtq", { XM, EXx } },
3255 /* PREFIX_0F3838 */
3257 { Bad_Opcode },
3258 { Bad_Opcode },
3259 { "pminsb", { XM, EXx } },
3262 /* PREFIX_0F3839 */
3264 { Bad_Opcode },
3265 { Bad_Opcode },
3266 { "pminsd", { XM, EXx } },
3269 /* PREFIX_0F383A */
3271 { Bad_Opcode },
3272 { Bad_Opcode },
3273 { "pminuw", { XM, EXx } },
3276 /* PREFIX_0F383B */
3278 { Bad_Opcode },
3279 { Bad_Opcode },
3280 { "pminud", { XM, EXx } },
3283 /* PREFIX_0F383C */
3285 { Bad_Opcode },
3286 { Bad_Opcode },
3287 { "pmaxsb", { XM, EXx } },
3290 /* PREFIX_0F383D */
3292 { Bad_Opcode },
3293 { Bad_Opcode },
3294 { "pmaxsd", { XM, EXx } },
3297 /* PREFIX_0F383E */
3299 { Bad_Opcode },
3300 { Bad_Opcode },
3301 { "pmaxuw", { XM, EXx } },
3304 /* PREFIX_0F383F */
3306 { Bad_Opcode },
3307 { Bad_Opcode },
3308 { "pmaxud", { XM, EXx } },
3311 /* PREFIX_0F3840 */
3313 { Bad_Opcode },
3314 { Bad_Opcode },
3315 { "pmulld", { XM, EXx } },
3318 /* PREFIX_0F3841 */
3320 { Bad_Opcode },
3321 { Bad_Opcode },
3322 { "phminposuw", { XM, EXx } },
3325 /* PREFIX_0F3880 */
3327 { Bad_Opcode },
3328 { Bad_Opcode },
3329 { "invept", { Gm, Mo } },
3332 /* PREFIX_0F3881 */
3334 { Bad_Opcode },
3335 { Bad_Opcode },
3336 { "invvpid", { Gm, Mo } },
3339 /* PREFIX_0F38DB */
3341 { Bad_Opcode },
3342 { Bad_Opcode },
3343 { "aesimc", { XM, EXx } },
3346 /* PREFIX_0F38DC */
3348 { Bad_Opcode },
3349 { Bad_Opcode },
3350 { "aesenc", { XM, EXx } },
3353 /* PREFIX_0F38DD */
3355 { Bad_Opcode },
3356 { Bad_Opcode },
3357 { "aesenclast", { XM, EXx } },
3360 /* PREFIX_0F38DE */
3362 { Bad_Opcode },
3363 { Bad_Opcode },
3364 { "aesdec", { XM, EXx } },
3367 /* PREFIX_0F38DF */
3369 { Bad_Opcode },
3370 { Bad_Opcode },
3371 { "aesdeclast", { XM, EXx } },
3374 /* PREFIX_0F38F0 */
3376 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3377 { Bad_Opcode },
3378 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3379 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3382 /* PREFIX_0F38F1 */
3384 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3385 { Bad_Opcode },
3386 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3387 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3390 /* PREFIX_0F3A08 */
3392 { Bad_Opcode },
3393 { Bad_Opcode },
3394 { "roundps", { XM, EXx, Ib } },
3397 /* PREFIX_0F3A09 */
3399 { Bad_Opcode },
3400 { Bad_Opcode },
3401 { "roundpd", { XM, EXx, Ib } },
3404 /* PREFIX_0F3A0A */
3406 { Bad_Opcode },
3407 { Bad_Opcode },
3408 { "roundss", { XM, EXd, Ib } },
3411 /* PREFIX_0F3A0B */
3413 { Bad_Opcode },
3414 { Bad_Opcode },
3415 { "roundsd", { XM, EXq, Ib } },
3418 /* PREFIX_0F3A0C */
3420 { Bad_Opcode },
3421 { Bad_Opcode },
3422 { "blendps", { XM, EXx, Ib } },
3425 /* PREFIX_0F3A0D */
3427 { Bad_Opcode },
3428 { Bad_Opcode },
3429 { "blendpd", { XM, EXx, Ib } },
3432 /* PREFIX_0F3A0E */
3434 { Bad_Opcode },
3435 { Bad_Opcode },
3436 { "pblendw", { XM, EXx, Ib } },
3439 /* PREFIX_0F3A14 */
3441 { Bad_Opcode },
3442 { Bad_Opcode },
3443 { "pextrb", { Edqb, XM, Ib } },
3446 /* PREFIX_0F3A15 */
3448 { Bad_Opcode },
3449 { Bad_Opcode },
3450 { "pextrw", { Edqw, XM, Ib } },
3453 /* PREFIX_0F3A16 */
3455 { Bad_Opcode },
3456 { Bad_Opcode },
3457 { "pextrK", { Edq, XM, Ib } },
3460 /* PREFIX_0F3A17 */
3462 { Bad_Opcode },
3463 { Bad_Opcode },
3464 { "extractps", { Edqd, XM, Ib } },
3467 /* PREFIX_0F3A20 */
3469 { Bad_Opcode },
3470 { Bad_Opcode },
3471 { "pinsrb", { XM, Edqb, Ib } },
3474 /* PREFIX_0F3A21 */
3476 { Bad_Opcode },
3477 { Bad_Opcode },
3478 { "insertps", { XM, EXd, Ib } },
3481 /* PREFIX_0F3A22 */
3483 { Bad_Opcode },
3484 { Bad_Opcode },
3485 { "pinsrK", { XM, Edq, Ib } },
3488 /* PREFIX_0F3A40 */
3490 { Bad_Opcode },
3491 { Bad_Opcode },
3492 { "dpps", { XM, EXx, Ib } },
3495 /* PREFIX_0F3A41 */
3497 { Bad_Opcode },
3498 { Bad_Opcode },
3499 { "dppd", { XM, EXx, Ib } },
3502 /* PREFIX_0F3A42 */
3504 { Bad_Opcode },
3505 { Bad_Opcode },
3506 { "mpsadbw", { XM, EXx, Ib } },
3509 /* PREFIX_0F3A44 */
3511 { Bad_Opcode },
3512 { Bad_Opcode },
3513 { "pclmulqdq", { XM, EXx, PCLMUL } },
3516 /* PREFIX_0F3A60 */
3518 { Bad_Opcode },
3519 { Bad_Opcode },
3520 { "pcmpestrm", { XM, EXx, Ib } },
3523 /* PREFIX_0F3A61 */
3525 { Bad_Opcode },
3526 { Bad_Opcode },
3527 { "pcmpestri", { XM, EXx, Ib } },
3530 /* PREFIX_0F3A62 */
3532 { Bad_Opcode },
3533 { Bad_Opcode },
3534 { "pcmpistrm", { XM, EXx, Ib } },
3537 /* PREFIX_0F3A63 */
3539 { Bad_Opcode },
3540 { Bad_Opcode },
3541 { "pcmpistri", { XM, EXx, Ib } },
3544 /* PREFIX_0F3ADF */
3546 { Bad_Opcode },
3547 { Bad_Opcode },
3548 { "aeskeygenassist", { XM, EXx, Ib } },
3551 /* PREFIX_VEX_10 */
3553 { VEX_W_TABLE (VEX_W_10_P_0) },
3554 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3555 { VEX_W_TABLE (VEX_W_10_P_2) },
3556 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3559 /* PREFIX_VEX_11 */
3561 { VEX_W_TABLE (VEX_W_11_P_0) },
3562 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3563 { VEX_W_TABLE (VEX_W_11_P_2) },
3564 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3567 /* PREFIX_VEX_12 */
3569 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3570 { VEX_W_TABLE (VEX_W_12_P_1) },
3571 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3572 { VEX_W_TABLE (VEX_W_12_P_3) },
3575 /* PREFIX_VEX_16 */
3577 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3578 { VEX_W_TABLE (VEX_W_16_P_1) },
3579 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3582 /* PREFIX_VEX_2A */
3584 { Bad_Opcode },
3585 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3586 { Bad_Opcode },
3587 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3590 /* PREFIX_VEX_2C */
3592 { Bad_Opcode },
3593 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3594 { Bad_Opcode },
3595 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3598 /* PREFIX_VEX_2D */
3600 { Bad_Opcode },
3601 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3602 { Bad_Opcode },
3603 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3606 /* PREFIX_VEX_2E */
3608 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3609 { Bad_Opcode },
3610 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3613 /* PREFIX_VEX_2F */
3615 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3616 { Bad_Opcode },
3617 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3620 /* PREFIX_VEX_51 */
3622 { VEX_W_TABLE (VEX_W_51_P_0) },
3623 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3624 { VEX_W_TABLE (VEX_W_51_P_2) },
3625 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3628 /* PREFIX_VEX_52 */
3630 { VEX_W_TABLE (VEX_W_52_P_0) },
3631 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3634 /* PREFIX_VEX_53 */
3636 { VEX_W_TABLE (VEX_W_53_P_0) },
3637 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3640 /* PREFIX_VEX_58 */
3642 { VEX_W_TABLE (VEX_W_58_P_0) },
3643 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3644 { VEX_W_TABLE (VEX_W_58_P_2) },
3645 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3648 /* PREFIX_VEX_59 */
3650 { VEX_W_TABLE (VEX_W_59_P_0) },
3651 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3652 { VEX_W_TABLE (VEX_W_59_P_2) },
3653 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3656 /* PREFIX_VEX_5A */
3658 { VEX_W_TABLE (VEX_W_5A_P_0) },
3659 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3660 { "vcvtpd2ps%XY", { XMM, EXx } },
3661 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3664 /* PREFIX_VEX_5B */
3666 { VEX_W_TABLE (VEX_W_5B_P_0) },
3667 { VEX_W_TABLE (VEX_W_5B_P_1) },
3668 { VEX_W_TABLE (VEX_W_5B_P_2) },
3671 /* PREFIX_VEX_5C */
3673 { VEX_W_TABLE (VEX_W_5C_P_0) },
3674 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3675 { VEX_W_TABLE (VEX_W_5C_P_2) },
3676 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3679 /* PREFIX_VEX_5D */
3681 { VEX_W_TABLE (VEX_W_5D_P_0) },
3682 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3683 { VEX_W_TABLE (VEX_W_5D_P_2) },
3684 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3687 /* PREFIX_VEX_5E */
3689 { VEX_W_TABLE (VEX_W_5E_P_0) },
3690 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3691 { VEX_W_TABLE (VEX_W_5E_P_2) },
3692 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3695 /* PREFIX_VEX_5F */
3697 { VEX_W_TABLE (VEX_W_5F_P_0) },
3698 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3699 { VEX_W_TABLE (VEX_W_5F_P_2) },
3700 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3703 /* PREFIX_VEX_60 */
3705 { Bad_Opcode },
3706 { Bad_Opcode },
3707 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3710 /* PREFIX_VEX_61 */
3712 { Bad_Opcode },
3713 { Bad_Opcode },
3714 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3717 /* PREFIX_VEX_62 */
3719 { Bad_Opcode },
3720 { Bad_Opcode },
3721 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3724 /* PREFIX_VEX_63 */
3726 { Bad_Opcode },
3727 { Bad_Opcode },
3728 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3731 /* PREFIX_VEX_64 */
3733 { Bad_Opcode },
3734 { Bad_Opcode },
3735 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3738 /* PREFIX_VEX_65 */
3740 { Bad_Opcode },
3741 { Bad_Opcode },
3742 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3745 /* PREFIX_VEX_66 */
3747 { Bad_Opcode },
3748 { Bad_Opcode },
3749 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3752 /* PREFIX_VEX_67 */
3754 { Bad_Opcode },
3755 { Bad_Opcode },
3756 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3759 /* PREFIX_VEX_68 */
3761 { Bad_Opcode },
3762 { Bad_Opcode },
3763 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3766 /* PREFIX_VEX_69 */
3768 { Bad_Opcode },
3769 { Bad_Opcode },
3770 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3773 /* PREFIX_VEX_6A */
3775 { Bad_Opcode },
3776 { Bad_Opcode },
3777 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3780 /* PREFIX_VEX_6B */
3782 { Bad_Opcode },
3783 { Bad_Opcode },
3784 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3787 /* PREFIX_VEX_6C */
3789 { Bad_Opcode },
3790 { Bad_Opcode },
3791 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3794 /* PREFIX_VEX_6D */
3796 { Bad_Opcode },
3797 { Bad_Opcode },
3798 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3801 /* PREFIX_VEX_6E */
3803 { Bad_Opcode },
3804 { Bad_Opcode },
3805 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3808 /* PREFIX_VEX_6F */
3810 { Bad_Opcode },
3811 { VEX_W_TABLE (VEX_W_6F_P_1) },
3812 { VEX_W_TABLE (VEX_W_6F_P_2) },
3815 /* PREFIX_VEX_70 */
3817 { Bad_Opcode },
3818 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3819 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3820 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3823 /* PREFIX_VEX_71_REG_2 */
3825 { Bad_Opcode },
3826 { Bad_Opcode },
3827 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3830 /* PREFIX_VEX_71_REG_4 */
3832 { Bad_Opcode },
3833 { Bad_Opcode },
3834 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3837 /* PREFIX_VEX_71_REG_6 */
3839 { Bad_Opcode },
3840 { Bad_Opcode },
3841 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3844 /* PREFIX_VEX_72_REG_2 */
3846 { Bad_Opcode },
3847 { Bad_Opcode },
3848 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3851 /* PREFIX_VEX_72_REG_4 */
3853 { Bad_Opcode },
3854 { Bad_Opcode },
3855 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3858 /* PREFIX_VEX_72_REG_6 */
3860 { Bad_Opcode },
3861 { Bad_Opcode },
3862 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3865 /* PREFIX_VEX_73_REG_2 */
3867 { Bad_Opcode },
3868 { Bad_Opcode },
3869 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3872 /* PREFIX_VEX_73_REG_3 */
3874 { Bad_Opcode },
3875 { Bad_Opcode },
3876 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3879 /* PREFIX_VEX_73_REG_6 */
3881 { Bad_Opcode },
3882 { Bad_Opcode },
3883 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3886 /* PREFIX_VEX_73_REG_7 */
3888 { Bad_Opcode },
3889 { Bad_Opcode },
3890 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3893 /* PREFIX_VEX_74 */
3895 { Bad_Opcode },
3896 { Bad_Opcode },
3897 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3900 /* PREFIX_VEX_75 */
3902 { Bad_Opcode },
3903 { Bad_Opcode },
3904 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3907 /* PREFIX_VEX_76 */
3909 { Bad_Opcode },
3910 { Bad_Opcode },
3911 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3914 /* PREFIX_VEX_77 */
3916 { VEX_W_TABLE (VEX_W_77_P_0) },
3919 /* PREFIX_VEX_7C */
3921 { Bad_Opcode },
3922 { Bad_Opcode },
3923 { VEX_W_TABLE (VEX_W_7C_P_2) },
3924 { VEX_W_TABLE (VEX_W_7C_P_3) },
3927 /* PREFIX_VEX_7D */
3929 { Bad_Opcode },
3930 { Bad_Opcode },
3931 { VEX_W_TABLE (VEX_W_7D_P_2) },
3932 { VEX_W_TABLE (VEX_W_7D_P_3) },
3935 /* PREFIX_VEX_7E */
3937 { Bad_Opcode },
3938 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3939 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3942 /* PREFIX_VEX_7F */
3944 { Bad_Opcode },
3945 { VEX_W_TABLE (VEX_W_7F_P_1) },
3946 { VEX_W_TABLE (VEX_W_7F_P_2) },
3949 /* PREFIX_VEX_C2 */
3951 { VEX_W_TABLE (VEX_W_C2_P_0) },
3952 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3953 { VEX_W_TABLE (VEX_W_C2_P_2) },
3954 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3957 /* PREFIX_VEX_C4 */
3959 { Bad_Opcode },
3960 { Bad_Opcode },
3961 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3964 /* PREFIX_VEX_C5 */
3966 { Bad_Opcode },
3967 { Bad_Opcode },
3968 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3971 /* PREFIX_VEX_D0 */
3973 { Bad_Opcode },
3974 { Bad_Opcode },
3975 { VEX_W_TABLE (VEX_W_D0_P_2) },
3976 { VEX_W_TABLE (VEX_W_D0_P_3) },
3979 /* PREFIX_VEX_D1 */
3981 { Bad_Opcode },
3982 { Bad_Opcode },
3983 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3986 /* PREFIX_VEX_D2 */
3988 { Bad_Opcode },
3989 { Bad_Opcode },
3990 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3993 /* PREFIX_VEX_D3 */
3995 { Bad_Opcode },
3996 { Bad_Opcode },
3997 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
4000 /* PREFIX_VEX_D4 */
4002 { Bad_Opcode },
4003 { Bad_Opcode },
4004 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
4007 /* PREFIX_VEX_D5 */
4009 { Bad_Opcode },
4010 { Bad_Opcode },
4011 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
4014 /* PREFIX_VEX_D6 */
4016 { Bad_Opcode },
4017 { Bad_Opcode },
4018 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
4021 /* PREFIX_VEX_D7 */
4023 { Bad_Opcode },
4024 { Bad_Opcode },
4025 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
4028 /* PREFIX_VEX_D8 */
4030 { Bad_Opcode },
4031 { Bad_Opcode },
4032 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4035 /* PREFIX_VEX_D9 */
4037 { Bad_Opcode },
4038 { Bad_Opcode },
4039 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4042 /* PREFIX_VEX_DA */
4044 { Bad_Opcode },
4045 { Bad_Opcode },
4046 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4049 /* PREFIX_VEX_DB */
4051 { Bad_Opcode },
4052 { Bad_Opcode },
4053 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4056 /* PREFIX_VEX_DC */
4058 { Bad_Opcode },
4059 { Bad_Opcode },
4060 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4063 /* PREFIX_VEX_DD */
4065 { Bad_Opcode },
4066 { Bad_Opcode },
4067 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4070 /* PREFIX_VEX_DE */
4072 { Bad_Opcode },
4073 { Bad_Opcode },
4074 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4077 /* PREFIX_VEX_DF */
4079 { Bad_Opcode },
4080 { Bad_Opcode },
4081 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4084 /* PREFIX_VEX_E0 */
4086 { Bad_Opcode },
4087 { Bad_Opcode },
4088 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4091 /* PREFIX_VEX_E1 */
4093 { Bad_Opcode },
4094 { Bad_Opcode },
4095 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4098 /* PREFIX_VEX_E2 */
4100 { Bad_Opcode },
4101 { Bad_Opcode },
4102 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4105 /* PREFIX_VEX_E3 */
4107 { Bad_Opcode },
4108 { Bad_Opcode },
4109 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4112 /* PREFIX_VEX_E4 */
4114 { Bad_Opcode },
4115 { Bad_Opcode },
4116 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4119 /* PREFIX_VEX_E5 */
4121 { Bad_Opcode },
4122 { Bad_Opcode },
4123 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4126 /* PREFIX_VEX_E6 */
4128 { Bad_Opcode },
4129 { VEX_W_TABLE (VEX_W_E6_P_1) },
4130 { VEX_W_TABLE (VEX_W_E6_P_2) },
4131 { VEX_W_TABLE (VEX_W_E6_P_3) },
4134 /* PREFIX_VEX_E7 */
4136 { Bad_Opcode },
4137 { Bad_Opcode },
4138 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4141 /* PREFIX_VEX_E8 */
4143 { Bad_Opcode },
4144 { Bad_Opcode },
4145 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4148 /* PREFIX_VEX_E9 */
4150 { Bad_Opcode },
4151 { Bad_Opcode },
4152 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4155 /* PREFIX_VEX_EA */
4157 { Bad_Opcode },
4158 { Bad_Opcode },
4159 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4162 /* PREFIX_VEX_EB */
4164 { Bad_Opcode },
4165 { Bad_Opcode },
4166 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4169 /* PREFIX_VEX_EC */
4171 { Bad_Opcode },
4172 { Bad_Opcode },
4173 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4176 /* PREFIX_VEX_ED */
4178 { Bad_Opcode },
4179 { Bad_Opcode },
4180 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4183 /* PREFIX_VEX_EE */
4185 { Bad_Opcode },
4186 { Bad_Opcode },
4187 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4190 /* PREFIX_VEX_EF */
4192 { Bad_Opcode },
4193 { Bad_Opcode },
4194 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4197 /* PREFIX_VEX_F0 */
4199 { Bad_Opcode },
4200 { Bad_Opcode },
4201 { Bad_Opcode },
4202 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4205 /* PREFIX_VEX_F1 */
4207 { Bad_Opcode },
4208 { Bad_Opcode },
4209 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4212 /* PREFIX_VEX_F2 */
4214 { Bad_Opcode },
4215 { Bad_Opcode },
4216 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4219 /* PREFIX_VEX_F3 */
4221 { Bad_Opcode },
4222 { Bad_Opcode },
4223 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4226 /* PREFIX_VEX_F4 */
4228 { Bad_Opcode },
4229 { Bad_Opcode },
4230 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4233 /* PREFIX_VEX_F5 */
4235 { Bad_Opcode },
4236 { Bad_Opcode },
4237 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4240 /* PREFIX_VEX_F6 */
4242 { Bad_Opcode },
4243 { Bad_Opcode },
4244 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4247 /* PREFIX_VEX_F7 */
4249 { Bad_Opcode },
4250 { Bad_Opcode },
4251 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4254 /* PREFIX_VEX_F8 */
4256 { Bad_Opcode },
4257 { Bad_Opcode },
4258 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4261 /* PREFIX_VEX_F9 */
4263 { Bad_Opcode },
4264 { Bad_Opcode },
4265 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4268 /* PREFIX_VEX_FA */
4270 { Bad_Opcode },
4271 { Bad_Opcode },
4272 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4275 /* PREFIX_VEX_FB */
4277 { Bad_Opcode },
4278 { Bad_Opcode },
4279 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4282 /* PREFIX_VEX_FC */
4284 { Bad_Opcode },
4285 { Bad_Opcode },
4286 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4289 /* PREFIX_VEX_FD */
4291 { Bad_Opcode },
4292 { Bad_Opcode },
4293 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4296 /* PREFIX_VEX_FE */
4298 { Bad_Opcode },
4299 { Bad_Opcode },
4300 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4303 /* PREFIX_VEX_3800 */
4305 { Bad_Opcode },
4306 { Bad_Opcode },
4307 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4310 /* PREFIX_VEX_3801 */
4312 { Bad_Opcode },
4313 { Bad_Opcode },
4314 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4317 /* PREFIX_VEX_3802 */
4319 { Bad_Opcode },
4320 { Bad_Opcode },
4321 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4324 /* PREFIX_VEX_3803 */
4326 { Bad_Opcode },
4327 { Bad_Opcode },
4328 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4331 /* PREFIX_VEX_3804 */
4333 { Bad_Opcode },
4334 { Bad_Opcode },
4335 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4338 /* PREFIX_VEX_3805 */
4340 { Bad_Opcode },
4341 { Bad_Opcode },
4342 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4345 /* PREFIX_VEX_3806 */
4347 { Bad_Opcode },
4348 { Bad_Opcode },
4349 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4352 /* PREFIX_VEX_3807 */
4354 { Bad_Opcode },
4355 { Bad_Opcode },
4356 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4359 /* PREFIX_VEX_3808 */
4361 { Bad_Opcode },
4362 { Bad_Opcode },
4363 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4366 /* PREFIX_VEX_3809 */
4368 { Bad_Opcode },
4369 { Bad_Opcode },
4370 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4373 /* PREFIX_VEX_380A */
4375 { Bad_Opcode },
4376 { Bad_Opcode },
4377 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4380 /* PREFIX_VEX_380B */
4382 { Bad_Opcode },
4383 { Bad_Opcode },
4384 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4387 /* PREFIX_VEX_380C */
4389 { Bad_Opcode },
4390 { Bad_Opcode },
4391 { VEX_W_TABLE (VEX_W_380C_P_2) },
4394 /* PREFIX_VEX_380D */
4396 { Bad_Opcode },
4397 { Bad_Opcode },
4398 { VEX_W_TABLE (VEX_W_380D_P_2) },
4401 /* PREFIX_VEX_380E */
4403 { Bad_Opcode },
4404 { Bad_Opcode },
4405 { VEX_W_TABLE (VEX_W_380E_P_2) },
4408 /* PREFIX_VEX_380F */
4410 { Bad_Opcode },
4411 { Bad_Opcode },
4412 { VEX_W_TABLE (VEX_W_380F_P_2) },
4415 /* PREFIX_VEX_3817 */
4417 { Bad_Opcode },
4418 { Bad_Opcode },
4419 { VEX_W_TABLE (VEX_W_3817_P_2) },
4422 /* PREFIX_VEX_3818 */
4424 { Bad_Opcode },
4425 { Bad_Opcode },
4426 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4429 /* PREFIX_VEX_3819 */
4431 { Bad_Opcode },
4432 { Bad_Opcode },
4433 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4436 /* PREFIX_VEX_381A */
4438 { Bad_Opcode },
4439 { Bad_Opcode },
4440 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4443 /* PREFIX_VEX_381C */
4445 { Bad_Opcode },
4446 { Bad_Opcode },
4447 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4450 /* PREFIX_VEX_381D */
4452 { Bad_Opcode },
4453 { Bad_Opcode },
4454 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4457 /* PREFIX_VEX_381E */
4459 { Bad_Opcode },
4460 { Bad_Opcode },
4461 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4464 /* PREFIX_VEX_3820 */
4466 { Bad_Opcode },
4467 { Bad_Opcode },
4468 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4471 /* PREFIX_VEX_3821 */
4473 { Bad_Opcode },
4474 { Bad_Opcode },
4475 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4478 /* PREFIX_VEX_3822 */
4480 { Bad_Opcode },
4481 { Bad_Opcode },
4482 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4485 /* PREFIX_VEX_3823 */
4487 { Bad_Opcode },
4488 { Bad_Opcode },
4489 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4492 /* PREFIX_VEX_3824 */
4494 { Bad_Opcode },
4495 { Bad_Opcode },
4496 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4499 /* PREFIX_VEX_3825 */
4501 { Bad_Opcode },
4502 { Bad_Opcode },
4503 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4506 /* PREFIX_VEX_3828 */
4508 { Bad_Opcode },
4509 { Bad_Opcode },
4510 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4513 /* PREFIX_VEX_3829 */
4515 { Bad_Opcode },
4516 { Bad_Opcode },
4517 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4520 /* PREFIX_VEX_382A */
4522 { Bad_Opcode },
4523 { Bad_Opcode },
4524 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4527 /* PREFIX_VEX_382B */
4529 { Bad_Opcode },
4530 { Bad_Opcode },
4531 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4534 /* PREFIX_VEX_382C */
4536 { Bad_Opcode },
4537 { Bad_Opcode },
4538 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4541 /* PREFIX_VEX_382D */
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4548 /* PREFIX_VEX_382E */
4550 { Bad_Opcode },
4551 { Bad_Opcode },
4552 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4555 /* PREFIX_VEX_382F */
4557 { Bad_Opcode },
4558 { Bad_Opcode },
4559 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4562 /* PREFIX_VEX_3830 */
4564 { Bad_Opcode },
4565 { Bad_Opcode },
4566 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4569 /* PREFIX_VEX_3831 */
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4576 /* PREFIX_VEX_3832 */
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4583 /* PREFIX_VEX_3833 */
4585 { Bad_Opcode },
4586 { Bad_Opcode },
4587 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4590 /* PREFIX_VEX_3834 */
4592 { Bad_Opcode },
4593 { Bad_Opcode },
4594 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4597 /* PREFIX_VEX_3835 */
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4604 /* PREFIX_VEX_3837 */
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4611 /* PREFIX_VEX_3838 */
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4618 /* PREFIX_VEX_3839 */
4620 { Bad_Opcode },
4621 { Bad_Opcode },
4622 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4625 /* PREFIX_VEX_383A */
4627 { Bad_Opcode },
4628 { Bad_Opcode },
4629 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4632 /* PREFIX_VEX_383B */
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4639 /* PREFIX_VEX_383C */
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4646 /* PREFIX_VEX_383D */
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4653 /* PREFIX_VEX_383E */
4655 { Bad_Opcode },
4656 { Bad_Opcode },
4657 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4660 /* PREFIX_VEX_383F */
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4667 /* PREFIX_VEX_3840 */
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4674 /* PREFIX_VEX_3841 */
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4681 /* PREFIX_VEX_3896 */
4683 { Bad_Opcode },
4684 { Bad_Opcode },
4685 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4688 /* PREFIX_VEX_3897 */
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4695 /* PREFIX_VEX_3898 */
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { "vfmadd132p%XW", { XM, Vex, EXx } },
4702 /* PREFIX_VEX_3899 */
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4709 /* PREFIX_VEX_389A */
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { "vfmsub132p%XW", { XM, Vex, EXx } },
4716 /* PREFIX_VEX_389B */
4718 { Bad_Opcode },
4719 { Bad_Opcode },
4720 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4723 /* PREFIX_VEX_389C */
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { "vfnmadd132p%XW", { XM, Vex, EXx } },
4730 /* PREFIX_VEX_389D */
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4737 /* PREFIX_VEX_389E */
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { "vfnmsub132p%XW", { XM, Vex, EXx } },
4744 /* PREFIX_VEX_389F */
4746 { Bad_Opcode },
4747 { Bad_Opcode },
4748 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4751 /* PREFIX_VEX_38A6 */
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4756 { Bad_Opcode },
4759 /* PREFIX_VEX_38A7 */
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4766 /* PREFIX_VEX_38A8 */
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { "vfmadd213p%XW", { XM, Vex, EXx } },
4773 /* PREFIX_VEX_38A9 */
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4780 /* PREFIX_VEX_38AA */
4782 { Bad_Opcode },
4783 { Bad_Opcode },
4784 { "vfmsub213p%XW", { XM, Vex, EXx } },
4787 /* PREFIX_VEX_38AB */
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4794 /* PREFIX_VEX_38AC */
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { "vfnmadd213p%XW", { XM, Vex, EXx } },
4801 /* PREFIX_VEX_38AD */
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4808 /* PREFIX_VEX_38AE */
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { "vfnmsub213p%XW", { XM, Vex, EXx } },
4815 /* PREFIX_VEX_38AF */
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4822 /* PREFIX_VEX_38B6 */
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4829 /* PREFIX_VEX_38B7 */
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4836 /* PREFIX_VEX_38B8 */
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { "vfmadd231p%XW", { XM, Vex, EXx } },
4843 /* PREFIX_VEX_38B9 */
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4850 /* PREFIX_VEX_38BA */
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { "vfmsub231p%XW", { XM, Vex, EXx } },
4857 /* PREFIX_VEX_38BB */
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4864 /* PREFIX_VEX_38BC */
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { "vfnmadd231p%XW", { XM, Vex, EXx } },
4871 /* PREFIX_VEX_38BD */
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4878 /* PREFIX_VEX_38BE */
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 { "vfnmsub231p%XW", { XM, Vex, EXx } },
4885 /* PREFIX_VEX_38BF */
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4892 /* PREFIX_VEX_38DB */
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4899 /* PREFIX_VEX_38DC */
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4906 /* PREFIX_VEX_38DD */
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4913 /* PREFIX_VEX_38DE */
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4920 /* PREFIX_VEX_38DF */
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4927 /* PREFIX_VEX_3A04 */
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 { VEX_W_TABLE (VEX_W_3A04_P_2) },
4934 /* PREFIX_VEX_3A05 */
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { VEX_W_TABLE (VEX_W_3A05_P_2) },
4941 /* PREFIX_VEX_3A06 */
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4948 /* PREFIX_VEX_3A08 */
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { VEX_W_TABLE (VEX_W_3A08_P_2) },
4955 /* PREFIX_VEX_3A09 */
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { VEX_W_TABLE (VEX_W_3A09_P_2) },
4962 /* PREFIX_VEX_3A0A */
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4969 /* PREFIX_VEX_3A0B */
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4976 /* PREFIX_VEX_3A0C */
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { VEX_W_TABLE (VEX_W_3A0C_P_2) },
4983 /* PREFIX_VEX_3A0D */
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { VEX_W_TABLE (VEX_W_3A0D_P_2) },
4990 /* PREFIX_VEX_3A0E */
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4997 /* PREFIX_VEX_3A0F */
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5004 /* PREFIX_VEX_3A14 */
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5011 /* PREFIX_VEX_3A15 */
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5018 /* PREFIX_VEX_3A16 */
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5025 /* PREFIX_VEX_3A17 */
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5032 /* PREFIX_VEX_3A18 */
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5039 /* PREFIX_VEX_3A19 */
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5046 /* PREFIX_VEX_3A20 */
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5053 /* PREFIX_VEX_3A21 */
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5060 /* PREFIX_VEX_3A22 */
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5067 /* PREFIX_VEX_3A40 */
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { VEX_W_TABLE (VEX_W_3A40_P_2) },
5074 /* PREFIX_VEX_3A41 */
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5081 /* PREFIX_VEX_3A42 */
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5088 /* PREFIX_VEX_3A44 */
5090 { Bad_Opcode },
5091 { Bad_Opcode },
5092 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5095 /* PREFIX_VEX_3A48 */
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { VEX_W_TABLE (VEX_W_3A48_P_2) },
5102 /* PREFIX_VEX_3A49 */
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { VEX_W_TABLE (VEX_W_3A49_P_2) },
5109 /* PREFIX_VEX_3A4A */
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5116 /* PREFIX_VEX_3A4B */
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5123 /* PREFIX_VEX_3A4C */
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5130 /* PREFIX_VEX_3A5C */
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5137 /* PREFIX_VEX_3A5D */
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5144 /* PREFIX_VEX_3A5E */
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5151 /* PREFIX_VEX_3A5F */
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5158 /* PREFIX_VEX_3A60 */
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5163 { Bad_Opcode },
5166 /* PREFIX_VEX_3A61 */
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5173 /* PREFIX_VEX_3A62 */
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5180 /* PREFIX_VEX_3A63 */
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5187 /* PREFIX_VEX_3A68 */
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5194 /* PREFIX_VEX_3A69 */
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5201 /* PREFIX_VEX_3A6A */
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5208 /* PREFIX_VEX_3A6B */
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5215 /* PREFIX_VEX_3A6C */
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5222 /* PREFIX_VEX_3A6D */
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5229 /* PREFIX_VEX_3A6E */
5231 { Bad_Opcode },
5232 { Bad_Opcode },
5233 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5236 /* PREFIX_VEX_3A6F */
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5243 /* PREFIX_VEX_3A78 */
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5250 /* PREFIX_VEX_3A79 */
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5257 /* PREFIX_VEX_3A7A */
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5264 /* PREFIX_VEX_3A7B */
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5271 /* PREFIX_VEX_3A7C */
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5276 { Bad_Opcode },
5279 /* PREFIX_VEX_3A7D */
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5286 /* PREFIX_VEX_3A7E */
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5293 /* PREFIX_VEX_3A7F */
5295 { Bad_Opcode },
5296 { Bad_Opcode },
5297 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5300 /* PREFIX_VEX_3ADF */
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5308 static const struct dis386 x86_64_table[][2] = {
5309 /* X86_64_06 */
5311 { "push{T|}", { es } },
5314 /* X86_64_07 */
5316 { "pop{T|}", { es } },
5319 /* X86_64_0D */
5321 { "push{T|}", { cs } },
5324 /* X86_64_16 */
5326 { "push{T|}", { ss } },
5329 /* X86_64_17 */
5331 { "pop{T|}", { ss } },
5334 /* X86_64_1E */
5336 { "push{T|}", { ds } },
5339 /* X86_64_1F */
5341 { "pop{T|}", { ds } },
5344 /* X86_64_27 */
5346 { "daa", { XX } },
5349 /* X86_64_2F */
5351 { "das", { XX } },
5354 /* X86_64_37 */
5356 { "aaa", { XX } },
5359 /* X86_64_3F */
5361 { "aas", { XX } },
5364 /* X86_64_60 */
5366 { "pusha{P|}", { XX } },
5369 /* X86_64_61 */
5371 { "popa{P|}", { XX } },
5374 /* X86_64_62 */
5376 { MOD_TABLE (MOD_62_32BIT) },
5379 /* X86_64_63 */
5381 { "arpl", { Ew, Gw } },
5382 { "movs{lq|xd}", { Gv, Ed } },
5385 /* X86_64_6D */
5387 { "ins{R|}", { Yzr, indirDX } },
5388 { "ins{G|}", { Yzr, indirDX } },
5391 /* X86_64_6F */
5393 { "outs{R|}", { indirDXr, Xz } },
5394 { "outs{G|}", { indirDXr, Xz } },
5397 /* X86_64_9A */
5399 { "Jcall{T|}", { Ap } },
5402 /* X86_64_C4 */
5404 { MOD_TABLE (MOD_C4_32BIT) },
5405 { VEX_C4_TABLE (VEX_0F) },
5408 /* X86_64_C5 */
5410 { MOD_TABLE (MOD_C5_32BIT) },
5411 { VEX_C5_TABLE (VEX_0F) },
5414 /* X86_64_CE */
5416 { "into", { XX } },
5419 /* X86_64_D4 */
5421 { "aam", { sIb } },
5424 /* X86_64_D5 */
5426 { "aad", { sIb } },
5429 /* X86_64_EA */
5431 { "Jjmp{T|}", { Ap } },
5434 /* X86_64_0F01_REG_0 */
5436 { "sgdt{Q|IQ}", { M } },
5437 { "sgdt", { M } },
5440 /* X86_64_0F01_REG_1 */
5442 { "sidt{Q|IQ}", { M } },
5443 { "sidt", { M } },
5446 /* X86_64_0F01_REG_2 */
5448 { "lgdt{Q|Q}", { M } },
5449 { "lgdt", { M } },
5452 /* X86_64_0F01_REG_3 */
5454 { "lidt{Q|Q}", { M } },
5455 { "lidt", { M } },
5459 static const struct dis386 three_byte_table[][256] = {
5461 /* THREE_BYTE_0F38 */
5463 /* 00 */
5464 { "pshufb", { MX, EM } },
5465 { "phaddw", { MX, EM } },
5466 { "phaddd", { MX, EM } },
5467 { "phaddsw", { MX, EM } },
5468 { "pmaddubsw", { MX, EM } },
5469 { "phsubw", { MX, EM } },
5470 { "phsubd", { MX, EM } },
5471 { "phsubsw", { MX, EM } },
5472 /* 08 */
5473 { "psignb", { MX, EM } },
5474 { "psignw", { MX, EM } },
5475 { "psignd", { MX, EM } },
5476 { "pmulhrsw", { MX, EM } },
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 /* 10 */
5482 { PREFIX_TABLE (PREFIX_0F3810) },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 { PREFIX_TABLE (PREFIX_0F3814) },
5487 { PREFIX_TABLE (PREFIX_0F3815) },
5488 { Bad_Opcode },
5489 { PREFIX_TABLE (PREFIX_0F3817) },
5490 /* 18 */
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { "pabsb", { MX, EM } },
5496 { "pabsw", { MX, EM } },
5497 { "pabsd", { MX, EM } },
5498 { Bad_Opcode },
5499 /* 20 */
5500 { PREFIX_TABLE (PREFIX_0F3820) },
5501 { PREFIX_TABLE (PREFIX_0F3821) },
5502 { PREFIX_TABLE (PREFIX_0F3822) },
5503 { PREFIX_TABLE (PREFIX_0F3823) },
5504 { PREFIX_TABLE (PREFIX_0F3824) },
5505 { PREFIX_TABLE (PREFIX_0F3825) },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 /* 28 */
5509 { PREFIX_TABLE (PREFIX_0F3828) },
5510 { PREFIX_TABLE (PREFIX_0F3829) },
5511 { PREFIX_TABLE (PREFIX_0F382A) },
5512 { PREFIX_TABLE (PREFIX_0F382B) },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 /* 30 */
5518 { PREFIX_TABLE (PREFIX_0F3830) },
5519 { PREFIX_TABLE (PREFIX_0F3831) },
5520 { PREFIX_TABLE (PREFIX_0F3832) },
5521 { PREFIX_TABLE (PREFIX_0F3833) },
5522 { PREFIX_TABLE (PREFIX_0F3834) },
5523 { PREFIX_TABLE (PREFIX_0F3835) },
5524 { Bad_Opcode },
5525 { PREFIX_TABLE (PREFIX_0F3837) },
5526 /* 38 */
5527 { PREFIX_TABLE (PREFIX_0F3838) },
5528 { PREFIX_TABLE (PREFIX_0F3839) },
5529 { PREFIX_TABLE (PREFIX_0F383A) },
5530 { PREFIX_TABLE (PREFIX_0F383B) },
5531 { PREFIX_TABLE (PREFIX_0F383C) },
5532 { PREFIX_TABLE (PREFIX_0F383D) },
5533 { PREFIX_TABLE (PREFIX_0F383E) },
5534 { PREFIX_TABLE (PREFIX_0F383F) },
5535 /* 40 */
5536 { PREFIX_TABLE (PREFIX_0F3840) },
5537 { PREFIX_TABLE (PREFIX_0F3841) },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 /* 48 */
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 { Bad_Opcode },
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 /* 50 */
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 { Bad_Opcode },
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 /* 58 */
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 /* 60 */
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 /* 68 */
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 { Bad_Opcode },
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 /* 70 */
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 /* 78 */
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 /* 80 */
5608 { PREFIX_TABLE (PREFIX_0F3880) },
5609 { PREFIX_TABLE (PREFIX_0F3881) },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 { Bad_Opcode },
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 /* 88 */
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 { Bad_Opcode },
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 /* 90 */
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 /* 98 */
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 /* a0 */
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 /* a8 */
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 /* b0 */
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 { Bad_Opcode },
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 /* b8 */
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 /* c0 */
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 /* c8 */
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 /* d0 */
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 /* d8 */
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { PREFIX_TABLE (PREFIX_0F38DB) },
5711 { PREFIX_TABLE (PREFIX_0F38DC) },
5712 { PREFIX_TABLE (PREFIX_0F38DD) },
5713 { PREFIX_TABLE (PREFIX_0F38DE) },
5714 { PREFIX_TABLE (PREFIX_0F38DF) },
5715 /* e0 */
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 /* e8 */
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 /* f0 */
5734 { PREFIX_TABLE (PREFIX_0F38F0) },
5735 { PREFIX_TABLE (PREFIX_0F38F1) },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { Bad_Opcode },
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 /* f8 */
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 { Bad_Opcode },
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5752 /* THREE_BYTE_0F3A */
5754 /* 00 */
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 /* 08 */
5764 { PREFIX_TABLE (PREFIX_0F3A08) },
5765 { PREFIX_TABLE (PREFIX_0F3A09) },
5766 { PREFIX_TABLE (PREFIX_0F3A0A) },
5767 { PREFIX_TABLE (PREFIX_0F3A0B) },
5768 { PREFIX_TABLE (PREFIX_0F3A0C) },
5769 { PREFIX_TABLE (PREFIX_0F3A0D) },
5770 { PREFIX_TABLE (PREFIX_0F3A0E) },
5771 { "palignr", { MX, EM, Ib } },
5772 /* 10 */
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 { Bad_Opcode },
5776 { Bad_Opcode },
5777 { PREFIX_TABLE (PREFIX_0F3A14) },
5778 { PREFIX_TABLE (PREFIX_0F3A15) },
5779 { PREFIX_TABLE (PREFIX_0F3A16) },
5780 { PREFIX_TABLE (PREFIX_0F3A17) },
5781 /* 18 */
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 /* 20 */
5791 { PREFIX_TABLE (PREFIX_0F3A20) },
5792 { PREFIX_TABLE (PREFIX_0F3A21) },
5793 { PREFIX_TABLE (PREFIX_0F3A22) },
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 { Bad_Opcode },
5799 /* 28 */
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 /* 30 */
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 /* 38 */
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 /* 40 */
5827 { PREFIX_TABLE (PREFIX_0F3A40) },
5828 { PREFIX_TABLE (PREFIX_0F3A41) },
5829 { PREFIX_TABLE (PREFIX_0F3A42) },
5830 { Bad_Opcode },
5831 { PREFIX_TABLE (PREFIX_0F3A44) },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 /* 48 */
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 /* 50 */
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { Bad_Opcode },
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 /* 58 */
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 /* 60 */
5863 { PREFIX_TABLE (PREFIX_0F3A60) },
5864 { PREFIX_TABLE (PREFIX_0F3A61) },
5865 { PREFIX_TABLE (PREFIX_0F3A62) },
5866 { PREFIX_TABLE (PREFIX_0F3A63) },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 /* 68 */
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 { Bad_Opcode },
5878 { Bad_Opcode },
5879 { Bad_Opcode },
5880 /* 70 */
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 /* 78 */
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 { Bad_Opcode },
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 /* 80 */
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 { Bad_Opcode },
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 /* 88 */
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 { Bad_Opcode },
5914 { Bad_Opcode },
5915 { Bad_Opcode },
5916 /* 90 */
5917 { Bad_Opcode },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 { Bad_Opcode },
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 /* 98 */
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 { Bad_Opcode },
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 /* a0 */
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { Bad_Opcode },
5940 { Bad_Opcode },
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 /* a8 */
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 /* b0 */
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 { Bad_Opcode },
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 /* b8 */
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 { Bad_Opcode },
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 /* c0 */
5971 { Bad_Opcode },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 { Bad_Opcode },
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 /* c8 */
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 { Bad_Opcode },
5986 { Bad_Opcode },
5987 { Bad_Opcode },
5988 /* d0 */
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 { Bad_Opcode },
5995 { Bad_Opcode },
5996 { Bad_Opcode },
5997 /* d8 */
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 { Bad_Opcode },
6004 { Bad_Opcode },
6005 { PREFIX_TABLE (PREFIX_0F3ADF) },
6006 /* e0 */
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 { Bad_Opcode },
6013 { Bad_Opcode },
6014 { Bad_Opcode },
6015 /* e8 */
6016 { Bad_Opcode },
6017 { Bad_Opcode },
6018 { Bad_Opcode },
6019 { Bad_Opcode },
6020 { Bad_Opcode },
6021 { Bad_Opcode },
6022 { Bad_Opcode },
6023 { Bad_Opcode },
6024 /* f0 */
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 /* f8 */
6034 { Bad_Opcode },
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 { Bad_Opcode },
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6044 /* THREE_BYTE_0F7A */
6046 /* 00 */
6047 { Bad_Opcode },
6048 { Bad_Opcode },
6049 { Bad_Opcode },
6050 { Bad_Opcode },
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 { Bad_Opcode },
6054 { Bad_Opcode },
6055 /* 08 */
6056 { Bad_Opcode },
6057 { Bad_Opcode },
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 /* 10 */
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 { Bad_Opcode },
6073 /* 18 */
6074 { Bad_Opcode },
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 { Bad_Opcode },
6082 /* 20 */
6083 { "ptest", { XX } },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { Bad_Opcode },
6091 /* 28 */
6092 { Bad_Opcode },
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 /* 30 */
6101 { Bad_Opcode },
6102 { Bad_Opcode },
6103 { Bad_Opcode },
6104 { Bad_Opcode },
6105 { Bad_Opcode },
6106 { Bad_Opcode },
6107 { Bad_Opcode },
6108 { Bad_Opcode },
6109 /* 38 */
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 { Bad_Opcode },
6116 { Bad_Opcode },
6117 { Bad_Opcode },
6118 /* 40 */
6119 { Bad_Opcode },
6120 { "phaddbw", { XM, EXq } },
6121 { "phaddbd", { XM, EXq } },
6122 { "phaddbq", { XM, EXq } },
6123 { Bad_Opcode },
6124 { Bad_Opcode },
6125 { "phaddwd", { XM, EXq } },
6126 { "phaddwq", { XM, EXq } },
6127 /* 48 */
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 { "phadddq", { XM, EXq } },
6132 { Bad_Opcode },
6133 { Bad_Opcode },
6134 { Bad_Opcode },
6135 { Bad_Opcode },
6136 /* 50 */
6137 { Bad_Opcode },
6138 { "phaddubw", { XM, EXq } },
6139 { "phaddubd", { XM, EXq } },
6140 { "phaddubq", { XM, EXq } },
6141 { Bad_Opcode },
6142 { Bad_Opcode },
6143 { "phadduwd", { XM, EXq } },
6144 { "phadduwq", { XM, EXq } },
6145 /* 58 */
6146 { Bad_Opcode },
6147 { Bad_Opcode },
6148 { Bad_Opcode },
6149 { "phaddudq", { XM, EXq } },
6150 { Bad_Opcode },
6151 { Bad_Opcode },
6152 { Bad_Opcode },
6153 { Bad_Opcode },
6154 /* 60 */
6155 { Bad_Opcode },
6156 { "phsubbw", { XM, EXq } },
6157 { "phsubbd", { XM, EXq } },
6158 { "phsubbq", { XM, EXq } },
6159 { Bad_Opcode },
6160 { Bad_Opcode },
6161 { Bad_Opcode },
6162 { Bad_Opcode },
6163 /* 68 */
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { Bad_Opcode },
6169 { Bad_Opcode },
6170 { Bad_Opcode },
6171 { Bad_Opcode },
6172 /* 70 */
6173 { Bad_Opcode },
6174 { Bad_Opcode },
6175 { Bad_Opcode },
6176 { Bad_Opcode },
6177 { Bad_Opcode },
6178 { Bad_Opcode },
6179 { Bad_Opcode },
6180 { Bad_Opcode },
6181 /* 78 */
6182 { Bad_Opcode },
6183 { Bad_Opcode },
6184 { Bad_Opcode },
6185 { Bad_Opcode },
6186 { Bad_Opcode },
6187 { Bad_Opcode },
6188 { Bad_Opcode },
6189 { Bad_Opcode },
6190 /* 80 */
6191 { Bad_Opcode },
6192 { Bad_Opcode },
6193 { Bad_Opcode },
6194 { Bad_Opcode },
6195 { Bad_Opcode },
6196 { Bad_Opcode },
6197 { Bad_Opcode },
6198 { Bad_Opcode },
6199 /* 88 */
6200 { Bad_Opcode },
6201 { Bad_Opcode },
6202 { Bad_Opcode },
6203 { Bad_Opcode },
6204 { Bad_Opcode },
6205 { Bad_Opcode },
6206 { Bad_Opcode },
6207 { Bad_Opcode },
6208 /* 90 */
6209 { Bad_Opcode },
6210 { Bad_Opcode },
6211 { Bad_Opcode },
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 { Bad_Opcode },
6215 { Bad_Opcode },
6216 { Bad_Opcode },
6217 /* 98 */
6218 { Bad_Opcode },
6219 { Bad_Opcode },
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { Bad_Opcode },
6223 { Bad_Opcode },
6224 { Bad_Opcode },
6225 { Bad_Opcode },
6226 /* a0 */
6227 { Bad_Opcode },
6228 { Bad_Opcode },
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 { Bad_Opcode },
6233 { Bad_Opcode },
6234 { Bad_Opcode },
6235 /* a8 */
6236 { Bad_Opcode },
6237 { Bad_Opcode },
6238 { Bad_Opcode },
6239 { Bad_Opcode },
6240 { Bad_Opcode },
6241 { Bad_Opcode },
6242 { Bad_Opcode },
6243 { Bad_Opcode },
6244 /* b0 */
6245 { Bad_Opcode },
6246 { Bad_Opcode },
6247 { Bad_Opcode },
6248 { Bad_Opcode },
6249 { Bad_Opcode },
6250 { Bad_Opcode },
6251 { Bad_Opcode },
6252 { Bad_Opcode },
6253 /* b8 */
6254 { Bad_Opcode },
6255 { Bad_Opcode },
6256 { Bad_Opcode },
6257 { Bad_Opcode },
6258 { Bad_Opcode },
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 { Bad_Opcode },
6262 /* c0 */
6263 { Bad_Opcode },
6264 { Bad_Opcode },
6265 { Bad_Opcode },
6266 { Bad_Opcode },
6267 { Bad_Opcode },
6268 { Bad_Opcode },
6269 { Bad_Opcode },
6270 { Bad_Opcode },
6271 /* c8 */
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 { Bad_Opcode },
6280 /* d0 */
6281 { Bad_Opcode },
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 { Bad_Opcode },
6289 /* d8 */
6290 { Bad_Opcode },
6291 { Bad_Opcode },
6292 { Bad_Opcode },
6293 { Bad_Opcode },
6294 { Bad_Opcode },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 /* e0 */
6299 { Bad_Opcode },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { Bad_Opcode },
6303 { Bad_Opcode },
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 { Bad_Opcode },
6307 /* e8 */
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { Bad_Opcode },
6315 { Bad_Opcode },
6316 /* f0 */
6317 { Bad_Opcode },
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 { Bad_Opcode },
6323 { Bad_Opcode },
6324 { Bad_Opcode },
6325 /* f8 */
6326 { Bad_Opcode },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 { Bad_Opcode },
6333 { Bad_Opcode },
6337 static const struct dis386 xop_table[][256] = {
6338 /* XOP_08 */
6340 /* 00 */
6341 { Bad_Opcode },
6342 { Bad_Opcode },
6343 { Bad_Opcode },
6344 { Bad_Opcode },
6345 { Bad_Opcode },
6346 { Bad_Opcode },
6347 { Bad_Opcode },
6348 { Bad_Opcode },
6349 /* 08 */
6350 { Bad_Opcode },
6351 { Bad_Opcode },
6352 { Bad_Opcode },
6353 { Bad_Opcode },
6354 { Bad_Opcode },
6355 { Bad_Opcode },
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 /* 10 */
6359 { Bad_Opcode },
6360 { Bad_Opcode },
6361 { Bad_Opcode },
6362 { Bad_Opcode },
6363 { Bad_Opcode },
6364 { Bad_Opcode },
6365 { Bad_Opcode },
6366 { Bad_Opcode },
6367 /* 18 */
6368 { Bad_Opcode },
6369 { Bad_Opcode },
6370 { Bad_Opcode },
6371 { Bad_Opcode },
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 /* 20 */
6377 { Bad_Opcode },
6378 { Bad_Opcode },
6379 { Bad_Opcode },
6380 { Bad_Opcode },
6381 { Bad_Opcode },
6382 { Bad_Opcode },
6383 { Bad_Opcode },
6384 { Bad_Opcode },
6385 /* 28 */
6386 { Bad_Opcode },
6387 { Bad_Opcode },
6388 { Bad_Opcode },
6389 { Bad_Opcode },
6390 { Bad_Opcode },
6391 { Bad_Opcode },
6392 { Bad_Opcode },
6393 { Bad_Opcode },
6394 /* 30 */
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { Bad_Opcode },
6398 { Bad_Opcode },
6399 { Bad_Opcode },
6400 { Bad_Opcode },
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 /* 38 */
6404 { Bad_Opcode },
6405 { Bad_Opcode },
6406 { Bad_Opcode },
6407 { Bad_Opcode },
6408 { Bad_Opcode },
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 /* 40 */
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 { Bad_Opcode },
6417 { Bad_Opcode },
6418 { Bad_Opcode },
6419 { Bad_Opcode },
6420 { Bad_Opcode },
6421 /* 48 */
6422 { Bad_Opcode },
6423 { Bad_Opcode },
6424 { Bad_Opcode },
6425 { Bad_Opcode },
6426 { Bad_Opcode },
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 /* 50 */
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 { Bad_Opcode },
6435 { Bad_Opcode },
6436 { Bad_Opcode },
6437 { Bad_Opcode },
6438 { Bad_Opcode },
6439 /* 58 */
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 { Bad_Opcode },
6444 { Bad_Opcode },
6445 { Bad_Opcode },
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 /* 60 */
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 { Bad_Opcode },
6454 { Bad_Opcode },
6455 { Bad_Opcode },
6456 { Bad_Opcode },
6457 /* 68 */
6458 { Bad_Opcode },
6459 { Bad_Opcode },
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 { Bad_Opcode },
6463 { Bad_Opcode },
6464 { Bad_Opcode },
6465 { Bad_Opcode },
6466 /* 70 */
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 { Bad_Opcode },
6472 { Bad_Opcode },
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 /* 78 */
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 { Bad_Opcode },
6480 { Bad_Opcode },
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 /* 80 */
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { Bad_Opcode },
6489 { Bad_Opcode },
6490 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6491 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6492 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6493 /* 88 */
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 { Bad_Opcode },
6499 { Bad_Opcode },
6500 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6501 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6502 /* 90 */
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 { Bad_Opcode },
6508 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6509 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6510 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6511 /* 98 */
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 { Bad_Opcode },
6517 { Bad_Opcode },
6518 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6519 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6520 /* a0 */
6521 { Bad_Opcode },
6522 { Bad_Opcode },
6523 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6524 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6525 { Bad_Opcode },
6526 { Bad_Opcode },
6527 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6528 { Bad_Opcode },
6529 /* a8 */
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 { Bad_Opcode },
6535 { Bad_Opcode },
6536 { Bad_Opcode },
6537 { Bad_Opcode },
6538 /* b0 */
6539 { Bad_Opcode },
6540 { Bad_Opcode },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 { Bad_Opcode },
6544 { Bad_Opcode },
6545 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6546 { Bad_Opcode },
6547 /* b8 */
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 { Bad_Opcode },
6552 { Bad_Opcode },
6553 { Bad_Opcode },
6554 { Bad_Opcode },
6555 { Bad_Opcode },
6556 /* c0 */
6557 { "vprotb", { XM, Vex_2src_1, Ib } },
6558 { "vprotw", { XM, Vex_2src_1, Ib } },
6559 { "vprotd", { XM, Vex_2src_1, Ib } },
6560 { "vprotq", { XM, Vex_2src_1, Ib } },
6561 { Bad_Opcode },
6562 { Bad_Opcode },
6563 { Bad_Opcode },
6564 { Bad_Opcode },
6565 /* c8 */
6566 { Bad_Opcode },
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { Bad_Opcode },
6570 { "vpcomb", { XM, Vex128, EXx, Ib } },
6571 { "vpcomw", { XM, Vex128, EXx, Ib } },
6572 { "vpcomd", { XM, Vex128, EXx, Ib } },
6573 { "vpcomq", { XM, Vex128, EXx, Ib } },
6574 /* d0 */
6575 { Bad_Opcode },
6576 { Bad_Opcode },
6577 { Bad_Opcode },
6578 { Bad_Opcode },
6579 { Bad_Opcode },
6580 { Bad_Opcode },
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 /* d8 */
6584 { Bad_Opcode },
6585 { Bad_Opcode },
6586 { Bad_Opcode },
6587 { Bad_Opcode },
6588 { Bad_Opcode },
6589 { Bad_Opcode },
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 /* e0 */
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { Bad_Opcode },
6597 { Bad_Opcode },
6598 { Bad_Opcode },
6599 { Bad_Opcode },
6600 { Bad_Opcode },
6601 /* e8 */
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 { Bad_Opcode },
6606 { "vpcomub", { XM, Vex128, EXx, Ib } },
6607 { "vpcomuw", { XM, Vex128, EXx, Ib } },
6608 { "vpcomud", { XM, Vex128, EXx, Ib } },
6609 { "vpcomuq", { XM, Vex128, EXx, Ib } },
6610 /* f0 */
6611 { Bad_Opcode },
6612 { Bad_Opcode },
6613 { Bad_Opcode },
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 { Bad_Opcode },
6617 { Bad_Opcode },
6618 { Bad_Opcode },
6619 /* f8 */
6620 { Bad_Opcode },
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 { Bad_Opcode },
6624 { Bad_Opcode },
6625 { Bad_Opcode },
6626 { Bad_Opcode },
6627 { Bad_Opcode },
6629 /* XOP_09 */
6631 /* 00 */
6632 { Bad_Opcode },
6633 { Bad_Opcode },
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 { Bad_Opcode },
6639 { Bad_Opcode },
6640 /* 08 */
6641 { Bad_Opcode },
6642 { Bad_Opcode },
6643 { Bad_Opcode },
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 /* 10 */
6650 { Bad_Opcode },
6651 { Bad_Opcode },
6652 { REG_TABLE (REG_XOP_LWPCB) },
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 /* 18 */
6659 { Bad_Opcode },
6660 { Bad_Opcode },
6661 { Bad_Opcode },
6662 { Bad_Opcode },
6663 { Bad_Opcode },
6664 { Bad_Opcode },
6665 { Bad_Opcode },
6666 { Bad_Opcode },
6667 /* 20 */
6668 { Bad_Opcode },
6669 { Bad_Opcode },
6670 { Bad_Opcode },
6671 { Bad_Opcode },
6672 { Bad_Opcode },
6673 { Bad_Opcode },
6674 { Bad_Opcode },
6675 { Bad_Opcode },
6676 /* 28 */
6677 { Bad_Opcode },
6678 { Bad_Opcode },
6679 { Bad_Opcode },
6680 { Bad_Opcode },
6681 { Bad_Opcode },
6682 { Bad_Opcode },
6683 { Bad_Opcode },
6684 { Bad_Opcode },
6685 /* 30 */
6686 { Bad_Opcode },
6687 { Bad_Opcode },
6688 { Bad_Opcode },
6689 { Bad_Opcode },
6690 { Bad_Opcode },
6691 { Bad_Opcode },
6692 { Bad_Opcode },
6693 { Bad_Opcode },
6694 /* 38 */
6695 { Bad_Opcode },
6696 { Bad_Opcode },
6697 { Bad_Opcode },
6698 { Bad_Opcode },
6699 { Bad_Opcode },
6700 { Bad_Opcode },
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 /* 40 */
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 { Bad_Opcode },
6708 { Bad_Opcode },
6709 { Bad_Opcode },
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 /* 48 */
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 { Bad_Opcode },
6716 { Bad_Opcode },
6717 { Bad_Opcode },
6718 { Bad_Opcode },
6719 { Bad_Opcode },
6720 { Bad_Opcode },
6721 /* 50 */
6722 { Bad_Opcode },
6723 { Bad_Opcode },
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 { Bad_Opcode },
6727 { Bad_Opcode },
6728 { Bad_Opcode },
6729 { Bad_Opcode },
6730 /* 58 */
6731 { Bad_Opcode },
6732 { Bad_Opcode },
6733 { Bad_Opcode },
6734 { Bad_Opcode },
6735 { Bad_Opcode },
6736 { Bad_Opcode },
6737 { Bad_Opcode },
6738 { Bad_Opcode },
6739 /* 60 */
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 { Bad_Opcode },
6745 { Bad_Opcode },
6746 { Bad_Opcode },
6747 { Bad_Opcode },
6748 /* 68 */
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 { Bad_Opcode },
6753 { Bad_Opcode },
6754 { Bad_Opcode },
6755 { Bad_Opcode },
6756 { Bad_Opcode },
6757 /* 70 */
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 { Bad_Opcode },
6763 { Bad_Opcode },
6764 { Bad_Opcode },
6765 { Bad_Opcode },
6766 /* 78 */
6767 { Bad_Opcode },
6768 { Bad_Opcode },
6769 { Bad_Opcode },
6770 { Bad_Opcode },
6771 { Bad_Opcode },
6772 { Bad_Opcode },
6773 { Bad_Opcode },
6774 { Bad_Opcode },
6775 /* 80 */
6776 { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6777 { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6778 { "vfrczss", { XM, EXd } },
6779 { "vfrczsd", { XM, EXq } },
6780 { Bad_Opcode },
6781 { Bad_Opcode },
6782 { Bad_Opcode },
6783 { Bad_Opcode },
6784 /* 88 */
6785 { Bad_Opcode },
6786 { Bad_Opcode },
6787 { Bad_Opcode },
6788 { Bad_Opcode },
6789 { Bad_Opcode },
6790 { Bad_Opcode },
6791 { Bad_Opcode },
6792 { Bad_Opcode },
6793 /* 90 */
6794 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
6795 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
6796 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
6797 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
6798 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
6799 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
6800 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
6801 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
6802 /* 98 */
6803 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
6804 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
6805 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
6806 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
6807 { Bad_Opcode },
6808 { Bad_Opcode },
6809 { Bad_Opcode },
6810 { Bad_Opcode },
6811 /* a0 */
6812 { Bad_Opcode },
6813 { Bad_Opcode },
6814 { Bad_Opcode },
6815 { Bad_Opcode },
6816 { Bad_Opcode },
6817 { Bad_Opcode },
6818 { Bad_Opcode },
6819 { Bad_Opcode },
6820 /* a8 */
6821 { Bad_Opcode },
6822 { Bad_Opcode },
6823 { Bad_Opcode },
6824 { Bad_Opcode },
6825 { Bad_Opcode },
6826 { Bad_Opcode },
6827 { Bad_Opcode },
6828 { Bad_Opcode },
6829 /* b0 */
6830 { Bad_Opcode },
6831 { Bad_Opcode },
6832 { Bad_Opcode },
6833 { Bad_Opcode },
6834 { Bad_Opcode },
6835 { Bad_Opcode },
6836 { Bad_Opcode },
6837 { Bad_Opcode },
6838 /* b8 */
6839 { Bad_Opcode },
6840 { Bad_Opcode },
6841 { Bad_Opcode },
6842 { Bad_Opcode },
6843 { Bad_Opcode },
6844 { Bad_Opcode },
6845 { Bad_Opcode },
6846 { Bad_Opcode },
6847 /* c0 */
6848 { Bad_Opcode },
6849 { "vphaddbw", { XM, EXxmm } },
6850 { "vphaddbd", { XM, EXxmm } },
6851 { "vphaddbq", { XM, EXxmm } },
6852 { Bad_Opcode },
6853 { Bad_Opcode },
6854 { "vphaddwd", { XM, EXxmm } },
6855 { "vphaddwq", { XM, EXxmm } },
6856 /* c8 */
6857 { Bad_Opcode },
6858 { Bad_Opcode },
6859 { Bad_Opcode },
6860 { "vphadddq", { XM, EXxmm } },
6861 { Bad_Opcode },
6862 { Bad_Opcode },
6863 { Bad_Opcode },
6864 { Bad_Opcode },
6865 /* d0 */
6866 { Bad_Opcode },
6867 { "vphaddubw", { XM, EXxmm } },
6868 { "vphaddubd", { XM, EXxmm } },
6869 { "vphaddubq", { XM, EXxmm } },
6870 { Bad_Opcode },
6871 { Bad_Opcode },
6872 { "vphadduwd", { XM, EXxmm } },
6873 { "vphadduwq", { XM, EXxmm } },
6874 /* d8 */
6875 { Bad_Opcode },
6876 { Bad_Opcode },
6877 { Bad_Opcode },
6878 { "vphaddudq", { XM, EXxmm } },
6879 { Bad_Opcode },
6880 { Bad_Opcode },
6881 { Bad_Opcode },
6882 { Bad_Opcode },
6883 /* e0 */
6884 { Bad_Opcode },
6885 { "vphsubbw", { XM, EXxmm } },
6886 { "vphsubwd", { XM, EXxmm } },
6887 { "vphsubdq", { XM, EXxmm } },
6888 { Bad_Opcode },
6889 { Bad_Opcode },
6890 { Bad_Opcode },
6891 { Bad_Opcode },
6892 /* e8 */
6893 { Bad_Opcode },
6894 { Bad_Opcode },
6895 { Bad_Opcode },
6896 { Bad_Opcode },
6897 { Bad_Opcode },
6898 { Bad_Opcode },
6899 { Bad_Opcode },
6900 { Bad_Opcode },
6901 /* f0 */
6902 { Bad_Opcode },
6903 { Bad_Opcode },
6904 { Bad_Opcode },
6905 { Bad_Opcode },
6906 { Bad_Opcode },
6907 { Bad_Opcode },
6908 { Bad_Opcode },
6909 { Bad_Opcode },
6910 /* f8 */
6911 { Bad_Opcode },
6912 { Bad_Opcode },
6913 { Bad_Opcode },
6914 { Bad_Opcode },
6915 { Bad_Opcode },
6916 { Bad_Opcode },
6917 { Bad_Opcode },
6918 { Bad_Opcode },
6920 /* XOP_0A */
6922 /* 00 */
6923 { Bad_Opcode },
6924 { Bad_Opcode },
6925 { Bad_Opcode },
6926 { Bad_Opcode },
6927 { Bad_Opcode },
6928 { Bad_Opcode },
6929 { Bad_Opcode },
6930 { Bad_Opcode },
6931 /* 08 */
6932 { Bad_Opcode },
6933 { Bad_Opcode },
6934 { Bad_Opcode },
6935 { Bad_Opcode },
6936 { Bad_Opcode },
6937 { Bad_Opcode },
6938 { Bad_Opcode },
6939 { Bad_Opcode },
6940 /* 10 */
6941 { Bad_Opcode },
6942 { Bad_Opcode },
6943 { REG_TABLE (REG_XOP_LWP) },
6944 { Bad_Opcode },
6945 { Bad_Opcode },
6946 { Bad_Opcode },
6947 { Bad_Opcode },
6948 { Bad_Opcode },
6949 /* 18 */
6950 { Bad_Opcode },
6951 { Bad_Opcode },
6952 { Bad_Opcode },
6953 { Bad_Opcode },
6954 { Bad_Opcode },
6955 { Bad_Opcode },
6956 { Bad_Opcode },
6957 { Bad_Opcode },
6958 /* 20 */
6959 { Bad_Opcode },
6960 { Bad_Opcode },
6961 { Bad_Opcode },
6962 { Bad_Opcode },
6963 { Bad_Opcode },
6964 { Bad_Opcode },
6965 { Bad_Opcode },
6966 { Bad_Opcode },
6967 /* 28 */
6968 { Bad_Opcode },
6969 { Bad_Opcode },
6970 { Bad_Opcode },
6971 { Bad_Opcode },
6972 { Bad_Opcode },
6973 { Bad_Opcode },
6974 { Bad_Opcode },
6975 { Bad_Opcode },
6976 /* 30 */
6977 { Bad_Opcode },
6978 { Bad_Opcode },
6979 { Bad_Opcode },
6980 { Bad_Opcode },
6981 { Bad_Opcode },
6982 { Bad_Opcode },
6983 { Bad_Opcode },
6984 { Bad_Opcode },
6985 /* 38 */
6986 { Bad_Opcode },
6987 { Bad_Opcode },
6988 { Bad_Opcode },
6989 { Bad_Opcode },
6990 { Bad_Opcode },
6991 { Bad_Opcode },
6992 { Bad_Opcode },
6993 { Bad_Opcode },
6994 /* 40 */
6995 { Bad_Opcode },
6996 { Bad_Opcode },
6997 { Bad_Opcode },
6998 { Bad_Opcode },
6999 { Bad_Opcode },
7000 { Bad_Opcode },
7001 { Bad_Opcode },
7002 { Bad_Opcode },
7003 /* 48 */
7004 { Bad_Opcode },
7005 { Bad_Opcode },
7006 { Bad_Opcode },
7007 { Bad_Opcode },
7008 { Bad_Opcode },
7009 { Bad_Opcode },
7010 { Bad_Opcode },
7011 { Bad_Opcode },
7012 /* 50 */
7013 { Bad_Opcode },
7014 { Bad_Opcode },
7015 { Bad_Opcode },
7016 { Bad_Opcode },
7017 { Bad_Opcode },
7018 { Bad_Opcode },
7019 { Bad_Opcode },
7020 { Bad_Opcode },
7021 /* 58 */
7022 { Bad_Opcode },
7023 { Bad_Opcode },
7024 { Bad_Opcode },
7025 { Bad_Opcode },
7026 { Bad_Opcode },
7027 { Bad_Opcode },
7028 { Bad_Opcode },
7029 { Bad_Opcode },
7030 /* 60 */
7031 { Bad_Opcode },
7032 { Bad_Opcode },
7033 { Bad_Opcode },
7034 { Bad_Opcode },
7035 { Bad_Opcode },
7036 { Bad_Opcode },
7037 { Bad_Opcode },
7038 { Bad_Opcode },
7039 /* 68 */
7040 { Bad_Opcode },
7041 { Bad_Opcode },
7042 { Bad_Opcode },
7043 { Bad_Opcode },
7044 { Bad_Opcode },
7045 { Bad_Opcode },
7046 { Bad_Opcode },
7047 { Bad_Opcode },
7048 /* 70 */
7049 { Bad_Opcode },
7050 { Bad_Opcode },
7051 { Bad_Opcode },
7052 { Bad_Opcode },
7053 { Bad_Opcode },
7054 { Bad_Opcode },
7055 { Bad_Opcode },
7056 { Bad_Opcode },
7057 /* 78 */
7058 { Bad_Opcode },
7059 { Bad_Opcode },
7060 { Bad_Opcode },
7061 { Bad_Opcode },
7062 { Bad_Opcode },
7063 { Bad_Opcode },
7064 { Bad_Opcode },
7065 { Bad_Opcode },
7066 /* 80 */
7067 { Bad_Opcode },
7068 { Bad_Opcode },
7069 { Bad_Opcode },
7070 { Bad_Opcode },
7071 { Bad_Opcode },
7072 { Bad_Opcode },
7073 { Bad_Opcode },
7074 { Bad_Opcode },
7075 /* 88 */
7076 { Bad_Opcode },
7077 { Bad_Opcode },
7078 { Bad_Opcode },
7079 { Bad_Opcode },
7080 { Bad_Opcode },
7081 { Bad_Opcode },
7082 { Bad_Opcode },
7083 { Bad_Opcode },
7084 /* 90 */
7085 { Bad_Opcode },
7086 { Bad_Opcode },
7087 { Bad_Opcode },
7088 { Bad_Opcode },
7089 { Bad_Opcode },
7090 { Bad_Opcode },
7091 { Bad_Opcode },
7092 { Bad_Opcode },
7093 /* 98 */
7094 { Bad_Opcode },
7095 { Bad_Opcode },
7096 { Bad_Opcode },
7097 { Bad_Opcode },
7098 { Bad_Opcode },
7099 { Bad_Opcode },
7100 { Bad_Opcode },
7101 { Bad_Opcode },
7102 /* a0 */
7103 { Bad_Opcode },
7104 { Bad_Opcode },
7105 { Bad_Opcode },
7106 { Bad_Opcode },
7107 { Bad_Opcode },
7108 { Bad_Opcode },
7109 { Bad_Opcode },
7110 { Bad_Opcode },
7111 /* a8 */
7112 { Bad_Opcode },
7113 { Bad_Opcode },
7114 { Bad_Opcode },
7115 { Bad_Opcode },
7116 { Bad_Opcode },
7117 { Bad_Opcode },
7118 { Bad_Opcode },
7119 { Bad_Opcode },
7120 /* b0 */
7121 { Bad_Opcode },
7122 { Bad_Opcode },
7123 { Bad_Opcode },
7124 { Bad_Opcode },
7125 { Bad_Opcode },
7126 { Bad_Opcode },
7127 { Bad_Opcode },
7128 { Bad_Opcode },
7129 /* b8 */
7130 { Bad_Opcode },
7131 { Bad_Opcode },
7132 { Bad_Opcode },
7133 { Bad_Opcode },
7134 { Bad_Opcode },
7135 { Bad_Opcode },
7136 { Bad_Opcode },
7137 { Bad_Opcode },
7138 /* c0 */
7139 { Bad_Opcode },
7140 { Bad_Opcode },
7141 { Bad_Opcode },
7142 { Bad_Opcode },
7143 { Bad_Opcode },
7144 { Bad_Opcode },
7145 { Bad_Opcode },
7146 { Bad_Opcode },
7147 /* c8 */
7148 { Bad_Opcode },
7149 { Bad_Opcode },
7150 { Bad_Opcode },
7151 { Bad_Opcode },
7152 { Bad_Opcode },
7153 { Bad_Opcode },
7154 { Bad_Opcode },
7155 { Bad_Opcode },
7156 /* d0 */
7157 { Bad_Opcode },
7158 { Bad_Opcode },
7159 { Bad_Opcode },
7160 { Bad_Opcode },
7161 { Bad_Opcode },
7162 { Bad_Opcode },
7163 { Bad_Opcode },
7164 { Bad_Opcode },
7165 /* d8 */
7166 { Bad_Opcode },
7167 { Bad_Opcode },
7168 { Bad_Opcode },
7169 { Bad_Opcode },
7170 { Bad_Opcode },
7171 { Bad_Opcode },
7172 { Bad_Opcode },
7173 { Bad_Opcode },
7174 /* e0 */
7175 { Bad_Opcode },
7176 { Bad_Opcode },
7177 { Bad_Opcode },
7178 { Bad_Opcode },
7179 { Bad_Opcode },
7180 { Bad_Opcode },
7181 { Bad_Opcode },
7182 { Bad_Opcode },
7183 /* e8 */
7184 { Bad_Opcode },
7185 { Bad_Opcode },
7186 { Bad_Opcode },
7187 { Bad_Opcode },
7188 { Bad_Opcode },
7189 { Bad_Opcode },
7190 { Bad_Opcode },
7191 { Bad_Opcode },
7192 /* f0 */
7193 { Bad_Opcode },
7194 { Bad_Opcode },
7195 { Bad_Opcode },
7196 { Bad_Opcode },
7197 { Bad_Opcode },
7198 { Bad_Opcode },
7199 { Bad_Opcode },
7200 { Bad_Opcode },
7201 /* f8 */
7202 { Bad_Opcode },
7203 { Bad_Opcode },
7204 { Bad_Opcode },
7205 { Bad_Opcode },
7206 { Bad_Opcode },
7207 { Bad_Opcode },
7208 { Bad_Opcode },
7209 { Bad_Opcode },
7213 static const struct dis386 vex_table[][256] = {
7214 /* VEX_0F */
7216 /* 00 */
7217 { Bad_Opcode },
7218 { Bad_Opcode },
7219 { Bad_Opcode },
7220 { Bad_Opcode },
7221 { Bad_Opcode },
7222 { Bad_Opcode },
7223 { Bad_Opcode },
7224 { Bad_Opcode },
7225 /* 08 */
7226 { Bad_Opcode },
7227 { Bad_Opcode },
7228 { Bad_Opcode },
7229 { Bad_Opcode },
7230 { Bad_Opcode },
7231 { Bad_Opcode },
7232 { Bad_Opcode },
7233 { Bad_Opcode },
7234 /* 10 */
7235 { PREFIX_TABLE (PREFIX_VEX_10) },
7236 { PREFIX_TABLE (PREFIX_VEX_11) },
7237 { PREFIX_TABLE (PREFIX_VEX_12) },
7238 { MOD_TABLE (MOD_VEX_13) },
7239 { VEX_W_TABLE (VEX_W_14) },
7240 { VEX_W_TABLE (VEX_W_15) },
7241 { PREFIX_TABLE (PREFIX_VEX_16) },
7242 { MOD_TABLE (MOD_VEX_17) },
7243 /* 18 */
7244 { Bad_Opcode },
7245 { Bad_Opcode },
7246 { Bad_Opcode },
7247 { Bad_Opcode },
7248 { Bad_Opcode },
7249 { Bad_Opcode },
7250 { Bad_Opcode },
7251 { Bad_Opcode },
7252 /* 20 */
7253 { Bad_Opcode },
7254 { Bad_Opcode },
7255 { Bad_Opcode },
7256 { Bad_Opcode },
7257 { Bad_Opcode },
7258 { Bad_Opcode },
7259 { Bad_Opcode },
7260 { Bad_Opcode },
7261 /* 28 */
7262 { VEX_W_TABLE (VEX_W_28) },
7263 { VEX_W_TABLE (VEX_W_29) },
7264 { PREFIX_TABLE (PREFIX_VEX_2A) },
7265 { MOD_TABLE (MOD_VEX_2B) },
7266 { PREFIX_TABLE (PREFIX_VEX_2C) },
7267 { PREFIX_TABLE (PREFIX_VEX_2D) },
7268 { PREFIX_TABLE (PREFIX_VEX_2E) },
7269 { PREFIX_TABLE (PREFIX_VEX_2F) },
7270 /* 30 */
7271 { Bad_Opcode },
7272 { Bad_Opcode },
7273 { Bad_Opcode },
7274 { Bad_Opcode },
7275 { Bad_Opcode },
7276 { Bad_Opcode },
7277 { Bad_Opcode },
7278 { Bad_Opcode },
7279 /* 38 */
7280 { Bad_Opcode },
7281 { Bad_Opcode },
7282 { Bad_Opcode },
7283 { Bad_Opcode },
7284 { Bad_Opcode },
7285 { Bad_Opcode },
7286 { Bad_Opcode },
7287 { Bad_Opcode },
7288 /* 40 */
7289 { Bad_Opcode },
7290 { Bad_Opcode },
7291 { Bad_Opcode },
7292 { Bad_Opcode },
7293 { Bad_Opcode },
7294 { Bad_Opcode },
7295 { Bad_Opcode },
7296 { Bad_Opcode },
7297 /* 48 */
7298 { Bad_Opcode },
7299 { Bad_Opcode },
7300 { Bad_Opcode },
7301 { Bad_Opcode },
7302 { Bad_Opcode },
7303 { Bad_Opcode },
7304 { Bad_Opcode },
7305 { Bad_Opcode },
7306 /* 50 */
7307 { MOD_TABLE (MOD_VEX_50) },
7308 { PREFIX_TABLE (PREFIX_VEX_51) },
7309 { PREFIX_TABLE (PREFIX_VEX_52) },
7310 { PREFIX_TABLE (PREFIX_VEX_53) },
7311 { "vandpX", { XM, Vex, EXx } },
7312 { "vandnpX", { XM, Vex, EXx } },
7313 { "vorpX", { XM, Vex, EXx } },
7314 { "vxorpX", { XM, Vex, EXx } },
7315 /* 58 */
7316 { PREFIX_TABLE (PREFIX_VEX_58) },
7317 { PREFIX_TABLE (PREFIX_VEX_59) },
7318 { PREFIX_TABLE (PREFIX_VEX_5A) },
7319 { PREFIX_TABLE (PREFIX_VEX_5B) },
7320 { PREFIX_TABLE (PREFIX_VEX_5C) },
7321 { PREFIX_TABLE (PREFIX_VEX_5D) },
7322 { PREFIX_TABLE (PREFIX_VEX_5E) },
7323 { PREFIX_TABLE (PREFIX_VEX_5F) },
7324 /* 60 */
7325 { PREFIX_TABLE (PREFIX_VEX_60) },
7326 { PREFIX_TABLE (PREFIX_VEX_61) },
7327 { PREFIX_TABLE (PREFIX_VEX_62) },
7328 { PREFIX_TABLE (PREFIX_VEX_63) },
7329 { PREFIX_TABLE (PREFIX_VEX_64) },
7330 { PREFIX_TABLE (PREFIX_VEX_65) },
7331 { PREFIX_TABLE (PREFIX_VEX_66) },
7332 { PREFIX_TABLE (PREFIX_VEX_67) },
7333 /* 68 */
7334 { PREFIX_TABLE (PREFIX_VEX_68) },
7335 { PREFIX_TABLE (PREFIX_VEX_69) },
7336 { PREFIX_TABLE (PREFIX_VEX_6A) },
7337 { PREFIX_TABLE (PREFIX_VEX_6B) },
7338 { PREFIX_TABLE (PREFIX_VEX_6C) },
7339 { PREFIX_TABLE (PREFIX_VEX_6D) },
7340 { PREFIX_TABLE (PREFIX_VEX_6E) },
7341 { PREFIX_TABLE (PREFIX_VEX_6F) },
7342 /* 70 */
7343 { PREFIX_TABLE (PREFIX_VEX_70) },
7344 { REG_TABLE (REG_VEX_71) },
7345 { REG_TABLE (REG_VEX_72) },
7346 { REG_TABLE (REG_VEX_73) },
7347 { PREFIX_TABLE (PREFIX_VEX_74) },
7348 { PREFIX_TABLE (PREFIX_VEX_75) },
7349 { PREFIX_TABLE (PREFIX_VEX_76) },
7350 { PREFIX_TABLE (PREFIX_VEX_77) },
7351 /* 78 */
7352 { Bad_Opcode },
7353 { Bad_Opcode },
7354 { Bad_Opcode },
7355 { Bad_Opcode },
7356 { PREFIX_TABLE (PREFIX_VEX_7C) },
7357 { PREFIX_TABLE (PREFIX_VEX_7D) },
7358 { PREFIX_TABLE (PREFIX_VEX_7E) },
7359 { PREFIX_TABLE (PREFIX_VEX_7F) },
7360 /* 80 */
7361 { Bad_Opcode },
7362 { Bad_Opcode },
7363 { Bad_Opcode },
7364 { Bad_Opcode },
7365 { Bad_Opcode },
7366 { Bad_Opcode },
7367 { Bad_Opcode },
7368 { Bad_Opcode },
7369 /* 88 */
7370 { Bad_Opcode },
7371 { Bad_Opcode },
7372 { Bad_Opcode },
7373 { Bad_Opcode },
7374 { Bad_Opcode },
7375 { Bad_Opcode },
7376 { Bad_Opcode },
7377 { Bad_Opcode },
7378 /* 90 */
7379 { Bad_Opcode },
7380 { Bad_Opcode },
7381 { Bad_Opcode },
7382 { Bad_Opcode },
7383 { Bad_Opcode },
7384 { Bad_Opcode },
7385 { Bad_Opcode },
7386 { Bad_Opcode },
7387 /* 98 */
7388 { Bad_Opcode },
7389 { Bad_Opcode },
7390 { Bad_Opcode },
7391 { Bad_Opcode },
7392 { Bad_Opcode },
7393 { Bad_Opcode },
7394 { Bad_Opcode },
7395 { Bad_Opcode },
7396 /* a0 */
7397 { Bad_Opcode },
7398 { Bad_Opcode },
7399 { Bad_Opcode },
7400 { Bad_Opcode },
7401 { Bad_Opcode },
7402 { Bad_Opcode },
7403 { Bad_Opcode },
7404 { Bad_Opcode },
7405 /* a8 */
7406 { Bad_Opcode },
7407 { Bad_Opcode },
7408 { Bad_Opcode },
7409 { Bad_Opcode },
7410 { Bad_Opcode },
7411 { Bad_Opcode },
7412 { REG_TABLE (REG_VEX_AE) },
7413 { Bad_Opcode },
7414 /* b0 */
7415 { Bad_Opcode },
7416 { Bad_Opcode },
7417 { Bad_Opcode },
7418 { Bad_Opcode },
7419 { Bad_Opcode },
7420 { Bad_Opcode },
7421 { Bad_Opcode },
7422 { Bad_Opcode },
7423 /* b8 */
7424 { Bad_Opcode },
7425 { Bad_Opcode },
7426 { Bad_Opcode },
7427 { Bad_Opcode },
7428 { Bad_Opcode },
7429 { Bad_Opcode },
7430 { Bad_Opcode },
7431 { Bad_Opcode },
7432 /* c0 */
7433 { Bad_Opcode },
7434 { Bad_Opcode },
7435 { PREFIX_TABLE (PREFIX_VEX_C2) },
7436 { Bad_Opcode },
7437 { PREFIX_TABLE (PREFIX_VEX_C4) },
7438 { PREFIX_TABLE (PREFIX_VEX_C5) },
7439 { "vshufpX", { XM, Vex, EXx, Ib } },
7440 { Bad_Opcode },
7441 /* c8 */
7442 { Bad_Opcode },
7443 { Bad_Opcode },
7444 { Bad_Opcode },
7445 { Bad_Opcode },
7446 { Bad_Opcode },
7447 { Bad_Opcode },
7448 { Bad_Opcode },
7449 { Bad_Opcode },
7450 /* d0 */
7451 { PREFIX_TABLE (PREFIX_VEX_D0) },
7452 { PREFIX_TABLE (PREFIX_VEX_D1) },
7453 { PREFIX_TABLE (PREFIX_VEX_D2) },
7454 { PREFIX_TABLE (PREFIX_VEX_D3) },
7455 { PREFIX_TABLE (PREFIX_VEX_D4) },
7456 { PREFIX_TABLE (PREFIX_VEX_D5) },
7457 { PREFIX_TABLE (PREFIX_VEX_D6) },
7458 { PREFIX_TABLE (PREFIX_VEX_D7) },
7459 /* d8 */
7460 { PREFIX_TABLE (PREFIX_VEX_D8) },
7461 { PREFIX_TABLE (PREFIX_VEX_D9) },
7462 { PREFIX_TABLE (PREFIX_VEX_DA) },
7463 { PREFIX_TABLE (PREFIX_VEX_DB) },
7464 { PREFIX_TABLE (PREFIX_VEX_DC) },
7465 { PREFIX_TABLE (PREFIX_VEX_DD) },
7466 { PREFIX_TABLE (PREFIX_VEX_DE) },
7467 { PREFIX_TABLE (PREFIX_VEX_DF) },
7468 /* e0 */
7469 { PREFIX_TABLE (PREFIX_VEX_E0) },
7470 { PREFIX_TABLE (PREFIX_VEX_E1) },
7471 { PREFIX_TABLE (PREFIX_VEX_E2) },
7472 { PREFIX_TABLE (PREFIX_VEX_E3) },
7473 { PREFIX_TABLE (PREFIX_VEX_E4) },
7474 { PREFIX_TABLE (PREFIX_VEX_E5) },
7475 { PREFIX_TABLE (PREFIX_VEX_E6) },
7476 { PREFIX_TABLE (PREFIX_VEX_E7) },
7477 /* e8 */
7478 { PREFIX_TABLE (PREFIX_VEX_E8) },
7479 { PREFIX_TABLE (PREFIX_VEX_E9) },
7480 { PREFIX_TABLE (PREFIX_VEX_EA) },
7481 { PREFIX_TABLE (PREFIX_VEX_EB) },
7482 { PREFIX_TABLE (PREFIX_VEX_EC) },
7483 { PREFIX_TABLE (PREFIX_VEX_ED) },
7484 { PREFIX_TABLE (PREFIX_VEX_EE) },
7485 { PREFIX_TABLE (PREFIX_VEX_EF) },
7486 /* f0 */
7487 { PREFIX_TABLE (PREFIX_VEX_F0) },
7488 { PREFIX_TABLE (PREFIX_VEX_F1) },
7489 { PREFIX_TABLE (PREFIX_VEX_F2) },
7490 { PREFIX_TABLE (PREFIX_VEX_F3) },
7491 { PREFIX_TABLE (PREFIX_VEX_F4) },
7492 { PREFIX_TABLE (PREFIX_VEX_F5) },
7493 { PREFIX_TABLE (PREFIX_VEX_F6) },
7494 { PREFIX_TABLE (PREFIX_VEX_F7) },
7495 /* f8 */
7496 { PREFIX_TABLE (PREFIX_VEX_F8) },
7497 { PREFIX_TABLE (PREFIX_VEX_F9) },
7498 { PREFIX_TABLE (PREFIX_VEX_FA) },
7499 { PREFIX_TABLE (PREFIX_VEX_FB) },
7500 { PREFIX_TABLE (PREFIX_VEX_FC) },
7501 { PREFIX_TABLE (PREFIX_VEX_FD) },
7502 { PREFIX_TABLE (PREFIX_VEX_FE) },
7503 { Bad_Opcode },
7505 /* VEX_0F38 */
7507 /* 00 */
7508 { PREFIX_TABLE (PREFIX_VEX_3800) },
7509 { PREFIX_TABLE (PREFIX_VEX_3801) },
7510 { PREFIX_TABLE (PREFIX_VEX_3802) },
7511 { PREFIX_TABLE (PREFIX_VEX_3803) },
7512 { PREFIX_TABLE (PREFIX_VEX_3804) },
7513 { PREFIX_TABLE (PREFIX_VEX_3805) },
7514 { PREFIX_TABLE (PREFIX_VEX_3806) },
7515 { PREFIX_TABLE (PREFIX_VEX_3807) },
7516 /* 08 */
7517 { PREFIX_TABLE (PREFIX_VEX_3808) },
7518 { PREFIX_TABLE (PREFIX_VEX_3809) },
7519 { PREFIX_TABLE (PREFIX_VEX_380A) },
7520 { PREFIX_TABLE (PREFIX_VEX_380B) },
7521 { PREFIX_TABLE (PREFIX_VEX_380C) },
7522 { PREFIX_TABLE (PREFIX_VEX_380D) },
7523 { PREFIX_TABLE (PREFIX_VEX_380E) },
7524 { PREFIX_TABLE (PREFIX_VEX_380F) },
7525 /* 10 */
7526 { Bad_Opcode },
7527 { Bad_Opcode },
7528 { Bad_Opcode },
7529 { Bad_Opcode },
7530 { Bad_Opcode },
7531 { Bad_Opcode },
7532 { Bad_Opcode },
7533 { PREFIX_TABLE (PREFIX_VEX_3817) },
7534 /* 18 */
7535 { PREFIX_TABLE (PREFIX_VEX_3818) },
7536 { PREFIX_TABLE (PREFIX_VEX_3819) },
7537 { PREFIX_TABLE (PREFIX_VEX_381A) },
7538 { Bad_Opcode },
7539 { PREFIX_TABLE (PREFIX_VEX_381C) },
7540 { PREFIX_TABLE (PREFIX_VEX_381D) },
7541 { PREFIX_TABLE (PREFIX_VEX_381E) },
7542 { Bad_Opcode },
7543 /* 20 */
7544 { PREFIX_TABLE (PREFIX_VEX_3820) },
7545 { PREFIX_TABLE (PREFIX_VEX_3821) },
7546 { PREFIX_TABLE (PREFIX_VEX_3822) },
7547 { PREFIX_TABLE (PREFIX_VEX_3823) },
7548 { PREFIX_TABLE (PREFIX_VEX_3824) },
7549 { PREFIX_TABLE (PREFIX_VEX_3825) },
7550 { Bad_Opcode },
7551 { Bad_Opcode },
7552 /* 28 */
7553 { PREFIX_TABLE (PREFIX_VEX_3828) },
7554 { PREFIX_TABLE (PREFIX_VEX_3829) },
7555 { PREFIX_TABLE (PREFIX_VEX_382A) },
7556 { PREFIX_TABLE (PREFIX_VEX_382B) },
7557 { PREFIX_TABLE (PREFIX_VEX_382C) },
7558 { PREFIX_TABLE (PREFIX_VEX_382D) },
7559 { PREFIX_TABLE (PREFIX_VEX_382E) },
7560 { PREFIX_TABLE (PREFIX_VEX_382F) },
7561 /* 30 */
7562 { PREFIX_TABLE (PREFIX_VEX_3830) },
7563 { PREFIX_TABLE (PREFIX_VEX_3831) },
7564 { PREFIX_TABLE (PREFIX_VEX_3832) },
7565 { PREFIX_TABLE (PREFIX_VEX_3833) },
7566 { PREFIX_TABLE (PREFIX_VEX_3834) },
7567 { PREFIX_TABLE (PREFIX_VEX_3835) },
7568 { Bad_Opcode },
7569 { PREFIX_TABLE (PREFIX_VEX_3837) },
7570 /* 38 */
7571 { PREFIX_TABLE (PREFIX_VEX_3838) },
7572 { PREFIX_TABLE (PREFIX_VEX_3839) },
7573 { PREFIX_TABLE (PREFIX_VEX_383A) },
7574 { PREFIX_TABLE (PREFIX_VEX_383B) },
7575 { PREFIX_TABLE (PREFIX_VEX_383C) },
7576 { PREFIX_TABLE (PREFIX_VEX_383D) },
7577 { PREFIX_TABLE (PREFIX_VEX_383E) },
7578 { PREFIX_TABLE (PREFIX_VEX_383F) },
7579 /* 40 */
7580 { PREFIX_TABLE (PREFIX_VEX_3840) },
7581 { PREFIX_TABLE (PREFIX_VEX_3841) },
7582 { Bad_Opcode },
7583 { Bad_Opcode },
7584 { Bad_Opcode },
7585 { Bad_Opcode },
7586 { Bad_Opcode },
7587 { Bad_Opcode },
7588 /* 48 */
7589 { Bad_Opcode },
7590 { Bad_Opcode },
7591 { Bad_Opcode },
7592 { Bad_Opcode },
7593 { Bad_Opcode },
7594 { Bad_Opcode },
7595 { Bad_Opcode },
7596 { Bad_Opcode },
7597 /* 50 */
7598 { Bad_Opcode },
7599 { Bad_Opcode },
7600 { Bad_Opcode },
7601 { Bad_Opcode },
7602 { Bad_Opcode },
7603 { Bad_Opcode },
7604 { Bad_Opcode },
7605 { Bad_Opcode },
7606 /* 58 */
7607 { Bad_Opcode },
7608 { Bad_Opcode },
7609 { Bad_Opcode },
7610 { Bad_Opcode },
7611 { Bad_Opcode },
7612 { Bad_Opcode },
7613 { Bad_Opcode },
7614 { Bad_Opcode },
7615 /* 60 */
7616 { Bad_Opcode },
7617 { Bad_Opcode },
7618 { Bad_Opcode },
7619 { Bad_Opcode },
7620 { Bad_Opcode },
7621 { Bad_Opcode },
7622 { Bad_Opcode },
7623 { Bad_Opcode },
7624 /* 68 */
7625 { Bad_Opcode },
7626 { Bad_Opcode },
7627 { Bad_Opcode },
7628 { Bad_Opcode },
7629 { Bad_Opcode },
7630 { Bad_Opcode },
7631 { Bad_Opcode },
7632 { Bad_Opcode },
7633 /* 70 */
7634 { Bad_Opcode },
7635 { Bad_Opcode },
7636 { Bad_Opcode },
7637 { Bad_Opcode },
7638 { Bad_Opcode },
7639 { Bad_Opcode },
7640 { Bad_Opcode },
7641 { Bad_Opcode },
7642 /* 78 */
7643 { Bad_Opcode },
7644 { Bad_Opcode },
7645 { Bad_Opcode },
7646 { Bad_Opcode },
7647 { Bad_Opcode },
7648 { Bad_Opcode },
7649 { Bad_Opcode },
7650 { Bad_Opcode },
7651 /* 80 */
7652 { Bad_Opcode },
7653 { Bad_Opcode },
7654 { Bad_Opcode },
7655 { Bad_Opcode },
7656 { Bad_Opcode },
7657 { Bad_Opcode },
7658 { Bad_Opcode },
7659 { Bad_Opcode },
7660 /* 88 */
7661 { Bad_Opcode },
7662 { Bad_Opcode },
7663 { Bad_Opcode },
7664 { Bad_Opcode },
7665 { Bad_Opcode },
7666 { Bad_Opcode },
7667 { Bad_Opcode },
7668 { Bad_Opcode },
7669 /* 90 */
7670 { Bad_Opcode },
7671 { Bad_Opcode },
7672 { Bad_Opcode },
7673 { Bad_Opcode },
7674 { Bad_Opcode },
7675 { Bad_Opcode },
7676 { PREFIX_TABLE (PREFIX_VEX_3896) },
7677 { PREFIX_TABLE (PREFIX_VEX_3897) },
7678 /* 98 */
7679 { PREFIX_TABLE (PREFIX_VEX_3898) },
7680 { PREFIX_TABLE (PREFIX_VEX_3899) },
7681 { PREFIX_TABLE (PREFIX_VEX_389A) },
7682 { PREFIX_TABLE (PREFIX_VEX_389B) },
7683 { PREFIX_TABLE (PREFIX_VEX_389C) },
7684 { PREFIX_TABLE (PREFIX_VEX_389D) },
7685 { PREFIX_TABLE (PREFIX_VEX_389E) },
7686 { PREFIX_TABLE (PREFIX_VEX_389F) },
7687 /* a0 */
7688 { Bad_Opcode },
7689 { Bad_Opcode },
7690 { Bad_Opcode },
7691 { Bad_Opcode },
7692 { Bad_Opcode },
7693 { Bad_Opcode },
7694 { PREFIX_TABLE (PREFIX_VEX_38A6) },
7695 { PREFIX_TABLE (PREFIX_VEX_38A7) },
7696 /* a8 */
7697 { PREFIX_TABLE (PREFIX_VEX_38A8) },
7698 { PREFIX_TABLE (PREFIX_VEX_38A9) },
7699 { PREFIX_TABLE (PREFIX_VEX_38AA) },
7700 { PREFIX_TABLE (PREFIX_VEX_38AB) },
7701 { PREFIX_TABLE (PREFIX_VEX_38AC) },
7702 { PREFIX_TABLE (PREFIX_VEX_38AD) },
7703 { PREFIX_TABLE (PREFIX_VEX_38AE) },
7704 { PREFIX_TABLE (PREFIX_VEX_38AF) },
7705 /* b0 */
7706 { Bad_Opcode },
7707 { Bad_Opcode },
7708 { Bad_Opcode },
7709 { Bad_Opcode },
7710 { Bad_Opcode },
7711 { Bad_Opcode },
7712 { PREFIX_TABLE (PREFIX_VEX_38B6) },
7713 { PREFIX_TABLE (PREFIX_VEX_38B7) },
7714 /* b8 */
7715 { PREFIX_TABLE (PREFIX_VEX_38B8) },
7716 { PREFIX_TABLE (PREFIX_VEX_38B9) },
7717 { PREFIX_TABLE (PREFIX_VEX_38BA) },
7718 { PREFIX_TABLE (PREFIX_VEX_38BB) },
7719 { PREFIX_TABLE (PREFIX_VEX_38BC) },
7720 { PREFIX_TABLE (PREFIX_VEX_38BD) },
7721 { PREFIX_TABLE (PREFIX_VEX_38BE) },
7722 { PREFIX_TABLE (PREFIX_VEX_38BF) },
7723 /* c0 */
7724 { Bad_Opcode },
7725 { Bad_Opcode },
7726 { Bad_Opcode },
7727 { Bad_Opcode },
7728 { Bad_Opcode },
7729 { Bad_Opcode },
7730 { Bad_Opcode },
7731 { Bad_Opcode },
7732 /* c8 */
7733 { Bad_Opcode },
7734 { Bad_Opcode },
7735 { Bad_Opcode },
7736 { Bad_Opcode },
7737 { Bad_Opcode },
7738 { Bad_Opcode },
7739 { Bad_Opcode },
7740 { Bad_Opcode },
7741 /* d0 */
7742 { Bad_Opcode },
7743 { Bad_Opcode },
7744 { Bad_Opcode },
7745 { Bad_Opcode },
7746 { Bad_Opcode },
7747 { Bad_Opcode },
7748 { Bad_Opcode },
7749 { Bad_Opcode },
7750 /* d8 */
7751 { Bad_Opcode },
7752 { Bad_Opcode },
7753 { Bad_Opcode },
7754 { PREFIX_TABLE (PREFIX_VEX_38DB) },
7755 { PREFIX_TABLE (PREFIX_VEX_38DC) },
7756 { PREFIX_TABLE (PREFIX_VEX_38DD) },
7757 { PREFIX_TABLE (PREFIX_VEX_38DE) },
7758 { PREFIX_TABLE (PREFIX_VEX_38DF) },
7759 /* e0 */
7760 { Bad_Opcode },
7761 { Bad_Opcode },
7762 { Bad_Opcode },
7763 { Bad_Opcode },
7764 { Bad_Opcode },
7765 { Bad_Opcode },
7766 { Bad_Opcode },
7767 { Bad_Opcode },
7768 /* e8 */
7769 { Bad_Opcode },
7770 { Bad_Opcode },
7771 { Bad_Opcode },
7772 { Bad_Opcode },
7773 { Bad_Opcode },
7774 { Bad_Opcode },
7775 { Bad_Opcode },
7776 { Bad_Opcode },
7777 /* f0 */
7778 { Bad_Opcode },
7779 { Bad_Opcode },
7780 { Bad_Opcode },
7781 { Bad_Opcode },
7782 { Bad_Opcode },
7783 { Bad_Opcode },
7784 { Bad_Opcode },
7785 { Bad_Opcode },
7786 /* f8 */
7787 { Bad_Opcode },
7788 { Bad_Opcode },
7789 { Bad_Opcode },
7790 { Bad_Opcode },
7791 { Bad_Opcode },
7792 { Bad_Opcode },
7793 { Bad_Opcode },
7794 { Bad_Opcode },
7796 /* VEX_0F3A */
7798 /* 00 */
7799 { Bad_Opcode },
7800 { Bad_Opcode },
7801 { Bad_Opcode },
7802 { Bad_Opcode },
7803 { PREFIX_TABLE (PREFIX_VEX_3A04) },
7804 { PREFIX_TABLE (PREFIX_VEX_3A05) },
7805 { PREFIX_TABLE (PREFIX_VEX_3A06) },
7806 { Bad_Opcode },
7807 /* 08 */
7808 { PREFIX_TABLE (PREFIX_VEX_3A08) },
7809 { PREFIX_TABLE (PREFIX_VEX_3A09) },
7810 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7811 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7812 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7813 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7814 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7815 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7816 /* 10 */
7817 { Bad_Opcode },
7818 { Bad_Opcode },
7819 { Bad_Opcode },
7820 { Bad_Opcode },
7821 { PREFIX_TABLE (PREFIX_VEX_3A14) },
7822 { PREFIX_TABLE (PREFIX_VEX_3A15) },
7823 { PREFIX_TABLE (PREFIX_VEX_3A16) },
7824 { PREFIX_TABLE (PREFIX_VEX_3A17) },
7825 /* 18 */
7826 { PREFIX_TABLE (PREFIX_VEX_3A18) },
7827 { PREFIX_TABLE (PREFIX_VEX_3A19) },
7828 { Bad_Opcode },
7829 { Bad_Opcode },
7830 { Bad_Opcode },
7831 { Bad_Opcode },
7832 { Bad_Opcode },
7833 { Bad_Opcode },
7834 /* 20 */
7835 { PREFIX_TABLE (PREFIX_VEX_3A20) },
7836 { PREFIX_TABLE (PREFIX_VEX_3A21) },
7837 { PREFIX_TABLE (PREFIX_VEX_3A22) },
7838 { Bad_Opcode },
7839 { Bad_Opcode },
7840 { Bad_Opcode },
7841 { Bad_Opcode },
7842 { Bad_Opcode },
7843 /* 28 */
7844 { Bad_Opcode },
7845 { Bad_Opcode },
7846 { Bad_Opcode },
7847 { Bad_Opcode },
7848 { Bad_Opcode },
7849 { Bad_Opcode },
7850 { Bad_Opcode },
7851 { Bad_Opcode },
7852 /* 30 */
7853 { Bad_Opcode },
7854 { Bad_Opcode },
7855 { Bad_Opcode },
7856 { Bad_Opcode },
7857 { Bad_Opcode },
7858 { Bad_Opcode },
7859 { Bad_Opcode },
7860 { Bad_Opcode },
7861 /* 38 */
7862 { Bad_Opcode },
7863 { Bad_Opcode },
7864 { Bad_Opcode },
7865 { Bad_Opcode },
7866 { Bad_Opcode },
7867 { Bad_Opcode },
7868 { Bad_Opcode },
7869 { Bad_Opcode },
7870 /* 40 */
7871 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7872 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7873 { PREFIX_TABLE (PREFIX_VEX_3A42) },
7874 { Bad_Opcode },
7875 { PREFIX_TABLE (PREFIX_VEX_3A44) },
7876 { Bad_Opcode },
7877 { Bad_Opcode },
7878 { Bad_Opcode },
7879 /* 48 */
7880 { PREFIX_TABLE (PREFIX_VEX_3A48) },
7881 { PREFIX_TABLE (PREFIX_VEX_3A49) },
7882 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7883 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7884 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7885 { Bad_Opcode },
7886 { Bad_Opcode },
7887 { Bad_Opcode },
7888 /* 50 */
7889 { Bad_Opcode },
7890 { Bad_Opcode },
7891 { Bad_Opcode },
7892 { Bad_Opcode },
7893 { Bad_Opcode },
7894 { Bad_Opcode },
7895 { Bad_Opcode },
7896 { Bad_Opcode },
7897 /* 58 */
7898 { Bad_Opcode },
7899 { Bad_Opcode },
7900 { Bad_Opcode },
7901 { Bad_Opcode },
7902 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7903 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7904 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7905 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7906 /* 60 */
7907 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7908 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7909 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7910 { PREFIX_TABLE (PREFIX_VEX_3A63) },
7911 { Bad_Opcode },
7912 { Bad_Opcode },
7913 { Bad_Opcode },
7914 { Bad_Opcode },
7915 /* 68 */
7916 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7917 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7918 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7919 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7920 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7921 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7922 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7923 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7924 /* 70 */
7925 { Bad_Opcode },
7926 { Bad_Opcode },
7927 { Bad_Opcode },
7928 { Bad_Opcode },
7929 { Bad_Opcode },
7930 { Bad_Opcode },
7931 { Bad_Opcode },
7932 { Bad_Opcode },
7933 /* 78 */
7934 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7935 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7936 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7937 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7938 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7939 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7940 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7941 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7942 /* 80 */
7943 { Bad_Opcode },
7944 { Bad_Opcode },
7945 { Bad_Opcode },
7946 { Bad_Opcode },
7947 { Bad_Opcode },
7948 { Bad_Opcode },
7949 { Bad_Opcode },
7950 { Bad_Opcode },
7951 /* 88 */
7952 { Bad_Opcode },
7953 { Bad_Opcode },
7954 { Bad_Opcode },
7955 { Bad_Opcode },
7956 { Bad_Opcode },
7957 { Bad_Opcode },
7958 { Bad_Opcode },
7959 { Bad_Opcode },
7960 /* 90 */
7961 { Bad_Opcode },
7962 { Bad_Opcode },
7963 { Bad_Opcode },
7964 { Bad_Opcode },
7965 { Bad_Opcode },
7966 { Bad_Opcode },
7967 { Bad_Opcode },
7968 { Bad_Opcode },
7969 /* 98 */
7970 { Bad_Opcode },
7971 { Bad_Opcode },
7972 { Bad_Opcode },
7973 { Bad_Opcode },
7974 { Bad_Opcode },
7975 { Bad_Opcode },
7976 { Bad_Opcode },
7977 { Bad_Opcode },
7978 /* a0 */
7979 { Bad_Opcode },
7980 { Bad_Opcode },
7981 { Bad_Opcode },
7982 { Bad_Opcode },
7983 { Bad_Opcode },
7984 { Bad_Opcode },
7985 { Bad_Opcode },
7986 { Bad_Opcode },
7987 /* a8 */
7988 { Bad_Opcode },
7989 { Bad_Opcode },
7990 { Bad_Opcode },
7991 { Bad_Opcode },
7992 { Bad_Opcode },
7993 { Bad_Opcode },
7994 { Bad_Opcode },
7995 { Bad_Opcode },
7996 /* b0 */
7997 { Bad_Opcode },
7998 { Bad_Opcode },
7999 { Bad_Opcode },
8000 { Bad_Opcode },
8001 { Bad_Opcode },
8002 { Bad_Opcode },
8003 { Bad_Opcode },
8004 { Bad_Opcode },
8005 /* b8 */
8006 { Bad_Opcode },
8007 { Bad_Opcode },
8008 { Bad_Opcode },
8009 { Bad_Opcode },
8010 { Bad_Opcode },
8011 { Bad_Opcode },
8012 { Bad_Opcode },
8013 { Bad_Opcode },
8014 /* c0 */
8015 { Bad_Opcode },
8016 { Bad_Opcode },
8017 { Bad_Opcode },
8018 { Bad_Opcode },
8019 { Bad_Opcode },
8020 { Bad_Opcode },
8021 { Bad_Opcode },
8022 { Bad_Opcode },
8023 /* c8 */
8024 { Bad_Opcode },
8025 { Bad_Opcode },
8026 { Bad_Opcode },
8027 { Bad_Opcode },
8028 { Bad_Opcode },
8029 { Bad_Opcode },
8030 { Bad_Opcode },
8031 { Bad_Opcode },
8032 /* d0 */
8033 { Bad_Opcode },
8034 { Bad_Opcode },
8035 { Bad_Opcode },
8036 { Bad_Opcode },
8037 { Bad_Opcode },
8038 { Bad_Opcode },
8039 { Bad_Opcode },
8040 { Bad_Opcode },
8041 /* d8 */
8042 { Bad_Opcode },
8043 { Bad_Opcode },
8044 { Bad_Opcode },
8045 { Bad_Opcode },
8046 { Bad_Opcode },
8047 { Bad_Opcode },
8048 { Bad_Opcode },
8049 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8050 /* e0 */
8051 { Bad_Opcode },
8052 { Bad_Opcode },
8053 { Bad_Opcode },
8054 { Bad_Opcode },
8055 { Bad_Opcode },
8056 { Bad_Opcode },
8057 { Bad_Opcode },
8058 { Bad_Opcode },
8059 /* e8 */
8060 { Bad_Opcode },
8061 { Bad_Opcode },
8062 { Bad_Opcode },
8063 { Bad_Opcode },
8064 { Bad_Opcode },
8065 { Bad_Opcode },
8066 { Bad_Opcode },
8067 { Bad_Opcode },
8068 /* f0 */
8069 { Bad_Opcode },
8070 { Bad_Opcode },
8071 { Bad_Opcode },
8072 { Bad_Opcode },
8073 { Bad_Opcode },
8074 { Bad_Opcode },
8075 { Bad_Opcode },
8076 { Bad_Opcode },
8077 /* f8 */
8078 { Bad_Opcode },
8079 { Bad_Opcode },
8080 { Bad_Opcode },
8081 { Bad_Opcode },
8082 { Bad_Opcode },
8083 { Bad_Opcode },
8084 { Bad_Opcode },
8085 { Bad_Opcode },
8089 static const struct dis386 vex_len_table[][2] = {
8090 /* VEX_LEN_10_P_1 */
8092 { VEX_W_TABLE (VEX_W_10_P_1) },
8093 { VEX_W_TABLE (VEX_W_10_P_1) },
8096 /* VEX_LEN_10_P_3 */
8098 { VEX_W_TABLE (VEX_W_10_P_3) },
8099 { VEX_W_TABLE (VEX_W_10_P_3) },
8102 /* VEX_LEN_11_P_1 */
8104 { VEX_W_TABLE (VEX_W_11_P_1) },
8105 { VEX_W_TABLE (VEX_W_11_P_1) },
8108 /* VEX_LEN_11_P_3 */
8110 { VEX_W_TABLE (VEX_W_11_P_3) },
8111 { VEX_W_TABLE (VEX_W_11_P_3) },
8114 /* VEX_LEN_12_P_0_M_0 */
8116 { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8119 /* VEX_LEN_12_P_0_M_1 */
8121 { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8124 /* VEX_LEN_12_P_2 */
8126 { VEX_W_TABLE (VEX_W_12_P_2) },
8129 /* VEX_LEN_13_M_0 */
8131 { VEX_W_TABLE (VEX_W_13_M_0) },
8134 /* VEX_LEN_16_P_0_M_0 */
8136 { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8139 /* VEX_LEN_16_P_0_M_1 */
8141 { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8144 /* VEX_LEN_16_P_2 */
8146 { VEX_W_TABLE (VEX_W_16_P_2) },
8149 /* VEX_LEN_17_M_0 */
8151 { VEX_W_TABLE (VEX_W_17_M_0) },
8154 /* VEX_LEN_2A_P_1 */
8156 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8157 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8160 /* VEX_LEN_2A_P_3 */
8162 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8163 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8166 /* VEX_LEN_2C_P_1 */
8168 { "vcvttss2siY", { Gv, EXdScalar } },
8169 { "vcvttss2siY", { Gv, EXdScalar } },
8172 /* VEX_LEN_2C_P_3 */
8174 { "vcvttsd2siY", { Gv, EXqScalar } },
8175 { "vcvttsd2siY", { Gv, EXqScalar } },
8178 /* VEX_LEN_2D_P_1 */
8180 { "vcvtss2siY", { Gv, EXdScalar } },
8181 { "vcvtss2siY", { Gv, EXdScalar } },
8184 /* VEX_LEN_2D_P_3 */
8186 { "vcvtsd2siY", { Gv, EXqScalar } },
8187 { "vcvtsd2siY", { Gv, EXqScalar } },
8190 /* VEX_LEN_2E_P_0 */
8192 { VEX_W_TABLE (VEX_W_2E_P_0) },
8193 { VEX_W_TABLE (VEX_W_2E_P_0) },
8196 /* VEX_LEN_2E_P_2 */
8198 { VEX_W_TABLE (VEX_W_2E_P_2) },
8199 { VEX_W_TABLE (VEX_W_2E_P_2) },
8202 /* VEX_LEN_2F_P_0 */
8204 { VEX_W_TABLE (VEX_W_2F_P_0) },
8205 { VEX_W_TABLE (VEX_W_2F_P_0) },
8208 /* VEX_LEN_2F_P_2 */
8210 { VEX_W_TABLE (VEX_W_2F_P_2) },
8211 { VEX_W_TABLE (VEX_W_2F_P_2) },
8214 /* VEX_LEN_51_P_1 */
8216 { VEX_W_TABLE (VEX_W_51_P_1) },
8217 { VEX_W_TABLE (VEX_W_51_P_1) },
8220 /* VEX_LEN_51_P_3 */
8222 { VEX_W_TABLE (VEX_W_51_P_3) },
8223 { VEX_W_TABLE (VEX_W_51_P_3) },
8226 /* VEX_LEN_52_P_1 */
8228 { VEX_W_TABLE (VEX_W_52_P_1) },
8229 { VEX_W_TABLE (VEX_W_52_P_1) },
8232 /* VEX_LEN_53_P_1 */
8234 { VEX_W_TABLE (VEX_W_53_P_1) },
8235 { VEX_W_TABLE (VEX_W_53_P_1) },
8238 /* VEX_LEN_58_P_1 */
8240 { VEX_W_TABLE (VEX_W_58_P_1) },
8241 { VEX_W_TABLE (VEX_W_58_P_1) },
8244 /* VEX_LEN_58_P_3 */
8246 { VEX_W_TABLE (VEX_W_58_P_3) },
8247 { VEX_W_TABLE (VEX_W_58_P_3) },
8250 /* VEX_LEN_59_P_1 */
8252 { VEX_W_TABLE (VEX_W_59_P_1) },
8253 { VEX_W_TABLE (VEX_W_59_P_1) },
8256 /* VEX_LEN_59_P_3 */
8258 { VEX_W_TABLE (VEX_W_59_P_3) },
8259 { VEX_W_TABLE (VEX_W_59_P_3) },
8262 /* VEX_LEN_5A_P_1 */
8264 { VEX_W_TABLE (VEX_W_5A_P_1) },
8265 { VEX_W_TABLE (VEX_W_5A_P_1) },
8268 /* VEX_LEN_5A_P_3 */
8270 { VEX_W_TABLE (VEX_W_5A_P_3) },
8271 { VEX_W_TABLE (VEX_W_5A_P_3) },
8274 /* VEX_LEN_5C_P_1 */
8276 { VEX_W_TABLE (VEX_W_5C_P_1) },
8277 { VEX_W_TABLE (VEX_W_5C_P_1) },
8280 /* VEX_LEN_5C_P_3 */
8282 { VEX_W_TABLE (VEX_W_5C_P_3) },
8283 { VEX_W_TABLE (VEX_W_5C_P_3) },
8286 /* VEX_LEN_5D_P_1 */
8288 { VEX_W_TABLE (VEX_W_5D_P_1) },
8289 { VEX_W_TABLE (VEX_W_5D_P_1) },
8292 /* VEX_LEN_5D_P_3 */
8294 { VEX_W_TABLE (VEX_W_5D_P_3) },
8295 { VEX_W_TABLE (VEX_W_5D_P_3) },
8298 /* VEX_LEN_5E_P_1 */
8300 { VEX_W_TABLE (VEX_W_5E_P_1) },
8301 { VEX_W_TABLE (VEX_W_5E_P_1) },
8304 /* VEX_LEN_5E_P_3 */
8306 { VEX_W_TABLE (VEX_W_5E_P_3) },
8307 { VEX_W_TABLE (VEX_W_5E_P_3) },
8310 /* VEX_LEN_5F_P_1 */
8312 { VEX_W_TABLE (VEX_W_5F_P_1) },
8313 { VEX_W_TABLE (VEX_W_5F_P_1) },
8316 /* VEX_LEN_5F_P_3 */
8318 { VEX_W_TABLE (VEX_W_5F_P_3) },
8319 { VEX_W_TABLE (VEX_W_5F_P_3) },
8322 /* VEX_LEN_60_P_2 */
8324 { VEX_W_TABLE (VEX_W_60_P_2) },
8327 /* VEX_LEN_61_P_2 */
8329 { VEX_W_TABLE (VEX_W_61_P_2) },
8332 /* VEX_LEN_62_P_2 */
8334 { VEX_W_TABLE (VEX_W_62_P_2) },
8337 /* VEX_LEN_63_P_2 */
8339 { VEX_W_TABLE (VEX_W_63_P_2) },
8342 /* VEX_LEN_64_P_2 */
8344 { VEX_W_TABLE (VEX_W_64_P_2) },
8347 /* VEX_LEN_65_P_2 */
8349 { VEX_W_TABLE (VEX_W_65_P_2) },
8352 /* VEX_LEN_66_P_2 */
8354 { VEX_W_TABLE (VEX_W_66_P_2) },
8357 /* VEX_LEN_67_P_2 */
8359 { VEX_W_TABLE (VEX_W_67_P_2) },
8362 /* VEX_LEN_68_P_2 */
8364 { VEX_W_TABLE (VEX_W_68_P_2) },
8367 /* VEX_LEN_69_P_2 */
8369 { VEX_W_TABLE (VEX_W_69_P_2) },
8372 /* VEX_LEN_6A_P_2 */
8374 { VEX_W_TABLE (VEX_W_6A_P_2) },
8377 /* VEX_LEN_6B_P_2 */
8379 { VEX_W_TABLE (VEX_W_6B_P_2) },
8382 /* VEX_LEN_6C_P_2 */
8384 { VEX_W_TABLE (VEX_W_6C_P_2) },
8387 /* VEX_LEN_6D_P_2 */
8389 { VEX_W_TABLE (VEX_W_6D_P_2) },
8392 /* VEX_LEN_6E_P_2 */
8394 { "vmovK", { XMScalar, Edq } },
8395 { "vmovK", { XMScalar, Edq } },
8398 /* VEX_LEN_70_P_1 */
8400 { VEX_W_TABLE (VEX_W_70_P_1) },
8403 /* VEX_LEN_70_P_2 */
8405 { VEX_W_TABLE (VEX_W_70_P_2) },
8408 /* VEX_LEN_70_P_3 */
8410 { VEX_W_TABLE (VEX_W_70_P_3) },
8413 /* VEX_LEN_71_R_2_P_2 */
8415 { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8418 /* VEX_LEN_71_R_4_P_2 */
8420 { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8423 /* VEX_LEN_71_R_6_P_2 */
8425 { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8428 /* VEX_LEN_72_R_2_P_2 */
8430 { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8433 /* VEX_LEN_72_R_4_P_2 */
8435 { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8438 /* VEX_LEN_72_R_6_P_2 */
8440 { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8443 /* VEX_LEN_73_R_2_P_2 */
8445 { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8448 /* VEX_LEN_73_R_3_P_2 */
8450 { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8453 /* VEX_LEN_73_R_6_P_2 */
8455 { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8458 /* VEX_LEN_73_R_7_P_2 */
8460 { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8463 /* VEX_LEN_74_P_2 */
8465 { VEX_W_TABLE (VEX_W_74_P_2) },
8468 /* VEX_LEN_75_P_2 */
8470 { VEX_W_TABLE (VEX_W_75_P_2) },
8473 /* VEX_LEN_76_P_2 */
8475 { VEX_W_TABLE (VEX_W_76_P_2) },
8478 /* VEX_LEN_7E_P_1 */
8480 { VEX_W_TABLE (VEX_W_7E_P_1) },
8481 { VEX_W_TABLE (VEX_W_7E_P_1) },
8484 /* VEX_LEN_7E_P_2 */
8486 { "vmovK", { Edq, XMScalar } },
8487 { "vmovK", { Edq, XMScalar } },
8490 /* VEX_LEN_AE_R_2_M_0 */
8492 { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8495 /* VEX_LEN_AE_R_3_M_0 */
8497 { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8500 /* VEX_LEN_C2_P_1 */
8502 { VEX_W_TABLE (VEX_W_C2_P_1) },
8503 { VEX_W_TABLE (VEX_W_C2_P_1) },
8506 /* VEX_LEN_C2_P_3 */
8508 { VEX_W_TABLE (VEX_W_C2_P_3) },
8509 { VEX_W_TABLE (VEX_W_C2_P_3) },
8512 /* VEX_LEN_C4_P_2 */
8514 { VEX_W_TABLE (VEX_W_C4_P_2) },
8517 /* VEX_LEN_C5_P_2 */
8519 { VEX_W_TABLE (VEX_W_C5_P_2) },
8522 /* VEX_LEN_D1_P_2 */
8524 { VEX_W_TABLE (VEX_W_D1_P_2) },
8527 /* VEX_LEN_D2_P_2 */
8529 { VEX_W_TABLE (VEX_W_D2_P_2) },
8532 /* VEX_LEN_D3_P_2 */
8534 { VEX_W_TABLE (VEX_W_D3_P_2) },
8537 /* VEX_LEN_D4_P_2 */
8539 { VEX_W_TABLE (VEX_W_D4_P_2) },
8542 /* VEX_LEN_D5_P_2 */
8544 { VEX_W_TABLE (VEX_W_D5_P_2) },
8547 /* VEX_LEN_D6_P_2 */
8549 { VEX_W_TABLE (VEX_W_D6_P_2) },
8550 { VEX_W_TABLE (VEX_W_D6_P_2) },
8553 /* VEX_LEN_D7_P_2_M_1 */
8555 { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8558 /* VEX_LEN_D8_P_2 */
8560 { VEX_W_TABLE (VEX_W_D8_P_2) },
8563 /* VEX_LEN_D9_P_2 */
8565 { VEX_W_TABLE (VEX_W_D9_P_2) },
8568 /* VEX_LEN_DA_P_2 */
8570 { VEX_W_TABLE (VEX_W_DA_P_2) },
8573 /* VEX_LEN_DB_P_2 */
8575 { VEX_W_TABLE (VEX_W_DB_P_2) },
8578 /* VEX_LEN_DC_P_2 */
8580 { VEX_W_TABLE (VEX_W_DC_P_2) },
8583 /* VEX_LEN_DD_P_2 */
8585 { VEX_W_TABLE (VEX_W_DD_P_2) },
8588 /* VEX_LEN_DE_P_2 */
8590 { VEX_W_TABLE (VEX_W_DE_P_2) },
8593 /* VEX_LEN_DF_P_2 */
8595 { VEX_W_TABLE (VEX_W_DF_P_2) },
8598 /* VEX_LEN_E0_P_2 */
8600 { VEX_W_TABLE (VEX_W_E0_P_2) },
8603 /* VEX_LEN_E1_P_2 */
8605 { VEX_W_TABLE (VEX_W_E1_P_2) },
8608 /* VEX_LEN_E2_P_2 */
8610 { VEX_W_TABLE (VEX_W_E2_P_2) },
8613 /* VEX_LEN_E3_P_2 */
8615 { VEX_W_TABLE (VEX_W_E3_P_2) },
8618 /* VEX_LEN_E4_P_2 */
8620 { VEX_W_TABLE (VEX_W_E4_P_2) },
8623 /* VEX_LEN_E5_P_2 */
8625 { VEX_W_TABLE (VEX_W_E5_P_2) },
8628 /* VEX_LEN_E8_P_2 */
8630 { VEX_W_TABLE (VEX_W_E8_P_2) },
8633 /* VEX_LEN_E9_P_2 */
8635 { VEX_W_TABLE (VEX_W_E9_P_2) },
8638 /* VEX_LEN_EA_P_2 */
8640 { VEX_W_TABLE (VEX_W_EA_P_2) },
8643 /* VEX_LEN_EB_P_2 */
8645 { VEX_W_TABLE (VEX_W_EB_P_2) },
8648 /* VEX_LEN_EC_P_2 */
8650 { VEX_W_TABLE (VEX_W_EC_P_2) },
8653 /* VEX_LEN_ED_P_2 */
8655 { VEX_W_TABLE (VEX_W_ED_P_2) },
8658 /* VEX_LEN_EE_P_2 */
8660 { VEX_W_TABLE (VEX_W_EE_P_2) },
8663 /* VEX_LEN_EF_P_2 */
8665 { VEX_W_TABLE (VEX_W_EF_P_2) },
8668 /* VEX_LEN_F1_P_2 */
8670 { VEX_W_TABLE (VEX_W_F1_P_2) },
8673 /* VEX_LEN_F2_P_2 */
8675 { VEX_W_TABLE (VEX_W_F2_P_2) },
8678 /* VEX_LEN_F3_P_2 */
8680 { VEX_W_TABLE (VEX_W_F3_P_2) },
8683 /* VEX_LEN_F4_P_2 */
8685 { VEX_W_TABLE (VEX_W_F4_P_2) },
8688 /* VEX_LEN_F5_P_2 */
8690 { VEX_W_TABLE (VEX_W_F5_P_2) },
8693 /* VEX_LEN_F6_P_2 */
8695 { VEX_W_TABLE (VEX_W_F6_P_2) },
8698 /* VEX_LEN_F7_P_2 */
8700 { VEX_W_TABLE (VEX_W_F7_P_2) },
8703 /* VEX_LEN_F8_P_2 */
8705 { VEX_W_TABLE (VEX_W_F8_P_2) },
8708 /* VEX_LEN_F9_P_2 */
8710 { VEX_W_TABLE (VEX_W_F9_P_2) },
8713 /* VEX_LEN_FA_P_2 */
8715 { VEX_W_TABLE (VEX_W_FA_P_2) },
8718 /* VEX_LEN_FB_P_2 */
8720 { VEX_W_TABLE (VEX_W_FB_P_2) },
8723 /* VEX_LEN_FC_P_2 */
8725 { VEX_W_TABLE (VEX_W_FC_P_2) },
8728 /* VEX_LEN_FD_P_2 */
8730 { VEX_W_TABLE (VEX_W_FD_P_2) },
8733 /* VEX_LEN_FE_P_2 */
8735 { VEX_W_TABLE (VEX_W_FE_P_2) },
8738 /* VEX_LEN_3800_P_2 */
8740 { VEX_W_TABLE (VEX_W_3800_P_2) },
8743 /* VEX_LEN_3801_P_2 */
8745 { VEX_W_TABLE (VEX_W_3801_P_2) },
8748 /* VEX_LEN_3802_P_2 */
8750 { VEX_W_TABLE (VEX_W_3802_P_2) },
8753 /* VEX_LEN_3803_P_2 */
8755 { VEX_W_TABLE (VEX_W_3803_P_2) },
8758 /* VEX_LEN_3804_P_2 */
8760 { VEX_W_TABLE (VEX_W_3804_P_2) },
8763 /* VEX_LEN_3805_P_2 */
8765 { VEX_W_TABLE (VEX_W_3805_P_2) },
8768 /* VEX_LEN_3806_P_2 */
8770 { VEX_W_TABLE (VEX_W_3806_P_2) },
8773 /* VEX_LEN_3807_P_2 */
8775 { VEX_W_TABLE (VEX_W_3807_P_2) },
8778 /* VEX_LEN_3808_P_2 */
8780 { VEX_W_TABLE (VEX_W_3808_P_2) },
8783 /* VEX_LEN_3809_P_2 */
8785 { VEX_W_TABLE (VEX_W_3809_P_2) },
8788 /* VEX_LEN_380A_P_2 */
8790 { VEX_W_TABLE (VEX_W_380A_P_2) },
8793 /* VEX_LEN_380B_P_2 */
8795 { VEX_W_TABLE (VEX_W_380B_P_2) },
8798 /* VEX_LEN_3819_P_2_M_0 */
8800 { Bad_Opcode },
8801 { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8804 /* VEX_LEN_381A_P_2_M_0 */
8806 { Bad_Opcode },
8807 { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8810 /* VEX_LEN_381C_P_2 */
8812 { VEX_W_TABLE (VEX_W_381C_P_2) },
8815 /* VEX_LEN_381D_P_2 */
8817 { VEX_W_TABLE (VEX_W_381D_P_2) },
8820 /* VEX_LEN_381E_P_2 */
8822 { VEX_W_TABLE (VEX_W_381E_P_2) },
8825 /* VEX_LEN_3820_P_2 */
8827 { VEX_W_TABLE (VEX_W_3820_P_2) },
8830 /* VEX_LEN_3821_P_2 */
8832 { VEX_W_TABLE (VEX_W_3821_P_2) },
8835 /* VEX_LEN_3822_P_2 */
8837 { VEX_W_TABLE (VEX_W_3822_P_2) },
8840 /* VEX_LEN_3823_P_2 */
8842 { VEX_W_TABLE (VEX_W_3823_P_2) },
8845 /* VEX_LEN_3824_P_2 */
8847 { VEX_W_TABLE (VEX_W_3824_P_2) },
8850 /* VEX_LEN_3825_P_2 */
8852 { VEX_W_TABLE (VEX_W_3825_P_2) },
8855 /* VEX_LEN_3828_P_2 */
8857 { VEX_W_TABLE (VEX_W_3828_P_2) },
8860 /* VEX_LEN_3829_P_2 */
8862 { VEX_W_TABLE (VEX_W_3829_P_2) },
8865 /* VEX_LEN_382A_P_2_M_0 */
8867 { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8870 /* VEX_LEN_382B_P_2 */
8872 { VEX_W_TABLE (VEX_W_382B_P_2) },
8875 /* VEX_LEN_3830_P_2 */
8877 { VEX_W_TABLE (VEX_W_3830_P_2) },
8880 /* VEX_LEN_3831_P_2 */
8882 { VEX_W_TABLE (VEX_W_3831_P_2) },
8885 /* VEX_LEN_3832_P_2 */
8887 { VEX_W_TABLE (VEX_W_3832_P_2) },
8890 /* VEX_LEN_3833_P_2 */
8892 { VEX_W_TABLE (VEX_W_3833_P_2) },
8895 /* VEX_LEN_3834_P_2 */
8897 { VEX_W_TABLE (VEX_W_3834_P_2) },
8900 /* VEX_LEN_3835_P_2 */
8902 { VEX_W_TABLE (VEX_W_3835_P_2) },
8905 /* VEX_LEN_3837_P_2 */
8907 { VEX_W_TABLE (VEX_W_3837_P_2) },
8910 /* VEX_LEN_3838_P_2 */
8912 { VEX_W_TABLE (VEX_W_3838_P_2) },
8915 /* VEX_LEN_3839_P_2 */
8917 { VEX_W_TABLE (VEX_W_3839_P_2) },
8920 /* VEX_LEN_383A_P_2 */
8922 { VEX_W_TABLE (VEX_W_383A_P_2) },
8925 /* VEX_LEN_383B_P_2 */
8927 { VEX_W_TABLE (VEX_W_383B_P_2) },
8930 /* VEX_LEN_383C_P_2 */
8932 { VEX_W_TABLE (VEX_W_383C_P_2) },
8935 /* VEX_LEN_383D_P_2 */
8937 { VEX_W_TABLE (VEX_W_383D_P_2) },
8940 /* VEX_LEN_383E_P_2 */
8942 { VEX_W_TABLE (VEX_W_383E_P_2) },
8945 /* VEX_LEN_383F_P_2 */
8947 { VEX_W_TABLE (VEX_W_383F_P_2) },
8950 /* VEX_LEN_3840_P_2 */
8952 { VEX_W_TABLE (VEX_W_3840_P_2) },
8955 /* VEX_LEN_3841_P_2 */
8957 { VEX_W_TABLE (VEX_W_3841_P_2) },
8960 /* VEX_LEN_38DB_P_2 */
8962 { VEX_W_TABLE (VEX_W_38DB_P_2) },
8965 /* VEX_LEN_38DC_P_2 */
8967 { VEX_W_TABLE (VEX_W_38DC_P_2) },
8970 /* VEX_LEN_38DD_P_2 */
8972 { VEX_W_TABLE (VEX_W_38DD_P_2) },
8975 /* VEX_LEN_38DE_P_2 */
8977 { VEX_W_TABLE (VEX_W_38DE_P_2) },
8980 /* VEX_LEN_38DF_P_2 */
8982 { VEX_W_TABLE (VEX_W_38DF_P_2) },
8985 /* VEX_LEN_3A06_P_2 */
8987 { Bad_Opcode },
8988 { VEX_W_TABLE (VEX_W_3A06_P_2) },
8991 /* VEX_LEN_3A0A_P_2 */
8993 { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8994 { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8997 /* VEX_LEN_3A0B_P_2 */
8999 { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9000 { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9003 /* VEX_LEN_3A0E_P_2 */
9005 { VEX_W_TABLE (VEX_W_3A0E_P_2) },
9008 /* VEX_LEN_3A0F_P_2 */
9010 { VEX_W_TABLE (VEX_W_3A0F_P_2) },
9013 /* VEX_LEN_3A14_P_2 */
9015 { VEX_W_TABLE (VEX_W_3A14_P_2) },
9018 /* VEX_LEN_3A15_P_2 */
9020 { VEX_W_TABLE (VEX_W_3A15_P_2) },
9023 /* VEX_LEN_3A16_P_2 */
9025 { "vpextrK", { Edq, XM, Ib } },
9028 /* VEX_LEN_3A17_P_2 */
9030 { "vextractps", { Edqd, XM, Ib } },
9033 /* VEX_LEN_3A18_P_2 */
9035 { Bad_Opcode },
9036 { VEX_W_TABLE (VEX_W_3A18_P_2) },
9039 /* VEX_LEN_3A19_P_2 */
9041 { Bad_Opcode },
9042 { VEX_W_TABLE (VEX_W_3A19_P_2) },
9045 /* VEX_LEN_3A20_P_2 */
9047 { VEX_W_TABLE (VEX_W_3A20_P_2) },
9050 /* VEX_LEN_3A21_P_2 */
9052 { VEX_W_TABLE (VEX_W_3A21_P_2) },
9055 /* VEX_LEN_3A22_P_2 */
9057 { "vpinsrK", { XM, Vex128, Edq, Ib } },
9060 /* VEX_LEN_3A41_P_2 */
9062 { VEX_W_TABLE (VEX_W_3A41_P_2) },
9065 /* VEX_LEN_3A42_P_2 */
9067 { VEX_W_TABLE (VEX_W_3A42_P_2) },
9070 /* VEX_LEN_3A44_P_2 */
9072 { VEX_W_TABLE (VEX_W_3A44_P_2) },
9075 /* VEX_LEN_3A4C_P_2 */
9077 { VEX_W_TABLE (VEX_W_3A4C_P_2) },
9080 /* VEX_LEN_3A60_P_2 */
9082 { VEX_W_TABLE (VEX_W_3A60_P_2) },
9085 /* VEX_LEN_3A61_P_2 */
9087 { VEX_W_TABLE (VEX_W_3A61_P_2) },
9090 /* VEX_LEN_3A62_P_2 */
9092 { VEX_W_TABLE (VEX_W_3A62_P_2) },
9095 /* VEX_LEN_3A63_P_2 */
9097 { VEX_W_TABLE (VEX_W_3A63_P_2) },
9100 /* VEX_LEN_3A6A_P_2 */
9102 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9105 /* VEX_LEN_3A6B_P_2 */
9107 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9110 /* VEX_LEN_3A6E_P_2 */
9112 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9115 /* VEX_LEN_3A6F_P_2 */
9117 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9120 /* VEX_LEN_3A7A_P_2 */
9122 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9125 /* VEX_LEN_3A7B_P_2 */
9127 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9130 /* VEX_LEN_3A7E_P_2 */
9132 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9135 /* VEX_LEN_3A7F_P_2 */
9137 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9140 /* VEX_LEN_3ADF_P_2 */
9142 { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9145 /* VEX_LEN_XOP_09_80 */
9147 { "vfrczps", { XM, EXxmm } },
9148 { "vfrczps", { XM, EXymmq } },
9151 /* VEX_LEN_XOP_09_81 */
9153 { "vfrczpd", { XM, EXxmm } },
9154 { "vfrczpd", { XM, EXymmq } },
9158 static const struct dis386 vex_w_table[][2] = {
9160 /* VEX_W_10_P_0 */
9161 { "vmovups", { XM, EXx } },
9164 /* VEX_W_10_P_1 */
9165 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
9168 /* VEX_W_10_P_2 */
9169 { "vmovupd", { XM, EXx } },
9172 /* VEX_W_10_P_3 */
9173 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
9176 /* VEX_W_11_P_0 */
9177 { "vmovups", { EXxS, XM } },
9180 /* VEX_W_11_P_1 */
9181 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9184 /* VEX_W_11_P_2 */
9185 { "vmovupd", { EXxS, XM } },
9188 /* VEX_W_11_P_3 */
9189 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9192 /* VEX_W_12_P_0_M_0 */
9193 { "vmovlps", { XM, Vex128, EXq } },
9196 /* VEX_W_12_P_0_M_1 */
9197 { "vmovhlps", { XM, Vex128, EXq } },
9200 /* VEX_W_12_P_1 */
9201 { "vmovsldup", { XM, EXx } },
9204 /* VEX_W_12_P_2 */
9205 { "vmovlpd", { XM, Vex128, EXq } },
9208 /* VEX_W_12_P_3 */
9209 { "vmovddup", { XM, EXymmq } },
9212 /* VEX_W_13_M_0 */
9213 { "vmovlpX", { EXq, XM } },
9216 /* VEX_W_14 */
9217 { "vunpcklpX", { XM, Vex, EXx } },
9220 /* VEX_W_15 */
9221 { "vunpckhpX", { XM, Vex, EXx } },
9224 /* VEX_W_16_P_0_M_0 */
9225 { "vmovhps", { XM, Vex128, EXq } },
9228 /* VEX_W_16_P_0_M_1 */
9229 { "vmovlhps", { XM, Vex128, EXq } },
9232 /* VEX_W_16_P_1 */
9233 { "vmovshdup", { XM, EXx } },
9236 /* VEX_W_16_P_2 */
9237 { "vmovhpd", { XM, Vex128, EXq } },
9240 /* VEX_W_17_M_0 */
9241 { "vmovhpX", { EXq, XM } },
9244 /* VEX_W_28 */
9245 { "vmovapX", { XM, EXx } },
9248 /* VEX_W_29 */
9249 { "vmovapX", { EXxS, XM } },
9252 /* VEX_W_2B_M_0 */
9253 { "vmovntpX", { Mx, XM } },
9256 /* VEX_W_2E_P_0 */
9257 { "vucomiss", { XMScalar, EXdScalar } },
9260 /* VEX_W_2E_P_2 */
9261 { "vucomisd", { XMScalar, EXqScalar } },
9264 /* VEX_W_2F_P_0 */
9265 { "vcomiss", { XMScalar, EXdScalar } },
9268 /* VEX_W_2F_P_2 */
9269 { "vcomisd", { XMScalar, EXqScalar } },
9272 /* VEX_W_50_M_0 */
9273 { "vmovmskpX", { Gdq, XS } },
9276 /* VEX_W_51_P_0 */
9277 { "vsqrtps", { XM, EXx } },
9280 /* VEX_W_51_P_1 */
9281 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
9284 /* VEX_W_51_P_2 */
9285 { "vsqrtpd", { XM, EXx } },
9288 /* VEX_W_51_P_3 */
9289 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
9292 /* VEX_W_52_P_0 */
9293 { "vrsqrtps", { XM, EXx } },
9296 /* VEX_W_52_P_1 */
9297 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
9300 /* VEX_W_53_P_0 */
9301 { "vrcpps", { XM, EXx } },
9304 /* VEX_W_53_P_1 */
9305 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
9308 /* VEX_W_58_P_0 */
9309 { "vaddps", { XM, Vex, EXx } },
9312 /* VEX_W_58_P_1 */
9313 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
9316 /* VEX_W_58_P_2 */
9317 { "vaddpd", { XM, Vex, EXx } },
9320 /* VEX_W_58_P_3 */
9321 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
9324 /* VEX_W_59_P_0 */
9325 { "vmulps", { XM, Vex, EXx } },
9328 /* VEX_W_59_P_1 */
9329 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
9332 /* VEX_W_59_P_2 */
9333 { "vmulpd", { XM, Vex, EXx } },
9336 /* VEX_W_59_P_3 */
9337 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
9340 /* VEX_W_5A_P_0 */
9341 { "vcvtps2pd", { XM, EXxmmq } },
9344 /* VEX_W_5A_P_1 */
9345 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
9348 /* VEX_W_5A_P_3 */
9349 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
9352 /* VEX_W_5B_P_0 */
9353 { "vcvtdq2ps", { XM, EXx } },
9356 /* VEX_W_5B_P_1 */
9357 { "vcvttps2dq", { XM, EXx } },
9360 /* VEX_W_5B_P_2 */
9361 { "vcvtps2dq", { XM, EXx } },
9364 /* VEX_W_5C_P_0 */
9365 { "vsubps", { XM, Vex, EXx } },
9368 /* VEX_W_5C_P_1 */
9369 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
9372 /* VEX_W_5C_P_2 */
9373 { "vsubpd", { XM, Vex, EXx } },
9376 /* VEX_W_5C_P_3 */
9377 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
9380 /* VEX_W_5D_P_0 */
9381 { "vminps", { XM, Vex, EXx } },
9384 /* VEX_W_5D_P_1 */
9385 { "vminss", { XMScalar, VexScalar, EXdScalar } },
9388 /* VEX_W_5D_P_2 */
9389 { "vminpd", { XM, Vex, EXx } },
9392 /* VEX_W_5D_P_3 */
9393 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
9396 /* VEX_W_5E_P_0 */
9397 { "vdivps", { XM, Vex, EXx } },
9400 /* VEX_W_5E_P_1 */
9401 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
9404 /* VEX_W_5E_P_2 */
9405 { "vdivpd", { XM, Vex, EXx } },
9408 /* VEX_W_5E_P_3 */
9409 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
9412 /* VEX_W_5F_P_0 */
9413 { "vmaxps", { XM, Vex, EXx } },
9416 /* VEX_W_5F_P_1 */
9417 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
9420 /* VEX_W_5F_P_2 */
9421 { "vmaxpd", { XM, Vex, EXx } },
9424 /* VEX_W_5F_P_3 */
9425 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
9428 /* VEX_W_60_P_2 */
9429 { "vpunpcklbw", { XM, Vex128, EXx } },
9432 /* VEX_W_61_P_2 */
9433 { "vpunpcklwd", { XM, Vex128, EXx } },
9436 /* VEX_W_62_P_2 */
9437 { "vpunpckldq", { XM, Vex128, EXx } },
9440 /* VEX_W_63_P_2 */
9441 { "vpacksswb", { XM, Vex128, EXx } },
9444 /* VEX_W_64_P_2 */
9445 { "vpcmpgtb", { XM, Vex128, EXx } },
9448 /* VEX_W_65_P_2 */
9449 { "vpcmpgtw", { XM, Vex128, EXx } },
9452 /* VEX_W_66_P_2 */
9453 { "vpcmpgtd", { XM, Vex128, EXx } },
9456 /* VEX_W_67_P_2 */
9457 { "vpackuswb", { XM, Vex128, EXx } },
9460 /* VEX_W_68_P_2 */
9461 { "vpunpckhbw", { XM, Vex128, EXx } },
9464 /* VEX_W_69_P_2 */
9465 { "vpunpckhwd", { XM, Vex128, EXx } },
9468 /* VEX_W_6A_P_2 */
9469 { "vpunpckhdq", { XM, Vex128, EXx } },
9472 /* VEX_W_6B_P_2 */
9473 { "vpackssdw", { XM, Vex128, EXx } },
9476 /* VEX_W_6C_P_2 */
9477 { "vpunpcklqdq", { XM, Vex128, EXx } },
9480 /* VEX_W_6D_P_2 */
9481 { "vpunpckhqdq", { XM, Vex128, EXx } },
9484 /* VEX_W_6F_P_1 */
9485 { "vmovdqu", { XM, EXx } },
9488 /* VEX_W_6F_P_2 */
9489 { "vmovdqa", { XM, EXx } },
9492 /* VEX_W_70_P_1 */
9493 { "vpshufhw", { XM, EXx, Ib } },
9496 /* VEX_W_70_P_2 */
9497 { "vpshufd", { XM, EXx, Ib } },
9500 /* VEX_W_70_P_3 */
9501 { "vpshuflw", { XM, EXx, Ib } },
9504 /* VEX_W_71_R_2_P_2 */
9505 { "vpsrlw", { Vex128, XS, Ib } },
9508 /* VEX_W_71_R_4_P_2 */
9509 { "vpsraw", { Vex128, XS, Ib } },
9512 /* VEX_W_71_R_6_P_2 */
9513 { "vpsllw", { Vex128, XS, Ib } },
9516 /* VEX_W_72_R_2_P_2 */
9517 { "vpsrld", { Vex128, XS, Ib } },
9520 /* VEX_W_72_R_4_P_2 */
9521 { "vpsrad", { Vex128, XS, Ib } },
9524 /* VEX_W_72_R_6_P_2 */
9525 { "vpslld", { Vex128, XS, Ib } },
9528 /* VEX_W_73_R_2_P_2 */
9529 { "vpsrlq", { Vex128, XS, Ib } },
9532 /* VEX_W_73_R_3_P_2 */
9533 { "vpsrldq", { Vex128, XS, Ib } },
9536 /* VEX_W_73_R_6_P_2 */
9537 { "vpsllq", { Vex128, XS, Ib } },
9540 /* VEX_W_73_R_7_P_2 */
9541 { "vpslldq", { Vex128, XS, Ib } },
9544 /* VEX_W_74_P_2 */
9545 { "vpcmpeqb", { XM, Vex128, EXx } },
9548 /* VEX_W_75_P_2 */
9549 { "vpcmpeqw", { XM, Vex128, EXx } },
9552 /* VEX_W_76_P_2 */
9553 { "vpcmpeqd", { XM, Vex128, EXx } },
9556 /* VEX_W_77_P_0 */
9557 { "", { VZERO } },
9560 /* VEX_W_7C_P_2 */
9561 { "vhaddpd", { XM, Vex, EXx } },
9564 /* VEX_W_7C_P_3 */
9565 { "vhaddps", { XM, Vex, EXx } },
9568 /* VEX_W_7D_P_2 */
9569 { "vhsubpd", { XM, Vex, EXx } },
9572 /* VEX_W_7D_P_3 */
9573 { "vhsubps", { XM, Vex, EXx } },
9576 /* VEX_W_7E_P_1 */
9577 { "vmovq", { XMScalar, EXqScalar } },
9580 /* VEX_W_7F_P_1 */
9581 { "vmovdqu", { EXxS, XM } },
9584 /* VEX_W_7F_P_2 */
9585 { "vmovdqa", { EXxS, XM } },
9588 /* VEX_W_AE_R_2_M_0 */
9589 { "vldmxcsr", { Md } },
9592 /* VEX_W_AE_R_3_M_0 */
9593 { "vstmxcsr", { Md } },
9596 /* VEX_W_C2_P_0 */
9597 { "vcmpps", { XM, Vex, EXx, VCMP } },
9600 /* VEX_W_C2_P_1 */
9601 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
9604 /* VEX_W_C2_P_2 */
9605 { "vcmppd", { XM, Vex, EXx, VCMP } },
9608 /* VEX_W_C2_P_3 */
9609 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
9612 /* VEX_W_C4_P_2 */
9613 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
9616 /* VEX_W_C5_P_2 */
9617 { "vpextrw", { Gdq, XS, Ib } },
9620 /* VEX_W_D0_P_2 */
9621 { "vaddsubpd", { XM, Vex, EXx } },
9624 /* VEX_W_D0_P_3 */
9625 { "vaddsubps", { XM, Vex, EXx } },
9628 /* VEX_W_D1_P_2 */
9629 { "vpsrlw", { XM, Vex128, EXx } },
9632 /* VEX_W_D2_P_2 */
9633 { "vpsrld", { XM, Vex128, EXx } },
9636 /* VEX_W_D3_P_2 */
9637 { "vpsrlq", { XM, Vex128, EXx } },
9640 /* VEX_W_D4_P_2 */
9641 { "vpaddq", { XM, Vex128, EXx } },
9644 /* VEX_W_D5_P_2 */
9645 { "vpmullw", { XM, Vex128, EXx } },
9648 /* VEX_W_D6_P_2 */
9649 { "vmovq", { EXqScalarS, XMScalar } },
9652 /* VEX_W_D7_P_2_M_1 */
9653 { "vpmovmskb", { Gdq, XS } },
9656 /* VEX_W_D8_P_2 */
9657 { "vpsubusb", { XM, Vex128, EXx } },
9660 /* VEX_W_D9_P_2 */
9661 { "vpsubusw", { XM, Vex128, EXx } },
9664 /* VEX_W_DA_P_2 */
9665 { "vpminub", { XM, Vex128, EXx } },
9668 /* VEX_W_DB_P_2 */
9669 { "vpand", { XM, Vex128, EXx } },
9672 /* VEX_W_DC_P_2 */
9673 { "vpaddusb", { XM, Vex128, EXx } },
9676 /* VEX_W_DD_P_2 */
9677 { "vpaddusw", { XM, Vex128, EXx } },
9680 /* VEX_W_DE_P_2 */
9681 { "vpmaxub", { XM, Vex128, EXx } },
9684 /* VEX_W_DF_P_2 */
9685 { "vpandn", { XM, Vex128, EXx } },
9688 /* VEX_W_E0_P_2 */
9689 { "vpavgb", { XM, Vex128, EXx } },
9692 /* VEX_W_E1_P_2 */
9693 { "vpsraw", { XM, Vex128, EXx } },
9696 /* VEX_W_E2_P_2 */
9697 { "vpsrad", { XM, Vex128, EXx } },
9700 /* VEX_W_E3_P_2 */
9701 { "vpavgw", { XM, Vex128, EXx } },
9704 /* VEX_W_E4_P_2 */
9705 { "vpmulhuw", { XM, Vex128, EXx } },
9708 /* VEX_W_E5_P_2 */
9709 { "vpmulhw", { XM, Vex128, EXx } },
9712 /* VEX_W_E6_P_1 */
9713 { "vcvtdq2pd", { XM, EXxmmq } },
9716 /* VEX_W_E6_P_2 */
9717 { "vcvttpd2dq%XY", { XMM, EXx } },
9720 /* VEX_W_E6_P_3 */
9721 { "vcvtpd2dq%XY", { XMM, EXx } },
9724 /* VEX_W_E7_P_2_M_0 */
9725 { "vmovntdq", { Mx, XM } },
9728 /* VEX_W_E8_P_2 */
9729 { "vpsubsb", { XM, Vex128, EXx } },
9732 /* VEX_W_E9_P_2 */
9733 { "vpsubsw", { XM, Vex128, EXx } },
9736 /* VEX_W_EA_P_2 */
9737 { "vpminsw", { XM, Vex128, EXx } },
9740 /* VEX_W_EB_P_2 */
9741 { "vpor", { XM, Vex128, EXx } },
9744 /* VEX_W_EC_P_2 */
9745 { "vpaddsb", { XM, Vex128, EXx } },
9748 /* VEX_W_ED_P_2 */
9749 { "vpaddsw", { XM, Vex128, EXx } },
9752 /* VEX_W_EE_P_2 */
9753 { "vpmaxsw", { XM, Vex128, EXx } },
9756 /* VEX_W_EF_P_2 */
9757 { "vpxor", { XM, Vex128, EXx } },
9760 /* VEX_W_F0_P_3_M_0 */
9761 { "vlddqu", { XM, M } },
9764 /* VEX_W_F1_P_2 */
9765 { "vpsllw", { XM, Vex128, EXx } },
9768 /* VEX_W_F2_P_2 */
9769 { "vpslld", { XM, Vex128, EXx } },
9772 /* VEX_W_F3_P_2 */
9773 { "vpsllq", { XM, Vex128, EXx } },
9776 /* VEX_W_F4_P_2 */
9777 { "vpmuludq", { XM, Vex128, EXx } },
9780 /* VEX_W_F5_P_2 */
9781 { "vpmaddwd", { XM, Vex128, EXx } },
9784 /* VEX_W_F6_P_2 */
9785 { "vpsadbw", { XM, Vex128, EXx } },
9788 /* VEX_W_F7_P_2 */
9789 { "vmaskmovdqu", { XM, XS } },
9792 /* VEX_W_F8_P_2 */
9793 { "vpsubb", { XM, Vex128, EXx } },
9796 /* VEX_W_F9_P_2 */
9797 { "vpsubw", { XM, Vex128, EXx } },
9800 /* VEX_W_FA_P_2 */
9801 { "vpsubd", { XM, Vex128, EXx } },
9804 /* VEX_W_FB_P_2 */
9805 { "vpsubq", { XM, Vex128, EXx } },
9808 /* VEX_W_FC_P_2 */
9809 { "vpaddb", { XM, Vex128, EXx } },
9812 /* VEX_W_FD_P_2 */
9813 { "vpaddw", { XM, Vex128, EXx } },
9816 /* VEX_W_FE_P_2 */
9817 { "vpaddd", { XM, Vex128, EXx } },
9820 /* VEX_W_3800_P_2 */
9821 { "vpshufb", { XM, Vex128, EXx } },
9824 /* VEX_W_3801_P_2 */
9825 { "vphaddw", { XM, Vex128, EXx } },
9828 /* VEX_W_3802_P_2 */
9829 { "vphaddd", { XM, Vex128, EXx } },
9832 /* VEX_W_3803_P_2 */
9833 { "vphaddsw", { XM, Vex128, EXx } },
9836 /* VEX_W_3804_P_2 */
9837 { "vpmaddubsw", { XM, Vex128, EXx } },
9840 /* VEX_W_3805_P_2 */
9841 { "vphsubw", { XM, Vex128, EXx } },
9844 /* VEX_W_3806_P_2 */
9845 { "vphsubd", { XM, Vex128, EXx } },
9848 /* VEX_W_3807_P_2 */
9849 { "vphsubsw", { XM, Vex128, EXx } },
9852 /* VEX_W_3808_P_2 */
9853 { "vpsignb", { XM, Vex128, EXx } },
9856 /* VEX_W_3809_P_2 */
9857 { "vpsignw", { XM, Vex128, EXx } },
9860 /* VEX_W_380A_P_2 */
9861 { "vpsignd", { XM, Vex128, EXx } },
9864 /* VEX_W_380B_P_2 */
9865 { "vpmulhrsw", { XM, Vex128, EXx } },
9868 /* VEX_W_380C_P_2 */
9869 { "vpermilps", { XM, Vex, EXx } },
9872 /* VEX_W_380D_P_2 */
9873 { "vpermilpd", { XM, Vex, EXx } },
9876 /* VEX_W_380E_P_2 */
9877 { "vtestps", { XM, EXx } },
9880 /* VEX_W_380F_P_2 */
9881 { "vtestpd", { XM, EXx } },
9884 /* VEX_W_3817_P_2 */
9885 { "vptest", { XM, EXx } },
9888 /* VEX_W_3818_P_2_M_0 */
9889 { "vbroadcastss", { XM, Md } },
9892 /* VEX_W_3819_P_2_M_0 */
9893 { "vbroadcastsd", { XM, Mq } },
9896 /* VEX_W_381A_P_2_M_0 */
9897 { "vbroadcastf128", { XM, Mxmm } },
9900 /* VEX_W_381C_P_2 */
9901 { "vpabsb", { XM, EXx } },
9904 /* VEX_W_381D_P_2 */
9905 { "vpabsw", { XM, EXx } },
9908 /* VEX_W_381E_P_2 */
9909 { "vpabsd", { XM, EXx } },
9912 /* VEX_W_3820_P_2 */
9913 { "vpmovsxbw", { XM, EXq } },
9916 /* VEX_W_3821_P_2 */
9917 { "vpmovsxbd", { XM, EXd } },
9920 /* VEX_W_3822_P_2 */
9921 { "vpmovsxbq", { XM, EXw } },
9924 /* VEX_W_3823_P_2 */
9925 { "vpmovsxwd", { XM, EXq } },
9928 /* VEX_W_3824_P_2 */
9929 { "vpmovsxwq", { XM, EXd } },
9932 /* VEX_W_3825_P_2 */
9933 { "vpmovsxdq", { XM, EXq } },
9936 /* VEX_W_3828_P_2 */
9937 { "vpmuldq", { XM, Vex128, EXx } },
9940 /* VEX_W_3829_P_2 */
9941 { "vpcmpeqq", { XM, Vex128, EXx } },
9944 /* VEX_W_382A_P_2_M_0 */
9945 { "vmovntdqa", { XM, Mx } },
9948 /* VEX_W_382B_P_2 */
9949 { "vpackusdw", { XM, Vex128, EXx } },
9952 /* VEX_W_382C_P_2_M_0 */
9953 { "vmaskmovps", { XM, Vex, Mx } },
9956 /* VEX_W_382D_P_2_M_0 */
9957 { "vmaskmovpd", { XM, Vex, Mx } },
9960 /* VEX_W_382E_P_2_M_0 */
9961 { "vmaskmovps", { Mx, Vex, XM } },
9964 /* VEX_W_382F_P_2_M_0 */
9965 { "vmaskmovpd", { Mx, Vex, XM } },
9968 /* VEX_W_3830_P_2 */
9969 { "vpmovzxbw", { XM, EXq } },
9972 /* VEX_W_3831_P_2 */
9973 { "vpmovzxbd", { XM, EXd } },
9976 /* VEX_W_3832_P_2 */
9977 { "vpmovzxbq", { XM, EXw } },
9980 /* VEX_W_3833_P_2 */
9981 { "vpmovzxwd", { XM, EXq } },
9984 /* VEX_W_3834_P_2 */
9985 { "vpmovzxwq", { XM, EXd } },
9988 /* VEX_W_3835_P_2 */
9989 { "vpmovzxdq", { XM, EXq } },
9992 /* VEX_W_3837_P_2 */
9993 { "vpcmpgtq", { XM, Vex128, EXx } },
9996 /* VEX_W_3838_P_2 */
9997 { "vpminsb", { XM, Vex128, EXx } },
10000 /* VEX_W_3839_P_2 */
10001 { "vpminsd", { XM, Vex128, EXx } },
10004 /* VEX_W_383A_P_2 */
10005 { "vpminuw", { XM, Vex128, EXx } },
10008 /* VEX_W_383B_P_2 */
10009 { "vpminud", { XM, Vex128, EXx } },
10012 /* VEX_W_383C_P_2 */
10013 { "vpmaxsb", { XM, Vex128, EXx } },
10016 /* VEX_W_383D_P_2 */
10017 { "vpmaxsd", { XM, Vex128, EXx } },
10020 /* VEX_W_383E_P_2 */
10021 { "vpmaxuw", { XM, Vex128, EXx } },
10024 /* VEX_W_383F_P_2 */
10025 { "vpmaxud", { XM, Vex128, EXx } },
10028 /* VEX_W_3840_P_2 */
10029 { "vpmulld", { XM, Vex128, EXx } },
10032 /* VEX_W_3841_P_2 */
10033 { "vphminposuw", { XM, EXx } },
10036 /* VEX_W_38DB_P_2 */
10037 { "vaesimc", { XM, EXx } },
10040 /* VEX_W_38DC_P_2 */
10041 { "vaesenc", { XM, Vex128, EXx } },
10044 /* VEX_W_38DD_P_2 */
10045 { "vaesenclast", { XM, Vex128, EXx } },
10048 /* VEX_W_38DE_P_2 */
10049 { "vaesdec", { XM, Vex128, EXx } },
10052 /* VEX_W_38DF_P_2 */
10053 { "vaesdeclast", { XM, Vex128, EXx } },
10056 /* VEX_W_3A04_P_2 */
10057 { "vpermilps", { XM, EXx, Ib } },
10060 /* VEX_W_3A05_P_2 */
10061 { "vpermilpd", { XM, EXx, Ib } },
10064 /* VEX_W_3A06_P_2 */
10065 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10068 /* VEX_W_3A08_P_2 */
10069 { "vroundps", { XM, EXx, Ib } },
10072 /* VEX_W_3A09_P_2 */
10073 { "vroundpd", { XM, EXx, Ib } },
10076 /* VEX_W_3A0A_P_2 */
10077 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
10080 /* VEX_W_3A0B_P_2 */
10081 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
10084 /* VEX_W_3A0C_P_2 */
10085 { "vblendps", { XM, Vex, EXx, Ib } },
10088 /* VEX_W_3A0D_P_2 */
10089 { "vblendpd", { XM, Vex, EXx, Ib } },
10092 /* VEX_W_3A0E_P_2 */
10093 { "vpblendw", { XM, Vex128, EXx, Ib } },
10096 /* VEX_W_3A0F_P_2 */
10097 { "vpalignr", { XM, Vex128, EXx, Ib } },
10100 /* VEX_W_3A14_P_2 */
10101 { "vpextrb", { Edqb, XM, Ib } },
10104 /* VEX_W_3A15_P_2 */
10105 { "vpextrw", { Edqw, XM, Ib } },
10108 /* VEX_W_3A18_P_2 */
10109 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10112 /* VEX_W_3A19_P_2 */
10113 { "vextractf128", { EXxmm, XM, Ib } },
10116 /* VEX_W_3A20_P_2 */
10117 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10120 /* VEX_W_3A21_P_2 */
10121 { "vinsertps", { XM, Vex128, EXd, Ib } },
10124 /* VEX_W_3A40_P_2 */
10125 { "vdpps", { XM, Vex, EXx, Ib } },
10128 /* VEX_W_3A41_P_2 */
10129 { "vdppd", { XM, Vex128, EXx, Ib } },
10132 /* VEX_W_3A42_P_2 */
10133 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
10136 /* VEX_W_3A44_P_2 */
10137 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10140 /* VEX_W_3A48_P_2 */
10141 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10142 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10145 /* VEX_W_3A49_P_2 */
10146 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10147 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10150 /* VEX_W_3A4A_P_2 */
10151 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
10154 /* VEX_W_3A4B_P_2 */
10155 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
10158 /* VEX_W_3A4C_P_2 */
10159 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
10162 /* VEX_W_3A60_P_2 */
10163 { "vpcmpestrm", { XM, EXx, Ib } },
10166 /* VEX_W_3A61_P_2 */
10167 { "vpcmpestri", { XM, EXx, Ib } },
10170 /* VEX_W_3A62_P_2 */
10171 { "vpcmpistrm", { XM, EXx, Ib } },
10174 /* VEX_W_3A63_P_2 */
10175 { "vpcmpistri", { XM, EXx, Ib } },
10178 /* VEX_W_3ADF_P_2 */
10179 { "vaeskeygenassist", { XM, EXx, Ib } },
10183 static const struct dis386 mod_table[][2] = {
10185 /* MOD_8D */
10186 { "leaS", { Gv, M } },
10189 /* MOD_0F01_REG_0 */
10190 { X86_64_TABLE (X86_64_0F01_REG_0) },
10191 { RM_TABLE (RM_0F01_REG_0) },
10194 /* MOD_0F01_REG_1 */
10195 { X86_64_TABLE (X86_64_0F01_REG_1) },
10196 { RM_TABLE (RM_0F01_REG_1) },
10199 /* MOD_0F01_REG_2 */
10200 { X86_64_TABLE (X86_64_0F01_REG_2) },
10201 { RM_TABLE (RM_0F01_REG_2) },
10204 /* MOD_0F01_REG_3 */
10205 { X86_64_TABLE (X86_64_0F01_REG_3) },
10206 { RM_TABLE (RM_0F01_REG_3) },
10209 /* MOD_0F01_REG_7 */
10210 { "invlpg", { Mb } },
10211 { RM_TABLE (RM_0F01_REG_7) },
10214 /* MOD_0F12_PREFIX_0 */
10215 { "movlps", { XM, EXq } },
10216 { "movhlps", { XM, EXq } },
10219 /* MOD_0F13 */
10220 { "movlpX", { EXq, XM } },
10223 /* MOD_0F16_PREFIX_0 */
10224 { "movhps", { XM, EXq } },
10225 { "movlhps", { XM, EXq } },
10228 /* MOD_0F17 */
10229 { "movhpX", { EXq, XM } },
10232 /* MOD_0F18_REG_0 */
10233 { "prefetchnta", { Mb } },
10236 /* MOD_0F18_REG_1 */
10237 { "prefetcht0", { Mb } },
10240 /* MOD_0F18_REG_2 */
10241 { "prefetcht1", { Mb } },
10244 /* MOD_0F18_REG_3 */
10245 { "prefetcht2", { Mb } },
10248 /* MOD_0F20 */
10249 { Bad_Opcode },
10250 { "movZ", { Rm, Cm } },
10253 /* MOD_0F21 */
10254 { Bad_Opcode },
10255 { "movZ", { Rm, Dm } },
10258 /* MOD_0F22 */
10259 { Bad_Opcode },
10260 { "movZ", { Cm, Rm } },
10263 /* MOD_0F23 */
10264 { Bad_Opcode },
10265 { "movZ", { Dm, Rm } },
10268 /* MOD_0F24 */
10269 { Bad_Opcode },
10270 { "movL", { Rd, Td } },
10273 /* MOD_0F26 */
10274 { Bad_Opcode },
10275 { "movL", { Td, Rd } },
10278 /* MOD_0F2B_PREFIX_0 */
10279 {"movntps", { Mx, XM } },
10282 /* MOD_0F2B_PREFIX_1 */
10283 {"movntss", { Md, XM } },
10286 /* MOD_0F2B_PREFIX_2 */
10287 {"movntpd", { Mx, XM } },
10290 /* MOD_0F2B_PREFIX_3 */
10291 {"movntsd", { Mq, XM } },
10294 /* MOD_0F51 */
10295 { Bad_Opcode },
10296 { "movmskpX", { Gdq, XS } },
10299 /* MOD_0F71_REG_2 */
10300 { Bad_Opcode },
10301 { "psrlw", { MS, Ib } },
10304 /* MOD_0F71_REG_4 */
10305 { Bad_Opcode },
10306 { "psraw", { MS, Ib } },
10309 /* MOD_0F71_REG_6 */
10310 { Bad_Opcode },
10311 { "psllw", { MS, Ib } },
10314 /* MOD_0F72_REG_2 */
10315 { Bad_Opcode },
10316 { "psrld", { MS, Ib } },
10319 /* MOD_0F72_REG_4 */
10320 { Bad_Opcode },
10321 { "psrad", { MS, Ib } },
10324 /* MOD_0F72_REG_6 */
10325 { Bad_Opcode },
10326 { "pslld", { MS, Ib } },
10329 /* MOD_0F73_REG_2 */
10330 { Bad_Opcode },
10331 { "psrlq", { MS, Ib } },
10334 /* MOD_0F73_REG_3 */
10335 { Bad_Opcode },
10336 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10339 /* MOD_0F73_REG_6 */
10340 { Bad_Opcode },
10341 { "psllq", { MS, Ib } },
10344 /* MOD_0F73_REG_7 */
10345 { Bad_Opcode },
10346 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10349 /* MOD_0FAE_REG_0 */
10350 { "fxsave", { FXSAVE } },
10353 /* MOD_0FAE_REG_1 */
10354 { "fxrstor", { FXSAVE } },
10357 /* MOD_0FAE_REG_2 */
10358 { "ldmxcsr", { Md } },
10361 /* MOD_0FAE_REG_3 */
10362 { "stmxcsr", { Md } },
10365 /* MOD_0FAE_REG_4 */
10366 { "xsave", { FXSAVE } },
10369 /* MOD_0FAE_REG_5 */
10370 { "xrstor", { FXSAVE } },
10371 { RM_TABLE (RM_0FAE_REG_5) },
10374 /* MOD_0FAE_REG_6 */
10375 { Bad_Opcode },
10376 { RM_TABLE (RM_0FAE_REG_6) },
10379 /* MOD_0FAE_REG_7 */
10380 { "clflush", { Mb } },
10381 { RM_TABLE (RM_0FAE_REG_7) },
10384 /* MOD_0FB2 */
10385 { "lssS", { Gv, Mp } },
10388 /* MOD_0FB4 */
10389 { "lfsS", { Gv, Mp } },
10392 /* MOD_0FB5 */
10393 { "lgsS", { Gv, Mp } },
10396 /* MOD_0FC7_REG_6 */
10397 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10400 /* MOD_0FC7_REG_7 */
10401 { "vmptrst", { Mq } },
10404 /* MOD_0FD7 */
10405 { Bad_Opcode },
10406 { "pmovmskb", { Gdq, MS } },
10409 /* MOD_0FE7_PREFIX_2 */
10410 { "movntdq", { Mx, XM } },
10413 /* MOD_0FF0_PREFIX_3 */
10414 { "lddqu", { XM, M } },
10417 /* MOD_0F382A_PREFIX_2 */
10418 { "movntdqa", { XM, Mx } },
10421 /* MOD_62_32BIT */
10422 { "bound{S|}", { Gv, Ma } },
10425 /* MOD_C4_32BIT */
10426 { "lesS", { Gv, Mp } },
10427 { VEX_C4_TABLE (VEX_0F) },
10430 /* MOD_C5_32BIT */
10431 { "ldsS", { Gv, Mp } },
10432 { VEX_C5_TABLE (VEX_0F) },
10435 /* MOD_VEX_12_PREFIX_0 */
10436 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10437 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10440 /* MOD_VEX_13 */
10441 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10444 /* MOD_VEX_16_PREFIX_0 */
10445 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10446 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10449 /* MOD_VEX_17 */
10450 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10453 /* MOD_VEX_2B */
10454 { VEX_W_TABLE (VEX_W_2B_M_0) },
10457 /* MOD_VEX_50 */
10458 { Bad_Opcode },
10459 { VEX_W_TABLE (VEX_W_50_M_0) },
10462 /* MOD_VEX_71_REG_2 */
10463 { Bad_Opcode },
10464 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10467 /* MOD_VEX_71_REG_4 */
10468 { Bad_Opcode },
10469 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10472 /* MOD_VEX_71_REG_6 */
10473 { Bad_Opcode },
10474 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10477 /* MOD_VEX_72_REG_2 */
10478 { Bad_Opcode },
10479 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10482 /* MOD_VEX_72_REG_4 */
10483 { Bad_Opcode },
10484 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10487 /* MOD_VEX_72_REG_6 */
10488 { Bad_Opcode },
10489 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10492 /* MOD_VEX_73_REG_2 */
10493 { Bad_Opcode },
10494 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10497 /* MOD_VEX_73_REG_3 */
10498 { Bad_Opcode },
10499 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10502 /* MOD_VEX_73_REG_6 */
10503 { Bad_Opcode },
10504 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10507 /* MOD_VEX_73_REG_7 */
10508 { Bad_Opcode },
10509 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10512 /* MOD_VEX_AE_REG_2 */
10513 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10516 /* MOD_VEX_AE_REG_3 */
10517 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10520 /* MOD_VEX_D7_PREFIX_2 */
10521 { Bad_Opcode },
10522 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10525 /* MOD_VEX_E7_PREFIX_2 */
10526 { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10529 /* MOD_VEX_F0_PREFIX_3 */
10530 { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10533 /* MOD_VEX_3818_PREFIX_2 */
10534 { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10537 /* MOD_VEX_3819_PREFIX_2 */
10538 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10541 /* MOD_VEX_381A_PREFIX_2 */
10542 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10545 /* MOD_VEX_382A_PREFIX_2 */
10546 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10549 /* MOD_VEX_382C_PREFIX_2 */
10550 { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10553 /* MOD_VEX_382D_PREFIX_2 */
10554 { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10557 /* MOD_VEX_382E_PREFIX_2 */
10558 { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10561 /* MOD_VEX_382F_PREFIX_2 */
10562 { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10566 static const struct dis386 rm_table[][8] = {
10568 /* RM_0F01_REG_0 */
10569 { Bad_Opcode },
10570 { "vmcall", { Skip_MODRM } },
10571 { "vmlaunch", { Skip_MODRM } },
10572 { "vmresume", { Skip_MODRM } },
10573 { "vmxoff", { Skip_MODRM } },
10576 /* RM_0F01_REG_1 */
10577 { "monitor", { { OP_Monitor, 0 } } },
10578 { "mwait", { { OP_Mwait, 0 } } },
10581 /* RM_0F01_REG_2 */
10582 { "xgetbv", { Skip_MODRM } },
10583 { "xsetbv", { Skip_MODRM } },
10586 /* RM_0F01_REG_3 */
10587 { "vmrun", { Skip_MODRM } },
10588 { "vmmcall", { Skip_MODRM } },
10589 { "vmload", { Skip_MODRM } },
10590 { "vmsave", { Skip_MODRM } },
10591 { "stgi", { Skip_MODRM } },
10592 { "clgi", { Skip_MODRM } },
10593 { "skinit", { Skip_MODRM } },
10594 { "invlpga", { Skip_MODRM } },
10597 /* RM_0F01_REG_7 */
10598 { "swapgs", { Skip_MODRM } },
10599 { "rdtscp", { Skip_MODRM } },
10602 /* RM_0FAE_REG_5 */
10603 { "lfence", { Skip_MODRM } },
10606 /* RM_0FAE_REG_6 */
10607 { "mfence", { Skip_MODRM } },
10610 /* RM_0FAE_REG_7 */
10611 { "sfence", { Skip_MODRM } },
10615 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10617 /* We use the high bit to indicate different name for the same
10618 prefix. */
10619 #define ADDR16_PREFIX (0x67 | 0x100)
10620 #define ADDR32_PREFIX (0x67 | 0x200)
10621 #define DATA16_PREFIX (0x66 | 0x100)
10622 #define DATA32_PREFIX (0x66 | 0x200)
10623 #define REP_PREFIX (0xf3 | 0x100)
10625 static int
10626 ckprefix (void)
10628 int newrex, i, length;
10629 rex = 0;
10630 rex_ignored = 0;
10631 prefixes = 0;
10632 used_prefixes = 0;
10633 rex_used = 0;
10634 last_lock_prefix = -1;
10635 last_repz_prefix = -1;
10636 last_repnz_prefix = -1;
10637 last_data_prefix = -1;
10638 last_addr_prefix = -1;
10639 last_rex_prefix = -1;
10640 last_seg_prefix = -1;
10641 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10642 all_prefixes[i] = 0;
10643 i = 0;
10644 length = 0;
10645 /* The maximum instruction length is 15bytes. */
10646 while (length < MAX_CODE_LENGTH - 1)
10648 FETCH_DATA (the_info, codep + 1);
10649 newrex = 0;
10650 switch (*codep)
10652 /* REX prefixes family. */
10653 case 0x40:
10654 case 0x41:
10655 case 0x42:
10656 case 0x43:
10657 case 0x44:
10658 case 0x45:
10659 case 0x46:
10660 case 0x47:
10661 case 0x48:
10662 case 0x49:
10663 case 0x4a:
10664 case 0x4b:
10665 case 0x4c:
10666 case 0x4d:
10667 case 0x4e:
10668 case 0x4f:
10669 if (address_mode == mode_64bit)
10670 newrex = *codep;
10671 else
10672 return 1;
10673 last_rex_prefix = i;
10674 break;
10675 case 0xf3:
10676 prefixes |= PREFIX_REPZ;
10677 last_repz_prefix = i;
10678 break;
10679 case 0xf2:
10680 prefixes |= PREFIX_REPNZ;
10681 last_repnz_prefix = i;
10682 break;
10683 case 0xf0:
10684 prefixes |= PREFIX_LOCK;
10685 last_lock_prefix = i;
10686 break;
10687 case 0x2e:
10688 prefixes |= PREFIX_CS;
10689 last_seg_prefix = i;
10690 break;
10691 case 0x36:
10692 prefixes |= PREFIX_SS;
10693 last_seg_prefix = i;
10694 break;
10695 case 0x3e:
10696 prefixes |= PREFIX_DS;
10697 last_seg_prefix = i;
10698 break;
10699 case 0x26:
10700 prefixes |= PREFIX_ES;
10701 last_seg_prefix = i;
10702 break;
10703 case 0x64:
10704 prefixes |= PREFIX_FS;
10705 last_seg_prefix = i;
10706 break;
10707 case 0x65:
10708 prefixes |= PREFIX_GS;
10709 last_seg_prefix = i;
10710 break;
10711 case 0x66:
10712 prefixes |= PREFIX_DATA;
10713 last_data_prefix = i;
10714 break;
10715 case 0x67:
10716 prefixes |= PREFIX_ADDR;
10717 last_addr_prefix = i;
10718 break;
10719 case FWAIT_OPCODE:
10720 /* fwait is really an instruction. If there are prefixes
10721 before the fwait, they belong to the fwait, *not* to the
10722 following instruction. */
10723 if (prefixes || rex)
10725 prefixes |= PREFIX_FWAIT;
10726 codep++;
10727 return 1;
10729 prefixes = PREFIX_FWAIT;
10730 break;
10731 default:
10732 return 1;
10734 /* Rex is ignored when followed by another prefix. */
10735 if (rex)
10737 rex_used = rex;
10738 return 1;
10740 if (*codep != FWAIT_OPCODE)
10741 all_prefixes[i++] = *codep;
10742 rex = newrex;
10743 codep++;
10744 length++;
10746 return 0;
10749 static int
10750 seg_prefix (int pref)
10752 switch (pref)
10754 case 0x2e:
10755 return PREFIX_CS;
10756 case 0x36:
10757 return PREFIX_SS;
10758 case 0x3e:
10759 return PREFIX_DS;
10760 case 0x26:
10761 return PREFIX_ES;
10762 case 0x64:
10763 return PREFIX_FS;
10764 case 0x65:
10765 return PREFIX_GS;
10766 default:
10767 return 0;
10771 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10772 prefix byte. */
10774 static const char *
10775 prefix_name (int pref, int sizeflag)
10777 static const char *rexes [16] =
10779 "rex", /* 0x40 */
10780 "rex.B", /* 0x41 */
10781 "rex.X", /* 0x42 */
10782 "rex.XB", /* 0x43 */
10783 "rex.R", /* 0x44 */
10784 "rex.RB", /* 0x45 */
10785 "rex.RX", /* 0x46 */
10786 "rex.RXB", /* 0x47 */
10787 "rex.W", /* 0x48 */
10788 "rex.WB", /* 0x49 */
10789 "rex.WX", /* 0x4a */
10790 "rex.WXB", /* 0x4b */
10791 "rex.WR", /* 0x4c */
10792 "rex.WRB", /* 0x4d */
10793 "rex.WRX", /* 0x4e */
10794 "rex.WRXB", /* 0x4f */
10797 switch (pref)
10799 /* REX prefixes family. */
10800 case 0x40:
10801 case 0x41:
10802 case 0x42:
10803 case 0x43:
10804 case 0x44:
10805 case 0x45:
10806 case 0x46:
10807 case 0x47:
10808 case 0x48:
10809 case 0x49:
10810 case 0x4a:
10811 case 0x4b:
10812 case 0x4c:
10813 case 0x4d:
10814 case 0x4e:
10815 case 0x4f:
10816 return rexes [pref - 0x40];
10817 case 0xf3:
10818 return "repz";
10819 case 0xf2:
10820 return "repnz";
10821 case 0xf0:
10822 return "lock";
10823 case 0x2e:
10824 return "cs";
10825 case 0x36:
10826 return "ss";
10827 case 0x3e:
10828 return "ds";
10829 case 0x26:
10830 return "es";
10831 case 0x64:
10832 return "fs";
10833 case 0x65:
10834 return "gs";
10835 case 0x66:
10836 return (sizeflag & DFLAG) ? "data16" : "data32";
10837 case 0x67:
10838 if (address_mode == mode_64bit)
10839 return (sizeflag & AFLAG) ? "addr32" : "addr64";
10840 else
10841 return (sizeflag & AFLAG) ? "addr16" : "addr32";
10842 case FWAIT_OPCODE:
10843 return "fwait";
10844 case ADDR16_PREFIX:
10845 return "addr16";
10846 case ADDR32_PREFIX:
10847 return "addr32";
10848 case DATA16_PREFIX:
10849 return "data16";
10850 case DATA32_PREFIX:
10851 return "data32";
10852 case REP_PREFIX:
10853 return "rep";
10854 default:
10855 return NULL;
10859 static char op_out[MAX_OPERANDS][100];
10860 static int op_ad, op_index[MAX_OPERANDS];
10861 static int two_source_ops;
10862 static bfd_vma op_address[MAX_OPERANDS];
10863 static bfd_vma op_riprel[MAX_OPERANDS];
10864 static bfd_vma start_pc;
10867 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10868 * (see topic "Redundant prefixes" in the "Differences from 8086"
10869 * section of the "Virtual 8086 Mode" chapter.)
10870 * 'pc' should be the address of this instruction, it will
10871 * be used to print the target address if this is a relative jump or call
10872 * The function returns the length of this instruction in bytes.
10875 static char intel_syntax;
10876 static char intel_mnemonic = !SYSV386_COMPAT;
10877 static char open_char;
10878 static char close_char;
10879 static char separator_char;
10880 static char scale_char;
10882 /* Here for backwards compatibility. When gdb stops using
10883 print_insn_i386_att and print_insn_i386_intel these functions can
10884 disappear, and print_insn_i386 be merged into print_insn. */
10886 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10888 intel_syntax = 0;
10890 return print_insn (pc, info);
10894 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10896 intel_syntax = 1;
10898 return print_insn (pc, info);
10902 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10904 intel_syntax = -1;
10906 return print_insn (pc, info);
10909 void
10910 print_i386_disassembler_options (FILE *stream)
10912 fprintf (stream, _("\n\
10913 The following i386/x86-64 specific disassembler options are supported for use\n\
10914 with the -M switch (multiple options should be separated by commas):\n"));
10916 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
10917 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
10918 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
10919 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
10920 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
10921 fprintf (stream, _(" att-mnemonic\n"
10922 " Display instruction in AT&T mnemonic\n"));
10923 fprintf (stream, _(" intel-mnemonic\n"
10924 " Display instruction in Intel mnemonic\n"));
10925 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
10926 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
10927 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
10928 fprintf (stream, _(" data32 Assume 32bit data size\n"));
10929 fprintf (stream, _(" data16 Assume 16bit data size\n"));
10930 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10933 /* Bad opcode. */
10934 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10936 /* Get a pointer to struct dis386 with a valid name. */
10938 static const struct dis386 *
10939 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10941 int vindex, vex_table_index;
10943 if (dp->name != NULL)
10944 return dp;
10946 switch (dp->op[0].bytemode)
10948 case USE_REG_TABLE:
10949 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10950 break;
10952 case USE_MOD_TABLE:
10953 vindex = modrm.mod == 0x3 ? 1 : 0;
10954 dp = &mod_table[dp->op[1].bytemode][vindex];
10955 break;
10957 case USE_RM_TABLE:
10958 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10959 break;
10961 case USE_PREFIX_TABLE:
10962 if (need_vex)
10964 /* The prefix in VEX is implicit. */
10965 switch (vex.prefix)
10967 case 0:
10968 vindex = 0;
10969 break;
10970 case REPE_PREFIX_OPCODE:
10971 vindex = 1;
10972 break;
10973 case DATA_PREFIX_OPCODE:
10974 vindex = 2;
10975 break;
10976 case REPNE_PREFIX_OPCODE:
10977 vindex = 3;
10978 break;
10979 default:
10980 abort ();
10981 break;
10984 else
10986 vindex = 0;
10987 used_prefixes |= (prefixes & PREFIX_REPZ);
10988 if (prefixes & PREFIX_REPZ)
10990 vindex = 1;
10991 all_prefixes[last_repz_prefix] = 0;
10993 else
10995 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10996 PREFIX_DATA. */
10997 used_prefixes |= (prefixes & PREFIX_REPNZ);
10998 if (prefixes & PREFIX_REPNZ)
11000 vindex = 3;
11001 all_prefixes[last_repnz_prefix] = 0;
11003 else
11005 used_prefixes |= (prefixes & PREFIX_DATA);
11006 if (prefixes & PREFIX_DATA)
11008 vindex = 2;
11009 all_prefixes[last_data_prefix] = 0;
11014 dp = &prefix_table[dp->op[1].bytemode][vindex];
11015 break;
11017 case USE_X86_64_TABLE:
11018 vindex = address_mode == mode_64bit ? 1 : 0;
11019 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11020 break;
11022 case USE_3BYTE_TABLE:
11023 FETCH_DATA (info, codep + 2);
11024 vindex = *codep++;
11025 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11026 modrm.mod = (*codep >> 6) & 3;
11027 modrm.reg = (*codep >> 3) & 7;
11028 modrm.rm = *codep & 7;
11029 break;
11031 case USE_VEX_LEN_TABLE:
11032 if (!need_vex)
11033 abort ();
11035 switch (vex.length)
11037 case 128:
11038 vindex = 0;
11039 break;
11040 case 256:
11041 vindex = 1;
11042 break;
11043 default:
11044 abort ();
11045 break;
11048 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11049 break;
11051 case USE_XOP_8F_TABLE:
11052 FETCH_DATA (info, codep + 3);
11053 /* All bits in the REX prefix are ignored. */
11054 rex_ignored = rex;
11055 rex = ~(*codep >> 5) & 0x7;
11057 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11058 switch ((*codep & 0x1f))
11060 default:
11061 dp = &bad_opcode;
11062 return dp;
11063 case 0x8:
11064 vex_table_index = XOP_08;
11065 break;
11066 case 0x9:
11067 vex_table_index = XOP_09;
11068 break;
11069 case 0xa:
11070 vex_table_index = XOP_0A;
11071 break;
11073 codep++;
11074 vex.w = *codep & 0x80;
11075 if (vex.w && address_mode == mode_64bit)
11076 rex |= REX_W;
11078 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11079 if (address_mode != mode_64bit
11080 && vex.register_specifier > 0x7)
11082 dp = &bad_opcode;
11083 return dp;
11086 vex.length = (*codep & 0x4) ? 256 : 128;
11087 switch ((*codep & 0x3))
11089 case 0:
11090 vex.prefix = 0;
11091 break;
11092 case 1:
11093 vex.prefix = DATA_PREFIX_OPCODE;
11094 break;
11095 case 2:
11096 vex.prefix = REPE_PREFIX_OPCODE;
11097 break;
11098 case 3:
11099 vex.prefix = REPNE_PREFIX_OPCODE;
11100 break;
11102 need_vex = 1;
11103 need_vex_reg = 1;
11104 codep++;
11105 vindex = *codep++;
11106 dp = &xop_table[vex_table_index][vindex];
11108 FETCH_DATA (info, codep + 1);
11109 modrm.mod = (*codep >> 6) & 3;
11110 modrm.reg = (*codep >> 3) & 7;
11111 modrm.rm = *codep & 7;
11112 break;
11114 case USE_VEX_C4_TABLE:
11115 FETCH_DATA (info, codep + 3);
11116 /* All bits in the REX prefix are ignored. */
11117 rex_ignored = rex;
11118 rex = ~(*codep >> 5) & 0x7;
11119 switch ((*codep & 0x1f))
11121 default:
11122 dp = &bad_opcode;
11123 return dp;
11124 case 0x1:
11125 vex_table_index = VEX_0F;
11126 break;
11127 case 0x2:
11128 vex_table_index = VEX_0F38;
11129 break;
11130 case 0x3:
11131 vex_table_index = VEX_0F3A;
11132 break;
11134 codep++;
11135 vex.w = *codep & 0x80;
11136 if (vex.w && address_mode == mode_64bit)
11137 rex |= REX_W;
11139 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11140 if (address_mode != mode_64bit
11141 && vex.register_specifier > 0x7)
11143 dp = &bad_opcode;
11144 return dp;
11147 vex.length = (*codep & 0x4) ? 256 : 128;
11148 switch ((*codep & 0x3))
11150 case 0:
11151 vex.prefix = 0;
11152 break;
11153 case 1:
11154 vex.prefix = DATA_PREFIX_OPCODE;
11155 break;
11156 case 2:
11157 vex.prefix = REPE_PREFIX_OPCODE;
11158 break;
11159 case 3:
11160 vex.prefix = REPNE_PREFIX_OPCODE;
11161 break;
11163 need_vex = 1;
11164 need_vex_reg = 1;
11165 codep++;
11166 vindex = *codep++;
11167 dp = &vex_table[vex_table_index][vindex];
11168 /* There is no MODRM byte for VEX [82|77]. */
11169 if (vindex != 0x77 && vindex != 0x82)
11171 FETCH_DATA (info, codep + 1);
11172 modrm.mod = (*codep >> 6) & 3;
11173 modrm.reg = (*codep >> 3) & 7;
11174 modrm.rm = *codep & 7;
11176 break;
11178 case USE_VEX_C5_TABLE:
11179 FETCH_DATA (info, codep + 2);
11180 /* All bits in the REX prefix are ignored. */
11181 rex_ignored = rex;
11182 rex = (*codep & 0x80) ? 0 : REX_R;
11184 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11185 if (address_mode != mode_64bit
11186 && vex.register_specifier > 0x7)
11188 dp = &bad_opcode;
11189 return dp;
11192 vex.w = 0;
11194 vex.length = (*codep & 0x4) ? 256 : 128;
11195 switch ((*codep & 0x3))
11197 case 0:
11198 vex.prefix = 0;
11199 break;
11200 case 1:
11201 vex.prefix = DATA_PREFIX_OPCODE;
11202 break;
11203 case 2:
11204 vex.prefix = REPE_PREFIX_OPCODE;
11205 break;
11206 case 3:
11207 vex.prefix = REPNE_PREFIX_OPCODE;
11208 break;
11210 need_vex = 1;
11211 need_vex_reg = 1;
11212 codep++;
11213 vindex = *codep++;
11214 dp = &vex_table[dp->op[1].bytemode][vindex];
11215 /* There is no MODRM byte for VEX [82|77]. */
11216 if (vindex != 0x77 && vindex != 0x82)
11218 FETCH_DATA (info, codep + 1);
11219 modrm.mod = (*codep >> 6) & 3;
11220 modrm.reg = (*codep >> 3) & 7;
11221 modrm.rm = *codep & 7;
11223 break;
11225 case USE_VEX_W_TABLE:
11226 if (!need_vex)
11227 abort ();
11229 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11230 break;
11232 case 0:
11233 dp = &bad_opcode;
11234 break;
11236 default:
11237 abort ();
11240 if (dp->name != NULL)
11241 return dp;
11242 else
11243 return get_valid_dis386 (dp, info);
11246 static int
11247 print_insn (bfd_vma pc, disassemble_info *info)
11249 const struct dis386 *dp;
11250 int i;
11251 char *op_txt[MAX_OPERANDS];
11252 int needcomma;
11253 int sizeflag;
11254 const char *p;
11255 struct dis_private priv;
11256 int prefix_length;
11257 int default_prefixes;
11259 if (info->mach == bfd_mach_x86_64_intel_syntax
11260 || info->mach == bfd_mach_x86_64
11261 || info->mach == bfd_mach_l1om
11262 || info->mach == bfd_mach_l1om_intel_syntax)
11263 address_mode = mode_64bit;
11264 else
11265 address_mode = mode_32bit;
11267 if (intel_syntax == (char) -1)
11268 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11269 || info->mach == bfd_mach_x86_64_intel_syntax
11270 || info->mach == bfd_mach_l1om_intel_syntax);
11272 if (info->mach == bfd_mach_i386_i386
11273 || info->mach == bfd_mach_x86_64
11274 || info->mach == bfd_mach_l1om
11275 || info->mach == bfd_mach_i386_i386_intel_syntax
11276 || info->mach == bfd_mach_x86_64_intel_syntax
11277 || info->mach == bfd_mach_l1om_intel_syntax)
11278 priv.orig_sizeflag = AFLAG | DFLAG;
11279 else if (info->mach == bfd_mach_i386_i8086)
11280 priv.orig_sizeflag = 0;
11281 else
11282 abort ();
11284 for (p = info->disassembler_options; p != NULL; )
11286 if (CONST_STRNEQ (p, "x86-64"))
11288 address_mode = mode_64bit;
11289 priv.orig_sizeflag = AFLAG | DFLAG;
11291 else if (CONST_STRNEQ (p, "i386"))
11293 address_mode = mode_32bit;
11294 priv.orig_sizeflag = AFLAG | DFLAG;
11296 else if (CONST_STRNEQ (p, "i8086"))
11298 address_mode = mode_16bit;
11299 priv.orig_sizeflag = 0;
11301 else if (CONST_STRNEQ (p, "intel"))
11303 intel_syntax = 1;
11304 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11305 intel_mnemonic = 1;
11307 else if (CONST_STRNEQ (p, "att"))
11309 intel_syntax = 0;
11310 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11311 intel_mnemonic = 0;
11313 else if (CONST_STRNEQ (p, "addr"))
11315 if (address_mode == mode_64bit)
11317 if (p[4] == '3' && p[5] == '2')
11318 priv.orig_sizeflag &= ~AFLAG;
11319 else if (p[4] == '6' && p[5] == '4')
11320 priv.orig_sizeflag |= AFLAG;
11322 else
11324 if (p[4] == '1' && p[5] == '6')
11325 priv.orig_sizeflag &= ~AFLAG;
11326 else if (p[4] == '3' && p[5] == '2')
11327 priv.orig_sizeflag |= AFLAG;
11330 else if (CONST_STRNEQ (p, "data"))
11332 if (p[4] == '1' && p[5] == '6')
11333 priv.orig_sizeflag &= ~DFLAG;
11334 else if (p[4] == '3' && p[5] == '2')
11335 priv.orig_sizeflag |= DFLAG;
11337 else if (CONST_STRNEQ (p, "suffix"))
11338 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11340 p = strchr (p, ',');
11341 if (p != NULL)
11342 p++;
11345 if (intel_syntax)
11347 names64 = intel_names64;
11348 names32 = intel_names32;
11349 names16 = intel_names16;
11350 names8 = intel_names8;
11351 names8rex = intel_names8rex;
11352 names_seg = intel_names_seg;
11353 names_mm = intel_names_mm;
11354 names_xmm = intel_names_xmm;
11355 names_ymm = intel_names_ymm;
11356 index64 = intel_index64;
11357 index32 = intel_index32;
11358 index16 = intel_index16;
11359 open_char = '[';
11360 close_char = ']';
11361 separator_char = '+';
11362 scale_char = '*';
11364 else
11366 names64 = att_names64;
11367 names32 = att_names32;
11368 names16 = att_names16;
11369 names8 = att_names8;
11370 names8rex = att_names8rex;
11371 names_seg = att_names_seg;
11372 names_mm = att_names_mm;
11373 names_xmm = att_names_xmm;
11374 names_ymm = att_names_ymm;
11375 index64 = att_index64;
11376 index32 = att_index32;
11377 index16 = att_index16;
11378 open_char = '(';
11379 close_char = ')';
11380 separator_char = ',';
11381 scale_char = ',';
11384 /* The output looks better if we put 7 bytes on a line, since that
11385 puts most long word instructions on a single line. Use 8 bytes
11386 for Intel L1OM. */
11387 if (info->mach == bfd_mach_l1om
11388 || info->mach == bfd_mach_l1om_intel_syntax)
11389 info->bytes_per_line = 8;
11390 else
11391 info->bytes_per_line = 7;
11393 info->private_data = &priv;
11394 priv.max_fetched = priv.the_buffer;
11395 priv.insn_start = pc;
11397 obuf[0] = 0;
11398 for (i = 0; i < MAX_OPERANDS; ++i)
11400 op_out[i][0] = 0;
11401 op_index[i] = -1;
11404 the_info = info;
11405 start_pc = pc;
11406 start_codep = priv.the_buffer;
11407 codep = priv.the_buffer;
11409 if (setjmp (priv.bailout) != 0)
11411 const char *name;
11413 /* Getting here means we tried for data but didn't get it. That
11414 means we have an incomplete instruction of some sort. Just
11415 print the first byte as a prefix or a .byte pseudo-op. */
11416 if (codep > priv.the_buffer)
11418 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11419 if (name != NULL)
11420 (*info->fprintf_func) (info->stream, "%s", name);
11421 else
11423 /* Just print the first byte as a .byte instruction. */
11424 (*info->fprintf_func) (info->stream, ".byte 0x%x",
11425 (unsigned int) priv.the_buffer[0]);
11428 return 1;
11431 return -1;
11434 obufp = obuf;
11435 sizeflag = priv.orig_sizeflag;
11437 if (!ckprefix () || rex_used)
11439 /* Too many prefixes or unused REX prefixes. */
11440 for (i = 0;
11441 all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11442 i++)
11443 (*info->fprintf_func) (info->stream, "%s",
11444 prefix_name (all_prefixes[i], sizeflag));
11445 return 1;
11448 insn_codep = codep;
11450 FETCH_DATA (info, codep + 1);
11451 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11453 if (((prefixes & PREFIX_FWAIT)
11454 && ((*codep < 0xd8) || (*codep > 0xdf))))
11456 (*info->fprintf_func) (info->stream, "fwait");
11457 return 1;
11460 if (*codep == 0x0f)
11462 unsigned char threebyte;
11463 FETCH_DATA (info, codep + 2);
11464 threebyte = *++codep;
11465 dp = &dis386_twobyte[threebyte];
11466 need_modrm = twobyte_has_modrm[*codep];
11467 codep++;
11469 else
11471 dp = &dis386[*codep];
11472 need_modrm = onebyte_has_modrm[*codep];
11473 codep++;
11476 if ((prefixes & PREFIX_REPZ))
11477 used_prefixes |= PREFIX_REPZ;
11478 if ((prefixes & PREFIX_REPNZ))
11479 used_prefixes |= PREFIX_REPNZ;
11480 if ((prefixes & PREFIX_LOCK))
11481 used_prefixes |= PREFIX_LOCK;
11483 default_prefixes = 0;
11484 if (prefixes & PREFIX_ADDR)
11486 sizeflag ^= AFLAG;
11487 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11489 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11490 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11491 else
11492 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11493 default_prefixes |= PREFIX_ADDR;
11497 if ((prefixes & PREFIX_DATA))
11499 sizeflag ^= DFLAG;
11500 if (dp->op[2].bytemode == cond_jump_mode
11501 && dp->op[0].bytemode == v_mode
11502 && !intel_syntax)
11504 if (sizeflag & DFLAG)
11505 all_prefixes[last_data_prefix] = DATA32_PREFIX;
11506 else
11507 all_prefixes[last_data_prefix] = DATA16_PREFIX;
11508 default_prefixes |= PREFIX_DATA;
11510 else if (rex & REX_W)
11512 /* REX_W will override PREFIX_DATA. */
11513 default_prefixes |= PREFIX_DATA;
11517 if (need_modrm)
11519 FETCH_DATA (info, codep + 1);
11520 modrm.mod = (*codep >> 6) & 3;
11521 modrm.reg = (*codep >> 3) & 7;
11522 modrm.rm = *codep & 7;
11525 need_vex = 0;
11526 need_vex_reg = 0;
11527 vex_w_done = 0;
11529 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11531 dofloat (sizeflag);
11533 else
11535 dp = get_valid_dis386 (dp, info);
11536 if (dp != NULL && putop (dp->name, sizeflag) == 0)
11538 for (i = 0; i < MAX_OPERANDS; ++i)
11540 obufp = op_out[i];
11541 op_ad = MAX_OPERANDS - 1 - i;
11542 if (dp->op[i].rtn)
11543 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11548 /* See if any prefixes were not used. If so, print the first one
11549 separately. If we don't do this, we'll wind up printing an
11550 instruction stream which does not precisely correspond to the
11551 bytes we are disassembling. */
11552 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11554 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11555 if (all_prefixes[i])
11557 const char *name;
11558 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11559 if (name == NULL)
11560 name = INTERNAL_DISASSEMBLER_ERROR;
11561 (*info->fprintf_func) (info->stream, "%s", name);
11562 return 1;
11566 /* Check if the REX prefix is used. */
11567 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11568 all_prefixes[last_rex_prefix] = 0;
11570 /* Check if the SEG prefix is used. */
11571 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11572 | PREFIX_FS | PREFIX_GS)) != 0
11573 && (used_prefixes
11574 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11575 all_prefixes[last_seg_prefix] = 0;
11577 /* Check if the ADDR prefix is used. */
11578 if ((prefixes & PREFIX_ADDR) != 0
11579 && (used_prefixes & PREFIX_ADDR) != 0)
11580 all_prefixes[last_addr_prefix] = 0;
11582 /* Check if the DATA prefix is used. */
11583 if ((prefixes & PREFIX_DATA) != 0
11584 && (used_prefixes & PREFIX_DATA) != 0)
11585 all_prefixes[last_data_prefix] = 0;
11587 prefix_length = 0;
11588 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11589 if (all_prefixes[i])
11591 const char *name;
11592 name = prefix_name (all_prefixes[i], sizeflag);
11593 if (name == NULL)
11594 abort ();
11595 prefix_length += strlen (name) + 1;
11596 (*info->fprintf_func) (info->stream, "%s ", name);
11599 /* Check maximum code length. */
11600 if ((codep - start_codep) > MAX_CODE_LENGTH)
11602 (*info->fprintf_func) (info->stream, "(bad)");
11603 return MAX_CODE_LENGTH;
11606 obufp = mnemonicendp;
11607 for (i = strlen (obuf) + prefix_length; i < 6; i++)
11608 oappend (" ");
11609 oappend (" ");
11610 (*info->fprintf_func) (info->stream, "%s", obuf);
11612 /* The enter and bound instructions are printed with operands in the same
11613 order as the intel book; everything else is printed in reverse order. */
11614 if (intel_syntax || two_source_ops)
11616 bfd_vma riprel;
11618 for (i = 0; i < MAX_OPERANDS; ++i)
11619 op_txt[i] = op_out[i];
11621 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11623 op_ad = op_index[i];
11624 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11625 op_index[MAX_OPERANDS - 1 - i] = op_ad;
11626 riprel = op_riprel[i];
11627 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11628 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11631 else
11633 for (i = 0; i < MAX_OPERANDS; ++i)
11634 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11637 needcomma = 0;
11638 for (i = 0; i < MAX_OPERANDS; ++i)
11639 if (*op_txt[i])
11641 if (needcomma)
11642 (*info->fprintf_func) (info->stream, ",");
11643 if (op_index[i] != -1 && !op_riprel[i])
11644 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11645 else
11646 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11647 needcomma = 1;
11650 for (i = 0; i < MAX_OPERANDS; i++)
11651 if (op_index[i] != -1 && op_riprel[i])
11653 (*info->fprintf_func) (info->stream, " # ");
11654 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11655 + op_address[op_index[i]]), info);
11656 break;
11658 return codep - priv.the_buffer;
11661 static const char *float_mem[] = {
11662 /* d8 */
11663 "fadd{s|}",
11664 "fmul{s|}",
11665 "fcom{s|}",
11666 "fcomp{s|}",
11667 "fsub{s|}",
11668 "fsubr{s|}",
11669 "fdiv{s|}",
11670 "fdivr{s|}",
11671 /* d9 */
11672 "fld{s|}",
11673 "(bad)",
11674 "fst{s|}",
11675 "fstp{s|}",
11676 "fldenvIC",
11677 "fldcw",
11678 "fNstenvIC",
11679 "fNstcw",
11680 /* da */
11681 "fiadd{l|}",
11682 "fimul{l|}",
11683 "ficom{l|}",
11684 "ficomp{l|}",
11685 "fisub{l|}",
11686 "fisubr{l|}",
11687 "fidiv{l|}",
11688 "fidivr{l|}",
11689 /* db */
11690 "fild{l|}",
11691 "fisttp{l|}",
11692 "fist{l|}",
11693 "fistp{l|}",
11694 "(bad)",
11695 "fld{t||t|}",
11696 "(bad)",
11697 "fstp{t||t|}",
11698 /* dc */
11699 "fadd{l|}",
11700 "fmul{l|}",
11701 "fcom{l|}",
11702 "fcomp{l|}",
11703 "fsub{l|}",
11704 "fsubr{l|}",
11705 "fdiv{l|}",
11706 "fdivr{l|}",
11707 /* dd */
11708 "fld{l|}",
11709 "fisttp{ll|}",
11710 "fst{l||}",
11711 "fstp{l|}",
11712 "frstorIC",
11713 "(bad)",
11714 "fNsaveIC",
11715 "fNstsw",
11716 /* de */
11717 "fiadd",
11718 "fimul",
11719 "ficom",
11720 "ficomp",
11721 "fisub",
11722 "fisubr",
11723 "fidiv",
11724 "fidivr",
11725 /* df */
11726 "fild",
11727 "fisttp",
11728 "fist",
11729 "fistp",
11730 "fbld",
11731 "fild{ll|}",
11732 "fbstp",
11733 "fistp{ll|}",
11736 static const unsigned char float_mem_mode[] = {
11737 /* d8 */
11738 d_mode,
11739 d_mode,
11740 d_mode,
11741 d_mode,
11742 d_mode,
11743 d_mode,
11744 d_mode,
11745 d_mode,
11746 /* d9 */
11747 d_mode,
11749 d_mode,
11750 d_mode,
11752 w_mode,
11754 w_mode,
11755 /* da */
11756 d_mode,
11757 d_mode,
11758 d_mode,
11759 d_mode,
11760 d_mode,
11761 d_mode,
11762 d_mode,
11763 d_mode,
11764 /* db */
11765 d_mode,
11766 d_mode,
11767 d_mode,
11768 d_mode,
11770 t_mode,
11772 t_mode,
11773 /* dc */
11774 q_mode,
11775 q_mode,
11776 q_mode,
11777 q_mode,
11778 q_mode,
11779 q_mode,
11780 q_mode,
11781 q_mode,
11782 /* dd */
11783 q_mode,
11784 q_mode,
11785 q_mode,
11786 q_mode,
11790 w_mode,
11791 /* de */
11792 w_mode,
11793 w_mode,
11794 w_mode,
11795 w_mode,
11796 w_mode,
11797 w_mode,
11798 w_mode,
11799 w_mode,
11800 /* df */
11801 w_mode,
11802 w_mode,
11803 w_mode,
11804 w_mode,
11805 t_mode,
11806 q_mode,
11807 t_mode,
11808 q_mode
11811 #define ST { OP_ST, 0 }
11812 #define STi { OP_STi, 0 }
11814 #define FGRPd9_2 NULL, { { NULL, 0 } }
11815 #define FGRPd9_4 NULL, { { NULL, 1 } }
11816 #define FGRPd9_5 NULL, { { NULL, 2 } }
11817 #define FGRPd9_6 NULL, { { NULL, 3 } }
11818 #define FGRPd9_7 NULL, { { NULL, 4 } }
11819 #define FGRPda_5 NULL, { { NULL, 5 } }
11820 #define FGRPdb_4 NULL, { { NULL, 6 } }
11821 #define FGRPde_3 NULL, { { NULL, 7 } }
11822 #define FGRPdf_4 NULL, { { NULL, 8 } }
11824 static const struct dis386 float_reg[][8] = {
11825 /* d8 */
11827 { "fadd", { ST, STi } },
11828 { "fmul", { ST, STi } },
11829 { "fcom", { STi } },
11830 { "fcomp", { STi } },
11831 { "fsub", { ST, STi } },
11832 { "fsubr", { ST, STi } },
11833 { "fdiv", { ST, STi } },
11834 { "fdivr", { ST, STi } },
11836 /* d9 */
11838 { "fld", { STi } },
11839 { "fxch", { STi } },
11840 { FGRPd9_2 },
11841 { Bad_Opcode },
11842 { FGRPd9_4 },
11843 { FGRPd9_5 },
11844 { FGRPd9_6 },
11845 { FGRPd9_7 },
11847 /* da */
11849 { "fcmovb", { ST, STi } },
11850 { "fcmove", { ST, STi } },
11851 { "fcmovbe",{ ST, STi } },
11852 { "fcmovu", { ST, STi } },
11853 { Bad_Opcode },
11854 { FGRPda_5 },
11855 { Bad_Opcode },
11856 { Bad_Opcode },
11858 /* db */
11860 { "fcmovnb",{ ST, STi } },
11861 { "fcmovne",{ ST, STi } },
11862 { "fcmovnbe",{ ST, STi } },
11863 { "fcmovnu",{ ST, STi } },
11864 { FGRPdb_4 },
11865 { "fucomi", { ST, STi } },
11866 { "fcomi", { ST, STi } },
11867 { Bad_Opcode },
11869 /* dc */
11871 { "fadd", { STi, ST } },
11872 { "fmul", { STi, ST } },
11873 { Bad_Opcode },
11874 { Bad_Opcode },
11875 { "fsub!M", { STi, ST } },
11876 { "fsubM", { STi, ST } },
11877 { "fdiv!M", { STi, ST } },
11878 { "fdivM", { STi, ST } },
11880 /* dd */
11882 { "ffree", { STi } },
11883 { Bad_Opcode },
11884 { "fst", { STi } },
11885 { "fstp", { STi } },
11886 { "fucom", { STi } },
11887 { "fucomp", { STi } },
11888 { Bad_Opcode },
11889 { Bad_Opcode },
11891 /* de */
11893 { "faddp", { STi, ST } },
11894 { "fmulp", { STi, ST } },
11895 { Bad_Opcode },
11896 { FGRPde_3 },
11897 { "fsub!Mp", { STi, ST } },
11898 { "fsubMp", { STi, ST } },
11899 { "fdiv!Mp", { STi, ST } },
11900 { "fdivMp", { STi, ST } },
11902 /* df */
11904 { "ffreep", { STi } },
11905 { Bad_Opcode },
11906 { Bad_Opcode },
11907 { Bad_Opcode },
11908 { FGRPdf_4 },
11909 { "fucomip", { ST, STi } },
11910 { "fcomip", { ST, STi } },
11911 { Bad_Opcode },
11915 static char *fgrps[][8] = {
11916 /* d9_2 0 */
11918 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11921 /* d9_4 1 */
11923 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11926 /* d9_5 2 */
11928 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11931 /* d9_6 3 */
11933 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11936 /* d9_7 4 */
11938 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11941 /* da_5 5 */
11943 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11946 /* db_4 6 */
11948 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11949 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11952 /* de_3 7 */
11954 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11957 /* df_4 8 */
11959 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11963 static void
11964 swap_operand (void)
11966 mnemonicendp[0] = '.';
11967 mnemonicendp[1] = 's';
11968 mnemonicendp += 2;
11971 static void
11972 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11973 int sizeflag ATTRIBUTE_UNUSED)
11975 /* Skip mod/rm byte. */
11976 MODRM_CHECK;
11977 codep++;
11980 static void
11981 dofloat (int sizeflag)
11983 const struct dis386 *dp;
11984 unsigned char floatop;
11986 floatop = codep[-1];
11988 if (modrm.mod != 3)
11990 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11992 putop (float_mem[fp_indx], sizeflag);
11993 obufp = op_out[0];
11994 op_ad = 2;
11995 OP_E (float_mem_mode[fp_indx], sizeflag);
11996 return;
11998 /* Skip mod/rm byte. */
11999 MODRM_CHECK;
12000 codep++;
12002 dp = &float_reg[floatop - 0xd8][modrm.reg];
12003 if (dp->name == NULL)
12005 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12007 /* Instruction fnstsw is only one with strange arg. */
12008 if (floatop == 0xdf && codep[-1] == 0xe0)
12009 strcpy (op_out[0], names16[0]);
12011 else
12013 putop (dp->name, sizeflag);
12015 obufp = op_out[0];
12016 op_ad = 2;
12017 if (dp->op[0].rtn)
12018 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12020 obufp = op_out[1];
12021 op_ad = 1;
12022 if (dp->op[1].rtn)
12023 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12027 static void
12028 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12030 oappend ("%st" + intel_syntax);
12033 static void
12034 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12036 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12037 oappend (scratchbuf + intel_syntax);
12040 /* Capital letters in template are macros. */
12041 static int
12042 putop (const char *in_template, int sizeflag)
12044 const char *p;
12045 int alt = 0;
12046 int cond = 1;
12047 unsigned int l = 0, len = 1;
12048 char last[4];
12050 #define SAVE_LAST(c) \
12051 if (l < len && l < sizeof (last)) \
12052 last[l++] = c; \
12053 else \
12054 abort ();
12056 for (p = in_template; *p; p++)
12058 switch (*p)
12060 default:
12061 *obufp++ = *p;
12062 break;
12063 case '%':
12064 len++;
12065 break;
12066 case '!':
12067 cond = 0;
12068 break;
12069 case '{':
12070 alt = 0;
12071 if (intel_syntax)
12073 while (*++p != '|')
12074 if (*p == '}' || *p == '\0')
12075 abort ();
12077 /* Fall through. */
12078 case 'I':
12079 alt = 1;
12080 continue;
12081 case '|':
12082 while (*++p != '}')
12084 if (*p == '\0')
12085 abort ();
12087 break;
12088 case '}':
12089 break;
12090 case 'A':
12091 if (intel_syntax)
12092 break;
12093 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12094 *obufp++ = 'b';
12095 break;
12096 case 'B':
12097 if (l == 0 && len == 1)
12099 case_B:
12100 if (intel_syntax)
12101 break;
12102 if (sizeflag & SUFFIX_ALWAYS)
12103 *obufp++ = 'b';
12105 else
12107 if (l != 1
12108 || len != 2
12109 || last[0] != 'L')
12111 SAVE_LAST (*p);
12112 break;
12115 if (address_mode == mode_64bit
12116 && !(prefixes & PREFIX_ADDR))
12118 *obufp++ = 'a';
12119 *obufp++ = 'b';
12120 *obufp++ = 's';
12123 goto case_B;
12125 break;
12126 case 'C':
12127 if (intel_syntax && !alt)
12128 break;
12129 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12131 if (sizeflag & DFLAG)
12132 *obufp++ = intel_syntax ? 'd' : 'l';
12133 else
12134 *obufp++ = intel_syntax ? 'w' : 's';
12135 used_prefixes |= (prefixes & PREFIX_DATA);
12137 break;
12138 case 'D':
12139 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12140 break;
12141 USED_REX (REX_W);
12142 if (modrm.mod == 3)
12144 if (rex & REX_W)
12145 *obufp++ = 'q';
12146 else
12148 if (sizeflag & DFLAG)
12149 *obufp++ = intel_syntax ? 'd' : 'l';
12150 else
12151 *obufp++ = 'w';
12152 used_prefixes |= (prefixes & PREFIX_DATA);
12155 else
12156 *obufp++ = 'w';
12157 break;
12158 case 'E': /* For jcxz/jecxz */
12159 if (address_mode == mode_64bit)
12161 if (sizeflag & AFLAG)
12162 *obufp++ = 'r';
12163 else
12164 *obufp++ = 'e';
12166 else
12167 if (sizeflag & AFLAG)
12168 *obufp++ = 'e';
12169 used_prefixes |= (prefixes & PREFIX_ADDR);
12170 break;
12171 case 'F':
12172 if (intel_syntax)
12173 break;
12174 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12176 if (sizeflag & AFLAG)
12177 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12178 else
12179 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12180 used_prefixes |= (prefixes & PREFIX_ADDR);
12182 break;
12183 case 'G':
12184 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12185 break;
12186 if ((rex & REX_W) || (sizeflag & DFLAG))
12187 *obufp++ = 'l';
12188 else
12189 *obufp++ = 'w';
12190 if (!(rex & REX_W))
12191 used_prefixes |= (prefixes & PREFIX_DATA);
12192 break;
12193 case 'H':
12194 if (intel_syntax)
12195 break;
12196 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12197 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12199 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12200 *obufp++ = ',';
12201 *obufp++ = 'p';
12202 if (prefixes & PREFIX_DS)
12203 *obufp++ = 't';
12204 else
12205 *obufp++ = 'n';
12207 break;
12208 case 'J':
12209 if (intel_syntax)
12210 break;
12211 *obufp++ = 'l';
12212 break;
12213 case 'K':
12214 USED_REX (REX_W);
12215 if (rex & REX_W)
12216 *obufp++ = 'q';
12217 else
12218 *obufp++ = 'd';
12219 break;
12220 case 'Z':
12221 if (intel_syntax)
12222 break;
12223 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12225 *obufp++ = 'q';
12226 break;
12228 /* Fall through. */
12229 goto case_L;
12230 case 'L':
12231 if (l != 0 || len != 1)
12233 SAVE_LAST (*p);
12234 break;
12236 case_L:
12237 if (intel_syntax)
12238 break;
12239 if (sizeflag & SUFFIX_ALWAYS)
12240 *obufp++ = 'l';
12241 break;
12242 case 'M':
12243 if (intel_mnemonic != cond)
12244 *obufp++ = 'r';
12245 break;
12246 case 'N':
12247 if ((prefixes & PREFIX_FWAIT) == 0)
12248 *obufp++ = 'n';
12249 else
12250 used_prefixes |= PREFIX_FWAIT;
12251 break;
12252 case 'O':
12253 USED_REX (REX_W);
12254 if (rex & REX_W)
12255 *obufp++ = 'o';
12256 else if (intel_syntax && (sizeflag & DFLAG))
12257 *obufp++ = 'q';
12258 else
12259 *obufp++ = 'd';
12260 if (!(rex & REX_W))
12261 used_prefixes |= (prefixes & PREFIX_DATA);
12262 break;
12263 case 'T':
12264 if (intel_syntax)
12265 break;
12266 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12268 *obufp++ = 'q';
12269 break;
12271 /* Fall through. */
12272 case 'P':
12273 if (intel_syntax)
12274 break;
12275 if ((prefixes & PREFIX_DATA)
12276 || (rex & REX_W)
12277 || (sizeflag & SUFFIX_ALWAYS))
12279 USED_REX (REX_W);
12280 if (rex & REX_W)
12281 *obufp++ = 'q';
12282 else
12284 if (sizeflag & DFLAG)
12285 *obufp++ = 'l';
12286 else
12287 *obufp++ = 'w';
12288 used_prefixes |= (prefixes & PREFIX_DATA);
12291 break;
12292 case 'U':
12293 if (intel_syntax)
12294 break;
12295 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12297 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12298 *obufp++ = 'q';
12299 break;
12301 /* Fall through. */
12302 goto case_Q;
12303 case 'Q':
12304 if (l == 0 && len == 1)
12306 case_Q:
12307 if (intel_syntax && !alt)
12308 break;
12309 USED_REX (REX_W);
12310 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12312 if (rex & REX_W)
12313 *obufp++ = 'q';
12314 else
12316 if (sizeflag & DFLAG)
12317 *obufp++ = intel_syntax ? 'd' : 'l';
12318 else
12319 *obufp++ = 'w';
12320 used_prefixes |= (prefixes & PREFIX_DATA);
12324 else
12326 if (l != 1 || len != 2 || last[0] != 'L')
12328 SAVE_LAST (*p);
12329 break;
12331 if (intel_syntax
12332 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12333 break;
12334 if ((rex & REX_W))
12336 USED_REX (REX_W);
12337 *obufp++ = 'q';
12339 else
12340 *obufp++ = 'l';
12342 break;
12343 case 'R':
12344 USED_REX (REX_W);
12345 if (rex & REX_W)
12346 *obufp++ = 'q';
12347 else if (sizeflag & DFLAG)
12349 if (intel_syntax)
12350 *obufp++ = 'd';
12351 else
12352 *obufp++ = 'l';
12354 else
12355 *obufp++ = 'w';
12356 if (intel_syntax && !p[1]
12357 && ((rex & REX_W) || (sizeflag & DFLAG)))
12358 *obufp++ = 'e';
12359 if (!(rex & REX_W))
12360 used_prefixes |= (prefixes & PREFIX_DATA);
12361 break;
12362 case 'V':
12363 if (l == 0 && len == 1)
12365 if (intel_syntax)
12366 break;
12367 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12369 if (sizeflag & SUFFIX_ALWAYS)
12370 *obufp++ = 'q';
12371 break;
12374 else
12376 if (l != 1
12377 || len != 2
12378 || last[0] != 'L')
12380 SAVE_LAST (*p);
12381 break;
12384 if (rex & REX_W)
12386 *obufp++ = 'a';
12387 *obufp++ = 'b';
12388 *obufp++ = 's';
12391 /* Fall through. */
12392 goto case_S;
12393 case 'S':
12394 if (l == 0 && len == 1)
12396 case_S:
12397 if (intel_syntax)
12398 break;
12399 if (sizeflag & SUFFIX_ALWAYS)
12401 if (rex & REX_W)
12402 *obufp++ = 'q';
12403 else
12405 if (sizeflag & DFLAG)
12406 *obufp++ = 'l';
12407 else
12408 *obufp++ = 'w';
12409 used_prefixes |= (prefixes & PREFIX_DATA);
12413 else
12415 if (l != 1
12416 || len != 2
12417 || last[0] != 'L')
12419 SAVE_LAST (*p);
12420 break;
12423 if (address_mode == mode_64bit
12424 && !(prefixes & PREFIX_ADDR))
12426 *obufp++ = 'a';
12427 *obufp++ = 'b';
12428 *obufp++ = 's';
12431 goto case_S;
12433 break;
12434 case 'X':
12435 if (l != 0 || len != 1)
12437 SAVE_LAST (*p);
12438 break;
12440 if (need_vex && vex.prefix)
12442 if (vex.prefix == DATA_PREFIX_OPCODE)
12443 *obufp++ = 'd';
12444 else
12445 *obufp++ = 's';
12447 else
12449 if (prefixes & PREFIX_DATA)
12450 *obufp++ = 'd';
12451 else
12452 *obufp++ = 's';
12453 used_prefixes |= (prefixes & PREFIX_DATA);
12455 break;
12456 case 'Y':
12457 if (l == 0 && len == 1)
12459 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12460 break;
12461 if (rex & REX_W)
12463 USED_REX (REX_W);
12464 *obufp++ = 'q';
12466 break;
12468 else
12470 if (l != 1 || len != 2 || last[0] != 'X')
12472 SAVE_LAST (*p);
12473 break;
12475 if (!need_vex)
12476 abort ();
12477 if (intel_syntax
12478 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12479 break;
12480 switch (vex.length)
12482 case 128:
12483 *obufp++ = 'x';
12484 break;
12485 case 256:
12486 *obufp++ = 'y';
12487 break;
12488 default:
12489 abort ();
12492 break;
12493 case 'W':
12494 if (l == 0 && len == 1)
12496 /* operand size flag for cwtl, cbtw */
12497 USED_REX (REX_W);
12498 if (rex & REX_W)
12500 if (intel_syntax)
12501 *obufp++ = 'd';
12502 else
12503 *obufp++ = 'l';
12505 else if (sizeflag & DFLAG)
12506 *obufp++ = 'w';
12507 else
12508 *obufp++ = 'b';
12509 if (!(rex & REX_W))
12510 used_prefixes |= (prefixes & PREFIX_DATA);
12512 else
12514 if (l != 1 || len != 2 || last[0] != 'X')
12516 SAVE_LAST (*p);
12517 break;
12519 if (!need_vex)
12520 abort ();
12521 *obufp++ = vex.w ? 'd': 's';
12523 break;
12525 alt = 0;
12527 *obufp = 0;
12528 mnemonicendp = obufp;
12529 return 0;
12532 static void
12533 oappend (const char *s)
12535 obufp = stpcpy (obufp, s);
12538 static void
12539 append_seg (void)
12541 if (prefixes & PREFIX_CS)
12543 used_prefixes |= PREFIX_CS;
12544 oappend ("%cs:" + intel_syntax);
12546 if (prefixes & PREFIX_DS)
12548 used_prefixes |= PREFIX_DS;
12549 oappend ("%ds:" + intel_syntax);
12551 if (prefixes & PREFIX_SS)
12553 used_prefixes |= PREFIX_SS;
12554 oappend ("%ss:" + intel_syntax);
12556 if (prefixes & PREFIX_ES)
12558 used_prefixes |= PREFIX_ES;
12559 oappend ("%es:" + intel_syntax);
12561 if (prefixes & PREFIX_FS)
12563 used_prefixes |= PREFIX_FS;
12564 oappend ("%fs:" + intel_syntax);
12566 if (prefixes & PREFIX_GS)
12568 used_prefixes |= PREFIX_GS;
12569 oappend ("%gs:" + intel_syntax);
12573 static void
12574 OP_indirE (int bytemode, int sizeflag)
12576 if (!intel_syntax)
12577 oappend ("*");
12578 OP_E (bytemode, sizeflag);
12581 static void
12582 print_operand_value (char *buf, int hex, bfd_vma disp)
12584 if (address_mode == mode_64bit)
12586 if (hex)
12588 char tmp[30];
12589 int i;
12590 buf[0] = '0';
12591 buf[1] = 'x';
12592 sprintf_vma (tmp, disp);
12593 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12594 strcpy (buf + 2, tmp + i);
12596 else
12598 bfd_signed_vma v = disp;
12599 char tmp[30];
12600 int i;
12601 if (v < 0)
12603 *(buf++) = '-';
12604 v = -disp;
12605 /* Check for possible overflow on 0x8000000000000000. */
12606 if (v < 0)
12608 strcpy (buf, "9223372036854775808");
12609 return;
12612 if (!v)
12614 strcpy (buf, "0");
12615 return;
12618 i = 0;
12619 tmp[29] = 0;
12620 while (v)
12622 tmp[28 - i] = (v % 10) + '0';
12623 v /= 10;
12624 i++;
12626 strcpy (buf, tmp + 29 - i);
12629 else
12631 if (hex)
12632 sprintf (buf, "0x%x", (unsigned int) disp);
12633 else
12634 sprintf (buf, "%d", (int) disp);
12638 /* Put DISP in BUF as signed hex number. */
12640 static void
12641 print_displacement (char *buf, bfd_vma disp)
12643 bfd_signed_vma val = disp;
12644 char tmp[30];
12645 int i, j = 0;
12647 if (val < 0)
12649 buf[j++] = '-';
12650 val = -disp;
12652 /* Check for possible overflow. */
12653 if (val < 0)
12655 switch (address_mode)
12657 case mode_64bit:
12658 strcpy (buf + j, "0x8000000000000000");
12659 break;
12660 case mode_32bit:
12661 strcpy (buf + j, "0x80000000");
12662 break;
12663 case mode_16bit:
12664 strcpy (buf + j, "0x8000");
12665 break;
12667 return;
12671 buf[j++] = '0';
12672 buf[j++] = 'x';
12674 sprintf_vma (tmp, (bfd_vma) val);
12675 for (i = 0; tmp[i] == '0'; i++)
12676 continue;
12677 if (tmp[i] == '\0')
12678 i--;
12679 strcpy (buf + j, tmp + i);
12682 static void
12683 intel_operand_size (int bytemode, int sizeflag)
12685 switch (bytemode)
12687 case b_mode:
12688 case b_swap_mode:
12689 case dqb_mode:
12690 oappend ("BYTE PTR ");
12691 break;
12692 case w_mode:
12693 case dqw_mode:
12694 oappend ("WORD PTR ");
12695 break;
12696 case stack_v_mode:
12697 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12699 oappend ("QWORD PTR ");
12700 break;
12702 /* FALLTHRU */
12703 case v_mode:
12704 case v_swap_mode:
12705 case dq_mode:
12706 USED_REX (REX_W);
12707 if (rex & REX_W)
12708 oappend ("QWORD PTR ");
12709 else
12711 if ((sizeflag & DFLAG) || bytemode == dq_mode)
12712 oappend ("DWORD PTR ");
12713 else
12714 oappend ("WORD PTR ");
12715 used_prefixes |= (prefixes & PREFIX_DATA);
12717 break;
12718 case z_mode:
12719 if ((rex & REX_W) || (sizeflag & DFLAG))
12720 *obufp++ = 'D';
12721 oappend ("WORD PTR ");
12722 if (!(rex & REX_W))
12723 used_prefixes |= (prefixes & PREFIX_DATA);
12724 break;
12725 case a_mode:
12726 if (sizeflag & DFLAG)
12727 oappend ("QWORD PTR ");
12728 else
12729 oappend ("DWORD PTR ");
12730 used_prefixes |= (prefixes & PREFIX_DATA);
12731 break;
12732 case d_mode:
12733 case d_scalar_mode:
12734 case d_scalar_swap_mode:
12735 case d_swap_mode:
12736 case dqd_mode:
12737 oappend ("DWORD PTR ");
12738 break;
12739 case q_mode:
12740 case q_scalar_mode:
12741 case q_scalar_swap_mode:
12742 case q_swap_mode:
12743 oappend ("QWORD PTR ");
12744 break;
12745 case m_mode:
12746 if (address_mode == mode_64bit)
12747 oappend ("QWORD PTR ");
12748 else
12749 oappend ("DWORD PTR ");
12750 break;
12751 case f_mode:
12752 if (sizeflag & DFLAG)
12753 oappend ("FWORD PTR ");
12754 else
12755 oappend ("DWORD PTR ");
12756 used_prefixes |= (prefixes & PREFIX_DATA);
12757 break;
12758 case t_mode:
12759 oappend ("TBYTE PTR ");
12760 break;
12761 case x_mode:
12762 case x_swap_mode:
12763 if (need_vex)
12765 switch (vex.length)
12767 case 128:
12768 oappend ("XMMWORD PTR ");
12769 break;
12770 case 256:
12771 oappend ("YMMWORD PTR ");
12772 break;
12773 default:
12774 abort ();
12777 else
12778 oappend ("XMMWORD PTR ");
12779 break;
12780 case xmm_mode:
12781 oappend ("XMMWORD PTR ");
12782 break;
12783 case xmmq_mode:
12784 if (!need_vex)
12785 abort ();
12787 switch (vex.length)
12789 case 128:
12790 oappend ("QWORD PTR ");
12791 break;
12792 case 256:
12793 oappend ("XMMWORD PTR ");
12794 break;
12795 default:
12796 abort ();
12798 break;
12799 case ymmq_mode:
12800 if (!need_vex)
12801 abort ();
12803 switch (vex.length)
12805 case 128:
12806 oappend ("QWORD PTR ");
12807 break;
12808 case 256:
12809 oappend ("YMMWORD PTR ");
12810 break;
12811 default:
12812 abort ();
12814 break;
12815 case o_mode:
12816 oappend ("OWORD PTR ");
12817 break;
12818 case vex_w_dq_mode:
12819 case vex_scalar_w_dq_mode:
12820 if (!need_vex)
12821 abort ();
12823 if (vex.w)
12824 oappend ("QWORD PTR ");
12825 else
12826 oappend ("DWORD PTR ");
12827 break;
12828 default:
12829 break;
12833 static void
12834 OP_E_register (int bytemode, int sizeflag)
12836 int reg = modrm.rm;
12837 const char **names;
12839 USED_REX (REX_B);
12840 if ((rex & REX_B))
12841 reg += 8;
12843 if ((sizeflag & SUFFIX_ALWAYS)
12844 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12845 swap_operand ();
12847 switch (bytemode)
12849 case b_mode:
12850 case b_swap_mode:
12851 USED_REX (0);
12852 if (rex)
12853 names = names8rex;
12854 else
12855 names = names8;
12856 break;
12857 case w_mode:
12858 names = names16;
12859 break;
12860 case d_mode:
12861 names = names32;
12862 break;
12863 case q_mode:
12864 names = names64;
12865 break;
12866 case m_mode:
12867 names = address_mode == mode_64bit ? names64 : names32;
12868 break;
12869 case stack_v_mode:
12870 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12872 names = names64;
12873 break;
12875 bytemode = v_mode;
12876 /* FALLTHRU */
12877 case v_mode:
12878 case v_swap_mode:
12879 case dq_mode:
12880 case dqb_mode:
12881 case dqd_mode:
12882 case dqw_mode:
12883 USED_REX (REX_W);
12884 if (rex & REX_W)
12885 names = names64;
12886 else
12888 if ((sizeflag & DFLAG)
12889 || (bytemode != v_mode
12890 && bytemode != v_swap_mode))
12891 names = names32;
12892 else
12893 names = names16;
12894 used_prefixes |= (prefixes & PREFIX_DATA);
12896 break;
12897 case 0:
12898 return;
12899 default:
12900 oappend (INTERNAL_DISASSEMBLER_ERROR);
12901 return;
12903 oappend (names[reg]);
12906 static void
12907 OP_E_memory (int bytemode, int sizeflag)
12909 bfd_vma disp = 0;
12910 int add = (rex & REX_B) ? 8 : 0;
12911 int riprel = 0;
12913 USED_REX (REX_B);
12914 if (intel_syntax)
12915 intel_operand_size (bytemode, sizeflag);
12916 append_seg ();
12918 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12920 /* 32/64 bit address mode */
12921 int havedisp;
12922 int havesib;
12923 int havebase;
12924 int haveindex;
12925 int needindex;
12926 int base, rbase;
12927 int vindex = 0;
12928 int scale = 0;
12930 havesib = 0;
12931 havebase = 1;
12932 haveindex = 0;
12933 base = modrm.rm;
12935 if (base == 4)
12937 havesib = 1;
12938 FETCH_DATA (the_info, codep + 1);
12939 vindex = (*codep >> 3) & 7;
12940 scale = (*codep >> 6) & 3;
12941 base = *codep & 7;
12942 USED_REX (REX_X);
12943 if (rex & REX_X)
12944 vindex += 8;
12945 haveindex = vindex != 4;
12946 codep++;
12948 rbase = base + add;
12950 switch (modrm.mod)
12952 case 0:
12953 if (base == 5)
12955 havebase = 0;
12956 if (address_mode == mode_64bit && !havesib)
12957 riprel = 1;
12958 disp = get32s ();
12960 break;
12961 case 1:
12962 FETCH_DATA (the_info, codep + 1);
12963 disp = *codep++;
12964 if ((disp & 0x80) != 0)
12965 disp -= 0x100;
12966 break;
12967 case 2:
12968 disp = get32s ();
12969 break;
12972 /* In 32bit mode, we need index register to tell [offset] from
12973 [eiz*1 + offset]. */
12974 needindex = (havesib
12975 && !havebase
12976 && !haveindex
12977 && address_mode == mode_32bit);
12978 havedisp = (havebase
12979 || needindex
12980 || (havesib && (haveindex || scale != 0)));
12982 if (!intel_syntax)
12983 if (modrm.mod != 0 || base == 5)
12985 if (havedisp || riprel)
12986 print_displacement (scratchbuf, disp);
12987 else
12988 print_operand_value (scratchbuf, 1, disp);
12989 oappend (scratchbuf);
12990 if (riprel)
12992 set_op (disp, 1);
12993 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12997 if (havebase || haveindex || riprel)
12998 used_prefixes |= PREFIX_ADDR;
13000 if (havedisp || (intel_syntax && riprel))
13002 *obufp++ = open_char;
13003 if (intel_syntax && riprel)
13005 set_op (disp, 1);
13006 oappend (sizeflag & AFLAG ? "rip" : "eip");
13008 *obufp = '\0';
13009 if (havebase)
13010 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13011 ? names64[rbase] : names32[rbase]);
13012 if (havesib)
13014 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13015 print index to tell base + index from base. */
13016 if (scale != 0
13017 || needindex
13018 || haveindex
13019 || (havebase && base != ESP_REG_NUM))
13021 if (!intel_syntax || havebase)
13023 *obufp++ = separator_char;
13024 *obufp = '\0';
13026 if (haveindex)
13027 oappend (address_mode == mode_64bit
13028 && (sizeflag & AFLAG)
13029 ? names64[vindex] : names32[vindex]);
13030 else
13031 oappend (address_mode == mode_64bit
13032 && (sizeflag & AFLAG)
13033 ? index64 : index32);
13035 *obufp++ = scale_char;
13036 *obufp = '\0';
13037 sprintf (scratchbuf, "%d", 1 << scale);
13038 oappend (scratchbuf);
13041 if (intel_syntax
13042 && (disp || modrm.mod != 0 || base == 5))
13044 if (!havedisp || (bfd_signed_vma) disp >= 0)
13046 *obufp++ = '+';
13047 *obufp = '\0';
13049 else if (modrm.mod != 1 && disp != -disp)
13051 *obufp++ = '-';
13052 *obufp = '\0';
13053 disp = - (bfd_signed_vma) disp;
13056 if (havedisp)
13057 print_displacement (scratchbuf, disp);
13058 else
13059 print_operand_value (scratchbuf, 1, disp);
13060 oappend (scratchbuf);
13063 *obufp++ = close_char;
13064 *obufp = '\0';
13066 else if (intel_syntax)
13068 if (modrm.mod != 0 || base == 5)
13070 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13071 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13073 else
13075 oappend (names_seg[ds_reg - es_reg]);
13076 oappend (":");
13078 print_operand_value (scratchbuf, 1, disp);
13079 oappend (scratchbuf);
13083 else
13085 /* 16 bit address mode */
13086 used_prefixes |= prefixes & PREFIX_ADDR;
13087 switch (modrm.mod)
13089 case 0:
13090 if (modrm.rm == 6)
13092 disp = get16 ();
13093 if ((disp & 0x8000) != 0)
13094 disp -= 0x10000;
13096 break;
13097 case 1:
13098 FETCH_DATA (the_info, codep + 1);
13099 disp = *codep++;
13100 if ((disp & 0x80) != 0)
13101 disp -= 0x100;
13102 break;
13103 case 2:
13104 disp = get16 ();
13105 if ((disp & 0x8000) != 0)
13106 disp -= 0x10000;
13107 break;
13110 if (!intel_syntax)
13111 if (modrm.mod != 0 || modrm.rm == 6)
13113 print_displacement (scratchbuf, disp);
13114 oappend (scratchbuf);
13117 if (modrm.mod != 0 || modrm.rm != 6)
13119 *obufp++ = open_char;
13120 *obufp = '\0';
13121 oappend (index16[modrm.rm]);
13122 if (intel_syntax
13123 && (disp || modrm.mod != 0 || modrm.rm == 6))
13125 if ((bfd_signed_vma) disp >= 0)
13127 *obufp++ = '+';
13128 *obufp = '\0';
13130 else if (modrm.mod != 1)
13132 *obufp++ = '-';
13133 *obufp = '\0';
13134 disp = - (bfd_signed_vma) disp;
13137 print_displacement (scratchbuf, disp);
13138 oappend (scratchbuf);
13141 *obufp++ = close_char;
13142 *obufp = '\0';
13144 else if (intel_syntax)
13146 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13147 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13149 else
13151 oappend (names_seg[ds_reg - es_reg]);
13152 oappend (":");
13154 print_operand_value (scratchbuf, 1, disp & 0xffff);
13155 oappend (scratchbuf);
13160 static void
13161 OP_E (int bytemode, int sizeflag)
13163 /* Skip mod/rm byte. */
13164 MODRM_CHECK;
13165 codep++;
13167 if (modrm.mod == 3)
13168 OP_E_register (bytemode, sizeflag);
13169 else
13170 OP_E_memory (bytemode, sizeflag);
13173 static void
13174 OP_G (int bytemode, int sizeflag)
13176 int add = 0;
13177 USED_REX (REX_R);
13178 if (rex & REX_R)
13179 add += 8;
13180 switch (bytemode)
13182 case b_mode:
13183 USED_REX (0);
13184 if (rex)
13185 oappend (names8rex[modrm.reg + add]);
13186 else
13187 oappend (names8[modrm.reg + add]);
13188 break;
13189 case w_mode:
13190 oappend (names16[modrm.reg + add]);
13191 break;
13192 case d_mode:
13193 oappend (names32[modrm.reg + add]);
13194 break;
13195 case q_mode:
13196 oappend (names64[modrm.reg + add]);
13197 break;
13198 case v_mode:
13199 case dq_mode:
13200 case dqb_mode:
13201 case dqd_mode:
13202 case dqw_mode:
13203 USED_REX (REX_W);
13204 if (rex & REX_W)
13205 oappend (names64[modrm.reg + add]);
13206 else
13208 if ((sizeflag & DFLAG) || bytemode != v_mode)
13209 oappend (names32[modrm.reg + add]);
13210 else
13211 oappend (names16[modrm.reg + add]);
13212 used_prefixes |= (prefixes & PREFIX_DATA);
13214 break;
13215 case m_mode:
13216 if (address_mode == mode_64bit)
13217 oappend (names64[modrm.reg + add]);
13218 else
13219 oappend (names32[modrm.reg + add]);
13220 break;
13221 default:
13222 oappend (INTERNAL_DISASSEMBLER_ERROR);
13223 break;
13227 static bfd_vma
13228 get64 (void)
13230 bfd_vma x;
13231 #ifdef BFD64
13232 unsigned int a;
13233 unsigned int b;
13235 FETCH_DATA (the_info, codep + 8);
13236 a = *codep++ & 0xff;
13237 a |= (*codep++ & 0xff) << 8;
13238 a |= (*codep++ & 0xff) << 16;
13239 a |= (*codep++ & 0xff) << 24;
13240 b = *codep++ & 0xff;
13241 b |= (*codep++ & 0xff) << 8;
13242 b |= (*codep++ & 0xff) << 16;
13243 b |= (*codep++ & 0xff) << 24;
13244 x = a + ((bfd_vma) b << 32);
13245 #else
13246 abort ();
13247 x = 0;
13248 #endif
13249 return x;
13252 static bfd_signed_vma
13253 get32 (void)
13255 bfd_signed_vma x = 0;
13257 FETCH_DATA (the_info, codep + 4);
13258 x = *codep++ & (bfd_signed_vma) 0xff;
13259 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13260 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13261 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13262 return x;
13265 static bfd_signed_vma
13266 get32s (void)
13268 bfd_signed_vma x = 0;
13270 FETCH_DATA (the_info, codep + 4);
13271 x = *codep++ & (bfd_signed_vma) 0xff;
13272 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13273 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13274 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13276 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13278 return x;
13281 static int
13282 get16 (void)
13284 int x = 0;
13286 FETCH_DATA (the_info, codep + 2);
13287 x = *codep++ & 0xff;
13288 x |= (*codep++ & 0xff) << 8;
13289 return x;
13292 static void
13293 set_op (bfd_vma op, int riprel)
13295 op_index[op_ad] = op_ad;
13296 if (address_mode == mode_64bit)
13298 op_address[op_ad] = op;
13299 op_riprel[op_ad] = riprel;
13301 else
13303 /* Mask to get a 32-bit address. */
13304 op_address[op_ad] = op & 0xffffffff;
13305 op_riprel[op_ad] = riprel & 0xffffffff;
13309 static void
13310 OP_REG (int code, int sizeflag)
13312 const char *s;
13313 int add;
13314 USED_REX (REX_B);
13315 if (rex & REX_B)
13316 add = 8;
13317 else
13318 add = 0;
13320 switch (code)
13322 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13323 case sp_reg: case bp_reg: case si_reg: case di_reg:
13324 s = names16[code - ax_reg + add];
13325 break;
13326 case es_reg: case ss_reg: case cs_reg:
13327 case ds_reg: case fs_reg: case gs_reg:
13328 s = names_seg[code - es_reg + add];
13329 break;
13330 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13331 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13332 USED_REX (0);
13333 if (rex)
13334 s = names8rex[code - al_reg + add];
13335 else
13336 s = names8[code - al_reg];
13337 break;
13338 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13339 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13340 if (address_mode == mode_64bit && (sizeflag & DFLAG))
13342 s = names64[code - rAX_reg + add];
13343 break;
13345 code += eAX_reg - rAX_reg;
13346 /* Fall through. */
13347 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13348 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13349 USED_REX (REX_W);
13350 if (rex & REX_W)
13351 s = names64[code - eAX_reg + add];
13352 else
13354 if (sizeflag & DFLAG)
13355 s = names32[code - eAX_reg + add];
13356 else
13357 s = names16[code - eAX_reg + add];
13358 used_prefixes |= (prefixes & PREFIX_DATA);
13360 break;
13361 default:
13362 s = INTERNAL_DISASSEMBLER_ERROR;
13363 break;
13365 oappend (s);
13368 static void
13369 OP_IMREG (int code, int sizeflag)
13371 const char *s;
13373 switch (code)
13375 case indir_dx_reg:
13376 if (intel_syntax)
13377 s = "dx";
13378 else
13379 s = "(%dx)";
13380 break;
13381 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13382 case sp_reg: case bp_reg: case si_reg: case di_reg:
13383 s = names16[code - ax_reg];
13384 break;
13385 case es_reg: case ss_reg: case cs_reg:
13386 case ds_reg: case fs_reg: case gs_reg:
13387 s = names_seg[code - es_reg];
13388 break;
13389 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13390 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13391 USED_REX (0);
13392 if (rex)
13393 s = names8rex[code - al_reg];
13394 else
13395 s = names8[code - al_reg];
13396 break;
13397 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13398 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13399 USED_REX (REX_W);
13400 if (rex & REX_W)
13401 s = names64[code - eAX_reg];
13402 else
13404 if (sizeflag & DFLAG)
13405 s = names32[code - eAX_reg];
13406 else
13407 s = names16[code - eAX_reg];
13408 used_prefixes |= (prefixes & PREFIX_DATA);
13410 break;
13411 case z_mode_ax_reg:
13412 if ((rex & REX_W) || (sizeflag & DFLAG))
13413 s = *names32;
13414 else
13415 s = *names16;
13416 if (!(rex & REX_W))
13417 used_prefixes |= (prefixes & PREFIX_DATA);
13418 break;
13419 default:
13420 s = INTERNAL_DISASSEMBLER_ERROR;
13421 break;
13423 oappend (s);
13426 static void
13427 OP_I (int bytemode, int sizeflag)
13429 bfd_signed_vma op;
13430 bfd_signed_vma mask = -1;
13432 switch (bytemode)
13434 case b_mode:
13435 FETCH_DATA (the_info, codep + 1);
13436 op = *codep++;
13437 mask = 0xff;
13438 break;
13439 case q_mode:
13440 if (address_mode == mode_64bit)
13442 op = get32s ();
13443 break;
13445 /* Fall through. */
13446 case v_mode:
13447 USED_REX (REX_W);
13448 if (rex & REX_W)
13449 op = get32s ();
13450 else
13452 if (sizeflag & DFLAG)
13454 op = get32 ();
13455 mask = 0xffffffff;
13457 else
13459 op = get16 ();
13460 mask = 0xfffff;
13462 used_prefixes |= (prefixes & PREFIX_DATA);
13464 break;
13465 case w_mode:
13466 mask = 0xfffff;
13467 op = get16 ();
13468 break;
13469 case const_1_mode:
13470 if (intel_syntax)
13471 oappend ("1");
13472 return;
13473 default:
13474 oappend (INTERNAL_DISASSEMBLER_ERROR);
13475 return;
13478 op &= mask;
13479 scratchbuf[0] = '$';
13480 print_operand_value (scratchbuf + 1, 1, op);
13481 oappend (scratchbuf + intel_syntax);
13482 scratchbuf[0] = '\0';
13485 static void
13486 OP_I64 (int bytemode, int sizeflag)
13488 bfd_signed_vma op;
13489 bfd_signed_vma mask = -1;
13491 if (address_mode != mode_64bit)
13493 OP_I (bytemode, sizeflag);
13494 return;
13497 switch (bytemode)
13499 case b_mode:
13500 FETCH_DATA (the_info, codep + 1);
13501 op = *codep++;
13502 mask = 0xff;
13503 break;
13504 case v_mode:
13505 USED_REX (REX_W);
13506 if (rex & REX_W)
13507 op = get64 ();
13508 else
13510 if (sizeflag & DFLAG)
13512 op = get32 ();
13513 mask = 0xffffffff;
13515 else
13517 op = get16 ();
13518 mask = 0xfffff;
13520 used_prefixes |= (prefixes & PREFIX_DATA);
13522 break;
13523 case w_mode:
13524 mask = 0xfffff;
13525 op = get16 ();
13526 break;
13527 default:
13528 oappend (INTERNAL_DISASSEMBLER_ERROR);
13529 return;
13532 op &= mask;
13533 scratchbuf[0] = '$';
13534 print_operand_value (scratchbuf + 1, 1, op);
13535 oappend (scratchbuf + intel_syntax);
13536 scratchbuf[0] = '\0';
13539 static void
13540 OP_sI (int bytemode, int sizeflag)
13542 bfd_signed_vma op;
13544 switch (bytemode)
13546 case b_mode:
13547 FETCH_DATA (the_info, codep + 1);
13548 op = *codep++;
13549 if ((op & 0x80) != 0)
13550 op -= 0x100;
13551 break;
13552 case v_mode:
13553 USED_REX (REX_W);
13554 if (rex & REX_W)
13555 op = get32s ();
13556 else
13558 if (sizeflag & DFLAG)
13560 op = get32s ();
13562 else
13564 op = get16 ();
13565 if ((op & 0x8000) != 0)
13566 op -= 0x10000;
13568 used_prefixes |= (prefixes & PREFIX_DATA);
13570 break;
13571 case w_mode:
13572 op = get16 ();
13573 if ((op & 0x8000) != 0)
13574 op -= 0x10000;
13575 break;
13576 default:
13577 oappend (INTERNAL_DISASSEMBLER_ERROR);
13578 return;
13581 scratchbuf[0] = '$';
13582 print_operand_value (scratchbuf + 1, 1, op);
13583 oappend (scratchbuf + intel_syntax);
13586 static void
13587 OP_J (int bytemode, int sizeflag)
13589 bfd_vma disp;
13590 bfd_vma mask = -1;
13591 bfd_vma segment = 0;
13593 switch (bytemode)
13595 case b_mode:
13596 FETCH_DATA (the_info, codep + 1);
13597 disp = *codep++;
13598 if ((disp & 0x80) != 0)
13599 disp -= 0x100;
13600 break;
13601 case v_mode:
13602 USED_REX (REX_W);
13603 if ((sizeflag & DFLAG) || (rex & REX_W))
13604 disp = get32s ();
13605 else
13607 disp = get16 ();
13608 if ((disp & 0x8000) != 0)
13609 disp -= 0x10000;
13610 /* In 16bit mode, address is wrapped around at 64k within
13611 the same segment. Otherwise, a data16 prefix on a jump
13612 instruction means that the pc is masked to 16 bits after
13613 the displacement is added! */
13614 mask = 0xffff;
13615 if ((prefixes & PREFIX_DATA) == 0)
13616 segment = ((start_pc + codep - start_codep)
13617 & ~((bfd_vma) 0xffff));
13619 if (!(rex & REX_W))
13620 used_prefixes |= (prefixes & PREFIX_DATA);
13621 break;
13622 default:
13623 oappend (INTERNAL_DISASSEMBLER_ERROR);
13624 return;
13626 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13627 set_op (disp, 0);
13628 print_operand_value (scratchbuf, 1, disp);
13629 oappend (scratchbuf);
13632 static void
13633 OP_SEG (int bytemode, int sizeflag)
13635 if (bytemode == w_mode)
13636 oappend (names_seg[modrm.reg]);
13637 else
13638 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13641 static void
13642 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13644 int seg, offset;
13646 if (sizeflag & DFLAG)
13648 offset = get32 ();
13649 seg = get16 ();
13651 else
13653 offset = get16 ();
13654 seg = get16 ();
13656 used_prefixes |= (prefixes & PREFIX_DATA);
13657 if (intel_syntax)
13658 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13659 else
13660 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13661 oappend (scratchbuf);
13664 static void
13665 OP_OFF (int bytemode, int sizeflag)
13667 bfd_vma off;
13669 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13670 intel_operand_size (bytemode, sizeflag);
13671 append_seg ();
13673 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13674 off = get32 ();
13675 else
13676 off = get16 ();
13678 if (intel_syntax)
13680 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13681 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13683 oappend (names_seg[ds_reg - es_reg]);
13684 oappend (":");
13687 print_operand_value (scratchbuf, 1, off);
13688 oappend (scratchbuf);
13691 static void
13692 OP_OFF64 (int bytemode, int sizeflag)
13694 bfd_vma off;
13696 if (address_mode != mode_64bit
13697 || (prefixes & PREFIX_ADDR))
13699 OP_OFF (bytemode, sizeflag);
13700 return;
13703 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13704 intel_operand_size (bytemode, sizeflag);
13705 append_seg ();
13707 off = get64 ();
13709 if (intel_syntax)
13711 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13712 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13714 oappend (names_seg[ds_reg - es_reg]);
13715 oappend (":");
13718 print_operand_value (scratchbuf, 1, off);
13719 oappend (scratchbuf);
13722 static void
13723 ptr_reg (int code, int sizeflag)
13725 const char *s;
13727 *obufp++ = open_char;
13728 used_prefixes |= (prefixes & PREFIX_ADDR);
13729 if (address_mode == mode_64bit)
13731 if (!(sizeflag & AFLAG))
13732 s = names32[code - eAX_reg];
13733 else
13734 s = names64[code - eAX_reg];
13736 else if (sizeflag & AFLAG)
13737 s = names32[code - eAX_reg];
13738 else
13739 s = names16[code - eAX_reg];
13740 oappend (s);
13741 *obufp++ = close_char;
13742 *obufp = 0;
13745 static void
13746 OP_ESreg (int code, int sizeflag)
13748 if (intel_syntax)
13750 switch (codep[-1])
13752 case 0x6d: /* insw/insl */
13753 intel_operand_size (z_mode, sizeflag);
13754 break;
13755 case 0xa5: /* movsw/movsl/movsq */
13756 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13757 case 0xab: /* stosw/stosl */
13758 case 0xaf: /* scasw/scasl */
13759 intel_operand_size (v_mode, sizeflag);
13760 break;
13761 default:
13762 intel_operand_size (b_mode, sizeflag);
13765 oappend ("%es:" + intel_syntax);
13766 ptr_reg (code, sizeflag);
13769 static void
13770 OP_DSreg (int code, int sizeflag)
13772 if (intel_syntax)
13774 switch (codep[-1])
13776 case 0x6f: /* outsw/outsl */
13777 intel_operand_size (z_mode, sizeflag);
13778 break;
13779 case 0xa5: /* movsw/movsl/movsq */
13780 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13781 case 0xad: /* lodsw/lodsl/lodsq */
13782 intel_operand_size (v_mode, sizeflag);
13783 break;
13784 default:
13785 intel_operand_size (b_mode, sizeflag);
13788 if ((prefixes
13789 & (PREFIX_CS
13790 | PREFIX_DS
13791 | PREFIX_SS
13792 | PREFIX_ES
13793 | PREFIX_FS
13794 | PREFIX_GS)) == 0)
13795 prefixes |= PREFIX_DS;
13796 append_seg ();
13797 ptr_reg (code, sizeflag);
13800 static void
13801 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13803 int add;
13804 if (rex & REX_R)
13806 USED_REX (REX_R);
13807 add = 8;
13809 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13811 all_prefixes[last_lock_prefix] = 0;
13812 used_prefixes |= PREFIX_LOCK;
13813 add = 8;
13815 else
13816 add = 0;
13817 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13818 oappend (scratchbuf + intel_syntax);
13821 static void
13822 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13824 int add;
13825 USED_REX (REX_R);
13826 if (rex & REX_R)
13827 add = 8;
13828 else
13829 add = 0;
13830 if (intel_syntax)
13831 sprintf (scratchbuf, "db%d", modrm.reg + add);
13832 else
13833 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13834 oappend (scratchbuf);
13837 static void
13838 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13840 sprintf (scratchbuf, "%%tr%d", modrm.reg);
13841 oappend (scratchbuf + intel_syntax);
13844 static void
13845 OP_R (int bytemode, int sizeflag)
13847 if (modrm.mod == 3)
13848 OP_E (bytemode, sizeflag);
13849 else
13850 BadOp ();
13853 static void
13854 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13856 int reg = modrm.reg;
13857 const char **names;
13859 used_prefixes |= (prefixes & PREFIX_DATA);
13860 if (prefixes & PREFIX_DATA)
13862 names = names_xmm;
13863 USED_REX (REX_R);
13864 if (rex & REX_R)
13865 reg += 8;
13867 else
13868 names = names_mm;
13869 oappend (names[reg]);
13872 static void
13873 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13875 int reg = modrm.reg;
13876 const char **names;
13878 USED_REX (REX_R);
13879 if (rex & REX_R)
13880 reg += 8;
13881 if (need_vex
13882 && bytemode != xmm_mode
13883 && bytemode != scalar_mode)
13885 switch (vex.length)
13887 case 128:
13888 names = names_xmm;
13889 break;
13890 case 256:
13891 names = names_ymm;
13892 break;
13893 default:
13894 abort ();
13897 else
13898 names = names_xmm;
13899 oappend (names[reg]);
13902 static void
13903 OP_EM (int bytemode, int sizeflag)
13905 int reg;
13906 const char **names;
13908 if (modrm.mod != 3)
13910 if (intel_syntax
13911 && (bytemode == v_mode || bytemode == v_swap_mode))
13913 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13914 used_prefixes |= (prefixes & PREFIX_DATA);
13916 OP_E (bytemode, sizeflag);
13917 return;
13920 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13921 swap_operand ();
13923 /* Skip mod/rm byte. */
13924 MODRM_CHECK;
13925 codep++;
13926 used_prefixes |= (prefixes & PREFIX_DATA);
13927 reg = modrm.rm;
13928 if (prefixes & PREFIX_DATA)
13930 names = names_xmm;
13931 USED_REX (REX_B);
13932 if (rex & REX_B)
13933 reg += 8;
13935 else
13936 names = names_mm;
13937 oappend (names[reg]);
13940 /* cvt* are the only instructions in sse2 which have
13941 both SSE and MMX operands and also have 0x66 prefix
13942 in their opcode. 0x66 was originally used to differentiate
13943 between SSE and MMX instruction(operands). So we have to handle the
13944 cvt* separately using OP_EMC and OP_MXC */
13945 static void
13946 OP_EMC (int bytemode, int sizeflag)
13948 if (modrm.mod != 3)
13950 if (intel_syntax && bytemode == v_mode)
13952 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13953 used_prefixes |= (prefixes & PREFIX_DATA);
13955 OP_E (bytemode, sizeflag);
13956 return;
13959 /* Skip mod/rm byte. */
13960 MODRM_CHECK;
13961 codep++;
13962 used_prefixes |= (prefixes & PREFIX_DATA);
13963 oappend (names_mm[modrm.rm]);
13966 static void
13967 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13969 used_prefixes |= (prefixes & PREFIX_DATA);
13970 oappend (names_mm[modrm.reg]);
13973 static void
13974 OP_EX (int bytemode, int sizeflag)
13976 int reg;
13977 const char **names;
13979 /* Skip mod/rm byte. */
13980 MODRM_CHECK;
13981 codep++;
13983 if (modrm.mod != 3)
13985 OP_E_memory (bytemode, sizeflag);
13986 return;
13989 reg = modrm.rm;
13990 USED_REX (REX_B);
13991 if (rex & REX_B)
13992 reg += 8;
13994 if ((sizeflag & SUFFIX_ALWAYS)
13995 && (bytemode == x_swap_mode
13996 || bytemode == d_swap_mode
13997 || bytemode == d_scalar_swap_mode
13998 || bytemode == q_swap_mode
13999 || bytemode == q_scalar_swap_mode))
14000 swap_operand ();
14002 if (need_vex
14003 && bytemode != xmm_mode
14004 && bytemode != xmmq_mode
14005 && bytemode != d_scalar_mode
14006 && bytemode != d_scalar_swap_mode
14007 && bytemode != q_scalar_mode
14008 && bytemode != q_scalar_swap_mode
14009 && bytemode != vex_scalar_w_dq_mode)
14011 switch (vex.length)
14013 case 128:
14014 names = names_xmm;
14015 break;
14016 case 256:
14017 names = names_ymm;
14018 break;
14019 default:
14020 abort ();
14023 else
14024 names = names_xmm;
14025 oappend (names[reg]);
14028 static void
14029 OP_MS (int bytemode, int sizeflag)
14031 if (modrm.mod == 3)
14032 OP_EM (bytemode, sizeflag);
14033 else
14034 BadOp ();
14037 static void
14038 OP_XS (int bytemode, int sizeflag)
14040 if (modrm.mod == 3)
14041 OP_EX (bytemode, sizeflag);
14042 else
14043 BadOp ();
14046 static void
14047 OP_M (int bytemode, int sizeflag)
14049 if (modrm.mod == 3)
14050 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14051 BadOp ();
14052 else
14053 OP_E (bytemode, sizeflag);
14056 static void
14057 OP_0f07 (int bytemode, int sizeflag)
14059 if (modrm.mod != 3 || modrm.rm != 0)
14060 BadOp ();
14061 else
14062 OP_E (bytemode, sizeflag);
14065 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14066 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14068 static void
14069 NOP_Fixup1 (int bytemode, int sizeflag)
14071 if ((prefixes & PREFIX_DATA) != 0
14072 || (rex != 0
14073 && rex != 0x48
14074 && address_mode == mode_64bit))
14075 OP_REG (bytemode, sizeflag);
14076 else
14077 strcpy (obuf, "nop");
14080 static void
14081 NOP_Fixup2 (int bytemode, int sizeflag)
14083 if ((prefixes & PREFIX_DATA) != 0
14084 || (rex != 0
14085 && rex != 0x48
14086 && address_mode == mode_64bit))
14087 OP_IMREG (bytemode, sizeflag);
14090 static const char *const Suffix3DNow[] = {
14091 /* 00 */ NULL, NULL, NULL, NULL,
14092 /* 04 */ NULL, NULL, NULL, NULL,
14093 /* 08 */ NULL, NULL, NULL, NULL,
14094 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
14095 /* 10 */ NULL, NULL, NULL, NULL,
14096 /* 14 */ NULL, NULL, NULL, NULL,
14097 /* 18 */ NULL, NULL, NULL, NULL,
14098 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
14099 /* 20 */ NULL, NULL, NULL, NULL,
14100 /* 24 */ NULL, NULL, NULL, NULL,
14101 /* 28 */ NULL, NULL, NULL, NULL,
14102 /* 2C */ NULL, NULL, NULL, NULL,
14103 /* 30 */ NULL, NULL, NULL, NULL,
14104 /* 34 */ NULL, NULL, NULL, NULL,
14105 /* 38 */ NULL, NULL, NULL, NULL,
14106 /* 3C */ NULL, NULL, NULL, NULL,
14107 /* 40 */ NULL, NULL, NULL, NULL,
14108 /* 44 */ NULL, NULL, NULL, NULL,
14109 /* 48 */ NULL, NULL, NULL, NULL,
14110 /* 4C */ NULL, NULL, NULL, NULL,
14111 /* 50 */ NULL, NULL, NULL, NULL,
14112 /* 54 */ NULL, NULL, NULL, NULL,
14113 /* 58 */ NULL, NULL, NULL, NULL,
14114 /* 5C */ NULL, NULL, NULL, NULL,
14115 /* 60 */ NULL, NULL, NULL, NULL,
14116 /* 64 */ NULL, NULL, NULL, NULL,
14117 /* 68 */ NULL, NULL, NULL, NULL,
14118 /* 6C */ NULL, NULL, NULL, NULL,
14119 /* 70 */ NULL, NULL, NULL, NULL,
14120 /* 74 */ NULL, NULL, NULL, NULL,
14121 /* 78 */ NULL, NULL, NULL, NULL,
14122 /* 7C */ NULL, NULL, NULL, NULL,
14123 /* 80 */ NULL, NULL, NULL, NULL,
14124 /* 84 */ NULL, NULL, NULL, NULL,
14125 /* 88 */ NULL, NULL, "pfnacc", NULL,
14126 /* 8C */ NULL, NULL, "pfpnacc", NULL,
14127 /* 90 */ "pfcmpge", NULL, NULL, NULL,
14128 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
14129 /* 98 */ NULL, NULL, "pfsub", NULL,
14130 /* 9C */ NULL, NULL, "pfadd", NULL,
14131 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
14132 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
14133 /* A8 */ NULL, NULL, "pfsubr", NULL,
14134 /* AC */ NULL, NULL, "pfacc", NULL,
14135 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
14136 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
14137 /* B8 */ NULL, NULL, NULL, "pswapd",
14138 /* BC */ NULL, NULL, NULL, "pavgusb",
14139 /* C0 */ NULL, NULL, NULL, NULL,
14140 /* C4 */ NULL, NULL, NULL, NULL,
14141 /* C8 */ NULL, NULL, NULL, NULL,
14142 /* CC */ NULL, NULL, NULL, NULL,
14143 /* D0 */ NULL, NULL, NULL, NULL,
14144 /* D4 */ NULL, NULL, NULL, NULL,
14145 /* D8 */ NULL, NULL, NULL, NULL,
14146 /* DC */ NULL, NULL, NULL, NULL,
14147 /* E0 */ NULL, NULL, NULL, NULL,
14148 /* E4 */ NULL, NULL, NULL, NULL,
14149 /* E8 */ NULL, NULL, NULL, NULL,
14150 /* EC */ NULL, NULL, NULL, NULL,
14151 /* F0 */ NULL, NULL, NULL, NULL,
14152 /* F4 */ NULL, NULL, NULL, NULL,
14153 /* F8 */ NULL, NULL, NULL, NULL,
14154 /* FC */ NULL, NULL, NULL, NULL,
14157 static void
14158 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14160 const char *mnemonic;
14162 FETCH_DATA (the_info, codep + 1);
14163 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14164 place where an 8-bit immediate would normally go. ie. the last
14165 byte of the instruction. */
14166 obufp = mnemonicendp;
14167 mnemonic = Suffix3DNow[*codep++ & 0xff];
14168 if (mnemonic)
14169 oappend (mnemonic);
14170 else
14172 /* Since a variable sized modrm/sib chunk is between the start
14173 of the opcode (0x0f0f) and the opcode suffix, we need to do
14174 all the modrm processing first, and don't know until now that
14175 we have a bad opcode. This necessitates some cleaning up. */
14176 op_out[0][0] = '\0';
14177 op_out[1][0] = '\0';
14178 BadOp ();
14180 mnemonicendp = obufp;
14183 static struct op simd_cmp_op[] =
14185 { STRING_COMMA_LEN ("eq") },
14186 { STRING_COMMA_LEN ("lt") },
14187 { STRING_COMMA_LEN ("le") },
14188 { STRING_COMMA_LEN ("unord") },
14189 { STRING_COMMA_LEN ("neq") },
14190 { STRING_COMMA_LEN ("nlt") },
14191 { STRING_COMMA_LEN ("nle") },
14192 { STRING_COMMA_LEN ("ord") }
14195 static void
14196 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14198 unsigned int cmp_type;
14200 FETCH_DATA (the_info, codep + 1);
14201 cmp_type = *codep++ & 0xff;
14202 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14204 char suffix [3];
14205 char *p = mnemonicendp - 2;
14206 suffix[0] = p[0];
14207 suffix[1] = p[1];
14208 suffix[2] = '\0';
14209 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14210 mnemonicendp += simd_cmp_op[cmp_type].len;
14212 else
14214 /* We have a reserved extension byte. Output it directly. */
14215 scratchbuf[0] = '$';
14216 print_operand_value (scratchbuf + 1, 1, cmp_type);
14217 oappend (scratchbuf + intel_syntax);
14218 scratchbuf[0] = '\0';
14222 static void
14223 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14224 int sizeflag ATTRIBUTE_UNUSED)
14226 /* mwait %eax,%ecx */
14227 if (!intel_syntax)
14229 const char **names = (address_mode == mode_64bit
14230 ? names64 : names32);
14231 strcpy (op_out[0], names[0]);
14232 strcpy (op_out[1], names[1]);
14233 two_source_ops = 1;
14235 /* Skip mod/rm byte. */
14236 MODRM_CHECK;
14237 codep++;
14240 static void
14241 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14242 int sizeflag ATTRIBUTE_UNUSED)
14244 /* monitor %eax,%ecx,%edx" */
14245 if (!intel_syntax)
14247 const char **op1_names;
14248 const char **names = (address_mode == mode_64bit
14249 ? names64 : names32);
14251 if (!(prefixes & PREFIX_ADDR))
14252 op1_names = (address_mode == mode_16bit
14253 ? names16 : names);
14254 else
14256 /* Remove "addr16/addr32". */
14257 all_prefixes[last_addr_prefix] = 0;
14258 op1_names = (address_mode != mode_32bit
14259 ? names32 : names16);
14260 used_prefixes |= PREFIX_ADDR;
14262 strcpy (op_out[0], op1_names[0]);
14263 strcpy (op_out[1], names[1]);
14264 strcpy (op_out[2], names[2]);
14265 two_source_ops = 1;
14267 /* Skip mod/rm byte. */
14268 MODRM_CHECK;
14269 codep++;
14272 static void
14273 BadOp (void)
14275 /* Throw away prefixes and 1st. opcode byte. */
14276 codep = insn_codep + 1;
14277 oappend ("(bad)");
14280 static void
14281 REP_Fixup (int bytemode, int sizeflag)
14283 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14284 lods and stos. */
14285 if (prefixes & PREFIX_REPZ)
14286 all_prefixes[last_repz_prefix] = REP_PREFIX;
14288 switch (bytemode)
14290 case al_reg:
14291 case eAX_reg:
14292 case indir_dx_reg:
14293 OP_IMREG (bytemode, sizeflag);
14294 break;
14295 case eDI_reg:
14296 OP_ESreg (bytemode, sizeflag);
14297 break;
14298 case eSI_reg:
14299 OP_DSreg (bytemode, sizeflag);
14300 break;
14301 default:
14302 abort ();
14303 break;
14307 static void
14308 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14310 USED_REX (REX_W);
14311 if (rex & REX_W)
14313 /* Change cmpxchg8b to cmpxchg16b. */
14314 char *p = mnemonicendp - 2;
14315 mnemonicendp = stpcpy (p, "16b");
14316 bytemode = o_mode;
14318 OP_M (bytemode, sizeflag);
14321 static void
14322 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14324 const char **names;
14326 if (need_vex)
14328 switch (vex.length)
14330 case 128:
14331 names = names_xmm;
14332 break;
14333 case 256:
14334 names = names_ymm;
14335 break;
14336 default:
14337 abort ();
14340 else
14341 names = names_xmm;
14342 oappend (names[reg]);
14345 static void
14346 CRC32_Fixup (int bytemode, int sizeflag)
14348 /* Add proper suffix to "crc32". */
14349 char *p = mnemonicendp;
14351 switch (bytemode)
14353 case b_mode:
14354 if (intel_syntax)
14355 goto skip;
14357 *p++ = 'b';
14358 break;
14359 case v_mode:
14360 if (intel_syntax)
14361 goto skip;
14363 USED_REX (REX_W);
14364 if (rex & REX_W)
14365 *p++ = 'q';
14366 else
14368 if (sizeflag & DFLAG)
14369 *p++ = 'l';
14370 else
14371 *p++ = 'w';
14372 used_prefixes |= (prefixes & PREFIX_DATA);
14374 break;
14375 default:
14376 oappend (INTERNAL_DISASSEMBLER_ERROR);
14377 break;
14379 mnemonicendp = p;
14380 *p = '\0';
14382 skip:
14383 if (modrm.mod == 3)
14385 int add;
14387 /* Skip mod/rm byte. */
14388 MODRM_CHECK;
14389 codep++;
14391 USED_REX (REX_B);
14392 add = (rex & REX_B) ? 8 : 0;
14393 if (bytemode == b_mode)
14395 USED_REX (0);
14396 if (rex)
14397 oappend (names8rex[modrm.rm + add]);
14398 else
14399 oappend (names8[modrm.rm + add]);
14401 else
14403 USED_REX (REX_W);
14404 if (rex & REX_W)
14405 oappend (names64[modrm.rm + add]);
14406 else if ((prefixes & PREFIX_DATA))
14407 oappend (names16[modrm.rm + add]);
14408 else
14409 oappend (names32[modrm.rm + add]);
14412 else
14413 OP_E (bytemode, sizeflag);
14416 static void
14417 FXSAVE_Fixup (int bytemode, int sizeflag)
14419 /* Add proper suffix to "fxsave" and "fxrstor". */
14420 USED_REX (REX_W);
14421 if (rex & REX_W)
14423 char *p = mnemonicendp;
14424 *p++ = '6';
14425 *p++ = '4';
14426 *p = '\0';
14427 mnemonicendp = p;
14429 OP_M (bytemode, sizeflag);
14432 /* Display the destination register operand for instructions with
14433 VEX. */
14435 static void
14436 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14438 int reg;
14439 const char **names;
14441 if (!need_vex)
14442 abort ();
14444 if (!need_vex_reg)
14445 return;
14447 reg = vex.register_specifier;
14448 if (bytemode == vex_scalar_mode)
14450 oappend (names_xmm[reg]);
14451 return;
14454 switch (vex.length)
14456 case 128:
14457 switch (bytemode)
14459 case vex_mode:
14460 case vex128_mode:
14461 break;
14462 default:
14463 abort ();
14464 return;
14467 names = names_xmm;
14468 break;
14469 case 256:
14470 switch (bytemode)
14472 case vex_mode:
14473 case vex256_mode:
14474 break;
14475 default:
14476 abort ();
14477 return;
14480 names = names_ymm;
14481 break;
14482 default:
14483 abort ();
14484 break;
14486 oappend (names[reg]);
14489 /* Get the VEX immediate byte without moving codep. */
14491 static unsigned char
14492 get_vex_imm8 (int sizeflag, int opnum)
14494 int bytes_before_imm = 0;
14496 if (modrm.mod != 3)
14498 /* There are SIB/displacement bytes. */
14499 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14501 /* 32/64 bit address mode */
14502 int base = modrm.rm;
14504 /* Check SIB byte. */
14505 if (base == 4)
14507 FETCH_DATA (the_info, codep + 1);
14508 base = *codep & 7;
14509 /* When decoding the third source, don't increase
14510 bytes_before_imm as this has already been incremented
14511 by one in OP_E_memory while decoding the second
14512 source operand. */
14513 if (opnum == 0)
14514 bytes_before_imm++;
14517 /* Don't increase bytes_before_imm when decoding the third source,
14518 it has already been incremented by OP_E_memory while decoding
14519 the second source operand. */
14520 if (opnum == 0)
14522 switch (modrm.mod)
14524 case 0:
14525 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14526 SIB == 5, there is a 4 byte displacement. */
14527 if (base != 5)
14528 /* No displacement. */
14529 break;
14530 case 2:
14531 /* 4 byte displacement. */
14532 bytes_before_imm += 4;
14533 break;
14534 case 1:
14535 /* 1 byte displacement. */
14536 bytes_before_imm++;
14537 break;
14541 else
14543 /* 16 bit address mode */
14544 /* Don't increase bytes_before_imm when decoding the third source,
14545 it has already been incremented by OP_E_memory while decoding
14546 the second source operand. */
14547 if (opnum == 0)
14549 switch (modrm.mod)
14551 case 0:
14552 /* When modrm.rm == 6, there is a 2 byte displacement. */
14553 if (modrm.rm != 6)
14554 /* No displacement. */
14555 break;
14556 case 2:
14557 /* 2 byte displacement. */
14558 bytes_before_imm += 2;
14559 break;
14560 case 1:
14561 /* 1 byte displacement: when decoding the third source,
14562 don't increase bytes_before_imm as this has already
14563 been incremented by one in OP_E_memory while decoding
14564 the second source operand. */
14565 if (opnum == 0)
14566 bytes_before_imm++;
14568 break;
14574 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14575 return codep [bytes_before_imm];
14578 static void
14579 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14581 const char **names;
14583 if (reg == -1 && modrm.mod != 3)
14585 OP_E_memory (bytemode, sizeflag);
14586 return;
14588 else
14590 if (reg == -1)
14592 reg = modrm.rm;
14593 USED_REX (REX_B);
14594 if (rex & REX_B)
14595 reg += 8;
14597 else if (reg > 7 && address_mode != mode_64bit)
14598 BadOp ();
14601 switch (vex.length)
14603 case 128:
14604 names = names_xmm;
14605 break;
14606 case 256:
14607 names = names_ymm;
14608 break;
14609 default:
14610 abort ();
14612 oappend (names[reg]);
14615 static void
14616 OP_EX_VexImmW (int bytemode, int sizeflag)
14618 int reg = -1;
14619 static unsigned char vex_imm8;
14621 if (vex_w_done == 0)
14623 vex_w_done = 1;
14625 /* Skip mod/rm byte. */
14626 MODRM_CHECK;
14627 codep++;
14629 vex_imm8 = get_vex_imm8 (sizeflag, 0);
14631 if (vex.w)
14632 reg = vex_imm8 >> 4;
14634 OP_EX_VexReg (bytemode, sizeflag, reg);
14636 else if (vex_w_done == 1)
14638 vex_w_done = 2;
14640 if (!vex.w)
14641 reg = vex_imm8 >> 4;
14643 OP_EX_VexReg (bytemode, sizeflag, reg);
14645 else
14647 /* Output the imm8 directly. */
14648 scratchbuf[0] = '$';
14649 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14650 oappend (scratchbuf + intel_syntax);
14651 scratchbuf[0] = '\0';
14652 codep++;
14656 static void
14657 OP_Vex_2src (int bytemode, int sizeflag)
14659 if (modrm.mod == 3)
14661 int reg = modrm.rm;
14662 USED_REX (REX_B);
14663 if (rex & REX_B)
14664 reg += 8;
14665 oappend (names_xmm[reg]);
14667 else
14669 if (intel_syntax
14670 && (bytemode == v_mode || bytemode == v_swap_mode))
14672 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14673 used_prefixes |= (prefixes & PREFIX_DATA);
14675 OP_E (bytemode, sizeflag);
14679 static void
14680 OP_Vex_2src_1 (int bytemode, int sizeflag)
14682 if (modrm.mod == 3)
14684 /* Skip mod/rm byte. */
14685 MODRM_CHECK;
14686 codep++;
14689 if (vex.w)
14690 oappend (names_xmm[vex.register_specifier]);
14691 else
14692 OP_Vex_2src (bytemode, sizeflag);
14695 static void
14696 OP_Vex_2src_2 (int bytemode, int sizeflag)
14698 if (vex.w)
14699 OP_Vex_2src (bytemode, sizeflag);
14700 else
14701 oappend (names_xmm[vex.register_specifier]);
14704 static void
14705 OP_EX_VexW (int bytemode, int sizeflag)
14707 int reg = -1;
14709 if (!vex_w_done)
14711 vex_w_done = 1;
14713 /* Skip mod/rm byte. */
14714 MODRM_CHECK;
14715 codep++;
14717 if (vex.w)
14718 reg = get_vex_imm8 (sizeflag, 0) >> 4;
14720 else
14722 if (!vex.w)
14723 reg = get_vex_imm8 (sizeflag, 1) >> 4;
14726 OP_EX_VexReg (bytemode, sizeflag, reg);
14729 static void
14730 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14731 int sizeflag ATTRIBUTE_UNUSED)
14733 /* Skip the immediate byte and check for invalid bits. */
14734 FETCH_DATA (the_info, codep + 1);
14735 if (*codep++ & 0xf)
14736 BadOp ();
14739 static void
14740 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14742 int reg;
14743 const char **names;
14745 FETCH_DATA (the_info, codep + 1);
14746 reg = *codep++;
14748 if (bytemode != x_mode)
14749 abort ();
14751 if (reg & 0xf)
14752 BadOp ();
14754 reg >>= 4;
14755 if (reg > 7 && address_mode != mode_64bit)
14756 BadOp ();
14758 switch (vex.length)
14760 case 128:
14761 names = names_xmm;
14762 break;
14763 case 256:
14764 names = names_ymm;
14765 break;
14766 default:
14767 abort ();
14769 oappend (names[reg]);
14772 static void
14773 OP_XMM_VexW (int bytemode, int sizeflag)
14775 /* Turn off the REX.W bit since it is used for swapping operands
14776 now. */
14777 rex &= ~REX_W;
14778 OP_XMM (bytemode, sizeflag);
14781 static void
14782 OP_EX_Vex (int bytemode, int sizeflag)
14784 if (modrm.mod != 3)
14786 if (vex.register_specifier != 0)
14787 BadOp ();
14788 need_vex_reg = 0;
14790 OP_EX (bytemode, sizeflag);
14793 static void
14794 OP_XMM_Vex (int bytemode, int sizeflag)
14796 if (modrm.mod != 3)
14798 if (vex.register_specifier != 0)
14799 BadOp ();
14800 need_vex_reg = 0;
14802 OP_XMM (bytemode, sizeflag);
14805 static void
14806 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14808 switch (vex.length)
14810 case 128:
14811 mnemonicendp = stpcpy (obuf, "vzeroupper");
14812 break;
14813 case 256:
14814 mnemonicendp = stpcpy (obuf, "vzeroall");
14815 break;
14816 default:
14817 abort ();
14821 static struct op vex_cmp_op[] =
14823 { STRING_COMMA_LEN ("eq") },
14824 { STRING_COMMA_LEN ("lt") },
14825 { STRING_COMMA_LEN ("le") },
14826 { STRING_COMMA_LEN ("unord") },
14827 { STRING_COMMA_LEN ("neq") },
14828 { STRING_COMMA_LEN ("nlt") },
14829 { STRING_COMMA_LEN ("nle") },
14830 { STRING_COMMA_LEN ("ord") },
14831 { STRING_COMMA_LEN ("eq_uq") },
14832 { STRING_COMMA_LEN ("nge") },
14833 { STRING_COMMA_LEN ("ngt") },
14834 { STRING_COMMA_LEN ("false") },
14835 { STRING_COMMA_LEN ("neq_oq") },
14836 { STRING_COMMA_LEN ("ge") },
14837 { STRING_COMMA_LEN ("gt") },
14838 { STRING_COMMA_LEN ("true") },
14839 { STRING_COMMA_LEN ("eq_os") },
14840 { STRING_COMMA_LEN ("lt_oq") },
14841 { STRING_COMMA_LEN ("le_oq") },
14842 { STRING_COMMA_LEN ("unord_s") },
14843 { STRING_COMMA_LEN ("neq_us") },
14844 { STRING_COMMA_LEN ("nlt_uq") },
14845 { STRING_COMMA_LEN ("nle_uq") },
14846 { STRING_COMMA_LEN ("ord_s") },
14847 { STRING_COMMA_LEN ("eq_us") },
14848 { STRING_COMMA_LEN ("nge_uq") },
14849 { STRING_COMMA_LEN ("ngt_uq") },
14850 { STRING_COMMA_LEN ("false_os") },
14851 { STRING_COMMA_LEN ("neq_os") },
14852 { STRING_COMMA_LEN ("ge_oq") },
14853 { STRING_COMMA_LEN ("gt_oq") },
14854 { STRING_COMMA_LEN ("true_us") },
14857 static void
14858 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14860 unsigned int cmp_type;
14862 FETCH_DATA (the_info, codep + 1);
14863 cmp_type = *codep++ & 0xff;
14864 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14866 char suffix [3];
14867 char *p = mnemonicendp - 2;
14868 suffix[0] = p[0];
14869 suffix[1] = p[1];
14870 suffix[2] = '\0';
14871 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14872 mnemonicendp += vex_cmp_op[cmp_type].len;
14874 else
14876 /* We have a reserved extension byte. Output it directly. */
14877 scratchbuf[0] = '$';
14878 print_operand_value (scratchbuf + 1, 1, cmp_type);
14879 oappend (scratchbuf + intel_syntax);
14880 scratchbuf[0] = '\0';
14884 static const struct op pclmul_op[] =
14886 { STRING_COMMA_LEN ("lql") },
14887 { STRING_COMMA_LEN ("hql") },
14888 { STRING_COMMA_LEN ("lqh") },
14889 { STRING_COMMA_LEN ("hqh") }
14892 static void
14893 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14894 int sizeflag ATTRIBUTE_UNUSED)
14896 unsigned int pclmul_type;
14898 FETCH_DATA (the_info, codep + 1);
14899 pclmul_type = *codep++ & 0xff;
14900 switch (pclmul_type)
14902 case 0x10:
14903 pclmul_type = 2;
14904 break;
14905 case 0x11:
14906 pclmul_type = 3;
14907 break;
14908 default:
14909 break;
14911 if (pclmul_type < ARRAY_SIZE (pclmul_op))
14913 char suffix [4];
14914 char *p = mnemonicendp - 3;
14915 suffix[0] = p[0];
14916 suffix[1] = p[1];
14917 suffix[2] = p[2];
14918 suffix[3] = '\0';
14919 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14920 mnemonicendp += pclmul_op[pclmul_type].len;
14922 else
14924 /* We have a reserved extension byte. Output it directly. */
14925 scratchbuf[0] = '$';
14926 print_operand_value (scratchbuf + 1, 1, pclmul_type);
14927 oappend (scratchbuf + intel_syntax);
14928 scratchbuf[0] = '\0';
14932 static void
14933 MOVBE_Fixup (int bytemode, int sizeflag)
14935 /* Add proper suffix to "movbe". */
14936 char *p = mnemonicendp;
14938 switch (bytemode)
14940 case v_mode:
14941 if (intel_syntax)
14942 goto skip;
14944 USED_REX (REX_W);
14945 if (sizeflag & SUFFIX_ALWAYS)
14947 if (rex & REX_W)
14948 *p++ = 'q';
14949 else
14951 if (sizeflag & DFLAG)
14952 *p++ = 'l';
14953 else
14954 *p++ = 'w';
14955 used_prefixes |= (prefixes & PREFIX_DATA);
14958 break;
14959 default:
14960 oappend (INTERNAL_DISASSEMBLER_ERROR);
14961 break;
14963 mnemonicendp = p;
14964 *p = '\0';
14966 skip:
14967 OP_M (bytemode, sizeflag);
14970 static void
14971 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14973 int reg;
14974 const char **names;
14976 /* Skip mod/rm byte. */
14977 MODRM_CHECK;
14978 codep++;
14980 if (vex.w)
14981 names = names64;
14982 else
14983 names = names32;
14985 reg = modrm.rm;
14986 USED_REX (REX_B);
14987 if (rex & REX_B)
14988 reg += 8;
14990 oappend (names[reg]);
14993 static void
14994 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14996 const char **names;
14998 if (vex.w)
14999 names = names64;
15000 else
15001 names = names32;
15003 oappend (names[vex.register_specifier]);