opcodes/openrisc-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
   8 Free Software Foundation, Inc.
   9
  10 This file is part of the GNU Binutils and GDB, the GNU debugger.
  11
  12 This program is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2, or (at your option)
  15 any later version.
  16
  17 This program is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with this program; if not, write to the Free Software Foundation, Inc.,
  24 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  25
  26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  27    Keep that in mind.  */
  28
  29 #include "sysdep.h"
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "dis-asm.h"
  33 #include "bfd.h"
  34 #include "symcat.h"
  35 #include "libiberty.h"
  36 #include "openrisc-desc.h"
  37 #include "openrisc-opc.h"
  38 #include "opintl.h"
  39
  40 /* Default text to print if an instruction isn't recognized.  */
  41 #define UNKNOWN_INSN_MSG _("*unknown*")
  42
  43 static void print_normal
  44      PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
  45 static void print_address
  46      PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
  47 static void print_keyword
  48      PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
  49 static void print_insn_normal
  50      PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
  51               bfd_vma, int));
  52 static int print_insn
  53      PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
  54 static int default_print_insn
  55      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  56 static int read_insn
  57      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
  58               CGEN_EXTRACT_INFO *, unsigned long *));
  59 \f
  60 /* -- disassembler routines inserted here */
  61
  62
  63 void openrisc_cgen_print_operand
  64   PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
  65            void const *, bfd_vma, int));
  66
  67 /* Main entry point for printing operands.
  68    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
  69    of dis-asm.h on cgen.h.
  70
  71    This function is basically just a big switch statement.  Earlier versions
  72    used tables to look up the function to use, but
  73    - if the table contains both assembler and disassembler functions then
  74      the disassembler contains much of the assembler and vice-versa,
  75    - there's a lot of inlining possibilities as things grow,
  76    - using a switch statement avoids the function call overhead.
  77
  78    This function could be moved into `print_insn_normal', but keeping it
  79    separate makes clear the interface between `print_insn_normal' and each of
  80    the handlers.  */
  81
  82 void
  83 openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
  84      CGEN_CPU_DESC cd;
  85      int opindex;
  86      PTR xinfo;
  87      CGEN_FIELDS *fields;
  88      void const *attrs ATTRIBUTE_UNUSED;
  89      bfd_vma pc;
  90      int length;
  91 {
  92  disassemble_info *info = (disassemble_info *) xinfo;
  93
  94   switch (opindex)
  95     {
  96     case OPENRISC_OPERAND_ABS_26 :
  97       print_address (cd, info, fields->f_abs26, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
  98       break;
  99     case OPENRISC_OPERAND_DISP_26 :
 100       print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 101       break;
 102     case OPENRISC_OPERAND_HI16 :
 103       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 104       break;
 105     case OPENRISC_OPERAND_LO16 :
 106       print_normal (cd, info, fields->f_lo16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 107       break;
 108     case OPENRISC_OPERAND_OP_F_23 :
 109       print_normal (cd, info, fields->f_op4, 0, pc, length);
 110       break;
 111     case OPENRISC_OPERAND_OP_F_3 :
 112       print_normal (cd, info, fields->f_op5, 0, pc, length);
 113       break;
 114     case OPENRISC_OPERAND_RA :
 115       print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0);
 116       break;
 117     case OPENRISC_OPERAND_RB :
 118       print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0);
 119       break;
 120     case OPENRISC_OPERAND_RD :
 121       print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0);
 122       break;
 123     case OPENRISC_OPERAND_SIMM_16 :
 124       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 125       break;
 126     case OPENRISC_OPERAND_UI16NC :
 127       print_normal (cd, info, fields->f_i16nc, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 128       break;
 129     case OPENRISC_OPERAND_UIMM_16 :
 130       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
 131       break;
 132     case OPENRISC_OPERAND_UIMM_5 :
 133       print_normal (cd, info, fields->f_uimm5, 0, pc, length);
 134       break;
 135
 136     default :
 137       /* xgettext:c-format */
 138       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 139                opindex);
 140     abort ();
 141   }
 142 }
 143
 144 cgen_print_fn * const openrisc_cgen_print_handlers[] =
 145 {
 146   print_insn_normal,
 147 };
 148
 149
 150 void
 151 openrisc_cgen_init_dis (cd)
 152      CGEN_CPU_DESC cd;
 153 {
 154   openrisc_cgen_init_opcode_table (cd);
 155   openrisc_cgen_init_ibld_table (cd);
 156   cd->print_handlers = & openrisc_cgen_print_handlers[0];
 157   cd->print_operand = openrisc_cgen_print_operand;
 158 }
 159
 160 \f
 161 /* Default print handler.  */
 162
 163 static void
 164 print_normal (cd, dis_info, value, attrs, pc, length)
 165      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 166      PTR dis_info;
 167      long value;
 168      unsigned int attrs;
 169      bfd_vma pc ATTRIBUTE_UNUSED;
 170      int length ATTRIBUTE_UNUSED;
 171 {
 172   disassemble_info *info = (disassemble_info *) dis_info;
 173
 174 #ifdef CGEN_PRINT_NORMAL
 175   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 176 #endif
 177
 178   /* Print the operand as directed by the attributes.  */
 179   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 180     ; /* nothing to do */
 181   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 182     (*info->fprintf_func) (info->stream, "%ld", value);
 183   else
 184     (*info->fprintf_func) (info->stream, "0x%lx", value);
 185 }
 186
 187 /* Default address handler.  */
 188
 189 static void
 190 print_address (cd, dis_info, value, attrs, pc, length)
 191      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 192      PTR dis_info;
 193      bfd_vma value;
 194      unsigned int attrs;
 195      bfd_vma pc ATTRIBUTE_UNUSED;
 196      int length ATTRIBUTE_UNUSED;
 197 {
 198   disassemble_info *info = (disassemble_info *) dis_info;
 199
 200 #ifdef CGEN_PRINT_ADDRESS
 201   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 202 #endif
 203
 204   /* Print the operand as directed by the attributes.  */
 205   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 206     ; /* nothing to do */
 207   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 208     (*info->print_address_func) (value, info);
 209   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 210     (*info->print_address_func) (value, info);
 211   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 212     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 213   else
 214     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 215 }
 216
 217 /* Keyword print handler.  */
 218
 219 static void
 220 print_keyword (cd, dis_info, keyword_table, value, attrs)
 221      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 222      PTR dis_info;
 223      CGEN_KEYWORD *keyword_table;
 224      long value;
 225      unsigned int attrs ATTRIBUTE_UNUSED;
 226 {
 227   disassemble_info *info = (disassemble_info *) dis_info;
 228   const CGEN_KEYWORD_ENTRY *ke;
 229
 230   ke = cgen_keyword_lookup_value (keyword_table, value);
 231   if (ke != NULL)
 232     (*info->fprintf_func) (info->stream, "%s", ke->name);
 233   else
 234     (*info->fprintf_func) (info->stream, "???");
 235 }
 236 \f
 237 /* Default insn printer.
 238
 239    DIS_INFO is defined as `PTR' so the disassembler needn't know anything
 240    about disassemble_info.  */
 241
 242 static void
 243 print_insn_normal (cd, dis_info, insn, fields, pc, length)
 244      CGEN_CPU_DESC cd;
 245      PTR dis_info;
 246      const CGEN_INSN *insn;
 247      CGEN_FIELDS *fields;
 248      bfd_vma pc;
 249      int length;
 250 {
 251   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 252   disassemble_info *info = (disassemble_info *) dis_info;
 253   const CGEN_SYNTAX_CHAR_TYPE *syn;
 254
 255   CGEN_INIT_PRINT (cd);
 256
 257   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 258     {
 259       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 260         {
 261           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 262           continue;
 263         }
 264       if (CGEN_SYNTAX_CHAR_P (*syn))
 265         {
 266           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 267           continue;
 268         }
 269
 270       /* We have an operand.  */
 271       openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 272                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 273     }
 274 }
 275 \f
 276 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 277    the extract info.
 278    Returns 0 if all is well, non-zero otherwise.  */
 279
 280 static int
 281 read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
 282      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 283      bfd_vma pc;
 284      disassemble_info *info;
 285      char *buf;
 286      int buflen;
 287      CGEN_EXTRACT_INFO *ex_info;
 288      unsigned long *insn_value;
 289 {
 290   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 291   if (status != 0)
 292     {
 293       (*info->memory_error_func) (status, pc, info);
 294       return -1;
 295     }
 296
 297   ex_info->dis_info = info;
 298   ex_info->valid = (1 << buflen) - 1;
 299   ex_info->insn_bytes = buf;
 300
 301   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 302   return 0;
 303 }
 304
 305 /* Utility to print an insn.
 306    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 307    The result is the size of the insn in bytes or zero for an unknown insn
 308    or -1 if an error occurs fetching data (memory_error_func will have
 309    been called).  */
 310
 311 static int
 312 print_insn (cd, pc, info, buf, buflen)
 313      CGEN_CPU_DESC cd;
 314      bfd_vma pc;
 315      disassemble_info *info;
 316      char *buf;
 317      unsigned int buflen;
 318 {
 319   CGEN_INSN_INT insn_value;
 320   const CGEN_INSN_LIST *insn_list;
 321   CGEN_EXTRACT_INFO ex_info;
 322   int basesize;
 323
 324   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 325   basesize = cd->base_insn_bitsize < buflen * 8 ?
 326                                      cd->base_insn_bitsize : buflen * 8;
 327   insn_value = cgen_get_insn_value (cd, buf, basesize);
 328
 329
 330   /* Fill in ex_info fields like read_insn would.  Don't actually call
 331      read_insn, since the incoming buffer is already read (and possibly
 332      modified a la m32r).  */
 333   ex_info.valid = (1 << buflen) - 1;
 334   ex_info.dis_info = info;
 335   ex_info.insn_bytes = buf;
 336
 337   /* The instructions are stored in hash lists.
 338      Pick the first one and keep trying until we find the right one.  */
 339
 340   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 341   while (insn_list != NULL)
 342     {
 343       const CGEN_INSN *insn = insn_list->insn;
 344       CGEN_FIELDS fields;
 345       int length;
 346       unsigned long insn_value_cropped;
 347
 348 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 349       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 350       /* Supported by this cpu?  */
 351       if (! openrisc_cgen_insn_supported (cd, insn))
 352         {
 353           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 354           continue;
 355         }
 356 #endif
 357
 358       /* Basic bit mask must be correct.  */
 359       /* ??? May wish to allow target to defer this check until the extract
 360          handler.  */
 361
 362       /* Base size may exceed this instruction's size.  Extract the
 363          relevant part from the buffer. */
 364       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 365           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 366         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 367                                            info->endian == BFD_ENDIAN_BIG);
 368       else
 369         insn_value_cropped = insn_value;
 370
 371       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 372           == CGEN_INSN_BASE_VALUE (insn))
 373         {
 374           /* Printing is handled in two passes.  The first pass parses the
 375              machine insn and extracts the fields.  The second pass prints
 376              them.  */
 377
 378           /* Make sure the entire insn is loaded into insn_value, if it
 379              can fit.  */
 380           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 381               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 382             {
 383               unsigned long full_insn_value;
 384               int rc = read_insn (cd, pc, info, buf,
 385                                   CGEN_INSN_BITSIZE (insn) / 8,
 386                                   & ex_info, & full_insn_value);
 387               if (rc != 0)
 388                 return rc;
 389               length = CGEN_EXTRACT_FN (cd, insn)
 390                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 391             }
 392           else
 393             length = CGEN_EXTRACT_FN (cd, insn)
 394               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 395
 396           /* length < 0 -> error */
 397           if (length < 0)
 398             return length;
 399           if (length > 0)
 400             {
 401               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 402               /* length is in bits, result is in bytes */
 403               return length / 8;
 404             }
 405         }
 406
 407       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 408     }
 409
 410   return 0;
 411 }
 412
 413 /* Default value for CGEN_PRINT_INSN.
 414    The result is the size of the insn in bytes or zero for an unknown insn
 415    or -1 if an error occured fetching bytes.  */
 416
 417 #ifndef CGEN_PRINT_INSN
 418 #define CGEN_PRINT_INSN default_print_insn
 419 #endif
 420
 421 static int
 422 default_print_insn (cd, pc, info)
 423      CGEN_CPU_DESC cd;
 424      bfd_vma pc;
 425      disassemble_info *info;
 426 {
 427   char buf[CGEN_MAX_INSN_SIZE];
 428   int buflen;
 429   int status;
 430
 431   /* Attempt to read the base part of the insn.  */
 432   buflen = cd->base_insn_bitsize / 8;
 433   status = (*info->read_memory_func) (pc, buf, buflen, info);
 434
 435   /* Try again with the minimum part, if min < base.  */
 436   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 437     {
 438       buflen = cd->min_insn_bitsize / 8;
 439       status = (*info->read_memory_func) (pc, buf, buflen, info);
 440     }
 441
 442   if (status != 0)
 443     {
 444       (*info->memory_error_func) (status, pc, info);
 445       return -1;
 446     }
 447
 448   return print_insn (cd, pc, info, buf, buflen);
 449 }
 450
 451 /* Main entry point.
 452    Print one instruction from PC on INFO->STREAM.
 453    Return the size of the instruction (in bytes).  */
 454
 455 typedef struct cpu_desc_list {
 456   struct cpu_desc_list *next;
 457   int isa;
 458   int mach;
 459   int endian;
 460   CGEN_CPU_DESC cd;
 461 } cpu_desc_list;
 462
 463 int
 464 print_insn_openrisc (pc, info)
 465      bfd_vma pc;
 466      disassemble_info *info;
 467 {
 468   static cpu_desc_list *cd_list = 0;
 469   cpu_desc_list *cl = 0;
 470   static CGEN_CPU_DESC cd = 0;
 471   static int prev_isa;
 472   static int prev_mach;
 473   static int prev_endian;
 474   int length;
 475   int isa,mach;
 476   int endian = (info->endian == BFD_ENDIAN_BIG
 477                 ? CGEN_ENDIAN_BIG
 478                 : CGEN_ENDIAN_LITTLE);
 479   enum bfd_architecture arch;
 480
 481   /* ??? gdb will set mach but leave the architecture as "unknown" */
 482 #ifndef CGEN_BFD_ARCH
 483 #define CGEN_BFD_ARCH bfd_arch_openrisc
 484 #endif
 485   arch = info->arch;
 486   if (arch == bfd_arch_unknown)
 487     arch = CGEN_BFD_ARCH;
 488
 489   /* There's no standard way to compute the machine or isa number
 490      so we leave it to the target.  */
 491 #ifdef CGEN_COMPUTE_MACH
 492   mach = CGEN_COMPUTE_MACH (info);
 493 #else
 494   mach = info->mach;
 495 #endif
 496
 497 #ifdef CGEN_COMPUTE_ISA
 498   isa = CGEN_COMPUTE_ISA (info);
 499 #else
 500   isa = info->insn_sets;
 501 #endif
 502
 503   /* If we've switched cpu's, try to find a handle we've used before */
 504   if (cd
 505       && (isa != prev_isa
 506           || mach != prev_mach
 507           || endian != prev_endian))
 508     {
 509       cd = 0;
 510       for (cl = cd_list; cl; cl = cl->next)
 511         {
 512           if (cl->isa == isa &&
 513               cl->mach == mach &&
 514               cl->endian == endian)
 515             {
 516               cd = cl->cd;
 517               break;
 518             }
 519         }
 520     }
 521
 522   /* If we haven't initialized yet, initialize the opcode table.  */
 523   if (! cd)
 524     {
 525       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 526       const char *mach_name;
 527
 528       if (!arch_type)
 529         abort ();
 530       mach_name = arch_type->printable_name;
 531
 532       prev_isa = isa;
 533       prev_mach = mach;
 534       prev_endian = endian;
 535       cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 536                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 537                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 538                                  CGEN_CPU_OPEN_END);
 539       if (!cd)
 540         abort ();
 541
 542       /* save this away for future reference */
 543       cl = xmalloc (sizeof (struct cpu_desc_list));
 544       cl->cd = cd;
 545       cl->isa = isa;
 546       cl->mach = mach;
 547       cl->endian = endian;
 548       cl->next = cd_list;
 549       cd_list = cl;
 550
 551       openrisc_cgen_init_dis (cd);
 552     }
 553
 554   /* We try to have as much common code as possible.
 555      But at this point some targets need to take over.  */
 556   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 557      but if not possible try to move this hook elsewhere rather than
 558      have two hooks.  */
 559   length = CGEN_PRINT_INSN (cd, pc, info);
 560   if (length > 0)
 561     return length;
 562   if (length < 0)
 563     return -1;
 564
 565   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 566   return cd->default_insn_bitsize / 8;
 567 }