opcodes/arm-opc.h

   1 /* Opcode table for the ARM.
   2
   3    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003, 2004
   4    Free Software Foundation, Inc.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20
  21 struct arm_opcode
  22 {
  23   unsigned long value, mask;    /* Recognise instruction if (op&mask)==value.  */
  24   char *assembler;              /* How to disassemble this instruction.  */
  25 };
  26
  27 struct thumb_opcode
  28 {
  29   unsigned short value, mask;   /* Recognise instruction if (op&mask)==value.  */
  30   char * assembler;             /* How to disassemble this instruction.  */
  31 };
  32
  33 /* Format of the assembler string :
  34
  35    %%                   %
  36    %<bitfield>d         print the bitfield in decimal
  37    %<bitfield>x         print the bitfield in hex
  38    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
  39    %<bitfield>W         print the bitfield plus one in decimal
  40    %<bitfield>r         print as an ARM register
  41    %<bitfield>f         print a floating point constant if >7 else a
  42                         floating point register
  43    %<code>y             print a single precision VFP reg.
  44                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
  45    %<code>z             print a double precision VFP reg
  46                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
  47    %c                   print condition code (always bits 28-31)
  48    %P                   print floating point precision in arithmetic insn
  49    %Q                   print floating point precision in ldf/stf insn
  50    %R                   print floating point rounding mode
  51    %<bitnum>'c          print specified char iff bit is one
  52    %<bitnum>`c          print specified char iff bit is zero
  53    %<bitnum>?ab         print a if bit is one else print b
  54    %p                   print 'p' iff bits 12-15 are 15
  55    %t                   print 't' iff bit 21 set and bit 24 clear
  56    %o                   print operand2 (immediate or register + shift)
  57    %a                   print address for ldr/str instruction
  58    %s                   print address for ldr/str halfword/signextend instruction
  59    %b                   print branch destination
  60    %B                   print arm BLX(1) destination
  61    %A                   print address for ldc/stc/ldf/stf instruction
  62    %m                   print register mask for ldm/stm instruction
  63    %C                   print the PSR sub type.
  64    %F                   print the COUNT field of a LFM/SFM instruction.
  65 IWMMXT specific format options:
  66    %<bitfield>g         print as an iWMMXt 64-bit register
  67    %<bitfield>G         print as an iWMMXt general purpose or control register
  68    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
  69    %Z                   print the Immediate of a WSHUFH instruction.
  70    %L                   print as an iWMMXt N/M width field.
  71    %l                   like 'A' except use byte offsets for 'B' & 'H' versions
  72 Thumb specific format options:
  73    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
  74    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
  75    %<bitfield>I         print bitfield as a signed decimal
  76                                 (top bit of range being the sign bit)
  77    %M                   print Thumb register mask
  78    %N                   print Thumb register mask (with LR)
  79    %O                   print Thumb register mask (with PC)
  80    %T                   print Thumb condition code (always bits 8-11)
  81    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  82    %<bitfield>B         print Thumb branch destination (signed displacement)
  83    %<bitfield>W         print (bitfield * 4) as a decimal
  84    %<bitfield>H         print (bitfield * 2) as a decimal
  85    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
  86    %e                   print arm SMI operand (bits 0..7,8..19).  */
  87
  88 /* Note: There is a partial ordering in this table - it must be searched from
  89    the top to obtain a correct match.  */
  90
  91 static const struct arm_opcode arm_opcodes[] =
  92 {
  93     /* ARM instructions.  */
  94     {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
  95     {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
  96     {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
  97     {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
  98     {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
  99     {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
 100     {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
 101
 102     /* ARM V6Z instructions.  */
 103     {0x01600070, 0x0ff000f0, "smi%c\t%e"},
 104
 105     /* ARM V6K instructions.  */
 106     {0xf57ff01f, 0xffffffff, "clrex"},
 107     {0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
 108     {0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
 109     {0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
 110     {0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
 111     {0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
 112     {0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
 113
 114     /* ARM V6K NOP hints.  */
 115     {0x0320f001, 0x0fffffff, "yield"},
 116     {0x0320f002, 0x0fffffff, "wfe"},
 117     {0x0320f003, 0x0fffffff, "wfi"},
 118     {0x0320f004, 0x0fffffff, "sev"},
 119     {0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
 120
 121     /* ARM V6 instructions.  */
 122     {0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
 123     {0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
 124     {0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"},
 125     {0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
 126     {0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"},
 127     {0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
 128     {0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
 129     {0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
 130     {0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"},
 131     {0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"},
 132     {0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"},
 133     {0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
 134     {0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
 135     {0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
 136     {0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
 137     {0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
 138     {0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
 139     {0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
 140     {0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
 141     {0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
 142     {0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
 143     {0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
 144     {0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
 145     {0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
 146     {0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
 147     {0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
 148     {0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
 149     {0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
 150     {0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
 151     {0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
 152     {0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
 153     {0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
 154     {0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
 155     {0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
 156     {0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
 157     {0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
 158     {0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
 159     {0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
 160     {0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
 161     {0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
 162     {0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
 163     {0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
 164     {0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
 165     {0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
 166     {0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
 167     {0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
 168     {0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
 169     {0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
 170     {0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
 171     {0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
 172     {0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
 173     {0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
 174     {0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"},
 175     {0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"},
 176     {0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"},
 177     {0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"},
 178     {0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"},
 179     {0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"},
 180     {0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"},
 181     {0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"},
 182     {0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"},
 183     {0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"},
 184     {0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"},
 185     {0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"},
 186     {0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"},
 187     {0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"},
 188     {0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"},
 189     {0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"},
 190     {0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"},
 191     {0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"},
 192     {0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"},
 193     {0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"},
 194     {0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"},
 195     {0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"},
 196     {0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"},
 197     {0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"},
 198     {0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
 199     {0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
 200     {0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
 201     {0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
 202     {0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
 203     {0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
 204     {0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
 205     {0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
 206     {0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
 207     {0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
 208     {0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
 209     {0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
 210     {0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
 211     {0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
 212     {0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
 213     {0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
 214     {0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
 215     {0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
 216     {0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
 217     {0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
 218     {0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
 219     {0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
 220     {0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
 221     {0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
 222     {0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
 223     {0xf1010000, 0xfffffc00, "setend\t%9?ble"},
 224     {0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
 225     {0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
 226     {0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 227     {0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 228     {0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 229     {0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 230     {0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
 231     {0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 232     {0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 233     {0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"},
 234     {0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
 235     {0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"},
 236     {0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"},
 237     {0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
 238     {0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
 239     {0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 240     {0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
 241     {0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 242     {0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
 243     {0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"},
 244     {0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"},
 245     {0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
 246
 247     /* V5J instruction.  */
 248     {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
 249
 250     /* XScale instructions.  */
 251     {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
 252     {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
 253     {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 254     {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 255     {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 256     {0xf450f000, 0xfc70f000, "pld\t%a"},
 257
 258     /* Intel Wireless MMX technology instructions.  */
 259 #define FIRST_IWMMXT_INSN 0x0e130130
 260 #define IWMMXT_INSN_COUNT 47
 261     {0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 262     {0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 263     {0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 264     {0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 265     {0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 266     {0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 267     {0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 268     {0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 269     {0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 270     {0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 271     {0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 272     {0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 273     {0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 274     {0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 275     {0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 276     {0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 277     {0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 278     {0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 279     {0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 280     {0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 281     {0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 282     {0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 283     {0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 284     {0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 285     {0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 286     {0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"},
 287     {0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 288     {0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 289     {0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"},
 290     {0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 291     {0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 292     {0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 293     {0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 294     {0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 295     {0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 296     {0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 297     {0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 298     {0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 299     {0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 300     {0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 301     {0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 302     {0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 303     {0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 304     {0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 305     {0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"},
 306     {0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 307     {0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 308     {0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 309     {0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 310
 311     /* V5 Instructions.  */
 312     {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
 313     {0xfa000000, 0xfe000000, "blx\t%B"},
 314     {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
 315     {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
 316     {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"},
 317     {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"},
 318     {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 319     {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 320     {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 321
 322     /* V5E "El Segundo" Instructions.  */
 323     {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
 324     {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
 325     {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 326     {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 327     {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 328     {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 329
 330     {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 331     {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
 332
 333     {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 334     {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 335     {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 336     {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
 337
 338     {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
 339     {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
 340     {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
 341     {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
 342
 343     {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
 344     {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
 345
 346     {0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15r, %0-3r, %16-19r"},
 347     {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
 348     {0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15r, %0-3r, %16-19r"},
 349     {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
 350
 351     /* ARM Instructions.  */
 352     {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"},
 353     {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"},
 354     {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
 355     {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
 356     {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
 357     {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
 358     {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
 359     {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
 360     {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
 361     {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
 362     {0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
 363     {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
 364     {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
 365     {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
 366     {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
 367     {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
 368     {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
 369     {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
 370     {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
 371     {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
 372     {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
 373     {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
 374     {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
 375     {0x06000010, 0x0e000010, "undefined"},
 376     {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
 377     {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
 378     {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
 379     {0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
 380     {0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
 381
 382     /* Floating point coprocessor (FPA) instructions */
 383     {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 384     {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 385     {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 386     {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 387     {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 388     {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 389     {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 390     {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 391     {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 392     {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 393     {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 394     {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 395     {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 396     {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 397     {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 398     {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 399     {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 400     {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 401     {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 402     {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 403     {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 404     {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 405     {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 406     {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 407     {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 408     {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 409     {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 410     {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 411     {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 412     {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 413     {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 414     {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 415     {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 416     {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 417     {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 418     {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 419     {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 420     {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 421     {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 422     {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 423     {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 424     {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 425     {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 426
 427     /* Floating point coprocessor (VFP) instructions */
 428     {0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"},
 429     {0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"},
 430     {0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"},
 431     {0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %1y"},
 432     {0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"},
 433     {0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"},
 434     {0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"},
 435     {0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%1y"},
 436     {0x0eb00b40, 0x0fff0ff0, "fcpyd%c\t%1z, %0z"},
 437     {0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%1y, %0y"},
 438     {0x0eb70ac0, 0x0fff0fd0, "fcvtds%c\t%1z, %0y"},
 439     {0x0eb70bc0, 0x0fbf0ff0, "fcvtsd%c\t%1y, %0z"},
 440     {0x0e800b00, 0x0ff00ff0, "fdivd%c\t%1z, %2z, %0z"},
 441     {0x0e800a00, 0x0fb00f50, "fdivs%c\t%1y, %2y, %0y"},
 442     {0x0d100b00, 0x0f700f00, "fldd%c\t%1z, %A"},
 443     {0x0c900b00, 0x0fd00f00, "fldmia%0?xd%c\t%16-19r%21'!, %3z"},
 444     {0x0d300b00, 0x0ff00f00, "fldmdb%0?xd%c\t%16-19r!, %3z"},
 445     {0x0d100a00, 0x0f300f00, "flds%c\t%1y, %A"},
 446     {0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %3y"},
 447     {0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %3y"},
 448     {0x0e000b00, 0x0ff00ff0, "fmacd%c\t%1z, %2z, %0z"},
 449     {0x0e000a00, 0x0fb00f50, "fmacs%c\t%1y, %2y, %0y"},
 450     {0x0e200b10, 0x0ff00fff, "fmdhr%c\t%2z, %12-15r"},
 451     {0x0e000b10, 0x0ff00fff, "fmdlr%c\t%2z, %12-15r"},
 452     {0x0c400b10, 0x0ff00ff0, "fmdrr%c\t%0z, %12-15r, %16-19r"},
 453     {0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %2z"},
 454     {0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %2z"},
 455     {0x0c500b10, 0x0ff00ff0, "fmrrd%c\t%12-15r, %16-19r, %0z"},
 456     {0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %4y"},
 457     {0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %2y"},
 458     {0x0ef1fa10, 0x0fffffff, "fmstat%c"},
 459     {0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
 460     {0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
 461     {0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
 462     {0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
 463     {0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},
 464     {0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"},
 465     {0x0e100b00, 0x0ff00ff0, "fmscd%c\t%1z, %2z, %0z"},
 466     {0x0e100a00, 0x0fb00f50, "fmscs%c\t%1y, %2y, %0y"},
 467     {0x0e000a10, 0x0ff00f7f, "fmsr%c\t%2y, %12-15r"},
 468     {0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %4y"},
 469     {0x0e200b00, 0x0ff00ff0, "fmuld%c\t%1z, %2z, %0z"},
 470     {0x0e200a00, 0x0fb00f50, "fmuls%c\t%1y, %2y, %0y"},
 471     {0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
 472     {0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
 473     {0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
 474     {0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
 475     {0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
 476     {0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"},
 477     {0x0eb10b40, 0x0fff0ff0, "fnegd%c\t%1z, %0z"},
 478     {0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%1y, %0y"},
 479     {0x0e000b40, 0x0ff00ff0, "fnmacd%c\t%1z, %2z, %0z"},
 480     {0x0e000a40, 0x0fb00f50, "fnmacs%c\t%1y, %2y, %0y"},
 481     {0x0e100b40, 0x0ff00ff0, "fnmscd%c\t%1z, %2z, %0z"},
 482     {0x0e100a40, 0x0fb00f50, "fnmscs%c\t%1y, %2y, %0y"},
 483     {0x0e200b40, 0x0ff00ff0, "fnmuld%c\t%1z, %2z, %0z"},
 484     {0x0e200a40, 0x0fb00f50, "fnmuls%c\t%1y, %2y, %0y"},
 485     {0x0eb80bc0, 0x0fff0fd0, "fsitod%c\t%1z, %0y"},
 486     {0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%1y, %0y"},
 487     {0x0eb10bc0, 0x0fff0ff0, "fsqrtd%c\t%1z, %0z"},
 488     {0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%1y, %0y"},
 489     {0x0d000b00, 0x0f700f00, "fstd%c\t%1z, %A"},
 490     {0x0c800b00, 0x0fd00f00, "fstmia%0?xd%c\t%16-19r%21'!, %3z"},
 491     {0x0d200b00, 0x0ff00f00, "fstmdb%0?xd%c\t%16-19r!, %3z"},
 492     {0x0d000a00, 0x0f300f00, "fsts%c\t%1y, %A"},
 493     {0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %3y"},
 494     {0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %3y"},
 495     {0x0e300b40, 0x0ff00ff0, "fsubd%c\t%1z, %2z, %0z"},
 496     {0x0e300a40, 0x0fb00f50, "fsubs%c\t%1y, %2y, %0y"},
 497     {0x0ebc0b40, 0x0fbe0f70, "fto%16?sui%7'zd%c\t%1y, %0z"},
 498     {0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%1y, %0y"},
 499     {0x0eb80b40, 0x0fff0fd0, "fuitod%c\t%1z, %0y"},
 500     {0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%1y, %0y"},
 501
 502     /* Cirrus coprocessor instructions.  */
 503     {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 504     {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 505     {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 506     {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 507     {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 508     {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 509     {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 510     {0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 511     {0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 512     {0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 513     {0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 514     {0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 515     {0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 516     {0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 517     {0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 518     {0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 519     {0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 520     {0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 521     {0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 522     {0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 523     {0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 524     {0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 525     {0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 526     {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 527     {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 528     {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 529     {0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 530     {0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 531     {0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 532     {0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 533     {0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 534     {0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 535     {0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 536     {0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 537     {0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 538     {0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 539     {0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 540     {0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 541     {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 542     {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 543     {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 544     {0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 545     {0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 546     {0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 547     {0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 548     {0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 549     {0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 550     {0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 551     {0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 552     {0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 553     {0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 554     {0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 555     {0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 556     {0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 557     {0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 558     {0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 559     {0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 560     {0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 561     {0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 562     {0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 563     {0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 564     {0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 565     {0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 566     {0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 567     {0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 568     {0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 569     {0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 570     {0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 571     {0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 572     {0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 573     {0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 574     {0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 575     {0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 576     {0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 577     {0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 578     {0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 579     {0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 580     {0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 581     {0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 582     {0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 583     {0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 584     {0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 585     {0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 586     {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 587
 588     /* Generic coprocessor instructions */
 589     {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
 590     {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
 591     {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 592     {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 593     {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 594     {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
 595     {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
 596
 597     /* The rest.  */
 598     {0x00000000, 0x00000000, "undefined instruction %0-31x"},
 599     {0x00000000, 0x00000000, 0}
 600 };
 601
 602 #define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */
 603
 604 static const struct thumb_opcode thumb_opcodes[] =
 605 {
 606   /* Thumb instructions.  */
 607
 608   /* ARM V6.  */
 609   {0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"},
 610   {0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"},
 611   {0x4600, 0xffc0, "cpy\t%0-2r, %3-5r"},
 612   {0xba00, 0xffc0, "rev\t%0-2r, %3-5r"},
 613   {0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"},
 614   {0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"},
 615   {0xb650, 0xfff7, "setend\t%3?ble\t"},
 616   {0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"},
 617   {0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"},
 618   {0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"},
 619   {0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"},
 620
 621   /* ARM V5 ISA extends Thumb.  */
 622   {0xbe00, 0xff00, "bkpt\t%0-7x"},
 623   {0x4780, 0xff87, "blx\t%3-6r"},       /* note: 4 bit register number.  */
 624   /* Note: this is BLX(2).  BLX(1) is done in arm-dis.c/print_insn_thumb()
 625      as an extension of the special processing there for Thumb BL.
 626      BL and BLX(1) involve 2 successive 16-bit instructions, which must
 627      always appear together in the correct order.  So, the empty
 628      string is put in this table, and the string interpreter takes <empty>
 629      to mean it has a pair of BL-ish instructions.  */
 630   {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},
 631   /* Format 5 instructions do not update the PSR.  */
 632   {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"},
 633   /* Format 4.  */
 634   {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"},
 635   {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"},
 636   {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"},
 637   {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"},
 638   {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"},
 639   {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"},
 640   {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"},
 641   {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"},
 642   {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"},
 643   {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"},
 644   {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"},
 645   {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"},
 646   {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"},
 647   {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"},
 648   {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"},
 649   {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"},
 650   /* format 13 */
 651   {0xB000, 0xFF80, "add\tsp, #%0-6W"},
 652   {0xB080, 0xFF80, "sub\tsp, #%0-6W"},
 653   /* format 5 */
 654   {0x4700, 0xFF80, "bx\t%S"},
 655   {0x4400, 0xFF00, "add\t%D, %S"},
 656   {0x4500, 0xFF00, "cmp\t%D, %S"},
 657   {0x4600, 0xFF00, "mov\t%D, %S"},
 658   /* format 14 */
 659   {0xB400, 0xFE00, "push\t%N"},
 660   {0xBC00, 0xFE00, "pop\t%O"},
 661   /* format 2 */
 662   {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"},
 663   {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"},
 664   {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"},
 665   {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"},
 666   /* format 8 */
 667   {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
 668   {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},
 669   {0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"},
 670   /* format 7 */
 671   {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"},
 672   {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"},
 673   /* format 1 */
 674   {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"},
 675   {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"},
 676   {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"},
 677   /* format 3 */
 678   {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"},
 679   {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"},
 680   {0x3000, 0xF800, "add\t%8-10r, #%0-7d"},
 681   {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"},
 682   /* format 6 */
 683   {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
 684   /* format 9 */
 685   {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
 686   {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
 687   {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
 688   {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
 689   /* format 10 */
 690   {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"},
 691   {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"},
 692   /* format 11 */
 693   {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"},
 694   {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"},
 695   /* format 12 */
 696   {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
 697   {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"},
 698   /* format 15 */
 699   {0xC000, 0xF800, "stmia\t%8-10r!,%M"},
 700   {0xC800, 0xF800, "ldmia\t%8-10r!,%M"},
 701   /* format 18 */
 702   {0xE000, 0xF800, "b\t%0-10B"},
 703   {0xE800, 0xF800, "undefined"},
 704   /* format 19 */
 705   {0xF000, 0xF800, ""}, /* special processing required in disassembler */
 706   {0xF800, 0xF800, "second half of BL instruction %0-15x"},
 707   /* format 16 */
 708   {0xD000, 0xFF00, "beq\t%0-7B"},
 709   {0xD100, 0xFF00, "bne\t%0-7B"},
 710   {0xD200, 0xFF00, "bcs\t%0-7B"},
 711   {0xD300, 0xFF00, "bcc\t%0-7B"},
 712   {0xD400, 0xFF00, "bmi\t%0-7B"},
 713   {0xD500, 0xFF00, "bpl\t%0-7B"},
 714   {0xD600, 0xFF00, "bvs\t%0-7B"},
 715   {0xD700, 0xFF00, "bvc\t%0-7B"},
 716   {0xD800, 0xFF00, "bhi\t%0-7B"},
 717   {0xD900, 0xFF00, "bls\t%0-7B"},
 718   {0xDA00, 0xFF00, "bge\t%0-7B"},
 719   {0xDB00, 0xFF00, "blt\t%0-7B"},
 720   {0xDC00, 0xFF00, "bgt\t%0-7B"},
 721   {0xDD00, 0xFF00, "ble\t%0-7B"},
 722   /* format 17 */
 723   {0xDE00, 0xFF00, "bal\t%0-7B"},
 724   {0xDF00, 0xFF00, "swi\t%0-7d"},
 725   /* format 9 */
 726   {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
 727   {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
 728   {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
 729   {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
 730   /* the rest */
 731   {0x0000, 0x0000, "undefined instruction %0-15x"},
 732   {0x0000, 0x0000, 0}
 733 };
 734
 735 #define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \
 736                      ^ 0x200000) - 0x200000) /* 23bit */
 737