| blob | 718197b973097c174ebc88e9cfda4ea774eae6fe |
1 2006-05-02 Ben Elliston <bje@au.ibm.com>
3 * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
4 field unsigned.
6 * sb.h (sb_list_vector): Move to sb.c.
7 * sb.c (free_list): Use type of sb_list_vector directly.
8 (sb_build): Fix off-by-one error in assertion about `size'.
10 2006-05-01 Ben Elliston <bje@au.ibm.com>
12 * listing.c (listing_listing): Remove useless loop.
13 * macro.c (macro_expand): Remove is_positional local variable.
14 * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
15 and simplify surrounding expressions, where possible.
16 (assign_symbol): Likewise.
17 (s_weakref): Likewise.
18 * symbols.c (colon): Likewise.
20 2006-05-01 James Lemke <jwlemke@wasabisystems.com>
22 * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
24 2006-04-30 Thiemo Seufer <ths@mips.com>
25 David Ung <davidu@mips.com>
27 * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
28 (mips_immed): New table that records various handling of udi
29 instruction patterns.
30 (mips_ip): Adds udi handling.
32 2006-04-28 Alan Modra <amodra@bigpond.net.au>
34 * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
35 of list rather than beginning.
37 2006-04-26 Julian Brown <julian@codesourcery.com>
39 * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
40 (is_quarter_float): Rename from above. Simplify slightly.
41 (parse_qfloat_immediate): Parse a "quarter precision" floating-point
42 number.
43 (parse_neon_mov): Parse floating-point constants.
44 (neon_qfloat_bits): Fix encoding.
45 (neon_cmode_for_move_imm): Tweak to use floating-point encoding in
46 preference to integer encoding when using the F32 type.
48 2006-04-26 Julian Brown <julian@codesourcery.com>
50 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
51 zero-initialising structures containing it will lead to invalid types).
52 (arm_it): Add vectype to each operand.
53 (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
54 defined field.
55 (neon_typed_alias): New structure. Extra information for typed
56 register aliases.
57 (reg_entry): Add neon type info field.
58 (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
59 Break out alternative syntax for coprocessor registers, etc. into...
60 (arm_reg_alt_syntax): New function. Alternate syntax handling broken
61 out from arm_reg_parse.
62 (parse_neon_type): Move. Return SUCCESS/FAIL.
63 (first_error): New function. Call to ensure first error which occurs is
64 reported.
65 (parse_neon_operand_type): Parse exactly one type.
66 (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
67 (parse_typed_reg_or_scalar): New function. Handle core of both
68 arm_typed_reg_parse and parse_scalar.
69 (arm_typed_reg_parse): Parse a register with an optional type.
70 (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
71 result.
72 (parse_scalar): Parse a Neon scalar with optional type.
73 (parse_reg_list): Use first_error.
74 (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
75 (neon_alias_types_same): New function. Return true if two (alias) types
76 are the same.
77 (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
78 of elements.
79 (insert_reg_alias): Return new reg_entry not void.
80 (insert_neon_reg_alias): New function. Insert type/index information as
81 well as register for alias.
82 (create_neon_reg_alias): New function. Parse .dn/.qn directives and
83 make typed register aliases accordingly.
84 (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
85 of line.
86 (s_unreq): Delete type information if present.
87 (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
88 (s_arm_unwind_save_mmxwcg): Likewise.
89 (s_arm_unwind_movsp): Likewise.
90 (s_arm_unwind_setfp): Likewise.
91 (parse_shift): Likewise.
92 (parse_shifter_operand): Likewise.
93 (parse_address): Likewise.
94 (parse_tb): Likewise.
95 (tc_arm_regname_to_dw2regnum): Likewise.
96 (md_pseudo_table): Add dn, qn.
97 (parse_neon_mov): Handle typed operands.
98 (parse_operands): Likewise.
99 (neon_type_mask): Add N_SIZ.
100 (N_ALLMODS): New macro.
101 (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
102 (el_type_of_type_chk): Add some safeguards.
103 (modify_types_allowed): Fix logic bug.
104 (neon_check_type): Handle operands with types.
105 (neon_three_same): Remove redundant optional arg handling.
106 (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
107 (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
108 (do_neon_step): Adjust accordingly.
109 (neon_cmode_for_logic_imm): Use first_error.
110 (do_neon_bitfield): Call neon_check_type.
111 (neon_dyadic): Rename to...
112 (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
113 to allow modification of type of the destination.
114 (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
115 (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
116 (do_neon_compare): Make destination be an untyped bitfield.
117 (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
118 (neon_mul_mac): Return early in case of errors.
119 (neon_move_immediate): Use first_error.
120 (neon_mac_reg_scalar_long): Fix type to include scalar.
121 (do_neon_dup): Likewise.
122 (do_neon_mov): Likewise (in several places).
123 (do_neon_tbl_tbx): Fix type.
124 (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
125 (do_neon_ld_dup): Exit early in case of errors and/or use
126 first_error.
127 (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
128 Handle .dn/.qn directives.
129 (REGDEF): Add zero for reg_entry neon field.
131 2006-04-26 Julian Brown <julian@codesourcery.com>
133 * config/tc-arm.c (limits.h): Include.
134 (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
135 (fpu_vfp_v3_or_neon_ext): Declare constants.
136 (neon_el_type): New enumeration of types for Neon vector elements.
137 (neon_type_el): New struct. Define type and size of a vector element.
138 (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
139 instruction.
140 (neon_type): Define struct. The type of an instruction.
141 (arm_it): Add 'vectype' for the current instruction.
142 (isscalar, immisalign, regisimm, isquad): New predicates for operands.
143 (vfp_sp_reg_pos): Rename to...
144 (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
145 tags.
146 (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
147 (Neon D or Q register).
148 (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
149 register.
150 (GE_OPT_PREFIX_BIG): Define constant, for use in...
151 (my_get_expression): Allow above constant as argument to accept
152 64-bit constants with optional prefix.
153 (arm_reg_parse): Add extra argument to return the specific type of
154 register in when either a D or Q register (REG_TYPE_NDQ) is
155 requested. Can be NULL.
156 (parse_scalar): New function. Parse Neon scalar (vector reg and index).
157 (parse_reg_list): Update for new arm_reg_parse args.
158 (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
159 (parse_neon_el_struct_list): New function. Parse element/structure
160 register lists for VLD<n>/VST<n> instructions.
161 (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
162 (s_arm_unwind_save_mmxwr): Likewise.
163 (s_arm_unwind_save_mmxwcg): Likewise.
164 (s_arm_unwind_movsp): Likewise.
165 (s_arm_unwind_setfp): Likewise.
166 (parse_big_immediate): New function. Parse an immediate, which may be
167 64 bits wide. Put results in inst.operands[i].
168 (parse_shift): Update for new arm_reg_parse args.
169 (parse_address): Likewise. Add parsing of alignment specifiers.
170 (parse_neon_mov): Parse the operands of a VMOV instruction.
171 (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
172 OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
173 OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
174 OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
175 (parse_operands): Handle new codes above.
176 (encode_arm_vfp_sp_reg): Rename to...
177 (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
178 selected VFP version only supports D0-D15.
179 (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
180 (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
181 (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
182 (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
183 encode_arm_vfp_reg name, and allow 32 D regs.
184 (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
185 (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
186 regs.
187 (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
188 (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
189 constant-load and conversion insns introduced with VFPv3.
190 (neon_tab_entry): New struct.
191 (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
192 those which are the targets of pseudo-instructions.
193 (neon_opc): Enumerate opcodes, use as indices into...
194 (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
195 (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
196 (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
197 (NEON_ENC_DUP): Define meaningful helper macros to look up values in
198 neon_enc_tab.
199 (neon_shape): Enumerate shapes (permitted register widths, etc.) for
200 Neon instructions.
201 (neon_type_mask): New. Compact type representation for type checking.
202 (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
203 permitted type combinations.
204 (N_IGNORE_TYPE): New macro.
205 (neon_check_shape): New function. Check an instruction shape for
206 multiple alternatives. Return the specific shape for the current
207 instruction.
208 (neon_modify_type_size): New function. Modify a vector type and size,
209 depending on the bit mask in argument 1.
210 (neon_type_promote): New function. Convert a given "key" type (of an
211 operand) into the correct type for a different operand, based on a bit
212 mask.
213 (type_chk_of_el_type): New function. Convert a type and size into the
214 compact representation used for type checking.
215 (el_type_of_type_ckh): New function. Reverse of above (only when a
216 single bit is set in the bit mask).
217 (modify_types_allowed): New function. Alter a mask of allowed types
218 based on a bit mask of modifications.
219 (neon_check_type): New function. Check the type of the current
220 instruction against the variable argument list. The "key" type of the
221 instruction is returned.
222 (neon_dp_fixup): New function. Fill in and modify instruction bits for
223 a Neon data-processing instruction depending on whether we're in ARM
224 mode or Thumb-2 mode.
225 (neon_logbits): New function.
226 (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
227 (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
228 (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
229 (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
230 (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
231 (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
232 (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
233 (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
234 (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
235 (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
236 (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
237 (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
238 (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
239 (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
240 (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
241 (neon_move_immediate, do_neon_mvn, neon_mixed_length)
242 (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
243 (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
244 (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
245 (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
246 (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
247 (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
248 (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
249 (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
250 (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
251 helpers.
252 (parse_neon_type): New function. Parse Neon type specifier.
253 (opcode_lookup): Allow parsing of Neon type specifiers.
254 (REGNUM2, REGSETH, REGSET2): New macros.
255 (reg_names): Add new VFPv3 and Neon registers.
256 (NUF, nUF, NCE, nCE): New macros for opcode table.
257 (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
258 fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
259 fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
260 Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
261 vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
262 vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
263 vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
264 vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
265 vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
266 vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
267 vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
268 vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
269 vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
270 vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
271 fto[us][lh][sd].
272 (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
273 (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
274 (arm_option_cpu_value): Add vfp3 and neon.
275 (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
276 VFPv1 attribute.
278 2006-04-25 Bob Wilson <bob.wilson@acm.org>
280 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
281 syntax instead of hardcoded opcodes with ".w18" suffixes.
282 (wide_branch_opcode): New.
283 (build_transition): Use it to check for wide branch opcodes with
284 either ".w18" or ".w15" suffixes.
286 2006-04-25 Bob Wilson <bob.wilson@acm.org>
288 * config/tc-xtensa.c (xtensa_create_literal_symbol,
289 xg_assemble_literal, xg_assemble_literal_space): Do not set the
290 frag's is_literal flag.
292 2006-04-25 Bob Wilson <bob.wilson@acm.org>
294 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
296 2006-04-23 Kazu Hirata <kazu@codesourcery.com>
298 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
299 config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
300 config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
301 config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
302 config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
304 2005-04-20 Paul Brook <paul@codesourcery.com>
306 * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
307 all targets.
308 (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
310 2006-04-19 Alan Modra <amodra@bigpond.net.au>
312 * Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
313 (CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
314 Make some cpus unsupported on ELF. Run "make dep-am".
315 * Makefile.in: Regenerate.
317 2006-04-19 Alan Modra <amodra@bigpond.net.au>
319 * configure.in (--enable-targets): Indent help message.
320 * configure: Regenerate.
322 2006-04-18 H.J. Lu <hongjiu.lu@intel.com>
324 PR gas/2533
325 * config/tc-i386.c (i386_immediate): Check illegal immediate
326 register operand.
328 2006-04-18 Alan Modra <amodra@bigpond.net.au>
330 * config/tc-i386.c: Formatting.
331 (output_disp, output_imm): ISO C90 params.
333 * frags.c (frag_offset_fixed_p): Constify args.
334 * frags.h (frag_offset_fixed_p): Ditto.
336 * config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
337 (COFF_MAGIC): Delete.
339 * config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
341 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
343 * po/POTFILES.in: Regenerated.
345 2006-04-16 Mark Mitchell <mark@codesourcery.com>
347 * doc/as.texinfo: Mention that some .type syntaxes are not
348 supported on all architectures.
350 2006-04-14 Sterling Augustine <sterling@tensilica.com>
352 * config/tc-xtensa.c (emit_single_op): Do not relax MOVI
353 instructions when such transformations have been disabled.
355 2006-04-10 Sterling Augustine <sterling@tensilica.com>
357 * config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
358 symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
359 (xtensa_fix_close_loop_end_frags): Use the recorded values instead of
360 decoding the loop instructions. Remove current_offset variable.
361 (xtensa_fix_short_loop_frags): Likewise.
362 (min_bytes_to_other_loop_end): Remove current_offset argument.
364 2006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
366 * config/tc-z80.c (z80_optimize_expr): Removed.
367 * config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
369 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
371 * gas/config/tc-avr.c (mcu_types): Add support for attiny261,
372 attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
373 attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
374 atmega644, atmega329, atmega3290, atmega649, atmega6490,
375 atmega406, atmega640, atmega1280, atmega1281, at90can32,
376 at90can64, at90usb646, at90usb647, at90usb1286 and
377 at90usb1287.
378 Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
380 2006-04-07 Paul Brook <paul@codesourcery.com>
382 * config/tc-arm.c (parse_operands): Set default error message.
384 2006-04-07 Paul Brook <paul@codesourcery.com>
386 * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
388 2006-04-07 Paul Brook <paul@codesourcery.com>
390 * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
392 2006-04-07 Paul Brook <paul@codesourcery.com>
394 * config/tc-arm.c (THUMB2_LOAD_BIT): Define.
395 (move_or_literal_pool): Handle Thumb-2 instructions.
396 (do_t_ldst): Call move_or_literal_pool for =N addressing modes.
398 2006-04-07 Alan Modra <amodra@bigpond.net.au>
400 PR 2512.
401 * config/tc-i386.c (match_template): Move 64-bit operand tests
402 inside loop.
404 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
406 * po/Make-in: Add install-html target.
407 * Makefile.am: Add install-html and install-html-recursive targets.
408 * Makefile.in: Regenerate.
409 * configure.in: AC_SUBST datarootdir, docdir, htmldir.
410 * configure: Regenerate.
411 * doc/Makefile.am: Add install-html and install-html-am targets.
412 * doc/Makefile.in: Regenerate.
414 2006-04-06 Alan Modra <amodra@bigpond.net.au>
416 * frags.c (frag_offset_fixed_p): Reinitialise offset before
417 second scan.
419 2006-04-05 Richard Sandiford <richard@codesourcery.com>
420 Daniel Jacobowitz <dan@codesourcery.com>
422 * config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
423 (GOTT_BASE, GOTT_INDEX): New.
424 (tc_gen_reloc): Don't alter relocations against GOTT_BASE and
425 GOTT_INDEX when generating VxWorks PIC.
426 * configure.tgt (sparc*-*-vxworks*): Remove this special case;
427 use the generic *-*-vxworks* stanza instead.
429 2006-04-04 Alan Modra <amodra@bigpond.net.au>
431 PR 997
432 * frags.c (frag_offset_fixed_p): New function.
433 * frags.h (frag_offset_fixed_p): Declare.
434 * expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
435 (resolve_expression): Likewise.
437 2006-04-03 Sterling Augustine <sterling@tensilica.com>
439 * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
440 of the same length but different numbers of slots.
442 2006-03-30 Andreas Schwab <schwab@suse.de>
444 * configure.in: Fix help string for --enable-targets option.
445 * configure: Regenerate.
447 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
449 * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
450 (m68k_ip): ... here. Use for all chips. Protect against buffer
451 overrun and avoid excessive copying.
453 * config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
454 m68020_control_regs, m68040_control_regs, m68060_control_regs,
455 mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
456 mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
457 mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
458 (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
459 mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
460 mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
461 mcf5282_ctrl, mcfv4e_ctrl): ... these.
462 (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
463 (struct m68k_cpu): Change chip field to control_regs.
464 (current_chip): Remove.
465 (control_regs): New.
466 (m68k_archs, m68k_extensions): Adjust.
467 (m68k_cpus): Reorder to be in cpu number order. Adjust.
468 (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
469 (find_cf_chip): Reimplement for new organization of cpu table.
470 (select_control_regs): Remove.
471 (mri_chip): Adjust.
472 (struct save_opts): Save control regs, not chip.
473 (s_save, s_restore): Adjust.
474 (m68k_lookup_cpu): Give deprecated warning when necessary.
475 (m68k_init_arch): Adjust.
476 (md_show_usage): Adjust for new cpu table organization.
478 2006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
480 * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
481 * config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
482 * config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
483 "elf/bfin.h".
484 (GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
485 (any_gotrel): New rule.
486 (got): Use it, and create Expr_Node_GOT_Reloc nodes.
487 * config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
488 "elf/bfin.h".
489 (DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
490 (bfin_pic_ptr): New function.
491 (md_pseudo_table): Add it for ".picptr".
492 (OPTION_FDPIC): New macro.
493 (md_longopts): Add -mfdpic.
494 (md_parse_option): Handle it.
495 (md_begin): Set BFD flags.
496 (md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
497 (bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
498 us for GOT relocs.
499 * Makefile.am (bfin-parse.o): Update dependencies.
500 (DEPTC_bfin_elf): Likewise.
501 * Makefile.in: Regenerate.
503 2006-03-25 Richard Sandiford <richard@codesourcery.com>
505 * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
506 mcfemac instead of mcfmac.
508 2006-03-23 Michael Matz <matz@suse.de>
510 * config/tc-i386.c (type_names): Correct placement of 'static'.
511 (reloc): Map some more relocs to their 64 bit counterpart when
512 size is 8.
513 (output_insn): Work around breakage if DEBUG386 is defined.
514 (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
515 needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
516 BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
517 different from i386.
518 (output_imm): Ditto.
519 (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
520 Imm64.
521 (md_convert_frag): Jumps can now be larger than 2GB away, error
522 out in that case.
523 (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
524 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
526 2006-03-22 Richard Sandiford <richard@codesourcery.com>
527 Daniel Jacobowitz <dan@codesourcery.com>
528 Phil Edwards <phil@codesourcery.com>
529 Zack Weinberg <zack@codesourcery.com>
530 Mark Mitchell <mark@codesourcery.com>
531 Nathan Sidwell <nathan@codesourcery.com>
533 * config/tc-mips.c (mips_target_format): Handle vxworks targets.
534 (md_begin): Complain about -G being used for PIC. Don't change
535 the text, data and bss alignments on VxWorks.
536 (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
537 generating VxWorks PIC.
538 (load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
539 (macro): Likewise, but do not treat la $25 specially for
540 VxWorks PIC, and do not handle jal.
541 (OPTION_MVXWORKS_PIC): New macro.
542 (md_longopts): Add -mvxworks-pic.
543 (md_parse_option): Don't complain about using PIC and -G together here.
544 Handle OPTION_MVXWORKS_PIC.
545 (md_estimate_size_before_relax): Always use the first relaxation
546 sequence on VxWorks.
547 * config/tc-mips.h (VXWORKS_PIC): New.
549 2006-03-21 Paul Brook <paul@codesourcery.com>
551 * config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
553 2006-03-21 Sterling Augustine <sterling@tensilica.com>
555 * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
556 (xtensa_setup_hw_workarounds): Set this new flag for older hardware.
557 (get_loop_align_size): New.
558 (xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
559 (xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
560 (get_text_align_power): Rewrite to handle inputs in the range 2-8.
561 (get_noop_aligned_address): Use get_loop_align_size.
562 (get_aligned_diff): Likewise.
564 2006-03-21 Paul Brook <paul@codesourcery.com>
566 * config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
568 2006-03-20 Paul Brook <paul@codesourcery.com>
570 * config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
571 (do_t_branch): Encode branches inside IT blocks as unconditional.
572 (do_t_cps): New function.
573 (do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
574 do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
575 (opcode_lookup): Allow conditional suffixes on all instructions in
576 Thumb mode.
577 (md_assemble): Advance condexec state before checking for errors.
578 (insns): Use do_t_cps.
580 2006-03-20 Paul Brook <paul@codesourcery.com>
582 * config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
583 outputting the insn.
585 2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
587 * config/tc-vax.c: Update copyright year.
588 * config/tc-vax.h: Likewise.
590 2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
592 * config/tc-vax.c (md_chars_to_number): Used only locally, so
593 make it static.
594 * config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
596 2006-03-17 Paul Brook <paul@codesourcery.com>
598 * config/tc-arm.c (insns): Add ldm and stm.
600 2006-03-17 Ben Elliston <bje@au.ibm.com>
602 PR gas/2446
603 * doc/as.texinfo (Ident): Document this directive more thoroughly.
605 2006-03-16 Paul Brook <paul@codesourcery.com>
607 * config/tc-arm.c (insns): Add "svc".
609 2006-03-13 Bob Wilson <bob.wilson@acm.org>
611 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
612 flag and avoid double underscore prefixes.
614 2006-03-10 Paul Brook <paul@codesourcery.com>
616 * config/tc-arm.c (md_begin): Handle EABIv5.
617 (arm_eabis): Add EF_ARM_EABI_VER5.
618 * doc/c-arm.texi: Document -meabi=5.
620 2006-03-10 Ben Elliston <bje@au.ibm.com>
622 * app.c (do_scrub_chars): Simplify string handling.
624 2006-03-07 Richard Sandiford <richard@codesourcery.com>
625 Daniel Jacobowitz <dan@codesourcery.com>
626 Zack Weinberg <zack@codesourcery.com>
627 Nathan Sidwell <nathan@codesourcery.com>
628 Paul Brook <paul@codesourcery.com>
629 Ricardo Anguiano <anguiano@codesourcery.com>
630 Phil Edwards <phil@codesourcery.com>
632 * config/tc-arm.c (md_apply_fix): Install a value of zero into a
633 BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
634 R_ARM_ABS12 reloc.
635 (tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
636 relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
637 relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
639 2006-03-06 Bob Wilson <bob.wilson@acm.org>
641 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
642 even when using the text-section-literals option.
644 2006-03-06 Nathan Sidwell <nathan@codesourcery.com>
646 * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
647 and cf.
648 (m68k_ip): <case 'J'> Check we have some control regs.
649 (md_parse_option): Allow raw arch switch.
650 (m68k_init_arch): Better detection of arch/cpu mismatch. Detect
651 whether 68881 or cfloat was meant by -mfloat.
652 (md_show_usage): Adjust extension display.
653 (m68k_elf_final_processing): Adjust.
655 2006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
657 * config/tc-avr.c (avr_mod_hash_value): New function.
658 (md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
659 BFD_RELOC_MS8_LDI for hlo8() and hhi8()
660 (md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
661 instead of int avr_ldi_expression: use avr_mod_hash_value instead
662 of (int).
663 (tc_gen_reloc): Handle substractions of symbols, if possible do
664 fixups, abort otherwise.
665 * config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
666 tc_fix_adjustable): Define.
668 2006-03-02 James E Wilson <wilson@specifix.com>
670 * config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
671 change the template, then clear md.slot[curr].end_of_insn_group.
673 2006-02-28 Jan Beulich <jbeulich@novell.com>
675 * macro.c (get_any_string): Don't insert quotes for <>-quoted input.
677 2006-02-28 Jan Beulich <jbeulich@novell.com>
679 PR/1070
680 * macro.c (getstring): Don't treat parentheses special anymore.
681 (get_any_string): Don't consider '(' and ')' as quoting anymore.
682 Special-case '(', ')', '[', and ']' when dealing with non-quoting
683 characters.
685 2006-02-28 Mat <mat@csail.mit.edu>
687 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
689 2006-02-27 Jakub Jelinek <jakub@redhat.com>
691 * dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
692 field.
693 (CFI_signal_frame): Define.
694 (cfi_pseudo_table): Add .cfi_signal_frame.
695 (dot_cfi): Handle CFI_signal_frame.
696 (output_cie): Handle cie->signal_frame.
697 (select_cie_for_fde): Don't share CIE if signal_frame flag is
698 different. Copy signal_frame from FDE to newly created CIE.
699 * doc/as.texinfo: Document .cfi_signal_frame.
701 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
703 * doc/Makefile.am: Add html target.
704 * doc/Makefile.in: Regenerate.
705 * po/Make-in: Add html target.
707 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
709 * config/tc-i386.c (output_insn): Support Intel Merom New
710 Instructions.
712 * config/tc-i386.h (CpuMNI): New.
713 (CpuUnknownFlags): Add CpuMNI.
715 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
717 * config/tc-sparc.c (priv_reg_table): Add entry for "gl".
718 (hpriv_reg_table): New table for hyperprivileged registers.
719 (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
720 register encoding.
722 2006-02-24 DJ Delorie <dj@redhat.com>
724 * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
725 (tc_gen_reloc): Don't define.
726 * config/tc-m32c.c (rl_for, relaxable): New convenience macros.
727 (OPTION_LINKRELAX): New.
728 (md_longopts): Add it.
729 (m32c_relax): New.
730 (md_parse_options): Set it.
731 (md_assemble): Emit relaxation relocs as needed.
732 (md_convert_frag): Emit relaxation relocs as needed.
733 (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
734 (m32c_apply_fix): New.
735 (tc_gen_reloc): New.
736 (m32c_force_relocation): Force out jump relocs when relaxing.
737 (m32c_fix_adjustable): Return false if relaxing.
739 2006-02-24 Paul Brook <paul@codesourcery.com>
741 * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
742 arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
743 (struct asm_barrier_opt): Define.
744 (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
745 (parse_psr): Accept V7M psr names.
746 (parse_barrier): New function.
747 (enum operand_parse_code): Add OP_oBARRIER.
748 (parse_operands): Implement OP_oBARRIER.
749 (do_barrier): New function.
750 (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
751 (do_t_cpsi): Add V7M restrictions.
752 (do_t_mrs, do_t_msr): Validate V7M variants.
753 (md_assemble): Check for NULL variants.
754 (v7m_psrs, barrier_opt_names): New tables.
755 (insns): Add V7 instructions. Mark V6 instructions absent from V7M.
756 (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
757 (arm_cpu_option_table): Add Cortex-M3, R4 and A8.
758 (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
759 (struct cpu_arch_ver_table): Define.
760 (cpu_arch_ver): New.
761 (aeabi_set_public_attributes): Use cpu_arch_ver. Set
762 Tag_CPU_arch_profile.
763 * doc/c-arm.texi: Document new cpu and arch options.
765 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
767 * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
769 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
771 * config/tc-ia64.c: Update copyright years.
773 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
775 * config/tc-ia64.c (specify_resource): Add the rule 17 from
776 SDM 2.2.
778 2005-02-22 Paul Brook <paul@codesourcery.com>
780 * config/tc-arm.c (do_pld): Remove incorrect write to
781 inst.instruction.
782 (encode_thumb32_addr_mode): Use correct operand.
784 2006-02-21 Paul Brook <paul@codesourcery.com>
786 * config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
788 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
789 Anil Paranjape <anilp1@kpitcummins.com>
790 Shilin Shakti <shilins@kpitcummins.com>
792 * Makefile.am: Add xc16x related entry.
793 * Makefile.in: Regenerate.
794 * configure.in: Added xc16x related entry.
795 * configure: Regenerate.
796 * config/tc-xc16x.h: New file
797 * config/tc-xc16x.c: New file
798 * doc/c-xc16x.texi: New file for xc16x
799 * doc/all.texi: Entry for xc16x
800 * doc/Makefile.texi: Added c-xc16x.texi
801 * NEWS: Announce the support for the new target.
803 2006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
805 * configure.tgt: set emulation for mips-*-netbsd*
807 2006-02-14 Jakub Jelinek <jakub@redhat.com>
809 * config.in: Rebuilt.
811 2006-02-13 Bob Wilson <bob.wilson@acm.org>
813 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
814 from 1, not 0, in error messages.
815 (md_assemble): Simplify special-case check for ENTRY instructions.
816 (tinsn_has_invalid_symbolic_operands): Do not include opcode and
817 operand in error message.
819 2006-02-13 Joseph S. Myers <joseph@codesourcery.com>
821 * configure.tgt (arm-*-linux-gnueabi*): Change to
822 arm-*-linux-*eabi*.
824 2006-02-10 Nick Clifton <nickc@redhat.com>
826 * config/tc-crx.c (check_range): Ensure that the sign bit of a
827 32-bit value is propagated into the upper bits of a 64-bit long.
829 * config/tc-arc.c (init_opcode_tables): Fix cast.
830 (arc_extoper, md_operand): Likewise.
832 2006-02-09 David Heine <dlheine@tensilica.com>
834 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
835 each relaxation step.
837 2006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
839 * configure.in (CHECK_DECLS): Add vsnprintf.
840 * configure: Regenerate.
841 * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
842 include/declare here, but...
843 * as.h: Move code detecting VARARGS idiom to the top.
844 (errno.h, stdarg.h, varargs.h, va_list): ...here.
845 (vsnprintf): Declare if not already declared.
847 2006-02-08 H.J. Lu <hongjiu.lu@intel.com>
849 * as.c (close_output_file): New.
850 (main): Register close_output_file with xatexit before
851 dump_statistics. Don't call output_file_close.
853 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
855 * config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
856 mcf5329_control_regs): New.
857 (not_current_architecture, selected_arch, selected_cpu): New.
858 (m68k_archs, m68k_extensions): New.
859 (archs): Renamed to ...
860 (m68k_cpus): ... here. Adjust.
861 (n_arches): Remove.
862 (md_pseudo_table): Add arch and cpu directives.
863 (find_cf_chip, m68k_ip): Adjust table scanning.
864 (no_68851, no_68881): Remove.
865 (md_assemble): Lazily initialize.
866 (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
867 (md_init_after_args): Move functionality to m68k_init_arch.
868 (mri_chip): Adjust table scanning.
869 (md_parse_option): Reimplement 'm' processing to add -march & -mcpu
870 options with saner parsing.
871 (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
872 m68k_init_arch): New.
873 (s_m68k_cpu, s_m68k_arch): New.
874 (md_show_usage): Adjust.
875 (m68k_elf_final_processing): Set CF EF flags.
876 * config/tc-m68k.h (m68k_init_after_args): Remove.
877 (tc_init_after_args): Remove.
878 * doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
879 (M68k-Directives): Document .arch and .cpu directives.
881 2006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
883 * config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
884 synonyms for equ and defl.
885 (z80_cons_fix_new): New function.
886 (emit_byte): Disallow relative jumps to absolute locations.
887 (emit_data): Only handle defb, prototype changed, because defb is
888 now handled as pseudo-op rather than an instruction.
889 (instab): Entries for defb,defw,db,dw moved from here...
890 (md_pseudo_table): ... to here, use generic cons() for defw,dw.
891 Add entries for def24,def32,d24,d32.
892 (md_assemble): Improved error handling.
893 (md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
894 * config/tc-z80.h (TC_CONS_FIX_NEW): Define.
895 (z80_cons_fix_new): Declare.
896 * doc/c-z80.texi (defb, db): Mention warning on overflow.
897 (def24,d24,def32,d32): New pseudo-ops.
899 2006-02-02 Paul Brook <paul@codesourcery.com>
901 * config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
903 2005-02-02 Paul Brook <paul@codesourcery.com>
905 * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
906 T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
907 T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
908 T2_OPCODE_RSB): Define.
909 (thumb32_negate_data_op): New function.
910 (md_apply_fix): Use it.
912 2006-01-31 Bob Wilson <bob.wilson@acm.org>
914 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
915 fields.
916 * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
917 * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
918 subtracted symbols.
919 (relaxation_requirements): Add pfinish_frag argument and use it to
920 replace setting tinsn->record_fix fields.
921 (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
922 and vinsn_to_insnbuf. Remove references to record_fix and
923 slot_sub_symbols fields.
924 (xtensa_mark_narrow_branches): Delete unused code.
925 (is_narrow_branch_guaranteed_in_range): Handle expr that is not just
926 a symbol.
927 (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
928 record_fix fields.
929 (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
930 (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
931 of the record_fix field. Simplify error messages for unexpected
932 symbolic operands.
933 (set_expr_symbol_offset_diff): Delete.
935 2006-01-31 Paul Brook <paul@codesourcery.com>
937 * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
939 2006-01-31 Paul Brook <paul@codesourcery.com>
940 Richard Earnshaw <rearnsha@arm.com>
942 * config/tc-arm.c: Use arm_feature_set.
943 (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
944 arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
945 fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
946 New variables.
947 (insns): Use them.
948 (md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
949 md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
950 arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
951 s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
952 feature flags.
953 (arm_legacy_option_table, arm_option_cpu_value_table): New types.
954 (arm_opts): Move old cpu/arch options from here...
955 (arm_legacy_opts): ... to here.
956 (md_parse_option): Search arm_legacy_opts.
957 (arm_cpus, arm_archs, arm_extensions, arm_fpus)
958 (arm_float_abis, arm_eabis): Make const.
960 2006-01-25 Bob Wilson <bob.wilson@acm.org>
962 * config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
964 2006-01-21 Jie Zhang <jie.zhang@analog.com>
966 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
967 in load immediate intruction.
969 2006-01-21 Jie Zhang <jie.zhang@analog.com>
971 * config/bfin-parse.y (value_match): Use correct conversion
972 specifications in template string for __FILE__ and __LINE__.
973 (binary): Ditto.
974 (unary): Ditto.
976 2006-01-18 Alexandre Oliva <aoliva@redhat.com>
978 Introduce TLS descriptors for i386 and x86_64.
979 * config/tc-i386.c (tc_i386_fix_adjustable): Handle
980 BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
981 BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
982 (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
983 BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
984 displacement bits.
985 (build_modrm_byte): Set up zero modrm for TLS desc calls.
986 (lex_got): Handle @tlsdesc and @tlscall.
987 (md_apply_fix, tc_gen_reloc): Handle the new relocations.
989 2006-01-11 Nick Clifton <nickc@redhat.com>
991 Fixes for building on 64-bit hosts:
992 * config/tc-avr.c (mod_index): New union to allow conversion
993 between pointers and integers.
994 (md_begin, avr_ldi_expression): Use it.
995 * config/tc-i370.c (md_assemble): Add cast for argument to print
996 statement.
997 * config/tc-tic54x.c (subsym_substitute): Likewise.
998 * config/tc-mn10200.c (md_assemble): Use a union to convert the
999 opindex field of fr_cgen structure into a pointer so that it can
1000 be stored in a frag.
1001 * config/tc-mn10300.c (md_assemble): Likewise.
1002 * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
1003 types.
1004 * config/tc-v850.c: Replace uses of (int) casts with correct
1005 types.
1007 2006-01-09 H.J. Lu <hongjiu.lu@intel.com>
1009 PR gas/2117
1010 * symbols.c (snapshot_symbol): Don't change a defined symbol.
1012 2006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
1014 PR gas/2101
1015 * config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
1016 a local-label reference.
1018 For older changes see ChangeLog-2005
1019 \f
1020 Local Variables:
1021 mode: change-log
1022 left-margin: 8
1023 fill-column: 74
1024 version-control: never
1025 End: