1 2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
3 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
5 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
7 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
8 (no_op_insn): Initialize array with instructions that have no
10 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
12 2004-11-29 Richard Earnshaw <rearnsha@arm.com>
14 * arm-dis.c: Correct top-level comment.
16 2004-11-27 Richard Earnshaw <rearnsha@arm.com>
18 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
19 architecuture defining the insn.
20 (arm_opcodes, thumb_opcodes): Delete. Move to ...
21 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
23 Also include opcode/arm.h.
24 * Makefile.am (arm-dis.lo): Update dependency list.
25 * Makefile.in: Regenerate.
27 2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
29 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
30 reflect the change to the short immediate syntax.
32 2004-11-19 Alan Modra <amodra@bigpond.net.au>
34 * or32-opc.c (debug): Warning fix.
35 * po/POTFILES.in: Regenerate.
37 * maxq-dis.c: Formatting.
38 (print_insn): Warning fix.
40 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
42 * arm-dis.c (WORD_ADDRESS): Define.
43 (print_insn): Use it. Correct big-endian end-of-section handling.
45 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
46 Vineet Sharma <vineets@noida.hcltech.com>
48 * maxq-dis.c: New file.
49 * disassemble.c (ARCH_maxq): Define.
50 (disassembler): Add 'print_insn_maxq_little' for handling maxq
52 * configure.in: Add case for bfd_maxq_arch.
53 * configure: Regenerate.
54 * Makefile.am: Add support for maxq-dis.c
55 * Makefile.in: Regenerate.
56 * aclocal.m4: Regenerate.
58 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
60 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
62 * crx-dis.c: Likewise.
64 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
66 Generally, handle CRISv32.
67 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
68 (struct cris_disasm_data): New type.
69 (format_reg, format_hex, cris_constraint, print_flags)
70 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
72 (format_sup_reg, print_insn_crisv32_with_register_prefix)
73 (print_insn_crisv32_without_register_prefix)
74 (print_insn_crisv10_v32_with_register_prefix)
75 (print_insn_crisv10_v32_without_register_prefix)
76 (cris_parse_disassembler_options): New functions.
77 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
78 parameter. All callers changed.
79 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
81 (cris_constraint) <case 'Y', 'U'>: New cases.
82 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
84 (print_with_operands) <case 'Y'>: New case.
85 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
86 <case 'N', 'Y', 'Q'>: New cases.
87 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
88 (print_insn_cris_with_register_prefix)
89 (print_insn_cris_without_register_prefix): Call
90 cris_parse_disassembler_options.
91 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
92 for CRISv32 and the size of immediate operands. New v32-only
93 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
94 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
95 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
96 Change brp to be v3..v10.
97 (cris_support_regs): New vector.
98 (cris_opcodes): Update head comment. New format characters '[',
99 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
100 Add new opcodes for v32 and adjust existing opcodes to accommodate
101 differences to earlier variants.
102 (cris_cond15s): New vector.
104 2004-11-04 Jan Beulich <jbeulich@novell.com>
106 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
108 (Mp): Use f_mode rather than none at all.
109 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
110 replaces what previously was x_mode; x_mode now means 128-bit SSE
112 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
113 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
114 pinsrw's second operand is Edqw.
115 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
116 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
117 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
118 mode when an operand size override is present or always suffixing.
119 More instructions will need to be added to this group.
120 (putop): Handle new macro chars 'C' (short/long suffix selector),
121 'I' (Intel mode override for following macro char), and 'J' (for
122 adding the 'l' prefix to far branches in AT&T mode). When an
123 alternative was specified in the template, honor macro character when
124 specified for Intel mode.
125 (OP_E): Handle new *_mode values. Correct pointer specifications for
126 memory operands. Consolidate output of index register.
127 (OP_G): Handle new *_mode values.
128 (OP_I): Handle const_1_mode.
129 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
130 respective opcode prefix bits have been consumed.
131 (OP_EM, OP_EX): Provide some default handling for generating pointer
134 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
136 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
139 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
141 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
142 (getregliststring): Support HI/LO and user registers.
143 * crx-opc.c (crx_instruction): Update data structure according to the
144 rearrangement done in CRX opcode header file.
145 (crx_regtab): Likewise.
146 (crx_optab): Likewise.
147 (crx_instruction): Reorder load/stor instructions, remove unsupported
149 support new Co-Processor instruction 'cpi'.
151 2004-10-27 Nick Clifton <nickc@redhat.com>
153 * opcodes/iq2000-asm.c: Regenerate.
154 * opcodes/iq2000-desc.c: Regenerate.
155 * opcodes/iq2000-desc.h: Regenerate.
156 * opcodes/iq2000-dis.c: Regenerate.
157 * opcodes/iq2000-ibld.c: Regenerate.
158 * opcodes/iq2000-opc.c: Regenerate.
159 * opcodes/iq2000-opc.h: Regenerate.
161 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
163 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
164 us4, us5 (respectively).
165 Remove unsupported 'popa' instruction.
166 Reverse operands order in store co-processor instructions.
168 2004-10-15 Alan Modra <amodra@bigpond.net.au>
170 * Makefile.am: Run "make dep-am"
171 * Makefile.in: Regenerate.
173 2004-10-12 Bob Wilson <bob.wilson@acm.org>
175 * xtensa-dis.c: Use ISO C90 formatting.
177 2004-10-09 Alan Modra <amodra@bigpond.net.au>
179 * ppc-opc.c: Revert 2004-09-09 change.
181 2004-10-07 Bob Wilson <bob.wilson@acm.org>
183 * xtensa-dis.c (state_names): Delete.
184 (fetch_data): Use xtensa_isa_maxlength.
185 (print_xtensa_operand): Replace operand parameter with opcode/operand
186 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
187 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
188 instruction bundles. Use xmalloc instead of malloc.
190 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
192 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
195 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
197 * crx-opc.c (crx_instruction): Support Co-processor insns.
198 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
199 (getregliststring): Change function to use the above enum.
200 (print_arg): Handle CO-Processor insns.
201 (crx_cinvs): Add 'b' option to invalidate the branch-target
204 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
206 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
207 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
208 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
209 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
210 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
212 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
214 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
217 2004-09-30 Paul Brook <paul@codesourcery.com>
219 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
220 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
222 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
224 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
225 (CONFIG_STATUS_DEPENDENCIES): New.
227 (config.status): Likewise.
228 * Makefile.in: Regenerated.
230 2004-09-17 Alan Modra <amodra@bigpond.net.au>
232 * Makefile.am: Run "make dep-am".
233 * Makefile.in: Regenerate.
234 * aclocal.m4: Regenerate.
235 * configure: Regenerate.
236 * po/POTFILES.in: Regenerate.
237 * po/opcodes.pot: Regenerate.
239 2004-09-11 Andreas Schwab <schwab@suse.de>
241 * configure: Rebuild.
243 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
245 * ppc-opc.c (L): Make this field not optional.
247 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
249 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
250 Fix parameter to 'm[t|f]csr' insns.
252 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
254 * configure.in: Autoupdate to autoconf 2.59.
255 * aclocal.m4: Rebuild with aclocal 1.4p6.
256 * configure: Rebuild with autoconf 2.59.
257 * Makefile.in: Rebuild with automake 1.4p6 (picking up
258 bfd changes for autoconf 2.59 on the way).
259 * config.in: Rebuild with autoheader 2.59.
261 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
263 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
265 2004-07-30 Michal Ludvig <mludvig@suse.cz>
267 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
268 (GRPPADLCK2): New define.
269 (twobyte_has_modrm): True for 0xA6.
270 (grps): GRPPADLCK2 for opcode 0xA6.
272 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
274 Introduce SH2a support.
275 * sh-opc.h (arch_sh2a_base): Renumber.
276 (arch_sh2a_nofpu_base): Remove.
277 (arch_sh_base_mask): Adjust.
278 (arch_opann_mask): New.
279 (arch_sh2a, arch_sh2a_nofpu): Adjust.
280 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
281 (sh_table): Adjust whitespace.
282 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
283 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
284 instruction list throughout.
285 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
286 of arch_sh2a in instruction list throughout.
287 (arch_sh2e_up): Accomodate above changes.
288 (arch_sh2_up): Ditto.
289 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
290 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
291 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
292 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
293 * sh-opc.h (arch_sh2a_nofpu): New.
294 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
295 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
297 2004-01-20 DJ Delorie <dj@redhat.com>
298 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
299 2003-12-29 DJ Delorie <dj@redhat.com>
300 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
301 sh_opcode_info, sh_table): Add sh2a support.
302 (arch_op32): New, to tag 32-bit opcodes.
303 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
304 2003-12-02 Michael Snyder <msnyder@redhat.com>
305 * sh-opc.h (arch_sh2a): Add.
306 * sh-dis.c (arch_sh2a): Handle.
307 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
309 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
311 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
313 2004-07-22 Nick Clifton <nickc@redhat.com>
316 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
317 insns - this is done by objdump itself.
318 * h8500-dis.c (print_insn_h8500): Likewise.
320 2004-07-21 Jan Beulich <jbeulich@novell.com>
322 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
323 regardless of address size prefix in effect.
324 (ptr_reg): Size or address registers does not depend on rex64, but
325 on the presence of an address size override.
326 (OP_MMX): Use rex.x only for xmm registers.
327 (OP_EM): Use rex.z only for xmm registers.
329 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
331 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
332 move/branch operations to the bottom so that VR5400 multimedia
333 instructions take precedence in disassembly.
335 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
337 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
338 ISA-specific "break" encoding.
340 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
342 * arm-opc.h: Fix typo in comment.
344 2004-07-11 Andreas Schwab <schwab@suse.de>
346 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
348 2004-07-09 Andreas Schwab <schwab@suse.de>
350 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
352 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
354 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
355 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
356 (crx-dis.lo): New target.
357 (crx-opc.lo): Likewise.
358 * Makefile.in: Regenerate.
359 * configure.in: Handle bfd_crx_arch.
360 * configure: Regenerate.
361 * crx-dis.c: New file.
362 * crx-opc.c: New file.
363 * disassemble.c (ARCH_crx): Define.
364 (disassembler): Handle ARCH_crx.
366 2004-06-29 James E Wilson <wilson@specifixinc.com>
368 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
369 * ia64-asmtab.c: Regnerate.
371 2004-06-28 Alan Modra <amodra@bigpond.net.au>
373 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
374 (extract_fxm): Don't test dialect.
375 (XFXFXM_MASK): Include the power4 bit.
376 (XFXM): Add p4 param.
377 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
379 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
381 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
382 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
384 2004-06-26 Alan Modra <amodra@bigpond.net.au>
386 * ppc-opc.c (BH, XLBH_MASK): Define.
387 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
389 2004-06-24 Alan Modra <amodra@bigpond.net.au>
391 * i386-dis.c (x_mode): Comment.
392 (two_source_ops): File scope.
393 (float_mem): Correct fisttpll and fistpll.
394 (float_mem_mode): New table.
396 (OP_E): Correct intel mode PTR output.
397 (ptr_reg): Use open_char and close_char.
398 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
399 operands. Set two_source_ops.
401 2004-06-15 Alan Modra <amodra@bigpond.net.au>
403 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
404 instead of _raw_size.
406 2004-06-08 Jakub Jelinek <jakub@redhat.com>
408 * ia64-gen.c (in_iclass): Handle more postinc st
410 * ia64-asmtab.c: Rebuilt.
412 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
414 * s390-opc.txt: Correct architecture mask for some opcodes.
415 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
416 in the esa mode as well.
418 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
420 * sh-dis.c (target_arch): Make unsigned.
421 (print_insn_sh): Replace (most of) switch with a call to
422 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
423 * sh-opc.h: Redefine architecture flags values.
424 Add sh3-nommu architecture.
425 Reorganise <arch>_up macros so they make more visual sense.
426 (SH_MERGE_ARCH_SET): Define new macro.
427 (SH_VALID_BASE_ARCH_SET): Likewise.
428 (SH_VALID_MMU_ARCH_SET): Likewise.
429 (SH_VALID_CO_ARCH_SET): Likewise.
430 (SH_VALID_ARCH_SET): Likewise.
431 (SH_MERGE_ARCH_SET_VALID): Likewise.
432 (SH_ARCH_SET_HAS_FPU): Likewise.
433 (SH_ARCH_SET_HAS_DSP): Likewise.
434 (SH_ARCH_UNKNOWN_ARCH): Likewise.
435 (sh_get_arch_from_bfd_mach): Add prototype.
436 (sh_get_arch_up_from_bfd_mach): Likewise.
437 (sh_get_bfd_mach_from_arch_set): Likewise.
438 (sh_merge_bfd_arc): Likewise.
440 2004-05-24 Peter Barada <peter@the-baradas.com>
442 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
443 into new match_insn_m68k function. Loop over canidate
444 matches and select first that completely matches.
445 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
446 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
447 to verify addressing for MAC/EMAC.
448 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
449 reigster halves since 'fpu' and 'spl' look misleading.
450 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
451 * m68k-opc.c: Rearragne mac/emac cases to use longest for
452 first, tighten up match masks.
453 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
454 'size' from special case code in print_insn_m68k to
455 determine decode size of insns.
457 2004-05-19 Alan Modra <amodra@bigpond.net.au>
459 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
460 well as when -mpower4.
462 2004-05-13 Nick Clifton <nickc@redhat.com>
464 * po/fr.po: Updated French translation.
466 2004-05-05 Peter Barada <peter@the-baradas.com>
468 * m68k-dis.c(print_insn_m68k): Add new chips, use core
469 variants in arch_mask. Only set m68881/68851 for 68k chips.
470 * m68k-op.c: Switch from ColdFire chips to core variants.
472 2004-05-05 Alan Modra <amodra@bigpond.net.au>
475 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
477 2004-04-29 Ben Elliston <bje@au.ibm.com>
479 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
480 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
482 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
484 * sh-dis.c (print_insn_sh): Print the value in constant pool
485 as a symbol if it looks like a symbol.
487 2004-04-22 Peter Barada <peter@the-baradas.com>
489 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
490 appropriate ColdFire architectures.
491 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
493 Add EMAC instructions, fix MAC instructions. Remove
494 macmw/macml/msacmw/msacml instructions since mask addressing now
497 2004-04-20 Jakub Jelinek <jakub@redhat.com>
499 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
500 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
501 suffix. Use fmov*x macros, create all 3 fpsize variants in one
502 macro. Adjust all users.
504 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
506 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
509 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
511 * m32r-asm.c: Regenerate.
513 2004-03-29 Stan Shebs <shebs@apple.com>
515 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
518 2004-03-19 Alan Modra <amodra@bigpond.net.au>
520 * aclocal.m4: Regenerate.
521 * config.in: Regenerate.
522 * configure: Regenerate.
523 * po/POTFILES.in: Regenerate.
524 * po/opcodes.pot: Regenerate.
526 2004-03-16 Alan Modra <amodra@bigpond.net.au>
528 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
530 * ppc-opc.c (RA0): Define.
531 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
532 (RAOPT): Rename from RAO. Update all uses.
533 (powerpc_opcodes): Use RA0 as appropriate.
535 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
537 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
539 2004-03-15 Alan Modra <amodra@bigpond.net.au>
541 * sparc-dis.c (print_insn_sparc): Update getword prototype.
543 2004-03-12 Michal Ludvig <mludvig@suse.cz>
545 * i386-dis.c (GRPPLOCK): Delete.
546 (grps): Delete GRPPLOCK entry.
548 2004-03-12 Alan Modra <amodra@bigpond.net.au>
550 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
552 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
554 (dis386): Use NOP_Fixup on "nop".
555 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
556 (twobyte_has_modrm): Set for 0xa7.
557 (padlock_table): Delete. Move to..
558 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
560 (print_insn): Revert PADLOCK_SPECIAL code.
561 (OP_E): Delete sfence, lfence, mfence checks.
563 2004-03-12 Jakub Jelinek <jakub@redhat.com>
565 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
566 (INVLPG_Fixup): New function.
567 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
569 2004-03-12 Michal Ludvig <mludvig@suse.cz>
571 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
572 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
573 (padlock_table): New struct with PadLock instructions.
574 (print_insn): Handle PADLOCK_SPECIAL.
576 2004-03-12 Alan Modra <amodra@bigpond.net.au>
578 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
579 (OP_E): Twiddle clflush to sfence here.
581 2004-03-08 Nick Clifton <nickc@redhat.com>
583 * po/de.po: Updated German translation.
585 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
587 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
588 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
589 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
592 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
594 * frv-asm.c: Regenerate.
595 * frv-desc.c: Regenerate.
596 * frv-desc.h: Regenerate.
597 * frv-dis.c: Regenerate.
598 * frv-ibld.c: Regenerate.
599 * frv-opc.c: Regenerate.
600 * frv-opc.h: Regenerate.
602 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
604 * frv-desc.c, frv-opc.c: Regenerate.
606 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
608 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
610 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
612 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
613 Also correct mistake in the comment.
615 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
617 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
618 ensure that double registers have even numbers.
619 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
620 that reserved instruction 0xfffd does not decode the same
622 * sh-opc.h: Add REG_N_D nibble type and use it whereever
623 REG_N refers to a double register.
624 Add REG_N_B01 nibble type and use it instead of REG_NM
626 Adjust the bit patterns in a few comments.
628 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
630 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
632 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
634 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
636 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
638 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
640 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
642 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
643 mtivor32, mtivor33, mtivor34.
645 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
647 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
649 2004-02-10 Petko Manolov <petkan@nucleusys.com>
651 * arm-opc.h Maverick accumulator register opcode fixes.
653 2004-02-13 Ben Elliston <bje@wasabisystems.com>
655 * m32r-dis.c: Regenerate.
657 2004-01-27 Michael Snyder <msnyder@redhat.com>
659 * sh-opc.h (sh_table): "fsrra", not "fssra".
661 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
663 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
666 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
668 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
670 2004-01-19 Alan Modra <amodra@bigpond.net.au>
672 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
673 1. Don't print scale factor on AT&T mode when index missing.
675 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
677 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
678 when loaded into XR registers.
680 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
682 * frv-desc.h: Regenerate.
683 * frv-desc.c: Regenerate.
684 * frv-opc.c: Regenerate.
686 2004-01-13 Michael Snyder <msnyder@redhat.com>
688 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
690 2004-01-09 Paul Brook <paul@codesourcery.com>
692 * arm-opc.h (arm_opcodes): Move generic mcrr after known
695 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
697 * Makefile.am (libopcodes_la_DEPENDENCIES)
698 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
699 comment about the problem.
700 * Makefile.in: Regenerate.
702 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
704 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
705 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
706 cut&paste errors in shifting/truncating numerical operands.
707 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
708 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
709 (parse_uslo16): Likewise.
710 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
711 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
712 (parse_s12): Likewise.
713 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
714 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
715 (parse_uslo16): Likewise.
716 (parse_uhi16): Parse gothi and gotfuncdeschi.
717 (parse_d12): Parse got12 and gotfuncdesc12.
718 (parse_s12): Likewise.
720 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
722 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
723 instruction which looks similar to an 'rla' instruction.
725 For older changes see ChangeLog-0203
731 version-control: never