opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   3    2005, 2006, 2007 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version
  11    2, or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  21    02110-1301, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, int, const char **);
  42 static long extract_bat (unsigned long, int, int *);
  43 static unsigned long insert_bba (unsigned long, long, int, const char **);
  44 static long extract_bba (unsigned long, int, int *);
  45 static unsigned long insert_bdm (unsigned long, long, int, const char **);
  46 static long extract_bdm (unsigned long, int, int *);
  47 static unsigned long insert_bdp (unsigned long, long, int, const char **);
  48 static long extract_bdp (unsigned long, int, int *);
  49 static unsigned long insert_bo (unsigned long, long, int, const char **);
  50 static long extract_bo (unsigned long, int, int *);
  51 static unsigned long insert_boe (unsigned long, long, int, const char **);
  52 static long extract_boe (unsigned long, int, int *);
  53 static unsigned long insert_fxm (unsigned long, long, int, const char **);
  54 static long extract_fxm (unsigned long, int, int *);
  55 static unsigned long insert_mbe (unsigned long, long, int, const char **);
  56 static long extract_mbe (unsigned long, int, int *);
  57 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
  58 static long extract_mb6 (unsigned long, int, int *);
  59 static long extract_nb (unsigned long, int, int *);
  60 static unsigned long insert_nsi (unsigned long, long, int, const char **);
  61 static long extract_nsi (unsigned long, int, int *);
  62 static unsigned long insert_ral (unsigned long, long, int, const char **);
  63 static unsigned long insert_ram (unsigned long, long, int, const char **);
  64 static unsigned long insert_raq (unsigned long, long, int, const char **);
  65 static unsigned long insert_ras (unsigned long, long, int, const char **);
  66 static unsigned long insert_rbs (unsigned long, long, int, const char **);
  67 static long extract_rbs (unsigned long, int, int *);
  68 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
  69 static long extract_sh6 (unsigned long, int, int *);
  70 static unsigned long insert_spr (unsigned long, long, int, const char **);
  71 static long extract_spr (unsigned long, int, int *);
  72 static unsigned long insert_sprg (unsigned long, long, int, const char **);
  73 static long extract_sprg (unsigned long, int, int *);
  74 static unsigned long insert_tbr (unsigned long, long, int, const char **);
  75 static long extract_tbr (unsigned long, int, int *);
  76 \f
  77 /* The operands table.
  78
  79    The fields are bitm, shift, insert, extract, flags.
  80
  81    We used to put parens around the various additions, like the one
  82    for BA just below.  However, that caused trouble with feeble
  83    compilers with a limit on depth of a parenthesized expression, like
  84    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  85    omit the parens, since the macros are never used in a context where
  86    the addition will be ambiguous.  */
  87
  88 const struct powerpc_operand powerpc_operands[] =
  89 {
  90   /* The zero index is used to indicate the end of the list of
  91      operands.  */
  92 #define UNUSED 0
  93   { 0, 0, NULL, NULL, 0 },
  94
  95   /* The BA field in an XL form instruction.  */
  96 #define BA UNUSED + 1
  97   /* The BI field in a B form or XL form instruction.  */
  98 #define BI BA
  99 #define BI_MASK (0x1f << 16)
 100   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
 101
 102   /* The BA field in an XL form instruction when it must be the same
 103      as the BT field in the same instruction.  */
 104 #define BAT BA + 1
 105   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 106
 107   /* The BB field in an XL form instruction.  */
 108 #define BB BAT + 1
 109 #define BB_MASK (0x1f << 11)
 110   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
 111
 112   /* The BB field in an XL form instruction when it must be the same
 113      as the BA field in the same instruction.  */
 114 #define BBA BB + 1
 115   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 116
 117   /* The BD field in a B form instruction.  The lower two bits are
 118      forced to zero.  */
 119 #define BD BBA + 1
 120   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 121
 122   /* The BD field in a B form instruction when absolute addressing is
 123      used.  */
 124 #define BDA BD + 1
 125   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 126
 127   /* The BD field in a B form instruction when the - modifier is used.
 128      This sets the y bit of the BO field appropriately.  */
 129 #define BDM BDA + 1
 130   { 0xfffc, 0, insert_bdm, extract_bdm,
 131       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 132
 133   /* The BD field in a B form instruction when the - modifier is used
 134      and absolute address is used.  */
 135 #define BDMA BDM + 1
 136   { 0xfffc, 0, insert_bdm, extract_bdm,
 137       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when the + modifier is used.
 140      This sets the y bit of the BO field appropriately.  */
 141 #define BDP BDMA + 1
 142   { 0xfffc, 0, insert_bdp, extract_bdp,
 143       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 144
 145   /* The BD field in a B form instruction when the + modifier is used
 146      and absolute addressing is used.  */
 147 #define BDPA BDP + 1
 148   { 0xfffc, 0, insert_bdp, extract_bdp,
 149       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 150
 151   /* The BF field in an X or XL form instruction.  */
 152 #define BF BDPA + 1
 153   /* The CRFD field in an X form instruction.  */
 154 #define CRFD BF
 155   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
 156
 157   /* An optional BF field.  This is used for comparison instructions,
 158      in which an omitted BF field is taken as zero.  */
 159 #define OBF BF + 1
 160   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 161
 162   /* The BFA field in an X or XL form instruction.  */
 163 #define BFA OBF + 1
 164   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
 165
 166   /* The BO field in a B form instruction.  Certain values are
 167      illegal.  */
 168 #define BO BFA + 1
 169 #define BO_MASK (0x1f << 21)
 170   { 0x1f, 21, insert_bo, extract_bo, 0 },
 171
 172   /* The BO field in a B form instruction when the + or - modifier is
 173      used.  This is like the BO field, but it must be even.  */
 174 #define BOE BO + 1
 175   { 0x1e, 21, insert_boe, extract_boe, 0 },
 176
 177 #define BH BOE + 1
 178   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 179
 180   /* The BT field in an X or XL form instruction.  */
 181 #define BT BH + 1
 182   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
 183
 184   /* The condition register number portion of the BI field in a B form
 185      or XL form instruction.  This is used for the extended
 186      conditional branch mnemonics, which set the lower two bits of the
 187      BI field.  This field is optional.  */
 188 #define CR BT + 1
 189   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 190
 191   /* The CRB field in an X form instruction.  */
 192 #define CRB CR + 1
 193   /* The MB field in an M form instruction.  */
 194 #define MB CRB
 195 #define MB_MASK (0x1f << 6)
 196   { 0x1f, 6, NULL, NULL, 0 },
 197
 198   /* The CRFS field in an X form instruction.  */
 199 #define CRFS CRB + 1
 200   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
 201
 202   /* The CT field in an X form instruction.  */
 203 #define CT CRFS + 1
 204   /* The MO field in an mbar instruction.  */
 205 #define MO CT
 206   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 207
 208   /* The D field in a D form instruction.  This is a displacement off
 209      a register, and implies that the next operand is a register in
 210      parentheses.  */
 211 #define D CT + 1
 212   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 213
 214   /* The DE field in a DE form instruction.  This is like D, but is 12
 215      bits only.  */
 216 #define DE D + 1
 217   { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 218
 219   /* The DES field in a DES form instruction.  This is like DS, but is 14
 220      bits only (12 stored.)  */
 221 #define DES DE + 1
 222   { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 223
 224   /* The DQ field in a DQ form instruction.  This is like D, but the
 225      lower four bits are forced to zero. */
 226 #define DQ DES + 1
 227   { 0xfff0, 0, NULL, NULL,
 228     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 229
 230   /* The DS field in a DS form instruction.  This is like D, but the
 231      lower two bits are forced to zero.  */
 232 #define DS DQ + 1
 233   { 0xfffc, 0, NULL, NULL,
 234     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 235
 236   /* The E field in a wrteei instruction.  */
 237 #define E DS + 1
 238   { 0x1, 15, NULL, NULL, 0 },
 239
 240   /* The FL1 field in a POWER SC form instruction.  */
 241 #define FL1 E + 1
 242   /* The U field in an X form instruction.  */
 243 #define U FL1
 244   { 0xf, 12, NULL, NULL, 0 },
 245
 246   /* The FL2 field in a POWER SC form instruction.  */
 247 #define FL2 FL1 + 1
 248   { 0x7, 2, NULL, NULL, 0 },
 249
 250   /* The FLM field in an XFL form instruction.  */
 251 #define FLM FL2 + 1
 252   { 0xff, 17, NULL, NULL, 0 },
 253
 254   /* The FRA field in an X or A form instruction.  */
 255 #define FRA FLM + 1
 256 #define FRA_MASK (0x1f << 16)
 257   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 258
 259   /* The FRB field in an X or A form instruction.  */
 260 #define FRB FRA + 1
 261 #define FRB_MASK (0x1f << 11)
 262   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 263
 264   /* The FRC field in an A form instruction.  */
 265 #define FRC FRB + 1
 266 #define FRC_MASK (0x1f << 6)
 267   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 268
 269   /* The FRS field in an X form instruction or the FRT field in a D, X
 270      or A form instruction.  */
 271 #define FRS FRC + 1
 272 #define FRT FRS
 273   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 274
 275   /* The FXM field in an XFX instruction.  */
 276 #define FXM FRS + 1
 277   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 278
 279   /* Power4 version for mfcr.  */
 280 #define FXM4 FXM + 1
 281   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 282
 283   /* The L field in a D or X form instruction.  */
 284 #define L FXM4 + 1
 285   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 286
 287   /* The LEV field in a POWER SVC form instruction.  */
 288 #define SVC_LEV L + 1
 289   { 0x7f, 5, NULL, NULL, 0 },
 290
 291   /* The LEV field in an SC form instruction.  */
 292 #define LEV SVC_LEV + 1
 293   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 294
 295   /* The LI field in an I form instruction.  The lower two bits are
 296      forced to zero.  */
 297 #define LI LEV + 1
 298   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 299
 300   /* The LI field in an I form instruction when used as an absolute
 301      address.  */
 302 #define LIA LI + 1
 303   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 304
 305   /* The LS field in an X (sync) form instruction.  */
 306 #define LS LIA + 1
 307   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 308
 309   /* The ME field in an M form instruction.  */
 310 #define ME LS + 1
 311 #define ME_MASK (0x1f << 1)
 312   { 0x1f, 1, NULL, NULL, 0 },
 313
 314   /* The MB and ME fields in an M form instruction expressed a single
 315      operand which is a bitmask indicating which bits to select.  This
 316      is a two operand form using PPC_OPERAND_NEXT.  See the
 317      description in opcode/ppc.h for what this means.  */
 318 #define MBE ME + 1
 319   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 320   { 0xff, 0, insert_mbe, extract_mbe, 0 },
 321
 322   /* The MB or ME field in an MD or MDS form instruction.  The high
 323      bit is wrapped to the low end.  */
 324 #define MB6 MBE + 2
 325 #define ME6 MB6
 326 #define MB6_MASK (0x3f << 5)
 327   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 328
 329   /* The NB field in an X form instruction.  The value 32 is stored as
 330      0.  */
 331 #define NB MB6 + 1
 332   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 333
 334   /* The NSI field in a D form instruction.  This is the same as the
 335      SI field, only negated.  */
 336 #define NSI NB + 1
 337   { 0xffff, 0, insert_nsi, extract_nsi,
 338       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 339
 340   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 341 #define RA NSI + 1
 342 #define RA_MASK (0x1f << 16)
 343   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 344
 345   /* As above, but 0 in the RA field means zero, not r0.  */
 346 #define RA0 RA + 1
 347   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 348
 349   /* The RA field in the DQ form lq instruction, which has special
 350      value restrictions.  */
 351 #define RAQ RA0 + 1
 352   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 353
 354   /* The RA field in a D or X form instruction which is an updating
 355      load, which means that the RA field may not be zero and may not
 356      equal the RT field.  */
 357 #define RAL RAQ + 1
 358   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 359
 360   /* The RA field in an lmw instruction, which has special value
 361      restrictions.  */
 362 #define RAM RAL + 1
 363   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 364
 365   /* The RA field in a D or X form instruction which is an updating
 366      store or an updating floating point load, which means that the RA
 367      field may not be zero.  */
 368 #define RAS RAM + 1
 369   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 370
 371   /* The RA field of the tlbwe instruction, which is optional.  */
 372 #define RAOPT RAS + 1
 373   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 374
 375   /* The RB field in an X, XO, M, or MDS form instruction.  */
 376 #define RB RAOPT + 1
 377 #define RB_MASK (0x1f << 11)
 378   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 379
 380   /* The RB field in an X form instruction when it must be the same as
 381      the RS field in the instruction.  This is used for extended
 382      mnemonics like mr.  */
 383 #define RBS RB + 1
 384   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 385
 386   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 387      instruction or the RT field in a D, DS, X, XFX or XO form
 388      instruction.  */
 389 #define RS RBS + 1
 390 #define RT RS
 391 #define RT_MASK (0x1f << 21)
 392   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 393
 394   /* The RS and RT fields of the DS form stq instruction, which have
 395      special value restrictions.  */
 396 #define RSQ RS + 1
 397 #define RTQ RSQ
 398   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
 399
 400   /* The RS field of the tlbwe instruction, which is optional.  */
 401 #define RSO RSQ + 1
 402 #define RTO RSO
 403   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 404
 405   /* The SH field in an X or M form instruction.  */
 406 #define SH RSO + 1
 407 #define SH_MASK (0x1f << 11)
 408   /* The other UIMM field in a EVX form instruction.  */
 409 #define EVUIMM SH
 410   { 0x1f, 11, NULL, NULL, 0 },
 411
 412   /* The SH field in an MD form instruction.  This is split.  */
 413 #define SH6 SH + 1
 414 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 415   { 0x3f, -1, insert_sh6, extract_sh6, 0 },
 416
 417   /* The SH field of the tlbwe instruction, which is optional.  */
 418 #define SHO SH6 + 1
 419   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 420
 421   /* The SI field in a D form instruction.  */
 422 #define SI SHO + 1
 423   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 424
 425   /* The SI field in a D form instruction when we accept a wide range
 426      of positive values.  */
 427 #define SISIGNOPT SI + 1
 428   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 429
 430   /* The SPR field in an XFX form instruction.  This is flipped--the
 431      lower 5 bits are stored in the upper 5 and vice- versa.  */
 432 #define SPR SISIGNOPT + 1
 433 #define PMR SPR
 434 #define SPR_MASK (0x3ff << 11)
 435   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 436
 437   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 438 #define SPRBAT SPR + 1
 439 #define SPRBAT_MASK (0x3 << 17)
 440   { 0x3, 17, NULL, NULL, 0 },
 441
 442   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 443 #define SPRG SPRBAT + 1
 444   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 445
 446   /* The SR field in an X form instruction.  */
 447 #define SR SPRG + 1
 448   { 0xf, 16, NULL, NULL, 0 },
 449
 450   /* The STRM field in an X AltiVec form instruction.  */
 451 #define STRM SR + 1
 452   { 0x3, 21, NULL, NULL, 0 },
 453
 454   /* The SV field in a POWER SC form instruction.  */
 455 #define SV STRM + 1
 456   { 0x3fff, 2, NULL, NULL, 0 },
 457
 458   /* The TBR field in an XFX form instruction.  This is like the SPR
 459      field, but it is optional.  */
 460 #define TBR SV + 1
 461   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 462
 463   /* The TO field in a D or X form instruction.  */
 464 #define TO TBR + 1
 465 #define TO_MASK (0x1f << 21)
 466   { 0x1f, 21, NULL, NULL, 0 },
 467
 468   /* The UI field in a D form instruction.  */
 469 #define UI TO + 1
 470   { 0xffff, 0, NULL, NULL, 0 },
 471
 472   /* The VA field in a VA, VX or VXR form instruction.  */
 473 #define VA UI + 1
 474   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 475
 476   /* The VB field in a VA, VX or VXR form instruction.  */
 477 #define VB VA + 1
 478   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 479
 480   /* The VC field in a VA form instruction.  */
 481 #define VC VB + 1
 482   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 483
 484   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 485 #define VD VC + 1
 486 #define VS VD
 487   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 488
 489   /* The SIMM field in a VX form instruction.  */
 490 #define SIMM VD + 1
 491   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 492
 493   /* The UIMM field in a VX form instruction, and TE in Z form.  */
 494 #define UIMM SIMM + 1
 495 #define TE UIMM
 496   { 0x1f, 16, NULL, NULL, 0 },
 497
 498   /* The SHB field in a VA form instruction.  */
 499 #define SHB UIMM + 1
 500   { 0xf, 6, NULL, NULL, 0 },
 501
 502   /* The other UIMM field in a half word EVX form instruction.  */
 503 #define EVUIMM_2 SHB + 1
 504   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 505
 506   /* The other UIMM field in a word EVX form instruction.  */
 507 #define EVUIMM_4 EVUIMM_2 + 1
 508   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 509
 510   /* The other UIMM field in a double EVX form instruction.  */
 511 #define EVUIMM_8 EVUIMM_4 + 1
 512   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 513
 514   /* The WS field.  */
 515 #define WS EVUIMM_8 + 1
 516   { 0x7, 11, NULL, NULL, 0 },
 517
 518   /* The L field in an mtmsrd or A form instruction.  */
 519 #define A_L WS + 1
 520   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 521
 522 #define RMC A_L + 1
 523   { 0x3, 9, NULL, NULL, 0 },
 524
 525 #define R RMC + 1
 526   { 0x1, 16, NULL, NULL, 0 },
 527
 528 #define SP R + 1
 529   { 0x3, 19, NULL, NULL, 0 },
 530
 531 #define S SP + 1
 532   { 0x1, 20, NULL, NULL, 0 },
 533
 534   /* SH field starting at bit position 16.  */
 535 #define SH16 S + 1
 536   /* The DCM and DGM fields in a Z form instruction.  */
 537 #define DCM SH16
 538 #define DGM DCM
 539   { 0x3f, 10, NULL, NULL, 0 },
 540
 541   /* The EH field in larx instruction.  */
 542 #define EH SH16 + 1
 543   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 544 };
 545
 546 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 547                                            / sizeof (powerpc_operands[0]));
 548
 549 /* The functions used to insert and extract complicated operands.  */
 550
 551 /* The BA field in an XL form instruction when it must be the same as
 552    the BT field in the same instruction.  This operand is marked FAKE.
 553    The insertion function just copies the BT field into the BA field,
 554    and the extraction function just checks that the fields are the
 555    same.  */
 556
 557 static unsigned long
 558 insert_bat (unsigned long insn,
 559             long value ATTRIBUTE_UNUSED,
 560             int dialect ATTRIBUTE_UNUSED,
 561             const char **errmsg ATTRIBUTE_UNUSED)
 562 {
 563   return insn | (((insn >> 21) & 0x1f) << 16);
 564 }
 565
 566 static long
 567 extract_bat (unsigned long insn,
 568              int dialect ATTRIBUTE_UNUSED,
 569              int *invalid)
 570 {
 571   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 572     *invalid = 1;
 573   return 0;
 574 }
 575
 576 /* The BB field in an XL form instruction when it must be the same as
 577    the BA field in the same instruction.  This operand is marked FAKE.
 578    The insertion function just copies the BA field into the BB field,
 579    and the extraction function just checks that the fields are the
 580    same.  */
 581
 582 static unsigned long
 583 insert_bba (unsigned long insn,
 584             long value ATTRIBUTE_UNUSED,
 585             int dialect ATTRIBUTE_UNUSED,
 586             const char **errmsg ATTRIBUTE_UNUSED)
 587 {
 588   return insn | (((insn >> 16) & 0x1f) << 11);
 589 }
 590
 591 static long
 592 extract_bba (unsigned long insn,
 593              int dialect ATTRIBUTE_UNUSED,
 594              int *invalid)
 595 {
 596   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 597     *invalid = 1;
 598   return 0;
 599 }
 600
 601 /* The BD field in a B form instruction when the - modifier is used.
 602    This modifier means that the branch is not expected to be taken.
 603    For chips built to versions of the architecture prior to version 2
 604    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 605    if the offset is negative.  When extracting, we require that the y
 606    bit be 1 and that the offset be positive, since if the y bit is 0
 607    we just want to print the normal form of the instruction.
 608    Power4 compatible targets use two bits, "a", and "t", instead of
 609    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 610    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 611    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 612    for branch on CTR.  We only handle the taken/not-taken hint here.
 613    Note that we don't relax the conditions tested here when
 614    disassembling with -Many because insns using extract_bdm and
 615    extract_bdp always occur in pairs.  One or the other will always
 616    be valid.  */
 617
 618 static unsigned long
 619 insert_bdm (unsigned long insn,
 620             long value,
 621             int dialect,
 622             const char **errmsg ATTRIBUTE_UNUSED)
 623 {
 624   if ((dialect & PPC_OPCODE_POWER4) == 0)
 625     {
 626       if ((value & 0x8000) != 0)
 627         insn |= 1 << 21;
 628     }
 629   else
 630     {
 631       if ((insn & (0x14 << 21)) == (0x04 << 21))
 632         insn |= 0x02 << 21;
 633       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 634         insn |= 0x08 << 21;
 635     }
 636   return insn | (value & 0xfffc);
 637 }
 638
 639 static long
 640 extract_bdm (unsigned long insn,
 641              int dialect,
 642              int *invalid)
 643 {
 644   if ((dialect & PPC_OPCODE_POWER4) == 0)
 645     {
 646       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 647         *invalid = 1;
 648     }
 649   else
 650     {
 651       if ((insn & (0x17 << 21)) != (0x06 << 21)
 652           && (insn & (0x1d << 21)) != (0x18 << 21))
 653         *invalid = 1;
 654     }
 655
 656   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 657 }
 658
 659 /* The BD field in a B form instruction when the + modifier is used.
 660    This is like BDM, above, except that the branch is expected to be
 661    taken.  */
 662
 663 static unsigned long
 664 insert_bdp (unsigned long insn,
 665             long value,
 666             int dialect,
 667             const char **errmsg ATTRIBUTE_UNUSED)
 668 {
 669   if ((dialect & PPC_OPCODE_POWER4) == 0)
 670     {
 671       if ((value & 0x8000) == 0)
 672         insn |= 1 << 21;
 673     }
 674   else
 675     {
 676       if ((insn & (0x14 << 21)) == (0x04 << 21))
 677         insn |= 0x03 << 21;
 678       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 679         insn |= 0x09 << 21;
 680     }
 681   return insn | (value & 0xfffc);
 682 }
 683
 684 static long
 685 extract_bdp (unsigned long insn,
 686              int dialect,
 687              int *invalid)
 688 {
 689   if ((dialect & PPC_OPCODE_POWER4) == 0)
 690     {
 691       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 692         *invalid = 1;
 693     }
 694   else
 695     {
 696       if ((insn & (0x17 << 21)) != (0x07 << 21)
 697           && (insn & (0x1d << 21)) != (0x19 << 21))
 698         *invalid = 1;
 699     }
 700
 701   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 702 }
 703
 704 /* Check for legal values of a BO field.  */
 705
 706 static int
 707 valid_bo (long value, int dialect, int extract)
 708 {
 709   if ((dialect & PPC_OPCODE_POWER4) == 0)
 710     {
 711       int valid;
 712       /* Certain encodings have bits that are required to be zero.
 713          These are (z must be zero, y may be anything):
 714              001zy
 715              011zy
 716              1z00y
 717              1z01y
 718              1z1zz
 719       */
 720       switch (value & 0x14)
 721         {
 722         default:
 723         case 0:
 724           valid = 1;
 725           break;
 726         case 0x4:
 727           valid = (value & 0x2) == 0;
 728           break;
 729         case 0x10:
 730           valid = (value & 0x8) == 0;
 731           break;
 732         case 0x14:
 733           valid = value == 0x14;
 734           break;
 735         }
 736       /* When disassembling with -Many, accept power4 encodings too.  */
 737       if (valid
 738           || (dialect & PPC_OPCODE_ANY) == 0
 739           || !extract)
 740         return valid;
 741     }
 742
 743   /* Certain encodings have bits that are required to be zero.
 744      These are (z must be zero, a & t may be anything):
 745          0000z
 746          0001z
 747          0100z
 748          0101z
 749          001at
 750          011at
 751          1a00t
 752          1a01t
 753          1z1zz
 754   */
 755   if ((value & 0x14) == 0)
 756     return (value & 0x1) == 0;
 757   else if ((value & 0x14) == 0x14)
 758     return value == 0x14;
 759   else
 760     return 1;
 761 }
 762
 763 /* The BO field in a B form instruction.  Warn about attempts to set
 764    the field to an illegal value.  */
 765
 766 static unsigned long
 767 insert_bo (unsigned long insn,
 768            long value,
 769            int dialect,
 770            const char **errmsg)
 771 {
 772   if (!valid_bo (value, dialect, 0))
 773     *errmsg = _("invalid conditional option");
 774   return insn | ((value & 0x1f) << 21);
 775 }
 776
 777 static long
 778 extract_bo (unsigned long insn,
 779             int dialect,
 780             int *invalid)
 781 {
 782   long value;
 783
 784   value = (insn >> 21) & 0x1f;
 785   if (!valid_bo (value, dialect, 1))
 786     *invalid = 1;
 787   return value;
 788 }
 789
 790 /* The BO field in a B form instruction when the + or - modifier is
 791    used.  This is like the BO field, but it must be even.  When
 792    extracting it, we force it to be even.  */
 793
 794 static unsigned long
 795 insert_boe (unsigned long insn,
 796             long value,
 797             int dialect,
 798             const char **errmsg)
 799 {
 800   if (!valid_bo (value, dialect, 0))
 801     *errmsg = _("invalid conditional option");
 802   else if ((value & 1) != 0)
 803     *errmsg = _("attempt to set y bit when using + or - modifier");
 804
 805   return insn | ((value & 0x1f) << 21);
 806 }
 807
 808 static long
 809 extract_boe (unsigned long insn,
 810              int dialect,
 811              int *invalid)
 812 {
 813   long value;
 814
 815   value = (insn >> 21) & 0x1f;
 816   if (!valid_bo (value, dialect, 1))
 817     *invalid = 1;
 818   return value & 0x1e;
 819 }
 820
 821 /* FXM mask in mfcr and mtcrf instructions.  */
 822
 823 static unsigned long
 824 insert_fxm (unsigned long insn,
 825             long value,
 826             int dialect,
 827             const char **errmsg)
 828 {
 829   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
 830      one bit of the mask field is set.  */
 831   if ((insn & (1 << 20)) != 0)
 832     {
 833       if (value == 0 || (value & -value) != value)
 834         {
 835           *errmsg = _("invalid mask field");
 836           value = 0;
 837         }
 838     }
 839
 840   /* If the optional field on mfcr is missing that means we want to use
 841      the old form of the instruction that moves the whole cr.  In that
 842      case we'll have VALUE zero.  There doesn't seem to be a way to
 843      distinguish this from the case where someone writes mfcr %r3,0.  */
 844   else if (value == 0)
 845     ;
 846
 847   /* If only one bit of the FXM field is set, we can use the new form
 848      of the instruction, which is faster.  Unlike the Power4 branch hint
 849      encoding, this is not backward compatible.  Do not generate the
 850      new form unless -mpower4 has been given, or -many and the two
 851      operand form of mfcr was used.  */
 852   else if ((value & -value) == value
 853            && ((dialect & PPC_OPCODE_POWER4) != 0
 854                || ((dialect & PPC_OPCODE_ANY) != 0
 855                    && (insn & (0x3ff << 1)) == 19 << 1)))
 856     insn |= 1 << 20;
 857
 858   /* Any other value on mfcr is an error.  */
 859   else if ((insn & (0x3ff << 1)) == 19 << 1)
 860     {
 861       *errmsg = _("ignoring invalid mfcr mask");
 862       value = 0;
 863     }
 864
 865   return insn | ((value & 0xff) << 12);
 866 }
 867
 868 static long
 869 extract_fxm (unsigned long insn,
 870              int dialect ATTRIBUTE_UNUSED,
 871              int *invalid)
 872 {
 873   long mask = (insn >> 12) & 0xff;
 874
 875   /* Is this a Power4 insn?  */
 876   if ((insn & (1 << 20)) != 0)
 877     {
 878       /* Exactly one bit of MASK should be set.  */
 879       if (mask == 0 || (mask & -mask) != mask)
 880         *invalid = 1;
 881     }
 882
 883   /* Check that non-power4 form of mfcr has a zero MASK.  */
 884   else if ((insn & (0x3ff << 1)) == 19 << 1)
 885     {
 886       if (mask != 0)
 887         *invalid = 1;
 888     }
 889
 890   return mask;
 891 }
 892
 893 /* The MB and ME fields in an M form instruction expressed as a single
 894    operand which is itself a bitmask.  The extraction function always
 895    marks it as invalid, since we never want to recognize an
 896    instruction which uses a field of this type.  */
 897
 898 static unsigned long
 899 insert_mbe (unsigned long insn,
 900             long value,
 901             int dialect ATTRIBUTE_UNUSED,
 902             const char **errmsg)
 903 {
 904   unsigned long uval, mask;
 905   int mb, me, mx, count, last;
 906
 907   uval = value;
 908
 909   if (uval == 0)
 910     {
 911       *errmsg = _("illegal bitmask");
 912       return insn;
 913     }
 914
 915   mb = 0;
 916   me = 32;
 917   if ((uval & 1) != 0)
 918     last = 1;
 919   else
 920     last = 0;
 921   count = 0;
 922
 923   /* mb: location of last 0->1 transition */
 924   /* me: location of last 1->0 transition */
 925   /* count: # transitions */
 926
 927   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
 928     {
 929       if ((uval & mask) && !last)
 930         {
 931           ++count;
 932           mb = mx;
 933           last = 1;
 934         }
 935       else if (!(uval & mask) && last)
 936         {
 937           ++count;
 938           me = mx;
 939           last = 0;
 940         }
 941     }
 942   if (me == 0)
 943     me = 32;
 944
 945   if (count != 2 && (count != 0 || ! last))
 946     *errmsg = _("illegal bitmask");
 947
 948   return insn | (mb << 6) | ((me - 1) << 1);
 949 }
 950
 951 static long
 952 extract_mbe (unsigned long insn,
 953              int dialect ATTRIBUTE_UNUSED,
 954              int *invalid)
 955 {
 956   long ret;
 957   int mb, me;
 958   int i;
 959
 960   *invalid = 1;
 961
 962   mb = (insn >> 6) & 0x1f;
 963   me = (insn >> 1) & 0x1f;
 964   if (mb < me + 1)
 965     {
 966       ret = 0;
 967       for (i = mb; i <= me; i++)
 968         ret |= 1L << (31 - i);
 969     }
 970   else if (mb == me + 1)
 971     ret = ~0;
 972   else /* (mb > me + 1) */
 973     {
 974       ret = ~0;
 975       for (i = me + 1; i < mb; i++)
 976         ret &= ~(1L << (31 - i));
 977     }
 978   return ret;
 979 }
 980
 981 /* The MB or ME field in an MD or MDS form instruction.  The high bit
 982    is wrapped to the low end.  */
 983
 984 static unsigned long
 985 insert_mb6 (unsigned long insn,
 986             long value,
 987             int dialect ATTRIBUTE_UNUSED,
 988             const char **errmsg ATTRIBUTE_UNUSED)
 989 {
 990   return insn | ((value & 0x1f) << 6) | (value & 0x20);
 991 }
 992
 993 static long
 994 extract_mb6 (unsigned long insn,
 995              int dialect ATTRIBUTE_UNUSED,
 996              int *invalid ATTRIBUTE_UNUSED)
 997 {
 998   return ((insn >> 6) & 0x1f) | (insn & 0x20);
 999 }
1000
1001 /* The NB field in an X form instruction.  The value 32 is stored as
1002    0.  */
1003
1004 static long
1005 extract_nb (unsigned long insn,
1006             int dialect ATTRIBUTE_UNUSED,
1007             int *invalid ATTRIBUTE_UNUSED)
1008 {
1009   long ret;
1010
1011   ret = (insn >> 11) & 0x1f;
1012   if (ret == 0)
1013     ret = 32;
1014   return ret;
1015 }
1016
1017 /* The NSI field in a D form instruction.  This is the same as the SI
1018    field, only negated.  The extraction function always marks it as
1019    invalid, since we never want to recognize an instruction which uses
1020    a field of this type.  */
1021
1022 static unsigned long
1023 insert_nsi (unsigned long insn,
1024             long value,
1025             int dialect ATTRIBUTE_UNUSED,
1026             const char **errmsg ATTRIBUTE_UNUSED)
1027 {
1028   return insn | (-value & 0xffff);
1029 }
1030
1031 static long
1032 extract_nsi (unsigned long insn,
1033              int dialect ATTRIBUTE_UNUSED,
1034              int *invalid)
1035 {
1036   *invalid = 1;
1037   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1038 }
1039
1040 /* The RA field in a D or X form instruction which is an updating
1041    load, which means that the RA field may not be zero and may not
1042    equal the RT field.  */
1043
1044 static unsigned long
1045 insert_ral (unsigned long insn,
1046             long value,
1047             int dialect ATTRIBUTE_UNUSED,
1048             const char **errmsg)
1049 {
1050   if (value == 0
1051       || (unsigned long) value == ((insn >> 21) & 0x1f))
1052     *errmsg = "invalid register operand when updating";
1053   return insn | ((value & 0x1f) << 16);
1054 }
1055
1056 /* The RA field in an lmw instruction, which has special value
1057    restrictions.  */
1058
1059 static unsigned long
1060 insert_ram (unsigned long insn,
1061             long value,
1062             int dialect ATTRIBUTE_UNUSED,
1063             const char **errmsg)
1064 {
1065   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1066     *errmsg = _("index register in load range");
1067   return insn | ((value & 0x1f) << 16);
1068 }
1069
1070 /* The RA field in the DQ form lq instruction, which has special
1071    value restrictions.  */
1072
1073 static unsigned long
1074 insert_raq (unsigned long insn,
1075             long value,
1076             int dialect ATTRIBUTE_UNUSED,
1077             const char **errmsg)
1078 {
1079   long rtvalue = (insn & RT_MASK) >> 21;
1080
1081   if (value == rtvalue)
1082     *errmsg = _("source and target register operands must be different");
1083   return insn | ((value & 0x1f) << 16);
1084 }
1085
1086 /* The RA field in a D or X form instruction which is an updating
1087    store or an updating floating point load, which means that the RA
1088    field may not be zero.  */
1089
1090 static unsigned long
1091 insert_ras (unsigned long insn,
1092             long value,
1093             int dialect ATTRIBUTE_UNUSED,
1094             const char **errmsg)
1095 {
1096   if (value == 0)
1097     *errmsg = _("invalid register operand when updating");
1098   return insn | ((value & 0x1f) << 16);
1099 }
1100
1101 /* The RB field in an X form instruction when it must be the same as
1102    the RS field in the instruction.  This is used for extended
1103    mnemonics like mr.  This operand is marked FAKE.  The insertion
1104    function just copies the BT field into the BA field, and the
1105    extraction function just checks that the fields are the same.  */
1106
1107 static unsigned long
1108 insert_rbs (unsigned long insn,
1109             long value ATTRIBUTE_UNUSED,
1110             int dialect ATTRIBUTE_UNUSED,
1111             const char **errmsg ATTRIBUTE_UNUSED)
1112 {
1113   return insn | (((insn >> 21) & 0x1f) << 11);
1114 }
1115
1116 static long
1117 extract_rbs (unsigned long insn,
1118              int dialect ATTRIBUTE_UNUSED,
1119              int *invalid)
1120 {
1121   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1122     *invalid = 1;
1123   return 0;
1124 }
1125
1126 /* The SH field in an MD form instruction.  This is split.  */
1127
1128 static unsigned long
1129 insert_sh6 (unsigned long insn,
1130             long value,
1131             int dialect ATTRIBUTE_UNUSED,
1132             const char **errmsg ATTRIBUTE_UNUSED)
1133 {
1134   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1135 }
1136
1137 static long
1138 extract_sh6 (unsigned long insn,
1139              int dialect ATTRIBUTE_UNUSED,
1140              int *invalid ATTRIBUTE_UNUSED)
1141 {
1142   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1143 }
1144
1145 /* The SPR field in an XFX form instruction.  This is flipped--the
1146    lower 5 bits are stored in the upper 5 and vice- versa.  */
1147
1148 static unsigned long
1149 insert_spr (unsigned long insn,
1150             long value,
1151             int dialect ATTRIBUTE_UNUSED,
1152             const char **errmsg ATTRIBUTE_UNUSED)
1153 {
1154   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1155 }
1156
1157 static long
1158 extract_spr (unsigned long insn,
1159              int dialect ATTRIBUTE_UNUSED,
1160              int *invalid ATTRIBUTE_UNUSED)
1161 {
1162   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1163 }
1164
1165 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1166
1167 static unsigned long
1168 insert_sprg (unsigned long insn,
1169              long value,
1170              int dialect,
1171              const char **errmsg)
1172 {
1173   /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1174      as a synonym.  If ever a 405 specific dialect is added this
1175      check should use that instead.  */
1176   if (value > 7
1177       || (value > 3
1178           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1179     *errmsg = _("invalid sprg number");
1180
1181   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1182      user mode.  Anything else must use spr 272..279.  */
1183   if (value <= 3 || (insn & 0x100) != 0)
1184     value |= 0x10;
1185
1186   return insn | ((value & 0x17) << 16);
1187 }
1188
1189 static long
1190 extract_sprg (unsigned long insn,
1191               int dialect,
1192               int *invalid)
1193 {
1194   unsigned long val = (insn >> 16) & 0x1f;
1195
1196   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1197      If not BOOKE or 405, then both use only 272..275.  */
1198   if (val <= 3
1199       || (val < 0x10 && (insn & 0x100) != 0)
1200       || (val - 0x10 > 3
1201           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1202     *invalid = 1;
1203   return val & 7;
1204 }
1205
1206 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1207    is optional.  When TBR is omitted, it must be inserted as 268 (the
1208    magic number of the TB register).  These functions treat 0
1209    (indicating an omitted optional operand) as 268.  This means that
1210    ``mftb 4,0'' is not handled correctly.  This does not matter very
1211    much, since the architecture manual does not define mftb as
1212    accepting any values other than 268 or 269.  */
1213
1214 #define TB (268)
1215
1216 static unsigned long
1217 insert_tbr (unsigned long insn,
1218             long value,
1219             int dialect ATTRIBUTE_UNUSED,
1220             const char **errmsg ATTRIBUTE_UNUSED)
1221 {
1222   if (value == 0)
1223     value = TB;
1224   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1225 }
1226
1227 static long
1228 extract_tbr (unsigned long insn,
1229              int dialect ATTRIBUTE_UNUSED,
1230              int *invalid ATTRIBUTE_UNUSED)
1231 {
1232   long ret;
1233
1234   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1235   if (ret == TB)
1236     ret = 0;
1237   return ret;
1238 }
1239 \f
1240 /* Macros used to form opcodes.  */
1241
1242 /* The main opcode.  */
1243 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1244 #define OP_MASK OP (0x3f)
1245
1246 /* The main opcode combined with a trap code in the TO field of a D
1247    form instruction.  Used for extended mnemonics for the trap
1248    instructions.  */
1249 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1250 #define OPTO_MASK (OP_MASK | TO_MASK)
1251
1252 /* The main opcode combined with a comparison size bit in the L field
1253    of a D form or X form instruction.  Used for extended mnemonics for
1254    the comparison instructions.  */
1255 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1256 #define OPL_MASK OPL (0x3f,1)
1257
1258 /* An A form instruction.  */
1259 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1260 #define A_MASK A (0x3f, 0x1f, 1)
1261
1262 /* An A_MASK with the FRB field fixed.  */
1263 #define AFRB_MASK (A_MASK | FRB_MASK)
1264
1265 /* An A_MASK with the FRC field fixed.  */
1266 #define AFRC_MASK (A_MASK | FRC_MASK)
1267
1268 /* An A_MASK with the FRA and FRC fields fixed.  */
1269 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1270
1271 /* An AFRAFRC_MASK, but with L bit clear.  */
1272 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1273
1274 /* A B form instruction.  */
1275 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1276 #define B_MASK B (0x3f, 1, 1)
1277
1278 /* A B form instruction setting the BO field.  */
1279 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1280 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1281
1282 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1283    matching a conditional branch regardless of the setting of the y
1284    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1285 #define Y_MASK   (((unsigned long) 1) << 21)
1286 #define AT1_MASK (((unsigned long) 3) << 21)
1287 #define AT2_MASK (((unsigned long) 9) << 21)
1288 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1289 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1290
1291 /* A B form instruction setting the BO field and the condition bits of
1292    the BI field.  */
1293 #define BBOCB(op, bo, cb, aa, lk) \
1294   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1295 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1296
1297 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1298 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1299 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1300 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1301
1302 /* A BBOYCB_MASK in which the BI field is fixed.  */
1303 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1304 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1305
1306 /* An Context form instruction.  */
1307 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1308 #define CTX_MASK CTX(0x3f, 0x7)
1309
1310 /* An User Context form instruction.  */
1311 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1312 #define UCTX_MASK UCTX(0x3f, 0x1f)
1313
1314 /* The main opcode mask with the RA field clear.  */
1315 #define DRA_MASK (OP_MASK | RA_MASK)
1316
1317 /* A DS form instruction.  */
1318 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1319 #define DS_MASK DSO (0x3f, 3)
1320
1321 /* A DE form instruction.  */
1322 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1323 #define DE_MASK DEO (0x3e, 0xf)
1324
1325 /* An EVSEL form instruction.  */
1326 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1327 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1328
1329 /* An M form instruction.  */
1330 #define M(op, rc) (OP (op) | ((rc) & 1))
1331 #define M_MASK M (0x3f, 1)
1332
1333 /* An M form instruction with the ME field specified.  */
1334 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1335
1336 /* An M_MASK with the MB and ME fields fixed.  */
1337 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1338
1339 /* An M_MASK with the SH and ME fields fixed.  */
1340 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1341
1342 /* An MD form instruction.  */
1343 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1344 #define MD_MASK MD (0x3f, 0x7, 1)
1345
1346 /* An MD_MASK with the MB field fixed.  */
1347 #define MDMB_MASK (MD_MASK | MB6_MASK)
1348
1349 /* An MD_MASK with the SH field fixed.  */
1350 #define MDSH_MASK (MD_MASK | SH6_MASK)
1351
1352 /* An MDS form instruction.  */
1353 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1354 #define MDS_MASK MDS (0x3f, 0xf, 1)
1355
1356 /* An MDS_MASK with the MB field fixed.  */
1357 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1358
1359 /* An SC form instruction.  */
1360 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1361 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1362
1363 /* An VX form instruction.  */
1364 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1365
1366 /* The mask for an VX form instruction.  */
1367 #define VX_MASK VX(0x3f, 0x7ff)
1368
1369 /* An VA form instruction.  */
1370 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1371
1372 /* The mask for an VA form instruction.  */
1373 #define VXA_MASK VXA(0x3f, 0x3f)
1374
1375 /* An VXR form instruction.  */
1376 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1377
1378 /* The mask for a VXR form instruction.  */
1379 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1380
1381 /* An X form instruction.  */
1382 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1383
1384 /* A Z form instruction.  */
1385 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1386
1387 /* An X form instruction with the RC bit specified.  */
1388 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1389
1390 /* A Z form instruction with the RC bit specified.  */
1391 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1392
1393 /* The mask for an X form instruction.  */
1394 #define X_MASK XRC (0x3f, 0x3ff, 1)
1395
1396 /* The mask for a Z form instruction.  */
1397 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1398 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1399
1400 /* An X_MASK with the RA field fixed.  */
1401 #define XRA_MASK (X_MASK | RA_MASK)
1402
1403 /* An X_MASK with the RB field fixed.  */
1404 #define XRB_MASK (X_MASK | RB_MASK)
1405
1406 /* An X_MASK with the RT field fixed.  */
1407 #define XRT_MASK (X_MASK | RT_MASK)
1408
1409 /* An XRT_MASK mask with the L bits clear.  */
1410 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1411
1412 /* An X_MASK with the RA and RB fields fixed.  */
1413 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1414
1415 /* An XRARB_MASK, but with the L bit clear.  */
1416 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1417
1418 /* An X_MASK with the RT and RA fields fixed.  */
1419 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1420
1421 /* An XRTRA_MASK, but with L bit clear.  */
1422 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1423
1424 /* An X form instruction with the L bit specified.  */
1425 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1426
1427 /* The mask for an X form comparison instruction.  */
1428 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1429
1430 /* The mask for an X form comparison instruction with the L field
1431    fixed.  */
1432 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1433
1434 /* An X form trap instruction with the TO field specified.  */
1435 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1436 #define XTO_MASK (X_MASK | TO_MASK)
1437
1438 /* An X form tlb instruction with the SH field specified.  */
1439 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1440 #define XTLB_MASK (X_MASK | SH_MASK)
1441
1442 /* An X form sync instruction.  */
1443 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1444
1445 /* An X form sync instruction with everything filled in except the LS field.  */
1446 #define XSYNC_MASK (0xff9fffff)
1447
1448 /* An X_MASK, but with the EH bit clear.  */
1449 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1450
1451 /* An X form AltiVec dss instruction.  */
1452 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1453 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1454
1455 /* An XFL form instruction.  */
1456 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1457 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1458
1459 /* An X form isel instruction.  */
1460 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1461 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1462
1463 /* An XL form instruction with the LK field set to 0.  */
1464 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1465
1466 /* An XL form instruction which uses the LK field.  */
1467 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1468
1469 /* The mask for an XL form instruction.  */
1470 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1471
1472 /* An XL form instruction which explicitly sets the BO field.  */
1473 #define XLO(op, bo, xop, lk) \
1474   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1475 #define XLO_MASK (XL_MASK | BO_MASK)
1476
1477 /* An XL form instruction which explicitly sets the y bit of the BO
1478    field.  */
1479 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1480 #define XLYLK_MASK (XL_MASK | Y_MASK)
1481
1482 /* An XL form instruction which sets the BO field and the condition
1483    bits of the BI field.  */
1484 #define XLOCB(op, bo, cb, xop, lk) \
1485   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1486 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1487
1488 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1489 #define XLBB_MASK (XL_MASK | BB_MASK)
1490 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1491 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1492
1493 /* A mask for branch instructions using the BH field.  */
1494 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1495
1496 /* An XL_MASK with the BO and BB fields fixed.  */
1497 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1498
1499 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1500 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1501
1502 /* An XO form instruction.  */
1503 #define XO(op, xop, oe, rc) \
1504   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1505 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1506
1507 /* An XO_MASK with the RB field fixed.  */
1508 #define XORB_MASK (XO_MASK | RB_MASK)
1509
1510 /* An XS form instruction.  */
1511 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1512 #define XS_MASK XS (0x3f, 0x1ff, 1)
1513
1514 /* A mask for the FXM version of an XFX form instruction.  */
1515 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1516
1517 /* An XFX form instruction with the FXM field filled in.  */
1518 #define XFXM(op, xop, fxm, p4) \
1519   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1520    | ((unsigned long)(p4) << 20))
1521
1522 /* An XFX form instruction with the SPR field filled in.  */
1523 #define XSPR(op, xop, spr) \
1524   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1525 #define XSPR_MASK (X_MASK | SPR_MASK)
1526
1527 /* An XFX form instruction with the SPR field filled in except for the
1528    SPRBAT field.  */
1529 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1530
1531 /* An XFX form instruction with the SPR field filled in except for the
1532    SPRG field.  */
1533 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1534
1535 /* An X form instruction with everything filled in except the E field.  */
1536 #define XE_MASK (0xffff7fff)
1537
1538 /* An X form user context instruction.  */
1539 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1540 #define XUC_MASK      XUC(0x3f, 0x1f)
1541
1542 /* The BO encodings used in extended conditional branch mnemonics.  */
1543 #define BODNZF  (0x0)
1544 #define BODNZFP (0x1)
1545 #define BODZF   (0x2)
1546 #define BODZFP  (0x3)
1547 #define BODNZT  (0x8)
1548 #define BODNZTP (0x9)
1549 #define BODZT   (0xa)
1550 #define BODZTP  (0xb)
1551
1552 #define BOF     (0x4)
1553 #define BOFP    (0x5)
1554 #define BOFM4   (0x6)
1555 #define BOFP4   (0x7)
1556 #define BOT     (0xc)
1557 #define BOTP    (0xd)
1558 #define BOTM4   (0xe)
1559 #define BOTP4   (0xf)
1560
1561 #define BODNZ   (0x10)
1562 #define BODNZP  (0x11)
1563 #define BODZ    (0x12)
1564 #define BODZP   (0x13)
1565 #define BODNZM4 (0x18)
1566 #define BODNZP4 (0x19)
1567 #define BODZM4  (0x1a)
1568 #define BODZP4  (0x1b)
1569
1570 #define BOU     (0x14)
1571
1572 /* The BI condition bit encodings used in extended conditional branch
1573    mnemonics.  */
1574 #define CBLT    (0)
1575 #define CBGT    (1)
1576 #define CBEQ    (2)
1577 #define CBSO    (3)
1578
1579 /* The TO encodings used in extended trap mnemonics.  */
1580 #define TOLGT   (0x1)
1581 #define TOLLT   (0x2)
1582 #define TOEQ    (0x4)
1583 #define TOLGE   (0x5)
1584 #define TOLNL   (0x5)
1585 #define TOLLE   (0x6)
1586 #define TOLNG   (0x6)
1587 #define TOGT    (0x8)
1588 #define TOGE    (0xc)
1589 #define TONL    (0xc)
1590 #define TOLT    (0x10)
1591 #define TOLE    (0x14)
1592 #define TONG    (0x14)
1593 #define TONE    (0x18)
1594 #define TOU     (0x1f)
1595 \f
1596 /* Smaller names for the flags so each entry in the opcodes table will
1597    fit on a single line.  */
1598 #undef  PPC
1599 #define PPC     PPC_OPCODE_PPC
1600 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1601 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1602 #define POWER4  PPC_OPCODE_POWER4
1603 #define POWER5  PPC_OPCODE_POWER5
1604 #define POWER6  PPC_OPCODE_POWER6
1605 #define CELL    PPC_OPCODE_CELL
1606 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1607 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1608 #define PPC403  PPC_OPCODE_403
1609 #define PPC405  PPC403
1610 #define PPC440  PPC_OPCODE_440
1611 #define PPC750  PPC
1612 #define PPC860  PPC
1613 #define PPCVEC  PPC_OPCODE_ALTIVEC
1614 #define POWER   PPC_OPCODE_POWER
1615 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1616 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1617 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1618 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1619 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1620 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1621 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1622 #define MFDEC1  PPC_OPCODE_POWER
1623 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1624 #define BOOKE   PPC_OPCODE_BOOKE
1625 #define BOOKE64 PPC_OPCODE_BOOKE64
1626 #define CLASSIC PPC_OPCODE_CLASSIC
1627 #define PPCE300 PPC_OPCODE_E300
1628 #define PPCSPE  PPC_OPCODE_SPE
1629 #define PPCISEL PPC_OPCODE_ISEL
1630 #define PPCEFS  PPC_OPCODE_EFS
1631 #define PPCBRLK PPC_OPCODE_BRLOCK
1632 #define PPCPMR  PPC_OPCODE_PMR
1633 #define PPCCHLK PPC_OPCODE_CACHELCK
1634 #define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1635 #define PPCRFMCI        PPC_OPCODE_RFMCI
1636 \f
1637 /* The opcode table.
1638
1639    The format of the opcode table is:
1640
1641    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1642
1643    NAME is the name of the instruction.
1644    OPCODE is the instruction opcode.
1645    MASK is the opcode mask; this is used to tell the disassembler
1646      which bits in the actual opcode must match OPCODE.
1647    FLAGS are flags indicated what processors support the instruction.
1648    OPERANDS is the list of operands.
1649
1650    The disassembler reads the table in order and prints the first
1651    instruction which matches, so this table is sorted to put more
1652    specific instructions before more general instructions.  It is also
1653    sorted by major opcode.  */
1654
1655 const struct powerpc_opcode powerpc_opcodes[] = {
1656 { "attn",    X(0,256), X_MASK,          POWER4,         { 0 } },
1657 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1658 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1659 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1660 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1661 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1662 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1663 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1664 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1665 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1666 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1667 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1668 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1669 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1670 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1671 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1672
1673 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1674 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1675 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1676 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1677 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1678 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1679 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1680 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1681 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1682 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1683 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1684 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1685 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1686 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1687 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1688 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1689 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1690 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1691 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1692 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1693 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1694 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1695 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1696 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1697 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1698 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1699 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1700 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1701 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1702 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1703
1704 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1705 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1706 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1707 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1708 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1709 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1710 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1711 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1712 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1713 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1714 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1715 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1716 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1717 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1718 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1719 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1720 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1721 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1722 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1723 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1724 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1725 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1726 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1727 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1728 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1729 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1730 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1731 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1732 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1733 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1734 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1735 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1736 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1737 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1738 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1739 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1740 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1741 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1742 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1743 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1744 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1745 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1746 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1747 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1748 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1749 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1750 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1751 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1752 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1753 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1754 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1755 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1756 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1757 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1758 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1759 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1760 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1761 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1762 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1763 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1764 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1765 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1766 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1767 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1768 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1769 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1770 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1771 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1772 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1773 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1774 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1775 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1776 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1777 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1778 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1779 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1780 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1781 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1782 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1783 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1784 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1785 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1786 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1787 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1788 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1789 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
1790
1791   /* Double-precision opcodes.  */
1792   /* Some of these conflict with AltiVec, so move them before, since
1793      PPCVEC includes the PPC_OPCODE_PPC set.  */
1794 { "efscfd",   VX(4, 719), VX_MASK,      PPCEFS,         { RS, RB } },
1795 { "efdabs",   VX(4, 740), VX_MASK,      PPCEFS,         { RS, RA } },
1796 { "efdnabs",  VX(4, 741), VX_MASK,      PPCEFS,         { RS, RA } },
1797 { "efdneg",   VX(4, 742), VX_MASK,      PPCEFS,         { RS, RA } },
1798 { "efdadd",   VX(4, 736), VX_MASK,      PPCEFS,         { RS, RA, RB } },
1799 { "efdsub",   VX(4, 737), VX_MASK,      PPCEFS,         { RS, RA, RB } },
1800 { "efdmul",   VX(4, 744), VX_MASK,      PPCEFS,         { RS, RA, RB } },
1801 { "efddiv",   VX(4, 745), VX_MASK,      PPCEFS,         { RS, RA, RB } },
1802 { "efdcmpgt", VX(4, 748), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1803 { "efdcmplt", VX(4, 749), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1804 { "efdcmpeq", VX(4, 750), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1805 { "efdtstgt", VX(4, 764), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1806 { "efdtstlt", VX(4, 765), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1807 { "efdtsteq", VX(4, 766), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1808 { "efdcfsi",  VX(4, 753), VX_MASK,      PPCEFS,         { RS, RB } },
1809 { "efdcfsid", VX(4, 739), VX_MASK,      PPCEFS,         { RS, RB } },
1810 { "efdcfui",  VX(4, 752), VX_MASK,      PPCEFS,         { RS, RB } },
1811 { "efdcfuid", VX(4, 738), VX_MASK,      PPCEFS,         { RS, RB } },
1812 { "efdcfsf",  VX(4, 755), VX_MASK,      PPCEFS,         { RS, RB } },
1813 { "efdcfuf",  VX(4, 754), VX_MASK,      PPCEFS,         { RS, RB } },
1814 { "efdctsi",  VX(4, 757), VX_MASK,      PPCEFS,         { RS, RB } },
1815 { "efdctsidz",VX(4, 747), VX_MASK,      PPCEFS,         { RS, RB } },
1816 { "efdctsiz", VX(4, 762), VX_MASK,      PPCEFS,         { RS, RB } },
1817 { "efdctui",  VX(4, 756), VX_MASK,      PPCEFS,         { RS, RB } },
1818 { "efdctuidz",VX(4, 746), VX_MASK,      PPCEFS,         { RS, RB } },
1819 { "efdctuiz", VX(4, 760), VX_MASK,      PPCEFS,         { RS, RB } },
1820 { "efdctsf",  VX(4, 759), VX_MASK,      PPCEFS,         { RS, RB } },
1821 { "efdctuf",  VX(4, 758), VX_MASK,      PPCEFS,         { RS, RB } },
1822 { "efdcfs",   VX(4, 751), VX_MASK,      PPCEFS,         { RS, RB } },
1823   /* End of double-precision opcodes.  */
1824
1825 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1826 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1827 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1828 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1829 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1830 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1831 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1832 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1833 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1834 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1835 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1836 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1837 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1838 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1839 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1840 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1841 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1842 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1843 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1844 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1845 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1846 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1847 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1848 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1849 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1850 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1851 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1852 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1853 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1854 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1855 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1856 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1857 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1858 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1859 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1860 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1861 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1862 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1863 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1864 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1865 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1866 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1867 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1868 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1869 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1870 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1871 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1872 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1873 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1874 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1875 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1876 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1877 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1878 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1879 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1880 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1881 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1882 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1883 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1884 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1885 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1886 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1887 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1888 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1889 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1890 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1891 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1892 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1893 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1894 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1895 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1896 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1897 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1898 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1899 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1900 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1901 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1902 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1903 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1904 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1905 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1906 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1907 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1908 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1909 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1910 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1911 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1912 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1913 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1914 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1915 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1916 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1917 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1918 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1919 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1920 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1921 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1922 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1923 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1924 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1925 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1926 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1927 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
1928 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
1929 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
1930 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
1931 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
1932 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1933 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1934 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1935 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
1936 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1937 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1938 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1939 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
1940 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1941 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1942 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1943 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1944 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1945 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
1946 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
1947 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
1948 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1949 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1950 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1951 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1952 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1953 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1954 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1955 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1956 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1957 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1958 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1959 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1960 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1961 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1962 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1963 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1964 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1965 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1966 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1967 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1968 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1969 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1970 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1971 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1972 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1973 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
1974 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
1975 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
1976 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
1977 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
1978 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
1979 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1980
1981 { "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RS, RA, RB } },
1982 { "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
1983 { "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RS, RA, RB } },
1984 { "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RS, RB, RA } },
1985 { "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RS, UIMM, RB } },
1986 { "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
1987 { "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RS, RA } },
1988 { "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RS, RA } },
1989 { "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RS, RA } },
1990 { "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RS, RA } },
1991 { "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RS, RA } },
1992 { "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RS, RA } },
1993 { "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RS, RA } },
1994
1995 { "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RS, RA, RB } },
1996
1997 { "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RS, RA, RB } },
1998 { "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RS, RA, RB } },
1999 { "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2000 { "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2001 { "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2002 { "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2003 { "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2004 { "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2005 { "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2006 { "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2007
2008 { "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2009 { "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2010 { "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2011 { "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2012 { "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2013 { "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2014 { "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2015 { "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2016 { "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RS, SIMM } },
2017 { "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RS, SIMM } },
2018 { "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2019 { "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2020 { "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2021 { "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2022
2023 { "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2024 { "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2025 { "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2026 { "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2027 { "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2028 { "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RS, RA, RB, CRFS } },
2029
2030 { "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2031 { "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2032 { "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2033 { "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2034 { "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2035 { "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2036 { "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2037 { "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2038 { "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2039 { "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2040 { "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2041 { "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2042 { "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2043 { "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2044 { "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2045 { "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2046 { "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
2047 { "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2048 { "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2049 { "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2050 { "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2051 { "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2052
2053 { "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2054 { "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2055 { "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2056 { "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2057 { "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2058 { "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2059 { "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2060 { "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2061 { "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2062 { "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2063 { "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2064 { "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2065 { "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2066 { "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2067
2068 { "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RS, RA } },
2069 { "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RS, RA } },
2070 { "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RS, RA } },
2071 { "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2072 { "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2073 { "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2074 { "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2075 { "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2076 { "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2077 { "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2078 { "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2079 { "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2080 { "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2081 { "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RS, RB } },
2082 { "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RS, RB } },
2083 { "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RS, RB } },
2084 { "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RS, RB } },
2085 { "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RS, RB } },
2086 { "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RS, RB } },
2087 { "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RS, RB } },
2088 { "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RS, RB } },
2089 { "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RS, RB } },
2090 { "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RS, RB } },
2091
2092 { "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RS, RA } },
2093 { "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RS, RA } },
2094 { "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RS, RA } },
2095 { "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2096 { "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2097 { "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2098 { "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2099 { "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2100 { "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2101 { "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2102 { "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2103 { "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2104 { "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2105 { "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RS, RB } },
2106 { "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RS, RB } },
2107 { "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RS, RB } },
2108 { "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RS, RB } },
2109 { "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RS, RB } },
2110 { "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RS, RB } },
2111 { "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RS, RB } },
2112 { "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RS, RB } },
2113 { "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RS, RB } },
2114 { "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RS, RB } },
2115
2116 { "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2117 { "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2118 { "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2119 { "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2120 { "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2121 { "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2122 { "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2123 { "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2124 { "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2125 { "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2126 { "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2127 { "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2128 { "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2129 { "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2130 { "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2131 { "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2132
2133 { "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2134 { "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2135 { "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2136 { "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2137 { "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2138 { "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2139 { "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2140 { "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2141 { "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2142 { "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2143 { "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2144 { "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2145
2146 { "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2147 { "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2148 { "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2149 { "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2150 { "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2151 { "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2152 { "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2153 { "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2154 { "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2155 { "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2156 { "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2157 { "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2158
2159 { "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2160 { "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2161 { "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2162 { "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2163 { "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2164 { "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2165
2166 { "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2167 { "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2168 { "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2169 { "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2170 { "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2171 { "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2172
2173 { "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2174 { "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2175 { "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2176 { "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2177 { "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2178 { "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2179 { "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2180 { "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2181
2182 { "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2183 { "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2184
2185 { "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2186 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2187 { "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2188 { "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2189
2190 { "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2191 { "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2192 { "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2193 { "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2194
2195 { "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2196 { "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2197 { "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2198 { "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2199 { "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2200 { "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2201 { "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2202 { "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2203
2204 { "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2205 { "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2206 { "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2207 { "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2208
2209 { "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2210 { "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2211 { "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2212 { "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2213
2214 { "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RS, RA } },
2215 { "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RS, RA } },
2216 { "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RS, RA } },
2217 { "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RS, RA } },
2218
2219 { "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RS, RA } },
2220 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RS, RA } },
2221 { "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RS, RA } },
2222 { "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RS, RA } },
2223
2224 { "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RS, RA } },
2225
2226 { "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2227 { "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2228
2229 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2230 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2231
2232 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2233 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2234
2235 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
2236
2237 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2238 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2239 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2240 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2241
2242 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
2243 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
2244 { "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
2245 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
2246
2247 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
2248 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
2249 { "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
2250 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
2251
2252 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2253 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2254 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2255
2256 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2257 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2258 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2259
2260 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
2261 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
2262 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, SI } },
2263 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
2264 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2265 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
2266
2267 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
2268 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
2269 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA0,SISIGNOPT } },
2270 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA0,SISIGNOPT } },
2271 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2272
2273 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDM } },
2274 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDP } },
2275 { "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BD } },
2276 { "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,      { BD } },
2277 { "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDM } },
2278 { "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDP } },
2279 { "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BD } },
2280 { "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,      { BD } },
2281 { "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2282 { "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2283 { "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDA } },
2284 { "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,      { BDA } },
2285 { "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2286 { "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2287 { "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDA } },
2288 { "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,      { BDA } },
2289 { "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDM } },
2290 { "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDP } },
2291 { "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,         { BD } },
2292 { "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDM } },
2293 { "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDP } },
2294 { "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,         { BD } },
2295 { "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2296 { "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2297 { "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,         { BDA } },
2298 { "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2299 { "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2300 { "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,         { BDA } },
2301 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2302 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2303 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2304 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2305 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2306 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2307 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2308 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2309 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2310 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2311 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2312 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2313 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2314 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2315 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2316 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2317 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2318 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2319 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2320 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2321 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2322 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2323 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2324 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2325 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2326 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2327 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2328 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2329 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2330 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2331 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2332 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2333 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2334 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2335 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2336 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2337 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2338 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2339 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2340 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2341 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2342 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2343 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2344 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2345 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2346 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2347 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2348 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2349 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2350 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2351 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2352 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2353 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2354 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2355 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2356 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2357 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2358 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2359 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2360 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2361 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2362 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2363 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2364 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2365 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2366 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2367 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2368 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2369 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2370 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2371 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2372 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2373 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2374 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2375 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2376 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2377 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2378 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2379 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2380 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2381 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2382 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2383 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2384 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2385 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2386 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2387 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2388 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2389 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2390 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2391 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2392 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2393 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2394 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2395 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2396 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2397 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2398 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2399 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2400 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2401 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2402 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2403 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2404 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2405 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2406 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2407 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2408 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2409 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2410 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2411 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2412 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2413 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2414 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2415 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2416 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2417 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2418 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2419 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2420 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2421 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2422 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2423 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2424 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2425 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2426 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2427 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2428 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2429 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2430 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2431 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2432 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2433 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2434 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2435 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2436 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2437 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2438 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2439 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2440 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2441 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2442 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2443 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2444 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2445 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2446 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2447 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2448 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2449 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2450 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2451 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2452 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2453 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2454 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2455 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2456 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2457 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2458 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2459 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2460 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2461 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2462 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2463 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2464 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2465 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2466 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2467 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2468 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2469 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2470 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2471 { "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2472 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2473 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2474 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2475 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2476 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2477 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2478 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2479 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2480 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2481 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2482 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2483 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2484 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2485 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2486 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2487 { "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2488 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2489 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2490 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2491 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2492 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2493 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2494 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2495 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2496 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2497 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2498 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2499 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2500 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2501 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2502 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2503 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2504 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2505 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2506 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2507 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2508 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2509 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2510 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2511 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2512 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2513 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2514 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2515 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2516 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2517 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2518 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2519 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2520 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2521 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2522 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2523 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2524 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2525 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2526 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2527 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2528 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2529 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2530 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2531 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2532 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2533 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2534 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2535 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2536 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2537
2538 { "sc",      SC(17,1,0), SC_MASK,       PPC,            { LEV } },
2539 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { SVC_LEV, FL1, FL2 } },
2540 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { SVC_LEV, FL1, FL2 } },
2541 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2542 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2543
2544 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2545 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2546 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2547 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2548
2549 { "mcrf",    XL(19,0),  XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },
2550
2551 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2552 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2553 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2554 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2555 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2556 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2557 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2558 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2559 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2560 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2561 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2562 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2563 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2564 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2565 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2566 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2567 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2568 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2569 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2570 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2571 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2572 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2573 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2574 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2575 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2576 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2577 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2578 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2579 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2580 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2581 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2582 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2583 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2584 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2585 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2586 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2587 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2588 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2589 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2590 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2591 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2592 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2593 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2594 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2595 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2596 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2597 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2598 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2599 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2600 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2601 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2602 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2603 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2604 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2605 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2606 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2607 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2608 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2609 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2610 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2611 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2612 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2613 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2614 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2615 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2616 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2617 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2618 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2619 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2620 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2621 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2622 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2623 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2624 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2625 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2626 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2627 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2628 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2629 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2630 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2631 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2632 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2633 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2634 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2635 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2636 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2637 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2638 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2639 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2640 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2641 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2642 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2643 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2644 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2645 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2646 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2647 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2648 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2649 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2650 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2651 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2652 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2653 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2654 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2655 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2656 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2657 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2658 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2659 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2660 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2661 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2662 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2663 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2664 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2665 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2666 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2667 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2668 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2669 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2670 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2671 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2672 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2673 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2674 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2675 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2676 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2677 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2678 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2679 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2680 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2681 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2682 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2683 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2684 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2685 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2686 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2687 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2688 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2689 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2690 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2691 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2692 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2693 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2694 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2695 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2696 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2697 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2698 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2699 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2700 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2701 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2702 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2703 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2704 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2705 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2706 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2707 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2708 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2709 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2710 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2711 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2712 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2713 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2714 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2715 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2716 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2717 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2718 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2719 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2720 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2721 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2722 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2723 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2724 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2725 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2726 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2727 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2728 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2729 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2730 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2731 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2732 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2733 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2734 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2735 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2736 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2737 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2738 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2739 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2740 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2741 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2742 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2743 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2744 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2745 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2746 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2747 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2748 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2749 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2750 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2751 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2752 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2753 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2754 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2755 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2756 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2757 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2758 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2759 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2760 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2761 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2762 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2763 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2764 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2765 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2766 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2767 { "bclr",    XLLK(19,16,0), XLBH_MASK,  PPCCOM,         { BO, BI, BH } },
2768 { "bclrl",   XLLK(19,16,1), XLBH_MASK,  PPCCOM,         { BO, BI, BH } },
2769 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2770 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2771 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2772 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2773
2774 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2775
2776 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2777 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2778 { "rfmci",    X(19,38), 0xffffffff,     PPCRFMCI,       { 0 } },
2779
2780 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2781 { "rfci",    XL(19,51), 0xffffffff,     PPC403 | BOOKE, { 0 } },
2782
2783 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2784
2785 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2786
2787 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2788 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2789
2790 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2791 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2792
2793 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2794
2795 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2796
2797 { "hrfid",   XL(19,274), 0xffffffff,    POWER5 | CELL,  { 0 } },
2798
2799 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2800 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2801
2802 { "doze",    XL(19,402), 0xffffffff,    POWER6,         { 0 } },
2803
2804 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2805
2806 { "nap",     XL(19,434), 0xffffffff,    POWER6,         { 0 } },
2807
2808 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2809 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2810
2811 { "sleep",   XL(19,466), 0xffffffff,    POWER6,         { 0 } },
2812 { "rvwinkle", XL(19,498), 0xffffffff,   POWER6,         { 0 } },
2813
2814 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2815 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2816 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2817 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2818 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2819 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2820 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2821 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2822 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2823 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2824 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2825 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2826 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2827 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2828 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2829 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2830 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2831 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2832 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2833 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2834 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2835 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2836 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2837 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2838 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2839 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2840 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2841 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2842 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2843 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2844 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2845 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2846 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2847 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2848 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2849 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2850 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2851 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2852 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2853 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2854 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2855 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2856 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2857 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2858 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2859 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2860 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2861 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2862 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2863 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2864 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2865 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2866 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2867 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2868 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2869 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2870 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2871 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2872 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2873 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2874 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2875 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2876 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2877 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2878 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2879 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2880 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2881 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2882 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2883 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2884 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2885 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2886 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2887 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2888 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2889 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2890 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2891 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2892 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2893 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2894 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2895 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2896 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2897 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2898 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2899 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2900 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2901 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2902 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2903 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2904 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2905 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2906 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2907 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2908 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2909 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2910 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2911 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2912 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2913 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2914 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2915 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2916 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2917 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2918 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2919 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2920 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2921 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2922 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2923 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2924 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2925 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2926 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2927 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2928 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2929 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2930 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2931 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2932 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2933 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2934 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2935 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2936 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2937 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
2938 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2939 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2940 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2941 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2942 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
2943 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2944 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2945 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2946 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2947 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
2948 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2949 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2950 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2951 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2952 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
2953 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2954 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2955 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2956 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2957 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2958 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2959 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2960 { "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
2961 { "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
2962 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2963 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2964 { "bcctre",  XLLK(19,529,0),     XLBB_MASK,   BOOKE64,  { BO, BI } },
2965 { "bcctrel", XLLK(19,529,1),     XLBB_MASK,   BOOKE64,  { BO, BI } },
2966
2967 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2968 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2969
2970 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2971 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2972
2973 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
2974 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2975 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2976 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2977 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
2978 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2979 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2980 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2981
2982 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2983 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2984
2985 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
2986 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
2987 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
2988 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
2989
2990 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2991 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2992 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2993 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2994 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2995 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2996
2997 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
2998 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2999 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3000
3001 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3002 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3003
3004 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3005 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3006
3007 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3008 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3009
3010 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3011 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3012
3013 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3014 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3015
3016 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3017 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3018 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3019 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3020 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3021 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3022
3023 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3024 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3025
3026 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3027 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3028
3029 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3030 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3031
3032 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3033 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3034 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3035 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3036
3037 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3038 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3039
3040 { "cmpw",    XOPL(31,0,0), XCMPL_MASK, PPCCOM,          { OBF, RA, RB } },
3041 { "cmpd",    XOPL(31,0,1), XCMPL_MASK, PPC64,           { OBF, RA, RB } },
3042 { "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
3043 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
3044
3045 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
3046 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
3047 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
3048 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
3049 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
3050 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
3051 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
3052 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
3053 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
3054 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
3055 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
3056 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
3057 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
3058 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
3059 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
3060 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
3061 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
3062 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
3063 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
3064 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
3065 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
3066 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
3067 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
3068 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
3069 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
3070 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
3071 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
3072 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
3073 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
3074 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
3075 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
3076
3077 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3078 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3079 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
3080 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3081 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3082 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
3083 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3084 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3085 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
3086 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3087 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3088 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
3089
3090 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
3091 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
3092
3093 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3094 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3095 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3096 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3097 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3098 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3099 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3100 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3101
3102 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3103 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3104
3105 { "isellt",  X(31,15),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3106 { "iselgt",  X(31,47),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3107 { "iseleq",  X(31,79),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3108 { "isel",    XISEL(31,15),  XISEL_MASK, PPCISEL,        { RT, RA, RB, CRB } },
3109
3110 { "mfocrf",  XFXM(31,19,0,1), XFXFXM_MASK, COM,         { RT, FXM } },
3111 { "mfcr",    X(31,19),  XRARB_MASK,     NOPOWER4 | COM, { RT } },
3112 { "mfcr",    X(31,19),  XFXFXM_MASK,    POWER4,         { RT, FXM4 } },
3113
3114 { "lwarx",   X(31,20),  XEH_MASK,       PPC,            { RT, RA0, RB, EH } },
3115
3116 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA0, RB } },
3117
3118 { "icbt",    X(31,22),  X_MASK,         BOOKE|PPCE300,  { CT, RA, RB } },
3119 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
3120
3121 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA0, RB } },
3122 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3123
3124 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
3125 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
3126 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
3127 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
3128
3129 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
3130 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
3131 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
3132 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
3133
3134 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
3135 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
3136
3137 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
3138 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
3139
3140 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
3141 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
3142
3143 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
3144
3145 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3146
3147 { "cmplw",   XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3148 { "cmpld",   XOPL(31,32,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
3149 { "cmpl",    X(31,32),  XCMP_MASK,       PPC,           { BF, L, RA, RB } },
3150 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
3151
3152 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3153 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
3154 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3155 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
3156 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
3157 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
3158 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
3159 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
3160
3161 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
3162
3163 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
3164
3165 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
3166 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3167
3168 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
3169
3170 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
3171
3172 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
3173 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
3174
3175 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
3176 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
3177
3178 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
3179 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
3180 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
3181 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
3182 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
3183 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
3184 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
3185 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
3186 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
3187 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
3188 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
3189 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
3190 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
3191 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
3192 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
3193
3194 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
3195 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
3196
3197 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3198 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3199
3200 { "dlmzb",   XRC(31,78,0),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3201 { "dlmzb.",  XRC(31,78,1),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3202
3203 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
3204
3205 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
3206
3207 { "ldarx",   X(31,84),  XEH_MASK,       PPC64,          { RT, RA0, RB, EH } },
3208
3209 { "dcbfl",   XOPL(31,86,1), XRT_MASK,   POWER5,         { RA, RB } },
3210 { "dcbf",    X(31,86),  XLRT_MASK,      PPC,            { RA, RB, L } },
3211
3212 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA0, RB } },
3213
3214 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
3215
3216 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3217
3218 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
3219 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
3220 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
3221 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
3222
3223 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3224 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3225 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3226 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3227
3228 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
3229
3230 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
3231
3232 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
3233
3234 { "popcntb", X(31,122), XRB_MASK,       POWER5,         { RA, RS } },
3235
3236 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
3237 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
3238 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
3239 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
3240
3241 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3242
3243 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3244
3245 { "wrtee",   X(31,131), XRARB_MASK,     PPC403 | BOOKE, { RS } },
3246
3247 { "dcbtstls",X(31,134), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3248
3249 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3250 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3251 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3252 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3253 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3254 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3255 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3256 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3257
3258 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3259 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3260 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3261 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3262 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3263 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3264 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3265 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3266
3267 { "dcbtstlse",X(31,142),X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3268
3269 { "mtocrf",  XFXM(31,144,0,1), XFXFXM_MASK, COM,        { FXM, RS } },
3270 { "mtcr",    XFXM(31,144,0xff,0), XRARB_MASK, COM,      { RS }},
3271 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
3272
3273 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
3274
3275 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA0, RB } },
3276
3277 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA0, RB } },
3278
3279 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA0, RB } },
3280 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
3281
3282 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA0, RB } },
3283
3284 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3285
3286 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
3287 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
3288
3289 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
3290 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
3291
3292 { "prtyw",   X(31,154), XRB_MASK,       POWER6,         { RA, RS } },
3293
3294 { "wrteei",  X(31,163), XE_MASK,        PPC403 | BOOKE, { E } },
3295
3296 { "dcbtls",  X(31,166), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3297 { "dcbtlse", X(31,174), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3298
3299 { "mtmsrd",  X(31,178), XRLARB_MASK,    PPC64,          { RS, A_L } },
3300
3301 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
3302
3303 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
3304 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA0, RB } },
3305
3306 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
3307 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
3308
3309 { "prtyd",   X(31,186), XRB_MASK,       POWER6,         { RA, RS } },
3310
3311 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3312
3313 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3314 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3315 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3316 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3317 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3318 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3319 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3320 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3321
3322 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3323 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3324 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3325 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3326 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3327 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3328 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3329 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3330
3331 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
3332
3333 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA0, RB } },
3334
3335 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA0, RB } },
3336
3337 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
3338 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
3339
3340 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
3341 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
3342
3343 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3344
3345 { "icblc",   X(31,230), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3346
3347 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3348 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3349 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3350 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3351 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3352 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3353 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3354 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3355
3356 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3357 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3358 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3359 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3360
3361 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3362 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3363 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3364 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3365 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3366 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3367 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3368 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3369
3370 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3371 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3372 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3373 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3374 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3375 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3376 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3377 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3378
3379 { "icblce",  X(31,238), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3380 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
3381 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
3382
3383 { "dcbtst",  X(31,246), X_MASK, PPC,                    { CT, RA, RB } },
3384
3385 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
3386
3387 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
3388 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
3389
3390 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
3391
3392 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3393
3394 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
3395
3396 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3397 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3398 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3399 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3400
3401 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3402 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3403 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3404 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3405 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3406 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3407 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3408 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3409
3410 { "tlbiel",  X(31,274), XRTLRA_MASK,    POWER4,         { RB, L } },
3411
3412 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
3413
3414 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
3415 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
3416
3417 { "dcbt",    X(31,278), X_MASK,         PPC,            { CT, RA, RB } },
3418
3419 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA0, RB } },
3420
3421 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
3422 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
3423
3424 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
3425
3426 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3427
3428 { "tlbie",   X(31,306), XRTLRA_MASK,    PPC,            { RB, L } },
3429 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA0, RB } },
3430
3431 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
3432
3433 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
3434
3435 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
3436 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
3437
3438 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3439
3440 { "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,      { RT } },
3441 { "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,      { RT } },
3442 { "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
3443 { "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
3444 { "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
3445 { "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
3446 { "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
3447 { "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
3448 { "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
3449 { "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
3450 { "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
3451 { "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
3452 { "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
3453 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
3454 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
3455 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
3456 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
3457 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
3458 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
3459 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
3460 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
3461 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
3462 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
3463 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
3464 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
3465 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
3466 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
3467 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
3468 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
3469 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
3470 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
3471 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
3472 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
3473 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
3474 { "mfdcr",    X(31,323),        X_MASK, PPC403 | BOOKE, { RT, SPR } },
3475
3476 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3477 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3478 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3479 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3480
3481 { "mfpmr",   X(31,334), X_MASK,         PPCPMR,         { RT, PMR }},
3482
3483 { "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,     { RT } },
3484 { "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,      { RT } },
3485 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,      { RT } },
3486 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,      { RT } },
3487 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,   { RT } },
3488 { "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,   { RT } },
3489 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,      { RT } },
3490 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,      { RT } },
3491 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,    { RT } },
3492 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,      { RT } },
3493 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,      { RT } },
3494 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,    { RT } },
3495 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,      { RT } },
3496 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,      { RT } },
3497 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,      { RT } },
3498 { "mfcfar",     XSPR(31,339,28),   XSPR_MASK, POWER6,   { RT } },
3499 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3500 { "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
3501 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3502 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3503 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3504 { "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,   { RT } },
3505 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3506 { "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,   { RT } },
3507 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3508 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,   { RT } },
3509 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,   { RT } },
3510 { "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,   { RT } },
3511 { "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,   { RT } },
3512 { "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,   { RT } },
3513 { "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,   { RT } },
3514 { "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,   { RT } },
3515 { "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,   { RT } },
3516 { "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,   { RT } },
3517 { "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,   { RT } },
3518 { "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,   { RT } },
3519 { "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,   { RT } },
3520 { "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,   { RT } },
3521 { "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,   { RT } },
3522 { "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,   { RT } },
3523 { "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,   { RT } },
3524 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,   { RT } },
3525 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3526 { "mftb",       X(31,371),         X_MASK,    CLASSIC,  { RT, TBR } },
3527 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3528 { "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,  { RT } },
3529 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3530 { "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,  { RT } },
3531 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3532 { "mfsprg",     XSPR(31,339,256),  XSPRG_MASK, PPC,     { RT, SPRG } },
3533 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,      { RT } },
3534 { "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,      { RT } },
3535 { "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,      { RT } },
3536 { "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,      { RT } },
3537 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3538 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3539 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3540 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3541 { "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,    { RT } },
3542 { "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,      { RT } },
3543 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3544 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,      { RT } },
3545 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3546 { "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   { RT } },
3547 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3548 { "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   { RT } },
3549 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3550 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
3551 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3552 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3553 { "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   { RT } },
3554 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3555 { "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   { RT } },
3556 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3557 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
3558 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3559 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
3560 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3561 { "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   { RT } },
3562 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3563 { "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   { RT } },
3564 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3565 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
3566 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3567 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
3568 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3569 { "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,   { RT } },
3570 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3571 { "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,   { RT } },
3572 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3573 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3574 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3575 { "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3576 { "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3577 { "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3578 { "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3579 { "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3580 { "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3581 { "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3582 { "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3583 { "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3584 { "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3585 { "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3586 { "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3587 { "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3588 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,   { RT } },
3589 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3590 { "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
3591 { "mfivor32",   XSPR(31,339,528),  XSPR_MASK, PPCSPE,   { RT } },
3592 { "mfivor33",   XSPR(31,339,529),  XSPR_MASK, PPCSPE,   { RT } },
3593 { "mfivor34",   XSPR(31,339,530),  XSPR_MASK, PPCSPE,   { RT } },
3594 { "mfivor35",   XSPR(31,339,531),  XSPR_MASK, PPCPMR,   { RT } },
3595 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3596 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3597 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3598 { "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3599 { "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,   { RT } },
3600 { "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,   { RT } },
3601 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,   { RT } },
3602 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,   { RT } },
3603 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,   { RT } },
3604 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3605 { "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,   { RT } },
3606 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3607 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3608 { "mfmcar",     XSPR(31,339,573),  XSPR_MASK, PPCRFMCI, { RT } },
3609 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,   { RT } },
3610 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,   { RT } },
3611 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,   { RT } },
3612 { "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,   { RT } },
3613 { "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,   { RT } },
3614 { "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,   { RT } },
3615 { "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,   { RT } },
3616 { "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,   { RT } },
3617 { "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,   { RT } },
3618 { "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,   { RT } },
3619 { "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,   { RT } },
3620 { "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,   { RT } },
3621 { "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,   { RT } },
3622 { "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,   { RT } },
3623 { "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,   { RT } },
3624 { "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,   { RT } },
3625 { "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,   { RT } },
3626 { "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,   { RT } },
3627 { "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,   { RT } },
3628 { "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,   { RT } },
3629 { "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,   { RT } },
3630 { "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,   { RT } },
3631 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3632 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3633 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3634 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3635 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3636 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3637 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3638 { "mfzpr",      XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
3639 { "mfccr0",     XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
3640 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
3641 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
3642 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
3643 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
3644 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
3645 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
3646 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
3647 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
3648 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
3649 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
3650 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
3651 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
3652 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,   { RT } },
3653 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,   { RT } },
3654 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,   { RT } },
3655 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,   { RT } },
3656 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,   { RT } },
3657 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,   { RT } },
3658 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,   { RT } },
3659 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3660 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   { RT } },
3661 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   { RT } },
3662 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3663 { "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   { RT } },
3664 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3665 { "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   { RT } },
3666 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3667 { "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   { RT } },
3668 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3669 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   { RT } },
3670 { "mfspr",      X(31,339),         X_MASK,    COM,      { RT, SPR } },
3671
3672 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA0, RB } },
3673
3674 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3675 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3676
3677 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA0, RB } },
3678
3679 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3680
3681 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3682 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3683
3684 { "dccci",   X(31,454), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
3685
3686 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
3687 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
3688 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
3689 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3690
3691 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3692 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3693 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3694 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3695
3696 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3697
3698 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3699
3700 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3701
3702 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3703
3704 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3705
3706 { "dcblc",   X(31,390), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3707
3708 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3709 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3710
3711 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3712 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3713
3714 { "dcblce",  X(31,398), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3715
3716 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3717
3718 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA0, RB } },
3719
3720 { "cmpb",    X(31,508), X_MASK,         POWER6,         { RA, RS, RB } },
3721
3722 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3723
3724 { "lfdpx",   X(31,791), X_MASK,         POWER6,         { FRT, RA, RB } },
3725
3726 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3727
3728 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3729
3730 { "stfdpx",  X(31,919), X_MASK,         POWER6,         { FRS, RA, RB } },
3731
3732 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3733
3734 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3735 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3736
3737 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3738 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3739
3740 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3741
3742 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3743
3744 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3745
3746 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3747
3748 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3749
3750 { "cctpl",   0x7c210b78,    0xffffffff, CELL,           { 0 }},
3751 { "cctpm",   0x7c421378,    0xffffffff, CELL,           { 0 }},
3752 { "cctph",   0x7c631b78,    0xffffffff, CELL,           { 0 }},
3753 { "db8cyc",  0x7f9ce378,    0xffffffff, CELL,           { 0 }},
3754 { "db10cyc", 0x7fbdeb78,    0xffffffff, CELL,           { 0 }},
3755 { "db12cyc", 0x7fdef378,    0xffffffff, CELL,           { 0 }},
3756 { "db16cyc", 0x7ffffb78,    0xffffffff, CELL,           { 0 }},
3757 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3758 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3759 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3760 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3761
3762 { "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,      { RS } },
3763 { "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,      { RS } },
3764 { "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,      { RS } },
3765 { "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,      { RS } },
3766 { "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,      { RS } },
3767 { "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,      { RS } },
3768 { "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,      { RS } },
3769 { "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,      { RS } },
3770 { "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,      { RS } },
3771 { "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,      { RS } },
3772 { "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,      { RS } },
3773 { "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,      { RS } },
3774 { "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,      { RS } },
3775 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RS } },
3776 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RS } },
3777 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RS } },
3778 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RS } },
3779 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RS } },
3780 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RS } },
3781 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RS } },
3782 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RS } },
3783 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RS } },
3784 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RS } },
3785 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RS } },
3786 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RS } },
3787 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RS } },
3788 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RS } },
3789 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RS } },
3790 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RS } },
3791 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RS } },
3792 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RS } },
3793 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RS } },
3794 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RS } },
3795 { "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,      { RS } },
3796 { "mtdcr",    X(31,451),        X_MASK, PPC403 | BOOKE, { SPR, RS } },
3797
3798 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3799 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3800
3801 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3802 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3803 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3804 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3805
3806 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3807 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3808
3809 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3810 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3811 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3812 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3813
3814 { "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,      { RS } },
3815 { "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,       { RS } },
3816 { "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,       { RS } },
3817 { "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,       { RS } },
3818 { "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,     { RS } },
3819 { "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,       { RS } },
3820 { "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,       { RS } },
3821 { "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,       { RS } },
3822 { "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,       { RS } },
3823 { "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,       { RS } },
3824 { "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,     { RS } },
3825 { "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,       { RS } },
3826 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,       { RS } },
3827 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,       { RS } },
3828 { "mtcfar",    XSPR(31,467,28),   XSPR_MASK, POWER6,    { RS } },
3829 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
3830 { "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,    { RS } },
3831 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
3832 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
3833 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
3834 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
3835 { "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,    { RS } },
3836 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
3837 { "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,    { RS } },
3838 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
3839 { "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,    { RS } },
3840 { "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,    { RS } },
3841 { "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,    { RS } },
3842 { "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,    { RS } },
3843 { "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,    { RS } },
3844 { "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,    { RS } },
3845 { "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,    { RS } },
3846 { "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,    { RS } },
3847 { "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,    { RS } },
3848 { "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,    { RS } },
3849 { "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,    { RS } },
3850 { "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,    { RS } },
3851 { "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,    { RS } },
3852 { "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,    { RS } },
3853 { "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,    { RS } },
3854 { "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,    { RS } },
3855 { "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,    { RS } },
3856 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
3857 { "mtsprg",    XSPR(31,467,256),  XSPRG_MASK,PPC,       { SPRG, RS } },
3858 { "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,       { RS } },
3859 { "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,       { RS } },
3860 { "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,       { RS } },
3861 { "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,       { RS } },
3862 { "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3863 { "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3864 { "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3865 { "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3866 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,     { RS } },
3867 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,       { RS } },
3868 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,       { RS } },
3869 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,       { RS } },
3870 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
3871 { "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,    { RS } },
3872 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
3873 { "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,    { RS } },
3874 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
3875 { "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,    { RS } },
3876 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
3877 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
3878 { "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,    { RS } },
3879 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
3880 { "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,    { RS } },
3881 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
3882 { "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,    { RS } },
3883 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
3884 { "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,    { RS } },
3885 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
3886 { "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,    { RS } },
3887 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
3888 { "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,    { RS } },
3889 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
3890 { "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,    { RS } },
3891 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
3892 { "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,    { RS } },
3893 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
3894 { "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,    { RS } },
3895 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
3896 { "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,    { RS } },
3897 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
3898 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
3899 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
3900 { "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
3901 { "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
3902 { "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
3903 { "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
3904 { "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
3905 { "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
3906 { "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
3907 { "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
3908 { "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
3909 { "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
3910 { "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
3911 { "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
3912 { "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
3913 { "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
3914 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
3915 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
3916 { "mtivor32",  XSPR(31,467,528),  XSPR_MASK, PPCSPE,    { RS } },
3917 { "mtivor33",  XSPR(31,467,529),  XSPR_MASK, PPCSPE,    { RS } },
3918 { "mtivor34",  XSPR(31,467,530),  XSPR_MASK, PPCSPE,    { RS } },
3919 { "mtivor35",  XSPR(31,467,531),  XSPR_MASK, PPCPMR,    { RS } },
3920 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3921 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3922 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3923 { "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3924 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
3925 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
3926 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
3927 { "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
3928 { "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
3929 { "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
3930 { "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
3931 { "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
3932 { "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
3933 { "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
3934 { "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,    { RS } },
3935 { "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,    { RS } },
3936 { "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
3937 { "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,    { RS } },
3938 { "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
3939 { "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,    { RS } },
3940 { "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
3941 { "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,    { RS } },
3942 { "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
3943 { "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,    { RS } },
3944 { "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
3945 { "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
3946 { "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
3947 { "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,    { RS } },
3948 { "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,    { RS } },
3949 { "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,    { RS } },
3950 { "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,    { RS } },
3951 { "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,    { RS } },
3952 { "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,    { RS } },
3953 { "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,    { RS } },
3954 { "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,    { RS } },
3955 { "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
3956 { "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,    { RS } },
3957 { "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,    { RS } },
3958 { "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
3959 { "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,    { RS } },
3960 { "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
3961 { "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,    { RS } },
3962 { "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
3963 { "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,    { RS } },
3964 { "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
3965 { "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,    { RS } },
3966 { "mtspr",     X(31,467),         X_MASK,    COM,       { SPR, RS } },
3967
3968 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
3969
3970 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
3971 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
3972
3973 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
3974
3975 { "dcread",  X(31,486), X_MASK,         PPC403|PPC440,  { RT, RA, RB }},
3976
3977 { "mtpmr",   X(31,462), X_MASK,         PPCPMR,         { PMR, RS }},
3978
3979 { "icbtls",  X(31,486), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3980
3981 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
3982 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3983 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
3984 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
3985 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3986 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
3987
3988 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3989 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3990 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3991 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3992
3993 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3994 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3995
3996 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3997 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3998 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3999 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
4000
4001 { "icbtlse", X(31,494), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
4002
4003 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
4004
4005 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
4006
4007 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
4008
4009 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
4010
4011 { "bblels",  X(31,518), X_MASK,         PPCBRLK,        { 0 }},
4012 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64,    { BF } },
4013
4014 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
4015
4016 { "ldbrx",   X(31,532), X_MASK,         CELL,           { RT, RA0, RB } },
4017
4018 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4019 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
4020
4021 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4022 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
4023
4024 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA0, RB } },
4025
4026 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4027 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4028 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4029 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4030
4031 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
4032 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
4033
4034 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
4035 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
4036
4037 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
4038 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
4039
4040 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4041
4042 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4043
4044 { "bbelr",   X(31,550), X_MASK,         PPCBRLK,        { 0 }},
4045
4046 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
4047
4048 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
4049
4050 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4051
4052 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
4053
4054 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA0, NB } },
4055 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA0, NB } },
4056
4057 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,          { 0 } },
4058 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
4059 { "msync",   X(31,598), 0xffffffff,     BOOKE,          { 0 } },
4060 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
4061 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
4062
4063 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA0, RB } },
4064
4065 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4066
4067 { "mffgpr",  XRC(31,607,0), XRA_MASK,   POWER6,         { FRT, RB } },
4068
4069 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
4070
4071 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
4072
4073 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
4074
4075 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4076
4077 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
4078
4079 { "stdbrx",  X(31,660), X_MASK,         CELL,           { RS, RA0, RB } },
4080
4081 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4082 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4083
4084 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4085 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4086
4087 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA0, RB } },
4088
4089 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
4090 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
4091
4092 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
4093 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
4094
4095 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4096
4097 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4098
4099 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
4100
4101 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
4102 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
4103
4104 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4105
4106 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA0, NB } },
4107 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA0, NB } },
4108
4109 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA0, RB } },
4110
4111 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
4112 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
4113
4114 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
4115 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
4116
4117 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4118
4119 { "mftgpr",  XRC(31,735,0), XRA_MASK,   POWER6,         { RT, FRB } },
4120
4121 { "dcba",    X(31,758), XRT_MASK,       PPC405 | BOOKE, { RA, RB } },
4122
4123 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
4124
4125 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
4126 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
4127
4128 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
4129
4130 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4131
4132 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
4133 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE64,        { RA, RB } },
4134
4135 { "lwzcix",  X(31,789), X_MASK,         POWER6,         { RT, RA0, RB } },
4136
4137 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA0, RB } },
4138
4139 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4140 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4141 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4142 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4143
4144 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
4145 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
4146
4147 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4148
4149 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4150 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4151
4152 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
4153
4154 { "lhzcix",  X(31,821), X_MASK,         POWER6,         { RT, RA0, RB } },
4155
4156 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
4157 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { 0 } },
4158
4159 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
4160 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
4161 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
4162 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
4163
4164 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
4165
4166 { "lbzcix",  X(31,853), X_MASK,         POWER6,         { RT, RA0, RB } },
4167
4168 { "mbar",    X(31,854), X_MASK,         BOOKE,          { MO } },
4169 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
4170
4171 { "lfiwax",  X(31,855), X_MASK,         POWER6,         { FRT, RA0, RB } },
4172
4173 { "ldcix",   X(31,885), X_MASK,         POWER6,         { RT, RA0, RB } },
4174
4175 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403|BOOKE,   { RTO, RA, RB } },
4176 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403|BOOKE,   { RTO, RA, RB } },
4177 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE64,        { RTO, RA, RB } },
4178 { "tlbsxe.", XRC(31,915,1), X_MASK,     BOOKE64,        { RTO, RA, RB } },
4179
4180 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
4181
4182 { "stwcix",  X(31,917), X_MASK,         POWER6,         { RS, RA0, RB } },
4183
4184 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA0, RB } },
4185
4186 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
4187 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
4188
4189 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
4190 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
4191
4192 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
4193 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
4194 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
4195 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
4196
4197 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4198
4199 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4200
4201 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
4202 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
4203 { "tlbre",   X(31,946), X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
4204
4205 { "sthcix",  X(31,949), X_MASK,         POWER6,         { RS, RA0, RB } },
4206
4207 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
4208 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
4209
4210 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
4211 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
4212
4213 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
4214
4215 { "iccci",   X(31,966), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4216
4217 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
4218 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
4219 { "tlbwe",   X(31,978), X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
4220 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
4221
4222 { "stbcix",  X(31,981), X_MASK,         POWER6,         { RS, RA0, RB } },
4223
4224 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
4225
4226 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA0, RB } },
4227
4228 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC64 | BOOKE64,{ RA, RS } },
4229 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC64,          { RA, RS } },
4230
4231 { "icread",  X(31,998), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4232
4233 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
4234 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4235
4236 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
4237
4238 { "stdcix",  X(31,1013), X_MASK,        POWER6,         { RS, RA0, RB } },
4239
4240 { "dcbzl",   XOPL(31,1014,1), XRT_MASK,POWER4,            { RA, RB } },
4241 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4242 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4243
4244 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
4245
4246 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
4247 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
4248 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
4249 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
4250 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
4251 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
4252 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
4253 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
4254 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
4255 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
4256 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
4257 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
4258
4259 /* New load/store left/right index vector instructions that are in the Cell only.  */
4260 { "lvlx",    X(31, 519), X_MASK,        CELL,           { VD, RA0, RB } },
4261 { "lvlxl",   X(31, 775), X_MASK,        CELL,           { VD, RA0, RB } },
4262 { "lvrx",    X(31, 551), X_MASK,        CELL,           { VD, RA0, RB } },
4263 { "lvrxl",   X(31, 807), X_MASK,        CELL,           { VD, RA0, RB } },
4264 { "stvlx",   X(31, 647), X_MASK,        CELL,           { VS, RA0, RB } },
4265 { "stvlxl",  X(31, 903), X_MASK,        CELL,           { VS, RA0, RB } },
4266 { "stvrx",   X(31, 679), X_MASK,        CELL,           { VS, RA0, RB } },
4267 { "stvrxl",  X(31, 935), X_MASK,        CELL,           { VS, RA0, RB } },
4268
4269 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
4270 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4271
4272 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
4273 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4274
4275 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA0 } },
4276
4277 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
4278
4279 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4280 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4281
4282 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
4283 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4284
4285 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA0 } },
4286
4287 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
4288
4289 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA0 } },
4290
4291 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
4292
4293 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA0 } },
4294
4295 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
4296
4297 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA0 } },
4298
4299 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
4300
4301 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
4302 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4303
4304 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4305 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4306
4307 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA0 } },
4308
4309 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
4310
4311 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA0 } },
4312
4313 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
4314
4315 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA0 } },
4316
4317 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
4318
4319 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA0 } },
4320
4321 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
4322
4323 { "lq",      OP(56),    OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },
4324
4325 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4326
4327 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4328
4329 { "lfdp",    OP(57),    OP_MASK,        POWER6,         { FRT, D, RA0 } },
4330
4331 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4332 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4333 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4334 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4335 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4336 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4337 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4338 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4339 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA0 } },
4340 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
4341 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4342 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4343 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4344 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4345
4346 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4347
4348 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
4349
4350 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4351
4352 { "dadd",    XRC(59,2,0), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4353 { "dadd.",   XRC(59,2,1), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4354
4355 { "dqua",    ZRC(59,3,0), Z2_MASK,      POWER6,         { FRT, FRA, FRB, RMC } },
4356 { "dqua.",   ZRC(59,3,1), Z2_MASK,      POWER6,         { FRT, FRA, FRB, RMC } },
4357
4358 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4359 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4360
4361 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4362 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4363
4364 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4365 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4366
4367 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4368 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4369
4370 { "fres",    A(59,24,0), AFRALFRC_MASK, PPC,            { FRT, FRB, A_L } },
4371 { "fres.",   A(59,24,1), AFRALFRC_MASK, PPC,            { FRT, FRB, A_L } },
4372
4373 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4374 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4375
4376 { "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5,         { FRT, FRB, A_L } },
4377 { "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5,         { FRT, FRB, A_L } },
4378
4379 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4380 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4381
4382 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4383 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4384
4385 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4386 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4387
4388 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4389 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4390
4391 { "dmul",    XRC(59,34,0), X_MASK,      POWER6,         { FRT, FRA, FRB } },
4392 { "dmul.",   XRC(59,34,1), X_MASK,      POWER6,         { FRT, FRA, FRB } },
4393
4394 { "drrnd",   ZRC(59,35,0), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4395 { "drrnd.",  ZRC(59,35,1), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4396
4397 { "dscli",   ZRC(59,66,0), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4398 { "dscli.",  ZRC(59,66,1), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4399
4400 { "dquai",   ZRC(59,67,0), Z2_MASK,     POWER6,         { TE,  FRT, FRB, RMC } },
4401 { "dquai.",  ZRC(59,67,1), Z2_MASK,     POWER6,         { TE,  FRT, FRB, RMC } },
4402
4403 { "dscri",   ZRC(59,98,0), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4404 { "dscri.",  ZRC(59,98,1), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4405
4406 { "drintx",  ZRC(59,99,0), Z2_MASK,     POWER6,         { R, FRT, FRB, RMC } },
4407 { "drintx.", ZRC(59,99,1), Z2_MASK,     POWER6,         { R, FRT, FRB, RMC } },
4408
4409 { "dcmpo",   X(59,130),    X_MASK,      POWER6,         { BF,  FRA, FRB } },
4410
4411 { "dtstex",  X(59,162),    X_MASK,      POWER6,         { BF,  FRA, FRB } },
4412 { "dtstdc",  Z(59,194),    Z_MASK,      POWER6,         { BF,  FRA, DCM } },
4413 { "dtstdg",  Z(59,226),    Z_MASK,      POWER6,         { BF,  FRA, DGM } },
4414
4415 { "drintn",  ZRC(59,227,0), Z2_MASK,    POWER6,         { R, FRT, FRB, RMC } },
4416 { "drintn.", ZRC(59,227,1), Z2_MASK,    POWER6,         { R, FRT, FRB, RMC } },
4417
4418 { "dctdp",   XRC(59,258,0), X_MASK,     POWER6,         { FRT, FRB } },
4419 { "dctdp.",  XRC(59,258,1), X_MASK,     POWER6,         { FRT, FRB } },
4420
4421 { "dctfix",  XRC(59,290,0), X_MASK,     POWER6,         { FRT, FRB } },
4422 { "dctfix.", XRC(59,290,1), X_MASK,     POWER6,         { FRT, FRB } },
4423
4424 { "ddedpd",  XRC(59,322,0), X_MASK,     POWER6,         { SP, FRT, FRB } },
4425 { "ddedpd.", XRC(59,322,1), X_MASK,     POWER6,         { SP, FRT, FRB } },
4426
4427 { "dxex",    XRC(59,354,0), X_MASK,     POWER6,         { FRT, FRB } },
4428 { "dxex.",   XRC(59,354,1), X_MASK,     POWER6,         { FRT, FRB } },
4429
4430 { "dsub",    XRC(59,514,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4431 { "dsub.",   XRC(59,514,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4432
4433 { "ddiv",    XRC(59,546,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4434 { "ddiv.",   XRC(59,546,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4435
4436 { "dcmpu",   X(59,642),     X_MASK,     POWER6,         { BF,  FRA, FRB } },
4437
4438 { "dtstsf",  X(59,674),    X_MASK,      POWER6,         { BF,  FRA, FRB } },
4439
4440 { "drsp",    XRC(59,770,0), X_MASK,     POWER6,         { FRT, FRB } },
4441 { "drsp.",   XRC(59,770,1), X_MASK,     POWER6,         { FRT, FRB } },
4442
4443 { "dcffix",  XRC(59,802,0), X_MASK,     POWER6,         { FRT, FRB } },
4444 { "dcffix.", XRC(59,802,1), X_MASK,     POWER6,         { FRT, FRB } },
4445
4446 { "denbcd",  XRC(59,834,0), X_MASK,     POWER6,         { S, FRT, FRB } },
4447 { "denbcd.", XRC(59,834,1), X_MASK,     POWER6,         { S, FRT, FRB } },
4448
4449 { "diex",    XRC(59,866,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4450 { "diex.",   XRC(59,866,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4451
4452 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
4453
4454 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
4455
4456 { "stfdp",   OP(61),    OP_MASK,        POWER6,         { FRT, D, RA0 } },
4457
4458 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4459 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4460 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4461 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4462 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4463 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4464 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA0 } },
4465 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
4466 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4467 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4468 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4469 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4470
4471 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA0 } },
4472
4473 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
4474
4475 { "stq",     DSO(62,2), DS_MASK,        POWER4,         { RSQ, DS, RA0 } },
4476
4477 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4478
4479 { "daddq",   XRC(63,2,0), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4480 { "daddq.",  XRC(63,2,1), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4481
4482 { "dquaq",   ZRC(63,3,0), Z2_MASK,      POWER6,         { FRT, FRA, FRB, RMC } },
4483 { "dquaq.",  ZRC(63,3,1), Z2_MASK,      POWER6,         { FRT, FRA, FRB, RMC } },
4484
4485 { "fcpsgn",  XRC(63,8,0), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4486 { "fcpsgn.", XRC(63,8,1), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4487
4488 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
4489 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
4490
4491 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4492 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4493 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4494 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4495
4496 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4497 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4498 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4499 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4500
4501 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4502 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4503 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4504 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4505
4506 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4507 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4508 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4509 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4510
4511 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4512 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4513 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4514 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4515
4516 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4517 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4518
4519 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4520 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4521
4522 { "fre",     A(63,24,0), AFRALFRC_MASK, POWER5,         { FRT, FRB, A_L } },
4523 { "fre.",    A(63,24,1), AFRALFRC_MASK, POWER5,         { FRT, FRB, A_L } },
4524
4525 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4526 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4527 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4528 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4529
4530 { "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC,            { FRT, FRB, A_L } },
4531 { "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC,            { FRT, FRB, A_L } },
4532
4533 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4534 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4535 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4536 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4537
4538 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4539 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4540 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4541 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4542
4543 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4544 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4545 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4546 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4547
4548 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4549 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4550 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4551 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4552
4553 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4554
4555 { "dmulq",   XRC(63,34,0), X_MASK,      POWER6,         { FRT, FRA, FRB } },
4556 { "dmulq.",  XRC(63,34,1), X_MASK,      POWER6,         { FRT, FRA, FRB } },
4557
4558 { "drrndq",  ZRC(63,35,0), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4559 { "drrndq.", ZRC(63,35,1), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4560
4561 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
4562 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
4563
4564 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
4565 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
4566
4567 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
4568
4569 { "dscliq",  ZRC(63,66,0), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4570 { "dscliq.", ZRC(63,66,1), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4571
4572 { "dquaiq",  ZRC(63,67,0), Z2_MASK,     POWER6,         { TE,  FRT, FRB, RMC } },
4573 { "dquaiq.", ZRC(63,67,1), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4574
4575 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
4576 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
4577
4578 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
4579 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
4580
4581 { "dscriq",  ZRC(63,98,0), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4582 { "dscriq.", ZRC(63,98,1), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4583
4584 { "drintxq", ZRC(63,99,0), Z2_MASK,     POWER6,         { R, FRT, FRB, RMC } },
4585 { "drintxq.",ZRC(63,99,1), Z2_MASK,     POWER6,         { R, FRT, FRB, RMC } },
4586
4587 { "dcmpoq",  X(63,130),    X_MASK,      POWER6,         { BF,  FRA, FRB } },
4588
4589 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4590 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4591
4592 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
4593 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
4594
4595 { "dtstexq", X(63,162),     X_MASK,     POWER6,         { BF,  FRA, FRB } },
4596 { "dtstdcq", Z(63,194),     Z_MASK,     POWER6,         { BF,  FRA, DCM } },
4597 { "dtstdgq", Z(63,226),     Z_MASK,     POWER6,         { BF,  FRA, DGM } },
4598
4599 { "drintnq", ZRC(63,227,0), Z2_MASK,    POWER6,         { R, FRT, FRB, RMC } },
4600 { "drintnq.",ZRC(63,227,1), Z2_MASK,    POWER6,         { R, FRT, FRB, RMC } },
4601
4602 { "dctqpq",  XRC(63,258,0), X_MASK,     POWER6,         { FRT, FRB } },
4603 { "dctqpq.", XRC(63,258,1), X_MASK,     POWER6,         { FRT, FRB } },
4604
4605 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
4606 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
4607
4608 { "dctfixq", XRC(63,290,0), X_MASK,     POWER6,         { FRT, FRB } },
4609 { "dctfixq.",XRC(63,290,1), X_MASK,     POWER6,         { FRT, FRB } },
4610
4611 { "ddedpdq", XRC(63,322,0), X_MASK,     POWER6,         { SP, FRT, FRB } },
4612 { "ddedpdq.",XRC(63,322,1), X_MASK,     POWER6,         { SP, FRT, FRB } },
4613
4614 { "dxexq",   XRC(63,354,0), X_MASK,     POWER6,         { FRT, FRB } },
4615 { "dxexq.",  XRC(63,354,1), X_MASK,     POWER6,         { FRT, FRB } },
4616
4617 { "frin",    XRC(63,392,0), XRA_MASK,   POWER5,         { FRT, FRB } },
4618 { "frin.",   XRC(63,392,1), XRA_MASK,   POWER5,         { FRT, FRB } },
4619 { "friz",    XRC(63,424,0), XRA_MASK,   POWER5,         { FRT, FRB } },
4620 { "friz.",   XRC(63,424,1), XRA_MASK,   POWER5,         { FRT, FRB } },
4621 { "frip",    XRC(63,456,0), XRA_MASK,   POWER5,         { FRT, FRB } },
4622 { "frip.",   XRC(63,456,1), XRA_MASK,   POWER5,         { FRT, FRB } },
4623 { "frim",    XRC(63,488,0), XRA_MASK,   POWER5,         { FRT, FRB } },
4624 { "frim.",   XRC(63,488,1), XRA_MASK,   POWER5,         { FRT, FRB } },
4625
4626 { "dsubq",   XRC(63,514,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4627 { "dsubq.",  XRC(63,514,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4628
4629 { "ddivq",   XRC(63,546,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4630 { "ddivq.",  XRC(63,546,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4631
4632 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
4633 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
4634
4635 { "dcmpuq",  X(63,642),     X_MASK,     POWER6,         { BF,  FRA, FRB } },
4636
4637 { "dtstsfq", X(63,674),     X_MASK,     POWER6,         { BF,  FRA, FRB } },
4638
4639 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
4640 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
4641
4642 { "drdpq",   XRC(63,770,0), X_MASK,     POWER6,         { FRT, FRB } },
4643 { "drdpq.",  XRC(63,770,1), X_MASK,     POWER6,         { FRT, FRB } },
4644
4645 { "dcffixq", XRC(63,802,0), X_MASK,     POWER6,         { FRT, FRB } },
4646 { "dcffixq.",XRC(63,802,1), X_MASK,     POWER6,         { FRT, FRB } },
4647
4648 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4649 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4650
4651 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4652 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4653
4654 { "denbcdq", XRC(63,834,0), X_MASK,     POWER6,         { S, FRT, FRB } },
4655 { "denbcdq.",XRC(63,834,1), X_MASK,     POWER6,         { S, FRT, FRB } },
4656
4657 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4658 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4659
4660 { "diexq",   XRC(63,866,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4661 { "diexq.",  XRC(63,866,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4662
4663 };
4664
4665 const int powerpc_num_opcodes =
4666   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4667 \f
4668 /* The macro table.  This is only used by the assembler.  */
4669
4670 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4671    when x=0; 32-x when x is between 1 and 31; are negative if x is
4672    negative; and are 32 or more otherwise.  This is what you want
4673    when, for instance, you are emulating a right shift by a
4674    rotate-left-and-mask, because the underlying instructions support
4675    shifts of size 0 but not shifts of size 32.  By comparison, when
4676    extracting x bits from some word you want to use just 32-x, because
4677    the underlying instructions don't support extracting 0 bits but do
4678    support extracting the whole word (32 bits in this case).  */
4679
4680 const struct powerpc_macro powerpc_macros[] = {
4681 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
4682 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
4683 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4684 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4685 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
4686 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4687 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4688 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4689 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
4690 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
4691 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4692 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4693 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
4694 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
4695 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
4696 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
4697
4698 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
4699 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
4700 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4701 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4702 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4703 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4704 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4705 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4706 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4707 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4708 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
4709 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
4710 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
4711 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
4712 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4713 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4714 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4715 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4716 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
4717 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
4718 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4719 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4720 };
4721
4722 const int powerpc_num_macros =
4723   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);