1 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
3 Generally, handle CRISv32.
4 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
5 (struct cris_disasm_data): New type.
6 (format_reg, format_hex, cris_constraint, print_flags)
7 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
9 (format_sup_reg, print_insn_crisv32_with_register_prefix)
10 (print_insn_crisv32_without_register_prefix)
11 (print_insn_crisv10_v32_with_register_prefix)
12 (print_insn_crisv10_v32_without_register_prefix)
13 (cris_parse_disassembler_options): New functions.
14 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
15 parameter. All callers changed.
16 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
18 (cris_constraint) <case 'Y', 'U'>: New cases.
19 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
21 (print_with_operands) <case 'Y'>: New case.
22 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
23 <case 'N', 'Y', 'Q'>: New cases.
24 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
25 (print_insn_cris_with_register_prefix)
26 (print_insn_cris_without_register_prefix): Call
27 cris_parse_disassembler_options.
28 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
29 for CRISv32 and the size of immediate operands. New v32-only
30 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
31 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
32 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
33 Change brp to be v3..v10.
34 (cris_support_regs): New vector.
35 (cris_opcodes): Update head comment. New format characters '[',
36 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
37 Add new opcodes for v32 and adjust existing opcodes to accommodate
38 differences to earlier variants.
39 (cris_cond15s): New vector.
41 2004-11-04 Jan Beulich <jbeulich@novell.com>
43 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
45 (Mp): Use f_mode rather than none at all.
46 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
47 replaces what previously was x_mode; x_mode now means 128-bit SSE
49 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
50 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
51 pinsrw's second operand is Edqw.
52 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
53 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
54 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
55 mode when an operand size override is present or always suffixing.
56 More instructions will need to be added to this group.
57 (putop): Handle new macro chars 'C' (short/long suffix selector),
58 'I' (Intel mode override for following macro char), and 'J' (for
59 adding the 'l' prefix to far branches in AT&T mode). When an
60 alternative was specified in the template, honor macro character when
61 specified for Intel mode.
62 (OP_E): Handle new *_mode values. Correct pointer specifications for
63 memory operands. Consolidate output of index register.
64 (OP_G): Handle new *_mode values.
65 (OP_I): Handle const_1_mode.
66 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
67 respective opcode prefix bits have been consumed.
68 (OP_EM, OP_EX): Provide some default handling for generating pointer
71 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
73 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
76 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
78 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
79 (getregliststring): Support HI/LO and user registers.
80 * crx-opc.c (crx_instruction): Update data structure according to the
81 rearrangement done in CRX opcode header file.
82 (crx_regtab): Likewise.
83 (crx_optab): Likewise.
84 (crx_instruction): Reorder load/stor instructions, remove unsupported
86 support new Co-Processor instruction 'cpi'.
88 2004-10-27 Nick Clifton <nickc@redhat.com>
90 * opcodes/iq2000-asm.c: Regenerate.
91 * opcodes/iq2000-desc.c: Regenerate.
92 * opcodes/iq2000-desc.h: Regenerate.
93 * opcodes/iq2000-dis.c: Regenerate.
94 * opcodes/iq2000-ibld.c: Regenerate.
95 * opcodes/iq2000-opc.c: Regenerate.
96 * opcodes/iq2000-opc.h: Regenerate.
98 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
100 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
101 us4, us5 (respectively).
102 Remove unsupported 'popa' instruction.
103 Reverse operands order in store co-processor instructions.
105 2004-10-15 Alan Modra <amodra@bigpond.net.au>
107 * Makefile.am: Run "make dep-am"
108 * Makefile.in: Regenerate.
110 2004-10-12 Bob Wilson <bob.wilson@acm.org>
112 * xtensa-dis.c: Use ISO C90 formatting.
114 2004-10-09 Alan Modra <amodra@bigpond.net.au>
116 * ppc-opc.c: Revert 2004-09-09 change.
118 2004-10-07 Bob Wilson <bob.wilson@acm.org>
120 * xtensa-dis.c (state_names): Delete.
121 (fetch_data): Use xtensa_isa_maxlength.
122 (print_xtensa_operand): Replace operand parameter with opcode/operand
123 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
124 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
125 instruction bundles. Use xmalloc instead of malloc.
127 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
129 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
132 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
134 * crx-opc.c (crx_instruction): Support Co-processor insns.
135 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
136 (getregliststring): Change function to use the above enum.
137 (print_arg): Handle CO-Processor insns.
138 (crx_cinvs): Add 'b' option to invalidate the branch-target
141 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
143 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
144 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
145 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
146 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
147 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
149 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
151 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
154 2004-09-30 Paul Brook <paul@codesourcery.com>
156 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
157 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
159 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
161 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
162 (CONFIG_STATUS_DEPENDENCIES): New.
164 (config.status): Likewise.
165 * Makefile.in: Regenerated.
167 2004-09-17 Alan Modra <amodra@bigpond.net.au>
169 * Makefile.am: Run "make dep-am".
170 * Makefile.in: Regenerate.
171 * aclocal.m4: Regenerate.
172 * configure: Regenerate.
173 * po/POTFILES.in: Regenerate.
174 * po/opcodes.pot: Regenerate.
176 2004-09-11 Andreas Schwab <schwab@suse.de>
178 * configure: Rebuild.
180 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
182 * ppc-opc.c (L): Make this field not optional.
184 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
186 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
187 Fix parameter to 'm[t|f]csr' insns.
189 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
191 * configure.in: Autoupdate to autoconf 2.59.
192 * aclocal.m4: Rebuild with aclocal 1.4p6.
193 * configure: Rebuild with autoconf 2.59.
194 * Makefile.in: Rebuild with automake 1.4p6 (picking up
195 bfd changes for autoconf 2.59 on the way).
196 * config.in: Rebuild with autoheader 2.59.
198 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
200 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
202 2004-07-30 Michal Ludvig <mludvig@suse.cz>
204 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
205 (GRPPADLCK2): New define.
206 (twobyte_has_modrm): True for 0xA6.
207 (grps): GRPPADLCK2 for opcode 0xA6.
209 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
211 Introduce SH2a support.
212 * sh-opc.h (arch_sh2a_base): Renumber.
213 (arch_sh2a_nofpu_base): Remove.
214 (arch_sh_base_mask): Adjust.
215 (arch_opann_mask): New.
216 (arch_sh2a, arch_sh2a_nofpu): Adjust.
217 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
218 (sh_table): Adjust whitespace.
219 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
220 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
221 instruction list throughout.
222 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
223 of arch_sh2a in instruction list throughout.
224 (arch_sh2e_up): Accomodate above changes.
225 (arch_sh2_up): Ditto.
226 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
227 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
228 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
229 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
230 * sh-opc.h (arch_sh2a_nofpu): New.
231 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
232 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
234 2004-01-20 DJ Delorie <dj@redhat.com>
235 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
236 2003-12-29 DJ Delorie <dj@redhat.com>
237 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
238 sh_opcode_info, sh_table): Add sh2a support.
239 (arch_op32): New, to tag 32-bit opcodes.
240 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
241 2003-12-02 Michael Snyder <msnyder@redhat.com>
242 * sh-opc.h (arch_sh2a): Add.
243 * sh-dis.c (arch_sh2a): Handle.
244 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
246 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
248 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
250 2004-07-22 Nick Clifton <nickc@redhat.com>
253 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
254 insns - this is done by objdump itself.
255 * h8500-dis.c (print_insn_h8500): Likewise.
257 2004-07-21 Jan Beulich <jbeulich@novell.com>
259 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
260 regardless of address size prefix in effect.
261 (ptr_reg): Size or address registers does not depend on rex64, but
262 on the presence of an address size override.
263 (OP_MMX): Use rex.x only for xmm registers.
264 (OP_EM): Use rex.z only for xmm registers.
266 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
268 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
269 move/branch operations to the bottom so that VR5400 multimedia
270 instructions take precedence in disassembly.
272 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
274 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
275 ISA-specific "break" encoding.
277 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
279 * arm-opc.h: Fix typo in comment.
281 2004-07-11 Andreas Schwab <schwab@suse.de>
283 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
285 2004-07-09 Andreas Schwab <schwab@suse.de>
287 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
289 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
291 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
292 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
293 (crx-dis.lo): New target.
294 (crx-opc.lo): Likewise.
295 * Makefile.in: Regenerate.
296 * configure.in: Handle bfd_crx_arch.
297 * configure: Regenerate.
298 * crx-dis.c: New file.
299 * crx-opc.c: New file.
300 * disassemble.c (ARCH_crx): Define.
301 (disassembler): Handle ARCH_crx.
303 2004-06-29 James E Wilson <wilson@specifixinc.com>
305 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
306 * ia64-asmtab.c: Regnerate.
308 2004-06-28 Alan Modra <amodra@bigpond.net.au>
310 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
311 (extract_fxm): Don't test dialect.
312 (XFXFXM_MASK): Include the power4 bit.
313 (XFXM): Add p4 param.
314 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
316 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
318 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
319 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
321 2004-06-26 Alan Modra <amodra@bigpond.net.au>
323 * ppc-opc.c (BH, XLBH_MASK): Define.
324 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
326 2004-06-24 Alan Modra <amodra@bigpond.net.au>
328 * i386-dis.c (x_mode): Comment.
329 (two_source_ops): File scope.
330 (float_mem): Correct fisttpll and fistpll.
331 (float_mem_mode): New table.
333 (OP_E): Correct intel mode PTR output.
334 (ptr_reg): Use open_char and close_char.
335 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
336 operands. Set two_source_ops.
338 2004-06-15 Alan Modra <amodra@bigpond.net.au>
340 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
341 instead of _raw_size.
343 2004-06-08 Jakub Jelinek <jakub@redhat.com>
345 * ia64-gen.c (in_iclass): Handle more postinc st
347 * ia64-asmtab.c: Rebuilt.
349 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
351 * s390-opc.txt: Correct architecture mask for some opcodes.
352 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
353 in the esa mode as well.
355 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
357 * sh-dis.c (target_arch): Make unsigned.
358 (print_insn_sh): Replace (most of) switch with a call to
359 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
360 * sh-opc.h: Redefine architecture flags values.
361 Add sh3-nommu architecture.
362 Reorganise <arch>_up macros so they make more visual sense.
363 (SH_MERGE_ARCH_SET): Define new macro.
364 (SH_VALID_BASE_ARCH_SET): Likewise.
365 (SH_VALID_MMU_ARCH_SET): Likewise.
366 (SH_VALID_CO_ARCH_SET): Likewise.
367 (SH_VALID_ARCH_SET): Likewise.
368 (SH_MERGE_ARCH_SET_VALID): Likewise.
369 (SH_ARCH_SET_HAS_FPU): Likewise.
370 (SH_ARCH_SET_HAS_DSP): Likewise.
371 (SH_ARCH_UNKNOWN_ARCH): Likewise.
372 (sh_get_arch_from_bfd_mach): Add prototype.
373 (sh_get_arch_up_from_bfd_mach): Likewise.
374 (sh_get_bfd_mach_from_arch_set): Likewise.
375 (sh_merge_bfd_arc): Likewise.
377 2004-05-24 Peter Barada <peter@the-baradas.com>
379 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
380 into new match_insn_m68k function. Loop over canidate
381 matches and select first that completely matches.
382 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
383 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
384 to verify addressing for MAC/EMAC.
385 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
386 reigster halves since 'fpu' and 'spl' look misleading.
387 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
388 * m68k-opc.c: Rearragne mac/emac cases to use longest for
389 first, tighten up match masks.
390 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
391 'size' from special case code in print_insn_m68k to
392 determine decode size of insns.
394 2004-05-19 Alan Modra <amodra@bigpond.net.au>
396 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
397 well as when -mpower4.
399 2004-05-13 Nick Clifton <nickc@redhat.com>
401 * po/fr.po: Updated French translation.
403 2004-05-05 Peter Barada <peter@the-baradas.com>
405 * m68k-dis.c(print_insn_m68k): Add new chips, use core
406 variants in arch_mask. Only set m68881/68851 for 68k chips.
407 * m68k-op.c: Switch from ColdFire chips to core variants.
409 2004-05-05 Alan Modra <amodra@bigpond.net.au>
412 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
414 2004-04-29 Ben Elliston <bje@au.ibm.com>
416 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
417 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
419 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
421 * sh-dis.c (print_insn_sh): Print the value in constant pool
422 as a symbol if it looks like a symbol.
424 2004-04-22 Peter Barada <peter@the-baradas.com>
426 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
427 appropriate ColdFire architectures.
428 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
430 Add EMAC instructions, fix MAC instructions. Remove
431 macmw/macml/msacmw/msacml instructions since mask addressing now
434 2004-04-20 Jakub Jelinek <jakub@redhat.com>
436 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
437 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
438 suffix. Use fmov*x macros, create all 3 fpsize variants in one
439 macro. Adjust all users.
441 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
443 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
446 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
448 * m32r-asm.c: Regenerate.
450 2004-03-29 Stan Shebs <shebs@apple.com>
452 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
455 2004-03-19 Alan Modra <amodra@bigpond.net.au>
457 * aclocal.m4: Regenerate.
458 * config.in: Regenerate.
459 * configure: Regenerate.
460 * po/POTFILES.in: Regenerate.
461 * po/opcodes.pot: Regenerate.
463 2004-03-16 Alan Modra <amodra@bigpond.net.au>
465 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
467 * ppc-opc.c (RA0): Define.
468 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
469 (RAOPT): Rename from RAO. Update all uses.
470 (powerpc_opcodes): Use RA0 as appropriate.
472 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
474 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
476 2004-03-15 Alan Modra <amodra@bigpond.net.au>
478 * sparc-dis.c (print_insn_sparc): Update getword prototype.
480 2004-03-12 Michal Ludvig <mludvig@suse.cz>
482 * i386-dis.c (GRPPLOCK): Delete.
483 (grps): Delete GRPPLOCK entry.
485 2004-03-12 Alan Modra <amodra@bigpond.net.au>
487 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
489 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
491 (dis386): Use NOP_Fixup on "nop".
492 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
493 (twobyte_has_modrm): Set for 0xa7.
494 (padlock_table): Delete. Move to..
495 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
497 (print_insn): Revert PADLOCK_SPECIAL code.
498 (OP_E): Delete sfence, lfence, mfence checks.
500 2004-03-12 Jakub Jelinek <jakub@redhat.com>
502 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
503 (INVLPG_Fixup): New function.
504 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
506 2004-03-12 Michal Ludvig <mludvig@suse.cz>
508 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
509 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
510 (padlock_table): New struct with PadLock instructions.
511 (print_insn): Handle PADLOCK_SPECIAL.
513 2004-03-12 Alan Modra <amodra@bigpond.net.au>
515 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
516 (OP_E): Twiddle clflush to sfence here.
518 2004-03-08 Nick Clifton <nickc@redhat.com>
520 * po/de.po: Updated German translation.
522 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
524 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
525 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
526 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
529 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
531 * frv-asm.c: Regenerate.
532 * frv-desc.c: Regenerate.
533 * frv-desc.h: Regenerate.
534 * frv-dis.c: Regenerate.
535 * frv-ibld.c: Regenerate.
536 * frv-opc.c: Regenerate.
537 * frv-opc.h: Regenerate.
539 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
541 * frv-desc.c, frv-opc.c: Regenerate.
543 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
545 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
547 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
549 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
550 Also correct mistake in the comment.
552 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
554 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
555 ensure that double registers have even numbers.
556 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
557 that reserved instruction 0xfffd does not decode the same
559 * sh-opc.h: Add REG_N_D nibble type and use it whereever
560 REG_N refers to a double register.
561 Add REG_N_B01 nibble type and use it instead of REG_NM
563 Adjust the bit patterns in a few comments.
565 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
567 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
569 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
571 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
573 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
575 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
577 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
579 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
580 mtivor32, mtivor33, mtivor34.
582 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
584 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
586 2004-02-10 Petko Manolov <petkan@nucleusys.com>
588 * arm-opc.h Maverick accumulator register opcode fixes.
590 2004-02-13 Ben Elliston <bje@wasabisystems.com>
592 * m32r-dis.c: Regenerate.
594 2004-01-27 Michael Snyder <msnyder@redhat.com>
596 * sh-opc.h (sh_table): "fsrra", not "fssra".
598 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
600 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
603 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
605 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
607 2004-01-19 Alan Modra <amodra@bigpond.net.au>
609 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
610 1. Don't print scale factor on AT&T mode when index missing.
612 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
614 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
615 when loaded into XR registers.
617 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
619 * frv-desc.h: Regenerate.
620 * frv-desc.c: Regenerate.
621 * frv-opc.c: Regenerate.
623 2004-01-13 Michael Snyder <msnyder@redhat.com>
625 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
627 2004-01-09 Paul Brook <paul@codesourcery.com>
629 * arm-opc.h (arm_opcodes): Move generic mcrr after known
632 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
634 * Makefile.am (libopcodes_la_DEPENDENCIES)
635 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
636 comment about the problem.
637 * Makefile.in: Regenerate.
639 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
641 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
642 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
643 cut&paste errors in shifting/truncating numerical operands.
644 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
645 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
646 (parse_uslo16): Likewise.
647 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
648 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
649 (parse_s12): Likewise.
650 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
651 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
652 (parse_uslo16): Likewise.
653 (parse_uhi16): Parse gothi and gotfuncdeschi.
654 (parse_d12): Parse got12 and gotfuncdesc12.
655 (parse_s12): Likewise.
657 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
659 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
660 instruction which looks similar to an 'rla' instruction.
662 For older changes see ChangeLog-0203
668 version-control: never