1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
33 #include "dwarf2dbg.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
55 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
56 static int fits_in_signed_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
58 static int fits_in_unsigned_word
PARAMS ((offsetT
));
59 static int fits_in_signed_word
PARAMS ((offsetT
));
60 static int fits_in_unsigned_long
PARAMS ((offsetT
));
61 static int fits_in_signed_long
PARAMS ((offsetT
));
62 static int smallest_imm_type
PARAMS ((offsetT
));
63 static offsetT offset_in_range
PARAMS ((offsetT
, int));
64 static int add_prefix
PARAMS ((unsigned int));
65 static void set_code_flag
PARAMS ((int));
66 static void set_16bit_gcc_code_flag
PARAMS ((int));
67 static void set_intel_syntax
PARAMS ((int));
68 static void set_cpu_arch
PARAMS ((int));
71 static bfd_reloc_code_real_type reloc
72 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
73 #define RELOC_ENUM enum bfd_reloc_code_real
75 #define RELOC_ENUM int
79 #define DEFAULT_ARCH "i386"
81 static char *default_arch
= DEFAULT_ARCH
;
83 /* 'md_assemble ()' gathers together information and puts it into a
90 const reg_entry
*regs
;
95 /* TM holds the template for the insn were currently assembling. */
98 /* SUFFIX holds the instruction mnemonic suffix if given.
99 (e.g. 'l' for 'movl') */
102 /* OPERANDS gives the number of given operands. */
103 unsigned int operands
;
105 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
106 of given register, displacement, memory operands and immediate
108 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
110 /* TYPES [i] is the type (see above #defines) which tells us how to
111 use OP[i] for the corresponding operand. */
112 unsigned int types
[MAX_OPERANDS
];
114 /* Displacement expression, immediate expression, or register for each
116 union i386_op op
[MAX_OPERANDS
];
118 /* Flags for operands. */
119 unsigned int flags
[MAX_OPERANDS
];
120 #define Operand_PCrel 1
122 /* Relocation type for operand */
123 RELOC_ENUM reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
243 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
245 static enum flag_code flag_code
;
246 static int use_rela_relocations
= 0;
248 /* The names used to print error messages. */
249 static const char *flag_code_names
[] =
256 /* 1 for intel syntax,
258 static int intel_syntax
= 0;
260 /* 1 if register prefix % not required. */
261 static int allow_naked_reg
= 0;
263 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
264 leave, push, and pop instructions so that gcc has the same stack
265 frame as in 32 bit mode. */
266 static char stackop_size
= '\0';
268 /* Non-zero to quieten some warnings. */
269 static int quiet_warnings
= 0;
272 static const char *cpu_arch_name
= NULL
;
274 /* CPU feature flags. */
275 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
277 /* If set, conditional jumps are not automatically promoted to handle
278 larger than a byte offset. */
279 static unsigned int no_cond_jump_promotion
= 0;
281 /* Interface to relax_segment.
282 There are 3 major relax states for 386 jump insns because the
283 different types of jumps add different sizes to frags when we're
284 figuring out what sort of jump to choose to reach a given label. */
287 #define UNCOND_JUMP 0
289 #define COND_JUMP86 2
294 #define SMALL16 (SMALL|CODE16)
296 #define BIG16 (BIG|CODE16)
300 #define INLINE __inline__
306 #define ENCODE_RELAX_STATE(type, size) \
307 ((relax_substateT) (((type) << 2) | (size)))
308 #define TYPE_FROM_RELAX_STATE(s) \
310 #define DISP_SIZE_FROM_RELAX_STATE(s) \
311 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
313 /* This table is used by relax_frag to promote short jumps to long
314 ones where necessary. SMALL (short) jumps may be promoted to BIG
315 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
316 don't allow a short jump in a 32 bit code segment to be promoted to
317 a 16 bit offset jump because it's slower (requires data size
318 prefix), and doesn't work, unless the destination is in the bottom
319 64k of the code segment (The top 16 bits of eip are zeroed). */
321 const relax_typeS md_relax_table
[] =
324 1) most positive reach of this state,
325 2) most negative reach of this state,
326 3) how many bytes this mode will have in the variable part of the frag
327 4) which index into the table to try if we can't fit into this one. */
329 /* UNCOND_JUMP states. */
330 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
331 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
332 /* dword jmp adds 4 bytes to frag:
333 0 extra opcode bytes, 4 displacement bytes. */
335 /* word jmp adds 2 byte2 to frag:
336 0 extra opcode bytes, 2 displacement bytes. */
339 /* COND_JUMP states. */
340 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
341 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
342 /* dword conditionals adds 5 bytes to frag:
343 1 extra opcode byte, 4 displacement bytes. */
345 /* word conditionals add 3 bytes to frag:
346 1 extra opcode byte, 2 displacement bytes. */
349 /* COND_JUMP86 states. */
350 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
351 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
352 /* dword conditionals adds 5 bytes to frag:
353 1 extra opcode byte, 4 displacement bytes. */
355 /* word conditionals add 4 bytes to frag:
356 1 displacement byte and a 3 byte long branch insn. */
360 static const arch_entry cpu_arch
[] = {
362 {"i186", Cpu086
|Cpu186
},
363 {"i286", Cpu086
|Cpu186
|Cpu286
},
364 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
365 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
366 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
367 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
368 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
369 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
370 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
371 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
372 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
373 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
378 i386_align_code (fragP
, count
)
382 /* Various efficient no-op patterns for aligning code labels.
383 Note: Don't try to assemble the instructions in the comments.
384 0L and 0w are not legal. */
385 static const char f32_1
[] =
387 static const char f32_2
[] =
388 {0x89,0xf6}; /* movl %esi,%esi */
389 static const char f32_3
[] =
390 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
391 static const char f32_4
[] =
392 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
393 static const char f32_5
[] =
395 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
396 static const char f32_6
[] =
397 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
398 static const char f32_7
[] =
399 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
400 static const char f32_8
[] =
402 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
403 static const char f32_9
[] =
404 {0x89,0xf6, /* movl %esi,%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_10
[] =
407 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
408 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
409 static const char f32_11
[] =
410 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
411 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
412 static const char f32_12
[] =
413 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
414 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
415 static const char f32_13
[] =
416 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
417 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
418 static const char f32_14
[] =
419 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
420 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
421 static const char f32_15
[] =
422 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
423 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
424 static const char f16_3
[] =
425 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
426 static const char f16_4
[] =
427 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
428 static const char f16_5
[] =
430 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
431 static const char f16_6
[] =
432 {0x89,0xf6, /* mov %si,%si */
433 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
434 static const char f16_7
[] =
435 {0x8d,0x74,0x00, /* lea 0(%si),%si */
436 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
437 static const char f16_8
[] =
438 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
439 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
440 static const char *const f32_patt
[] = {
441 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
442 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
444 static const char *const f16_patt
[] = {
445 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
446 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
449 /* ??? We can't use these fillers for x86_64, since they often kills the
450 upper halves. Solve later. */
451 if (flag_code
== CODE_64BIT
)
454 if (count
> 0 && count
<= 15)
456 if (flag_code
== CODE_16BIT
)
458 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
459 f16_patt
[count
- 1], count
);
461 /* Adjust jump offset. */
462 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
465 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
466 f32_patt
[count
- 1], count
);
467 fragP
->fr_var
= count
;
471 static char *output_invalid
PARAMS ((int c
));
472 static int i386_operand
PARAMS ((char *operand_string
));
473 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
474 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
478 static void s_bss
PARAMS ((int));
481 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
483 static INLINE
unsigned int
484 mode_from_disp_size (t
)
487 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
491 fits_in_signed_byte (num
)
494 return (num
>= -128) && (num
<= 127);
498 fits_in_unsigned_byte (num
)
501 return (num
& 0xff) == num
;
505 fits_in_unsigned_word (num
)
508 return (num
& 0xffff) == num
;
512 fits_in_signed_word (num
)
515 return (-32768 <= num
) && (num
<= 32767);
518 fits_in_signed_long (num
)
519 offsetT num ATTRIBUTE_UNUSED
;
524 return (!(((offsetT
) -1 << 31) & num
)
525 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
527 } /* fits_in_signed_long() */
529 fits_in_unsigned_long (num
)
530 offsetT num ATTRIBUTE_UNUSED
;
535 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
537 } /* fits_in_unsigned_long() */
540 smallest_imm_type (num
)
543 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
544 && !(cpu_arch_flags
& (CpuUnknown
)))
546 /* This code is disabled on the 486 because all the Imm1 forms
547 in the opcode table are slower on the i486. They're the
548 versions with the implicitly specified single-position
549 displacement, which has another syntax if you really want to
552 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
554 return (fits_in_signed_byte (num
)
555 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
556 : fits_in_unsigned_byte (num
)
557 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
558 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
559 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
560 : fits_in_signed_long (num
)
561 ? (Imm32
| Imm32S
| Imm64
)
562 : fits_in_unsigned_long (num
)
568 offset_in_range (val
, size
)
576 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
577 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
578 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
580 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
585 /* If BFD64, sign extend val. */
586 if (!use_rela_relocations
)
587 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
588 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
590 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
592 char buf1
[40], buf2
[40];
594 sprint_value (buf1
, val
);
595 sprint_value (buf2
, val
& mask
);
596 as_warn (_("%s shortened to %s"), buf1
, buf2
);
601 /* Returns 0 if attempting to add a prefix where one from the same
602 class already exists, 1 if non rep/repne added, 2 if rep/repne
611 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
619 case CS_PREFIX_OPCODE
:
620 case DS_PREFIX_OPCODE
:
621 case ES_PREFIX_OPCODE
:
622 case FS_PREFIX_OPCODE
:
623 case GS_PREFIX_OPCODE
:
624 case SS_PREFIX_OPCODE
:
628 case REPNE_PREFIX_OPCODE
:
629 case REPE_PREFIX_OPCODE
:
632 case LOCK_PREFIX_OPCODE
:
640 case ADDR_PREFIX_OPCODE
:
644 case DATA_PREFIX_OPCODE
:
651 as_bad (_("same type of prefix used twice"));
656 i
.prefix
[q
] = prefix
;
661 set_code_flag (value
)
665 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
666 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
667 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
669 as_bad (_("64bit mode not supported on this CPU."));
671 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
673 as_bad (_("32bit mode not supported on this CPU."));
679 set_16bit_gcc_code_flag (new_code_flag
)
682 flag_code
= new_code_flag
;
683 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
684 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
689 set_intel_syntax (syntax_flag
)
692 /* Find out if register prefixing is specified. */
693 int ask_naked_reg
= 0;
696 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
698 char *string
= input_line_pointer
;
699 int e
= get_symbol_end ();
701 if (strcmp (string
, "prefix") == 0)
703 else if (strcmp (string
, "noprefix") == 0)
706 as_bad (_("bad argument to syntax directive."));
707 *input_line_pointer
= e
;
709 demand_empty_rest_of_line ();
711 intel_syntax
= syntax_flag
;
713 if (ask_naked_reg
== 0)
716 allow_naked_reg
= (intel_syntax
717 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
719 /* Conservative default. */
724 allow_naked_reg
= (ask_naked_reg
< 0);
729 int dummy ATTRIBUTE_UNUSED
;
733 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
735 char *string
= input_line_pointer
;
736 int e
= get_symbol_end ();
739 for (i
= 0; cpu_arch
[i
].name
; i
++)
741 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
743 cpu_arch_name
= cpu_arch
[i
].name
;
744 cpu_arch_flags
= (cpu_arch
[i
].flags
745 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
749 if (!cpu_arch
[i
].name
)
750 as_bad (_("no such architecture: `%s'"), string
);
752 *input_line_pointer
= e
;
755 as_bad (_("missing cpu architecture"));
757 no_cond_jump_promotion
= 0;
758 if (*input_line_pointer
== ','
759 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
761 char *string
= ++input_line_pointer
;
762 int e
= get_symbol_end ();
764 if (strcmp (string
, "nojumps") == 0)
765 no_cond_jump_promotion
= 1;
766 else if (strcmp (string
, "jumps") == 0)
769 as_bad (_("no such architecture modifier: `%s'"), string
);
771 *input_line_pointer
= e
;
774 demand_empty_rest_of_line ();
777 const pseudo_typeS md_pseudo_table
[] =
779 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
780 {"align", s_align_bytes
, 0},
782 {"align", s_align_ptwo
, 0},
784 {"arch", set_cpu_arch
, 0},
788 {"ffloat", float_cons
, 'f'},
789 {"dfloat", float_cons
, 'd'},
790 {"tfloat", float_cons
, 'x'},
792 {"noopt", s_ignore
, 0},
793 {"optim", s_ignore
, 0},
794 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
795 {"code16", set_code_flag
, CODE_16BIT
},
796 {"code32", set_code_flag
, CODE_32BIT
},
797 {"code64", set_code_flag
, CODE_64BIT
},
798 {"intel_syntax", set_intel_syntax
, 1},
799 {"att_syntax", set_intel_syntax
, 0},
800 {"file", dwarf2_directive_file
, 0},
801 {"loc", dwarf2_directive_loc
, 0},
805 /* For interface with expression (). */
806 extern char *input_line_pointer
;
808 /* Hash table for instruction mnemonic lookup. */
809 static struct hash_control
*op_hash
;
811 /* Hash table for register lookup. */
812 static struct hash_control
*reg_hash
;
818 if (!strcmp (default_arch
, "x86_64"))
819 return bfd_mach_x86_64
;
820 else if (!strcmp (default_arch
, "i386"))
821 return bfd_mach_i386_i386
;
823 as_fatal (_("Unknown architecture"));
830 const char *hash_err
;
832 /* Initialize op_hash hash table. */
833 op_hash
= hash_new ();
836 register const template *optab
;
837 register templates
*core_optab
;
839 /* Setup for loop. */
841 core_optab
= (templates
*) xmalloc (sizeof (templates
));
842 core_optab
->start
= optab
;
847 if (optab
->name
== NULL
848 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
850 /* different name --> ship out current template list;
851 add to hash table; & begin anew. */
852 core_optab
->end
= optab
;
853 hash_err
= hash_insert (op_hash
,
858 as_fatal (_("Internal Error: Can't hash %s: %s"),
862 if (optab
->name
== NULL
)
864 core_optab
= (templates
*) xmalloc (sizeof (templates
));
865 core_optab
->start
= optab
;
870 /* Initialize reg_hash hash table. */
871 reg_hash
= hash_new ();
873 register const reg_entry
*regtab
;
875 for (regtab
= i386_regtab
;
876 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
879 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
881 as_fatal (_("Internal Error: Can't hash %s: %s"),
887 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
892 for (c
= 0; c
< 256; c
++)
897 mnemonic_chars
[c
] = c
;
898 register_chars
[c
] = c
;
899 operand_chars
[c
] = c
;
901 else if (islower (c
))
903 mnemonic_chars
[c
] = c
;
904 register_chars
[c
] = c
;
905 operand_chars
[c
] = c
;
907 else if (isupper (c
))
909 mnemonic_chars
[c
] = tolower (c
);
910 register_chars
[c
] = mnemonic_chars
[c
];
911 operand_chars
[c
] = c
;
914 if (isalpha (c
) || isdigit (c
))
915 identifier_chars
[c
] = c
;
918 identifier_chars
[c
] = c
;
919 operand_chars
[c
] = c
;
924 identifier_chars
['@'] = '@';
926 digit_chars
['-'] = '-';
927 identifier_chars
['_'] = '_';
928 identifier_chars
['.'] = '.';
930 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
931 operand_chars
[(unsigned char) *p
] = *p
;
934 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
935 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
937 record_alignment (text_section
, 2);
938 record_alignment (data_section
, 2);
939 record_alignment (bss_section
, 2);
945 i386_print_statistics (file
)
948 hash_print_statistics (file
, "i386 opcode", op_hash
);
949 hash_print_statistics (file
, "i386 register", reg_hash
);
954 /* Debugging routines for md_assemble. */
955 static void pi
PARAMS ((char *, i386_insn
*));
956 static void pte
PARAMS ((template *));
957 static void pt
PARAMS ((unsigned int));
958 static void pe
PARAMS ((expressionS
*));
959 static void ps
PARAMS ((symbolS
*));
968 fprintf (stdout
, "%s: template ", line
);
970 fprintf (stdout
, " address: base %s index %s scale %x\n",
971 x
->base_reg
? x
->base_reg
->reg_name
: "none",
972 x
->index_reg
? x
->index_reg
->reg_name
: "none",
973 x
->log2_scale_factor
);
974 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
975 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
976 fprintf (stdout
, " sib: base %x index %x scale %x\n",
977 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
978 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
979 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
980 for (i
= 0; i
< x
->operands
; i
++)
982 fprintf (stdout
, " #%d: ", i
+ 1);
984 fprintf (stdout
, "\n");
986 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
987 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
988 if (x
->types
[i
] & Imm
)
990 if (x
->types
[i
] & Disp
)
1000 fprintf (stdout
, " %d operands ", t
->operands
);
1001 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1002 if (t
->extension_opcode
!= None
)
1003 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1004 if (t
->opcode_modifier
& D
)
1005 fprintf (stdout
, "D");
1006 if (t
->opcode_modifier
& W
)
1007 fprintf (stdout
, "W");
1008 fprintf (stdout
, "\n");
1009 for (i
= 0; i
< t
->operands
; i
++)
1011 fprintf (stdout
, " #%d type ", i
+ 1);
1012 pt (t
->operand_types
[i
]);
1013 fprintf (stdout
, "\n");
1021 fprintf (stdout
, " operation %d\n", e
->X_op
);
1022 fprintf (stdout
, " add_number %ld (%lx)\n",
1023 (long) e
->X_add_number
, (long) e
->X_add_number
);
1024 if (e
->X_add_symbol
)
1026 fprintf (stdout
, " add_symbol ");
1027 ps (e
->X_add_symbol
);
1028 fprintf (stdout
, "\n");
1032 fprintf (stdout
, " op_symbol ");
1033 ps (e
->X_op_symbol
);
1034 fprintf (stdout
, "\n");
1042 fprintf (stdout
, "%s type %s%s",
1044 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1045 segment_name (S_GET_SEGMENT (s
)));
1067 { BaseIndex
, "BaseIndex" },
1071 { Disp32S
, "d32s" },
1073 { InOutPortReg
, "InOutPortReg" },
1074 { ShiftCount
, "ShiftCount" },
1075 { Control
, "control reg" },
1076 { Test
, "test reg" },
1077 { Debug
, "debug reg" },
1078 { FloatReg
, "FReg" },
1079 { FloatAcc
, "FAcc" },
1083 { JumpAbsolute
, "Jump Absolute" },
1094 register struct type_name
*ty
;
1096 for (ty
= type_names
; ty
->mask
; ty
++)
1098 fprintf (stdout
, "%s, ", ty
->tname
);
1102 #endif /* DEBUG386 */
1105 tc_i386_force_relocation (fixp
)
1108 #ifdef BFD_ASSEMBLER
1109 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1110 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1115 return fixp
->fx_r_type
== 7;
1119 #ifdef BFD_ASSEMBLER
1121 static bfd_reloc_code_real_type
1122 reloc (size
, pcrel
, sign
, other
)
1126 bfd_reloc_code_real_type other
;
1128 if (other
!= NO_RELOC
)
1134 as_bad (_("There are no unsigned pc-relative relocations"));
1137 case 1: return BFD_RELOC_8_PCREL
;
1138 case 2: return BFD_RELOC_16_PCREL
;
1139 case 4: return BFD_RELOC_32_PCREL
;
1141 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1148 case 4: return BFD_RELOC_X86_64_32S
;
1153 case 1: return BFD_RELOC_8
;
1154 case 2: return BFD_RELOC_16
;
1155 case 4: return BFD_RELOC_32
;
1156 case 8: return BFD_RELOC_64
;
1158 as_bad (_("can not do %s %d byte relocation"),
1159 sign
? "signed" : "unsigned", size
);
1163 return BFD_RELOC_NONE
;
1166 /* Here we decide which fixups can be adjusted to make them relative to
1167 the beginning of the section instead of the symbol. Basically we need
1168 to make sure that the dynamic relocations are done correctly, so in
1169 some cases we force the original symbol to be used. */
1172 tc_i386_fix_adjustable (fixP
)
1175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1176 /* Prevent all adjustments to global symbols, or else dynamic
1177 linking will not work correctly. */
1178 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1179 || S_IS_WEAK (fixP
->fx_addsy
))
1182 /* adjust_reloc_syms doesn't know about the GOT. */
1183 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1184 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1185 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1186 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1187 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1188 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1189 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1190 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1195 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1196 #define BFD_RELOC_16 0
1197 #define BFD_RELOC_32 0
1198 #define BFD_RELOC_16_PCREL 0
1199 #define BFD_RELOC_32_PCREL 0
1200 #define BFD_RELOC_386_PLT32 0
1201 #define BFD_RELOC_386_GOT32 0
1202 #define BFD_RELOC_386_GOTOFF 0
1203 #define BFD_RELOC_X86_64_PLT32 0
1204 #define BFD_RELOC_X86_64_GOT32 0
1205 #define BFD_RELOC_X86_64_GOTPCREL 0
1208 static int intel_float_operand
PARAMS ((char *mnemonic
));
1211 intel_float_operand (mnemonic
)
1214 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1217 if (mnemonic
[0] == 'f')
1223 /* This is the guts of the machine-dependent assembler. LINE points to a
1224 machine dependent instruction. This function is supposed to emit
1225 the frags/bytes it assembles to. */
1231 /* Points to template once we've found it. */
1236 char mnemonic
[MAX_MNEM_SIZE
];
1238 /* Initialize globals. */
1239 memset (&i
, '\0', sizeof (i
));
1240 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1241 i
.reloc
[j
] = NO_RELOC
;
1242 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1243 memset (im_expressions
, '\0', sizeof (im_expressions
));
1244 save_stack_p
= save_stack
;
1246 /* First parse an instruction mnemonic & call i386_operand for the operands.
1247 We assume that the scrubber has arranged it so that line[0] is the valid
1248 start of a (possibly prefixed) mnemonic. */
1251 char *token_start
= l
;
1254 /* Non-zero if we found a prefix only acceptable with string insns. */
1255 const char *expecting_string_instruction
= NULL
;
1260 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1263 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1265 as_bad (_("no such instruction: `%s'"), token_start
);
1270 if (!is_space_char (*l
)
1271 && *l
!= END_OF_INSN
1272 && *l
!= PREFIX_SEPARATOR
1275 as_bad (_("invalid character %s in mnemonic"),
1276 output_invalid (*l
));
1279 if (token_start
== l
)
1281 if (*l
== PREFIX_SEPARATOR
)
1282 as_bad (_("expecting prefix; got nothing"));
1284 as_bad (_("expecting mnemonic; got nothing"));
1288 /* Look up instruction (or prefix) via hash table. */
1289 current_templates
= hash_find (op_hash
, mnemonic
);
1291 if (*l
!= END_OF_INSN
1292 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1293 && current_templates
1294 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1296 /* If we are in 16-bit mode, do not allow addr16 or data16.
1297 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1298 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1299 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1300 ^ (flag_code
== CODE_16BIT
)))
1302 as_bad (_("redundant %s prefix"),
1303 current_templates
->start
->name
);
1306 /* Add prefix, checking for repeated prefixes. */
1307 switch (add_prefix (current_templates
->start
->base_opcode
))
1312 expecting_string_instruction
= current_templates
->start
->name
;
1315 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1322 if (!current_templates
)
1324 /* See if we can get a match by trimming off a suffix. */
1327 case WORD_MNEM_SUFFIX
:
1328 case BYTE_MNEM_SUFFIX
:
1329 case QWORD_MNEM_SUFFIX
:
1330 i
.suffix
= mnem_p
[-1];
1332 current_templates
= hash_find (op_hash
, mnemonic
);
1334 case SHORT_MNEM_SUFFIX
:
1335 case LONG_MNEM_SUFFIX
:
1338 i
.suffix
= mnem_p
[-1];
1340 current_templates
= hash_find (op_hash
, mnemonic
);
1348 if (intel_float_operand (mnemonic
))
1349 i
.suffix
= SHORT_MNEM_SUFFIX
;
1351 i
.suffix
= LONG_MNEM_SUFFIX
;
1353 current_templates
= hash_find (op_hash
, mnemonic
);
1357 if (!current_templates
)
1359 as_bad (_("no such instruction: `%s'"), token_start
);
1364 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1366 /* Check for a branch hint. We allow ",pt" and ",pn" for
1367 predict taken and predict not taken respectively.
1368 I'm not sure that branch hints actually do anything on loop
1369 and jcxz insns (JumpByte) for current Pentium4 chips. They
1370 may work in the future and it doesn't hurt to accept them
1372 if (l
[0] == ',' && l
[1] == 'p')
1376 if (! add_prefix (DS_PREFIX_OPCODE
))
1380 else if (l
[2] == 'n')
1382 if (! add_prefix (CS_PREFIX_OPCODE
))
1388 /* Any other comma loses. */
1391 as_bad (_("invalid character %s in mnemonic"),
1392 output_invalid (*l
));
1396 /* Check if instruction is supported on specified architecture. */
1397 if (cpu_arch_flags
!= 0)
1399 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1400 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1402 as_warn (_("`%s' is not supported on `%s'"),
1403 current_templates
->start
->name
, cpu_arch_name
);
1405 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1407 as_warn (_("use .code16 to ensure correct addressing mode"));
1411 /* Check for rep/repne without a string instruction. */
1412 if (expecting_string_instruction
1413 && !(current_templates
->start
->opcode_modifier
& IsString
))
1415 as_bad (_("expecting string instruction after `%s'"),
1416 expecting_string_instruction
);
1420 /* There may be operands to parse. */
1421 if (*l
!= END_OF_INSN
)
1423 /* 1 if operand is pending after ','. */
1424 unsigned int expecting_operand
= 0;
1426 /* Non-zero if operand parens not balanced. */
1427 unsigned int paren_not_balanced
;
1431 /* Skip optional white space before operand. */
1432 if (is_space_char (*l
))
1434 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1436 as_bad (_("invalid character %s before operand %d"),
1437 output_invalid (*l
),
1441 token_start
= l
; /* after white space */
1442 paren_not_balanced
= 0;
1443 while (paren_not_balanced
|| *l
!= ',')
1445 if (*l
== END_OF_INSN
)
1447 if (paren_not_balanced
)
1450 as_bad (_("unbalanced parenthesis in operand %d."),
1453 as_bad (_("unbalanced brackets in operand %d."),
1458 break; /* we are done */
1460 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1462 as_bad (_("invalid character %s in operand %d"),
1463 output_invalid (*l
),
1470 ++paren_not_balanced
;
1472 --paren_not_balanced
;
1477 ++paren_not_balanced
;
1479 --paren_not_balanced
;
1483 if (l
!= token_start
)
1484 { /* Yes, we've read in another operand. */
1485 unsigned int operand_ok
;
1486 this_operand
= i
.operands
++;
1487 if (i
.operands
> MAX_OPERANDS
)
1489 as_bad (_("spurious operands; (%d operands/instruction max)"),
1493 /* Now parse operand adding info to 'i' as we go along. */
1494 END_STRING_AND_SAVE (l
);
1498 i386_intel_operand (token_start
,
1499 intel_float_operand (mnemonic
));
1501 operand_ok
= i386_operand (token_start
);
1503 RESTORE_END_STRING (l
);
1509 if (expecting_operand
)
1511 expecting_operand_after_comma
:
1512 as_bad (_("expecting operand after ','; got nothing"));
1517 as_bad (_("expecting operand before ','; got nothing"));
1522 /* Now *l must be either ',' or END_OF_INSN. */
1525 if (*++l
== END_OF_INSN
)
1527 /* Just skip it, if it's \n complain. */
1528 goto expecting_operand_after_comma
;
1530 expecting_operand
= 1;
1533 while (*l
!= END_OF_INSN
);
1537 /* Now we've parsed the mnemonic into a set of templates, and have the
1540 Next, we find a template that matches the given insn,
1541 making sure the overlap of the given operands types is consistent
1542 with the template operand types. */
1544 #define MATCH(overlap, given, template) \
1545 ((overlap & ~JumpAbsolute) \
1546 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1548 /* If given types r0 and r1 are registers they must be of the same type
1549 unless the expected operand type register overlap is null.
1550 Note that Acc in a template matches every size of reg. */
1551 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1552 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1553 ((g0) & Reg) == ((g1) & Reg) || \
1554 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1557 register unsigned int overlap0
, overlap1
;
1558 unsigned int overlap2
;
1559 unsigned int found_reverse_match
;
1562 /* All intel opcodes have reversed operands except for "bound" and
1563 "enter". We also don't reverse intersegment "jmp" and "call"
1564 instructions with 2 immediate operands so that the immediate segment
1565 precedes the offset, as it does when in AT&T mode. "enter" and the
1566 intersegment "jmp" and "call" instructions are the only ones that
1567 have two immediate operands. */
1568 if (intel_syntax
&& i
.operands
> 1
1569 && (strcmp (mnemonic
, "bound") != 0)
1570 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1572 union i386_op temp_op
;
1573 unsigned int temp_type
;
1574 RELOC_ENUM temp_reloc
;
1578 if (i
.operands
== 2)
1583 else if (i
.operands
== 3)
1588 temp_type
= i
.types
[xchg2
];
1589 i
.types
[xchg2
] = i
.types
[xchg1
];
1590 i
.types
[xchg1
] = temp_type
;
1591 temp_op
= i
.op
[xchg2
];
1592 i
.op
[xchg2
] = i
.op
[xchg1
];
1593 i
.op
[xchg1
] = temp_op
;
1594 temp_reloc
= i
.reloc
[xchg2
];
1595 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1596 i
.reloc
[xchg1
] = temp_reloc
;
1598 if (i
.mem_operands
== 2)
1600 const seg_entry
*temp_seg
;
1601 temp_seg
= i
.seg
[0];
1602 i
.seg
[0] = i
.seg
[1];
1603 i
.seg
[1] = temp_seg
;
1609 /* Try to ensure constant immediates are represented in the smallest
1611 char guess_suffix
= 0;
1615 guess_suffix
= i
.suffix
;
1616 else if (i
.reg_operands
)
1618 /* Figure out a suffix from the last register operand specified.
1619 We can't do this properly yet, ie. excluding InOutPortReg,
1620 but the following works for instructions with immediates.
1621 In any case, we can't set i.suffix yet. */
1622 for (op
= i
.operands
; --op
>= 0;)
1623 if (i
.types
[op
] & Reg
)
1625 if (i
.types
[op
] & Reg8
)
1626 guess_suffix
= BYTE_MNEM_SUFFIX
;
1627 else if (i
.types
[op
] & Reg16
)
1628 guess_suffix
= WORD_MNEM_SUFFIX
;
1629 else if (i
.types
[op
] & Reg32
)
1630 guess_suffix
= LONG_MNEM_SUFFIX
;
1631 else if (i
.types
[op
] & Reg64
)
1632 guess_suffix
= QWORD_MNEM_SUFFIX
;
1636 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1637 guess_suffix
= WORD_MNEM_SUFFIX
;
1639 for (op
= i
.operands
; --op
>= 0;)
1640 if (i
.types
[op
] & Imm
)
1642 switch (i
.op
[op
].imms
->X_op
)
1645 /* If a suffix is given, this operand may be shortened. */
1646 switch (guess_suffix
)
1648 case LONG_MNEM_SUFFIX
:
1649 i
.types
[op
] |= Imm32
| Imm64
;
1651 case WORD_MNEM_SUFFIX
:
1652 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1654 case BYTE_MNEM_SUFFIX
:
1655 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1659 /* If this operand is at most 16 bits, convert it
1660 to a signed 16 bit number before trying to see
1661 whether it will fit in an even smaller size.
1662 This allows a 16-bit operand such as $0xffe0 to
1663 be recognised as within Imm8S range. */
1664 if ((i
.types
[op
] & Imm16
)
1665 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1667 i
.op
[op
].imms
->X_add_number
=
1668 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1670 if ((i
.types
[op
] & Imm32
)
1671 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1673 i
.op
[op
].imms
->X_add_number
=
1674 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1676 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1677 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1678 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1679 i
.types
[op
] &= ~Imm32
;
1684 /* Symbols and expressions. */
1686 /* Convert symbolic operand to proper sizes for matching. */
1687 switch (guess_suffix
)
1689 case QWORD_MNEM_SUFFIX
:
1690 i
.types
[op
] = Imm64
| Imm32S
;
1692 case LONG_MNEM_SUFFIX
:
1693 i
.types
[op
] = Imm32
| Imm64
;
1695 case WORD_MNEM_SUFFIX
:
1696 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1699 case BYTE_MNEM_SUFFIX
:
1700 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1709 if (i
.disp_operands
)
1711 /* Try to use the smallest displacement type too. */
1714 for (op
= i
.operands
; --op
>= 0;)
1715 if ((i
.types
[op
] & Disp
)
1716 && i
.op
[op
].disps
->X_op
== O_constant
)
1718 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1720 if (i
.types
[op
] & Disp16
)
1722 /* We know this operand is at most 16 bits, so
1723 convert to a signed 16 bit number before trying
1724 to see whether it will fit in an even smaller
1727 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1729 else if (i
.types
[op
] & Disp32
)
1731 /* We know this operand is at most 32 bits, so convert to a
1732 signed 32 bit number before trying to see whether it will
1733 fit in an even smaller size. */
1734 disp
&= (((offsetT
) 2 << 31) - 1);
1735 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1737 if (flag_code
== CODE_64BIT
)
1739 if (fits_in_signed_long (disp
))
1740 i
.types
[op
] |= Disp32S
;
1741 if (fits_in_unsigned_long (disp
))
1742 i
.types
[op
] |= Disp32
;
1744 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1745 && fits_in_signed_byte (disp
))
1746 i
.types
[op
] |= Disp8
;
1753 found_reverse_match
= 0;
1754 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1756 : (i
.suffix
== WORD_MNEM_SUFFIX
1758 : (i
.suffix
== SHORT_MNEM_SUFFIX
1760 : (i
.suffix
== LONG_MNEM_SUFFIX
1762 : (i
.suffix
== QWORD_MNEM_SUFFIX
1764 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1766 for (t
= current_templates
->start
;
1767 t
< current_templates
->end
;
1770 /* Must have right number of operands. */
1771 if (i
.operands
!= t
->operands
)
1774 /* Check the suffix, except for some instructions in intel mode. */
1775 if ((t
->opcode_modifier
& suffix_check
)
1777 && (t
->opcode_modifier
& IgnoreSize
))
1779 && t
->base_opcode
== 0xd9
1780 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1781 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1784 /* Do not verify operands when there are none. */
1785 else if (!t
->operands
)
1787 if (t
->cpu_flags
& ~cpu_arch_flags
)
1789 /* We've found a match; break out of loop. */
1793 overlap0
= i
.types
[0] & t
->operand_types
[0];
1794 switch (t
->operands
)
1797 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1802 overlap1
= i
.types
[1] & t
->operand_types
[1];
1803 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1804 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1805 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1806 t
->operand_types
[0],
1807 overlap1
, i
.types
[1],
1808 t
->operand_types
[1]))
1810 /* Check if other direction is valid ... */
1811 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1814 /* Try reversing direction of operands. */
1815 overlap0
= i
.types
[0] & t
->operand_types
[1];
1816 overlap1
= i
.types
[1] & t
->operand_types
[0];
1817 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1818 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1819 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1820 t
->operand_types
[1],
1821 overlap1
, i
.types
[1],
1822 t
->operand_types
[0]))
1824 /* Does not match either direction. */
1827 /* found_reverse_match holds which of D or FloatDR
1829 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1831 /* Found a forward 2 operand match here. */
1832 else if (t
->operands
== 3)
1834 /* Here we make use of the fact that there are no
1835 reverse match 3 operand instructions, and all 3
1836 operand instructions only need to be checked for
1837 register consistency between operands 2 and 3. */
1838 overlap2
= i
.types
[2] & t
->operand_types
[2];
1839 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1840 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1841 t
->operand_types
[1],
1842 overlap2
, i
.types
[2],
1843 t
->operand_types
[2]))
1847 /* Found either forward/reverse 2 or 3 operand match here:
1848 slip through to break. */
1850 if (t
->cpu_flags
& ~cpu_arch_flags
)
1852 found_reverse_match
= 0;
1855 /* We've found a match; break out of loop. */
1858 if (t
== current_templates
->end
)
1860 /* We found no match. */
1861 as_bad (_("suffix or operands invalid for `%s'"),
1862 current_templates
->start
->name
);
1866 if (!quiet_warnings
)
1869 && ((i
.types
[0] & JumpAbsolute
)
1870 != (t
->operand_types
[0] & JumpAbsolute
)))
1872 as_warn (_("indirect %s without `*'"), t
->name
);
1875 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1876 == (IsPrefix
|IgnoreSize
))
1878 /* Warn them that a data or address size prefix doesn't
1879 affect assembly of the next line of code. */
1880 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1884 /* Copy the template we found. */
1886 if (found_reverse_match
)
1888 /* If we found a reverse match we must alter the opcode
1889 direction bit. found_reverse_match holds bits to change
1890 (different for int & float insns). */
1892 i
.tm
.base_opcode
^= found_reverse_match
;
1894 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1895 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1898 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1901 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1902 i
.tm
.base_opcode
^= FloatR
;
1904 if (i
.tm
.opcode_modifier
& FWait
)
1905 if (! add_prefix (FWAIT_OPCODE
))
1908 /* Check string instruction segment overrides. */
1909 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1911 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1912 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1914 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1916 as_bad (_("`%s' operand %d must use `%%es' segment"),
1921 /* There's only ever one segment override allowed per instruction.
1922 This instruction possibly has a legal segment override on the
1923 second operand, so copy the segment to where non-string
1924 instructions store it, allowing common code. */
1925 i
.seg
[0] = i
.seg
[1];
1927 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1929 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1931 as_bad (_("`%s' operand %d must use `%%es' segment"),
1939 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1942 for (op
= i
.operands
; --op
>= 0;)
1943 if ((i
.types
[op
] & Reg
)
1944 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1946 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1947 i
.op
[op
].regs
->reg_name
);
1952 /* If matched instruction specifies an explicit instruction mnemonic
1954 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1956 if (i
.tm
.opcode_modifier
& Size16
)
1957 i
.suffix
= WORD_MNEM_SUFFIX
;
1958 else if (i
.tm
.opcode_modifier
& Size64
)
1959 i
.suffix
= QWORD_MNEM_SUFFIX
;
1961 i
.suffix
= LONG_MNEM_SUFFIX
;
1963 else if (i
.reg_operands
)
1965 /* If there's no instruction mnemonic suffix we try to invent one
1966 based on register operands. */
1969 /* We take i.suffix from the last register operand specified,
1970 Destination register type is more significant than source
1973 for (op
= i
.operands
; --op
>= 0;)
1974 if ((i
.types
[op
] & Reg
)
1975 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1977 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1978 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1979 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1984 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1987 for (op
= i
.operands
; --op
>= 0;)
1989 /* If this is an eight bit register, it's OK. If it's
1990 the 16 or 32 bit version of an eight bit register,
1991 we will just use the low portion, and that's OK too. */
1992 if (i
.types
[op
] & Reg8
)
1995 /* movzx and movsx should not generate this warning. */
1997 && (i
.tm
.base_opcode
== 0xfb7
1998 || i
.tm
.base_opcode
== 0xfb6
1999 || i
.tm
.base_opcode
== 0x63
2000 || i
.tm
.base_opcode
== 0xfbe
2001 || i
.tm
.base_opcode
== 0xfbf))
2004 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2006 /* Check that the template allows eight bit regs
2007 This kills insns such as `orb $1,%edx', which
2008 maybe should be allowed. */
2009 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
2013 /* Prohibit these changes in the 64bit mode, since
2014 the lowering is more complicated. */
2015 if (flag_code
== CODE_64BIT
2016 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2017 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2018 i
.op
[op
].regs
->reg_name
,
2020 #if REGISTER_WARNINGS
2022 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2023 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2025 + (i
.types
[op
] & Reg16
2026 ? REGNAM_AL
- REGNAM_AX
2027 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2028 i
.op
[op
].regs
->reg_name
,
2033 /* Any other register is bad. */
2034 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2036 | Control
| Debug
| Test
2037 | FloatReg
| FloatAcc
))
2039 as_bad (_("`%%%s' not allowed with `%s%c'"),
2040 i
.op
[op
].regs
->reg_name
,
2047 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2051 for (op
= i
.operands
; --op
>= 0;)
2052 /* Reject eight bit registers, except where the template
2053 requires them. (eg. movzb) */
2054 if ((i
.types
[op
] & Reg8
) != 0
2055 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2057 as_bad (_("`%%%s' not allowed with `%s%c'"),
2058 i
.op
[op
].regs
->reg_name
,
2063 /* Warn if the e prefix on a general reg is missing. */
2064 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2065 && (i
.types
[op
] & Reg16
) != 0
2066 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2068 /* Prohibit these changes in the 64bit mode, since
2069 the lowering is more complicated. */
2070 if (flag_code
== CODE_64BIT
)
2071 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2072 i
.op
[op
].regs
->reg_name
,
2074 #if REGISTER_WARNINGS
2076 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2077 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2078 i
.op
[op
].regs
->reg_name
,
2082 /* Warn if the r prefix on a general reg is missing. */
2083 else if ((i
.types
[op
] & Reg64
) != 0
2084 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2086 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2087 i
.op
[op
].regs
->reg_name
,
2091 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2095 for (op
= i
.operands
; --op
>= 0; )
2096 /* Reject eight bit registers, except where the template
2097 requires them. (eg. movzb) */
2098 if ((i
.types
[op
] & Reg8
) != 0
2099 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2101 as_bad (_("`%%%s' not allowed with `%s%c'"),
2102 i
.op
[op
].regs
->reg_name
,
2107 /* Warn if the e prefix on a general reg is missing. */
2108 else if (((i
.types
[op
] & Reg16
) != 0
2109 || (i
.types
[op
] & Reg32
) != 0)
2110 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2112 /* Prohibit these changes in the 64bit mode, since
2113 the lowering is more complicated. */
2114 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2115 i
.op
[op
].regs
->reg_name
,
2119 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2122 for (op
= i
.operands
; --op
>= 0;)
2123 /* Reject eight bit registers, except where the template
2124 requires them. (eg. movzb) */
2125 if ((i
.types
[op
] & Reg8
) != 0
2126 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2128 as_bad (_("`%%%s' not allowed with `%s%c'"),
2129 i
.op
[op
].regs
->reg_name
,
2134 /* Warn if the e prefix on a general reg is present. */
2135 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2136 && (i
.types
[op
] & Reg32
) != 0
2137 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2139 /* Prohibit these changes in the 64bit mode, since
2140 the lowering is more complicated. */
2141 if (flag_code
== CODE_64BIT
)
2142 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2143 i
.op
[op
].regs
->reg_name
,
2146 #if REGISTER_WARNINGS
2147 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2148 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2149 i
.op
[op
].regs
->reg_name
,
2154 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2155 /* Do nothing if the instruction is going to ignore the prefix. */
2160 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2162 i
.suffix
= stackop_size
;
2164 /* Make still unresolved immediate matches conform to size of immediate
2165 given in i.suffix. Note: overlap2 cannot be an immediate! */
2166 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2167 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2168 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2169 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2173 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2174 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2175 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2177 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2178 || overlap0
== (Imm16
| Imm32
)
2179 || overlap0
== (Imm16
| Imm32S
))
2182 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2184 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2185 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2186 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2188 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2192 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2193 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2194 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2195 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2199 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2200 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2201 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2203 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2204 || overlap1
== (Imm16
| Imm32
)
2205 || overlap1
== (Imm16
| Imm32S
))
2208 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2210 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2211 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2212 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2214 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2218 assert ((overlap2
& Imm
) == 0);
2220 i
.types
[0] = overlap0
;
2221 if (overlap0
& ImplicitRegister
)
2223 if (overlap0
& Imm1
)
2224 i
.imm_operands
= 0; /* kludge for shift insns. */
2226 i
.types
[1] = overlap1
;
2227 if (overlap1
& ImplicitRegister
)
2230 i
.types
[2] = overlap2
;
2231 if (overlap2
& ImplicitRegister
)
2234 /* Finalize opcode. First, we change the opcode based on the operand
2235 size given by i.suffix: We need not change things for byte insns. */
2237 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2239 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2243 /* For movzx and movsx, need to check the register type. */
2245 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2246 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2248 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2250 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2251 if (!add_prefix (prefix
))
2255 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2257 /* It's not a byte, select word/dword operation. */
2258 if (i
.tm
.opcode_modifier
& W
)
2260 if (i
.tm
.opcode_modifier
& ShortForm
)
2261 i
.tm
.base_opcode
|= 8;
2263 i
.tm
.base_opcode
|= 1;
2265 /* Now select between word & dword operations via the operand
2266 size prefix, except for instructions that will ignore this
2268 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2269 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2270 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2272 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2273 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2274 prefix
= ADDR_PREFIX_OPCODE
;
2276 if (! add_prefix (prefix
))
2280 /* Set mode64 for an operand. */
2281 if (i
.suffix
== QWORD_MNEM_SUFFIX
2282 && !(i
.tm
.opcode_modifier
& NoRex64
))
2285 if (flag_code
< CODE_64BIT
)
2287 as_bad (_("64bit operations available only in 64bit modes."));
2292 /* Size floating point instruction. */
2293 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2295 if (i
.tm
.opcode_modifier
& FloatMF
)
2296 i
.tm
.base_opcode
^= 4;
2300 if (i
.tm
.opcode_modifier
& ImmExt
)
2302 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2303 opcode suffix which is coded in the same place as an 8-bit
2304 immediate field would be. Here we fake an 8-bit immediate
2305 operand from the opcode suffix stored in tm.extension_opcode. */
2309 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2311 exp
= &im_expressions
[i
.imm_operands
++];
2312 i
.op
[i
.operands
].imms
= exp
;
2313 i
.types
[i
.operands
++] = Imm8
;
2314 exp
->X_op
= O_constant
;
2315 exp
->X_add_number
= i
.tm
.extension_opcode
;
2316 i
.tm
.extension_opcode
= None
;
2319 /* For insns with operands there are more diddles to do to the opcode. */
2322 /* Default segment register this instruction will use
2323 for memory accesses. 0 means unknown.
2324 This is only for optimizing out unnecessary segment overrides. */
2325 const seg_entry
*default_seg
= 0;
2327 /* The imul $imm, %reg instruction is converted into
2328 imul $imm, %reg, %reg, and the clr %reg instruction
2329 is converted into xor %reg, %reg. */
2330 if (i
.tm
.opcode_modifier
& regKludge
)
2332 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2333 /* Pretend we saw the extra register operand. */
2334 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2335 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2336 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2340 if (i
.tm
.opcode_modifier
& ShortForm
)
2342 /* The register or float register operand is in operand 0 or 1. */
2343 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2344 /* Register goes in low 3 bits of opcode. */
2345 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2346 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2348 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2350 /* Warn about some common errors, but press on regardless.
2351 The first case can be generated by gcc (<= 2.8.1). */
2352 if (i
.operands
== 2)
2354 /* Reversed arguments on faddp, fsubp, etc. */
2355 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2356 i
.op
[1].regs
->reg_name
,
2357 i
.op
[0].regs
->reg_name
);
2361 /* Extraneous `l' suffix on fp insn. */
2362 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2363 i
.op
[0].regs
->reg_name
);
2367 else if (i
.tm
.opcode_modifier
& Modrm
)
2369 /* The opcode is completed (modulo i.tm.extension_opcode which
2370 must be put into the modrm byte).
2371 Now, we make the modrm & index base bytes based on all the
2372 info we've collected. */
2374 /* i.reg_operands MUST be the number of real register operands;
2375 implicit registers do not count. */
2376 if (i
.reg_operands
== 2)
2378 unsigned int source
, dest
;
2379 source
= ((i
.types
[0]
2380 & (Reg
| RegMMX
| RegXMM
2382 | Control
| Debug
| Test
))
2387 /* One of the register operands will be encoded in the
2388 i.tm.reg field, the other in the combined i.tm.mode
2389 and i.tm.regmem fields. If no form of this
2390 instruction supports a memory destination operand,
2391 then we assume the source operand may sometimes be
2392 a memory operand and so we need to store the
2393 destination in the i.rm.reg field. */
2394 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2396 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2397 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2398 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2400 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2405 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2406 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2407 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2409 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2414 { /* If it's not 2 reg operands... */
2417 unsigned int fake_zero_displacement
= 0;
2418 unsigned int op
= ((i
.types
[0] & AnyMem
)
2420 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2427 if (! i
.disp_operands
)
2428 fake_zero_displacement
= 1;
2431 /* Operand is just <disp> */
2432 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2434 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2435 i
.types
[op
] &= ~Disp
;
2436 i
.types
[op
] |= Disp16
;
2438 else if (flag_code
!= CODE_64BIT
)
2440 i
.rm
.regmem
= NO_BASE_REGISTER
;
2441 i
.types
[op
] &= ~Disp
;
2442 i
.types
[op
] |= Disp32
;
2446 /* 64bit mode overwrites the 32bit
2447 absolute addressing by RIP relative
2448 addressing and absolute addressing
2449 is encoded by one of the redundant
2452 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2453 i
.sib
.base
= NO_BASE_REGISTER
;
2454 i
.sib
.index
= NO_INDEX_REGISTER
;
2455 i
.types
[op
] &= ~Disp
;
2456 i
.types
[op
] |= Disp32S
;
2459 else /* ! i.base_reg && i.index_reg */
2461 i
.sib
.index
= i
.index_reg
->reg_num
;
2462 i
.sib
.base
= NO_BASE_REGISTER
;
2463 i
.sib
.scale
= i
.log2_scale_factor
;
2464 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2465 i
.types
[op
] &= ~Disp
;
2466 if (flag_code
!= CODE_64BIT
)
2467 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2469 i
.types
[op
] |= Disp32S
;
2470 if (i
.index_reg
->reg_flags
& RegRex
)
2474 /* RIP addressing for 64bit mode. */
2475 else if (i
.base_reg
->reg_type
== BaseIndex
)
2477 i
.rm
.regmem
= NO_BASE_REGISTER
;
2478 i
.types
[op
] &= ~Disp
;
2479 i
.types
[op
] |= Disp32S
;
2480 i
.flags
[op
] = Operand_PCrel
;
2482 else if (i
.base_reg
->reg_type
& Reg16
)
2484 switch (i
.base_reg
->reg_num
)
2489 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2490 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2497 if ((i
.types
[op
] & Disp
) == 0)
2499 /* fake (%bp) into 0(%bp) */
2500 i
.types
[op
] |= Disp8
;
2501 fake_zero_displacement
= 1;
2504 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2505 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2507 default: /* (%si) -> 4 or (%di) -> 5 */
2508 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2510 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2512 else /* i.base_reg and 32/64 bit mode */
2514 if (flag_code
== CODE_64BIT
2515 && (i
.types
[op
] & Disp
))
2517 if (i
.types
[op
] & Disp8
)
2518 i
.types
[op
] = Disp8
| Disp32S
;
2520 i
.types
[op
] = Disp32S
;
2522 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2523 if (i
.base_reg
->reg_flags
& RegRex
)
2525 i
.sib
.base
= i
.base_reg
->reg_num
;
2526 /* x86-64 ignores REX prefix bit here to avoid
2527 decoder complications. */
2528 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2531 if (i
.disp_operands
== 0)
2533 fake_zero_displacement
= 1;
2534 i
.types
[op
] |= Disp8
;
2537 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2541 i
.sib
.scale
= i
.log2_scale_factor
;
2544 /* <disp>(%esp) becomes two byte modrm
2545 with no index register. We've already
2546 stored the code for esp in i.rm.regmem
2547 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2548 base register besides %esp will not use
2549 the extra modrm byte. */
2550 i
.sib
.index
= NO_INDEX_REGISTER
;
2551 #if ! SCALE1_WHEN_NO_INDEX
2552 /* Another case where we force the second
2554 if (i
.log2_scale_factor
)
2555 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2560 i
.sib
.index
= i
.index_reg
->reg_num
;
2561 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2562 if (i
.index_reg
->reg_flags
& RegRex
)
2565 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2568 if (fake_zero_displacement
)
2570 /* Fakes a zero displacement assuming that i.types[op]
2571 holds the correct displacement size. */
2574 assert (i
.op
[op
].disps
== 0);
2575 exp
= &disp_expressions
[i
.disp_operands
++];
2576 i
.op
[op
].disps
= exp
;
2577 exp
->X_op
= O_constant
;
2578 exp
->X_add_number
= 0;
2579 exp
->X_add_symbol
= (symbolS
*) 0;
2580 exp
->X_op_symbol
= (symbolS
*) 0;
2584 /* Fill in i.rm.reg or i.rm.regmem field with register
2585 operand (if any) based on i.tm.extension_opcode.
2586 Again, we must be careful to make sure that
2587 segment/control/debug/test/MMX registers are coded
2588 into the i.rm.reg field. */
2593 & (Reg
| RegMMX
| RegXMM
2595 | Control
| Debug
| Test
))
2598 & (Reg
| RegMMX
| RegXMM
2600 | Control
| Debug
| Test
))
2603 /* If there is an extension opcode to put here, the
2604 register number must be put into the regmem field. */
2605 if (i
.tm
.extension_opcode
!= None
)
2607 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2608 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2613 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2614 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2618 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2619 we must set it to 3 to indicate this is a register
2620 operand in the regmem field. */
2621 if (!i
.mem_operands
)
2625 /* Fill in i.rm.reg field with extension opcode (if any). */
2626 if (i
.tm
.extension_opcode
!= None
)
2627 i
.rm
.reg
= i
.tm
.extension_opcode
;
2630 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2632 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2633 && i
.op
[0].regs
->reg_num
== 1)
2635 as_bad (_("you can't `pop %%cs'"));
2638 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2639 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2642 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2646 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2648 /* For the string instructions that allow a segment override
2649 on one of their operands, the default segment is ds. */
2653 /* If a segment was explicitly specified,
2654 and the specified segment is not the default,
2655 use an opcode prefix to select it.
2656 If we never figured out what the default segment is,
2657 then default_seg will be zero at this point,
2658 and the specified segment prefix will always be used. */
2659 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2661 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2665 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2667 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2668 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2672 /* Handle conversion of 'int $3' --> special int3 insn. */
2673 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2675 i
.tm
.base_opcode
= INT3_OPCODE
;
2679 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2680 && i
.op
[0].disps
->X_op
== O_constant
)
2682 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2683 the absolute address given by the constant. Since ix86 jumps and
2684 calls are pc relative, we need to generate a reloc. */
2685 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2686 i
.op
[0].disps
->X_op
= O_symbol
;
2689 if (i
.tm
.opcode_modifier
& Rex64
)
2692 /* For 8bit registers we would need an empty rex prefix.
2693 Also in the case instruction is already having prefix,
2694 we need to convert old registers to new ones. */
2696 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2697 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2698 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2699 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2703 for (x
= 0; x
< 2; x
++)
2705 /* Look for 8bit operand that does use old registers. */
2706 if (i
.types
[x
] & Reg8
2707 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2709 /* In case it is "hi" register, give up. */
2710 if (i
.op
[x
].regs
->reg_num
> 3)
2711 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2712 i
.op
[x
].regs
->reg_name
);
2714 /* Otherwise it is equivalent to the extended register.
2715 Since the encoding don't change this is merely cosmetical
2716 cleanup for debug output. */
2718 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2723 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2725 | (i
.rex
.mode64
? 8 : 0)
2726 | (i
.rex
.extX
? 4 : 0)
2727 | (i
.rex
.extY
? 2 : 0)
2728 | (i
.rex
.extZ
? 1 : 0));
2730 /* We are ready to output the insn. */
2734 /* Tie dwarf2 debug info to the address at the start of the insn.
2735 We can't do this after the insn has been output as the current
2736 frag may have been closed off. eg. by frag_var. */
2737 dwarf2_emit_insn (0);
2740 if (i
.tm
.opcode_modifier
& Jump
)
2746 if (flag_code
== CODE_16BIT
)
2750 if (i
.prefix
[DATA_PREFIX
])
2756 /* Pentium4 branch hints. */
2757 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2758 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2763 if (i
.prefix
[REX_PREFIX
])
2769 if (i
.prefixes
!= 0 && !intel_syntax
)
2770 as_warn (_("skipping prefixes on this instruction"));
2772 /* It's always a symbol; End frag & setup for relax.
2773 Make sure there is enough room in this frag for the largest
2774 instruction we may generate in md_convert_frag. This is 2
2775 bytes for the opcode and room for the prefix and largest
2777 frag_grow (prefix
+ 2 + 4);
2778 /* Prefix and 1 opcode byte go in fr_fix. */
2779 p
= frag_more (prefix
+ 1);
2780 if (i
.prefix
[DATA_PREFIX
])
2781 *p
++ = DATA_PREFIX_OPCODE
;
2782 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2783 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2784 *p
++ = i
.prefix
[SEG_PREFIX
];
2785 if (i
.prefix
[REX_PREFIX
])
2786 *p
++ = i
.prefix
[REX_PREFIX
];
2787 *p
= i
.tm
.base_opcode
;
2788 /* 1 possible extra opcode + displacement go in var part.
2789 Pass reloc in fr_var. */
2790 frag_var (rs_machine_dependent
,
2793 ((unsigned char) *p
== JUMP_PC_RELATIVE
2794 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2795 : ((cpu_arch_flags
& Cpu386
) != 0
2796 ? ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
2797 : ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
) | code16
)),
2798 i
.op
[0].disps
->X_add_symbol
,
2799 i
.op
[0].disps
->X_add_number
,
2802 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2806 if (i
.tm
.opcode_modifier
& JumpByte
)
2808 /* This is a loop or jecxz type instruction. */
2810 if (i
.prefix
[ADDR_PREFIX
])
2812 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2815 /* Pentium4 branch hints. */
2816 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2817 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2819 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
2828 if (flag_code
== CODE_16BIT
)
2831 if (i
.prefix
[DATA_PREFIX
])
2833 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2843 if (i
.prefix
[REX_PREFIX
])
2845 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2849 if (i
.prefixes
!= 0 && !intel_syntax
)
2850 as_warn (_("skipping prefixes on this instruction"));
2852 p
= frag_more (1 + size
);
2853 *p
++ = i
.tm
.base_opcode
;
2855 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2856 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
2858 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2865 if (flag_code
== CODE_16BIT
)
2869 if (i
.prefix
[DATA_PREFIX
])
2875 if (i
.prefix
[REX_PREFIX
])
2885 if (i
.prefixes
!= 0 && !intel_syntax
)
2886 as_warn (_("skipping prefixes on this instruction"));
2888 /* 1 opcode; 2 segment; offset */
2889 p
= frag_more (prefix
+ 1 + 2 + size
);
2891 if (i
.prefix
[DATA_PREFIX
])
2892 *p
++ = DATA_PREFIX_OPCODE
;
2894 if (i
.prefix
[REX_PREFIX
])
2895 *p
++ = i
.prefix
[REX_PREFIX
];
2897 *p
++ = i
.tm
.base_opcode
;
2898 if (i
.op
[1].imms
->X_op
== O_constant
)
2900 offsetT n
= i
.op
[1].imms
->X_add_number
;
2903 && !fits_in_unsigned_word (n
)
2904 && !fits_in_signed_word (n
))
2906 as_bad (_("16-bit jump out of range"));
2909 md_number_to_chars (p
, n
, size
);
2912 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2913 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
2914 if (i
.op
[0].imms
->X_op
!= O_constant
)
2915 as_bad (_("can't handle non absolute segment in `%s'"),
2917 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2921 /* Output normal instructions here. */
2924 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2925 byte for the SSE instructions to specify prefix they require. */
2926 if (i
.tm
.base_opcode
& 0xff0000)
2927 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2929 /* The prefix bytes. */
2931 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2937 md_number_to_chars (p
, (valueT
) *q
, 1);
2941 /* Now the opcode; be careful about word order here! */
2942 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2944 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2949 /* Put out high byte first: can't use md_number_to_chars! */
2950 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2951 *p
= i
.tm
.base_opcode
& 0xff;
2954 /* Now the modrm byte and sib byte (if present). */
2955 if (i
.tm
.opcode_modifier
& Modrm
)
2958 md_number_to_chars (p
,
2959 (valueT
) (i
.rm
.regmem
<< 0
2963 /* If i.rm.regmem == ESP (4)
2964 && i.rm.mode != (Register mode)
2966 ==> need second modrm byte. */
2967 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2969 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2972 md_number_to_chars (p
,
2973 (valueT
) (i
.sib
.base
<< 0
2975 | i
.sib
.scale
<< 6),
2980 if (i
.disp_operands
)
2982 register unsigned int n
;
2984 for (n
= 0; n
< i
.operands
; n
++)
2986 if (i
.types
[n
] & Disp
)
2988 if (i
.op
[n
].disps
->X_op
== O_constant
)
2994 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2997 if (i
.types
[n
] & Disp8
)
2999 if (i
.types
[n
] & Disp64
)
3002 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3004 p
= frag_more (size
);
3005 md_number_to_chars (p
, val
, size
);
3011 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3013 /* The PC relative address is computed relative
3014 to the instruction boundary, so in case immediate
3015 fields follows, we need to adjust the value. */
3016 if (pcrel
&& i
.imm_operands
)
3019 register unsigned int n1
;
3021 for (n1
= 0; n1
< i
.operands
; n1
++)
3022 if (i
.types
[n1
] & Imm
)
3024 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3027 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3029 if (i
.types
[n1
] & Imm64
)
3034 /* We should find the immediate. */
3035 if (n1
== i
.operands
)
3037 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3040 if (i
.types
[n
] & Disp32S
)
3043 if (i
.types
[n
] & (Disp16
| Disp64
))
3046 if (i
.types
[n
] & Disp64
)
3050 p
= frag_more (size
);
3051 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3052 i
.op
[n
].disps
, pcrel
,
3053 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3059 /* Output immediate. */
3062 register unsigned int n
;
3064 for (n
= 0; n
< i
.operands
; n
++)
3066 if (i
.types
[n
] & Imm
)
3068 if (i
.op
[n
].imms
->X_op
== O_constant
)
3074 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3077 if (i
.types
[n
] & (Imm8
| Imm8S
))
3079 else if (i
.types
[n
] & Imm64
)
3082 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3084 p
= frag_more (size
);
3085 md_number_to_chars (p
, val
, size
);
3089 /* Not absolute_section.
3090 Need a 32-bit fixup (don't support 8bit
3091 non-absolute imms). Try to support other
3093 RELOC_ENUM reloc_type
;
3097 if ((i
.types
[n
] & (Imm32S
))
3098 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3100 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3103 if (i
.types
[n
] & (Imm8
| Imm8S
))
3105 if (i
.types
[n
] & Imm64
)
3109 p
= frag_more (size
);
3110 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3111 #ifdef BFD_ASSEMBLER
3112 if (reloc_type
== BFD_RELOC_32
3114 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3115 && (i
.op
[n
].imms
->X_op
== O_symbol
3116 || (i
.op
[n
].imms
->X_op
== O_add
3117 && ((symbol_get_value_expression
3118 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3121 /* We don't support dynamic linking on x86-64 yet. */
3122 if (flag_code
== CODE_64BIT
)
3124 reloc_type
= BFD_RELOC_386_GOTPC
;
3125 i
.op
[n
].imms
->X_add_number
+= 3;
3128 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3129 i
.op
[n
].imms
, 0, reloc_type
);
3141 #endif /* DEBUG386 */
3146 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3148 /* Parse operands of the form
3149 <symbol>@GOTOFF+<nnn>
3150 and similar .plt or .got references.
3152 If we find one, set up the correct relocation in RELOC and copy the
3153 input string, minus the `@GOTOFF' into a malloc'd buffer for
3154 parsing by the calling routine. Return this buffer, and if ADJUST
3155 is non-null set it to the length of the string we removed from the
3156 input line. Otherwise return NULL. */
3158 lex_got (reloc
, adjust
)
3162 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3163 static const struct {
3165 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3167 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3168 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3169 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3170 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3175 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3176 if (is_end_of_line
[(unsigned char) *cp
])
3179 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3183 len
= strlen (gotrel
[j
].str
);
3184 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3186 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3189 char *tmpbuf
, *past_reloc
;
3191 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3195 if (GOT_symbol
== NULL
)
3196 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3198 /* Replace the relocation token with ' ', so that
3199 errors like foo@GOTOFF1 will be detected. */
3201 /* The length of the first part of our input line. */
3202 first
= cp
- input_line_pointer
;
3204 /* The second part goes from after the reloc token until
3205 (and including) an end_of_line char. Don't use strlen
3206 here as the end_of_line char may not be a NUL. */
3207 past_reloc
= cp
+ 1 + len
;
3208 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3210 second
= cp
- past_reloc
;
3212 /* Allocate and copy string. The trailing NUL shouldn't
3213 be necessary, but be safe. */
3214 tmpbuf
= xmalloc (first
+ second
+ 2);
3215 memcpy (tmpbuf
, input_line_pointer
, first
);
3216 tmpbuf
[first
] = ' ';
3217 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3218 tmpbuf
[first
+ second
+ 1] = '\0';
3222 as_bad (_("@%s reloc is not supported in %s bit mode"),
3223 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3228 /* Might be a symbol version string. Don't as_bad here. */
3232 /* x86_cons_fix_new is called via the expression parsing code when a
3233 reloc is needed. We use this hook to get the correct .got reloc. */
3234 static RELOC_ENUM got_reloc
= NO_RELOC
;
3237 x86_cons_fix_new (frag
, off
, len
, exp
)
3243 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3244 got_reloc
= NO_RELOC
;
3245 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3249 x86_cons (exp
, size
)
3255 /* Handle @GOTOFF and the like in an expression. */
3257 char *gotfree_input_line
;
3260 save
= input_line_pointer
;
3261 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3262 if (gotfree_input_line
)
3263 input_line_pointer
= gotfree_input_line
;
3267 if (gotfree_input_line
)
3269 /* expression () has merrily parsed up to the end of line,
3270 or a comma - in the wrong buffer. Transfer how far
3271 input_line_pointer has moved to the right buffer. */
3272 input_line_pointer
= (save
3273 + (input_line_pointer
- gotfree_input_line
)
3275 free (gotfree_input_line
);
3283 static int i386_immediate
PARAMS ((char *));
3286 i386_immediate (imm_start
)
3289 char *save_input_line_pointer
;
3291 char *gotfree_input_line
;
3296 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3298 as_bad (_("only 1 or 2 immediate operands are allowed"));
3302 exp
= &im_expressions
[i
.imm_operands
++];
3303 i
.op
[this_operand
].imms
= exp
;
3305 if (is_space_char (*imm_start
))
3308 save_input_line_pointer
= input_line_pointer
;
3309 input_line_pointer
= imm_start
;
3312 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3313 if (gotfree_input_line
)
3314 input_line_pointer
= gotfree_input_line
;
3317 exp_seg
= expression (exp
);
3320 if (*input_line_pointer
)
3321 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3323 input_line_pointer
= save_input_line_pointer
;
3325 if (gotfree_input_line
)
3326 free (gotfree_input_line
);
3329 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3331 /* Missing or bad expr becomes absolute 0. */
3332 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3334 exp
->X_op
= O_constant
;
3335 exp
->X_add_number
= 0;
3336 exp
->X_add_symbol
= (symbolS
*) 0;
3337 exp
->X_op_symbol
= (symbolS
*) 0;
3339 else if (exp
->X_op
== O_constant
)
3341 /* Size it properly later. */
3342 i
.types
[this_operand
] |= Imm64
;
3343 /* If BFD64, sign extend val. */
3344 if (!use_rela_relocations
)
3345 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3346 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3348 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3350 #ifdef BFD_ASSEMBLER
3351 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3353 && exp_seg
!= text_section
3354 && exp_seg
!= data_section
3355 && exp_seg
!= bss_section
3356 && exp_seg
!= undefined_section
3357 #ifdef BFD_ASSEMBLER
3358 && !bfd_is_com_section (exp_seg
)
3362 #ifdef BFD_ASSEMBLER
3363 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3365 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3372 /* This is an address. The size of the address will be
3373 determined later, depending on destination register,
3374 suffix, or the default for the section. */
3375 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3381 static char *i386_scale
PARAMS ((char *));
3388 char *save
= input_line_pointer
;
3390 input_line_pointer
= scale
;
3391 val
= get_absolute_expression ();
3397 i
.log2_scale_factor
= 0;
3400 i
.log2_scale_factor
= 1;
3403 i
.log2_scale_factor
= 2;
3406 i
.log2_scale_factor
= 3;
3409 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3411 input_line_pointer
= save
;
3414 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3416 as_warn (_("scale factor of %d without an index register"),
3417 1 << i
.log2_scale_factor
);
3418 #if SCALE1_WHEN_NO_INDEX
3419 i
.log2_scale_factor
= 0;
3422 scale
= input_line_pointer
;
3423 input_line_pointer
= save
;
3427 static int i386_displacement
PARAMS ((char *, char *));
3430 i386_displacement (disp_start
, disp_end
)
3434 register expressionS
*exp
;
3436 char *save_input_line_pointer
;
3438 char *gotfree_input_line
;
3440 int bigdisp
= Disp32
;
3442 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3444 if (flag_code
== CODE_64BIT
)
3446 i
.types
[this_operand
] |= bigdisp
;
3448 exp
= &disp_expressions
[i
.disp_operands
];
3449 i
.op
[this_operand
].disps
= exp
;
3451 save_input_line_pointer
= input_line_pointer
;
3452 input_line_pointer
= disp_start
;
3453 END_STRING_AND_SAVE (disp_end
);
3455 #ifndef GCC_ASM_O_HACK
3456 #define GCC_ASM_O_HACK 0
3459 END_STRING_AND_SAVE (disp_end
+ 1);
3460 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3461 && displacement_string_end
[-1] == '+')
3463 /* This hack is to avoid a warning when using the "o"
3464 constraint within gcc asm statements.
3467 #define _set_tssldt_desc(n,addr,limit,type) \
3468 __asm__ __volatile__ ( \
3470 "movw %w1,2+%0\n\t" \
3472 "movb %b1,4+%0\n\t" \
3473 "movb %4,5+%0\n\t" \
3474 "movb $0,6+%0\n\t" \
3475 "movb %h1,7+%0\n\t" \
3477 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3479 This works great except that the output assembler ends
3480 up looking a bit weird if it turns out that there is
3481 no offset. You end up producing code that looks like:
3494 So here we provide the missing zero. */
3496 *displacement_string_end
= '0';
3500 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3501 if (gotfree_input_line
)
3502 input_line_pointer
= gotfree_input_line
;
3505 exp_seg
= expression (exp
);
3508 if (*input_line_pointer
)
3509 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3511 RESTORE_END_STRING (disp_end
+ 1);
3513 RESTORE_END_STRING (disp_end
);
3514 input_line_pointer
= save_input_line_pointer
;
3516 if (gotfree_input_line
)
3517 free (gotfree_input_line
);
3520 #ifdef BFD_ASSEMBLER
3521 /* We do this to make sure that the section symbol is in
3522 the symbol table. We will ultimately change the relocation
3523 to be relative to the beginning of the section. */
3524 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3525 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3527 if (exp
->X_op
!= O_symbol
)
3529 as_bad (_("bad expression used with @%s"),
3530 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3536 if (S_IS_LOCAL (exp
->X_add_symbol
)
3537 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3538 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3539 exp
->X_op
= O_subtract
;
3540 exp
->X_op_symbol
= GOT_symbol
;
3541 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3542 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3544 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3548 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3550 /* Missing or bad expr becomes absolute 0. */
3551 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3553 exp
->X_op
= O_constant
;
3554 exp
->X_add_number
= 0;
3555 exp
->X_add_symbol
= (symbolS
*) 0;
3556 exp
->X_op_symbol
= (symbolS
*) 0;
3559 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3560 if (exp
->X_op
!= O_constant
3561 #ifdef BFD_ASSEMBLER
3562 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3564 && exp_seg
!= text_section
3565 && exp_seg
!= data_section
3566 && exp_seg
!= bss_section
3567 && exp_seg
!= undefined_section
)
3569 #ifdef BFD_ASSEMBLER
3570 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3572 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3577 else if (flag_code
== CODE_64BIT
)
3578 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3582 static int i386_index_check
PARAMS ((const char *));
3584 /* Make sure the memory operand we've been dealt is valid.
3585 Return 1 on success, 0 on a failure. */
3588 i386_index_check (operand_string
)
3589 const char *operand_string
;
3592 #if INFER_ADDR_PREFIX
3598 if (flag_code
== CODE_64BIT
)
3602 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3603 && (i
.base_reg
->reg_type
!= BaseIndex
3606 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3607 != (Reg64
|BaseIndex
))))
3612 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3616 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3617 != (Reg16
|BaseIndex
)))
3619 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3620 != (Reg16
|BaseIndex
))
3622 && i
.base_reg
->reg_num
< 6
3623 && i
.index_reg
->reg_num
>= 6
3624 && i
.log2_scale_factor
== 0))))
3631 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3633 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3634 != (Reg32
|BaseIndex
))))
3640 #if INFER_ADDR_PREFIX
3641 if (flag_code
!= CODE_64BIT
3642 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3644 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3646 /* Change the size of any displacement too. At most one of
3647 Disp16 or Disp32 is set.
3648 FIXME. There doesn't seem to be any real need for separate
3649 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3650 Removing them would probably clean up the code quite a lot. */
3651 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3652 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3657 as_bad (_("`%s' is not a valid base/index expression"),
3661 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3663 flag_code_names
[flag_code
]);
3669 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3673 i386_operand (operand_string
)
3674 char *operand_string
;
3678 char *op_string
= operand_string
;
3680 if (is_space_char (*op_string
))
3683 /* We check for an absolute prefix (differentiating,
3684 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3685 if (*op_string
== ABSOLUTE_PREFIX
)
3688 if (is_space_char (*op_string
))
3690 i
.types
[this_operand
] |= JumpAbsolute
;
3693 /* Check if operand is a register. */
3694 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3695 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3697 /* Check for a segment override by searching for ':' after a
3698 segment register. */
3700 if (is_space_char (*op_string
))
3702 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3707 i
.seg
[i
.mem_operands
] = &es
;
3710 i
.seg
[i
.mem_operands
] = &cs
;
3713 i
.seg
[i
.mem_operands
] = &ss
;
3716 i
.seg
[i
.mem_operands
] = &ds
;
3719 i
.seg
[i
.mem_operands
] = &fs
;
3722 i
.seg
[i
.mem_operands
] = &gs
;
3726 /* Skip the ':' and whitespace. */
3728 if (is_space_char (*op_string
))
3731 if (!is_digit_char (*op_string
)
3732 && !is_identifier_char (*op_string
)
3733 && *op_string
!= '('
3734 && *op_string
!= ABSOLUTE_PREFIX
)
3736 as_bad (_("bad memory operand `%s'"), op_string
);
3739 /* Handle case of %es:*foo. */
3740 if (*op_string
== ABSOLUTE_PREFIX
)
3743 if (is_space_char (*op_string
))
3745 i
.types
[this_operand
] |= JumpAbsolute
;
3747 goto do_memory_reference
;
3751 as_bad (_("junk `%s' after register"), op_string
);
3754 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3755 i
.op
[this_operand
].regs
= r
;
3758 else if (*op_string
== REGISTER_PREFIX
)
3760 as_bad (_("bad register name `%s'"), op_string
);
3763 else if (*op_string
== IMMEDIATE_PREFIX
)
3766 if (i
.types
[this_operand
] & JumpAbsolute
)
3768 as_bad (_("immediate operand illegal with absolute jump"));
3771 if (!i386_immediate (op_string
))
3774 else if (is_digit_char (*op_string
)
3775 || is_identifier_char (*op_string
)
3776 || *op_string
== '(')
3778 /* This is a memory reference of some sort. */
3781 /* Start and end of displacement string expression (if found). */
3782 char *displacement_string_start
;
3783 char *displacement_string_end
;
3785 do_memory_reference
:
3786 if ((i
.mem_operands
== 1
3787 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3788 || i
.mem_operands
== 2)
3790 as_bad (_("too many memory references for `%s'"),
3791 current_templates
->start
->name
);
3795 /* Check for base index form. We detect the base index form by
3796 looking for an ')' at the end of the operand, searching
3797 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3799 base_string
= op_string
+ strlen (op_string
);
3802 if (is_space_char (*base_string
))
3805 /* If we only have a displacement, set-up for it to be parsed later. */
3806 displacement_string_start
= op_string
;
3807 displacement_string_end
= base_string
+ 1;
3809 if (*base_string
== ')')
3812 unsigned int parens_balanced
= 1;
3813 /* We've already checked that the number of left & right ()'s are
3814 equal, so this loop will not be infinite. */
3818 if (*base_string
== ')')
3820 if (*base_string
== '(')
3823 while (parens_balanced
);
3825 temp_string
= base_string
;
3827 /* Skip past '(' and whitespace. */
3829 if (is_space_char (*base_string
))
3832 if (*base_string
== ','
3833 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3834 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3836 displacement_string_end
= temp_string
;
3838 i
.types
[this_operand
] |= BaseIndex
;
3842 base_string
= end_op
;
3843 if (is_space_char (*base_string
))
3847 /* There may be an index reg or scale factor here. */
3848 if (*base_string
== ',')
3851 if (is_space_char (*base_string
))
3854 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3855 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3857 base_string
= end_op
;
3858 if (is_space_char (*base_string
))
3860 if (*base_string
== ',')
3863 if (is_space_char (*base_string
))
3866 else if (*base_string
!= ')')
3868 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3873 else if (*base_string
== REGISTER_PREFIX
)
3875 as_bad (_("bad register name `%s'"), base_string
);
3879 /* Check for scale factor. */
3880 if (*base_string
!= ')')
3882 char *end_scale
= i386_scale (base_string
);
3887 base_string
= end_scale
;
3888 if (is_space_char (*base_string
))
3890 if (*base_string
!= ')')
3892 as_bad (_("expecting `)' after scale factor in `%s'"),
3897 else if (!i
.index_reg
)
3899 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3904 else if (*base_string
!= ')')
3906 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3911 else if (*base_string
== REGISTER_PREFIX
)
3913 as_bad (_("bad register name `%s'"), base_string
);
3918 /* If there's an expression beginning the operand, parse it,
3919 assuming displacement_string_start and
3920 displacement_string_end are meaningful. */
3921 if (displacement_string_start
!= displacement_string_end
)
3923 if (!i386_displacement (displacement_string_start
,
3924 displacement_string_end
))
3928 /* Special case for (%dx) while doing input/output op. */
3930 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3932 && i
.log2_scale_factor
== 0
3933 && i
.seg
[i
.mem_operands
] == 0
3934 && (i
.types
[this_operand
] & Disp
) == 0)
3936 i
.types
[this_operand
] = InOutPortReg
;
3940 if (i386_index_check (operand_string
) == 0)
3946 /* It's not a memory operand; argh! */
3947 as_bad (_("invalid char %s beginning operand %d `%s'"),
3948 output_invalid (*op_string
),
3953 return 1; /* Normal return. */
3956 /* md_estimate_size_before_relax()
3958 Called just before relax() for rs_machine_dependent frags. The x86
3959 assembler uses these frags to handle variable size jump
3962 Any symbol that is now undefined will not become defined.
3963 Return the correct fr_subtype in the frag.
3964 Return the initial "guess for variable size of frag" to caller.
3965 The guess is actually the growth beyond the fixed part. Whatever
3966 we do to grow the fixed or variable part contributes to our
3970 md_estimate_size_before_relax (fragP
, segment
)
3971 register fragS
*fragP
;
3972 register segT segment
;
3974 /* We've already got fragP->fr_subtype right; all we have to do is
3975 check for un-relaxable symbols. On an ELF system, we can't relax
3976 an externally visible symbol, because it may be overridden by a
3978 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3979 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3980 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3981 || S_IS_WEAK (fragP
->fr_symbol
)
3985 /* Symbol is undefined in this segment, or we need to keep a
3986 reloc so that weak symbols can be overridden. */
3987 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3988 RELOC_ENUM reloc_type
;
3989 unsigned char *opcode
;
3992 if (fragP
->fr_var
!= NO_RELOC
)
3993 reloc_type
= fragP
->fr_var
;
3995 reloc_type
= BFD_RELOC_16_PCREL
;
3997 reloc_type
= BFD_RELOC_32_PCREL
;
3999 old_fr_fix
= fragP
->fr_fix
;
4000 opcode
= (unsigned char *) fragP
->fr_opcode
;
4002 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4005 /* Make jmp (0xeb) a (d)word displacement jump. */
4007 fragP
->fr_fix
+= size
;
4008 fix_new (fragP
, old_fr_fix
, size
,
4010 fragP
->fr_offset
, 1,
4015 if (no_cond_jump_promotion
)
4020 /* Negate the condition, and branch past an
4021 unconditional jump. */
4024 /* Insert an unconditional jump. */
4026 /* We added two extra opcode bytes, and have a two byte
4028 fragP
->fr_fix
+= 2 + 2;
4029 fix_new (fragP
, old_fr_fix
+ 2, 2,
4031 fragP
->fr_offset
, 1,
4038 if (no_cond_jump_promotion
)
4041 /* This changes the byte-displacement jump 0x7N
4042 to the (d)word-displacement jump 0x0f,0x8N. */
4043 opcode
[1] = opcode
[0] + 0x10;
4044 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4045 /* We've added an opcode byte. */
4046 fragP
->fr_fix
+= 1 + size
;
4047 fix_new (fragP
, old_fr_fix
+ 1, size
,
4049 fragP
->fr_offset
, 1,
4054 BAD_CASE (fragP
->fr_subtype
);
4058 return fragP
->fr_fix
- old_fr_fix
;
4062 /* Guess size depending on current relax state. Initially the relax
4063 state will correspond to a short jump and we return 1, because
4064 the variable part of the frag (the branch offset) is one byte
4065 long. However, we can relax a section more than once and in that
4066 case we must either set fr_subtype back to the unrelaxed state,
4067 or return the value for the appropriate branch. */
4068 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4071 /* Called after relax() is finished.
4073 In: Address of frag.
4074 fr_type == rs_machine_dependent.
4075 fr_subtype is what the address relaxed to.
4077 Out: Any fixSs and constants are set up.
4078 Caller will turn frag into a ".space 0". */
4080 #ifndef BFD_ASSEMBLER
4082 md_convert_frag (headers
, sec
, fragP
)
4083 object_headers
*headers ATTRIBUTE_UNUSED
;
4084 segT sec ATTRIBUTE_UNUSED
;
4085 register fragS
*fragP
;
4088 md_convert_frag (abfd
, sec
, fragP
)
4089 bfd
*abfd ATTRIBUTE_UNUSED
;
4090 segT sec ATTRIBUTE_UNUSED
;
4091 register fragS
*fragP
;
4094 register unsigned char *opcode
;
4095 unsigned char *where_to_put_displacement
= NULL
;
4096 offsetT target_address
;
4097 offsetT opcode_address
;
4098 unsigned int extension
= 0;
4099 offsetT displacement_from_opcode_start
;
4101 opcode
= (unsigned char *) fragP
->fr_opcode
;
4103 /* Address we want to reach in file space. */
4104 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4106 /* Address opcode resides at in file space. */
4107 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4109 /* Displacement from opcode start to fill into instruction. */
4110 displacement_from_opcode_start
= target_address
- opcode_address
;
4112 if ((fragP
->fr_subtype
& BIG
) == 0)
4114 /* Don't have to change opcode. */
4115 extension
= 1; /* 1 opcode + 1 displacement */
4116 where_to_put_displacement
= &opcode
[1];
4120 if (no_cond_jump_promotion
4121 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4122 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4124 switch (fragP
->fr_subtype
)
4126 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4127 extension
= 4; /* 1 opcode + 4 displacement */
4129 where_to_put_displacement
= &opcode
[1];
4132 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4133 extension
= 2; /* 1 opcode + 2 displacement */
4135 where_to_put_displacement
= &opcode
[1];
4138 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4139 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4140 extension
= 5; /* 2 opcode + 4 displacement */
4141 opcode
[1] = opcode
[0] + 0x10;
4142 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4143 where_to_put_displacement
= &opcode
[2];
4146 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4147 extension
= 3; /* 2 opcode + 2 displacement */
4148 opcode
[1] = opcode
[0] + 0x10;
4149 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4150 where_to_put_displacement
= &opcode
[2];
4153 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4158 where_to_put_displacement
= &opcode
[3];
4162 BAD_CASE (fragP
->fr_subtype
);
4167 /* Now put displacement after opcode. */
4168 md_number_to_chars ((char *) where_to_put_displacement
,
4169 (valueT
) (displacement_from_opcode_start
- extension
),
4170 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4171 fragP
->fr_fix
+= extension
;
4174 /* Size of byte displacement jmp. */
4175 int md_short_jump_size
= 2;
4177 /* Size of dword displacement jmp. */
4178 int md_long_jump_size
= 5;
4180 /* Size of relocation record. */
4181 const int md_reloc_size
= 8;
4184 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4186 addressT from_addr
, to_addr
;
4187 fragS
*frag ATTRIBUTE_UNUSED
;
4188 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4192 offset
= to_addr
- (from_addr
+ 2);
4193 /* Opcode for byte-disp jump. */
4194 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4195 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4199 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4201 addressT from_addr
, to_addr
;
4202 fragS
*frag ATTRIBUTE_UNUSED
;
4203 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4207 offset
= to_addr
- (from_addr
+ 5);
4208 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4209 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4212 /* Apply a fixup (fixS) to segment data, once it has been determined
4213 by our caller that we have all the info we need to fix it up.
4215 On the 386, immediates, displacements, and data pointers are all in
4216 the same (little-endian) format, so we don't need to care about which
4220 md_apply_fix3 (fixP
, valp
, seg
)
4221 /* The fix we're to put in. */
4224 /* Pointer to the value of the bits. */
4227 /* Segment fix is from. */
4228 segT seg ATTRIBUTE_UNUSED
;
4230 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4231 valueT value
= *valp
;
4233 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4236 switch (fixP
->fx_r_type
)
4242 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4245 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4248 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4253 /* This is a hack. There should be a better way to handle this.
4254 This covers for the fact that bfd_install_relocation will
4255 subtract the current location (for partial_inplace, PC relative
4256 relocations); see more below. */
4257 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4258 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4259 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4260 && fixP
->fx_addsy
&& !use_rela_relocations
)
4263 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4265 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4268 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4270 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4271 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4273 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4276 || (symbol_section_p (fixP
->fx_addsy
)
4277 && fseg
!= absolute_section
))
4278 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4279 && ! S_IS_WEAK (fixP
->fx_addsy
)
4280 && S_IS_DEFINED (fixP
->fx_addsy
)
4281 && ! S_IS_COMMON (fixP
->fx_addsy
))
4283 /* Yes, we add the values in twice. This is because
4284 bfd_perform_relocation subtracts them out again. I think
4285 bfd_perform_relocation is broken, but I don't dare change
4287 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4291 #if defined (OBJ_COFF) && defined (TE_PE)
4292 /* For some reason, the PE format does not store a section
4293 address offset for a PC relative symbol. */
4294 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4295 value
+= md_pcrel_from (fixP
);
4299 /* Fix a few things - the dynamic linker expects certain values here,
4300 and we must not dissappoint it. */
4301 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4302 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4304 switch (fixP
->fx_r_type
)
4306 case BFD_RELOC_386_PLT32
:
4307 case BFD_RELOC_X86_64_PLT32
:
4308 /* Make the jump instruction point to the address of the operand. At
4309 runtime we merely add the offset to the actual PLT entry. */
4312 case BFD_RELOC_386_GOTPC
:
4314 /* This is tough to explain. We end up with this one if we have
4315 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4316 * here is to obtain the absolute address of the GOT, and it is strongly
4317 * preferable from a performance point of view to avoid using a runtime
4318 * relocation for this. The actual sequence of instructions often look
4324 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4326 * The call and pop essentially return the absolute address of
4327 * the label .L66 and store it in %ebx. The linker itself will
4328 * ultimately change the first operand of the addl so that %ebx points to
4329 * the GOT, but to keep things simple, the .o file must have this operand
4330 * set so that it generates not the absolute address of .L66, but the
4331 * absolute address of itself. This allows the linker itself simply
4332 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4333 * added in, and the addend of the relocation is stored in the operand
4334 * field for the instruction itself.
4336 * Our job here is to fix the operand so that it would add the correct
4337 * offset so that %ebx would point to itself. The thing that is tricky is
4338 * that .-.L66 will point to the beginning of the instruction, so we need
4339 * to further modify the operand so that it will point to itself.
4340 * There are other cases where you have something like:
4342 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4344 * and here no correction would be required. Internally in the assembler
4345 * we treat operands of this form as not being pcrel since the '.' is
4346 * explicitly mentioned, and I wonder whether it would simplify matters
4347 * to do it this way. Who knows. In earlier versions of the PIC patches,
4348 * the pcrel_adjust field was used to store the correction, but since the
4349 * expression is not pcrel, I felt it would be confusing to do it this
4354 case BFD_RELOC_386_GOT32
:
4355 case BFD_RELOC_X86_64_GOT32
:
4356 value
= 0; /* Fully resolved at runtime. No addend. */
4358 case BFD_RELOC_386_GOTOFF
:
4359 case BFD_RELOC_X86_64_GOTPCREL
:
4362 case BFD_RELOC_VTABLE_INHERIT
:
4363 case BFD_RELOC_VTABLE_ENTRY
:
4370 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4372 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4374 #ifndef BFD_ASSEMBLER
4375 md_number_to_chars (p
, value
, fixP
->fx_size
);
4377 /* Are we finished with this relocation now? */
4378 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4380 else if (use_rela_relocations
)
4382 fixP
->fx_no_overflow
= 1;
4385 md_number_to_chars (p
, value
, fixP
->fx_size
);
4391 #define MAX_LITTLENUMS 6
4393 /* Turn the string pointed to by litP into a floating point constant
4394 of type TYPE, and emit the appropriate bytes. The number of
4395 LITTLENUMS emitted is stored in *SIZEP. An error message is
4396 returned, or NULL on OK. */
4399 md_atof (type
, litP
, sizeP
)
4405 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4406 LITTLENUM_TYPE
*wordP
;
4428 return _("Bad call to md_atof ()");
4430 t
= atof_ieee (input_line_pointer
, type
, words
);
4432 input_line_pointer
= t
;
4434 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4435 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4436 the bigendian 386. */
4437 for (wordP
= words
+ prec
- 1; prec
--;)
4439 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4440 litP
+= sizeof (LITTLENUM_TYPE
);
4445 char output_invalid_buf
[8];
4452 sprintf (output_invalid_buf
, "'%c'", c
);
4454 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4455 return output_invalid_buf
;
4458 /* REG_STRING starts *before* REGISTER_PREFIX. */
4460 static const reg_entry
*
4461 parse_register (reg_string
, end_op
)
4465 char *s
= reg_string
;
4467 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4470 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4471 if (*s
== REGISTER_PREFIX
)
4474 if (is_space_char (*s
))
4478 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4480 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4481 return (const reg_entry
*) NULL
;
4485 /* For naked regs, make sure that we are not dealing with an identifier.
4486 This prevents confusing an identifier like `eax_var' with register
4488 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4489 return (const reg_entry
*) NULL
;
4493 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4495 /* Handle floating point regs, allowing spaces in the (i) part. */
4496 if (r
== i386_regtab
/* %st is first entry of table */)
4498 if (is_space_char (*s
))
4503 if (is_space_char (*s
))
4505 if (*s
>= '0' && *s
<= '7')
4507 r
= &i386_float_regtab
[*s
- '0'];
4509 if (is_space_char (*s
))
4517 /* We have "%st(" then garbage. */
4518 return (const reg_entry
*) NULL
;
4525 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4526 const char *md_shortopts
= "kVQ:sq";
4528 const char *md_shortopts
= "q";
4531 struct option md_longopts
[] = {
4532 #define OPTION_32 (OPTION_MD_BASE + 0)
4533 {"32", no_argument
, NULL
, OPTION_32
},
4534 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4535 #define OPTION_64 (OPTION_MD_BASE + 1)
4536 {"64", no_argument
, NULL
, OPTION_64
},
4538 {NULL
, no_argument
, NULL
, 0}
4540 size_t md_longopts_size
= sizeof (md_longopts
);
4543 md_parse_option (c
, arg
)
4545 char *arg ATTRIBUTE_UNUSED
;
4553 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4554 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4555 should be emitted or not. FIXME: Not implemented. */
4559 /* -V: SVR4 argument to print version ID. */
4561 print_version_id ();
4564 /* -k: Ignore for FreeBSD compatibility. */
4569 /* -s: On i386 Solaris, this tells the native assembler to use
4570 .stab instead of .stab.excl. We always use .stab anyhow. */
4575 const char **list
, **l
;
4577 list
= bfd_target_list ();
4578 for (l
= list
; *l
!= NULL
; l
++)
4579 if (strcmp (*l
, "elf64-x86-64") == 0)
4581 default_arch
= "x86_64";
4585 as_fatal (_("No compiled in support for x86_64"));
4592 default_arch
= "i386";
4602 md_show_usage (stream
)
4605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4606 fprintf (stream
, _("\
4608 -V print assembler version number\n\
4610 -q quieten some warnings\n\
4613 fprintf (stream
, _("\
4614 -q quieten some warnings\n"));
4618 #ifdef BFD_ASSEMBLER
4619 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4620 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4622 /* Pick the target format to use. */
4625 i386_target_format ()
4627 if (!strcmp (default_arch
, "x86_64"))
4628 set_code_flag (CODE_64BIT
);
4629 else if (!strcmp (default_arch
, "i386"))
4630 set_code_flag (CODE_32BIT
);
4632 as_fatal (_("Unknown architecture"));
4633 switch (OUTPUT_FLAVOR
)
4635 #ifdef OBJ_MAYBE_AOUT
4636 case bfd_target_aout_flavour
:
4637 return AOUT_TARGET_FORMAT
;
4639 #ifdef OBJ_MAYBE_COFF
4640 case bfd_target_coff_flavour
:
4643 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4644 case bfd_target_elf_flavour
:
4646 if (flag_code
== CODE_64BIT
)
4647 use_rela_relocations
= 1;
4648 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4657 #endif /* OBJ_MAYBE_ more than one */
4658 #endif /* BFD_ASSEMBLER */
4661 md_undefined_symbol (name
)
4664 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4665 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4666 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4667 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4671 if (symbol_find (name
))
4672 as_bad (_("GOT already in symbol table"));
4673 GOT_symbol
= symbol_new (name
, undefined_section
,
4674 (valueT
) 0, &zero_address_frag
);
4681 /* Round up a section size to the appropriate boundary. */
4684 md_section_align (segment
, size
)
4685 segT segment ATTRIBUTE_UNUSED
;
4688 #ifdef BFD_ASSEMBLER
4689 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4690 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4692 /* For a.out, force the section size to be aligned. If we don't do
4693 this, BFD will align it for us, but it will not write out the
4694 final bytes of the section. This may be a bug in BFD, but it is
4695 easier to fix it here since that is how the other a.out targets
4699 align
= bfd_get_section_alignment (stdoutput
, segment
);
4700 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4708 /* On the i386, PC-relative offsets are relative to the start of the
4709 next instruction. That is, the address of the offset, plus its
4710 size, since the offset is always the last part of the insn. */
4713 md_pcrel_from (fixP
)
4716 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4723 int ignore ATTRIBUTE_UNUSED
;
4727 temp
= get_absolute_expression ();
4728 subseg_set (bss_section
, (subsegT
) temp
);
4729 demand_empty_rest_of_line ();
4734 #ifdef BFD_ASSEMBLER
4737 i386_validate_fix (fixp
)
4740 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4742 /* GOTOFF relocation are nonsense in 64bit mode. */
4743 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4745 if (flag_code
!= CODE_64BIT
)
4747 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4751 if (flag_code
== CODE_64BIT
)
4753 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4760 tc_gen_reloc (section
, fixp
)
4761 asection
*section ATTRIBUTE_UNUSED
;
4765 bfd_reloc_code_real_type code
;
4767 switch (fixp
->fx_r_type
)
4769 case BFD_RELOC_X86_64_PLT32
:
4770 case BFD_RELOC_X86_64_GOT32
:
4771 case BFD_RELOC_X86_64_GOTPCREL
:
4772 case BFD_RELOC_386_PLT32
:
4773 case BFD_RELOC_386_GOT32
:
4774 case BFD_RELOC_386_GOTOFF
:
4775 case BFD_RELOC_386_GOTPC
:
4776 case BFD_RELOC_X86_64_32S
:
4778 case BFD_RELOC_VTABLE_ENTRY
:
4779 case BFD_RELOC_VTABLE_INHERIT
:
4780 code
= fixp
->fx_r_type
;
4785 switch (fixp
->fx_size
)
4788 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4789 _("can not do %d byte pc-relative relocation"),
4791 code
= BFD_RELOC_32_PCREL
;
4793 case 1: code
= BFD_RELOC_8_PCREL
; break;
4794 case 2: code
= BFD_RELOC_16_PCREL
; break;
4795 case 4: code
= BFD_RELOC_32_PCREL
; break;
4800 switch (fixp
->fx_size
)
4803 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4804 _("can not do %d byte relocation"),
4806 code
= BFD_RELOC_32
;
4808 case 1: code
= BFD_RELOC_8
; break;
4809 case 2: code
= BFD_RELOC_16
; break;
4810 case 4: code
= BFD_RELOC_32
; break;
4811 case 8: code
= BFD_RELOC_64
; break;
4817 if (code
== BFD_RELOC_32
4819 && fixp
->fx_addsy
== GOT_symbol
)
4821 /* We don't support GOTPC on 64bit targets. */
4822 if (flag_code
== CODE_64BIT
)
4824 code
= BFD_RELOC_386_GOTPC
;
4827 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4828 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4829 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4831 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4832 if (!use_rela_relocations
)
4834 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4835 vtable entry to be used in the relocation's section offset. */
4836 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4837 rel
->address
= fixp
->fx_offset
;
4840 rel
->addend
= fixp
->fx_addnumber
;
4844 /* Use the rela in 64bit mode. */
4847 rel
->addend
= fixp
->fx_offset
;
4849 rel
->addend
-= fixp
->fx_size
;
4852 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4853 if (rel
->howto
== NULL
)
4855 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4856 _("cannot represent relocation type %s"),
4857 bfd_get_reloc_code_name (code
));
4858 /* Set howto to a garbage value so that we can keep going. */
4859 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4860 assert (rel
->howto
!= NULL
);
4866 #else /* ! BFD_ASSEMBLER */
4868 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4870 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4873 relax_addressT segment_address_in_file
;
4875 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4876 Out: GNU LD relocation length code: 0, 1, or 2. */
4878 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4881 know (fixP
->fx_addsy
!= NULL
);
4883 md_number_to_chars (where
,
4884 (valueT
) (fixP
->fx_frag
->fr_address
4885 + fixP
->fx_where
- segment_address_in_file
),
4888 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4889 ? S_GET_TYPE (fixP
->fx_addsy
)
4890 : fixP
->fx_addsy
->sy_number
);
4892 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4893 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4894 where
[4] = r_symbolnum
& 0x0ff;
4895 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4896 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4897 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4900 #endif /* OBJ_AOUT or OBJ_BOUT. */
4902 #if defined (I386COFF)
4905 tc_coff_fix2rtype (fixP
)
4908 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4911 return (fixP
->fx_pcrel
?
4912 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4913 fixP
->fx_size
== 2 ? R_PCRWORD
:
4915 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4916 fixP
->fx_size
== 2 ? R_RELWORD
:
4921 tc_coff_sizemachdep (frag
)
4925 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4930 #endif /* I386COFF */
4932 #endif /* ! BFD_ASSEMBLER */
4934 /* Parse operands using Intel syntax. This implements a recursive descent
4935 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4938 FIXME: We do not recognize the full operand grammar defined in the MASM
4939 documentation. In particular, all the structure/union and
4940 high-level macro operands are missing.
4942 Uppercase words are terminals, lower case words are non-terminals.
4943 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4944 bars '|' denote choices. Most grammar productions are implemented in
4945 functions called 'intel_<production>'.
4947 Initial production is 'expr'.
4953 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4955 constant digits [[ radixOverride ]]
4957 dataType BYTE | WORD | DWORD | QWORD | XWORD
4990 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4991 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4993 hexdigit a | b | c | d | e | f
4994 | A | B | C | D | E | F
5004 register specialRegister
5008 segmentRegister CS | DS | ES | FS | GS | SS
5010 specialRegister CR0 | CR2 | CR3
5011 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5012 | TR3 | TR4 | TR5 | TR6 | TR7
5014 We simplify the grammar in obvious places (e.g., register parsing is
5015 done by calling parse_register) and eliminate immediate left recursion
5016 to implement a recursive-descent parser.
5056 /* Parsing structure for the intel syntax parser. Used to implement the
5057 semantic actions for the operand grammar. */
5058 struct intel_parser_s
5060 char *op_string
; /* The string being parsed. */
5061 int got_a_float
; /* Whether the operand is a float. */
5062 int op_modifier
; /* Operand modifier. */
5063 int is_mem
; /* 1 if operand is memory reference. */
5064 const reg_entry
*reg
; /* Last register reference found. */
5065 char *disp
; /* Displacement string being built. */
5068 static struct intel_parser_s intel_parser
;
5070 /* Token structure for parsing intel syntax. */
5073 int code
; /* Token code. */
5074 const reg_entry
*reg
; /* Register entry for register tokens. */
5075 char *str
; /* String representation. */
5078 static struct intel_token cur_token
, prev_token
;
5080 /* Token codes for the intel parser. Since T_SHORT is already used
5081 by COFF, undefine it first to prevent a warning. */
5096 /* Prototypes for intel parser functions. */
5097 static int intel_match_token
PARAMS ((int code
));
5098 static void intel_get_token
PARAMS ((void));
5099 static void intel_putback_token
PARAMS ((void));
5100 static int intel_expr
PARAMS ((void));
5101 static int intel_e05
PARAMS ((void));
5102 static int intel_e05_1
PARAMS ((void));
5103 static int intel_e06
PARAMS ((void));
5104 static int intel_e06_1
PARAMS ((void));
5105 static int intel_e09
PARAMS ((void));
5106 static int intel_e09_1
PARAMS ((void));
5107 static int intel_e10
PARAMS ((void));
5108 static int intel_e10_1
PARAMS ((void));
5109 static int intel_e11
PARAMS ((void));
5112 i386_intel_operand (operand_string
, got_a_float
)
5113 char *operand_string
;
5119 /* Initialize token holders. */
5120 cur_token
.code
= prev_token
.code
= T_NIL
;
5121 cur_token
.reg
= prev_token
.reg
= NULL
;
5122 cur_token
.str
= prev_token
.str
= NULL
;
5124 /* Initialize parser structure. */
5125 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5128 strcpy (intel_parser
.op_string
, operand_string
);
5129 intel_parser
.got_a_float
= got_a_float
;
5130 intel_parser
.op_modifier
= -1;
5131 intel_parser
.is_mem
= 0;
5132 intel_parser
.reg
= NULL
;
5133 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5134 if (intel_parser
.disp
== NULL
)
5136 intel_parser
.disp
[0] = '\0';
5138 /* Read the first token and start the parser. */
5140 ret
= intel_expr ();
5144 /* If we found a memory reference, hand it over to i386_displacement
5145 to fill in the rest of the operand fields. */
5146 if (intel_parser
.is_mem
)
5148 if ((i
.mem_operands
== 1
5149 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5150 || i
.mem_operands
== 2)
5152 as_bad (_("too many memory references for '%s'"),
5153 current_templates
->start
->name
);
5158 char *s
= intel_parser
.disp
;
5161 /* Add the displacement expression. */
5163 ret
= i386_displacement (s
, s
+ strlen (s
))
5164 && i386_index_check (s
);
5168 /* Constant and OFFSET expressions are handled by i386_immediate. */
5169 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5170 || intel_parser
.reg
== NULL
)
5171 ret
= i386_immediate (intel_parser
.disp
);
5175 free (intel_parser
.disp
);
5185 /* expr SHORT e05 */
5186 if (cur_token
.code
== T_SHORT
)
5188 intel_parser
.op_modifier
= SHORT
;
5189 intel_match_token (T_SHORT
);
5191 return (intel_e05 ());
5196 return intel_e05 ();
5206 return (intel_e06 () && intel_e05_1 ());
5212 /* e05' addOp e06 e05' */
5213 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5215 strcat (intel_parser
.disp
, cur_token
.str
);
5216 intel_match_token (cur_token
.code
);
5218 return (intel_e06 () && intel_e05_1 ());
5233 return (intel_e09 () && intel_e06_1 ());
5239 /* e06' mulOp e09 e06' */
5240 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5242 strcat (intel_parser
.disp
, cur_token
.str
);
5243 intel_match_token (cur_token
.code
);
5245 return (intel_e09 () && intel_e06_1 ());
5253 /* e09 OFFSET e10 e09'
5262 /* e09 OFFSET e10 e09' */
5263 if (cur_token
.code
== T_OFFSET
)
5265 intel_parser
.is_mem
= 0;
5266 intel_parser
.op_modifier
= OFFSET_FLAT
;
5267 intel_match_token (T_OFFSET
);
5269 return (intel_e10 () && intel_e09_1 ());
5274 return (intel_e10 () && intel_e09_1 ());
5280 /* e09' PTR e10 e09' */
5281 if (cur_token
.code
== T_PTR
)
5283 if (prev_token
.code
== T_BYTE
)
5284 i
.suffix
= BYTE_MNEM_SUFFIX
;
5286 else if (prev_token
.code
== T_WORD
)
5288 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5289 i
.suffix
= SHORT_MNEM_SUFFIX
;
5291 i
.suffix
= WORD_MNEM_SUFFIX
;
5294 else if (prev_token
.code
== T_DWORD
)
5296 if (intel_parser
.got_a_float
== 1) /* "f..." */
5297 i
.suffix
= SHORT_MNEM_SUFFIX
;
5299 i
.suffix
= LONG_MNEM_SUFFIX
;
5302 else if (prev_token
.code
== T_QWORD
)
5304 if (intel_parser
.got_a_float
== 1) /* "f..." */
5305 i
.suffix
= LONG_MNEM_SUFFIX
;
5307 i
.suffix
= QWORD_MNEM_SUFFIX
;
5310 else if (prev_token
.code
== T_XWORD
)
5311 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5315 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5319 intel_match_token (T_PTR
);
5321 return (intel_e10 () && intel_e09_1 ());
5324 /* e09 : e10 e09' */
5325 else if (cur_token
.code
== ':')
5327 /* Mark as a memory operand only if it's not already known to be an
5328 offset expression. */
5329 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5330 intel_parser
.is_mem
= 1;
5332 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5347 return (intel_e11 () && intel_e10_1 ());
5353 /* e10' [ expr ] e10' */
5354 if (cur_token
.code
== '[')
5356 intel_match_token ('[');
5358 /* Mark as a memory operand only if it's not already known to be an
5359 offset expression. If it's an offset expression, we need to keep
5361 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5362 intel_parser
.is_mem
= 1;
5364 strcat (intel_parser
.disp
, "[");
5366 /* Add a '+' to the displacement string if necessary. */
5367 if (*intel_parser
.disp
!= '\0'
5368 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5369 strcat (intel_parser
.disp
, "+");
5371 if (intel_expr () && intel_match_token (']'))
5373 /* Preserve brackets when the operand is an offset expression. */
5374 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5375 strcat (intel_parser
.disp
, "]");
5377 return intel_e10_1 ();
5404 if (cur_token
.code
== '(')
5406 intel_match_token ('(');
5407 strcat (intel_parser
.disp
, "(");
5409 if (intel_expr () && intel_match_token (')'))
5411 strcat (intel_parser
.disp
, ")");
5419 else if (cur_token
.code
== '[')
5421 intel_match_token ('[');
5423 /* Mark as a memory operand only if it's not already known to be an
5424 offset expression. If it's an offset expression, we need to keep
5426 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5427 intel_parser
.is_mem
= 1;
5429 strcat (intel_parser
.disp
, "[");
5431 /* Operands for jump/call inside brackets denote absolute addresses. */
5432 if (current_templates
->start
->opcode_modifier
& Jump
5433 || current_templates
->start
->opcode_modifier
& JumpDword
5434 || current_templates
->start
->opcode_modifier
& JumpByte
5435 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5436 i
.types
[this_operand
] |= JumpAbsolute
;
5438 /* Add a '+' to the displacement string if necessary. */
5439 if (*intel_parser
.disp
!= '\0'
5440 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5441 strcat (intel_parser
.disp
, "+");
5443 if (intel_expr () && intel_match_token (']'))
5445 /* Preserve brackets when the operand is an offset expression. */
5446 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5447 strcat (intel_parser
.disp
, "]");
5460 else if (cur_token
.code
== T_BYTE
5461 || cur_token
.code
== T_WORD
5462 || cur_token
.code
== T_DWORD
5463 || cur_token
.code
== T_QWORD
5464 || cur_token
.code
== T_XWORD
)
5466 intel_match_token (cur_token
.code
);
5473 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5475 strcat (intel_parser
.disp
, cur_token
.str
);
5476 intel_match_token (cur_token
.code
);
5478 /* Mark as a memory operand only if it's not already known to be an
5479 offset expression. */
5480 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5481 intel_parser
.is_mem
= 1;
5487 else if (cur_token
.code
== T_REG
)
5489 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5491 intel_match_token (T_REG
);
5493 /* Check for segment change. */
5494 if (cur_token
.code
== ':')
5496 if (reg
->reg_type
& (SReg2
| SReg3
))
5498 switch (reg
->reg_num
)
5501 i
.seg
[i
.mem_operands
] = &es
;
5504 i
.seg
[i
.mem_operands
] = &cs
;
5507 i
.seg
[i
.mem_operands
] = &ss
;
5510 i
.seg
[i
.mem_operands
] = &ds
;
5513 i
.seg
[i
.mem_operands
] = &fs
;
5516 i
.seg
[i
.mem_operands
] = &gs
;
5522 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5527 /* Not a segment register. Check for register scaling. */
5528 else if (cur_token
.code
== '*')
5530 if (!intel_parser
.is_mem
)
5532 as_bad (_("Register scaling only allowed in memory operands."));
5536 /* What follows must be a valid scale. */
5537 if (intel_match_token ('*')
5538 && strchr ("01248", *cur_token
.str
))
5541 i
.types
[this_operand
] |= BaseIndex
;
5543 /* Set the scale after setting the register (otherwise,
5544 i386_scale will complain) */
5545 i386_scale (cur_token
.str
);
5546 intel_match_token (T_CONST
);
5550 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5556 /* No scaling. If this is a memory operand, the register is either a
5557 base register (first occurrence) or an index register (second
5559 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5561 if (i
.base_reg
&& i
.index_reg
)
5563 as_bad (_("Too many register references in memory operand.\n"));
5567 if (i
.base_reg
== NULL
)
5572 i
.types
[this_operand
] |= BaseIndex
;
5575 /* Offset modifier. Add the register to the displacement string to be
5576 parsed as an immediate expression after we're done. */
5577 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5578 strcat (intel_parser
.disp
, reg
->reg_name
);
5580 /* It's neither base nor index nor offset. */
5583 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5584 i
.op
[this_operand
].regs
= reg
;
5588 /* Since registers are not part of the displacement string (except
5589 when we're parsing offset operands), we may need to remove any
5590 preceding '+' from the displacement string. */
5591 if (*intel_parser
.disp
!= '\0'
5592 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5594 char *s
= intel_parser
.disp
;
5595 s
+= strlen (s
) - 1;
5604 else if (cur_token
.code
== T_ID
)
5606 /* Add the identifier to the displacement string. */
5607 strcat (intel_parser
.disp
, cur_token
.str
);
5608 intel_match_token (T_ID
);
5610 /* The identifier represents a memory reference only if it's not
5611 preceded by an offset modifier. */
5612 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5613 intel_parser
.is_mem
= 1;
5619 else if (cur_token
.code
== T_CONST
5620 || cur_token
.code
== '-'
5621 || cur_token
.code
== '+')
5625 /* Allow constants that start with `+' or `-'. */
5626 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5628 strcat (intel_parser
.disp
, cur_token
.str
);
5629 intel_match_token (cur_token
.code
);
5630 if (cur_token
.code
!= T_CONST
)
5632 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5638 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5639 if (save_str
== NULL
)
5641 strcpy (save_str
, cur_token
.str
);
5643 /* Get the next token to check for register scaling. */
5644 intel_match_token (cur_token
.code
);
5646 /* Check if this constant is a scaling factor for an index register. */
5647 if (cur_token
.code
== '*')
5649 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5651 if (!intel_parser
.is_mem
)
5653 as_bad (_("Register scaling only allowed in memory operands."));
5657 /* The constant is followed by `* reg', so it must be
5659 if (strchr ("01248", *save_str
))
5661 i
.index_reg
= cur_token
.reg
;
5662 i
.types
[this_operand
] |= BaseIndex
;
5664 /* Set the scale after setting the register (otherwise,
5665 i386_scale will complain) */
5666 i386_scale (save_str
);
5667 intel_match_token (T_REG
);
5669 /* Since registers are not part of the displacement
5670 string, we may need to remove any preceding '+' from
5671 the displacement string. */
5672 if (*intel_parser
.disp
!= '\0')
5674 char *s
= intel_parser
.disp
;
5675 s
+= strlen (s
) - 1;
5688 /* The constant was not used for register scaling. Since we have
5689 already consumed the token following `*' we now need to put it
5690 back in the stream. */
5692 intel_putback_token ();
5695 /* Add the constant to the displacement string. */
5696 strcat (intel_parser
.disp
, save_str
);
5702 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5706 /* Match the given token against cur_token. If they match, read the next
5707 token from the operand string. */
5709 intel_match_token (code
)
5712 if (cur_token
.code
== code
)
5719 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5724 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5729 const reg_entry
*reg
;
5730 struct intel_token new_token
;
5732 new_token
.code
= T_NIL
;
5733 new_token
.reg
= NULL
;
5734 new_token
.str
= NULL
;
5736 /* Free the memory allocated to the previous token and move
5737 cur_token to prev_token. */
5739 free (prev_token
.str
);
5741 prev_token
= cur_token
;
5743 /* Skip whitespace. */
5744 while (is_space_char (*intel_parser
.op_string
))
5745 intel_parser
.op_string
++;
5747 /* Return an empty token if we find nothing else on the line. */
5748 if (*intel_parser
.op_string
== '\0')
5750 cur_token
= new_token
;
5754 /* The new token cannot be larger than the remainder of the operand
5756 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5757 if (new_token
.str
== NULL
)
5759 new_token
.str
[0] = '\0';
5761 if (strchr ("0123456789", *intel_parser
.op_string
))
5763 char *p
= new_token
.str
;
5764 char *q
= intel_parser
.op_string
;
5765 new_token
.code
= T_CONST
;
5767 /* Allow any kind of identifier char to encompass floating point and
5768 hexadecimal numbers. */
5769 while (is_identifier_char (*q
))
5773 /* Recognize special symbol names [0-9][bf]. */
5774 if (strlen (intel_parser
.op_string
) == 2
5775 && (intel_parser
.op_string
[1] == 'b'
5776 || intel_parser
.op_string
[1] == 'f'))
5777 new_token
.code
= T_ID
;
5780 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5782 new_token
.code
= *intel_parser
.op_string
;
5783 new_token
.str
[0] = *intel_parser
.op_string
;
5784 new_token
.str
[1] = '\0';
5787 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5788 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5790 new_token
.code
= T_REG
;
5791 new_token
.reg
= reg
;
5793 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5795 new_token
.str
[0] = REGISTER_PREFIX
;
5796 new_token
.str
[1] = '\0';
5799 strcat (new_token
.str
, reg
->reg_name
);
5802 else if (is_identifier_char (*intel_parser
.op_string
))
5804 char *p
= new_token
.str
;
5805 char *q
= intel_parser
.op_string
;
5807 /* A '.' or '$' followed by an identifier char is an identifier.
5808 Otherwise, it's operator '.' followed by an expression. */
5809 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5811 new_token
.code
= *q
;
5812 new_token
.str
[0] = *q
;
5813 new_token
.str
[1] = '\0';
5817 while (is_identifier_char (*q
) || *q
== '@')
5821 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5822 new_token
.code
= T_BYTE
;
5824 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5825 new_token
.code
= T_WORD
;
5827 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5828 new_token
.code
= T_DWORD
;
5830 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5831 new_token
.code
= T_QWORD
;
5833 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5834 new_token
.code
= T_XWORD
;
5836 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5837 new_token
.code
= T_PTR
;
5839 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5840 new_token
.code
= T_SHORT
;
5842 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5844 new_token
.code
= T_OFFSET
;
5846 /* ??? This is not mentioned in the MASM grammar but gcc
5847 makes use of it with -mintel-syntax. OFFSET may be
5848 followed by FLAT: */
5849 if (strncasecmp (q
, " FLAT:", 6) == 0)
5850 strcat (new_token
.str
, " FLAT:");
5853 /* ??? This is not mentioned in the MASM grammar. */
5854 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5855 new_token
.code
= T_OFFSET
;
5858 new_token
.code
= T_ID
;
5863 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5865 intel_parser
.op_string
+= strlen (new_token
.str
);
5866 cur_token
= new_token
;
5869 /* Put cur_token back into the token stream and make cur_token point to
5872 intel_putback_token ()
5874 intel_parser
.op_string
-= strlen (cur_token
.str
);
5875 free (cur_token
.str
);
5876 cur_token
= prev_token
;
5878 /* Forget prev_token. */
5879 prev_token
.code
= T_NIL
;
5880 prev_token
.reg
= NULL
;
5881 prev_token
.str
= NULL
;