opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* AVX2 support required */
  96   CpuAVX2,
  97   /* Intel L1OM support required */
  98   CpuL1OM,
  99   /* Xsave/xrstor New Instructions support required */
 100   CpuXsave,
 101   /* Xsaveopt New Instructions support required */
 102   CpuXsaveopt,
 103   /* AES support required */
 104   CpuAES,
 105   /* PCLMUL support required */
 106   CpuPCLMUL,
 107   /* FMA support required */
 108   CpuFMA,
 109   /* FMA4 support required */
 110   CpuFMA4,
 111   /* XOP support required */
 112   CpuXOP,
 113   /* LWP support required */
 114   CpuLWP,
 115   /* BMI support required */
 116   CpuBMI,
 117   /* TBM support required */
 118   CpuTBM,
 119   /* MOVBE Instruction support required */
 120   CpuMovbe,
 121   /* EPT Instructions required */
 122   CpuEPT,
 123   /* RDTSCP Instruction support required */
 124   CpuRdtscp,
 125   /* FSGSBASE Instructions required */
 126   CpuFSGSBase,
 127   /* RDRND Instructions required */
 128   CpuRdRnd,
 129   /* F16C Instructions required */
 130   CpuF16C,
 131   /* Intel BMI2 support required */
 132   CpuBMI2,
 133   /* LZCNT support required */
 134   CpuLZCNT,
 135   /* INVPCID Instructions required */
 136   CpuINVPCID,
 137   /* 64bit support available, used by -march= in assembler.  */
 138   CpuLM,
 139   /* 64bit support required  */
 140   Cpu64,
 141   /* Not supported in the 64bit mode  */
 142   CpuNo64,
 143   /* The last bitfield in i386_cpu_flags.  */
 144   CpuMax = CpuNo64
 145 };
 146
 147 #define CpuNumOfUints \
 148   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 149 #define CpuNumOfBits \
 150   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 151
 152 /* If you get a compiler error for zero width of the unused field,
 153    comment it out.  */
 154 #define CpuUnused       (CpuMax + 1)
 155
 156 /* We can check if an instruction is available with array instead
 157    of bitfield. */
 158 typedef union i386_cpu_flags
 159 {
 160   struct
 161     {
 162       unsigned int cpui186:1;
 163       unsigned int cpui286:1;
 164       unsigned int cpui386:1;
 165       unsigned int cpui486:1;
 166       unsigned int cpui586:1;
 167       unsigned int cpui686:1;
 168       unsigned int cpuclflush:1;
 169       unsigned int cpunop:1;
 170       unsigned int cpusyscall:1;
 171       unsigned int cpu8087:1;
 172       unsigned int cpu287:1;
 173       unsigned int cpu387:1;
 174       unsigned int cpu687:1;
 175       unsigned int cpufisttp:1;
 176       unsigned int cpummx:1;
 177       unsigned int cpusse:1;
 178       unsigned int cpusse2:1;
 179       unsigned int cpua3dnow:1;
 180       unsigned int cpua3dnowa:1;
 181       unsigned int cpusse3:1;
 182       unsigned int cpupadlock:1;
 183       unsigned int cpusvme:1;
 184       unsigned int cpuvmx:1;
 185       unsigned int cpusmx:1;
 186       unsigned int cpussse3:1;
 187       unsigned int cpusse4a:1;
 188       unsigned int cpuabm:1;
 189       unsigned int cpusse4_1:1;
 190       unsigned int cpusse4_2:1;
 191       unsigned int cpuavx:1;
 192       unsigned int cpuavx2:1;
 193       unsigned int cpul1om:1;
 194       unsigned int cpuxsave:1;
 195       unsigned int cpuxsaveopt:1;
 196       unsigned int cpuaes:1;
 197       unsigned int cpupclmul:1;
 198       unsigned int cpufma:1;
 199       unsigned int cpufma4:1;
 200       unsigned int cpuxop:1;
 201       unsigned int cpulwp:1;
 202       unsigned int cpubmi:1;
 203       unsigned int cputbm:1;
 204       unsigned int cpumovbe:1;
 205       unsigned int cpuept:1;
 206       unsigned int cpurdtscp:1;
 207       unsigned int cpufsgsbase:1;
 208       unsigned int cpurdrnd:1;
 209       unsigned int cpuf16c:1;
 210       unsigned int cpubmi2:1;
 211       unsigned int cpulzcnt:1;
 212       unsigned int cpuinvpcid:1;
 213       unsigned int cpulm:1;
 214       unsigned int cpu64:1;
 215       unsigned int cpuno64:1;
 216 #ifdef CpuUnused
 217       unsigned int unused:(CpuNumOfBits - CpuUnused);
 218 #endif
 219     } bitfield;
 220   unsigned int array[CpuNumOfUints];
 221 } i386_cpu_flags;
 222
 223 /* Position of opcode_modifier bits.  */
 224
 225 enum
 226 {
 227   /* has direction bit. */
 228   D = 0,
 229   /* set if operands can be words or dwords encoded the canonical way */
 230   W,
 231   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 232      operand in encoding.  */
 233   S,
 234   /* insn has a modrm byte. */
 235   Modrm,
 236   /* register is in low 3 bits of opcode */
 237   ShortForm,
 238   /* special case for jump insns.  */
 239   Jump,
 240   /* call and jump */
 241   JumpDword,
 242   /* loop and jecxz */
 243   JumpByte,
 244   /* special case for intersegment leaps/calls */
 245   JumpInterSegment,
 246   /* FP insn memory format bit, sized by 0x4 */
 247   FloatMF,
 248   /* src/dest swap for floats. */
 249   FloatR,
 250   /* has float insn direction bit. */
 251   FloatD,
 252   /* needs size prefix if in 32-bit mode */
 253   Size16,
 254   /* needs size prefix if in 16-bit mode */
 255   Size32,
 256   /* needs size prefix if in 64-bit mode */
 257   Size64,
 258   /* check register size.  */
 259   CheckRegSize,
 260   /* instruction ignores operand size prefix and in Intel mode ignores
 261      mnemonic size suffix check.  */
 262   IgnoreSize,
 263   /* default insn size depends on mode */
 264   DefaultSize,
 265   /* b suffix on instruction illegal */
 266   No_bSuf,
 267   /* w suffix on instruction illegal */
 268   No_wSuf,
 269   /* l suffix on instruction illegal */
 270   No_lSuf,
 271   /* s suffix on instruction illegal */
 272   No_sSuf,
 273   /* q suffix on instruction illegal */
 274   No_qSuf,
 275   /* long double suffix on instruction illegal */
 276   No_ldSuf,
 277   /* instruction needs FWAIT */
 278   FWait,
 279   /* quick test for string instructions */
 280   IsString,
 281   /* quick test for lockable instructions */
 282   IsLockable,
 283   /* fake an extra reg operand for clr, imul and special register
 284      processing for some instructions.  */
 285   RegKludge,
 286   /* The first operand must be xmm0 */
 287   FirstXmm0,
 288   /* An implicit xmm0 as the first operand */
 289   Implicit1stXmm0,
 290   /* Convert to DWORD */
 291   ToDword,
 292   /* Convert to QWORD */
 293   ToQword,
 294   /* Address prefix changes operand 0 */
 295   AddrPrefixOp0,
 296   /* opcode is a prefix */
 297   IsPrefix,
 298   /* instruction has extension in 8 bit imm */
 299   ImmExt,
 300   /* instruction don't need Rex64 prefix.  */
 301   NoRex64,
 302   /* instruction require Rex64 prefix.  */
 303   Rex64,
 304   /* deprecated fp insn, gets a warning */
 305   Ugh,
 306   /* insn has VEX prefix:
 307         1: 128bit VEX prefix.
 308         2: 256bit VEX prefix.
 309         3: Scalar VEX prefix.
 310    */
 311 #define VEX128          1
 312 #define VEX256          2
 313 #define VEXScalar       3
 314   Vex,
 315   /* How to encode VEX.vvvv:
 316      0: VEX.vvvv must be 1111b.
 317      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 318         the content of source registers will be preserved.
 319         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 320         where the content of first source register will be overwritten
 321         by the result.
 322         VEX.NDD2.  The second destination register operand is encoded in
 323         VEX.vvvv for instructions with 2 destination register operands.
 324         For assembler, there are no difference between VEX.NDS, VEX.DDS
 325         and VEX.NDD2.
 326      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 327      instructions with 1 destination register operand.
 328      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 329         of the operands can access a memory location.
 330    */
 331 #define VEXXDS  1
 332 #define VEXNDD  2
 333 #define VEXLWP  3
 334   VexVVVV,
 335   /* How the VEX.W bit is used:
 336      0: Set by the REX.W bit.
 337      1: VEX.W0.  Should always be 0.
 338      2: VEX.W1.  Should always be 1.
 339    */
 340 #define VEXW0   1
 341 #define VEXW1   2
 342   VexW,
 343   /* VEX opcode prefix:
 344      0: VEX 0x0F opcode prefix.
 345      1: VEX 0x0F38 opcode prefix.
 346      2: VEX 0x0F3A opcode prefix
 347      3: XOP 0x08 opcode prefix.
 348      4: XOP 0x09 opcode prefix
 349      5: XOP 0x0A opcode prefix.
 350    */
 351 #define VEX0F           0
 352 #define VEX0F38         1
 353 #define VEX0F3A         2
 354 #define XOP08           3
 355 #define XOP09           4
 356 #define XOP0A           5
 357   VexOpcode,
 358   /* number of VEX source operands:
 359      0: <= 2 source operands.
 360      1: 2 XOP source operands.
 361      2: 3 source operands.
 362    */
 363 #define XOP2SOURCES     1
 364 #define VEX3SOURCES     2
 365   VexSources,
 366   /* instruction has VEX 8 bit imm */
 367   VexImmExt,
 368   /* Instruction with vector SIB byte:
 369         1: 128bit vector register.
 370         2: 256bit vector register.
 371    */
 372 #define VecSIB128       1
 373 #define VecSIB256       2
 374   VecSIB,
 375   /* SSE to AVX support required */
 376   SSE2AVX,
 377   /* No AVX equivalent */
 378   NoAVX,
 379   /* Compatible with old (<= 2.8.1) versions of gcc  */
 380   OldGcc,
 381   /* AT&T mnemonic.  */
 382   ATTMnemonic,
 383   /* AT&T syntax.  */
 384   ATTSyntax,
 385   /* Intel syntax.  */
 386   IntelSyntax,
 387   /* The last bitfield in i386_opcode_modifier.  */
 388   Opcode_Modifier_Max
 389 };
 390
 391 typedef struct i386_opcode_modifier
 392 {
 393   unsigned int d:1;
 394   unsigned int w:1;
 395   unsigned int s:1;
 396   unsigned int modrm:1;
 397   unsigned int shortform:1;
 398   unsigned int jump:1;
 399   unsigned int jumpdword:1;
 400   unsigned int jumpbyte:1;
 401   unsigned int jumpintersegment:1;
 402   unsigned int floatmf:1;
 403   unsigned int floatr:1;
 404   unsigned int floatd:1;
 405   unsigned int size16:1;
 406   unsigned int size32:1;
 407   unsigned int size64:1;
 408   unsigned int checkregsize:1;
 409   unsigned int ignoresize:1;
 410   unsigned int defaultsize:1;
 411   unsigned int no_bsuf:1;
 412   unsigned int no_wsuf:1;
 413   unsigned int no_lsuf:1;
 414   unsigned int no_ssuf:1;
 415   unsigned int no_qsuf:1;
 416   unsigned int no_ldsuf:1;
 417   unsigned int fwait:1;
 418   unsigned int isstring:1;
 419   unsigned int islockable:1;
 420   unsigned int regkludge:1;
 421   unsigned int firstxmm0:1;
 422   unsigned int implicit1stxmm0:1;
 423   unsigned int todword:1;
 424   unsigned int toqword:1;
 425   unsigned int addrprefixop0:1;
 426   unsigned int isprefix:1;
 427   unsigned int immext:1;
 428   unsigned int norex64:1;
 429   unsigned int rex64:1;
 430   unsigned int ugh:1;
 431   unsigned int vex:2;
 432   unsigned int vexvvvv:2;
 433   unsigned int vexw:2;
 434   unsigned int vexopcode:3;
 435   unsigned int vexsources:2;
 436   unsigned int veximmext:1;
 437   unsigned int vecsib:2;
 438   unsigned int sse2avx:1;
 439   unsigned int noavx:1;
 440   unsigned int oldgcc:1;
 441   unsigned int attmnemonic:1;
 442   unsigned int attsyntax:1;
 443   unsigned int intelsyntax:1;
 444 } i386_opcode_modifier;
 445
 446 /* Position of operand_type bits.  */
 447
 448 enum
 449 {
 450   /* 8bit register */
 451   Reg8 = 0,
 452   /* 16bit register */
 453   Reg16,
 454   /* 32bit register */
 455   Reg32,
 456   /* 64bit register */
 457   Reg64,
 458   /* Floating pointer stack register */
 459   FloatReg,
 460   /* MMX register */
 461   RegMMX,
 462   /* SSE register */
 463   RegXMM,
 464   /* AVX registers */
 465   RegYMM,
 466   /* Control register */
 467   Control,
 468   /* Debug register */
 469   Debug,
 470   /* Test register */
 471   Test,
 472   /* 2 bit segment register */
 473   SReg2,
 474   /* 3 bit segment register */
 475   SReg3,
 476   /* 1 bit immediate */
 477   Imm1,
 478   /* 8 bit immediate */
 479   Imm8,
 480   /* 8 bit immediate sign extended */
 481   Imm8S,
 482   /* 16 bit immediate */
 483   Imm16,
 484   /* 32 bit immediate */
 485   Imm32,
 486   /* 32 bit immediate sign extended */
 487   Imm32S,
 488   /* 64 bit immediate */
 489   Imm64,
 490   /* 8bit/16bit/32bit displacements are used in different ways,
 491      depending on the instruction.  For jumps, they specify the
 492      size of the PC relative displacement, for instructions with
 493      memory operand, they specify the size of the offset relative
 494      to the base register, and for instructions with memory offset
 495      such as `mov 1234,%al' they specify the size of the offset
 496      relative to the segment base.  */
 497   /* 8 bit displacement */
 498   Disp8,
 499   /* 16 bit displacement */
 500   Disp16,
 501   /* 32 bit displacement */
 502   Disp32,
 503   /* 32 bit signed displacement */
 504   Disp32S,
 505   /* 64 bit displacement */
 506   Disp64,
 507   /* Accumulator %al/%ax/%eax/%rax */
 508   Acc,
 509   /* Floating pointer top stack register %st(0) */
 510   FloatAcc,
 511   /* Register which can be used for base or index in memory operand.  */
 512   BaseIndex,
 513   /* Register to hold in/out port addr = dx */
 514   InOutPortReg,
 515   /* Register to hold shift count = cl */
 516   ShiftCount,
 517   /* Absolute address for jump.  */
 518   JumpAbsolute,
 519   /* String insn operand with fixed es segment */
 520   EsSeg,
 521   /* RegMem is for instructions with a modrm byte where the register
 522      destination operand should be encoded in the mod and regmem fields.
 523      Normally, it will be encoded in the reg field. We add a RegMem
 524      flag to the destination register operand to indicate that it should
 525      be encoded in the regmem field.  */
 526   RegMem,
 527   /* Memory.  */
 528   Mem,
 529   /* BYTE memory. */
 530   Byte,
 531   /* WORD memory. 2 byte */
 532   Word,
 533   /* DWORD memory. 4 byte */
 534   Dword,
 535   /* FWORD memory. 6 byte */
 536   Fword,
 537   /* QWORD memory. 8 byte */
 538   Qword,
 539   /* TBYTE memory. 10 byte */
 540   Tbyte,
 541   /* XMMWORD memory. */
 542   Xmmword,
 543   /* YMMWORD memory. */
 544   Ymmword,
 545   /* Unspecified memory size.  */
 546   Unspecified,
 547   /* Any memory size.  */
 548   Anysize,
 549
 550   /* Vector 4 bit immediate.  */
 551   Vec_Imm4,
 552
 553   /* The last bitfield in i386_operand_type.  */
 554   OTMax
 555 };
 556
 557 #define OTNumOfUints \
 558   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 559 #define OTNumOfBits \
 560   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 561
 562 /* If you get a compiler error for zero width of the unused field,
 563    comment it out.  */
 564 #define OTUnused                (OTMax + 1)
 565
 566 typedef union i386_operand_type
 567 {
 568   struct
 569     {
 570       unsigned int reg8:1;
 571       unsigned int reg16:1;
 572       unsigned int reg32:1;
 573       unsigned int reg64:1;
 574       unsigned int floatreg:1;
 575       unsigned int regmmx:1;
 576       unsigned int regxmm:1;
 577       unsigned int regymm:1;
 578       unsigned int control:1;
 579       unsigned int debug:1;
 580       unsigned int test:1;
 581       unsigned int sreg2:1;
 582       unsigned int sreg3:1;
 583       unsigned int imm1:1;
 584       unsigned int imm8:1;
 585       unsigned int imm8s:1;
 586       unsigned int imm16:1;
 587       unsigned int imm32:1;
 588       unsigned int imm32s:1;
 589       unsigned int imm64:1;
 590       unsigned int disp8:1;
 591       unsigned int disp16:1;
 592       unsigned int disp32:1;
 593       unsigned int disp32s:1;
 594       unsigned int disp64:1;
 595       unsigned int acc:1;
 596       unsigned int floatacc:1;
 597       unsigned int baseindex:1;
 598       unsigned int inoutportreg:1;
 599       unsigned int shiftcount:1;
 600       unsigned int jumpabsolute:1;
 601       unsigned int esseg:1;
 602       unsigned int regmem:1;
 603       unsigned int mem:1;
 604       unsigned int byte:1;
 605       unsigned int word:1;
 606       unsigned int dword:1;
 607       unsigned int fword:1;
 608       unsigned int qword:1;
 609       unsigned int tbyte:1;
 610       unsigned int xmmword:1;
 611       unsigned int ymmword:1;
 612       unsigned int unspecified:1;
 613       unsigned int anysize:1;
 614       unsigned int vec_imm4:1;
 615 #ifdef OTUnused
 616       unsigned int unused:(OTNumOfBits - OTUnused);
 617 #endif
 618     } bitfield;
 619   unsigned int array[OTNumOfUints];
 620 } i386_operand_type;
 621
 622 typedef struct insn_template
 623 {
 624   /* instruction name sans width suffix ("mov" for movl insns) */
 625   char *name;
 626
 627   /* how many operands */
 628   unsigned int operands;
 629
 630   /* base_opcode is the fundamental opcode byte without optional
 631      prefix(es).  */
 632   unsigned int base_opcode;
 633 #define Opcode_D        0x2 /* Direction bit:
 634                                set if Reg --> Regmem;
 635                                unset if Regmem --> Reg. */
 636 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 637 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 638
 639   /* extension_opcode is the 3 bit extension for group <n> insns.
 640      This field is also used to store the 8-bit opcode suffix for the
 641      AMD 3DNow! instructions.
 642      If this template has no extension opcode (the usual case) use None
 643      Instructions */
 644   unsigned int extension_opcode;
 645 #define None 0xffff             /* If no extension_opcode is possible.  */
 646
 647   /* Opcode length.  */
 648   unsigned char opcode_length;
 649
 650   /* cpu feature flags */
 651   i386_cpu_flags cpu_flags;
 652
 653   /* the bits in opcode_modifier are used to generate the final opcode from
 654      the base_opcode.  These bits also are used to detect alternate forms of
 655      the same instruction */
 656   i386_opcode_modifier opcode_modifier;
 657
 658   /* operand_types[i] describes the type of operand i.  This is made
 659      by OR'ing together all of the possible type masks.  (e.g.
 660      'operand_types[i] = Reg|Imm' specifies that operand i can be
 661      either a register or an immediate operand.  */
 662   i386_operand_type operand_types[MAX_OPERANDS];
 663 }
 664 insn_template;
 665
 666 extern const insn_template i386_optab[];
 667
 668 /* these are for register name --> number & type hash lookup */
 669 typedef struct
 670 {
 671   char *reg_name;
 672   i386_operand_type reg_type;
 673   unsigned char reg_flags;
 674 #define RegRex      0x1  /* Extended register.  */
 675 #define RegRex64    0x2  /* Extended 8 bit register.  */
 676   unsigned char reg_num;
 677 #define RegRip  ((unsigned char ) ~0)
 678 #define RegEip  (RegRip - 1)
 679 /* EIZ and RIZ are fake index registers.  */
 680 #define RegEiz  (RegEip - 1)
 681 #define RegRiz  (RegEiz - 1)
 682 /* FLAT is a fake segment register (Intel mode).  */
 683 #define RegFlat     ((unsigned char) ~0)
 684   signed char dw2_regnum[2];
 685 #define Dw2Inval (-1)
 686 }
 687 reg_entry;
 688
 689 /* Entries in i386_regtab.  */
 690 #define REGNAM_AL 1
 691 #define REGNAM_AX 25
 692 #define REGNAM_EAX 41
 693
 694 extern const reg_entry i386_regtab[];
 695 extern const unsigned int i386_regtab_size;
 696
 697 typedef struct
 698 {
 699   char *seg_name;
 700   unsigned int seg_prefix;
 701 }
 702 seg_entry;
 703
 704 extern const seg_entry cs;
 705 extern const seg_entry ds;
 706 extern const seg_entry ss;
 707 extern const seg_entry es;
 708 extern const seg_entry fs;
 709 extern const seg_entry gs;