* m32c-desc.c: Regenerate.
[binutils.git] / opcodes / m32c-desc.c
blobe38828ebdcb5055573e00271a1389b5069b0ffde
1 /* CPU data for m32c.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2005 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
25 #include "sysdep.h"
26 #include <stdio.h>
27 #include <stdarg.h>
28 #include "ansidecl.h"
29 #include "bfd.h"
30 #include "symcat.h"
31 #include "m32c-desc.h"
32 #include "m32c-opc.h"
33 #include "opintl.h"
34 #include "libiberty.h"
35 #include "xregex.h"
37 /* Attributes. */
39 static const CGEN_ATTR_ENTRY bool_attr[] =
41 { "#f", 0 },
42 { "#t", 1 },
43 { 0, 0 }
46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
48 { "base", MACH_BASE },
49 { "m16c", MACH_M16C },
50 { "m32c", MACH_M32C },
51 { "max", MACH_MAX },
52 { 0, 0 }
55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
57 { "m16c", ISA_M16C },
58 { "m32c", ISA_M32C },
59 { "max", ISA_MAX },
60 { 0, 0 }
63 const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[] =
65 { "MACH", & MACH_attr[0], & MACH_attr[0] },
66 { "ISA", & ISA_attr[0], & ISA_attr[0] },
67 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
68 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
69 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
70 { "RESERVED", &bool_attr[0], &bool_attr[0] },
71 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
72 { "SIGNED", &bool_attr[0], &bool_attr[0] },
73 { 0, 0, 0 }
76 const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[] =
78 { "MACH", & MACH_attr[0], & MACH_attr[0] },
79 { "ISA", & ISA_attr[0], & ISA_attr[0] },
80 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
81 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
82 { "PC", &bool_attr[0], &bool_attr[0] },
83 { "PROFILE", &bool_attr[0], &bool_attr[0] },
84 { 0, 0, 0 }
87 const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[] =
89 { "MACH", & MACH_attr[0], & MACH_attr[0] },
90 { "ISA", & ISA_attr[0], & ISA_attr[0] },
91 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
92 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
93 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
94 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
95 { "SIGNED", &bool_attr[0], &bool_attr[0] },
96 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
97 { "RELAX", &bool_attr[0], &bool_attr[0] },
98 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
99 { 0, 0, 0 }
102 const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[] =
104 { "MACH", & MACH_attr[0], & MACH_attr[0] },
105 { "ISA", & ISA_attr[0], & ISA_attr[0] },
106 { "ALIAS", &bool_attr[0], &bool_attr[0] },
107 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
108 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
109 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
110 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
111 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
112 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
113 { "RELAXED", &bool_attr[0], &bool_attr[0] },
114 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
115 { "PBB", &bool_attr[0], &bool_attr[0] },
116 { 0, 0, 0 }
119 /* Instruction set variants. */
121 static const CGEN_ISA m32c_cgen_isa_table[] = {
122 { "m16c", 32, 32, 8, 56 },
123 { "m32c", 32, 32, 8, 80 },
124 { 0, 0, 0, 0, 0 }
127 /* Machine variants. */
129 static const CGEN_MACH m32c_cgen_mach_table[] = {
130 { "m16c", "m16c", MACH_M16C, 0 },
131 { "m32c", "m32c", MACH_M32C, 0 },
132 { 0, 0, 0, 0 }
135 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] =
137 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
138 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
139 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
140 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
143 CGEN_KEYWORD m32c_cgen_opval_h_gr =
145 & m32c_cgen_opval_h_gr_entries[0],
147 0, 0, 0, 0, ""
150 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] =
152 { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
153 { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 },
154 { "r1l", 2, {0, {{{0, 0}}}}, 0, 0 },
155 { "r1h", 3, {0, {{{0, 0}}}}, 0, 0 }
158 CGEN_KEYWORD m32c_cgen_opval_h_gr_QI =
160 & m32c_cgen_opval_h_gr_QI_entries[0],
162 0, 0, 0, 0, ""
165 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] =
167 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
168 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
169 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
170 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
173 CGEN_KEYWORD m32c_cgen_opval_h_gr_HI =
175 & m32c_cgen_opval_h_gr_HI_entries[0],
177 0, 0, 0, 0, ""
180 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] =
182 { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 },
183 { "r3r1", 1, {0, {{{0, 0}}}}, 0, 0 }
186 CGEN_KEYWORD m32c_cgen_opval_h_gr_SI =
188 & m32c_cgen_opval_h_gr_SI_entries[0],
190 0, 0, 0, 0, ""
193 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] =
195 { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
196 { "r1l", 1, {0, {{{0, 0}}}}, 0, 0 }
199 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI =
201 & m32c_cgen_opval_h_gr_ext_QI_entries[0],
203 0, 0, 0, 0, ""
206 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] =
208 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
209 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }
212 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI =
214 & m32c_cgen_opval_h_gr_ext_HI_entries[0],
216 0, 0, 0, 0, ""
219 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] =
221 { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }
224 CGEN_KEYWORD m32c_cgen_opval_h_r0l =
226 & m32c_cgen_opval_h_r0l_entries[0],
228 0, 0, 0, 0, ""
231 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] =
233 { "r0h", 0, {0, {{{0, 0}}}}, 0, 0 }
236 CGEN_KEYWORD m32c_cgen_opval_h_r0h =
238 & m32c_cgen_opval_h_r0h_entries[0],
240 0, 0, 0, 0, ""
243 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] =
245 { "r1l", 0, {0, {{{0, 0}}}}, 0, 0 }
248 CGEN_KEYWORD m32c_cgen_opval_h_r1l =
250 & m32c_cgen_opval_h_r1l_entries[0],
252 0, 0, 0, 0, ""
255 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] =
257 { "r1h", 0, {0, {{{0, 0}}}}, 0, 0 }
260 CGEN_KEYWORD m32c_cgen_opval_h_r1h =
262 & m32c_cgen_opval_h_r1h_entries[0],
264 0, 0, 0, 0, ""
267 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] =
269 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }
272 CGEN_KEYWORD m32c_cgen_opval_h_r0 =
274 & m32c_cgen_opval_h_r0_entries[0],
276 0, 0, 0, 0, ""
279 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] =
281 { "r1", 0, {0, {{{0, 0}}}}, 0, 0 }
284 CGEN_KEYWORD m32c_cgen_opval_h_r1 =
286 & m32c_cgen_opval_h_r1_entries[0],
288 0, 0, 0, 0, ""
291 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] =
293 { "r2", 0, {0, {{{0, 0}}}}, 0, 0 }
296 CGEN_KEYWORD m32c_cgen_opval_h_r2 =
298 & m32c_cgen_opval_h_r2_entries[0],
300 0, 0, 0, 0, ""
303 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] =
305 { "r3", 0, {0, {{{0, 0}}}}, 0, 0 }
308 CGEN_KEYWORD m32c_cgen_opval_h_r3 =
310 & m32c_cgen_opval_h_r3_entries[0],
312 0, 0, 0, 0, ""
315 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] =
317 { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
318 { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 }
321 CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h =
323 & m32c_cgen_opval_h_r0l_r0h_entries[0],
325 0, 0, 0, 0, ""
328 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] =
330 { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
333 CGEN_KEYWORD m32c_cgen_opval_h_r2r0 =
335 & m32c_cgen_opval_h_r2r0_entries[0],
337 0, 0, 0, 0, ""
340 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] =
342 { "r3r1", 0, {0, {{{0, 0}}}}, 0, 0 }
345 CGEN_KEYWORD m32c_cgen_opval_h_r3r1 =
347 & m32c_cgen_opval_h_r3r1_entries[0],
349 0, 0, 0, 0, ""
352 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] =
354 { "r1r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
357 CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 =
359 & m32c_cgen_opval_h_r1r2r0_entries[0],
361 0, 0, 0, 0, ""
364 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] =
366 { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
367 { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
370 CGEN_KEYWORD m32c_cgen_opval_h_ar =
372 & m32c_cgen_opval_h_ar_entries[0],
374 0, 0, 0, 0, ""
377 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] =
379 { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
380 { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
383 CGEN_KEYWORD m32c_cgen_opval_h_ar_QI =
385 & m32c_cgen_opval_h_ar_QI_entries[0],
387 0, 0, 0, 0, ""
390 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] =
392 { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
393 { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
396 CGEN_KEYWORD m32c_cgen_opval_h_ar_HI =
398 & m32c_cgen_opval_h_ar_HI_entries[0],
400 0, 0, 0, 0, ""
403 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] =
405 { "a1a0", 0, {0, {{{0, 0}}}}, 0, 0 }
408 CGEN_KEYWORD m32c_cgen_opval_h_ar_SI =
410 & m32c_cgen_opval_h_ar_SI_entries[0],
412 0, 0, 0, 0, ""
415 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] =
417 { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }
420 CGEN_KEYWORD m32c_cgen_opval_h_a0 =
422 & m32c_cgen_opval_h_a0_entries[0],
424 0, 0, 0, 0, ""
427 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] =
429 { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
432 CGEN_KEYWORD m32c_cgen_opval_h_a1 =
434 & m32c_cgen_opval_h_a1_entries[0],
436 0, 0, 0, 0, ""
439 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] =
441 { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
442 { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
443 { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
444 { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
445 { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
446 { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
447 { "le", 4, {0, {{{0, 0}}}}, 0, 0 },
448 { "o", 5, {0, {{{0, 0}}}}, 0, 0 },
449 { "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
450 { "ltu", 248, {0, {{{0, 0}}}}, 0, 0 },
451 { "nc", 248, {0, {{{0, 0}}}}, 0, 0 },
452 { "leu", 249, {0, {{{0, 0}}}}, 0, 0 },
453 { "ne", 250, {0, {{{0, 0}}}}, 0, 0 },
454 { "nz", 250, {0, {{{0, 0}}}}, 0, 0 },
455 { "pz", 251, {0, {{{0, 0}}}}, 0, 0 },
456 { "gt", 252, {0, {{{0, 0}}}}, 0, 0 },
457 { "no", 253, {0, {{{0, 0}}}}, 0, 0 },
458 { "lt", 254, {0, {{{0, 0}}}}, 0, 0 }
461 CGEN_KEYWORD m32c_cgen_opval_h_cond16 =
463 & m32c_cgen_opval_h_cond16_entries[0],
465 0, 0, 0, 0, ""
468 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] =
470 { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
471 { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
472 { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
473 { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
474 { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
475 { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
476 { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
477 { "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
478 { "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
479 { "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
480 { "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
481 { "pz", 7, {0, {{{0, 0}}}}, 0, 0 },
482 { "le", 8, {0, {{{0, 0}}}}, 0, 0 },
483 { "o", 9, {0, {{{0, 0}}}}, 0, 0 },
484 { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
485 { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
486 { "no", 13, {0, {{{0, 0}}}}, 0, 0 },
487 { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
490 CGEN_KEYWORD m32c_cgen_opval_h_cond16c =
492 & m32c_cgen_opval_h_cond16c_entries[0],
494 0, 0, 0, 0, ""
497 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] =
499 { "le", 8, {0, {{{0, 0}}}}, 0, 0 },
500 { "o", 9, {0, {{{0, 0}}}}, 0, 0 },
501 { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
502 { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
503 { "no", 13, {0, {{{0, 0}}}}, 0, 0 },
504 { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
507 CGEN_KEYWORD m32c_cgen_opval_h_cond16j =
509 & m32c_cgen_opval_h_cond16j_entries[0],
511 0, 0, 0, 0, ""
514 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] =
516 { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
517 { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
518 { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
519 { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
520 { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
521 { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
522 { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
523 { "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
524 { "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
525 { "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
526 { "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
527 { "pz", 7, {0, {{{0, 0}}}}, 0, 0 }
530 CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 =
532 & m32c_cgen_opval_h_cond16j_5_entries[0],
534 0, 0, 0, 0, ""
537 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] =
539 { "ltu", 0, {0, {{{0, 0}}}}, 0, 0 },
540 { "nc", 0, {0, {{{0, 0}}}}, 0, 0 },
541 { "leu", 1, {0, {{{0, 0}}}}, 0, 0 },
542 { "ne", 2, {0, {{{0, 0}}}}, 0, 0 },
543 { "nz", 2, {0, {{{0, 0}}}}, 0, 0 },
544 { "pz", 3, {0, {{{0, 0}}}}, 0, 0 },
545 { "no", 4, {0, {{{0, 0}}}}, 0, 0 },
546 { "gt", 5, {0, {{{0, 0}}}}, 0, 0 },
547 { "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
548 { "geu", 8, {0, {{{0, 0}}}}, 0, 0 },
549 { "c", 8, {0, {{{0, 0}}}}, 0, 0 },
550 { "gtu", 9, {0, {{{0, 0}}}}, 0, 0 },
551 { "eq", 10, {0, {{{0, 0}}}}, 0, 0 },
552 { "z", 10, {0, {{{0, 0}}}}, 0, 0 },
553 { "n", 11, {0, {{{0, 0}}}}, 0, 0 },
554 { "o", 12, {0, {{{0, 0}}}}, 0, 0 },
555 { "le", 13, {0, {{{0, 0}}}}, 0, 0 },
556 { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
559 CGEN_KEYWORD m32c_cgen_opval_h_cond32 =
561 & m32c_cgen_opval_h_cond32_entries[0],
563 0, 0, 0, 0, ""
566 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] =
568 { "dct0", 0, {0, {{{0, 0}}}}, 0, 0 },
569 { "dct1", 1, {0, {{{0, 0}}}}, 0, 0 },
570 { "flg", 2, {0, {{{0, 0}}}}, 0, 0 },
571 { "svf", 3, {0, {{{0, 0}}}}, 0, 0 },
572 { "drc0", 4, {0, {{{0, 0}}}}, 0, 0 },
573 { "drc1", 5, {0, {{{0, 0}}}}, 0, 0 },
574 { "dmd0", 6, {0, {{{0, 0}}}}, 0, 0 },
575 { "dmd1", 7, {0, {{{0, 0}}}}, 0, 0 }
578 CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 =
580 & m32c_cgen_opval_h_cr1_32_entries[0],
582 0, 0, 0, 0, ""
585 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] =
587 { "intb", 0, {0, {{{0, 0}}}}, 0, 0 },
588 { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
589 { "sb", 2, {0, {{{0, 0}}}}, 0, 0 },
590 { "fb", 3, {0, {{{0, 0}}}}, 0, 0 },
591 { "svp", 4, {0, {{{0, 0}}}}, 0, 0 },
592 { "vct", 5, {0, {{{0, 0}}}}, 0, 0 },
593 { "isp", 7, {0, {{{0, 0}}}}, 0, 0 }
596 CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 =
598 & m32c_cgen_opval_h_cr2_32_entries[0],
600 0, 0, 0, 0, ""
603 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] =
605 { "dma0", 2, {0, {{{0, 0}}}}, 0, 0 },
606 { "dma1", 3, {0, {{{0, 0}}}}, 0, 0 },
607 { "dra0", 4, {0, {{{0, 0}}}}, 0, 0 },
608 { "dra1", 5, {0, {{{0, 0}}}}, 0, 0 },
609 { "dsa0", 6, {0, {{{0, 0}}}}, 0, 0 },
610 { "dsa1", 7, {0, {{{0, 0}}}}, 0, 0 }
613 CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 =
615 & m32c_cgen_opval_h_cr3_32_entries[0],
617 0, 0, 0, 0, ""
620 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] =
622 { "intbl", 1, {0, {{{0, 0}}}}, 0, 0 },
623 { "intbh", 2, {0, {{{0, 0}}}}, 0, 0 },
624 { "flg", 3, {0, {{{0, 0}}}}, 0, 0 },
625 { "isp", 4, {0, {{{0, 0}}}}, 0, 0 },
626 { "sp", 5, {0, {{{0, 0}}}}, 0, 0 },
627 { "sb", 6, {0, {{{0, 0}}}}, 0, 0 },
628 { "fb", 7, {0, {{{0, 0}}}}, 0, 0 }
631 CGEN_KEYWORD m32c_cgen_opval_h_cr_16 =
633 & m32c_cgen_opval_h_cr_16_entries[0],
635 0, 0, 0, 0, ""
638 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] =
640 { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
641 { "d", 1, {0, {{{0, 0}}}}, 0, 0 },
642 { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
643 { "s", 3, {0, {{{0, 0}}}}, 0, 0 },
644 { "b", 4, {0, {{{0, 0}}}}, 0, 0 },
645 { "o", 5, {0, {{{0, 0}}}}, 0, 0 },
646 { "i", 6, {0, {{{0, 0}}}}, 0, 0 },
647 { "u", 7, {0, {{{0, 0}}}}, 0, 0 }
650 CGEN_KEYWORD m32c_cgen_opval_h_flags =
652 & m32c_cgen_opval_h_flags_entries[0],
654 0, 0, 0, 0, ""
657 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] =
659 { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
660 { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
661 { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
662 { "4", 3, {0, {{{0, 0}}}}, 0, 0 },
663 { "5", 4, {0, {{{0, 0}}}}, 0, 0 },
664 { "6", 5, {0, {{{0, 0}}}}, 0, 0 },
665 { "7", 6, {0, {{{0, 0}}}}, 0, 0 },
666 { "8", 7, {0, {{{0, 0}}}}, 0, 0 },
667 { "-1", -8, {0, {{{0, 0}}}}, 0, 0 },
668 { "-2", -7, {0, {{{0, 0}}}}, 0, 0 },
669 { "-3", -6, {0, {{{0, 0}}}}, 0, 0 },
670 { "-4", -5, {0, {{{0, 0}}}}, 0, 0 },
671 { "-5", -4, {0, {{{0, 0}}}}, 0, 0 },
672 { "-6", -3, {0, {{{0, 0}}}}, 0, 0 },
673 { "-7", -2, {0, {{{0, 0}}}}, 0, 0 },
674 { "-8", -1, {0, {{{0, 0}}}}, 0, 0 }
677 CGEN_KEYWORD m32c_cgen_opval_h_shimm =
679 & m32c_cgen_opval_h_shimm_entries[0],
681 0, 0, 0, 0, ""
685 /* The hardware table. */
687 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
688 #define A(a) (1 << CGEN_HW_##a)
689 #else
690 #define A(a) (1 << CGEN_HW_/**/a)
691 #endif
693 const CGEN_HW_ENTRY m32c_cgen_hw_table[] =
695 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
696 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
697 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
698 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
699 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
700 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
701 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
702 { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
703 { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
704 { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
705 { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
706 { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
707 { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
708 { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
709 { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
710 { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
711 { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
712 { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
713 { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
714 { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
715 { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
716 { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
717 { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
718 { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
719 { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
720 { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
721 { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
722 { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
723 { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
724 { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
725 { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
726 { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
727 { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
728 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
729 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
730 { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
731 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
732 { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
733 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
734 { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
735 { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
736 { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
737 { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
738 { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
739 { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
740 { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
741 { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
742 { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
743 { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
744 { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
745 { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
746 { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
747 { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
748 { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
749 { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
750 { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
751 { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
752 { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
753 { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
754 { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
755 { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
756 { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
757 { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
758 { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
759 { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
760 { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
761 { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
762 { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
763 { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
764 { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
765 { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
766 { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
767 { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
768 { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
769 { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
770 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
773 #undef A
776 /* The instruction field table. */
778 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
779 #define A(a) (1 << CGEN_IFLD_##a)
780 #else
781 #define A(a) (1 << CGEN_IFLD_/**/a)
782 #endif
784 const CGEN_IFLD m32c_cgen_ifld_table[] =
786 { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
787 { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
788 { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
789 { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
790 { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
791 { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
792 { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
793 { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
794 { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
795 { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
796 { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
797 { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
798 { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
799 { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
800 { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
801 { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
802 { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
803 { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
804 { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
805 { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
806 { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
807 { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
808 { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
809 { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
810 { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
811 { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
812 { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
813 { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
814 { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
815 { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
816 { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
817 { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
818 { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
819 { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
820 { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
821 { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
822 { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
823 { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
824 { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
825 { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
826 { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
827 { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
828 { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
829 { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
830 { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
831 { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
832 { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
833 { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
834 { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
835 { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
836 { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
837 { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
838 { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
839 { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
840 { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
841 { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
842 { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
843 { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
844 { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
845 { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
846 { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
847 { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
848 { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
849 { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
850 { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
851 { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
852 { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
853 { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
854 { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
855 { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
856 { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
857 { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
858 { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
859 { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
860 { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
861 { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
862 { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
863 { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
864 { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
865 { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
866 { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
867 { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
868 { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
869 { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
870 { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
871 { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
872 { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
873 { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
874 { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
875 { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
876 { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
877 { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
878 { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
879 { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
880 { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
881 { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
882 { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
883 { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
884 { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
885 { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
886 { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
887 { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
888 { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
889 { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
890 { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
891 { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
892 { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
893 { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
894 { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
895 { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
896 { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
897 { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
898 { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
899 { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
900 { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
901 { M32C_F_DSP_8_S24, "f-dsp-8-s24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
902 { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
903 { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
904 { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
905 { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
906 { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
907 { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
908 { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
909 { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
910 { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
911 { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
912 { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
913 { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
914 { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
915 { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
916 { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
917 { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
918 { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
919 { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
920 { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
921 { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
922 { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
923 { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
924 { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
925 { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
926 { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
927 { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
928 { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
929 { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
930 { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
931 { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
932 { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
933 { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
934 { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
935 { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
936 { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
937 { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
938 { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
939 { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
940 { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
941 { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
942 { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
943 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
946 #undef A
950 /* multi ifield declarations */
952 const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [];
953 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [];
954 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [];
955 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [];
956 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [];
957 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [];
958 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [];
959 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [];
960 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [];
961 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [];
962 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [];
963 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [];
964 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [];
965 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [];
966 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [];
967 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [];
968 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [];
969 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [];
970 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [];
971 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [];
972 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [];
973 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [];
974 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [];
975 const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [];
976 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [];
977 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [];
980 /* multi ifield definitions */
982 const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [] =
984 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
985 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
986 { 0, { (const PTR) 0 } }
988 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [] =
990 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
991 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
992 { 0, { (const PTR) 0 } }
994 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [] =
996 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
997 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
998 { 0, { (const PTR) 0 } }
1000 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [] =
1002 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1003 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1004 { 0, { (const PTR) 0 } }
1006 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [] =
1008 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1009 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1010 { 0, { (const PTR) 0 } }
1012 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [] =
1014 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
1015 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1016 { 0, { (const PTR) 0 } }
1018 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [] =
1020 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1021 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1022 { 0, { (const PTR) 0 } }
1024 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [] =
1026 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1027 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1028 { 0, { (const PTR) 0 } }
1030 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [] =
1032 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1033 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1034 { 0, { (const PTR) 0 } }
1036 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [] =
1038 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1039 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1040 { 0, { (const PTR) 0 } }
1042 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [] =
1044 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1045 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1046 { 0, { (const PTR) 0 } }
1048 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [] =
1050 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_U8] } },
1051 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1052 { 0, { (const PTR) 0 } }
1054 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [] =
1056 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO16_S] } },
1057 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
1058 { 0, { (const PTR) 0 } }
1060 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [] =
1062 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1063 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1064 { 0, { (const PTR) 0 } }
1066 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [] =
1068 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1069 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1070 { 0, { (const PTR) 0 } }
1072 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [] =
1074 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1075 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1076 { 0, { (const PTR) 0 } }
1078 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [] =
1080 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1081 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1082 { 0, { (const PTR) 0 } }
1084 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [] =
1086 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1087 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1088 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1089 { 0, { (const PTR) 0 } }
1091 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [] =
1093 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1094 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1095 { 0, { (const PTR) 0 } }
1097 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [] =
1099 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1100 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1101 { 0, { (const PTR) 0 } }
1103 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [] =
1105 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1106 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1107 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1108 { 0, { (const PTR) 0 } }
1110 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [] =
1112 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1113 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1114 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1115 { 0, { (const PTR) 0 } }
1117 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [] =
1119 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1120 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1121 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1122 { 0, { (const PTR) 0 } }
1124 const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [] =
1126 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
1127 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1128 { 0, { (const PTR) 0 } }
1130 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [] =
1132 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_1] } },
1133 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1134 { 0, { (const PTR) 0 } }
1136 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [] =
1138 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_1_3] } },
1139 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1140 { 0, { (const PTR) 0 } }
1143 /* The operand table. */
1145 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1146 #define A(a) (1 << CGEN_OPERAND_##a)
1147 #else
1148 #define A(a) (1 << CGEN_OPERAND_/**/a)
1149 #endif
1150 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1151 #define OPERAND(op) M32C_OPERAND_##op
1152 #else
1153 #define OPERAND(op) M32C_OPERAND_/**/op
1154 #endif
1156 const CGEN_OPERAND m32c_cgen_operand_table[] =
1158 /* pc: program counter */
1159 { "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0,
1160 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } },
1161 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1162 /* Src16RnQI: general register QI view */
1163 { "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2,
1164 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
1165 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1166 /* Src16RnHI: general register QH view */
1167 { "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2,
1168 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
1169 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1170 /* Src32RnUnprefixedQI: general register QI view */
1171 { "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2,
1172 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } },
1173 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1174 /* Src32RnUnprefixedHI: general register HI view */
1175 { "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2,
1176 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } },
1177 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1178 /* Src32RnUnprefixedSI: general register SI view */
1179 { "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2,
1180 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } },
1181 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1182 /* Src32RnPrefixedQI: general register QI view */
1183 { "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2,
1184 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } },
1185 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1186 /* Src32RnPrefixedHI: general register HI view */
1187 { "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2,
1188 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } },
1189 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1190 /* Src32RnPrefixedSI: general register SI view */
1191 { "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2,
1192 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } },
1193 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1194 /* Src16An: address register */
1195 { "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1,
1196 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1197 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1198 /* Src16AnQI: address register QI view */
1199 { "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1,
1200 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1201 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1202 /* Src16AnHI: address register HI view */
1203 { "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1,
1204 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1205 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1206 /* Src32AnUnprefixed: address register */
1207 { "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1,
1208 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1209 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1210 /* Src32AnUnprefixedQI: address register QI view */
1211 { "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1,
1212 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1213 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1214 /* Src32AnUnprefixedHI: address register HI view */
1215 { "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1,
1216 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1217 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1218 /* Src32AnUnprefixedSI: address register SI view */
1219 { "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1,
1220 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1221 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1222 /* Src32AnPrefixed: address register */
1223 { "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1,
1224 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1225 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1226 /* Src32AnPrefixedQI: address register QI view */
1227 { "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1,
1228 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1229 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1230 /* Src32AnPrefixedHI: address register HI view */
1231 { "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1,
1232 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1233 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1234 /* Src32AnPrefixedSI: address register SI view */
1235 { "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1,
1236 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1237 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1238 /* Dst16RnQI: general register QI view */
1239 { "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2,
1240 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1241 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1242 /* Dst16RnHI: general register HI view */
1243 { "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2,
1244 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1245 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1246 /* Dst16RnSI: general register SI view */
1247 { "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2,
1248 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1249 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1250 /* Dst16RnExtQI: general register QI/HI view for 'ext' insns */
1251 { "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1,
1252 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } },
1253 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1254 /* Dst32R0QI-S: general register QI view */
1255 { "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0,
1256 { 0, { (const PTR) 0 } },
1257 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1258 /* Dst32R0HI-S: general register HI view */
1259 { "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0,
1260 { 0, { (const PTR) 0 } },
1261 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1262 /* Dst32RnUnprefixedQI: general register QI view */
1263 { "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2,
1264 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
1265 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1266 /* Dst32RnUnprefixedHI: general register HI view */
1267 { "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2,
1268 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } },
1269 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1270 /* Dst32RnUnprefixedSI: general register SI view */
1271 { "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2,
1272 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } },
1273 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1274 /* Dst32RnExtUnprefixedQI: general register QI view */
1275 { "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1,
1276 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
1277 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1278 /* Dst32RnExtUnprefixedHI: general register HI view */
1279 { "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1,
1280 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
1281 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1282 /* Dst32RnPrefixedQI: general register QI view */
1283 { "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2,
1284 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
1285 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1286 /* Dst32RnPrefixedHI: general register HI view */
1287 { "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2,
1288 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } },
1289 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1290 /* Dst32RnPrefixedSI: general register SI view */
1291 { "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2,
1292 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } },
1293 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1294 /* Dst16RnQI-S: general register QI view */
1295 { "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1,
1296 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
1297 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1298 /* Dst16AnQI-S: address register QI view */
1299 { "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1,
1300 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
1301 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1302 /* Bit16Rn: general register bit view */
1303 { "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2,
1304 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1305 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1306 /* Bit32RnPrefixed: general register bit view */
1307 { "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2,
1308 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
1309 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1310 /* Bit32RnUnprefixed: general register bit view */
1311 { "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2,
1312 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
1313 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1314 /* R0: r0 */
1315 { "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0,
1316 { 0, { (const PTR) 0 } },
1317 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1318 /* R1: r1 */
1319 { "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0,
1320 { 0, { (const PTR) 0 } },
1321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1322 /* R2: r2 */
1323 { "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0,
1324 { 0, { (const PTR) 0 } },
1325 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1326 /* R3: r3 */
1327 { "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0,
1328 { 0, { (const PTR) 0 } },
1329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1330 /* R0l: r0l */
1331 { "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0,
1332 { 0, { (const PTR) 0 } },
1333 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1334 /* R0h: r0h */
1335 { "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0,
1336 { 0, { (const PTR) 0 } },
1337 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1338 /* R2R0: r2r0 */
1339 { "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0,
1340 { 0, { (const PTR) 0 } },
1341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1342 /* R3R1: r3r1 */
1343 { "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0,
1344 { 0, { (const PTR) 0 } },
1345 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1346 /* R1R2R0: r1r2r0 */
1347 { "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0,
1348 { 0, { (const PTR) 0 } },
1349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1350 /* Dst16An: address register */
1351 { "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1,
1352 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1353 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1354 /* Dst16AnQI: address register QI view */
1355 { "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1,
1356 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1357 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1358 /* Dst16AnHI: address register HI view */
1359 { "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1,
1360 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1361 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1362 /* Dst16AnSI: address register SI view */
1363 { "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1,
1364 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1365 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1366 /* Dst16An-S: address register HI view */
1367 { "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1,
1368 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } },
1369 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1370 /* Dst32AnUnprefixed: address register */
1371 { "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1,
1372 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1373 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1374 /* Dst32AnUnprefixedQI: address register QI view */
1375 { "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1,
1376 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1377 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1378 /* Dst32AnUnprefixedHI: address register HI view */
1379 { "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1,
1380 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1381 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1382 /* Dst32AnUnprefixedSI: address register SI view */
1383 { "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1,
1384 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1385 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1386 /* Dst32AnExtUnprefixed: address register */
1387 { "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1,
1388 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1389 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1390 /* Dst32AnPrefixed: address register */
1391 { "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1,
1392 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1393 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1394 /* Dst32AnPrefixedQI: address register QI view */
1395 { "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1,
1396 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1397 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1398 /* Dst32AnPrefixedHI: address register HI view */
1399 { "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1,
1400 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1401 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1402 /* Dst32AnPrefixedSI: address register SI view */
1403 { "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1,
1404 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1405 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1406 /* Bit16An: address register bit view */
1407 { "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1,
1408 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1409 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1410 /* Bit32AnPrefixed: address register bit */
1411 { "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1,
1412 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1413 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1414 /* Bit32AnUnprefixed: address register bit */
1415 { "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1,
1416 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1417 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1418 /* A0: a0 */
1419 { "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0,
1420 { 0, { (const PTR) 0 } },
1421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1422 /* A1: a1 */
1423 { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
1424 { 0, { (const PTR) 0 } },
1425 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1426 /* sb: SB register */
1427 { "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
1428 { 0, { (const PTR) 0 } },
1429 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1430 /* fb: FB register */
1431 { "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0,
1432 { 0, { (const PTR) 0 } },
1433 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1434 /* sp: SP register */
1435 { "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0,
1436 { 0, { (const PTR) 0 } },
1437 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1438 /* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */
1439 { "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1,
1440 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } },
1441 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1442 /* Regsetpop: popm regset */
1443 { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8,
1444 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
1445 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1446 /* Regsetpush: pushm regset */
1447 { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8,
1448 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
1449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1450 /* Rn16-push-S: r0[lh] */
1451 { "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1,
1452 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
1453 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1454 /* An16-push-S: a[01] */
1455 { "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1,
1456 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
1457 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
1458 /* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */
1459 { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6,
1460 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } },
1461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1462 /* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */
1463 { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8,
1464 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
1465 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1466 /* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */
1467 { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16,
1468 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } },
1469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1470 /* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */
1471 { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8,
1472 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
1473 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1474 /* Dsp-8-s24: signed 24 bit displacement at offset 8 bits */
1475 { "Dsp-8-s24", M32C_OPERAND_DSP_8_S24, HW_H_SINT, 8, 24,
1476 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S24] } },
1477 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1478 /* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */
1479 { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24,
1480 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } },
1481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1482 /* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */
1483 { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
1484 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } },
1485 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1486 /* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */
1487 { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8,
1488 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1490 /* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */
1491 { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16,
1492 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1493 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1494 /* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */
1495 { "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24,
1496 { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
1497 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1498 /* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */
1499 { "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24,
1500 { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
1501 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1502 /* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */
1503 { "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8,
1504 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1505 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1506 /* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */
1507 { "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16,
1508 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1510 /* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */
1511 { "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8,
1512 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1513 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1514 /* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */
1515 { "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16,
1516 { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } },
1517 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1518 /* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */
1519 { "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24,
1520 { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
1521 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1522 /* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */
1523 { "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24,
1524 { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
1525 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1526 /* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */
1527 { "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8,
1528 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1530 /* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */
1531 { "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16,
1532 { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
1533 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1534 /* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */
1535 { "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8,
1536 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1537 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1538 /* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */
1539 { "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16,
1540 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1542 /* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */
1543 { "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24,
1544 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1545 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1546 /* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */
1547 { "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24,
1548 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1550 /* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */
1551 { "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8,
1552 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1553 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1554 /* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */
1555 { "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16,
1556 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
1557 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1558 /* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */
1559 { "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8,
1560 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
1561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1562 /* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */
1563 { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8,
1564 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
1565 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1566 /* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */
1567 { "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16,
1568 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } },
1569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1570 /* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */
1571 { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16,
1572 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
1573 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1574 /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
1575 { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24,
1576 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
1577 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1578 /* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */
1579 { "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8,
1580 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } },
1581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1582 /* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */
1583 { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8,
1584 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
1585 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1586 /* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */
1587 { "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16,
1588 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1590 /* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */
1591 { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16,
1592 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
1593 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1594 /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
1595 { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24,
1596 { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } },
1597 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1598 /* Imm-8-s4: signed 4 bit immediate at offset 8 bits */
1599 { "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4,
1600 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
1601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1602 /* Imm-8-s4n: negated 4 bit immediate at offset 8 bits */
1603 { "Imm-8-s4n", M32C_OPERAND_IMM_8_S4N, HW_H_SINT, 8, 4,
1604 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
1605 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1606 /* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */
1607 { "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4,
1608 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
1609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1610 /* Imm-8-QI: signed 8 bit immediate at offset 8 bits */
1611 { "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8,
1612 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
1613 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1614 /* Imm-8-HI: signed 16 bit immediate at offset 8 bits */
1615 { "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16,
1616 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } },
1617 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1618 /* Imm-12-s4: signed 4 bit immediate at offset 12 bits */
1619 { "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4,
1620 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
1621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1622 /* Imm-12-s4n: negated 4 bit immediate at offset 12 bits */
1623 { "Imm-12-s4n", M32C_OPERAND_IMM_12_S4N, HW_H_SINT, 12, 4,
1624 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
1625 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1626 /* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */
1627 { "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4,
1628 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
1629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1630 /* Imm-13-u3: signed 3 bit immediate at offset 13 bits */
1631 { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3,
1632 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } },
1633 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1634 /* Imm-20-s4: signed 4 bit immediate at offset 20 bits */
1635 { "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4,
1636 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
1637 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1638 /* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */
1639 { "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4,
1640 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
1641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1642 /* Imm-16-QI: signed 8 bit immediate at offset 16 bits */
1643 { "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8,
1644 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1645 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1646 /* Imm-16-HI: signed 16 bit immediate at offset 16 bits */
1647 { "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16,
1648 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1650 /* Imm-16-SI: signed 32 bit immediate at offset 16 bits */
1651 { "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32,
1652 { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } },
1653 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1654 /* Imm-24-QI: signed 8 bit immediate at offset 24 bits */
1655 { "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8,
1656 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1657 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1658 /* Imm-24-HI: signed 16 bit immediate at offset 24 bits */
1659 { "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16,
1660 { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
1661 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1662 /* Imm-24-SI: signed 32 bit immediate at offset 24 bits */
1663 { "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32,
1664 { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } },
1665 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1666 /* Imm-32-QI: signed 8 bit immediate at offset 32 bits */
1667 { "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8,
1668 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1670 /* Imm-32-SI: signed 32 bit immediate at offset 32 bits */
1671 { "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32,
1672 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } },
1673 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1674 /* Imm-32-HI: signed 16 bit immediate at offset 32 bits */
1675 { "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16,
1676 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
1677 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1678 /* Imm-40-QI: signed 8 bit immediate at offset 40 bits */
1679 { "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8,
1680 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
1681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1682 /* Imm-40-HI: signed 16 bit immediate at offset 40 bits */
1683 { "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16,
1684 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
1685 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1686 /* Imm-40-SI: signed 32 bit immediate at offset 40 bits */
1687 { "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32,
1688 { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } },
1689 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1690 /* Imm-48-QI: signed 8 bit immediate at offset 48 bits */
1691 { "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8,
1692 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
1693 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1694 /* Imm-48-HI: signed 16 bit immediate at offset 48 bits */
1695 { "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16,
1696 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
1697 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1698 /* Imm-48-SI: signed 32 bit immediate at offset 48 bits */
1699 { "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32,
1700 { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } },
1701 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1702 /* Imm-56-QI: signed 8 bit immediate at offset 56 bits */
1703 { "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8,
1704 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } },
1705 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1706 /* Imm-56-HI: signed 16 bit immediate at offset 56 bits */
1707 { "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16,
1708 { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } },
1709 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1710 /* Imm-64-HI: signed 16 bit immediate at offset 64 bits */
1711 { "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16,
1712 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } },
1713 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1714 /* Imm1-S: signed 1 bit immediate for short format binary insns */
1715 { "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1,
1716 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } },
1717 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1718 /* Imm3-S: signed 3 bit immediate for short format binary insns */
1719 { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3,
1720 { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
1721 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1722 /* Bitno16R: bit number for indexing registers */
1723 { "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8,
1724 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1725 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1726 /* Bitno32Prefixed: bit number for indexing objects */
1727 { "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3,
1728 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1730 /* Bitno32Unprefixed: bit number for indexing objects */
1731 { "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3,
1732 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1733 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1734 /* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */
1735 { "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8,
1736 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1737 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1738 /* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */
1739 { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8,
1740 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1742 /* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */
1743 { "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16,
1744 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1745 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1746 /* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */
1747 { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11,
1748 { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } },
1749 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1750 /* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */
1751 { "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11,
1752 { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } },
1753 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1754 /* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */
1755 { "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11,
1756 { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } },
1757 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1758 /* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */
1759 { "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19,
1760 { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } },
1761 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1762 /* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */
1763 { "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19,
1764 { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } },
1765 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1766 /* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */
1767 { "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27,
1768 { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } },
1769 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1770 /* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */
1771 { "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11,
1772 { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } },
1773 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1774 /* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */
1775 { "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11,
1776 { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } },
1777 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1778 /* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */
1779 { "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19,
1780 { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } },
1781 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1782 /* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */
1783 { "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19,
1784 { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } },
1785 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1786 /* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */
1787 { "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27,
1788 { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } },
1789 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1790 /* Lab-5-3: 3 bit label */
1791 { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3,
1792 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } },
1793 { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1794 /* Lab32-jmp-s: 3 bit label */
1795 { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3,
1796 { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } },
1797 { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1798 /* Lab-8-8: 8 bit label */
1799 { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8,
1800 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } },
1801 { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1802 /* Lab-8-16: 16 bit label */
1803 { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16,
1804 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } },
1805 { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1806 /* Lab-8-24: 24 bit label */
1807 { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24,
1808 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } },
1809 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1810 /* Lab-16-8: 8 bit label */
1811 { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8,
1812 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } },
1813 { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1814 /* Lab-24-8: 8 bit label */
1815 { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8,
1816 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } },
1817 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1818 /* Lab-32-8: 8 bit label */
1819 { "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8,
1820 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } },
1821 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1822 /* Lab-40-8: 8 bit label */
1823 { "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8,
1824 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } },
1825 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1826 /* sbit: negative bit */
1827 { "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0,
1828 { 0, { (const PTR) 0 } },
1829 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1830 /* obit: overflow bit */
1831 { "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0,
1832 { 0, { (const PTR) 0 } },
1833 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1834 /* zbit: zero bit */
1835 { "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
1836 { 0, { (const PTR) 0 } },
1837 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1838 /* cbit: carry bit */
1839 { "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0,
1840 { 0, { (const PTR) 0 } },
1841 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1842 /* ubit: stack ptr select bit */
1843 { "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0,
1844 { 0, { (const PTR) 0 } },
1845 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1846 /* ibit: interrupt enable bit */
1847 { "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0,
1848 { 0, { (const PTR) 0 } },
1849 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1850 /* bbit: reg bank select bit */
1851 { "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0,
1852 { 0, { (const PTR) 0 } },
1853 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1854 /* dbit: debug bit */
1855 { "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0,
1856 { 0, { (const PTR) 0 } },
1857 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1858 /* cond16-16: condition */
1859 { "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8,
1860 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1862 /* cond16-24: condition */
1863 { "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8,
1864 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1865 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1866 /* cond16-32: condition */
1867 { "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8,
1868 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1870 /* cond32-16: condition */
1871 { "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8,
1872 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1873 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1874 /* cond32-24: condition */
1875 { "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8,
1876 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1877 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1878 /* cond32-32: condition */
1879 { "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8,
1880 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1882 /* cond32-40: condition */
1883 { "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8,
1884 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
1885 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1886 /* cond16c: condition */
1887 { "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4,
1888 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1890 /* cond16j: condition */
1891 { "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4,
1892 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1893 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1894 /* cond16j5: condition */
1895 { "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3,
1896 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } },
1897 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1898 /* cond32: condition */
1899 { "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4,
1900 { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } },
1901 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1902 /* cond32j: condition */
1903 { "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4,
1904 { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } },
1905 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1906 /* sccond32: scCND condition */
1907 { "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4,
1908 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1910 /* flags16: flags */
1911 { "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3,
1912 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
1913 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1914 /* flags32: flags */
1915 { "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3,
1916 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1917 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1918 /* cr16: control */
1919 { "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3,
1920 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
1921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
1922 /* cr1-Unprefixed-32: control */
1923 { "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3,
1924 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1925 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1926 /* cr1-Prefixed-32: control */
1927 { "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3,
1928 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
1929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1930 /* cr2-32: control */
1931 { "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3,
1932 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1933 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1934 /* cr3-Unprefixed-32: control */
1935 { "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3,
1936 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1937 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1938 /* cr3-Prefixed-32: control */
1939 { "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3,
1940 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
1941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
1942 /* Z: Suffix for zero format insns */
1943 { "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0,
1944 { 0, { (const PTR) 0 } },
1945 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1946 /* S: Suffix for short format insns */
1947 { "S", M32C_OPERAND_S, HW_H_SINT, 0, 0,
1948 { 0, { (const PTR) 0 } },
1949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1950 /* Q: Suffix for quick format insns */
1951 { "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0,
1952 { 0, { (const PTR) 0 } },
1953 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1954 /* G: Suffix for general format insns */
1955 { "G", M32C_OPERAND_G, HW_H_SINT, 0, 0,
1956 { 0, { (const PTR) 0 } },
1957 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1958 /* X: Empty suffix */
1959 { "X", M32C_OPERAND_X, HW_H_SINT, 0, 0,
1960 { 0, { (const PTR) 0 } },
1961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1962 /* size: any size specifier */
1963 { "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0,
1964 { 0, { (const PTR) 0 } },
1965 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
1966 /* BitIndex: Bit Index for the next insn */
1967 { "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0,
1968 { 0, { (const PTR) 0 } },
1969 { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1970 /* SrcIndex: Source Index for the next insn */
1971 { "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0,
1972 { 0, { (const PTR) 0 } },
1973 { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1974 /* DstIndex: Destination Index for the next insn */
1975 { "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0,
1976 { 0, { (const PTR) 0 } },
1977 { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1978 /* NoRemainder: Place holder for when the remainder is not kept */
1979 { "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0,
1980 { 0, { (const PTR) 0 } },
1981 { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
1982 /* src16-Rn-direct-QI: m16c Rn direct source QI */
1983 /* src16-Rn-direct-HI: m16c Rn direct source HI */
1984 /* src32-Rn-direct-Unprefixed-QI: m32c Rn direct source QI */
1985 /* src32-Rn-direct-Prefixed-QI: m32c Rn direct source QI */
1986 /* src32-Rn-direct-Unprefixed-HI: m32c Rn direct source HI */
1987 /* src32-Rn-direct-Prefixed-HI: m32c Rn direct source HI */
1988 /* src32-Rn-direct-Unprefixed-SI: m32c Rn direct source SI */
1989 /* src32-Rn-direct-Prefixed-SI: m32c Rn direct source SI */
1990 /* src16-An-direct-QI: m16c An direct destination QI */
1991 /* src16-An-direct-HI: m16c An direct destination HI */
1992 /* src32-An-direct-Unprefixed-QI: m32c An direct destination QI */
1993 /* src32-An-direct-Unprefixed-HI: m32c An direct destination HI */
1994 /* src32-An-direct-Unprefixed-SI: m32c An direct destination SI */
1995 /* src32-An-direct-Prefixed-QI: m32c An direct destination QI */
1996 /* src32-An-direct-Prefixed-HI: m32c An direct destination HI */
1997 /* src32-An-direct-Prefixed-SI: m32c An direct destination SI */
1998 /* src16-An-indirect-QI: m16c An indirect destination QI */
1999 /* src16-An-indirect-HI: m16c An indirect destination HI */
2000 /* src32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
2001 /* src32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
2002 /* src32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
2003 /* src32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
2004 /* src32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
2005 /* src32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
2006 /* src16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2007 /* src16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2008 /* src16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2009 /* src16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2010 /* src16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2011 /* src16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2012 /* src16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2013 /* src16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2014 /* src16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2015 /* src16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2016 /* src32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2017 /* src32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2018 /* src32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2019 /* src32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2020 /* src32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2021 /* src32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2022 /* src32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2023 /* src32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2024 /* src32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2025 /* src32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2026 /* src32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2027 /* src32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2028 /* src32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2029 /* src32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2030 /* src32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2031 /* src32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2032 /* src32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2033 /* src32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2034 /* src32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2035 /* src32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2036 /* src32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2037 /* src32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2038 /* src32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2039 /* src32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2040 /* src32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2041 /* src32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2042 /* src32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2043 /* src32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2044 /* src32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2045 /* src32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2046 /* src32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2047 /* src32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2048 /* src32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2049 /* src32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2050 /* src32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2051 /* src32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2052 /* src32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2053 /* src32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2054 /* src32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2055 /* src32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2056 /* src32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2057 /* src32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2058 /* src16-16-16-absolute-QI: m16c absolute address QI */
2059 /* src16-16-16-absolute-HI: m16c absolute address HI */
2060 /* src32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2061 /* src32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2062 /* src32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2063 /* src32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2064 /* src32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2065 /* src32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2066 /* src32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2067 /* src32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2068 /* src32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2069 /* src32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2070 /* src32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2071 /* src32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2072 /* src16-2-S-8-SB-relative-QI: m16c SB relative address */
2073 /* src16-2-S-8-FB-relative-QI: m16c FB relative address */
2074 /* src16-2-S-16-absolute-QI: m16c absolute address */
2075 /* src32-2-S-8-SB-relative-QI: m32c SB relative address */
2076 /* src32-2-S-8-FB-relative-QI: m32c FB relative address */
2077 /* src32-2-S-16-absolute-QI: m32c absolute address */
2078 /* src32-2-S-8-SB-relative-HI: m32c SB relative address */
2079 /* src32-2-S-8-FB-relative-HI: m32c FB relative address */
2080 /* src32-2-S-16-absolute-HI: m32c absolute address */
2081 /* dst16-Rn-direct-QI: m16c Rn direct destination QI */
2082 /* dst16-Rn-direct-HI: m16c Rn direct destination HI */
2083 /* dst16-Rn-direct-SI: m16c Rn direct destination SI */
2084 /* dst16-Rn-direct-Ext-QI: m16c Rn direct destination QI */
2085 /* dst32-Rn-direct-Unprefixed-QI: m32c Rn direct destination QI */
2086 /* dst32-Rn-direct-Prefixed-QI: m32c Rn direct destination QI */
2087 /* dst32-Rn-direct-Unprefixed-HI: m32c Rn direct destination HI */
2088 /* dst32-Rn-direct-Prefixed-HI: m32c Rn direct destination HI */
2089 /* dst32-Rn-direct-Unprefixed-SI: m32c Rn direct destination SI */
2090 /* dst32-Rn-direct-Prefixed-SI: m32c Rn direct destination SI */
2091 /* dst32-Rn-direct-ExtUnprefixed-QI: m32c Rn direct destination QI */
2092 /* dst32-Rn-direct-ExtUnprefixed-HI: m32c Rn direct destination HI */
2093 /* dst32-R3-direct-Unprefixed-HI: m32c R3 direct HI */
2094 /* dst16-An-direct-QI: m16c An direct destination QI */
2095 /* dst16-An-direct-HI: m16c An direct destination HI */
2096 /* dst16-An-direct-SI: m16c An direct destination SI */
2097 /* dst32-An-direct-Unprefixed-QI: m32c An direct destination QI */
2098 /* dst32-An-direct-Prefixed-QI: m32c An direct destination QI */
2099 /* dst32-An-direct-Unprefixed-HI: m32c An direct destination HI */
2100 /* dst32-An-direct-Prefixed-HI: m32c An direct destination HI */
2101 /* dst32-An-direct-Unprefixed-SI: m32c An direct destination SI */
2102 /* dst32-An-direct-Prefixed-SI: m32c An direct destination SI */
2103 /* dst16-An-indirect-QI: m16c An indirect destination QI */
2104 /* dst16-An-indirect-HI: m16c An indirect destination HI */
2105 /* dst16-An-indirect-SI: m16c An indirect destination SI */
2106 /* dst16-An-indirect-Ext-QI: m16c An indirect destination QI */
2107 /* dst32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
2108 /* dst32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
2109 /* dst32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
2110 /* dst32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
2111 /* dst32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
2112 /* dst32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
2113 /* dst32-An-indirect-ExtUnprefixed-QI: m32c An indirect destination QI */
2114 /* dst32-An-indirect-ExtUnprefixed-HI: m32c An indirect destination HI */
2115 /* dst16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2116 /* dst16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2117 /* dst16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2118 /* dst16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2119 /* dst16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2120 /* dst16-24-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2121 /* dst16-24-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2122 /* dst16-24-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2123 /* dst16-24-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2124 /* dst16-24-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2125 /* dst16-32-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2126 /* dst16-32-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2127 /* dst16-32-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2128 /* dst16-32-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2129 /* dst16-32-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2130 /* dst16-40-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2131 /* dst16-40-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2132 /* dst16-40-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2133 /* dst16-40-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2134 /* dst16-40-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2135 /* dst16-48-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2136 /* dst16-48-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2137 /* dst16-48-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2138 /* dst16-48-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2139 /* dst16-48-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2140 /* dst16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2141 /* dst16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2142 /* dst16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2143 /* dst16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2144 /* dst16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2145 /* dst16-24-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2146 /* dst16-24-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2147 /* dst16-24-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2148 /* dst16-24-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2149 /* dst16-24-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2150 /* dst16-32-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2151 /* dst16-32-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2152 /* dst16-32-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2153 /* dst16-32-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2154 /* dst16-32-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2155 /* dst16-40-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2156 /* dst16-40-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2157 /* dst16-40-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2158 /* dst16-40-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2159 /* dst16-40-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2160 /* dst16-48-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2161 /* dst16-48-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2162 /* dst16-48-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2163 /* dst16-48-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2164 /* dst16-48-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2165 /* dst16-16-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2166 /* dst16-16-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2167 /* dst16-16-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2168 /* dst16-16-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2169 /* dst16-16-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2170 /* dst16-24-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2171 /* dst16-24-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2172 /* dst16-24-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2173 /* dst16-24-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2174 /* dst16-24-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2175 /* dst16-32-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2176 /* dst16-32-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2177 /* dst16-32-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2178 /* dst16-32-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2179 /* dst16-32-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2180 /* dst16-40-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2181 /* dst16-40-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2182 /* dst16-40-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2183 /* dst16-40-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2184 /* dst16-40-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2185 /* dst16-48-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2186 /* dst16-48-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2187 /* dst16-48-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2188 /* dst16-48-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2189 /* dst16-48-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2190 /* dst16-16-8-SB-relative-Ext-QI: m16c dsp:8[sb] relative destination QI */
2191 /* dst16-16-16-SB-relative-Ext-QI: m16c dsp:16[sb] relative destination QI */
2192 /* dst16-16-8-FB-relative-Ext-QI: m16c dsp:8[fb] relative destination QI */
2193 /* dst16-16-8-An-relative-Ext-QI: m16c dsp:8[An] relative destination QI */
2194 /* dst16-16-16-An-relative-Ext-QI: m16c dsp:16[An] relative destination QI */
2195 /* dst32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2196 /* dst32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2197 /* dst32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2198 /* dst32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2199 /* dst32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2200 /* dst32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2201 /* dst32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2202 /* dst32-24-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2203 /* dst32-24-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2204 /* dst32-24-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2205 /* dst32-24-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2206 /* dst32-24-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2207 /* dst32-24-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2208 /* dst32-24-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2209 /* dst32-32-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2210 /* dst32-32-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2211 /* dst32-32-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2212 /* dst32-32-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2213 /* dst32-32-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2214 /* dst32-32-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2215 /* dst32-32-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2216 /* dst32-40-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2217 /* dst32-40-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2218 /* dst32-40-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2219 /* dst32-40-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2220 /* dst32-40-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2221 /* dst32-40-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2222 /* dst32-40-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2223 /* dst32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2224 /* dst32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2225 /* dst32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2226 /* dst32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2227 /* dst32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2228 /* dst32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2229 /* dst32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2230 /* dst32-24-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2231 /* dst32-24-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2232 /* dst32-24-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2233 /* dst32-24-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2234 /* dst32-24-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2235 /* dst32-24-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2236 /* dst32-24-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2237 /* dst32-32-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2238 /* dst32-32-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2239 /* dst32-32-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2240 /* dst32-32-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2241 /* dst32-32-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2242 /* dst32-32-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2243 /* dst32-32-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2244 /* dst32-40-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2245 /* dst32-40-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2246 /* dst32-40-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2247 /* dst32-40-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2248 /* dst32-40-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2249 /* dst32-40-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2250 /* dst32-40-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2251 /* dst32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2252 /* dst32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2253 /* dst32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2254 /* dst32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2255 /* dst32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2256 /* dst32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2257 /* dst32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2258 /* dst32-24-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2259 /* dst32-24-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2260 /* dst32-24-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2261 /* dst32-24-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2262 /* dst32-24-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2263 /* dst32-24-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2264 /* dst32-24-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2265 /* dst32-32-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2266 /* dst32-32-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2267 /* dst32-32-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2268 /* dst32-32-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2269 /* dst32-32-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2270 /* dst32-32-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2271 /* dst32-32-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2272 /* dst32-40-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2273 /* dst32-40-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2274 /* dst32-40-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2275 /* dst32-40-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2276 /* dst32-40-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2277 /* dst32-40-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2278 /* dst32-40-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2279 /* dst32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2280 /* dst32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2281 /* dst32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2282 /* dst32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2283 /* dst32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2284 /* dst32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2285 /* dst32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2286 /* dst32-32-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2287 /* dst32-32-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2288 /* dst32-32-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2289 /* dst32-32-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2290 /* dst32-32-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2291 /* dst32-32-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2292 /* dst32-32-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2293 /* dst32-40-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2294 /* dst32-40-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2295 /* dst32-40-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2296 /* dst32-40-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2297 /* dst32-40-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2298 /* dst32-40-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2299 /* dst32-40-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2300 /* dst32-48-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2301 /* dst32-48-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2302 /* dst32-48-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2303 /* dst32-48-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2304 /* dst32-48-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2305 /* dst32-48-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2306 /* dst32-48-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2307 /* dst32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2308 /* dst32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2309 /* dst32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2310 /* dst32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2311 /* dst32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2312 /* dst32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2313 /* dst32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2314 /* dst32-32-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2315 /* dst32-32-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2316 /* dst32-32-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2317 /* dst32-32-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2318 /* dst32-32-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2319 /* dst32-32-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2320 /* dst32-32-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2321 /* dst32-40-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2322 /* dst32-40-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2323 /* dst32-40-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2324 /* dst32-40-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2325 /* dst32-40-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2326 /* dst32-40-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2327 /* dst32-40-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2328 /* dst32-48-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2329 /* dst32-48-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2330 /* dst32-48-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2331 /* dst32-48-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2332 /* dst32-48-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2333 /* dst32-48-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2334 /* dst32-48-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2335 /* dst32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2336 /* dst32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2337 /* dst32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2338 /* dst32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2339 /* dst32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2340 /* dst32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2341 /* dst32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2342 /* dst32-32-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2343 /* dst32-32-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2344 /* dst32-32-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2345 /* dst32-32-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2346 /* dst32-32-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2347 /* dst32-32-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2348 /* dst32-32-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2349 /* dst32-40-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2350 /* dst32-40-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2351 /* dst32-40-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2352 /* dst32-40-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2353 /* dst32-40-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2354 /* dst32-40-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2355 /* dst32-40-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2356 /* dst32-48-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2357 /* dst32-48-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2358 /* dst32-48-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2359 /* dst32-48-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2360 /* dst32-48-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2361 /* dst32-48-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2362 /* dst32-48-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2363 /* dst32-16-8-SB-relative-ExtUnprefixed-QI: m32c dsp:8[sb] relative destination QI */
2364 /* dst32-16-16-SB-relative-ExtUnprefixed-QI: m32c dsp:16[sb] relative destination QI */
2365 /* dst32-16-8-FB-relative-ExtUnprefixed-QI: m32c dsp:8[fb] relative destination QI */
2366 /* dst32-16-16-FB-relative-ExtUnprefixed-QI: m32c dsp:16[fb] relative destination QI */
2367 /* dst32-16-8-An-relative-ExtUnprefixed-QI: m32c dsp:8[An] relative destination QI */
2368 /* dst32-16-16-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2369 /* dst32-16-24-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2370 /* dst32-16-8-SB-relative-ExtUnprefixed-HI: m32c dsp:8[sb] relative destination HI */
2371 /* dst32-16-16-SB-relative-ExtUnprefixed-HI: m32c dsp:16[sb] relative destination HI */
2372 /* dst32-16-8-FB-relative-ExtUnprefixed-HI: m32c dsp:8[fb] relative destination HI */
2373 /* dst32-16-16-FB-relative-ExtUnprefixed-HI: m32c dsp:16[fb] relative destination HI */
2374 /* dst32-16-8-An-relative-ExtUnprefixed-HI: m32c dsp:8[An] relative destination HI */
2375 /* dst32-16-16-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2376 /* dst32-16-24-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2377 /* dst16-16-16-absolute-QI: m16c absolute address QI */
2378 /* dst16-24-16-absolute-QI: m16c absolute address QI */
2379 /* dst16-32-16-absolute-QI: m16c absolute address QI */
2380 /* dst16-40-16-absolute-QI: m16c absolute address QI */
2381 /* dst16-48-16-absolute-QI: m16c absolute address QI */
2382 /* dst16-16-16-absolute-HI: m16c absolute address HI */
2383 /* dst16-24-16-absolute-HI: m16c absolute address HI */
2384 /* dst16-32-16-absolute-HI: m16c absolute address HI */
2385 /* dst16-40-16-absolute-HI: m16c absolute address HI */
2386 /* dst16-48-16-absolute-HI: m16c absolute address HI */
2387 /* dst16-16-16-absolute-SI: m16c absolute address SI */
2388 /* dst16-24-16-absolute-SI: m16c absolute address SI */
2389 /* dst16-32-16-absolute-SI: m16c absolute address SI */
2390 /* dst16-40-16-absolute-SI: m16c absolute address SI */
2391 /* dst16-48-16-absolute-SI: m16c absolute address SI */
2392 /* dst16-16-16-absolute-Ext-QI: m16c absolute address QI */
2393 /* dst32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2394 /* dst32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2395 /* dst32-24-16-absolute-Unprefixed-QI: m32c absolute address QI */
2396 /* dst32-24-24-absolute-Unprefixed-QI: m32c absolute address QI */
2397 /* dst32-32-16-absolute-Unprefixed-QI: m32c absolute address QI */
2398 /* dst32-32-24-absolute-Unprefixed-QI: m32c absolute address QI */
2399 /* dst32-40-16-absolute-Unprefixed-QI: m32c absolute address QI */
2400 /* dst32-40-24-absolute-Unprefixed-QI: m32c absolute address QI */
2401 /* dst32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2402 /* dst32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2403 /* dst32-24-16-absolute-Unprefixed-HI: m32c absolute address HI */
2404 /* dst32-24-24-absolute-Unprefixed-HI: m32c absolute address HI */
2405 /* dst32-32-16-absolute-Unprefixed-HI: m32c absolute address HI */
2406 /* dst32-32-24-absolute-Unprefixed-HI: m32c absolute address HI */
2407 /* dst32-40-16-absolute-Unprefixed-HI: m32c absolute address HI */
2408 /* dst32-40-24-absolute-Unprefixed-HI: m32c absolute address HI */
2409 /* dst32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2410 /* dst32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2411 /* dst32-24-16-absolute-Unprefixed-SI: m32c absolute address SI */
2412 /* dst32-24-24-absolute-Unprefixed-SI: m32c absolute address SI */
2413 /* dst32-32-16-absolute-Unprefixed-SI: m32c absolute address SI */
2414 /* dst32-32-24-absolute-Unprefixed-SI: m32c absolute address SI */
2415 /* dst32-40-16-absolute-Unprefixed-SI: m32c absolute address SI */
2416 /* dst32-40-24-absolute-Unprefixed-SI: m32c absolute address SI */
2417 /* dst32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2418 /* dst32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2419 /* dst32-32-16-absolute-Prefixed-QI: m32c absolute address QI */
2420 /* dst32-32-24-absolute-Prefixed-QI: m32c absolute address QI */
2421 /* dst32-40-16-absolute-Prefixed-QI: m32c absolute address QI */
2422 /* dst32-40-24-absolute-Prefixed-QI: m32c absolute address QI */
2423 /* dst32-48-16-absolute-Prefixed-QI: m32c absolute address QI */
2424 /* dst32-48-24-absolute-Prefixed-QI: m32c absolute address QI */
2425 /* dst32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2426 /* dst32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2427 /* dst32-32-16-absolute-Prefixed-HI: m32c absolute address HI */
2428 /* dst32-32-24-absolute-Prefixed-HI: m32c absolute address HI */
2429 /* dst32-40-16-absolute-Prefixed-HI: m32c absolute address HI */
2430 /* dst32-40-24-absolute-Prefixed-HI: m32c absolute address HI */
2431 /* dst32-48-16-absolute-Prefixed-HI: m32c absolute address HI */
2432 /* dst32-48-24-absolute-Prefixed-HI: m32c absolute address HI */
2433 /* dst32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2434 /* dst32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2435 /* dst32-32-16-absolute-Prefixed-SI: m32c absolute address SI */
2436 /* dst32-32-24-absolute-Prefixed-SI: m32c absolute address SI */
2437 /* dst32-40-16-absolute-Prefixed-SI: m32c absolute address SI */
2438 /* dst32-40-24-absolute-Prefixed-SI: m32c absolute address SI */
2439 /* dst32-48-16-absolute-Prefixed-SI: m32c absolute address SI */
2440 /* dst32-48-24-absolute-Prefixed-SI: m32c absolute address SI */
2441 /* dst32-16-16-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2442 /* dst32-16-24-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2443 /* dst32-16-16-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2444 /* dst32-16-24-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2445 /* bit16-Rn-direct: m16c Rn direct bit */
2446 /* bit32-Rn-direct-Unprefixed: m32c Rn direct bit */
2447 /* bit32-Rn-direct-Prefixed: m32c Rn direct bit */
2448 /* bit16-An-direct: m16c An direct bit */
2449 /* bit32-An-direct-Unprefixed: m32c An direct bit */
2450 /* bit32-An-direct-Prefixed: m32c An direct bit */
2451 /* bit16-An-indirect: m16c An indirect bit */
2452 /* bit32-An-indirect-Unprefixed: m32c An indirect destination */
2453 /* bit32-An-indirect-Prefixed: m32c An indirect destination */
2454 /* bit16-16-8-SB-relative: m16c dsp:8[sb] relative bit xmode */
2455 /* bit16-16-16-SB-relative: m16c dsp:16[sb] relative bit xmode */
2456 /* bit16-16-8-FB-relative: m16c dsp:8[fb] relative bit xmode */
2457 /* bit16-16-8-An-relative: m16c dsp:8[An] relative bit xmode */
2458 /* bit16-16-16-An-relative: m16c dsp:16[An] relative bit xmode */
2459 /* bit32-16-11-SB-relative-Unprefixed: m32c bit,base:11[sb] relative bit */
2460 /* bit32-16-19-SB-relative-Unprefixed: m32c bit,base:19[sb] relative bit */
2461 /* bit32-16-11-FB-relative-Unprefixed: m32c bit,base:11[fb] relative bit */
2462 /* bit32-16-19-FB-relative-Unprefixed: m32c bit,base:19[fb] relative bit */
2463 /* bit32-16-11-An-relative-Unprefixed: m32c bit,base:11[An] relative bit */
2464 /* bit32-16-19-An-relative-Unprefixed: m32c bit,base:19[An] relative bit */
2465 /* bit32-16-27-An-relative-Unprefixed: m32c bit,base:27[An] relative bit */
2466 /* bit32-24-11-SB-relative-Prefixed: m32c bit,base:11[sb] relative bit */
2467 /* bit32-24-19-SB-relative-Prefixed: m32c bit,base:19[sb] relative bit */
2468 /* bit32-24-11-FB-relative-Prefixed: m32c bit,base:11[fb] relative bit */
2469 /* bit32-24-19-FB-relative-Prefixed: m32c bit,base:19[fb] relative bit */
2470 /* bit32-24-11-An-relative-Prefixed: m32c bit,base:11[An] relative bit */
2471 /* bit32-24-19-An-relative-Prefixed: m32c bit,base:19[An] relative bit */
2472 /* bit32-24-27-An-relative-Prefixed: m32c bit,base:27[An] relative bit */
2473 /* bit16-11-SB-relative-S: m16c bit,base:11[sb] relative bit */
2474 /* Rn16-push-S-derived: m16c r0[lh] for push,pop short version */
2475 /* An16-push-S-derived: m16c r0[lh] for push,pop short version */
2476 /* bit16-16-16-absolute: m16c absolute address */
2477 /* bit32-16-19-absolute-Unprefixed: m32c absolute address bit */
2478 /* bit32-16-27-absolute-Unprefixed: m32c absolute address bit */
2479 /* bit32-24-19-absolute-Prefixed: m32c absolute address bit */
2480 /* bit32-24-27-absolute-Prefixed: m32c absolute address bit */
2481 /* dst16-3-S-R0l-direct-QI: m16c R0l direct QI */
2482 /* dst16-3-S-R0h-direct-QI: m16c R0h direct QI */
2483 /* dst16-3-S-8-8-SB-relative-QI: m16c SB relative QI */
2484 /* dst16-3-S-8-8-FB-relative-QI: m16c FB relative QI */
2485 /* dst16-3-S-8-16-absolute-QI: m16c absolute address QI */
2486 /* dst16-3-S-16-8-SB-relative-QI: m16c SB relative QI */
2487 /* dst16-3-S-16-8-FB-relative-QI: m16c FB relative QI */
2488 /* dst16-3-S-16-16-absolute-QI: m16c absolute address QI */
2489 /* srcdst16-r0l-r0h-S-derived: m16c r0l/r0h operand for short format insns */
2490 /* dst32-2-S-R0l-direct-QI: m32c R0l direct QI */
2491 /* dst32-2-S-R0-direct-HI: m32c R0 direct HI */
2492 /* dst32-1-S-A0-direct-HI: m32c A0 direct HI */
2493 /* dst32-1-S-A1-direct-HI: m32c A1 direct HI */
2494 /* dst32-2-S-8-SB-relative-QI: m32c SB relative for short binary insns */
2495 /* dst32-2-S-8-FB-relative-QI: m32c FB relative for short binary insns */
2496 /* dst32-2-S-16-absolute-QI: m32c absolute address for short binary insns */
2497 /* dst32-2-S-8-SB-relative-HI: m32c SB relative for short binary insns */
2498 /* dst32-2-S-8-FB-relative-HI: m32c FB relative for short binary insns */
2499 /* dst32-2-S-16-absolute-HI: m32c absolute address for short binary insns */
2500 /* dst32-2-S-8-SB-relative-SI: m32c SB relative for short binary insns */
2501 /* dst32-2-S-8-FB-relative-SI: m32c FB relative for short binary insns */
2502 /* dst32-2-S-16-absolute-SI: m32c absolute address for short binary insns */
2503 /* src16-basic-QI: m16c source operand of size QI with no additional fields */
2504 /* src16-basic-HI: m16c source operand of size HI with no additional fields */
2505 /* src32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2506 /* src32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2507 /* src32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2508 /* src32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2509 /* src32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2510 /* src32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2511 /* src32-basic-ExtPrefixed-QI: m32c source operand of size QI with no additional fields */
2512 /* src16-16-8-QI: m16c source operand of size QI with additional 8 bit fields at offset 16 */
2513 /* src16-16-16-QI: m16c source operand of size QI with additional 16 bit fields at offset 16 */
2514 /* src16-16-8-HI: m16c source operand of size HI with additional 8 bit fields at offset 16 */
2515 /* src16-16-16-HI: m16c source operand of size HI with additional 16 bit fields at offset 16 */
2516 /* src32-16-8-Unprefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 16 */
2517 /* src32-16-16-Unprefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2518 /* src32-16-24-Unprefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2519 /* src32-16-8-Unprefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 16 */
2520 /* src32-16-16-Unprefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2521 /* src32-16-24-Unprefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2522 /* src32-16-8-Unprefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 16 */
2523 /* src32-16-16-Unprefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2524 /* src32-16-24-Unprefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2525 /* src32-24-8-Prefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 24 */
2526 /* src32-24-16-Prefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2527 /* src32-24-24-Prefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2528 /* src32-24-8-Prefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 24 */
2529 /* src32-24-16-Prefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2530 /* src32-24-24-Prefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2531 /* src32-24-8-Prefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 24 */
2532 /* src32-24-16-Prefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2533 /* src32-24-24-Prefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2534 /* dst16-basic-QI: m16c destination operand of size QI with no additional fields */
2535 /* dst16-basic-HI: m16c destination operand of size HI with no additional fields */
2536 /* dst16-basic-SI: m16c destination operand of size SI with no additional fields */
2537 /* dst32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2538 /* dst32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2539 /* dst32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2540 /* dst32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2541 /* dst32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2542 /* dst32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2543 /* dst16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2544 /* dst16-16-8-QI: m16c destination operand of size QI with additional fields at offset 16 */
2545 /* dst16-16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2546 /* dst16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2547 /* dst16-16-8-HI: m16c destination operand of size HI with additional fields at offset 16 */
2548 /* dst16-16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2549 /* dst16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2550 /* dst16-16-8-SI: m16c destination operand of size SI with additional fields at offset 16 */
2551 /* dst16-16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2552 /* dst16-16-Ext-QI: m16c destination operand of size QI for 'ext' insns with additional fields at offset 16 */
2553 /* dst16-An-indirect-Mova-HI: m16c addressof An indirect destination HI */
2554 /* dst16-16-8-An-relative-Mova-HI: m16c addressof dsp:8[An] relative destination HI */
2555 /* dst16-16-16-An-relative-Mova-HI: m16c addressof dsp:16[An] relative destination HI */
2556 /* dst16-16-8-SB-relative-Mova-HI: m16c addressof dsp:8[sb] relative destination HI */
2557 /* dst16-16-16-SB-relative-Mova-HI: m16c addressof dsp:16[sb] relative destination HI */
2558 /* dst16-16-8-FB-relative-Mova-HI: m16c addressof dsp:8[fb] relative destination HI */
2559 /* dst16-16-16-absolute-Mova-HI: m16c addressof absolute address HI */
2560 /* dst16-16-Mova-HI: m16c addressof destination operand of size HI with additional fields at offset 16 */
2561 /* dst32-An-indirect-Unprefixed-Mova-SI: m32c addressof An indirect destination SI */
2562 /* dst32-16-8-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[An] relative destination SI */
2563 /* dst32-16-16-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[An] relative destination SI */
2564 /* dst32-16-24-An-relative-Unprefixed-Mova-SI: addressof m32c dsp:16[An] relative destination SI */
2565 /* dst32-16-8-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[sb] relative destination SI */
2566 /* dst32-16-16-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[sb] relative destination SI */
2567 /* dst32-16-8-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[fb] relative destination SI */
2568 /* dst32-16-16-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[fb] relative destination SI */
2569 /* dst32-16-16-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2570 /* dst32-16-24-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2571 /* dst32-16-Unprefixed-Mova-SI: m32c addressof destination operand of size SI with additional fields at offset 16 */
2572 /* dst32-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2573 /* dst32-16-8-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2574 /* dst32-16-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2575 /* dst32-16-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2576 /* dst32-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2577 /* dst32-16-8-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2578 /* dst32-16-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2579 /* dst32-16-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2580 /* dst32-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2581 /* dst32-16-8-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2582 /* dst32-16-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2583 /* dst32-16-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2584 /* dst32-16-ExtUnprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2585 /* dst32-16-ExtUnprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2586 /* dst32-16-Unprefixed-Mulex-HI: m32c destination operand of size HI with additional fields at offset 16 */
2587 /* dst16-24-QI: m16c destination operand of size QI with additional fields at offset 24 */
2588 /* dst16-24-HI: m16c destination operand of size HI with additional fields at offset 24 */
2589 /* dst32-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2590 /* dst32-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2591 /* dst32-24-8-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2592 /* dst32-24-16-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2593 /* dst32-24-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2594 /* dst32-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2595 /* dst32-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2596 /* dst32-24-8-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2597 /* dst32-24-16-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2598 /* dst32-24-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2599 /* dst32-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2600 /* dst32-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2601 /* dst32-24-8-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2602 /* dst32-24-16-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2603 /* dst32-24-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2604 /* dst16-32-QI: m16c destination operand of size QI with additional fields at offset 32 */
2605 /* dst16-32-HI: m16c destination operand of size HI with additional fields at offset 32 */
2606 /* dst32-32-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2607 /* dst32-32-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2608 /* dst32-32-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2609 /* dst32-32-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2610 /* dst32-32-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2611 /* dst32-32-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2612 /* dst32-40-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2613 /* dst32-40-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2614 /* dst32-40-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2615 /* dst32-40-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2616 /* dst32-40-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2617 /* dst32-40-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2618 /* dst32-48-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2619 /* dst32-48-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2620 /* dst32-48-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2621 /* bit16-16: m16c bit operand with possible additional fields at offset 24 */
2622 /* bit16-16-basic: m16c bit operand with no additional fields */
2623 /* bit16-16-8: m16c bit operand with possible additional fields at offset 24 */
2624 /* bit16-16-16: m16c bit operand with possible additional fields at offset 24 */
2625 /* bit32-16-Unprefixed: m32c bit operand with possible additional fields at offset 24 */
2626 /* bit32-24-Prefixed: m32c bit operand with possible additional fields at offset 24 */
2627 /* bit32-basic-Unprefixed: m32c bit operand with no additional fields */
2628 /* bit32-16-8-Unprefixed: m32c bit operand with 8 bit additional fields */
2629 /* bit32-16-16-Unprefixed: m32c bit operand with 16 bit additional fields */
2630 /* bit32-16-24-Unprefixed: m32c bit operand with 24 bit additional fields */
2631 /* src16-2-S: m16c source operand of size QI for short format insns */
2632 /* src32-2-S-QI: m32c source operand of size QI for short format insns */
2633 /* src32-2-S-HI: m32c source operand of size QI for short format insns */
2634 /* Dst16-3-S-8: m16c destination operand of size QI for short format insns */
2635 /* Dst16-3-S-16: m16c destination operand of size QI for short format insns */
2636 /* srcdst16-r0l-r0h-S: m16c r0l/r0h operand of size QI for short format insns */
2637 /* dst32-2-S-basic-QI: m32c r0l operand of size QI for short format binary insns */
2638 /* dst32-2-S-basic-HI: m32c r0 operand of size HI for short format binary insns */
2639 /* dst32-2-S-8-QI: m32c operand of size */
2640 /* dst32-2-S-16-QI: m32c operand of size */
2641 /* dst32-2-S-8-HI: m32c operand of size */
2642 /* dst32-2-S-16-HI: m32c operand of size */
2643 /* dst32-2-S-8-SI: m32c operand of size */
2644 /* dst32-2-S-16-SI: m32c operand of size */
2645 /* dst32-an-S: m32c An operand for short format binary insns */
2646 /* bit16-11-S: m16c bit operand for short format insns */
2647 /* Rn16-push-S-anyof: m16c bit operand for short format insns */
2648 /* An16-push-S-anyof: m16c bit operand for short format insns */
2649 /* sentinel */
2650 { 0, 0, 0, 0, 0,
2651 { 0, { (const PTR) 0 } },
2652 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
2655 #undef A
2658 /* The instruction table. */
2660 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2661 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2662 #define A(a) (1 << CGEN_INSN_##a)
2663 #else
2664 #define A(a) (1 << CGEN_INSN_/**/a)
2665 #endif
2667 static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
2669 /* Special null first entry.
2670 A `num' value of zero is thus invalid.
2671 Also, the special `invalid' insn resides here. */
2672 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
2673 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2675 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2678 /* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
2680 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2683 /* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
2685 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2688 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2690 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2693 /* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
2695 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2698 /* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
2700 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2703 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2705 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2708 /* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
2710 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2713 /* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
2715 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2718 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
2720 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2723 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2725 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2728 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2730 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2733 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
2735 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2738 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2740 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2743 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2745 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2748 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
2750 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2753 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2755 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2758 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2760 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2763 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
2765 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2768 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
2770 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2773 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
2775 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2778 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
2780 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2783 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
2785 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2788 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
2790 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2793 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
2795 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2798 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
2800 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2803 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
2805 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2808 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
2810 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2813 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
2815 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2818 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
2820 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2823 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
2825 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2828 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
2830 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2833 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
2835 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2838 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
2840 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2843 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
2845 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2848 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
2850 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2853 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2855 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2858 /* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
2860 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2863 /* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
2865 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2868 /* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
2870 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2873 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2875 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2878 /* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
2880 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2883 /* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
2885 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2888 /* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
2890 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2893 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2895 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2898 /* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
2900 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2903 /* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
2905 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2908 /* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
2910 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2913 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
2915 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2918 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2920 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2923 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2925 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2928 /* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
2930 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2933 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
2935 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2938 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2940 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2943 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2945 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2948 /* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
2950 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2953 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
2955 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2958 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2960 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2963 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2965 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2968 /* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
2970 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2973 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
2975 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2978 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
2980 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2983 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
2985 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2988 /* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
2990 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2993 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
2995 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
2996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
2998 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
3000 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
3001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3003 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
3005 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
3006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3008 /* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
3010 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
3011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3013 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
3015 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3018 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
3020 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3023 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3025 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3028 /* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3030 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3033 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3035 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3038 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3040 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3043 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3045 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3048 /* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3050 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3053 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3055 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3058 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3060 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3063 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3065 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3068 /* extz ${Dsp-24-u16},${Dsp-40-u16} */
3070 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3073 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3075 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3078 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3080 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3083 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3085 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3088 /* extz ${Dsp-24-u16},${Dsp-40-u24} */
3090 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3093 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3095 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
3096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3098 /* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
3100 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
3101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3103 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3105 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
3106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3108 /* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
3110 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
3111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3113 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3115 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
3116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3118 /* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
3120 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
3121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3123 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3125 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
3126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3128 /* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3130 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
3131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3133 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3135 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
3136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3138 /* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3140 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
3141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3143 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3145 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
3146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3148 /* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3150 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
3151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3153 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3155 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
3156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3158 /* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3160 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
3161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3163 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3165 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
3166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3168 /* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3170 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
3171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3173 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3175 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
3176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3178 /* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3180 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
3181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3183 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3185 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
3186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3188 /* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3190 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
3191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3193 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3195 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
3196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3198 /* extz ${Dsp-24-u24},${Dsp-48-u16} */
3200 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
3201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3203 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3205 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
3206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3208 /* extz ${Dsp-24-u24},${Dsp-48-u24} */
3210 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
3211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3213 /* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3215 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
3216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3218 /* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3220 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
3221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3223 /* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3225 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
3226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3228 /* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3230 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
3231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3233 /* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3235 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
3236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3238 /* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3240 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
3241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3243 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3245 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
3246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3248 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3250 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
3251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3253 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3255 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
3256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3258 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3260 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
3261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3263 /* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3265 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
3266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3268 /* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3270 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
3271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3273 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3275 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
3276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3278 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3280 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
3281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3283 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3285 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
3286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3288 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3290 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
3291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3293 /* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3295 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
3296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3298 /* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3300 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
3301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3303 /* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3305 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
3306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3308 /* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3310 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
3311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3313 /* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
3315 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
3316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3318 /* extz [$Src32AnPrefixed],${Dsp-24-u16} */
3320 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
3321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3323 /* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
3325 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
3326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3328 /* extz [$Src32AnPrefixed],${Dsp-24-u24} */
3330 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
3331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3333 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3335 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3338 /* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
3340 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3343 /* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
3345 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3348 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3350 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3353 /* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
3355 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3358 /* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
3360 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3363 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3365 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3368 /* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
3370 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3373 /* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
3375 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3378 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
3380 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3383 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3385 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3388 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3390 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3393 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
3395 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3398 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3400 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3403 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3405 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3408 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
3410 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3413 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3415 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3418 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3420 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3423 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
3425 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3428 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
3430 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3433 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
3435 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3438 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
3440 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3443 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
3445 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3448 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
3450 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3453 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
3455 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3458 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
3460 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3463 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
3465 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3468 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
3470 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3473 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
3475 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3478 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
3480 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3483 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
3485 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3488 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
3490 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3493 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
3495 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3498 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
3500 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3503 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
3505 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3508 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
3510 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3513 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3515 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3518 /* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
3520 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3523 /* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
3525 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3528 /* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
3530 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3533 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3535 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3538 /* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
3540 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3543 /* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
3545 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3548 /* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
3550 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3553 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3555 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3558 /* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
3560 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3563 /* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
3565 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3568 /* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
3570 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3573 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
3575 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3578 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3580 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3583 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3585 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3588 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
3590 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3593 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
3595 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3598 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3600 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3603 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3605 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3608 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
3610 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3613 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
3615 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3618 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3620 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3623 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3625 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3628 /* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
3630 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3633 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
3635 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3638 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
3640 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3643 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
3645 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3648 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
3650 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3653 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
3655 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3658 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
3660 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3663 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
3665 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3668 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
3670 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3673 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
3675 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3678 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
3680 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3683 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3685 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3688 /* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3690 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3693 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3695 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3698 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3700 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3703 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3705 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3708 /* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3710 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3713 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3715 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3718 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3720 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3723 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3725 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3728 /* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
3730 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3733 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3735 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3738 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3740 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3743 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3745 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3748 /* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
3750 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3753 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3755 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
3756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3758 /* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
3760 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
3761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3763 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3765 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
3766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3768 /* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
3770 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
3771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3773 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3775 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
3776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3778 /* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
3780 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
3781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3783 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3785 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
3786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3788 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3790 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
3791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3793 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3795 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
3796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3798 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3800 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
3801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3803 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3805 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
3806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3808 /* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3810 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
3811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3813 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3815 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
3816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3818 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3820 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
3821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3823 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3825 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
3826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3828 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3830 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
3831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3833 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3835 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
3836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3838 /* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3840 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
3841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3843 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3845 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
3846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3848 /* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3850 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
3851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3853 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3855 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
3856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3858 /* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
3860 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
3861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3863 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3865 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
3866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3868 /* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
3870 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
3871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3873 /* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3875 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
3876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3878 /* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3880 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
3881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3883 /* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3885 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
3886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3888 /* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3890 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
3891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3893 /* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3895 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
3896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3898 /* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3900 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
3901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3903 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3905 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
3906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3908 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3910 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
3911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3913 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3915 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
3916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3918 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3920 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
3921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3923 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3925 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
3926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3928 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3930 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
3931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3933 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3935 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
3936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3938 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3940 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
3941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3943 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3945 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
3946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3948 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3950 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
3951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3953 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3955 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
3956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3958 /* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3960 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
3961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3963 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3965 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
3966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3968 /* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3970 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
3971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3973 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
3975 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
3976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3978 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
3980 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
3981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3983 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
3985 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
3986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3988 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
3990 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
3991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3993 /* exts.w $Dst32RnExtUnprefixedHI */
3995 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-HI", "exts.w", 16,
3996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
3998 /* exts.w $Dst32AnUnprefixedSI */
4000 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "exts32.w-16-ExtUnprefixed-dst32-An-direct-Unprefixed-SI", "exts.w", 16,
4001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4003 /* exts.w [$Dst32AnExtUnprefixed] */
4005 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-HI", "exts.w", 16,
4006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4008 /* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
4010 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-HI", "exts.w", 24,
4011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4013 /* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
4015 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-HI", "exts.w", 32,
4016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4018 /* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
4020 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-HI", "exts.w", 40,
4021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4023 /* exts.w ${Dsp-16-u8}[sb] */
4025 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-HI", "exts.w", 24,
4026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4028 /* exts.w ${Dsp-16-u16}[sb] */
4030 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-HI", "exts.w", 32,
4031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4033 /* exts.w ${Dsp-16-s8}[fb] */
4035 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-HI", "exts.w", 24,
4036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4038 /* exts.w ${Dsp-16-s16}[fb] */
4040 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-HI", "exts.w", 32,
4041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4043 /* exts.w ${Dsp-16-u16} */
4045 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-HI", "exts.w", 32,
4046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4048 /* exts.w ${Dsp-16-u24} */
4050 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-HI", "exts.w", 40,
4051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4053 /* exts.b $Dst32RnExtUnprefixedQI */
4055 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-QI", "exts.b", 16,
4056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4058 /* exts.b $Dst32AnUnprefixedHI */
4060 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "exts32.b-16-ExtUnprefixed-dst32-An-direct-Unprefixed-HI", "exts.b", 16,
4061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4063 /* exts.b [$Dst32AnExtUnprefixed] */
4065 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-QI", "exts.b", 16,
4066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4068 /* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
4070 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-QI", "exts.b", 24,
4071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4073 /* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
4075 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-QI", "exts.b", 32,
4076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4078 /* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
4080 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-QI", "exts.b", 40,
4081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4083 /* exts.b ${Dsp-16-u8}[sb] */
4085 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-QI", "exts.b", 24,
4086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4088 /* exts.b ${Dsp-16-u16}[sb] */
4090 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-QI", "exts.b", 32,
4091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4093 /* exts.b ${Dsp-16-s8}[fb] */
4095 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-QI", "exts.b", 24,
4096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4098 /* exts.b ${Dsp-16-s16}[fb] */
4100 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-QI", "exts.b", 32,
4101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4103 /* exts.b ${Dsp-16-u16} */
4105 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-QI", "exts.b", 32,
4106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4108 /* exts.b ${Dsp-16-u24} */
4110 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-QI", "exts.b", 40,
4111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4113 /* exts.b $Dst16RnExtQI */
4115 M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, "exts16.b-16-Ext-dst16-Rn-direct-Ext-QI", "exts.b", 16,
4116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
4118 /* exts.b [$Dst16An] */
4120 M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, "exts16.b-16-Ext-dst16-An-indirect-Ext-QI", "exts.b", 16,
4121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
4123 /* exts.b ${Dsp-16-u8}[$Dst16An] */
4125 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-An-relative-Ext-QI", "exts.b", 24,
4126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
4128 /* exts.b ${Dsp-16-u16}[$Dst16An] */
4130 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-An-relative-Ext-QI", "exts.b", 32,
4131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
4133 /* exts.b ${Dsp-16-u8}[sb] */
4135 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-SB-relative-Ext-QI", "exts.b", 24,
4136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
4138 /* exts.b ${Dsp-16-u16}[sb] */
4140 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-SB-relative-Ext-QI", "exts.b", 32,
4141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
4143 /* exts.b ${Dsp-16-s8}[fb] */
4145 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-FB-relative-Ext-QI", "exts.b", 24,
4146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
4148 /* exts.b ${Dsp-16-u16} */
4150 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-absolute-Ext-QI", "exts.b", 32,
4151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
4153 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4155 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4158 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
4160 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4163 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
4165 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4168 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4170 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4173 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
4175 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4178 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
4180 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4183 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4185 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4188 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4190 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4193 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4195 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4198 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4200 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4203 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4205 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4208 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4210 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4213 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4215 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4218 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4220 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4223 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4225 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4228 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4230 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4233 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4235 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4238 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4240 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4243 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4245 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4248 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4250 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4253 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4255 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4258 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4260 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4263 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4265 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4268 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
4270 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4273 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
4275 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4278 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
4280 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4283 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
4285 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4288 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
4290 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4293 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
4295 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4298 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
4300 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4303 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
4305 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4308 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
4310 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4313 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
4315 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4318 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
4320 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4323 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
4325 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4328 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
4330 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4333 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4335 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4338 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
4340 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4343 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
4345 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4348 /* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
4350 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4353 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4355 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4358 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
4360 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4363 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
4365 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4368 /* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
4370 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4373 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4375 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4378 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
4380 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4383 /* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
4385 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4388 /* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
4390 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4393 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4395 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4398 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4400 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4403 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4405 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4408 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
4410 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4413 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4415 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4418 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4420 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4423 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4425 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4428 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
4430 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4433 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4435 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4438 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4440 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4443 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4445 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4448 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
4450 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4453 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
4455 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4458 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
4460 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4463 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
4465 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4468 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
4470 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4473 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
4475 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4478 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
4480 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4483 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
4485 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4488 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
4490 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4493 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
4495 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4498 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
4500 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4503 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
4505 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4508 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
4510 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4513 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
4515 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4518 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
4520 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4523 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
4525 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4528 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
4530 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4533 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
4535 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4538 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
4540 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4543 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
4545 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4548 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
4550 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4553 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
4555 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4558 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
4560 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4563 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
4565 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4568 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
4570 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4573 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4575 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
4576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4578 /* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
4580 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
4581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4583 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4585 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
4586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4588 /* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
4590 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
4591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4593 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4595 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
4596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4598 /* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
4600 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
4601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4603 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
4605 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
4606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4608 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
4610 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
4611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4613 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
4615 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
4616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4618 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
4620 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
4621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4623 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
4625 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
4626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4628 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
4630 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
4631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4633 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
4635 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
4636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4638 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
4640 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
4641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4643 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
4645 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
4646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4648 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
4650 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
4651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4653 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
4655 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
4656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4658 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
4660 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
4661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4663 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
4665 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
4666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4668 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
4670 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
4671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4673 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
4675 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
4676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4678 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
4680 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
4681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4683 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
4685 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
4686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4688 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
4690 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
4691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4693 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
4695 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4698 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
4700 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4703 /* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4705 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4708 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
4710 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4713 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
4715 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4718 /* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4720 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4723 /* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
4725 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4728 /* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
4730 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4733 /* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4735 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4738 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4740 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4743 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4745 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4748 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
4750 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4753 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4755 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4758 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4760 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4763 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
4765 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4768 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4770 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4773 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4775 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4778 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
4780 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4783 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
4785 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4788 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
4790 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4793 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
4795 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4798 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
4800 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4803 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
4805 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4808 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
4810 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4813 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
4815 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4818 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
4820 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4823 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
4825 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4828 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
4830 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4833 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
4835 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4838 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
4840 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4843 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
4845 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4848 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
4850 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4853 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
4855 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4858 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
4860 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4863 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
4865 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4868 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
4870 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4873 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
4875 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4878 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
4880 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4883 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
4885 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4888 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
4890 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4893 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
4895 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4898 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
4900 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4903 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4905 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4908 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4910 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4913 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4915 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4918 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4920 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4923 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4925 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4928 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4930 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4933 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4935 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4938 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4940 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4943 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4945 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4948 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4950 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4953 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4955 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4958 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4960 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4963 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4965 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4968 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4970 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4973 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4975 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4978 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4980 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4983 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4985 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4988 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
4990 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4993 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
4995 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
4996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
4998 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
5000 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
5001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5003 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
5005 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
5006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5008 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
5010 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5013 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
5015 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5018 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
5020 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5023 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
5025 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5028 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5030 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5033 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5035 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5038 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
5040 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5043 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
5045 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5048 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
5050 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5053 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5055 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5058 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
5060 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5063 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
5065 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5068 /* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
5070 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5073 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5075 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5078 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
5080 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5083 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
5085 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5088 /* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
5090 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5093 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5095 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5098 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
5100 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5103 /* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
5105 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5108 /* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
5110 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5113 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5115 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5118 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5120 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5123 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5125 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5128 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
5130 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5133 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5135 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5138 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5140 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5143 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5145 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5148 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
5150 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5153 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5155 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5158 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5160 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5163 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5165 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5168 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
5170 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5173 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
5175 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5178 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5180 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5183 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
5185 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5188 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5190 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5193 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
5195 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5198 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5200 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5203 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
5205 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5208 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5210 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5213 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
5215 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5218 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5220 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5223 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
5225 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5228 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5230 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5233 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
5235 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5238 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
5240 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5243 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
5245 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5248 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
5250 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5253 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
5255 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5258 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5260 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5263 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
5265 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5268 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
5270 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5273 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
5275 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5278 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
5280 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5283 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
5285 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5288 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
5290 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5293 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5295 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
5296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5298 /* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
5300 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
5301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5303 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5305 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
5306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5308 /* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
5310 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
5311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5313 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5315 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
5316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5318 /* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
5320 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
5321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5323 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
5325 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
5326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5328 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
5330 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
5331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5333 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
5335 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
5336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5338 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
5340 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
5341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5343 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
5345 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
5346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5348 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
5350 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
5351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5353 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
5355 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
5356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5358 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
5360 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
5361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5363 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
5365 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
5366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5368 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
5370 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
5371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5373 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
5375 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
5376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5378 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
5380 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
5381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5383 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
5385 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
5386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5388 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
5390 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
5391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5393 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
5395 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
5396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5398 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
5400 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
5401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5403 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
5405 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
5406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5408 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
5410 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
5411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5413 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
5415 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5418 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
5420 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5423 /* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5425 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5428 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
5430 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5433 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
5435 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5438 /* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5440 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5443 /* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
5445 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5448 /* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
5450 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5453 /* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5455 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5458 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5460 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5463 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5465 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5468 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
5470 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5473 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5475 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5478 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5480 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5483 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
5485 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5488 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5490 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5493 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5495 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5498 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
5500 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5503 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
5505 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5508 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
5510 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5513 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
5515 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5518 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
5520 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5523 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
5525 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5528 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
5530 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5533 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
5535 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5538 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
5540 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5543 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
5545 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5548 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
5550 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5553 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
5555 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5558 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
5560 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5563 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
5565 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5568 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
5570 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5573 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
5575 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5578 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
5580 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5583 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
5585 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5588 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
5590 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
5593 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
5595 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5598 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
5600 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5603 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
5605 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5608 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
5610 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5613 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
5615 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5618 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
5620 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5623 /* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
5625 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5628 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
5630 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5633 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
5635 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5638 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
5640 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5643 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
5645 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5648 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
5650 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5653 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
5655 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5658 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
5660 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5663 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
5665 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5668 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
5670 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5673 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
5675 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5678 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
5680 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5683 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
5685 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5688 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
5690 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5693 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
5695 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5698 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
5700 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5703 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
5705 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5708 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
5710 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5713 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
5715 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5718 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5720 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5723 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5725 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5728 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
5730 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
5731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5733 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
5735 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
5736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5738 /* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
5740 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "xor.w", 32,
5741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5743 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
5745 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "xor.w", 32,
5746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5748 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
5750 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "xor.w", 32,
5751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5753 /* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
5755 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "xor.w", 32,
5756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5758 /* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
5760 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
5761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5763 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
5765 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
5766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5768 /* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
5770 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "xor.w", 32,
5771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5773 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
5775 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5778 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
5780 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5783 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
5785 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5788 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
5790 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5793 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
5795 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5798 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
5800 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5803 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
5805 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5808 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5810 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5813 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5815 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5818 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
5820 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5823 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5825 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5828 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5830 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5833 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
5835 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5838 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5840 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5843 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5845 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5848 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
5850 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5853 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5855 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5858 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
5860 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5863 /* xor.w${G} $Src16RnHI,$Dst16RnHI */
5865 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
5866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5868 /* xor.w${G} $Src16AnHI,$Dst16RnHI */
5870 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
5871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5873 /* xor.w${G} [$Src16An],$Dst16RnHI */
5875 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "xor.w", 16,
5876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5878 /* xor.w${G} $Src16RnHI,$Dst16AnHI */
5880 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "xor.w", 16,
5881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5883 /* xor.w${G} $Src16AnHI,$Dst16AnHI */
5885 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "xor.w", 16,
5886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5888 /* xor.w${G} [$Src16An],$Dst16AnHI */
5890 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "xor.w", 16,
5891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5893 /* xor.w${G} $Src16RnHI,[$Dst16An] */
5895 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
5896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5898 /* xor.w${G} $Src16AnHI,[$Dst16An] */
5900 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
5901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5903 /* xor.w${G} [$Src16An],[$Dst16An] */
5905 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "xor.w", 16,
5906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5908 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
5910 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5913 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
5915 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5918 /* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
5920 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5923 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
5925 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5928 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
5930 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5933 /* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
5935 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5938 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
5940 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5943 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
5945 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5948 /* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
5950 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5953 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
5955 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5958 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
5960 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5963 /* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
5965 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5968 /* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
5970 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5973 /* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
5975 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5978 /* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
5980 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5983 /* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
5985 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5988 /* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
5990 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5993 /* xor.w${G} [$Src16An],${Dsp-16-u16} */
5995 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
5998 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
6000 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6003 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
6005 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6008 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
6010 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6013 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
6015 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6018 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
6020 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6023 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
6025 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6028 /* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
6030 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6033 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
6035 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6038 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
6040 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6043 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
6045 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6048 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
6050 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6053 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
6055 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6058 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
6060 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6063 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
6065 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6068 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
6070 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6073 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
6075 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6078 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
6080 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6083 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
6085 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6088 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
6090 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6093 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
6095 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6098 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
6100 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6103 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
6105 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6108 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
6110 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6113 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
6115 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6118 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
6120 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6123 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
6125 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6128 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
6130 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6133 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
6135 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6138 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
6140 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6143 /* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
6145 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "xor.b", 32,
6146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6148 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
6150 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6153 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
6155 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6158 /* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
6160 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "xor.b", 32,
6161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6163 /* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
6165 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6168 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
6170 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6173 /* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
6175 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "xor.b", 32,
6176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6178 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
6180 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6183 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
6185 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6188 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
6190 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6193 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
6195 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6198 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
6200 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6203 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
6205 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6208 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
6210 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6213 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
6215 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6218 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
6220 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6223 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
6225 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6228 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
6230 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6233 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
6235 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6238 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
6240 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6243 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
6245 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6248 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
6250 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6253 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
6255 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6258 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
6260 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6263 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
6265 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6268 /* xor.b${G} $Src16RnQI,$Dst16RnQI */
6270 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6273 /* xor.b${G} $Src16AnQI,$Dst16RnQI */
6275 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6278 /* xor.b${G} [$Src16An],$Dst16RnQI */
6280 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "xor.b", 16,
6281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6283 /* xor.b${G} $Src16RnQI,$Dst16AnQI */
6285 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6288 /* xor.b${G} $Src16AnQI,$Dst16AnQI */
6290 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6293 /* xor.b${G} [$Src16An],$Dst16AnQI */
6295 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "xor.b", 16,
6296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6298 /* xor.b${G} $Src16RnQI,[$Dst16An] */
6300 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6303 /* xor.b${G} $Src16AnQI,[$Dst16An] */
6305 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6308 /* xor.b${G} [$Src16An],[$Dst16An] */
6310 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "xor.b", 16,
6311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6313 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
6315 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6318 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
6320 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6323 /* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
6325 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6328 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
6330 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6333 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
6335 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6338 /* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
6340 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6343 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
6345 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6348 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
6350 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6353 /* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
6355 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6358 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
6360 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6363 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
6365 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6368 /* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
6370 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6373 /* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
6375 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6378 /* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
6380 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6383 /* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
6385 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6388 /* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
6390 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6393 /* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
6395 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6398 /* xor.b${G} [$Src16An],${Dsp-16-u16} */
6400 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6403 /* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
6405 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
6406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6408 /* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
6410 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
6411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6413 /* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
6415 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
6416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6418 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6420 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 40,
6421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6423 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6425 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 40,
6426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6428 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6430 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 40,
6431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6433 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6435 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 48,
6436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6438 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6440 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 48,
6441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6443 /* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
6445 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 48,
6446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6448 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6450 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 48,
6451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6453 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6455 M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 56,
6456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6458 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
6460 M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 56,
6461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6463 /* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
6465 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
6466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6468 /* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
6470 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
6471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6473 /* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
6475 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
6476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6478 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6480 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 32,
6481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6483 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6485 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 32,
6486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6488 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6490 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 32,
6491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6493 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6495 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 40,
6496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6498 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6500 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 40,
6501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6503 /* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
6505 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 40,
6506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6508 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6510 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 40,
6511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6513 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6515 M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 48,
6516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6518 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
6520 M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 48,
6521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6523 /* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
6525 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-Rn-direct-HI", "xor.w", 32,
6526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6528 /* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
6530 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-An-direct-HI", "xor.w", 32,
6531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6533 /* xor.w${G} #${Imm-16-HI},[$Dst16An] */
6535 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "xor16.w-imm-G-basic-dst16-An-indirect-HI", "xor.w", 32,
6536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6538 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
6540 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "xor.w", 40,
6541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6543 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6545 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "xor.w", 40,
6546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6548 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6550 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "xor.w", 40,
6551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6553 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
6555 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "xor.w", 48,
6556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6558 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6560 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "xor.w", 48,
6561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6563 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6565 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "xor16.w-imm-G-16-16-dst16-16-16-absolute-HI", "xor.w", 48,
6566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6568 /* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
6570 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-Rn-direct-QI", "xor.b", 24,
6571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6573 /* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
6575 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-An-direct-QI", "xor.b", 24,
6576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6578 /* xor.b${G} #${Imm-16-QI},[$Dst16An] */
6580 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "xor16.b-imm-G-basic-dst16-An-indirect-QI", "xor.b", 24,
6581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6583 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
6585 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "xor.b", 32,
6586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6588 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6590 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "xor.b", 32,
6591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6593 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6595 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "xor.b", 32,
6596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6598 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
6600 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "xor.b", 40,
6601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6603 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6605 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "xor.b", 40,
6606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6608 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6610 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "xor16.b-imm-G-16-16-dst16-16-16-absolute-QI", "xor.b", 40,
6611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
6613 /* xchg.w r3,$Dst32RnUnprefixedHI */
6615 M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6618 /* xchg.w r3,$Dst32AnUnprefixedHI */
6620 M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6623 /* xchg.w r3,[$Dst32AnUnprefixed] */
6625 M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6628 /* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6630 M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6633 /* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6635 M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6638 /* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6640 M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6643 /* xchg.w r3,${Dsp-16-u8}[sb] */
6645 M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6648 /* xchg.w r3,${Dsp-16-u16}[sb] */
6650 M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6653 /* xchg.w r3,${Dsp-16-s8}[fb] */
6655 M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6658 /* xchg.w r3,${Dsp-16-s16}[fb] */
6660 M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6663 /* xchg.w r3,${Dsp-16-u16} */
6665 M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6668 /* xchg.w r3,${Dsp-16-u24} */
6670 M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6673 /* xchg.w r2,$Dst32RnUnprefixedHI */
6675 M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6678 /* xchg.w r2,$Dst32AnUnprefixedHI */
6680 M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6683 /* xchg.w r2,[$Dst32AnUnprefixed] */
6685 M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6688 /* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6690 M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6693 /* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6695 M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6698 /* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6700 M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6703 /* xchg.w r2,${Dsp-16-u8}[sb] */
6705 M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6708 /* xchg.w r2,${Dsp-16-u16}[sb] */
6710 M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6713 /* xchg.w r2,${Dsp-16-s8}[fb] */
6715 M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6718 /* xchg.w r2,${Dsp-16-s16}[fb] */
6720 M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6723 /* xchg.w r2,${Dsp-16-u16} */
6725 M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6728 /* xchg.w r2,${Dsp-16-u24} */
6730 M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6733 /* xchg.w a1,$Dst32RnUnprefixedHI */
6735 M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6738 /* xchg.w a1,$Dst32AnUnprefixedHI */
6740 M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6743 /* xchg.w a1,[$Dst32AnUnprefixed] */
6745 M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6748 /* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6750 M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6753 /* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6755 M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6758 /* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6760 M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6763 /* xchg.w a1,${Dsp-16-u8}[sb] */
6765 M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6768 /* xchg.w a1,${Dsp-16-u16}[sb] */
6770 M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6773 /* xchg.w a1,${Dsp-16-s8}[fb] */
6775 M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6778 /* xchg.w a1,${Dsp-16-s16}[fb] */
6780 M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6783 /* xchg.w a1,${Dsp-16-u16} */
6785 M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6788 /* xchg.w a1,${Dsp-16-u24} */
6790 M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6793 /* xchg.w a0,$Dst32RnUnprefixedHI */
6795 M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6798 /* xchg.w a0,$Dst32AnUnprefixedHI */
6800 M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6803 /* xchg.w a0,[$Dst32AnUnprefixed] */
6805 M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6808 /* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6810 M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6813 /* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6815 M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6818 /* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6820 M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6823 /* xchg.w a0,${Dsp-16-u8}[sb] */
6825 M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6828 /* xchg.w a0,${Dsp-16-u16}[sb] */
6830 M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6833 /* xchg.w a0,${Dsp-16-s8}[fb] */
6835 M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6838 /* xchg.w a0,${Dsp-16-s16}[fb] */
6840 M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6843 /* xchg.w a0,${Dsp-16-u16} */
6845 M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6848 /* xchg.w a0,${Dsp-16-u24} */
6850 M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6853 /* xchg.w r1,$Dst32RnUnprefixedHI */
6855 M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6858 /* xchg.w r1,$Dst32AnUnprefixedHI */
6860 M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6863 /* xchg.w r1,[$Dst32AnUnprefixed] */
6865 M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6868 /* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6870 M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6873 /* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6875 M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6878 /* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6880 M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6883 /* xchg.w r1,${Dsp-16-u8}[sb] */
6885 M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6888 /* xchg.w r1,${Dsp-16-u16}[sb] */
6890 M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6893 /* xchg.w r1,${Dsp-16-s8}[fb] */
6895 M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6898 /* xchg.w r1,${Dsp-16-s16}[fb] */
6900 M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6903 /* xchg.w r1,${Dsp-16-u16} */
6905 M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6908 /* xchg.w r1,${Dsp-16-u24} */
6910 M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6913 /* xchg.w r0,$Dst32RnUnprefixedHI */
6915 M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6918 /* xchg.w r0,$Dst32AnUnprefixedHI */
6920 M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6923 /* xchg.w r0,[$Dst32AnUnprefixed] */
6925 M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6928 /* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6930 M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6933 /* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6935 M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6938 /* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6940 M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6943 /* xchg.w r0,${Dsp-16-u8}[sb] */
6945 M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6948 /* xchg.w r0,${Dsp-16-u16}[sb] */
6950 M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6953 /* xchg.w r0,${Dsp-16-s8}[fb] */
6955 M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6958 /* xchg.w r0,${Dsp-16-s16}[fb] */
6960 M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6963 /* xchg.w r0,${Dsp-16-u16} */
6965 M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6968 /* xchg.w r0,${Dsp-16-u24} */
6970 M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6973 /* xchg.b r1h,$Dst32RnUnprefixedQI */
6975 M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6978 /* xchg.b r1h,$Dst32AnUnprefixedQI */
6980 M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6983 /* xchg.b r1h,[$Dst32AnUnprefixed] */
6985 M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6988 /* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6990 M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
6991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6993 /* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6995 M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
6996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
6998 /* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7000 M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7003 /* xchg.b r1h,${Dsp-16-u8}[sb] */
7005 M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7008 /* xchg.b r1h,${Dsp-16-u16}[sb] */
7010 M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7013 /* xchg.b r1h,${Dsp-16-s8}[fb] */
7015 M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7018 /* xchg.b r1h,${Dsp-16-s16}[fb] */
7020 M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7023 /* xchg.b r1h,${Dsp-16-u16} */
7025 M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7028 /* xchg.b r1h,${Dsp-16-u24} */
7030 M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7033 /* xchg.b r0h,$Dst32RnUnprefixedQI */
7035 M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7038 /* xchg.b r0h,$Dst32AnUnprefixedQI */
7040 M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7043 /* xchg.b r0h,[$Dst32AnUnprefixed] */
7045 M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7048 /* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7050 M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7053 /* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7055 M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7058 /* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7060 M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7063 /* xchg.b r0h,${Dsp-16-u8}[sb] */
7065 M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7068 /* xchg.b r0h,${Dsp-16-u16}[sb] */
7070 M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7073 /* xchg.b r0h,${Dsp-16-s8}[fb] */
7075 M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7078 /* xchg.b r0h,${Dsp-16-s16}[fb] */
7080 M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7083 /* xchg.b r0h,${Dsp-16-u16} */
7085 M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7088 /* xchg.b r0h,${Dsp-16-u24} */
7090 M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7093 /* xchg.b a1,$Dst32RnUnprefixedQI */
7095 M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7098 /* xchg.b a1,$Dst32AnUnprefixedQI */
7100 M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7103 /* xchg.b a1,[$Dst32AnUnprefixed] */
7105 M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7108 /* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7110 M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7113 /* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7115 M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7118 /* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7120 M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7123 /* xchg.b a1,${Dsp-16-u8}[sb] */
7125 M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7128 /* xchg.b a1,${Dsp-16-u16}[sb] */
7130 M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7133 /* xchg.b a1,${Dsp-16-s8}[fb] */
7135 M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7138 /* xchg.b a1,${Dsp-16-s16}[fb] */
7140 M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7143 /* xchg.b a1,${Dsp-16-u16} */
7145 M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7148 /* xchg.b a1,${Dsp-16-u24} */
7150 M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7153 /* xchg.b a0,$Dst32RnUnprefixedQI */
7155 M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7158 /* xchg.b a0,$Dst32AnUnprefixedQI */
7160 M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7163 /* xchg.b a0,[$Dst32AnUnprefixed] */
7165 M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7168 /* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7170 M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7173 /* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7175 M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7178 /* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7180 M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7183 /* xchg.b a0,${Dsp-16-u8}[sb] */
7185 M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7188 /* xchg.b a0,${Dsp-16-u16}[sb] */
7190 M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7193 /* xchg.b a0,${Dsp-16-s8}[fb] */
7195 M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7198 /* xchg.b a0,${Dsp-16-s16}[fb] */
7200 M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7203 /* xchg.b a0,${Dsp-16-u16} */
7205 M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7208 /* xchg.b a0,${Dsp-16-u24} */
7210 M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7213 /* xchg.b r1l,$Dst32RnUnprefixedQI */
7215 M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7218 /* xchg.b r1l,$Dst32AnUnprefixedQI */
7220 M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7223 /* xchg.b r1l,[$Dst32AnUnprefixed] */
7225 M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7228 /* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7230 M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7233 /* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7235 M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7238 /* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7240 M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7243 /* xchg.b r1l,${Dsp-16-u8}[sb] */
7245 M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7248 /* xchg.b r1l,${Dsp-16-u16}[sb] */
7250 M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7253 /* xchg.b r1l,${Dsp-16-s8}[fb] */
7255 M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7258 /* xchg.b r1l,${Dsp-16-s16}[fb] */
7260 M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7263 /* xchg.b r1l,${Dsp-16-u16} */
7265 M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7268 /* xchg.b r1l,${Dsp-16-u24} */
7270 M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7273 /* xchg.b r0l,$Dst32RnUnprefixedQI */
7275 M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7278 /* xchg.b r0l,$Dst32AnUnprefixedQI */
7280 M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7283 /* xchg.b r0l,[$Dst32AnUnprefixed] */
7285 M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7288 /* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7290 M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7293 /* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7295 M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7298 /* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7300 M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7303 /* xchg.b r0l,${Dsp-16-u8}[sb] */
7305 M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7308 /* xchg.b r0l,${Dsp-16-u16}[sb] */
7310 M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7313 /* xchg.b r0l,${Dsp-16-s8}[fb] */
7315 M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7318 /* xchg.b r0l,${Dsp-16-s16}[fb] */
7320 M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7323 /* xchg.b r0l,${Dsp-16-u16} */
7325 M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7328 /* xchg.b r0l,${Dsp-16-u24} */
7330 M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7333 /* xchg.w r3,$Dst16RnHI */
7335 M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, "xchg16w-r3-dst16-Rn-direct-HI", "xchg.w", 16,
7336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7338 /* xchg.w r3,$Dst16AnHI */
7340 M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, "xchg16w-r3-dst16-An-direct-HI", "xchg.w", 16,
7341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7343 /* xchg.w r3,[$Dst16An] */
7345 M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI, "xchg16w-r3-dst16-An-indirect-HI", "xchg.w", 16,
7346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7348 /* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
7350 M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-8-An-relative-HI", "xchg.w", 24,
7351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7353 /* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
7355 M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-16-An-relative-HI", "xchg.w", 32,
7356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7358 /* xchg.w r3,${Dsp-16-u8}[sb] */
7360 M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7363 /* xchg.w r3,${Dsp-16-u16}[sb] */
7365 M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7368 /* xchg.w r3,${Dsp-16-s8}[fb] */
7370 M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7373 /* xchg.w r3,${Dsp-16-u16} */
7375 M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, "xchg16w-r3-dst16-16-16-absolute-HI", "xchg.w", 32,
7376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7378 /* xchg.w r2,$Dst16RnHI */
7380 M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, "xchg16w-r2-dst16-Rn-direct-HI", "xchg.w", 16,
7381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7383 /* xchg.w r2,$Dst16AnHI */
7385 M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI, "xchg16w-r2-dst16-An-direct-HI", "xchg.w", 16,
7386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7388 /* xchg.w r2,[$Dst16An] */
7390 M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, "xchg16w-r2-dst16-An-indirect-HI", "xchg.w", 16,
7391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7393 /* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
7395 M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-8-An-relative-HI", "xchg.w", 24,
7396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7398 /* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
7400 M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-16-An-relative-HI", "xchg.w", 32,
7401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7403 /* xchg.w r2,${Dsp-16-u8}[sb] */
7405 M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7408 /* xchg.w r2,${Dsp-16-u16}[sb] */
7410 M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7413 /* xchg.w r2,${Dsp-16-s8}[fb] */
7415 M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7418 /* xchg.w r2,${Dsp-16-u16} */
7420 M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, "xchg16w-r2-dst16-16-16-absolute-HI", "xchg.w", 32,
7421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7423 /* xchg.w r1,$Dst16RnHI */
7425 M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI, "xchg16w-r1-dst16-Rn-direct-HI", "xchg.w", 16,
7426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7428 /* xchg.w r1,$Dst16AnHI */
7430 M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, "xchg16w-r1-dst16-An-direct-HI", "xchg.w", 16,
7431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7433 /* xchg.w r1,[$Dst16An] */
7435 M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, "xchg16w-r1-dst16-An-indirect-HI", "xchg.w", 16,
7436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7438 /* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
7440 M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-8-An-relative-HI", "xchg.w", 24,
7441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7443 /* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
7445 M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-16-An-relative-HI", "xchg.w", 32,
7446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7448 /* xchg.w r1,${Dsp-16-u8}[sb] */
7450 M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7453 /* xchg.w r1,${Dsp-16-u16}[sb] */
7455 M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7458 /* xchg.w r1,${Dsp-16-s8}[fb] */
7460 M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7463 /* xchg.w r1,${Dsp-16-u16} */
7465 M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32,
7466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7468 /* xchg.w r0,$Dst16RnHI */
7470 M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, "xchg16w-r0-dst16-Rn-direct-HI", "xchg.w", 16,
7471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7473 /* xchg.w r0,$Dst16AnHI */
7475 M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, "xchg16w-r0-dst16-An-direct-HI", "xchg.w", 16,
7476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7478 /* xchg.w r0,[$Dst16An] */
7480 M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, "xchg16w-r0-dst16-An-indirect-HI", "xchg.w", 16,
7481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7483 /* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
7485 M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-8-An-relative-HI", "xchg.w", 24,
7486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7488 /* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
7490 M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-16-An-relative-HI", "xchg.w", 32,
7491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7493 /* xchg.w r0,${Dsp-16-u8}[sb] */
7495 M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7498 /* xchg.w r0,${Dsp-16-u16}[sb] */
7500 M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7503 /* xchg.w r0,${Dsp-16-s8}[fb] */
7505 M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7508 /* xchg.w r0,${Dsp-16-u16} */
7510 M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, "xchg16w-r0-dst16-16-16-absolute-HI", "xchg.w", 32,
7511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7513 /* xchg.b r1h,$Dst16RnQI */
7515 M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, "xchg16b-r1h-dst16-Rn-direct-QI", "xchg.b", 16,
7516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7518 /* xchg.b r1h,$Dst16AnQI */
7520 M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, "xchg16b-r1h-dst16-An-direct-QI", "xchg.b", 16,
7521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7523 /* xchg.b r1h,[$Dst16An] */
7525 M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI, "xchg16b-r1h-dst16-An-indirect-QI", "xchg.b", 16,
7526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7528 /* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
7530 M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-An-relative-QI", "xchg.b", 24,
7531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7533 /* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
7535 M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-An-relative-QI", "xchg.b", 32,
7536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7538 /* xchg.b r1h,${Dsp-16-u8}[sb] */
7540 M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7543 /* xchg.b r1h,${Dsp-16-u16}[sb] */
7545 M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7548 /* xchg.b r1h,${Dsp-16-s8}[fb] */
7550 M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7553 /* xchg.b r1h,${Dsp-16-u16} */
7555 M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1h-dst16-16-16-absolute-QI", "xchg.b", 32,
7556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7558 /* xchg.b r1l,$Dst16RnQI */
7560 M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, "xchg16b-r1l-dst16-Rn-direct-QI", "xchg.b", 16,
7561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7563 /* xchg.b r1l,$Dst16AnQI */
7565 M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI, "xchg16b-r1l-dst16-An-direct-QI", "xchg.b", 16,
7566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7568 /* xchg.b r1l,[$Dst16An] */
7570 M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, "xchg16b-r1l-dst16-An-indirect-QI", "xchg.b", 16,
7571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7573 /* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
7575 M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-An-relative-QI", "xchg.b", 24,
7576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7578 /* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
7580 M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-An-relative-QI", "xchg.b", 32,
7581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7583 /* xchg.b r1l,${Dsp-16-u8}[sb] */
7585 M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7588 /* xchg.b r1l,${Dsp-16-u16}[sb] */
7590 M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7593 /* xchg.b r1l,${Dsp-16-s8}[fb] */
7595 M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7598 /* xchg.b r1l,${Dsp-16-u16} */
7600 M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1l-dst16-16-16-absolute-QI", "xchg.b", 32,
7601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7603 /* xchg.b r0h,$Dst16RnQI */
7605 M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI, "xchg16b-r0h-dst16-Rn-direct-QI", "xchg.b", 16,
7606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7608 /* xchg.b r0h,$Dst16AnQI */
7610 M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, "xchg16b-r0h-dst16-An-direct-QI", "xchg.b", 16,
7611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7613 /* xchg.b r0h,[$Dst16An] */
7615 M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, "xchg16b-r0h-dst16-An-indirect-QI", "xchg.b", 16,
7616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7618 /* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
7620 M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-An-relative-QI", "xchg.b", 24,
7621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7623 /* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
7625 M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-An-relative-QI", "xchg.b", 32,
7626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7628 /* xchg.b r0h,${Dsp-16-u8}[sb] */
7630 M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7633 /* xchg.b r0h,${Dsp-16-u16}[sb] */
7635 M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7638 /* xchg.b r0h,${Dsp-16-s8}[fb] */
7640 M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7643 /* xchg.b r0h,${Dsp-16-u16} */
7645 M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0h-dst16-16-16-absolute-QI", "xchg.b", 32,
7646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7648 /* xchg.b r0l,$Dst16RnQI */
7650 M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, "xchg16b-r0l-dst16-Rn-direct-QI", "xchg.b", 16,
7651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7653 /* xchg.b r0l,$Dst16AnQI */
7655 M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, "xchg16b-r0l-dst16-An-direct-QI", "xchg.b", 16,
7656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7658 /* xchg.b r0l,[$Dst16An] */
7660 M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, "xchg16b-r0l-dst16-An-indirect-QI", "xchg.b", 16,
7661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7663 /* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
7665 M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-An-relative-QI", "xchg.b", 24,
7666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7668 /* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
7670 M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-An-relative-QI", "xchg.b", 32,
7671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7673 /* xchg.b r0l,${Dsp-16-u8}[sb] */
7675 M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7678 /* xchg.b r0l,${Dsp-16-u16}[sb] */
7680 M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7683 /* xchg.b r0l,${Dsp-16-s8}[fb] */
7685 M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7688 /* xchg.b r0l,${Dsp-16-u16} */
7690 M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0l-dst16-16-16-absolute-QI", "xchg.b", 32,
7691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
7693 /* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
7695 M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "tst.w", 32,
7696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7698 /* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
7700 M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "tst.w", 32,
7701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7703 /* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
7705 M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "tst32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "tst.w", 40,
7706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7708 /* tst.w${S} #${Imm-8-HI},r0 */
7710 M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "tst32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "tst.w", 24,
7711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7713 /* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
7715 M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "tst.b", 24,
7716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7718 /* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
7720 M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "tst.b", 24,
7721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7723 /* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
7725 M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "tst32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "tst.b", 32,
7726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7728 /* tst.b${S} #${Imm-8-QI},r0l */
7730 M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "tst32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "tst.b", 16,
7731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7733 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7735 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7738 /* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
7740 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7743 /* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
7745 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7748 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7750 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7753 /* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
7755 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7758 /* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
7760 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7763 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7765 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7768 /* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
7770 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7773 /* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
7775 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7778 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
7780 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7783 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7785 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7788 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7790 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7793 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
7795 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7798 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7800 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7803 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7805 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7808 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
7810 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7813 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7815 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7818 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7820 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7823 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
7825 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7828 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
7830 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7833 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
7835 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7838 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
7840 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7843 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
7845 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7848 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
7850 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7853 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
7855 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7858 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
7860 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7863 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
7865 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7868 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
7870 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7873 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
7875 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7878 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
7880 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7883 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
7885 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7888 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
7890 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7893 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
7895 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7898 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
7900 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7903 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
7905 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7908 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
7910 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7913 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7915 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7918 /* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
7920 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7923 /* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
7925 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7928 /* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */
7930 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7933 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7935 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7938 /* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
7940 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7943 /* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
7945 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7948 /* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */
7950 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7953 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7955 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7958 /* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
7960 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7963 /* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
7965 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7968 /* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
7970 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7973 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
7975 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7978 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
7980 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7983 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
7985 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7988 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
7990 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7993 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
7995 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
7996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
7998 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8000 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
8001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8003 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8005 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
8006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8008 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8010 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
8011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8013 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8015 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8018 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8020 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8023 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8025 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8028 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8030 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8033 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8035 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8038 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8040 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8043 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8045 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8048 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8050 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8053 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8055 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8058 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8060 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8063 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8065 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8068 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8070 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8073 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8075 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8078 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8080 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8083 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8085 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8088 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8090 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8093 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8095 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8098 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8100 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8103 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8105 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8108 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8110 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8113 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8115 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8118 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8120 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8123 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8125 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8128 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */
8130 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8133 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8135 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8138 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8140 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8143 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8145 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8148 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */
8150 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8153 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8155 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
8156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8158 /* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */
8160 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
8161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8163 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8165 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
8166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8168 /* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */
8170 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
8171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8173 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8175 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
8176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8178 /* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
8180 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
8181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8183 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8185 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
8186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8188 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8190 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
8191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8193 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8195 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
8196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8198 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8200 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
8201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8203 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8205 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
8206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8208 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8210 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
8211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8213 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8215 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
8216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8218 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8220 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
8221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8223 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8225 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
8226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8228 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8230 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
8231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8233 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8235 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
8236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8238 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8240 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
8241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8243 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8245 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
8246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8248 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8250 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
8251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8253 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8255 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
8256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8258 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */
8260 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
8261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8263 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8265 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
8266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8268 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */
8270 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
8271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8273 /* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
8275 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8278 /* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
8280 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8283 /* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
8285 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8288 /* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
8290 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8293 /* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
8295 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8298 /* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
8300 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8303 /* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
8305 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8308 /* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
8310 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8313 /* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
8315 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8318 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8320 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8323 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8325 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8328 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
8330 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8333 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8335 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8338 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8340 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8343 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
8345 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8348 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8350 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8353 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8355 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8358 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
8360 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8363 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
8365 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8368 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
8370 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8373 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
8375 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8378 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
8380 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8383 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
8385 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8388 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
8390 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8393 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
8395 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8398 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
8400 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8403 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
8405 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8408 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
8410 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8413 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
8415 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8418 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
8420 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8423 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */
8425 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8428 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */
8430 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8433 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */
8435 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8438 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */
8440 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8443 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */
8445 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8448 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */
8450 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8453 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8455 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8458 /* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
8460 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8463 /* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
8465 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8468 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8470 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8473 /* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
8475 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8478 /* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
8480 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8483 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8485 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8488 /* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
8490 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8493 /* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
8495 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8498 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
8500 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8503 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8505 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8508 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8510 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8513 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
8515 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8518 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8520 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8523 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8525 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8528 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
8530 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8533 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8535 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8538 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8540 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8543 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
8545 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8548 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
8550 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8553 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
8555 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8558 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
8560 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8563 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
8565 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8568 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
8570 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8573 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
8575 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8578 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
8580 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8583 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
8585 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8588 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
8590 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8593 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
8595 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8598 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
8600 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8603 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
8605 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8608 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
8610 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8613 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
8615 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8618 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
8620 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8623 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
8625 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8628 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
8630 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8633 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8635 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8638 /* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
8640 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8643 /* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
8645 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8648 /* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */
8650 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8653 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8655 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8658 /* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
8660 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8663 /* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
8665 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8668 /* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */
8670 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8673 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8675 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8678 /* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
8680 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8683 /* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
8685 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8688 /* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
8690 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8693 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
8695 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8698 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8700 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8703 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8705 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8708 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8710 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8713 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8715 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8718 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8720 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8723 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8725 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8728 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8730 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8733 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8735 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8738 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8740 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8743 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8745 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8748 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8750 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8753 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8755 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8758 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8760 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8763 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8765 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8768 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8770 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8773 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8775 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8778 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8780 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8783 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8785 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8788 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8790 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8793 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8795 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8798 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8800 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8803 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8805 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8808 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8810 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8813 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8815 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8818 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8820 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8823 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8825 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8828 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8830 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8833 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8835 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8838 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8840 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8843 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8845 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8848 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */
8850 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8853 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8855 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8858 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8860 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8863 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8865 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8868 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */
8870 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8873 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8875 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
8876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8878 /* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */
8880 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
8881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8883 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8885 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
8886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8888 /* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */
8890 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
8891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8893 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8895 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
8896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8898 /* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
8900 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
8901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8903 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8905 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
8906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8908 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8910 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
8911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8913 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8915 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
8916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8918 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8920 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
8921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8923 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8925 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
8926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8928 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8930 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
8931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8933 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8935 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
8936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8938 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8940 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
8941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8943 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8945 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
8946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8948 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8950 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
8951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8953 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8955 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
8956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8958 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8960 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
8961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8963 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8965 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
8966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8968 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8970 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
8971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8973 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8975 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
8976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8978 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */
8980 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
8981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8983 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8985 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
8986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8988 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */
8990 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
8991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8993 /* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
8995 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
8996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
8998 /* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
9000 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
9001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9003 /* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
9005 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
9006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9008 /* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
9010 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9013 /* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
9015 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9018 /* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
9020 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9023 /* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
9025 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9028 /* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
9030 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9033 /* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
9035 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9038 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9040 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9043 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9045 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9048 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
9050 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9053 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9055 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9058 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9060 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9063 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
9065 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9068 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9070 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9073 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9075 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9078 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
9080 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9083 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
9085 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9088 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
9090 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9093 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
9095 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9098 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
9100 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9103 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
9105 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9108 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
9110 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9113 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
9115 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9118 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
9120 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9123 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
9125 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9128 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
9130 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9133 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
9135 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9138 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
9140 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9143 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */
9145 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9148 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */
9150 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9153 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */
9155 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9158 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */
9160 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9163 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */
9165 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9168 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */
9170 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9173 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
9175 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9178 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
9180 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9183 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
9185 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9188 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
9190 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9193 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
9195 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9198 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
9200 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9203 /* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9205 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9208 /* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9210 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9213 /* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9215 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9218 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9220 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9223 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9225 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9228 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9230 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9233 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9235 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9238 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9240 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9243 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9245 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9248 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9250 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9253 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9255 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9258 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9260 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9263 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9265 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9268 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9270 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9273 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9275 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9278 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9280 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9283 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9285 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9288 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9290 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9293 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9295 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9298 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9300 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9303 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9305 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9308 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
9310 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
9311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9313 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
9315 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
9316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9318 /* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
9320 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "tst.w", 32,
9321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9323 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
9325 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "tst.w", 32,
9326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9328 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
9330 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "tst.w", 32,
9331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9333 /* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
9335 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "tst.w", 32,
9336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9338 /* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9340 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
9341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9343 /* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9345 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
9346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9348 /* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
9350 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "tst.w", 32,
9351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9353 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9355 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9358 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9360 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9363 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9365 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9368 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9370 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9373 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9375 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9378 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9380 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9383 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9385 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9388 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9390 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9393 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9395 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9398 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9400 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9403 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9405 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9408 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9410 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9413 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9415 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9418 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9420 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9423 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9425 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9428 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9430 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9433 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9435 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9438 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
9440 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9443 /* tst.w${X} $Src16RnHI,$Dst16RnHI */
9445 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
9446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9448 /* tst.w${X} $Src16AnHI,$Dst16RnHI */
9450 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
9451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9453 /* tst.w${X} [$Src16An],$Dst16RnHI */
9455 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "tst.w", 16,
9456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9458 /* tst.w${X} $Src16RnHI,$Dst16AnHI */
9460 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "tst.w", 16,
9461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9463 /* tst.w${X} $Src16AnHI,$Dst16AnHI */
9465 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "tst.w", 16,
9466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9468 /* tst.w${X} [$Src16An],$Dst16AnHI */
9470 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "tst.w", 16,
9471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9473 /* tst.w${X} $Src16RnHI,[$Dst16An] */
9475 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
9476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9478 /* tst.w${X} $Src16AnHI,[$Dst16An] */
9480 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
9481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9483 /* tst.w${X} [$Src16An],[$Dst16An] */
9485 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "tst.w", 16,
9486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9488 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
9490 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9493 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
9495 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9498 /* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9500 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9503 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
9505 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9508 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
9510 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9513 /* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9515 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9518 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
9520 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9523 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
9525 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9528 /* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
9530 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9533 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
9535 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9538 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
9540 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9543 /* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
9545 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9548 /* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
9550 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9553 /* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
9555 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9558 /* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
9560 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9563 /* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
9565 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9568 /* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
9570 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9573 /* tst.w${X} [$Src16An],${Dsp-16-u16} */
9575 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9578 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
9580 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9583 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
9585 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9588 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
9590 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9593 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
9595 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9598 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
9600 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9603 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
9605 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9608 /* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9610 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9613 /* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9615 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9618 /* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9620 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9623 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9625 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9628 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9630 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9633 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9635 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9638 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9640 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9643 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9645 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9648 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9650 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9653 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9655 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9658 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9660 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9663 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9665 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9668 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9670 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9673 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9675 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9678 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9680 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9683 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9685 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9688 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9690 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9693 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9695 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9698 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9700 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9703 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9705 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9708 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9710 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9713 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
9715 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
9716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9718 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
9720 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
9721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9723 /* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
9725 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "tst.b", 32,
9726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9728 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
9730 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "tst.b", 32,
9731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9733 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
9735 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "tst.b", 32,
9736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9738 /* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
9740 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "tst.b", 32,
9741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9743 /* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9745 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
9746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9748 /* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9750 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
9751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9753 /* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
9755 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "tst.b", 32,
9756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9758 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9760 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9763 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9765 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9768 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9770 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9773 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9775 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9778 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9780 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9783 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9785 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9788 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9790 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9793 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9795 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9798 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9800 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9803 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9805 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9808 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9810 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9813 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9815 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9818 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9820 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9823 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9825 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9828 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9830 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9833 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9835 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9838 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9840 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9843 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
9845 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9848 /* tst.b${X} $Src16RnQI,$Dst16RnQI */
9850 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
9851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9853 /* tst.b${X} $Src16AnQI,$Dst16RnQI */
9855 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
9856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9858 /* tst.b${X} [$Src16An],$Dst16RnQI */
9860 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "tst.b", 16,
9861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9863 /* tst.b${X} $Src16RnQI,$Dst16AnQI */
9865 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "tst.b", 16,
9866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9868 /* tst.b${X} $Src16AnQI,$Dst16AnQI */
9870 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "tst.b", 16,
9871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9873 /* tst.b${X} [$Src16An],$Dst16AnQI */
9875 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "tst.b", 16,
9876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9878 /* tst.b${X} $Src16RnQI,[$Dst16An] */
9880 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
9881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9883 /* tst.b${X} $Src16AnQI,[$Dst16An] */
9885 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
9886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9888 /* tst.b${X} [$Src16An],[$Dst16An] */
9890 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "tst.b", 16,
9891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9893 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
9895 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9898 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
9900 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9903 /* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9905 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9908 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
9910 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9913 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
9915 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9918 /* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9920 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9923 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
9925 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9928 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
9930 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9933 /* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
9935 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9938 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
9940 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9943 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
9945 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9948 /* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
9950 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9953 /* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
9955 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9958 /* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
9960 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9963 /* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
9965 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9968 /* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
9970 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9973 /* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
9975 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9978 /* tst.b${X} [$Src16An],${Dsp-16-u16} */
9980 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
9983 /* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
9985 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "tst.w", 32,
9986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9988 /* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
9990 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "tst.w", 32,
9991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9993 /* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
9995 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "tst.w", 32,
9996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
9998 /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10000 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "tst.w", 40,
10001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10003 /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
10005 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "tst.w", 40,
10006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10008 /* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
10010 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "tst.w", 40,
10011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10013 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10015 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "tst.w", 48,
10016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10018 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
10020 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "tst.w", 48,
10021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10023 /* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
10025 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "tst.w", 48,
10026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10028 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
10030 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "tst.w", 48,
10031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10033 /* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10035 M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "tst.w", 56,
10036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10038 /* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */
10040 M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "tst.w", 56,
10041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10043 /* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
10045 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "tst.b", 24,
10046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10048 /* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
10050 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "tst.b", 24,
10051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10053 /* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
10055 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "tst.b", 24,
10056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10058 /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10060 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "tst.b", 32,
10061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10063 /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10065 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "tst.b", 32,
10066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10068 /* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10070 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "tst.b", 32,
10071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10073 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10075 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "tst.b", 40,
10076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10078 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10080 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "tst.b", 40,
10081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10083 /* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
10085 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "tst.b", 40,
10086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10088 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
10090 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "tst.b", 40,
10091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10093 /* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10095 M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "tst.b", 48,
10096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10098 /* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */
10100 M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "tst.b", 48,
10101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10103 /* tst.w${G} #${Imm-16-HI},$Dst16RnHI */
10105 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-Rn-direct-HI", "tst.w", 32,
10106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10108 /* tst.w${G} #${Imm-16-HI},$Dst16AnHI */
10110 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-An-direct-HI", "tst.w", 32,
10111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10113 /* tst.w${G} #${Imm-16-HI},[$Dst16An] */
10115 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "tst16.w-imm-G-basic-dst16-An-indirect-HI", "tst.w", 32,
10116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10118 /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
10120 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "tst.w", 40,
10121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10123 /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
10125 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "tst.w", 40,
10126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10128 /* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
10130 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "tst.w", 40,
10131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10133 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
10135 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "tst.w", 48,
10136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10138 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
10140 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "tst.w", 48,
10141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10143 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
10145 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "tst16.w-imm-G-16-16-dst16-16-16-absolute-HI", "tst.w", 48,
10146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10148 /* tst.b${G} #${Imm-16-QI},$Dst16RnQI */
10150 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-Rn-direct-QI", "tst.b", 24,
10151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10153 /* tst.b${G} #${Imm-16-QI},$Dst16AnQI */
10155 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-An-direct-QI", "tst.b", 24,
10156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10158 /* tst.b${G} #${Imm-16-QI},[$Dst16An] */
10160 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "tst16.b-imm-G-basic-dst16-An-indirect-QI", "tst.b", 24,
10161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10163 /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
10165 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "tst.b", 32,
10166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10168 /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10170 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "tst.b", 32,
10171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10173 /* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10175 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "tst.b", 32,
10176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10178 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
10180 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "tst.b", 40,
10181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10183 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10185 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "tst.b", 40,
10186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10188 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
10190 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "tst16.b-imm-G-16-16-dst16-16-16-absolute-QI", "tst.b", 40,
10191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
10193 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10195 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10198 /* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
10200 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10203 /* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
10205 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10208 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10210 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10213 /* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
10215 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10218 /* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
10220 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10223 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10225 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10228 /* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
10230 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10233 /* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
10235 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10238 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10240 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10243 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10245 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10248 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10250 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10253 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10255 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10258 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10260 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10263 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10265 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10268 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10270 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10273 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10275 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10278 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10280 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10283 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
10285 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10288 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
10290 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10293 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
10295 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10298 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
10300 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10303 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
10305 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10308 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
10310 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10313 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
10315 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10318 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
10320 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10323 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
10325 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10328 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
10330 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10333 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
10335 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10338 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
10340 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10343 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
10345 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10348 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
10350 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10353 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
10355 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10358 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
10360 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10363 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
10365 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10368 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
10370 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10373 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10375 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10378 /* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
10380 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10383 /* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
10385 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10388 /* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
10390 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10393 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10395 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10398 /* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
10400 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10403 /* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
10405 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10408 /* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
10410 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10413 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10415 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10418 /* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
10420 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10423 /* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
10425 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10428 /* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
10430 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10433 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10435 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10438 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10440 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10443 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10445 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10448 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
10450 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10453 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10455 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10458 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10460 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10463 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10465 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10468 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
10470 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10473 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10475 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10478 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10480 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10483 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10485 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10488 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10490 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10493 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10495 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10498 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10500 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10503 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10505 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10508 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10510 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10513 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10515 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10518 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10520 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10523 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10525 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10528 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10530 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10533 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10535 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10538 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10540 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10543 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10545 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10548 /* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10550 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10553 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10555 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10558 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10560 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10563 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10565 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10568 /* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10570 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10573 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10575 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10578 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10580 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10583 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
10585 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10588 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
10590 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10593 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
10595 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10598 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
10600 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10603 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
10605 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10608 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
10610 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10613 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10615 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
10616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10618 /* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
10620 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
10621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10623 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10625 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
10626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10628 /* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
10630 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
10631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10633 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10635 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
10636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10638 /* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
10640 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
10641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10643 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
10645 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
10646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10648 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
10650 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
10651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10653 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
10655 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
10656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10658 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
10660 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
10661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10663 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
10665 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
10666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10668 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
10670 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
10671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10673 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
10675 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
10676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10678 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
10680 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
10681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10683 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
10685 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
10686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10688 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
10690 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
10691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10693 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
10695 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
10696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10698 /* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
10700 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
10701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10703 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
10705 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
10706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10708 /* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
10710 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
10711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10713 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
10715 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
10716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10718 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
10720 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
10721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10723 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
10725 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
10726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10728 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
10730 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
10731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10733 /* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
10735 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10738 /* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
10740 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10743 /* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10745 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10748 /* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
10750 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10753 /* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
10755 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10758 /* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10760 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10763 /* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
10765 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10768 /* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
10770 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10773 /* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10775 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10778 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10780 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10783 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10785 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10788 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
10790 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10793 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10795 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10798 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10800 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10803 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
10805 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10808 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10810 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10813 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10815 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10818 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
10820 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10823 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
10825 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10828 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
10830 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10833 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
10835 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10838 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
10840 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10843 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
10845 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10848 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
10850 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10853 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
10855 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10858 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
10860 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10863 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
10865 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10868 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
10870 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10873 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
10875 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10878 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
10880 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10883 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
10885 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10888 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
10890 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10893 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
10895 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10898 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
10900 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10903 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
10905 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10908 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
10910 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10913 /* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
10915 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10918 /* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
10920 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "subx", 24,
10921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10923 /* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
10925 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10928 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10930 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "subx", 32,
10931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10933 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10935 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 32,
10936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10938 /* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10940 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 32,
10941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10943 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10945 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "subx", 40,
10946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10948 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10950 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 40,
10951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10953 /* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
10955 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 40,
10956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10958 /* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
10960 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "subx", 40,
10961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10963 /* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10965 M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "subx", 48,
10966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10968 /* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
10970 M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "subx", 48,
10971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10973 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
10975 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stzx.w", 48,
10976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10978 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
10980 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stzx.w", 48,
10981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10983 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
10985 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stzx.w", 48,
10986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10988 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10990 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stzx.w", 56,
10991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10993 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
10995 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stzx.w", 56,
10996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
10998 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
11000 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stzx.w", 56,
11001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11003 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11005 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stzx.w", 64,
11006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11008 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
11010 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stzx.w", 64,
11011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11013 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
11015 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stzx.w", 64,
11016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11018 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
11020 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stzx.w", 64,
11021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11023 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11025 M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stzx.w", 72,
11026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11028 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
11030 M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stzx.w", 72,
11031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11033 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
11035 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stzx.b", 32,
11036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11038 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
11040 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stzx.b", 32,
11041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11043 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
11045 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stzx.b", 32,
11046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11048 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11050 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stzx.b", 40,
11051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11053 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
11055 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stzx.b", 40,
11056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11058 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
11060 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stzx.b", 40,
11061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11063 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11065 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stzx.b", 48,
11066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11068 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
11070 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stzx.b", 48,
11071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11073 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
11075 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stzx.b", 48,
11076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11078 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
11080 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stzx.b", 48,
11081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11083 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11085 M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stzx.b", 56,
11086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11088 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
11090 M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stzx.b", 56,
11091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11093 /* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11095 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stz.w", 32,
11096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11098 /* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11100 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stz.w", 32,
11101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11103 /* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11105 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stz.w", 32,
11106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11108 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11110 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stz.w", 40,
11111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11113 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11115 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stz.w", 40,
11116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11118 /* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11120 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stz.w", 40,
11121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11123 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11125 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stz.w", 48,
11126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11128 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11130 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stz.w", 48,
11131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11133 /* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11135 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stz.w", 48,
11136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11138 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11140 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stz.w", 48,
11141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11143 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11145 M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stz.w", 56,
11146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11148 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11150 M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stz.w", 56,
11151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11153 /* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11155 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stz.b", 24,
11156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11158 /* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11160 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stz.b", 24,
11161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11163 /* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11165 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stz.b", 24,
11166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11168 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11170 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stz.b", 32,
11171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11173 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11175 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stz.b", 32,
11176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11178 /* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11180 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stz.b", 32,
11181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11183 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11185 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stz.b", 40,
11186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11188 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11190 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stz.b", 40,
11191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11193 /* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11195 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stz.b", 40,
11196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11198 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11200 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stz.b", 40,
11201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11203 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11205 M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stz.b", 48,
11206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11208 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11210 M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stz.b", 48,
11211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11213 /* stz${S} #${Imm-8-QI},r0l */
11215 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stz", 16,
11216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11218 /* stz${S} #${Imm-8-QI},r0h */
11220 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stz", 16,
11221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11223 /* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11225 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stz", 24,
11226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11228 /* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11230 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stz", 24,
11231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11233 /* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
11235 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stz", 32,
11236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11238 /* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11240 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stnz.w", 32,
11241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11243 /* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11245 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stnz.w", 32,
11246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11248 /* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11250 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stnz.w", 32,
11251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11253 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11255 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stnz.w", 40,
11256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11258 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11260 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stnz.w", 40,
11261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11263 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11265 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stnz.w", 40,
11266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11268 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11270 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stnz.w", 48,
11271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11273 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11275 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stnz.w", 48,
11276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11278 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11280 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stnz.w", 48,
11281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11283 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11285 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stnz.w", 48,
11286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11288 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11290 M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stnz.w", 56,
11291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11293 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11295 M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stnz.w", 56,
11296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11298 /* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11300 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stnz.b", 24,
11301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11303 /* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11305 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stnz.b", 24,
11306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11308 /* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11310 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stnz.b", 24,
11311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11313 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11315 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stnz.b", 32,
11316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11318 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11320 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stnz.b", 32,
11321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11323 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11325 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stnz.b", 32,
11326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11328 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11330 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stnz.b", 40,
11331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11333 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11335 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stnz.b", 40,
11336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11338 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11340 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stnz.b", 40,
11341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11343 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11345 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stnz.b", 40,
11346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11348 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11350 M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stnz.b", 48,
11351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11353 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11355 M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stnz.b", 48,
11356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11358 /* stnz${S} #${Imm-8-QI},r0l */
11360 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stnz", 16,
11361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11363 /* stnz${S} #${Imm-8-QI},r0h */
11365 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stnz", 16,
11366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11368 /* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11370 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stnz", 24,
11371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11373 /* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11375 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stnz", 24,
11376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11378 /* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
11380 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stnz", 32,
11381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11383 /* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11385 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shlnc.l", 24,
11386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11388 /* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11390 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shlnc.l", 24,
11391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11393 /* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11395 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shlnc.l", 24,
11396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11398 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11400 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shlnc.l", 32,
11401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11403 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11405 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shlnc.l", 32,
11406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11408 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11410 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shlnc.l", 32,
11411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11413 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11415 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shlnc.l", 40,
11416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11418 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11420 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shlnc.l", 40,
11421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11423 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11425 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shlnc.l", 40,
11426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11428 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11430 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shlnc.l", 40,
11431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11433 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11435 M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shlnc.l", 48,
11436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11438 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11440 M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shlnc.l", 48,
11441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11443 /* shl.l r1h,$Dst32RnUnprefixedSI */
11445 M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-Rn-direct-Unprefixed-SI", "shl.l", 16,
11446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11448 /* shl.l r1h,$Dst32AnUnprefixedSI */
11450 M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-direct-Unprefixed-SI", "shl.l", 16,
11451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11453 /* shl.l r1h,[$Dst32AnUnprefixed] */
11455 M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-indirect-Unprefixed-SI", "shl.l", 16,
11456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11458 /* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11460 M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 24,
11461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11463 /* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11465 M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 32,
11466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11468 /* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11470 M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 40,
11471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11473 /* shl.l r1h,${Dsp-16-u8}[sb] */
11475 M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 24,
11476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11478 /* shl.l r1h,${Dsp-16-u16}[sb] */
11480 M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 32,
11481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11483 /* shl.l r1h,${Dsp-16-s8}[fb] */
11485 M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 24,
11486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11488 /* shl.l r1h,${Dsp-16-s16}[fb] */
11490 M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 32,
11491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11493 /* shl.l r1h,${Dsp-16-u16} */
11495 M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 32,
11496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11498 /* shl.l r1h,${Dsp-16-u24} */
11500 M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 40,
11501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11503 /* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11505 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shl.l", 24,
11506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11508 /* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11510 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shl.l", 24,
11511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11513 /* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11515 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shl.l", 24,
11516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11518 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11520 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 32,
11521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11523 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11525 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 32,
11526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11528 /* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11530 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 32,
11531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11533 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11535 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 40,
11536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11538 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11540 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 40,
11541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11543 /* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11545 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 40,
11546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11548 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11550 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 40,
11551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11553 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11555 M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 48,
11556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11558 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11560 M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 48,
11561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11563 /* shl.w r1h,$Dst32RnUnprefixedHI */
11565 M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
11566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11568 /* shl.w r1h,$Dst32AnUnprefixedHI */
11570 M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
11571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11573 /* shl.w r1h,[$Dst32AnUnprefixed] */
11575 M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
11576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11578 /* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11580 M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
11581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11583 /* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11585 M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
11586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11588 /* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11590 M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
11591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11593 /* shl.w r1h,${Dsp-16-u8}[sb] */
11595 M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
11596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11598 /* shl.w r1h,${Dsp-16-u16}[sb] */
11600 M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
11601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11603 /* shl.w r1h,${Dsp-16-s8}[fb] */
11605 M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
11606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11608 /* shl.w r1h,${Dsp-16-s16}[fb] */
11610 M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
11611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11613 /* shl.w r1h,${Dsp-16-u16} */
11615 M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
11616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11618 /* shl.w r1h,${Dsp-16-u24} */
11620 M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
11621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11623 /* shl.b r1h,$Dst32RnUnprefixedQI */
11625 M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
11626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11628 /* shl.b r1h,$Dst32AnUnprefixedQI */
11630 M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
11631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11633 /* shl.b r1h,[$Dst32AnUnprefixed] */
11635 M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
11636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11638 /* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11640 M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
11641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11643 /* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11645 M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
11646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11648 /* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11650 M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
11651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11653 /* shl.b r1h,${Dsp-16-u8}[sb] */
11655 M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
11656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11658 /* shl.b r1h,${Dsp-16-u16}[sb] */
11660 M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
11661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11663 /* shl.b r1h,${Dsp-16-s8}[fb] */
11665 M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
11666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11668 /* shl.b r1h,${Dsp-16-s16}[fb] */
11670 M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
11671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11673 /* shl.b r1h,${Dsp-16-u16} */
11675 M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
11676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11678 /* shl.b r1h,${Dsp-16-u24} */
11680 M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
11681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11683 /* shl.w r1h,$Dst16RnHI */
11685 M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI, "shl16.w-dst-dst16-Rn-direct-HI", "shl.w", 16,
11686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11688 /* shl.w r1h,$Dst16AnHI */
11690 M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, "shl16.w-dst-dst16-An-direct-HI", "shl.w", 16,
11691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11693 /* shl.w r1h,[$Dst16An] */
11695 M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, "shl16.w-dst-dst16-An-indirect-HI", "shl.w", 16,
11696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11698 /* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
11700 M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-8-An-relative-HI", "shl.w", 24,
11701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11703 /* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
11705 M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-16-An-relative-HI", "shl.w", 32,
11706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11708 /* shl.w r1h,${Dsp-16-u8}[sb] */
11710 M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-SB-relative-HI", "shl.w", 24,
11711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11713 /* shl.w r1h,${Dsp-16-u16}[sb] */
11715 M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-16-SB-relative-HI", "shl.w", 32,
11716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11718 /* shl.w r1h,${Dsp-16-s8}[fb] */
11720 M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-FB-relative-HI", "shl.w", 24,
11721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11723 /* shl.w r1h,${Dsp-16-u16} */
11725 M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI, "shl16.w-dst-dst16-16-16-absolute-HI", "shl.w", 32,
11726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11728 /* shl.b r1h,$Dst16RnQI */
11730 M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, "shl16.b-dst-dst16-Rn-direct-QI", "shl.b", 16,
11731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11733 /* shl.b r1h,$Dst16AnQI */
11735 M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, "shl16.b-dst-dst16-An-direct-QI", "shl.b", 16,
11736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11738 /* shl.b r1h,[$Dst16An] */
11740 M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, "shl16.b-dst-dst16-An-indirect-QI", "shl.b", 16,
11741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11743 /* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
11745 M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-8-An-relative-QI", "shl.b", 24,
11746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11748 /* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
11750 M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-16-An-relative-QI", "shl.b", 32,
11751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11753 /* shl.b r1h,${Dsp-16-u8}[sb] */
11755 M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-SB-relative-QI", "shl.b", 24,
11756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11758 /* shl.b r1h,${Dsp-16-u16}[sb] */
11760 M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-16-SB-relative-QI", "shl.b", 32,
11761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11763 /* shl.b r1h,${Dsp-16-s8}[fb] */
11765 M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-FB-relative-QI", "shl.b", 24,
11766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11768 /* shl.b r1h,${Dsp-16-u16} */
11770 M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, "shl16.b-dst-dst16-16-16-absolute-QI", "shl.b", 32,
11771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11773 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
11775 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
11776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11778 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
11780 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
11781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11783 /* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11785 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
11786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11788 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11790 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
11791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11793 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11795 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
11796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11798 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11800 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
11801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11803 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11805 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
11806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11808 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11810 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
11811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11813 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11815 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
11816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11818 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11820 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
11821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11823 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11825 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
11826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11828 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11830 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
11831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11833 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
11835 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
11836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11838 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
11840 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
11841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11843 /* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11845 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
11846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11848 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11850 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
11851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11853 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11855 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
11856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11858 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11860 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
11861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11863 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11865 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
11866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11868 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11870 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
11871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11873 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11875 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
11876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11878 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11880 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
11881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11883 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11885 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
11886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11888 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11890 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
11891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11893 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
11895 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-Rn-direct-HI", "shl.w", 16,
11896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11898 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
11900 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-direct-HI", "shl.w", 16,
11901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11903 /* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
11905 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-indirect-HI", "shl.w", 16,
11906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11908 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11910 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "shl.w", 24,
11911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11913 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11915 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "shl.w", 32,
11916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11918 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11920 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "shl.w", 24,
11921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11923 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11925 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "shl.w", 32,
11926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11928 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11930 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "shl.w", 24,
11931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11933 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11935 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "shl16.w-imm4-Q-16-dst16-16-16-absolute-HI", "shl.w", 32,
11936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11938 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
11940 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-Rn-direct-QI", "shl.b", 16,
11941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11943 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
11945 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-direct-QI", "shl.b", 16,
11946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11948 /* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
11950 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-indirect-QI", "shl.b", 16,
11951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11953 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11955 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "shl.b", 24,
11956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11958 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11960 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "shl.b", 32,
11961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11963 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11965 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "shl.b", 24,
11966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11968 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11970 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "shl.b", 32,
11971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11973 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11975 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "shl.b", 24,
11976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11978 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11980 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "shl16.b-imm4-Q-16-dst16-16-16-absolute-QI", "shl.b", 32,
11981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
11983 /* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11985 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shanc.l", 24,
11986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11988 /* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11990 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shanc.l", 24,
11991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11993 /* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11995 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shanc.l", 24,
11996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
11998 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12000 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shanc.l", 32,
12001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12003 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12005 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shanc.l", 32,
12006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12008 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12010 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shanc.l", 32,
12011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12013 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12015 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shanc.l", 40,
12016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12018 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12020 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shanc.l", 40,
12021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12023 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12025 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shanc.l", 40,
12026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12028 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12030 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shanc.l", 40,
12031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12033 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12035 M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shanc.l", 48,
12036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12038 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12040 M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shanc.l", 48,
12041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12043 /* sha.l r1h,$Dst32RnUnprefixedSI */
12045 M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-Rn-direct-Unprefixed-SI", "sha.l", 16,
12046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12048 /* sha.l r1h,$Dst32AnUnprefixedSI */
12050 M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-direct-Unprefixed-SI", "sha.l", 16,
12051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12053 /* sha.l r1h,[$Dst32AnUnprefixed] */
12055 M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-indirect-Unprefixed-SI", "sha.l", 16,
12056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12058 /* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12060 M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 24,
12061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12063 /* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12065 M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 32,
12066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12068 /* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12070 M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 40,
12071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12073 /* sha.l r1h,${Dsp-16-u8}[sb] */
12075 M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 24,
12076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12078 /* sha.l r1h,${Dsp-16-u16}[sb] */
12080 M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 32,
12081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12083 /* sha.l r1h,${Dsp-16-s8}[fb] */
12085 M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 24,
12086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12088 /* sha.l r1h,${Dsp-16-s16}[fb] */
12090 M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 32,
12091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12093 /* sha.l r1h,${Dsp-16-u16} */
12095 M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 32,
12096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12098 /* sha.l r1h,${Dsp-16-u24} */
12100 M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 40,
12101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12103 /* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
12105 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sha.l", 24,
12106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12108 /* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
12110 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sha.l", 24,
12111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12113 /* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12115 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sha.l", 24,
12116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12118 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12120 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 32,
12121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12123 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12125 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 32,
12126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12128 /* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12130 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 32,
12131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12133 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12135 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 40,
12136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12138 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12140 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 40,
12141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12143 /* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12145 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 40,
12146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12148 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12150 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 40,
12151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12153 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12155 M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 48,
12156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12158 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12160 M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 48,
12161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12163 /* sha.w r1h,$Dst32RnUnprefixedHI */
12165 M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
12166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12168 /* sha.w r1h,$Dst32AnUnprefixedHI */
12170 M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
12171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12173 /* sha.w r1h,[$Dst32AnUnprefixed] */
12175 M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
12176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12178 /* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12180 M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
12181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12183 /* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12185 M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
12186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12188 /* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12190 M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
12191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12193 /* sha.w r1h,${Dsp-16-u8}[sb] */
12195 M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
12196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12198 /* sha.w r1h,${Dsp-16-u16}[sb] */
12200 M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
12201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12203 /* sha.w r1h,${Dsp-16-s8}[fb] */
12205 M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
12206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12208 /* sha.w r1h,${Dsp-16-s16}[fb] */
12210 M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
12211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12213 /* sha.w r1h,${Dsp-16-u16} */
12215 M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
12216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12218 /* sha.w r1h,${Dsp-16-u24} */
12220 M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
12221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12223 /* sha.b r1h,$Dst32RnUnprefixedQI */
12225 M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
12226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12228 /* sha.b r1h,$Dst32AnUnprefixedQI */
12230 M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
12231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12233 /* sha.b r1h,[$Dst32AnUnprefixed] */
12235 M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
12236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12238 /* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12240 M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
12241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12243 /* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12245 M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
12246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12248 /* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12250 M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
12251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12253 /* sha.b r1h,${Dsp-16-u8}[sb] */
12255 M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
12256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12258 /* sha.b r1h,${Dsp-16-u16}[sb] */
12260 M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
12261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12263 /* sha.b r1h,${Dsp-16-s8}[fb] */
12265 M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
12266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12268 /* sha.b r1h,${Dsp-16-s16}[fb] */
12270 M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
12271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12273 /* sha.b r1h,${Dsp-16-u16} */
12275 M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
12276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12278 /* sha.b r1h,${Dsp-16-u24} */
12280 M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
12281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12283 /* sha.w r1h,$Dst16RnHI */
12285 M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI, "sha16.w-dst-dst16-Rn-direct-HI", "sha.w", 16,
12286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12288 /* sha.w r1h,$Dst16AnHI */
12290 M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, "sha16.w-dst-dst16-An-direct-HI", "sha.w", 16,
12291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12293 /* sha.w r1h,[$Dst16An] */
12295 M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, "sha16.w-dst-dst16-An-indirect-HI", "sha.w", 16,
12296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12298 /* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
12300 M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-8-An-relative-HI", "sha.w", 24,
12301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12303 /* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
12305 M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-16-An-relative-HI", "sha.w", 32,
12306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12308 /* sha.w r1h,${Dsp-16-u8}[sb] */
12310 M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-SB-relative-HI", "sha.w", 24,
12311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12313 /* sha.w r1h,${Dsp-16-u16}[sb] */
12315 M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-16-SB-relative-HI", "sha.w", 32,
12316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12318 /* sha.w r1h,${Dsp-16-s8}[fb] */
12320 M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-FB-relative-HI", "sha.w", 24,
12321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12323 /* sha.w r1h,${Dsp-16-u16} */
12325 M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI, "sha16.w-dst-dst16-16-16-absolute-HI", "sha.w", 32,
12326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12328 /* sha.b r1h,$Dst16RnQI */
12330 M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, "sha16.b-dst-dst16-Rn-direct-QI", "sha.b", 16,
12331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12333 /* sha.b r1h,$Dst16AnQI */
12335 M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, "sha16.b-dst-dst16-An-direct-QI", "sha.b", 16,
12336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12338 /* sha.b r1h,[$Dst16An] */
12340 M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, "sha16.b-dst-dst16-An-indirect-QI", "sha.b", 16,
12341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12343 /* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
12345 M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-8-An-relative-QI", "sha.b", 24,
12346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12348 /* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
12350 M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-16-An-relative-QI", "sha.b", 32,
12351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12353 /* sha.b r1h,${Dsp-16-u8}[sb] */
12355 M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-SB-relative-QI", "sha.b", 24,
12356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12358 /* sha.b r1h,${Dsp-16-u16}[sb] */
12360 M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-16-SB-relative-QI", "sha.b", 32,
12361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12363 /* sha.b r1h,${Dsp-16-s8}[fb] */
12365 M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-FB-relative-QI", "sha.b", 24,
12366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12368 /* sha.b r1h,${Dsp-16-u16} */
12370 M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, "sha16.b-dst-dst16-16-16-absolute-QI", "sha.b", 32,
12371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12373 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
12375 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
12376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12378 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
12380 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
12381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12383 /* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12385 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
12386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12388 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12390 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
12391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12393 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12395 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
12396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12398 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12400 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
12401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12403 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12405 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
12406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12408 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12410 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
12411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12413 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12415 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
12416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12418 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12420 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
12421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12423 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12425 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
12426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12428 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12430 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
12431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12433 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
12435 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
12436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12438 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
12440 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
12441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12443 /* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12445 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
12446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12448 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12450 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
12451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12453 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12455 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
12456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12458 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12460 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
12461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12463 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12465 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
12466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12468 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12470 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
12471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12473 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12475 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
12476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12478 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12480 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
12481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12483 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12485 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
12486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12488 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12490 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
12491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12493 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
12495 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-Rn-direct-HI", "sha.w", 16,
12496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12498 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
12500 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-direct-HI", "sha.w", 16,
12501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12503 /* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
12505 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-indirect-HI", "sha.w", 16,
12506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12508 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12510 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "sha.w", 24,
12511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12513 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12515 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "sha.w", 32,
12516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12518 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12520 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "sha.w", 24,
12521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12523 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12525 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "sha.w", 32,
12526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12528 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12530 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "sha.w", 24,
12531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12533 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12535 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "sha16.w-imm4-Q-16-dst16-16-16-absolute-HI", "sha.w", 32,
12536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12538 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
12540 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-Rn-direct-QI", "sha.b", 16,
12541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12543 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
12545 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-direct-QI", "sha.b", 16,
12546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12548 /* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
12550 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-indirect-QI", "sha.b", 16,
12551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12553 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12555 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "sha.b", 24,
12556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12558 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12560 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "sha.b", 32,
12561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12563 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12565 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "sha.b", 24,
12566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12568 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12570 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "sha.b", 32,
12571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12573 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12575 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "sha.b", 24,
12576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12578 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12580 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "sha16.b-imm4-Q-16-dst16-16-16-absolute-QI", "sha.b", 32,
12581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12583 /* sc${sccond32} $Dst32RnUnprefixedHI */
12585 M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-Rn-direct-Unprefixed-HI", "sc", 16,
12586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12588 /* sc${sccond32} $Dst32AnUnprefixedHI */
12590 M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-An-direct-Unprefixed-HI", "sc", 16,
12591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12593 /* sc${sccond32} [$Dst32AnUnprefixed] */
12595 M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, "sccnd-dst32-An-indirect-Unprefixed-HI", "sc", 16,
12596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12598 /* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
12600 M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-An-relative-Unprefixed-HI", "sc", 24,
12601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12603 /* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
12605 M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-An-relative-Unprefixed-HI", "sc", 32,
12606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12608 /* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
12610 M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-24-An-relative-Unprefixed-HI", "sc", 40,
12611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12613 /* sc${sccond32} ${Dsp-16-u8}[sb] */
12615 M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-SB-relative-Unprefixed-HI", "sc", 24,
12616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12618 /* sc${sccond32} ${Dsp-16-u16}[sb] */
12620 M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-SB-relative-Unprefixed-HI", "sc", 32,
12621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12623 /* sc${sccond32} ${Dsp-16-s8}[fb] */
12625 M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-FB-relative-Unprefixed-HI", "sc", 24,
12626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12628 /* sc${sccond32} ${Dsp-16-s16}[fb] */
12630 M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-FB-relative-Unprefixed-HI", "sc", 32,
12631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12633 /* sc${sccond32} ${Dsp-16-u16} */
12635 M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-16-absolute-Unprefixed-HI", "sc", 32,
12636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12638 /* sc${sccond32} ${Dsp-16-u24} */
12640 M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40,
12641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12643 /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
12645 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32,
12646 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12648 /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
12650 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32,
12651 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12653 /* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
12655 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32,
12656 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12658 /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
12660 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40,
12661 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12663 /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
12665 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40,
12666 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12668 /* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
12670 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40,
12671 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12673 /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
12675 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40,
12676 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12678 /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
12680 M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48,
12681 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12683 /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
12685 M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48,
12686 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12688 /* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */
12690 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24,
12691 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12693 /* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */
12695 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24,
12696 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12698 /* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
12700 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24,
12701 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12703 /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
12705 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32,
12706 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12708 /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
12710 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32,
12711 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12713 /* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
12715 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32,
12716 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12718 /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
12720 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40,
12721 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12723 /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
12725 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40,
12726 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12728 /* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
12730 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40,
12731 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12733 /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
12735 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40,
12736 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12738 /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
12740 M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48,
12741 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12743 /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
12745 M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48,
12746 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12748 /* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */
12750 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24,
12751 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12753 /* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */
12755 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24,
12756 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12758 /* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
12760 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24,
12761 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12763 /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
12765 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32,
12766 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12768 /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
12770 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32,
12771 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12773 /* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
12775 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32,
12776 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12778 /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
12780 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40,
12781 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12783 /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
12785 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40,
12786 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12788 /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
12790 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40,
12791 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12793 /* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */
12795 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24,
12796 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12798 /* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */
12800 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24,
12801 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12803 /* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
12805 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24,
12806 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12808 /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
12810 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32,
12811 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12813 /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
12815 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32,
12816 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12818 /* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
12820 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32,
12821 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12823 /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
12825 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40,
12826 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12828 /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
12830 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40,
12831 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12833 /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
12835 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40,
12836 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12838 /* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */
12840 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24,
12841 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12843 /* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */
12845 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24,
12846 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12848 /* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
12850 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24,
12851 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
12853 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
12855 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12858 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
12860 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12863 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
12865 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12868 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
12870 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12873 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
12875 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12878 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
12880 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12883 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
12885 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12888 /* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
12890 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12893 /* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
12895 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12898 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
12900 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12903 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12905 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12908 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12910 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12913 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
12915 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12918 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12920 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12923 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12925 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12928 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
12930 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12933 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12935 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12938 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12940 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12943 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
12945 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12948 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
12950 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12953 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
12955 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12958 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
12960 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12963 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
12965 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12968 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
12970 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12973 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
12975 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12978 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
12980 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12983 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
12985 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12988 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
12990 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
12991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12993 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
12995 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
12996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
12998 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
13000 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
13001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13003 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
13005 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
13006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13008 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
13010 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
13011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13013 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
13015 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
13016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13018 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
13020 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13023 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13025 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13028 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13030 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13033 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13035 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13038 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
13040 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13043 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
13045 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13048 /* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
13050 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13053 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13055 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13058 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
13060 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13063 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
13065 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13068 /* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
13070 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13073 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13075 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13078 /* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13080 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13083 /* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13085 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13088 /* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13090 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13093 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13095 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13098 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13100 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13103 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13105 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13108 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13110 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13113 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13115 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13118 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13120 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13123 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13125 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13128 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13130 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13133 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13135 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13138 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13140 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13143 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13145 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13148 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13150 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13153 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13155 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13158 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13160 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13163 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13165 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13168 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13170 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13173 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13175 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13178 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13180 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13183 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13185 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13188 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13190 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13193 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13195 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13198 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13200 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13203 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13205 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13208 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13210 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13213 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13215 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13218 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13220 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13223 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13225 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13228 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13230 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13233 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13235 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13238 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13240 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13243 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13245 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13248 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
13250 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13253 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13255 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13258 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13260 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13263 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13265 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13268 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
13270 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13273 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13275 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
13276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13278 /* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
13280 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
13281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13283 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13285 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
13286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13288 /* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
13290 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
13291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13293 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13295 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
13296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13298 /* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
13300 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
13301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13303 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
13305 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
13306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13308 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
13310 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
13311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13313 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
13315 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
13316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13318 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
13320 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
13321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13323 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
13325 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
13326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13328 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
13330 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
13331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13333 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
13335 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
13336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13338 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
13340 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
13341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13343 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
13345 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
13346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13348 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
13350 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
13351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13353 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
13355 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
13356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13358 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
13360 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
13361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13363 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
13365 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
13366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13368 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
13370 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
13371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13373 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
13375 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
13376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13378 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
13380 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
13381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13383 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
13385 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
13386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13388 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
13390 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
13391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13393 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
13395 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13398 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
13400 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13403 /* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
13405 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13408 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
13410 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13413 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
13415 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13418 /* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
13420 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13423 /* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
13425 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13428 /* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
13430 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13433 /* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
13435 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13438 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13440 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13443 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13445 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13448 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
13450 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13453 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13455 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13458 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13460 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13463 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
13465 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13468 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13470 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13473 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13475 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13478 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
13480 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13483 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
13485 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13488 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
13490 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13493 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
13495 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13498 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
13500 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13503 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
13505 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13508 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
13510 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13513 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
13515 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13518 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
13520 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13523 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
13525 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13528 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
13530 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13533 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
13535 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13538 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
13540 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13543 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
13545 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13548 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
13550 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13553 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
13555 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13558 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
13560 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13563 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
13565 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13568 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
13570 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13573 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13575 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13578 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
13580 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13583 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
13585 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13588 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13590 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13593 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
13595 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13598 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
13600 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13603 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13605 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13608 /* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
13610 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13613 /* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
13615 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13618 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
13620 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13623 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13625 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13628 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13630 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13633 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
13635 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13638 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13640 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13643 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13645 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13648 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
13650 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13653 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13655 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13658 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13660 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13663 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
13665 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13668 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
13670 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13673 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
13675 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13678 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
13680 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13683 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
13685 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13688 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
13690 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13693 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
13695 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13698 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
13700 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13703 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
13705 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13708 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
13710 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13713 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
13715 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13718 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
13720 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13723 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
13725 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13728 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
13730 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13733 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
13735 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13738 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
13740 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13743 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13745 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13748 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13750 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13753 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13755 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13758 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
13760 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13763 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
13765 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13768 /* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
13770 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13773 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13775 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13778 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
13780 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13783 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
13785 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13788 /* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
13790 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13793 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13795 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13798 /* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13800 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13803 /* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13805 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13808 /* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13810 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13813 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13815 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13818 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13820 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13823 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13825 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13828 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13830 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13833 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13835 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13838 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13840 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13843 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13845 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13848 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13850 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13853 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13855 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13858 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13860 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13863 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13865 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13868 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13870 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13873 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13875 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13878 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13880 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13883 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13885 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13888 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13890 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13893 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13895 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13898 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13900 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13903 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13905 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13908 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13910 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13913 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13915 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13918 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13920 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13923 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13925 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13928 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13930 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13933 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13935 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13938 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13940 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13943 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13945 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13948 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13950 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13953 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13955 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13958 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13960 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13963 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13965 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13968 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
13970 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13973 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13975 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13978 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13980 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13983 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13985 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13988 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
13990 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13993 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13995 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
13996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
13998 /* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
14000 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
14001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14003 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
14005 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
14006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14008 /* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
14010 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
14011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14013 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
14015 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
14016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14018 /* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
14020 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
14021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14023 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
14025 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
14026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14028 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
14030 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
14031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14033 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
14035 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
14036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14038 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
14040 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
14041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14043 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
14045 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
14046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14048 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
14050 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
14051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14053 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
14055 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
14056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14058 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
14060 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
14061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14063 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
14065 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
14066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14068 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
14070 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
14071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14073 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
14075 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
14076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14078 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
14080 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
14081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14083 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
14085 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
14086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14088 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
14090 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
14091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14093 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
14095 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
14096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14098 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
14100 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
14101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14103 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
14105 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
14106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14108 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
14110 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
14111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14113 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
14115 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14118 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
14120 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14123 /* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
14125 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14128 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
14130 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14133 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
14135 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14138 /* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
14140 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14143 /* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
14145 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14148 /* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
14150 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14153 /* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
14155 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14158 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14160 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14163 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14165 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14168 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
14170 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14173 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14175 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14178 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14180 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14183 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
14185 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14188 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14190 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14193 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14195 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14198 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
14200 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14203 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
14205 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14208 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
14210 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14213 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
14215 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14218 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
14220 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14223 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
14225 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14228 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
14230 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14233 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
14235 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14238 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
14240 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14243 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
14245 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14248 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
14250 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14253 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
14255 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14258 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
14260 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14263 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
14265 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14268 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
14270 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14273 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
14275 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14278 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
14280 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14283 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
14285 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14288 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
14290 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
14293 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
14295 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14298 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
14300 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14303 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
14305 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14308 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
14310 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14313 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
14315 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14318 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
14320 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14323 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14325 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14328 /* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14330 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14333 /* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14335 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14338 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14340 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14343 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14345 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14348 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14350 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14353 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14355 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14358 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14360 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14363 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14365 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14368 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14370 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14373 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14375 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14378 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14380 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14383 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14385 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14388 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14390 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14393 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14395 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14398 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14400 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14403 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14405 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14408 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14410 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14413 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14415 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14418 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14420 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14423 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14425 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14428 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
14430 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14433 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
14435 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14438 /* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
14440 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14443 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
14445 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
14446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14448 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
14450 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
14451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14453 /* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
14455 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sbb.w", 32,
14456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14458 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14460 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
14461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14463 /* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14465 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
14466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14468 /* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
14470 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sbb.w", 32,
14471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14473 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14475 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14478 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14480 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14483 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14485 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14488 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14490 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14493 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14495 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14498 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14500 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14503 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14505 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14508 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14510 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14513 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14515 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14518 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14520 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14523 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14525 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14528 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14530 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14533 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14535 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14538 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14540 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14543 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14545 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14548 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14550 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14553 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14555 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14558 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
14560 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14563 /* sbb.w${X} $Src16RnHI,$Dst16RnHI */
14565 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14568 /* sbb.w${X} $Src16AnHI,$Dst16RnHI */
14570 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14573 /* sbb.w${X} [$Src16An],$Dst16RnHI */
14575 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14578 /* sbb.w${X} $Src16RnHI,$Dst16AnHI */
14580 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
14581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14583 /* sbb.w${X} $Src16AnHI,$Dst16AnHI */
14585 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
14586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14588 /* sbb.w${X} [$Src16An],$Dst16AnHI */
14590 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sbb.w", 16,
14591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14593 /* sbb.w${X} $Src16RnHI,[$Dst16An] */
14595 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
14596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14598 /* sbb.w${X} $Src16AnHI,[$Dst16An] */
14600 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
14601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14603 /* sbb.w${X} [$Src16An],[$Dst16An] */
14605 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sbb.w", 16,
14606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14608 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
14610 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14613 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
14615 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14618 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
14620 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14623 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
14625 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14628 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
14630 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14633 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
14635 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14638 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
14640 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14643 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
14645 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14648 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
14650 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14653 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
14655 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14658 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
14660 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14663 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
14665 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14668 /* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
14670 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14673 /* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
14675 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14678 /* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
14680 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14683 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
14685 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14688 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
14690 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14693 /* sbb.w${X} [$Src16An],${Dsp-16-u16} */
14695 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14698 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
14700 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14703 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
14705 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14708 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
14710 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14713 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
14715 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14718 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
14720 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14723 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
14725 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14728 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14730 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14733 /* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14735 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14738 /* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14740 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14743 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14745 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14748 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14750 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14753 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14755 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14758 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14760 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14763 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14765 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14768 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14770 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14773 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14775 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14778 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14780 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14783 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14785 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14788 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14790 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14793 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14795 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14798 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14800 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14803 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14805 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14808 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14810 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14813 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14815 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14818 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14820 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14823 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14825 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14828 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14830 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14833 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
14835 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14838 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
14840 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14843 /* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
14845 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14848 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
14850 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
14851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14853 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
14855 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
14856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14858 /* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
14860 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sbb.b", 32,
14861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14863 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14865 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
14866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14868 /* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14870 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
14871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14873 /* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
14875 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sbb.b", 32,
14876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14878 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14880 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14883 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14885 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14888 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14890 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14893 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14895 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14898 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14900 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14903 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14905 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14908 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14910 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14913 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14915 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14918 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14920 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14923 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14925 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14928 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14930 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14933 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14935 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14938 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14940 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14943 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14945 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14948 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14950 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14953 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14955 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14958 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14960 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14963 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
14965 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14968 /* sbb.b${X} $Src16RnQI,$Dst16RnQI */
14970 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14973 /* sbb.b${X} $Src16AnQI,$Dst16RnQI */
14975 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14978 /* sbb.b${X} [$Src16An],$Dst16RnQI */
14980 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14983 /* sbb.b${X} $Src16RnQI,$Dst16AnQI */
14985 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
14986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14988 /* sbb.b${X} $Src16AnQI,$Dst16AnQI */
14990 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
14991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14993 /* sbb.b${X} [$Src16An],$Dst16AnQI */
14995 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sbb.b", 16,
14996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
14998 /* sbb.b${X} $Src16RnQI,[$Dst16An] */
15000 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
15001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15003 /* sbb.b${X} $Src16AnQI,[$Dst16An] */
15005 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
15006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15008 /* sbb.b${X} [$Src16An],[$Dst16An] */
15010 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sbb.b", 16,
15011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15013 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
15015 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15018 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
15020 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15023 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
15025 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15028 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
15030 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15033 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
15035 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15038 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
15040 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15043 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
15045 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15048 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
15050 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15053 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
15055 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15058 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
15060 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15063 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
15065 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15068 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
15070 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15073 /* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
15075 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15078 /* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
15080 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15083 /* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
15085 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15088 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
15090 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15093 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
15095 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15098 /* sbb.b${X} [$Src16An],${Dsp-16-u16} */
15100 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15103 /* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
15105 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
15106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15108 /* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
15110 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
15111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15113 /* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
15115 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
15116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15118 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15120 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 48,
15121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15123 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
15125 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 48,
15126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15128 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
15130 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 48,
15131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15133 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15135 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 56,
15136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15138 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
15140 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 56,
15141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15143 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
15145 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 56,
15146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15148 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
15150 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 56,
15151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15153 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15155 M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 64,
15156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15158 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
15160 M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 64,
15161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15163 /* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
15165 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
15166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15168 /* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
15170 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
15171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15173 /* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
15175 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
15176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15178 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15180 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 40,
15181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15183 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
15185 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 40,
15186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15188 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
15190 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 40,
15191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15193 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15195 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 48,
15196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15198 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
15200 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 48,
15201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15203 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
15205 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 48,
15206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15208 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
15210 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 48,
15211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15213 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15215 M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 56,
15216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15218 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
15220 M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 56,
15221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15223 /* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
15225 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-Rn-direct-HI", "sbb.w", 32,
15226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15228 /* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
15230 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-direct-HI", "sbb.w", 32,
15231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15233 /* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
15235 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-indirect-HI", "sbb.w", 32,
15236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15238 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
15240 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sbb.w", 40,
15241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15243 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
15245 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sbb.w", 40,
15246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15248 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
15250 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sbb.w", 40,
15251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15253 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
15255 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sbb.w", 48,
15256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15258 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
15260 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sbb.w", 48,
15261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15263 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
15265 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sbb.w", 48,
15266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15268 /* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
15270 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-Rn-direct-QI", "sbb.b", 24,
15271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15273 /* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
15275 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-direct-QI", "sbb.b", 24,
15276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15278 /* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
15280 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-indirect-QI", "sbb.b", 24,
15281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15283 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
15285 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sbb.b", 32,
15286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15288 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
15290 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sbb.b", 32,
15291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15293 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
15295 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sbb.b", 32,
15296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15298 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
15300 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sbb.b", 40,
15301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15303 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
15305 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sbb.b", 40,
15306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15308 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
15310 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40,
15311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15313 /* rot.w r1h,$Dst32RnUnprefixedHI */
15315 M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
15316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15318 /* rot.w r1h,$Dst32AnUnprefixedHI */
15320 M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
15321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15323 /* rot.w r1h,[$Dst32AnUnprefixed] */
15325 M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
15326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15328 /* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15330 M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
15331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15333 /* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15335 M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
15336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15338 /* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15340 M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
15341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15343 /* rot.w r1h,${Dsp-16-u8}[sb] */
15345 M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
15346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15348 /* rot.w r1h,${Dsp-16-u16}[sb] */
15350 M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
15351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15353 /* rot.w r1h,${Dsp-16-s8}[fb] */
15355 M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
15356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15358 /* rot.w r1h,${Dsp-16-s16}[fb] */
15360 M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
15361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15363 /* rot.w r1h,${Dsp-16-u16} */
15365 M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
15366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15368 /* rot.w r1h,${Dsp-16-u24} */
15370 M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
15371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15373 /* rot.b r1h,$Dst32RnUnprefixedQI */
15375 M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
15376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15378 /* rot.b r1h,$Dst32AnUnprefixedQI */
15380 M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
15381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15383 /* rot.b r1h,[$Dst32AnUnprefixed] */
15385 M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
15386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15388 /* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15390 M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
15391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15393 /* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15395 M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
15396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15398 /* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15400 M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
15401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15403 /* rot.b r1h,${Dsp-16-u8}[sb] */
15405 M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
15406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15408 /* rot.b r1h,${Dsp-16-u16}[sb] */
15410 M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
15411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15413 /* rot.b r1h,${Dsp-16-s8}[fb] */
15415 M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
15416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15418 /* rot.b r1h,${Dsp-16-s16}[fb] */
15420 M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
15421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15423 /* rot.b r1h,${Dsp-16-u16} */
15425 M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
15426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15428 /* rot.b r1h,${Dsp-16-u24} */
15430 M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
15431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15433 /* rot.w r1h,$Dst16RnHI */
15435 M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, "rot16.w-dst-dst16-Rn-direct-HI", "rot.w", 16,
15436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15438 /* rot.w r1h,$Dst16AnHI */
15440 M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, "rot16.w-dst-dst16-An-direct-HI", "rot.w", 16,
15441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15443 /* rot.w r1h,[$Dst16An] */
15445 M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI, "rot16.w-dst-dst16-An-indirect-HI", "rot.w", 16,
15446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15448 /* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
15450 M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-8-An-relative-HI", "rot.w", 24,
15451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15453 /* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
15455 M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-16-An-relative-HI", "rot.w", 32,
15456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15458 /* rot.w r1h,${Dsp-16-u8}[sb] */
15460 M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-SB-relative-HI", "rot.w", 24,
15461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15463 /* rot.w r1h,${Dsp-16-u16}[sb] */
15465 M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-16-SB-relative-HI", "rot.w", 32,
15466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15468 /* rot.w r1h,${Dsp-16-s8}[fb] */
15470 M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-FB-relative-HI", "rot.w", 24,
15471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15473 /* rot.w r1h,${Dsp-16-u16} */
15475 M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32,
15476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15478 /* rot.b r1h,$Dst16RnQI */
15480 M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, "rot16.b-dst-dst16-Rn-direct-QI", "rot.b", 16,
15481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15483 /* rot.b r1h,$Dst16AnQI */
15485 M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI, "rot16.b-dst-dst16-An-direct-QI", "rot.b", 16,
15486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15488 /* rot.b r1h,[$Dst16An] */
15490 M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, "rot16.b-dst-dst16-An-indirect-QI", "rot.b", 16,
15491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15493 /* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
15495 M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-8-An-relative-QI", "rot.b", 24,
15496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15498 /* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
15500 M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-16-An-relative-QI", "rot.b", 32,
15501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15503 /* rot.b r1h,${Dsp-16-u8}[sb] */
15505 M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-SB-relative-QI", "rot.b", 24,
15506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15508 /* rot.b r1h,${Dsp-16-u16}[sb] */
15510 M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-16-SB-relative-QI", "rot.b", 32,
15511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15513 /* rot.b r1h,${Dsp-16-s8}[fb] */
15515 M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-FB-relative-QI", "rot.b", 24,
15516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15518 /* rot.b r1h,${Dsp-16-u16} */
15520 M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, "rot16.b-dst-dst16-16-16-absolute-QI", "rot.b", 32,
15521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15523 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
15525 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
15526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15528 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
15530 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
15531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15533 /* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15535 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
15536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15538 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15540 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
15541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15543 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15545 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
15546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15548 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15550 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
15551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15553 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15555 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
15556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15558 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15560 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
15561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15563 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15565 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
15566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15568 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15570 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
15571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15573 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15575 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
15576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15578 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15580 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
15581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15583 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
15585 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
15586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15588 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
15590 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
15591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15593 /* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15595 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
15596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15598 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15600 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
15601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15603 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15605 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
15606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15608 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15610 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
15611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15613 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15615 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
15616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15618 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15620 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
15621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15623 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15625 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
15626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15628 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15630 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
15631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15633 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15635 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
15636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15638 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15640 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
15641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15643 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
15645 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-Rn-direct-HI", "rot.w", 16,
15646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15648 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
15650 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-direct-HI", "rot.w", 16,
15651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15653 /* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
15655 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-indirect-HI", "rot.w", 16,
15656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15658 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15660 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "rot.w", 24,
15661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15663 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15665 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "rot.w", 32,
15666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15668 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15670 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "rot.w", 24,
15671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15673 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15675 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "rot.w", 32,
15676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15678 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15680 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "rot.w", 24,
15681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15683 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15685 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "rot16.w-imm4-Q-16-dst16-16-16-absolute-HI", "rot.w", 32,
15686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15688 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
15690 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-Rn-direct-QI", "rot.b", 16,
15691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15693 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
15695 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-direct-QI", "rot.b", 16,
15696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15698 /* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
15700 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-indirect-QI", "rot.b", 16,
15701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15703 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15705 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "rot.b", 24,
15706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15708 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15710 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "rot.b", 32,
15711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15713 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15715 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "rot.b", 24,
15716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15718 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15720 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "rot.b", 32,
15721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15723 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15725 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "rot.b", 24,
15726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15728 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15730 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "rot16.b-imm4-Q-16-dst16-16-16-absolute-QI", "rot.b", 32,
15731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15733 /* rorc.w $Dst32RnUnprefixedHI */
15735 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rorc.w", 16,
15736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15738 /* rorc.w $Dst32AnUnprefixedHI */
15740 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rorc.w", 16,
15741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15743 /* rorc.w [$Dst32AnUnprefixed] */
15745 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rorc.w", 16,
15746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15748 /* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15750 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rorc.w", 24,
15751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15753 /* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15755 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rorc.w", 32,
15756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15758 /* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15760 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rorc.w", 40,
15761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15763 /* rorc.w ${Dsp-16-u8}[sb] */
15765 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rorc.w", 24,
15766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15768 /* rorc.w ${Dsp-16-u16}[sb] */
15770 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rorc.w", 32,
15771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15773 /* rorc.w ${Dsp-16-s8}[fb] */
15775 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rorc.w", 24,
15776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15778 /* rorc.w ${Dsp-16-s16}[fb] */
15780 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rorc.w", 32,
15781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15783 /* rorc.w ${Dsp-16-u16} */
15785 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rorc.w", 32,
15786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15788 /* rorc.w ${Dsp-16-u24} */
15790 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rorc.w", 40,
15791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15793 /* rorc.b $Dst32RnUnprefixedQI */
15795 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rorc.b", 16,
15796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15798 /* rorc.b $Dst32AnUnprefixedQI */
15800 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rorc.b", 16,
15801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15803 /* rorc.b [$Dst32AnUnprefixed] */
15805 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rorc.b", 16,
15806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15808 /* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15810 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rorc.b", 24,
15811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15813 /* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15815 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rorc.b", 32,
15816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15818 /* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15820 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rorc.b", 40,
15821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15823 /* rorc.b ${Dsp-16-u8}[sb] */
15825 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rorc.b", 24,
15826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15828 /* rorc.b ${Dsp-16-u16}[sb] */
15830 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rorc.b", 32,
15831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15833 /* rorc.b ${Dsp-16-s8}[fb] */
15835 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rorc.b", 24,
15836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15838 /* rorc.b ${Dsp-16-s16}[fb] */
15840 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rorc.b", 32,
15841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15843 /* rorc.b ${Dsp-16-u16} */
15845 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rorc.b", 32,
15846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15848 /* rorc.b ${Dsp-16-u24} */
15850 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rorc.b", 40,
15851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15853 /* rorc.w $Dst16RnHI */
15855 M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, "rorc16.w-16-dst16-Rn-direct-HI", "rorc.w", 16,
15856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15858 /* rorc.w $Dst16AnHI */
15860 M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, "rorc16.w-16-dst16-An-direct-HI", "rorc.w", 16,
15861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15863 /* rorc.w [$Dst16An] */
15865 M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI, "rorc16.w-16-dst16-An-indirect-HI", "rorc.w", 16,
15866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15868 /* rorc.w ${Dsp-16-u8}[$Dst16An] */
15870 M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-8-An-relative-HI", "rorc.w", 24,
15871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15873 /* rorc.w ${Dsp-16-u16}[$Dst16An] */
15875 M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-16-An-relative-HI", "rorc.w", 32,
15876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15878 /* rorc.w ${Dsp-16-u8}[sb] */
15880 M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-SB-relative-HI", "rorc.w", 24,
15881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15883 /* rorc.w ${Dsp-16-u16}[sb] */
15885 M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-16-SB-relative-HI", "rorc.w", 32,
15886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15888 /* rorc.w ${Dsp-16-s8}[fb] */
15890 M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-FB-relative-HI", "rorc.w", 24,
15891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15893 /* rorc.w ${Dsp-16-u16} */
15895 M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, "rorc16.w-16-dst16-16-16-absolute-HI", "rorc.w", 32,
15896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15898 /* rorc.b $Dst16RnQI */
15900 M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, "rorc16.b-16-dst16-Rn-direct-QI", "rorc.b", 16,
15901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15903 /* rorc.b $Dst16AnQI */
15905 M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI, "rorc16.b-16-dst16-An-direct-QI", "rorc.b", 16,
15906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15908 /* rorc.b [$Dst16An] */
15910 M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, "rorc16.b-16-dst16-An-indirect-QI", "rorc.b", 16,
15911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15913 /* rorc.b ${Dsp-16-u8}[$Dst16An] */
15915 M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-8-An-relative-QI", "rorc.b", 24,
15916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15918 /* rorc.b ${Dsp-16-u16}[$Dst16An] */
15920 M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-16-An-relative-QI", "rorc.b", 32,
15921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15923 /* rorc.b ${Dsp-16-u8}[sb] */
15925 M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-SB-relative-QI", "rorc.b", 24,
15926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15928 /* rorc.b ${Dsp-16-u16}[sb] */
15930 M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-16-SB-relative-QI", "rorc.b", 32,
15931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15933 /* rorc.b ${Dsp-16-s8}[fb] */
15935 M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-FB-relative-QI", "rorc.b", 24,
15936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15938 /* rorc.b ${Dsp-16-u16} */
15940 M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, "rorc16.b-16-dst16-16-16-absolute-QI", "rorc.b", 32,
15941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
15943 /* rolc.w $Dst32RnUnprefixedHI */
15945 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rolc.w", 16,
15946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15948 /* rolc.w $Dst32AnUnprefixedHI */
15950 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rolc.w", 16,
15951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15953 /* rolc.w [$Dst32AnUnprefixed] */
15955 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rolc.w", 16,
15956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15958 /* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15960 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rolc.w", 24,
15961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15963 /* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15965 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rolc.w", 32,
15966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15968 /* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15970 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rolc.w", 40,
15971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15973 /* rolc.w ${Dsp-16-u8}[sb] */
15975 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rolc.w", 24,
15976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15978 /* rolc.w ${Dsp-16-u16}[sb] */
15980 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rolc.w", 32,
15981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15983 /* rolc.w ${Dsp-16-s8}[fb] */
15985 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rolc.w", 24,
15986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15988 /* rolc.w ${Dsp-16-s16}[fb] */
15990 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rolc.w", 32,
15991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15993 /* rolc.w ${Dsp-16-u16} */
15995 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rolc.w", 32,
15996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
15998 /* rolc.w ${Dsp-16-u24} */
16000 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rolc.w", 40,
16001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16003 /* rolc.b $Dst32RnUnprefixedQI */
16005 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rolc.b", 16,
16006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16008 /* rolc.b $Dst32AnUnprefixedQI */
16010 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rolc.b", 16,
16011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16013 /* rolc.b [$Dst32AnUnprefixed] */
16015 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rolc.b", 16,
16016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16018 /* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16020 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rolc.b", 24,
16021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16023 /* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16025 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rolc.b", 32,
16026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16028 /* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16030 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rolc.b", 40,
16031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16033 /* rolc.b ${Dsp-16-u8}[sb] */
16035 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rolc.b", 24,
16036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16038 /* rolc.b ${Dsp-16-u16}[sb] */
16040 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rolc.b", 32,
16041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16043 /* rolc.b ${Dsp-16-s8}[fb] */
16045 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rolc.b", 24,
16046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16048 /* rolc.b ${Dsp-16-s16}[fb] */
16050 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rolc.b", 32,
16051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16053 /* rolc.b ${Dsp-16-u16} */
16055 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rolc.b", 32,
16056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16058 /* rolc.b ${Dsp-16-u24} */
16060 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rolc.b", 40,
16061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16063 /* rolc.w $Dst16RnHI */
16065 M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI, "rolc16.w-16-dst16-Rn-direct-HI", "rolc.w", 16,
16066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16068 /* rolc.w $Dst16AnHI */
16070 M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, "rolc16.w-16-dst16-An-direct-HI", "rolc.w", 16,
16071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16073 /* rolc.w [$Dst16An] */
16075 M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, "rolc16.w-16-dst16-An-indirect-HI", "rolc.w", 16,
16076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16078 /* rolc.w ${Dsp-16-u8}[$Dst16An] */
16080 M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-8-An-relative-HI", "rolc.w", 24,
16081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16083 /* rolc.w ${Dsp-16-u16}[$Dst16An] */
16085 M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-16-An-relative-HI", "rolc.w", 32,
16086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16088 /* rolc.w ${Dsp-16-u8}[sb] */
16090 M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-SB-relative-HI", "rolc.w", 24,
16091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16093 /* rolc.w ${Dsp-16-u16}[sb] */
16095 M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-16-SB-relative-HI", "rolc.w", 32,
16096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16098 /* rolc.w ${Dsp-16-s8}[fb] */
16100 M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-FB-relative-HI", "rolc.w", 24,
16101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16103 /* rolc.w ${Dsp-16-u16} */
16105 M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI, "rolc16.w-16-dst16-16-16-absolute-HI", "rolc.w", 32,
16106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16108 /* rolc.b $Dst16RnQI */
16110 M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, "rolc16.b-16-dst16-Rn-direct-QI", "rolc.b", 16,
16111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16113 /* rolc.b $Dst16AnQI */
16115 M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, "rolc16.b-16-dst16-An-direct-QI", "rolc.b", 16,
16116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16118 /* rolc.b [$Dst16An] */
16120 M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, "rolc16.b-16-dst16-An-indirect-QI", "rolc.b", 16,
16121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16123 /* rolc.b ${Dsp-16-u8}[$Dst16An] */
16125 M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-8-An-relative-QI", "rolc.b", 24,
16126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16128 /* rolc.b ${Dsp-16-u16}[$Dst16An] */
16130 M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-16-An-relative-QI", "rolc.b", 32,
16131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16133 /* rolc.b ${Dsp-16-u8}[sb] */
16135 M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-SB-relative-QI", "rolc.b", 24,
16136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16138 /* rolc.b ${Dsp-16-u16}[sb] */
16140 M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-16-SB-relative-QI", "rolc.b", 32,
16141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16143 /* rolc.b ${Dsp-16-s8}[fb] */
16145 M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-FB-relative-QI", "rolc.b", 24,
16146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16148 /* rolc.b ${Dsp-16-u16} */
16150 M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, "rolc16.b-16-dst16-16-16-absolute-QI", "rolc.b", 32,
16151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16153 /* pusha [$Dst32AnUnprefixed] */
16155 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-An-indirect-Unprefixed-Mova-SI", "pusha", 16,
16156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16158 /* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16160 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-An-relative-Unprefixed-Mova-SI", "pusha", 24,
16161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16163 /* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16165 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-An-relative-Unprefixed-Mova-SI", "pusha", 32,
16166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16168 /* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16170 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-An-relative-Unprefixed-Mova-SI", "pusha", 40,
16171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16173 /* pusha ${Dsp-16-u8}[sb] */
16175 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "pusha", 24,
16176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16178 /* pusha ${Dsp-16-u16}[sb] */
16180 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "pusha", 32,
16181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16183 /* pusha ${Dsp-16-s8}[fb] */
16185 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "pusha", 24,
16186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16188 /* pusha ${Dsp-16-s16}[fb] */
16190 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "pusha", 32,
16191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16193 /* pusha ${Dsp-16-u16} */
16195 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-absolute-Unprefixed-Mova-SI", "pusha", 32,
16196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16198 /* pusha ${Dsp-16-u24} */
16200 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-absolute-Unprefixed-Mova-SI", "pusha", 40,
16201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16203 /* pusha [$Dst16An] */
16205 M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI, "pusha16-16-Mova-dst16-An-indirect-Mova-HI", "pusha", 16,
16206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16208 /* pusha ${Dsp-16-u8}[$Dst16An] */
16210 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-An-relative-Mova-HI", "pusha", 24,
16211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16213 /* pusha ${Dsp-16-u16}[$Dst16An] */
16215 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-An-relative-Mova-HI", "pusha", 32,
16216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16218 /* pusha ${Dsp-16-u8}[sb] */
16220 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-SB-relative-Mova-HI", "pusha", 24,
16221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16223 /* pusha ${Dsp-16-u16}[sb] */
16225 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-SB-relative-Mova-HI", "pusha", 32,
16226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16228 /* pusha ${Dsp-16-s8}[fb] */
16230 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-FB-relative-Mova-HI", "pusha", 24,
16231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16233 /* pusha ${Dsp-16-u16} */
16235 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-absolute-Mova-HI", "pusha", 32,
16236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16238 /* push.l $Dst32RnUnprefixedSI */
16240 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "push.l", 16,
16241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16243 /* push.l $Dst32AnUnprefixedSI */
16245 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "push.l", 16,
16246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16248 /* push.l [$Dst32AnUnprefixed] */
16250 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "push.l", 16,
16251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16253 /* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16255 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "push.l", 24,
16256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16258 /* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16260 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "push.l", 32,
16261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16263 /* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16265 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "push.l", 40,
16266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16268 /* push.l ${Dsp-16-u8}[sb] */
16270 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "push.l", 24,
16271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16273 /* push.l ${Dsp-16-u16}[sb] */
16275 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "push.l", 32,
16276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16278 /* push.l ${Dsp-16-s8}[fb] */
16280 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "push.l", 24,
16281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16283 /* push.l ${Dsp-16-s16}[fb] */
16285 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "push.l", 32,
16286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16288 /* push.l ${Dsp-16-u16} */
16290 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "push.l", 32,
16291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16293 /* push.l ${Dsp-16-u24} */
16295 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "push.l", 40,
16296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16298 /* push.w${S} ${An16-push-S} */
16300 M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, "push16.b-s-an-An16-push-S-derived", "push.w", 8,
16301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16303 /* push.b${S} ${Rn16-push-S} */
16305 M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED, "push16.b-s-rn-Rn16-push-S-derived", "push.b", 8,
16306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16308 /* push.w $Dst32RnUnprefixedHI */
16310 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "push.w", 16,
16311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16313 /* push.w $Dst32AnUnprefixedHI */
16315 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "push.w", 16,
16316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16318 /* push.w [$Dst32AnUnprefixed] */
16320 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "push.w", 16,
16321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16323 /* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16325 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "push.w", 24,
16326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16328 /* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16330 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "push.w", 32,
16331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16333 /* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16335 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "push.w", 40,
16336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16338 /* push.w ${Dsp-16-u8}[sb] */
16340 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "push.w", 24,
16341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16343 /* push.w ${Dsp-16-u16}[sb] */
16345 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "push.w", 32,
16346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16348 /* push.w ${Dsp-16-s8}[fb] */
16350 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "push.w", 24,
16351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16353 /* push.w ${Dsp-16-s16}[fb] */
16355 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "push.w", 32,
16356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16358 /* push.w ${Dsp-16-u16} */
16360 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "push.w", 32,
16361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16363 /* push.w ${Dsp-16-u24} */
16365 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "push.w", 40,
16366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16368 /* push.b $Dst32RnUnprefixedQI */
16370 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "push.b", 16,
16371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16373 /* push.b $Dst32AnUnprefixedQI */
16375 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "push.b", 16,
16376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16378 /* push.b [$Dst32AnUnprefixed] */
16380 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "push.b", 16,
16381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16383 /* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16385 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "push.b", 24,
16386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16388 /* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16390 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "push.b", 32,
16391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16393 /* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16395 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "push.b", 40,
16396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16398 /* push.b ${Dsp-16-u8}[sb] */
16400 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "push.b", 24,
16401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16403 /* push.b ${Dsp-16-u16}[sb] */
16405 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "push.b", 32,
16406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16408 /* push.b ${Dsp-16-s8}[fb] */
16410 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "push.b", 24,
16411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16413 /* push.b ${Dsp-16-s16}[fb] */
16415 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "push.b", 32,
16416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16418 /* push.b ${Dsp-16-u16} */
16420 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "push.b", 32,
16421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16423 /* push.b ${Dsp-16-u24} */
16425 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40,
16426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16428 /* push.w${G} $Dst16RnHI */
16430 M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16,
16431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16433 /* push.w${G} $Dst16AnHI */
16435 M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16,
16436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16438 /* push.w${G} [$Dst16An] */
16440 M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16,
16441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16443 /* push.w${G} ${Dsp-16-u8}[$Dst16An] */
16445 M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24,
16446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16448 /* push.w${G} ${Dsp-16-u16}[$Dst16An] */
16450 M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32,
16451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16453 /* push.w${G} ${Dsp-16-u8}[sb] */
16455 M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24,
16456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16458 /* push.w${G} ${Dsp-16-u16}[sb] */
16460 M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32,
16461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16463 /* push.w${G} ${Dsp-16-s8}[fb] */
16465 M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24,
16466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16468 /* push.w${G} ${Dsp-16-u16} */
16470 M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32,
16471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16473 /* push.b${G} $Dst16RnQI */
16475 M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16,
16476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16478 /* push.b${G} $Dst16AnQI */
16480 M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16,
16481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16483 /* push.b${G} [$Dst16An] */
16485 M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16,
16486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16488 /* push.b${G} ${Dsp-16-u8}[$Dst16An] */
16490 M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24,
16491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16493 /* push.b${G} ${Dsp-16-u16}[$Dst16An] */
16495 M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32,
16496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16498 /* push.b${G} ${Dsp-16-u8}[sb] */
16500 M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24,
16501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16503 /* push.b${G} ${Dsp-16-u16}[sb] */
16505 M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32,
16506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16508 /* push.b${G} ${Dsp-16-s8}[fb] */
16510 M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24,
16511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16513 /* push.b${G} ${Dsp-16-u16} */
16515 M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32,
16516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16518 /* pop.w${S} ${An16-push-S} */
16520 M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, "pop16.b-s-an-An16-push-S-derived", "pop.w", 8,
16521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16523 /* pop.b${S} ${Rn16-push-S} */
16525 M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED, "pop16.b-s-rn-Rn16-push-S-derived", "pop.b", 8,
16526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16528 /* pop.w $Dst32RnUnprefixedHI */
16530 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "pop.w", 16,
16531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16533 /* pop.w $Dst32AnUnprefixedHI */
16535 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "pop.w", 16,
16536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16538 /* pop.w [$Dst32AnUnprefixed] */
16540 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "pop.w", 16,
16541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16543 /* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16545 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "pop.w", 24,
16546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16548 /* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16550 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "pop.w", 32,
16551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16553 /* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16555 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "pop.w", 40,
16556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16558 /* pop.w ${Dsp-16-u8}[sb] */
16560 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "pop.w", 24,
16561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16563 /* pop.w ${Dsp-16-u16}[sb] */
16565 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "pop.w", 32,
16566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16568 /* pop.w ${Dsp-16-s8}[fb] */
16570 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "pop.w", 24,
16571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16573 /* pop.w ${Dsp-16-s16}[fb] */
16575 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "pop.w", 32,
16576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16578 /* pop.w ${Dsp-16-u16} */
16580 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "pop.w", 32,
16581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16583 /* pop.w ${Dsp-16-u24} */
16585 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "pop.w", 40,
16586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16588 /* pop.b $Dst32RnUnprefixedQI */
16590 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "pop.b", 16,
16591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16593 /* pop.b $Dst32AnUnprefixedQI */
16595 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "pop.b", 16,
16596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16598 /* pop.b [$Dst32AnUnprefixed] */
16600 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "pop.b", 16,
16601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16603 /* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16605 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "pop.b", 24,
16606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16608 /* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16610 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "pop.b", 32,
16611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16613 /* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16615 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "pop.b", 40,
16616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16618 /* pop.b ${Dsp-16-u8}[sb] */
16620 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "pop.b", 24,
16621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16623 /* pop.b ${Dsp-16-u16}[sb] */
16625 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "pop.b", 32,
16626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16628 /* pop.b ${Dsp-16-s8}[fb] */
16630 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "pop.b", 24,
16631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16633 /* pop.b ${Dsp-16-s16}[fb] */
16635 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "pop.b", 32,
16636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16638 /* pop.b ${Dsp-16-u16} */
16640 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "pop.b", 32,
16641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16643 /* pop.b ${Dsp-16-u24} */
16645 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "pop.b", 40,
16646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16648 /* pop.w $Dst16RnHI */
16650 M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, "pop16.w-16-dst16-Rn-direct-HI", "pop.w", 16,
16651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16653 /* pop.w $Dst16AnHI */
16655 M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, "pop16.w-16-dst16-An-direct-HI", "pop.w", 16,
16656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16658 /* pop.w [$Dst16An] */
16660 M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, "pop16.w-16-dst16-An-indirect-HI", "pop.w", 16,
16661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16663 /* pop.w ${Dsp-16-u8}[$Dst16An] */
16665 M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI, "pop16.w-16-dst16-16-8-An-relative-HI", "pop.w", 24,
16666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16668 /* pop.w ${Dsp-16-u16}[$Dst16An] */
16670 M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, "pop16.w-16-dst16-16-16-An-relative-HI", "pop.w", 32,
16671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16673 /* pop.w ${Dsp-16-u8}[sb] */
16675 M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, "pop16.w-16-dst16-16-8-SB-relative-HI", "pop.w", 24,
16676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16678 /* pop.w ${Dsp-16-u16}[sb] */
16680 M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, "pop16.w-16-dst16-16-16-SB-relative-HI", "pop.w", 32,
16681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16683 /* pop.w ${Dsp-16-s8}[fb] */
16685 M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI, "pop16.w-16-dst16-16-8-FB-relative-HI", "pop.w", 24,
16686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16688 /* pop.w ${Dsp-16-u16} */
16690 M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, "pop16.w-16-dst16-16-16-absolute-HI", "pop.w", 32,
16691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16693 /* pop.b $Dst16RnQI */
16695 M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, "pop16.b-16-dst16-Rn-direct-QI", "pop.b", 16,
16696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16698 /* pop.b $Dst16AnQI */
16700 M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, "pop16.b-16-dst16-An-direct-QI", "pop.b", 16,
16701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16703 /* pop.b [$Dst16An] */
16705 M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI, "pop16.b-16-dst16-An-indirect-QI", "pop.b", 16,
16706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16708 /* pop.b ${Dsp-16-u8}[$Dst16An] */
16710 M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, "pop16.b-16-dst16-16-8-An-relative-QI", "pop.b", 24,
16711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16713 /* pop.b ${Dsp-16-u16}[$Dst16An] */
16715 M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, "pop16.b-16-dst16-16-16-An-relative-QI", "pop.b", 32,
16716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16718 /* pop.b ${Dsp-16-u8}[sb] */
16720 M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, "pop16.b-16-dst16-16-8-SB-relative-QI", "pop.b", 24,
16721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16723 /* pop.b ${Dsp-16-u16}[sb] */
16725 M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI, "pop16.b-16-dst16-16-16-SB-relative-QI", "pop.b", 32,
16726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16728 /* pop.b ${Dsp-16-s8}[fb] */
16730 M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, "pop16.b-16-dst16-16-8-FB-relative-QI", "pop.b", 24,
16731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16733 /* pop.b ${Dsp-16-u16} */
16735 M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, "pop16.b-16-dst16-16-16-absolute-QI", "pop.b", 32,
16736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
16738 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16740 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16743 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
16745 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16748 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
16750 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16753 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16755 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16758 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
16760 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16763 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
16765 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16768 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16770 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16773 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
16775 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16778 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
16780 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16783 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16785 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16788 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16790 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16793 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16795 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16798 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16800 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16803 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16805 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16808 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16810 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16813 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16815 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16818 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16820 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16823 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16825 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16828 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
16830 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16833 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
16835 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16838 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
16840 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16843 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
16845 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16848 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
16850 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16853 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
16855 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16858 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
16860 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16863 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
16865 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16868 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
16870 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16873 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
16875 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16878 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
16880 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16883 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
16885 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16888 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
16890 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16893 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
16895 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16898 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
16900 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16903 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
16905 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16908 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
16910 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16913 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
16915 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16918 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16920 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16923 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
16925 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16928 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
16930 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16933 /* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
16935 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16938 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16940 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16943 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
16945 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16948 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
16950 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16953 /* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
16955 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16958 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16960 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16963 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
16965 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16968 /* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
16970 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16973 /* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
16975 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16978 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16980 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16983 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16985 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16988 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16990 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16993 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
16995 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
16998 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17000 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17003 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17005 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17008 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17010 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17013 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17015 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17018 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17020 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17023 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17025 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17028 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17030 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17033 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17035 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17038 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17040 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17043 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17045 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17048 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17050 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17053 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17055 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17058 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17060 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17063 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17065 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17068 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17070 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17073 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17075 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17078 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17080 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17083 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17085 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17088 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17090 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17093 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17095 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17098 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17100 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17103 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17105 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17108 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17110 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17113 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17115 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17118 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17120 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17123 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17125 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17128 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17130 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17133 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
17135 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17138 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17140 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17143 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17145 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17148 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17150 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17153 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
17155 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17158 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17160 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
17161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17163 /* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
17165 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
17166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17168 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17170 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
17171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17173 /* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
17175 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
17176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17178 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17180 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
17181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17183 /* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17185 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
17186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17188 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17190 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
17191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17193 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17195 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
17196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17198 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17200 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
17201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17203 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17205 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
17206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17208 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17210 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
17211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17213 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17215 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
17216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17218 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17220 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
17221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17223 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17225 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
17226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17228 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17230 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
17231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17233 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17235 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
17236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17238 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17240 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
17241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17243 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17245 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
17246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17248 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17250 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
17251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17253 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17255 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
17256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17258 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17260 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
17261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17263 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
17265 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
17266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17268 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17270 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
17271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17273 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
17275 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
17276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17278 /* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
17280 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17283 /* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
17285 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17288 /* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17290 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17293 /* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
17295 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17298 /* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
17300 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17303 /* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17305 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17308 /* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
17310 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17313 /* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
17315 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17318 /* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17320 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17323 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17325 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17328 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17330 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17333 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
17335 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17338 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17340 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17343 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17345 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17348 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
17350 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17353 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17355 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17358 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17360 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17363 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
17365 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17368 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
17370 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17373 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
17375 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17378 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
17380 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17383 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
17385 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17388 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
17390 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17393 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
17395 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17398 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
17400 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17403 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
17405 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17408 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
17410 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17413 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
17415 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17418 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
17420 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17423 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
17425 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17428 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
17430 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17433 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
17435 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17438 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
17440 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17443 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
17445 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17448 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
17450 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17453 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
17455 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17458 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17460 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17463 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
17465 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17468 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
17470 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17473 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17475 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17478 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
17480 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17483 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
17485 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17488 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17490 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17493 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
17495 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17498 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
17500 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17503 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17505 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17508 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17510 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17513 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17515 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17518 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17520 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17523 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17525 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17528 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17530 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17533 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17535 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17538 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17540 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17543 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17545 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17548 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
17550 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17553 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
17555 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17558 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
17560 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17563 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
17565 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17568 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
17570 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17573 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
17575 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17578 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
17580 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17583 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
17585 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17588 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
17590 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17593 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
17595 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17598 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
17600 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17603 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
17605 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17608 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
17610 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17613 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
17615 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17618 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
17620 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17623 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
17625 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17628 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
17630 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17633 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
17635 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17638 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17640 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17643 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
17645 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17648 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
17650 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17653 /* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
17655 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17658 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17660 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17663 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
17665 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17668 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
17670 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17673 /* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
17675 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17678 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17680 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17683 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
17685 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17688 /* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
17690 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17693 /* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
17695 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17698 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17700 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17703 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17705 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17708 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17710 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17713 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17715 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17718 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17720 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17723 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17725 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17728 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17730 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17733 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17735 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17738 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17740 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17743 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17745 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17748 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17750 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17753 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17755 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17758 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17760 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17763 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17765 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17768 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17770 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17773 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17775 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17778 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17780 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17783 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17785 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17788 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17790 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17793 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17795 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17798 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17800 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17803 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17805 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17808 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17810 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17813 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17815 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17818 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17820 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17823 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17825 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17828 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17830 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17833 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17835 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17838 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17840 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17843 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17845 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17848 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17850 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17853 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
17855 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17858 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17860 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17863 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17865 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17868 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17870 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17873 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
17875 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17878 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17880 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
17881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17883 /* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
17885 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
17886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17888 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17890 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
17891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17893 /* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
17895 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
17896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17898 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17900 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
17901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17903 /* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17905 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
17906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17908 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17910 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
17911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17913 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17915 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
17916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17918 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17920 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
17921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17923 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17925 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
17926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17928 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17930 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
17931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17933 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17935 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
17936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17938 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17940 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
17941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17943 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17945 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
17946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17948 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17950 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
17951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17953 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17955 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
17956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17958 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17960 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
17961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17963 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17965 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
17966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17968 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17970 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
17971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17973 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17975 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
17976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17978 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17980 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
17981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17983 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
17985 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
17986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17988 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17990 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
17991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17993 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
17995 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
17996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
17998 /* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
18000 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
18001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18003 /* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
18005 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
18006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18008 /* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
18010 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
18011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18013 /* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
18015 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18018 /* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
18020 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18023 /* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
18025 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18028 /* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
18030 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18033 /* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
18035 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18038 /* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
18040 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18043 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18045 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18048 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18050 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18053 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
18055 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18058 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18060 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18063 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18065 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18068 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
18070 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18073 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18075 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18078 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18080 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18083 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
18085 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18088 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
18090 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18093 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
18095 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18098 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
18100 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18103 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
18105 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18108 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
18110 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18113 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
18115 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18118 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
18120 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18123 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
18125 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18128 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
18130 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18133 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
18135 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18138 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
18140 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18143 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
18145 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18148 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
18150 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18153 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
18155 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18158 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
18160 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18163 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
18165 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18168 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
18170 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18173 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
18175 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18178 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
18180 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18183 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
18185 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18188 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
18190 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18193 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
18195 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "or.w", 24,
18196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18198 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
18200 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "or.w", 24,
18201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18203 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
18205 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "or.w", 24,
18206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18208 /* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18210 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18213 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18215 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18218 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18220 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18223 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18225 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18228 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18230 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18233 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18235 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18238 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18240 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18243 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18245 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18248 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18250 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18253 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18255 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18258 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18260 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18263 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18265 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18268 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18270 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18273 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18275 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18278 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18280 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18283 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18285 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18288 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18290 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18293 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18295 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18298 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18300 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18303 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18305 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18308 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18310 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18313 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
18315 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
18316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18318 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
18320 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
18321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18323 /* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
18325 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "or.w", 32,
18326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18328 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
18330 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "or.w", 32,
18331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18333 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
18335 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "or.w", 32,
18336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18338 /* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
18340 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "or.w", 32,
18341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18343 /* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18345 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "or.w", 32,
18346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18348 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18350 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "or.w", 32,
18351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18353 /* or.w${G} ${Dsp-16-u16},[$Dst16An] */
18355 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "or.w", 32,
18356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18358 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18360 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18363 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18365 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18368 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18370 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18373 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18375 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18378 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18380 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18383 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18385 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18388 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18390 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18393 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18395 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18398 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18400 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18403 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18405 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18408 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18410 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18413 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18415 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18418 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18420 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18423 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18425 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18428 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18430 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18433 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18435 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
18436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18438 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18440 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
18441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18443 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
18445 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "or.w", 48,
18446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18448 /* or.w${G} $Src16RnHI,$Dst16RnHI */
18450 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
18451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18453 /* or.w${G} $Src16AnHI,$Dst16RnHI */
18455 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
18456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18458 /* or.w${G} [$Src16An],$Dst16RnHI */
18460 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "or.w", 16,
18461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18463 /* or.w${G} $Src16RnHI,$Dst16AnHI */
18465 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "or.w", 16,
18466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18468 /* or.w${G} $Src16AnHI,$Dst16AnHI */
18470 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "or.w", 16,
18471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18473 /* or.w${G} [$Src16An],$Dst16AnHI */
18475 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "or.w", 16,
18476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18478 /* or.w${G} $Src16RnHI,[$Dst16An] */
18480 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "or.w", 16,
18481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18483 /* or.w${G} $Src16AnHI,[$Dst16An] */
18485 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "or.w", 16,
18486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18488 /* or.w${G} [$Src16An],[$Dst16An] */
18490 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "or.w", 16,
18491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18493 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
18495 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18498 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
18500 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18503 /* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18505 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18508 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
18510 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18513 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
18515 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18518 /* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18520 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18523 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
18525 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18528 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
18530 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18533 /* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
18535 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18538 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
18540 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18543 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
18545 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18548 /* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
18550 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18553 /* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
18555 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18558 /* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
18560 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18563 /* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
18565 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18568 /* or.w${G} $Src16RnHI,${Dsp-16-u16} */
18570 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
18571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18573 /* or.w${G} $Src16AnHI,${Dsp-16-u16} */
18575 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
18576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18578 /* or.w${G} [$Src16An],${Dsp-16-u16} */
18580 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "or.w", 32,
18581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18583 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
18585 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18588 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
18590 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18593 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
18595 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18598 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
18600 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "or.b", 24,
18601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18603 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
18605 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "or.b", 24,
18606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18608 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
18610 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "or.b", 24,
18611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18613 /* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18615 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18618 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18620 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18623 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18625 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18628 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18630 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18633 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18635 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18638 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18640 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18643 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18645 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18648 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18650 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18653 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18655 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18658 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18660 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18663 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18665 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18668 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18670 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18673 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18675 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18678 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18680 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18683 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18685 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18688 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18690 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18693 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18695 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18698 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18700 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18703 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18705 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18708 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18710 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18713 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18715 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18718 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
18720 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
18721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18723 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
18725 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
18726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18728 /* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
18730 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "or.b", 32,
18731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18733 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
18735 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "or.b", 32,
18736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18738 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
18740 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "or.b", 32,
18741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18743 /* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
18745 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "or.b", 32,
18746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18748 /* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18750 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "or.b", 32,
18751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18753 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18755 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "or.b", 32,
18756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18758 /* or.b${G} ${Dsp-16-u16},[$Dst16An] */
18760 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "or.b", 32,
18761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18763 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18765 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18768 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18770 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18773 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18775 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18778 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18780 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18783 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18785 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18788 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18790 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18793 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18795 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18798 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18800 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18803 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18805 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18808 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18810 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18813 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18815 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18818 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18820 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18823 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18825 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18828 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18830 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18833 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18835 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18838 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18840 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
18841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18843 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18845 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
18846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18848 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
18850 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "or.b", 48,
18851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18853 /* or.b${G} $Src16RnQI,$Dst16RnQI */
18855 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
18856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18858 /* or.b${G} $Src16AnQI,$Dst16RnQI */
18860 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
18861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18863 /* or.b${G} [$Src16An],$Dst16RnQI */
18865 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "or.b", 16,
18866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18868 /* or.b${G} $Src16RnQI,$Dst16AnQI */
18870 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "or.b", 16,
18871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18873 /* or.b${G} $Src16AnQI,$Dst16AnQI */
18875 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "or.b", 16,
18876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18878 /* or.b${G} [$Src16An],$Dst16AnQI */
18880 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "or.b", 16,
18881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18883 /* or.b${G} $Src16RnQI,[$Dst16An] */
18885 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "or.b", 16,
18886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18888 /* or.b${G} $Src16AnQI,[$Dst16An] */
18890 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "or.b", 16,
18891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18893 /* or.b${G} [$Src16An],[$Dst16An] */
18895 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "or.b", 16,
18896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18898 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
18900 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18903 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
18905 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18908 /* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18910 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18913 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
18915 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18918 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
18920 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18923 /* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18925 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18928 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
18930 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18933 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
18935 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18938 /* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
18940 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18943 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
18945 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18948 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
18950 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18953 /* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
18955 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18958 /* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
18960 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18963 /* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
18965 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18968 /* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
18970 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18973 /* or.b${G} $Src16RnQI,${Dsp-16-u16} */
18975 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
18976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18978 /* or.b${G} $Src16AnQI,${Dsp-16-u16} */
18980 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
18981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18983 /* or.b${G} [$Src16An],${Dsp-16-u16} */
18985 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "or.b", 32,
18986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
18988 /* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
18990 M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "or.w", 32,
18991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18993 /* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
18995 M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "or.w", 32,
18996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
18998 /* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
19000 M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "or32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "or.w", 40,
19001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19003 /* or.w${S} #${Imm-8-HI},r0 */
19005 M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "or32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "or.w", 24,
19006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19008 /* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
19010 M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "or.b", 24,
19011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19013 /* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
19015 M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "or.b", 24,
19016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19018 /* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
19020 M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "or32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "or.b", 32,
19021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19023 /* or.b${S} #${Imm-8-QI},r0l */
19025 M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "or32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "or.b", 16,
19026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19028 /* or.b${S} #${Imm-8-QI},r0l */
19030 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "or.b", 16,
19031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19033 /* or.b${S} #${Imm-8-QI},r0h */
19035 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "or.b", 16,
19036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19038 /* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
19040 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "or.b", 24,
19041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19043 /* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
19045 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "or.b", 24,
19046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19048 /* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
19050 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "or.b", 32,
19051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19053 /* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
19055 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
19056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19058 /* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
19060 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "or.w", 32,
19061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19063 /* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
19065 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
19066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19068 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19070 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 40,
19071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19073 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19075 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 40,
19076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19078 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19080 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 40,
19081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19083 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19085 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 48,
19086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19088 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19090 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 48,
19091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19093 /* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
19095 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 48,
19096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19098 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19100 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "or.w", 48,
19101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19103 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19105 M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 56,
19106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19108 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
19110 M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "or.w", 56,
19111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19113 /* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
19115 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
19116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19118 /* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
19120 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "or.b", 24,
19121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19123 /* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19125 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
19126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19128 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19130 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 32,
19131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19133 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19135 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 32,
19136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19138 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19140 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 32,
19141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19143 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19145 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 40,
19146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19148 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19150 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 40,
19151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19153 /* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19155 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 40,
19156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19158 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19160 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "or.b", 40,
19161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19163 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19165 M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 48,
19166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19168 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
19170 M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "or.b", 48,
19171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19173 /* or.w${G} #${Imm-16-HI},$Dst16RnHI */
19175 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "or16.w-imm-G-basic-dst16-Rn-direct-HI", "or.w", 32,
19176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19178 /* or.w${G} #${Imm-16-HI},$Dst16AnHI */
19180 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "or16.w-imm-G-basic-dst16-An-direct-HI", "or.w", 32,
19181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19183 /* or.w${G} #${Imm-16-HI},[$Dst16An] */
19185 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "or16.w-imm-G-basic-dst16-An-indirect-HI", "or.w", 32,
19186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19188 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
19190 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "or.w", 40,
19191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19193 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19195 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "or.w", 40,
19196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19198 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19200 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "or.w", 40,
19201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19203 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
19205 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "or.w", 48,
19206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19208 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19210 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "or.w", 48,
19211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19213 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19215 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "or16.w-imm-G-16-16-dst16-16-16-absolute-HI", "or.w", 48,
19216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19218 /* or.b${G} #${Imm-16-QI},$Dst16RnQI */
19220 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "or16.b-imm-G-basic-dst16-Rn-direct-QI", "or.b", 24,
19221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19223 /* or.b${G} #${Imm-16-QI},$Dst16AnQI */
19225 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "or16.b-imm-G-basic-dst16-An-direct-QI", "or.b", 24,
19226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19228 /* or.b${G} #${Imm-16-QI},[$Dst16An] */
19230 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "or16.b-imm-G-basic-dst16-An-indirect-QI", "or.b", 24,
19231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19233 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
19235 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "or.b", 32,
19236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19238 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19240 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "or.b", 32,
19241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19243 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19245 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "or.b", 32,
19246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19248 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
19250 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "or.b", 40,
19251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19253 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19255 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "or.b", 40,
19256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19258 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19260 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40,
19261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19263 /* not.b:s r0l */
19265 M32C_INSN_NOT16_B_S_DST16_3_S_R0L_DIRECT_QI, "not16.b.s-dst16-3-S-R0l-direct-QI", "not.b:s", 8,
19266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19268 /* not.b:s r0h */
19270 M32C_INSN_NOT16_B_S_DST16_3_S_R0H_DIRECT_QI, "not16.b.s-dst16-3-S-R0h-direct-QI", "not.b:s", 8,
19271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19273 /* not.b:s ${Dsp-8-u8}[sb] */
19275 M32C_INSN_NOT16_B_S_DST16_3_S_8_8_SB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-SB-relative-QI", "not.b:s", 16,
19276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19278 /* not.b:s ${Dsp-8-s8}[fb] */
19280 M32C_INSN_NOT16_B_S_DST16_3_S_8_8_FB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-FB-relative-QI", "not.b:s", 16,
19281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19283 /* not.b:s ${Dsp-8-u16} */
19285 M32C_INSN_NOT16_B_S_DST16_3_S_8_16_ABSOLUTE_QI, "not16.b.s-dst16-3-S-8-16-absolute-QI", "not.b:s", 24,
19286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19288 /* not.w${G} $Dst32RnUnprefixedHI */
19290 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16,
19291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19293 /* not.w${G} $Dst32AnUnprefixedHI */
19295 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16,
19296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19298 /* not.w${G} [$Dst32AnUnprefixed] */
19300 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16,
19301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19303 /* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19305 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24,
19306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19308 /* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19310 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32,
19311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19313 /* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19315 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40,
19316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19318 /* not.w${G} ${Dsp-16-u8}[sb] */
19320 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24,
19321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19323 /* not.w${G} ${Dsp-16-u16}[sb] */
19325 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32,
19326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19328 /* not.w${G} ${Dsp-16-s8}[fb] */
19330 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24,
19331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19333 /* not.w${G} ${Dsp-16-s16}[fb] */
19335 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32,
19336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19338 /* not.w${G} ${Dsp-16-u16} */
19340 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32,
19341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19343 /* not.w${G} ${Dsp-16-u24} */
19345 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40,
19346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19348 /* not.b${G} $Dst32RnUnprefixedQI */
19350 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16,
19351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19353 /* not.b${G} $Dst32AnUnprefixedQI */
19355 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16,
19356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19358 /* not.b${G} [$Dst32AnUnprefixed] */
19360 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16,
19361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19363 /* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19365 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24,
19366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19368 /* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19370 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32,
19371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19373 /* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19375 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40,
19376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19378 /* not.b${G} ${Dsp-16-u8}[sb] */
19380 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24,
19381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19383 /* not.b${G} ${Dsp-16-u16}[sb] */
19385 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32,
19386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19388 /* not.b${G} ${Dsp-16-s8}[fb] */
19390 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24,
19391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19393 /* not.b${G} ${Dsp-16-s16}[fb] */
19395 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32,
19396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19398 /* not.b${G} ${Dsp-16-u16} */
19400 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32,
19401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19403 /* not.b${G} ${Dsp-16-u24} */
19405 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40,
19406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19408 /* not.w${G} $Dst16RnHI */
19410 M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16,
19411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19413 /* not.w${G} $Dst16AnHI */
19415 M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16,
19416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19418 /* not.w${G} [$Dst16An] */
19420 M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16,
19421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19423 /* not.w${G} ${Dsp-16-u8}[$Dst16An] */
19425 M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24,
19426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19428 /* not.w${G} ${Dsp-16-u16}[$Dst16An] */
19430 M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32,
19431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19433 /* not.w${G} ${Dsp-16-u8}[sb] */
19435 M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24,
19436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19438 /* not.w${G} ${Dsp-16-u16}[sb] */
19440 M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32,
19441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19443 /* not.w${G} ${Dsp-16-s8}[fb] */
19445 M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24,
19446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19448 /* not.w${G} ${Dsp-16-u16} */
19450 M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32,
19451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19453 /* not.b${G} $Dst16RnQI */
19455 M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16,
19456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19458 /* not.b${G} $Dst16AnQI */
19460 M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16,
19461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19463 /* not.b${G} [$Dst16An] */
19465 M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16,
19466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19468 /* not.b${G} ${Dsp-16-u8}[$Dst16An] */
19470 M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24,
19471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19473 /* not.b${G} ${Dsp-16-u16}[$Dst16An] */
19475 M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32,
19476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19478 /* not.b${G} ${Dsp-16-u8}[sb] */
19480 M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24,
19481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19483 /* not.b${G} ${Dsp-16-u16}[sb] */
19485 M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32,
19486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19488 /* not.b${G} ${Dsp-16-s8}[fb] */
19490 M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24,
19491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19493 /* not.b${G} ${Dsp-16-u16} */
19495 M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32,
19496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19498 /* neg.w $Dst32RnUnprefixedHI */
19500 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "neg.w", 16,
19501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19503 /* neg.w $Dst32AnUnprefixedHI */
19505 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "neg.w", 16,
19506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19508 /* neg.w [$Dst32AnUnprefixed] */
19510 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "neg.w", 16,
19511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19513 /* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19515 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "neg.w", 24,
19516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19518 /* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19520 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "neg.w", 32,
19521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19523 /* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19525 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "neg.w", 40,
19526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19528 /* neg.w ${Dsp-16-u8}[sb] */
19530 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "neg.w", 24,
19531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19533 /* neg.w ${Dsp-16-u16}[sb] */
19535 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "neg.w", 32,
19536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19538 /* neg.w ${Dsp-16-s8}[fb] */
19540 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "neg.w", 24,
19541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19543 /* neg.w ${Dsp-16-s16}[fb] */
19545 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "neg.w", 32,
19546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19548 /* neg.w ${Dsp-16-u16} */
19550 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "neg.w", 32,
19551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19553 /* neg.w ${Dsp-16-u24} */
19555 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "neg.w", 40,
19556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19558 /* neg.b $Dst32RnUnprefixedQI */
19560 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "neg.b", 16,
19561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19563 /* neg.b $Dst32AnUnprefixedQI */
19565 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "neg.b", 16,
19566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19568 /* neg.b [$Dst32AnUnprefixed] */
19570 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "neg.b", 16,
19571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19573 /* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19575 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "neg.b", 24,
19576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19578 /* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19580 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "neg.b", 32,
19581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19583 /* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19585 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "neg.b", 40,
19586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19588 /* neg.b ${Dsp-16-u8}[sb] */
19590 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "neg.b", 24,
19591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19593 /* neg.b ${Dsp-16-u16}[sb] */
19595 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "neg.b", 32,
19596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19598 /* neg.b ${Dsp-16-s8}[fb] */
19600 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "neg.b", 24,
19601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19603 /* neg.b ${Dsp-16-s16}[fb] */
19605 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "neg.b", 32,
19606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19608 /* neg.b ${Dsp-16-u16} */
19610 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "neg.b", 32,
19611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19613 /* neg.b ${Dsp-16-u24} */
19615 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "neg.b", 40,
19616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19618 /* neg.w $Dst16RnHI */
19620 M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, "neg16.w-16-dst16-Rn-direct-HI", "neg.w", 16,
19621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19623 /* neg.w $Dst16AnHI */
19625 M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, "neg16.w-16-dst16-An-direct-HI", "neg.w", 16,
19626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19628 /* neg.w [$Dst16An] */
19630 M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, "neg16.w-16-dst16-An-indirect-HI", "neg.w", 16,
19631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19633 /* neg.w ${Dsp-16-u8}[$Dst16An] */
19635 M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, "neg16.w-16-dst16-16-8-An-relative-HI", "neg.w", 24,
19636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19638 /* neg.w ${Dsp-16-u16}[$Dst16An] */
19640 M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, "neg16.w-16-dst16-16-16-An-relative-HI", "neg.w", 32,
19641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19643 /* neg.w ${Dsp-16-u8}[sb] */
19645 M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, "neg16.w-16-dst16-16-8-SB-relative-HI", "neg.w", 24,
19646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19648 /* neg.w ${Dsp-16-u16}[sb] */
19650 M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, "neg16.w-16-dst16-16-16-SB-relative-HI", "neg.w", 32,
19651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19653 /* neg.w ${Dsp-16-s8}[fb] */
19655 M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, "neg16.w-16-dst16-16-8-FB-relative-HI", "neg.w", 24,
19656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19658 /* neg.w ${Dsp-16-u16} */
19660 M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, "neg16.w-16-dst16-16-16-absolute-HI", "neg.w", 32,
19661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19663 /* neg.b $Dst16RnQI */
19665 M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, "neg16.b-16-dst16-Rn-direct-QI", "neg.b", 16,
19666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19668 /* neg.b $Dst16AnQI */
19670 M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, "neg16.b-16-dst16-An-direct-QI", "neg.b", 16,
19671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19673 /* neg.b [$Dst16An] */
19675 M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, "neg16.b-16-dst16-An-indirect-QI", "neg.b", 16,
19676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19678 /* neg.b ${Dsp-16-u8}[$Dst16An] */
19680 M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, "neg16.b-16-dst16-16-8-An-relative-QI", "neg.b", 24,
19681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19683 /* neg.b ${Dsp-16-u16}[$Dst16An] */
19685 M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, "neg16.b-16-dst16-16-16-An-relative-QI", "neg.b", 32,
19686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19688 /* neg.b ${Dsp-16-u8}[sb] */
19690 M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, "neg16.b-16-dst16-16-8-SB-relative-QI", "neg.b", 24,
19691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19693 /* neg.b ${Dsp-16-u16}[sb] */
19695 M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, "neg16.b-16-dst16-16-16-SB-relative-QI", "neg.b", 32,
19696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19698 /* neg.b ${Dsp-16-s8}[fb] */
19700 M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, "neg16.b-16-dst16-16-8-FB-relative-QI", "neg.b", 24,
19701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19703 /* neg.b ${Dsp-16-u16} */
19705 M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, "neg16.b-16-dst16-16-16-absolute-QI", "neg.b", 32,
19706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
19708 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19710 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19713 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
19715 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19718 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
19720 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19723 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19725 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19728 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
19730 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19733 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
19735 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19738 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19740 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19743 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
19745 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19748 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
19750 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19753 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19755 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19758 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19760 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19763 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19765 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19768 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19770 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19773 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19775 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19778 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19780 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19783 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19785 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19788 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19790 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19793 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19795 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19798 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
19800 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19803 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
19805 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19808 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
19810 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19813 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
19815 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19818 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
19820 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19823 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
19825 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19828 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
19830 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19833 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
19835 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19838 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
19840 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19843 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
19845 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19848 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
19850 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19853 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
19855 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19858 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
19860 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19863 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
19865 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19868 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
19870 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19873 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
19875 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19878 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
19880 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19883 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
19885 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19888 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19890 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19893 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
19895 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19898 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
19900 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19903 /* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
19905 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19908 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19910 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19913 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
19915 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19918 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
19920 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19923 /* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
19925 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19928 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19930 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19933 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
19935 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19938 /* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
19940 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19943 /* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
19945 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19948 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19950 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19953 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19955 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19958 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19960 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19963 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
19965 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19968 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19970 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19973 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19975 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19978 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19980 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19983 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
19985 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19988 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19990 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19993 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19995 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
19998 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20000 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
20001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20003 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
20005 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
20006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20008 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
20010 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
20011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20013 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
20015 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
20016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20018 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
20020 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
20021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20023 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
20025 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
20026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20028 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
20030 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20033 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
20035 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20038 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
20040 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20043 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
20045 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20048 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20050 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20053 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20055 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20058 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20060 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20063 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20065 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20068 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20070 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20073 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20075 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20078 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20080 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20083 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20085 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20088 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20090 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20093 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20095 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20098 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20100 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20103 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
20105 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20108 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20110 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20113 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20115 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20118 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20120 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20123 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
20125 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20128 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20130 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
20131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20133 /* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
20135 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
20136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20138 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20140 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
20141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20143 /* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
20145 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
20146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20148 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20150 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
20151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20153 /* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20155 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
20156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20158 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20160 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
20161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20163 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20165 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
20166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20168 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20170 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
20171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20173 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20175 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
20176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20178 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20180 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
20181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20183 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20185 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
20186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20188 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20190 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
20191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20193 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20195 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
20196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20198 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20200 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
20201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20203 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20205 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
20206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20208 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20210 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
20211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20213 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20215 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
20216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20218 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20220 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
20221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20223 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20225 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
20226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20228 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20230 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
20231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20233 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
20235 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
20236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20238 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20240 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
20241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20243 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
20245 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
20246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20248 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
20250 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20253 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
20255 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20258 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20260 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20263 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
20265 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20268 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
20270 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20273 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20275 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20278 /* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
20280 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20283 /* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
20285 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20288 /* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20290 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20293 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20295 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20298 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20300 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20303 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
20305 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20308 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20310 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20313 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20315 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20318 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
20320 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20323 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20325 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20328 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20330 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20333 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
20335 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20338 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
20340 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20343 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
20345 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20348 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
20350 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20353 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
20355 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20358 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
20360 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20363 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
20365 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20368 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
20370 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20373 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
20375 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20378 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
20380 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20383 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
20385 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20388 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
20390 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20393 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
20395 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20398 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
20400 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20403 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
20405 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20408 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
20410 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20413 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
20415 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20418 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
20420 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20423 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
20425 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20428 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20430 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20433 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
20435 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20438 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
20440 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20443 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20445 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20448 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
20450 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20453 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
20455 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20458 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20460 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20463 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
20465 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20468 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
20470 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20473 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20475 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20478 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20480 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20483 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20485 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20488 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20490 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20493 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20495 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20498 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20500 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20503 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20505 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20508 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20510 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20513 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20515 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20518 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
20520 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20523 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
20525 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20528 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
20530 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20533 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
20535 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20538 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
20540 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20543 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
20545 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20548 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
20550 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20553 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
20555 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20558 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
20560 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20563 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
20565 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20568 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
20570 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20573 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
20575 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20578 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
20580 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20583 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
20585 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20588 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
20590 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20593 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
20595 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20598 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
20600 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20603 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
20605 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20608 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20610 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20613 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
20615 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20618 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
20620 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20623 /* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
20625 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20628 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20630 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20633 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
20635 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20638 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
20640 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20643 /* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
20645 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20648 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20650 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20653 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
20655 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20658 /* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
20660 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20663 /* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
20665 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20668 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20670 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20673 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20675 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20678 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20680 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20683 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
20685 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20688 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20690 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20693 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20695 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20698 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20700 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20703 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
20705 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20708 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20710 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20713 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20715 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20718 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20720 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20723 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
20725 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20728 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
20730 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20733 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
20735 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20738 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
20740 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20743 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
20745 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20748 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
20750 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20753 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
20755 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20758 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
20760 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20763 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
20765 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20768 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20770 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20773 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20775 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20778 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20780 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20783 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20785 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20788 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20790 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20793 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20795 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20798 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20800 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20803 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20805 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20808 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20810 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20813 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20815 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20818 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20820 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20823 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
20825 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20828 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20830 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20833 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20835 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20838 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20840 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20843 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
20845 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20848 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20850 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
20851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20853 /* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
20855 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
20856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20858 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20860 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
20861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20863 /* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
20865 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
20866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20868 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20870 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
20871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20873 /* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20875 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
20876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20878 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20880 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
20881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20883 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20885 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
20886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20888 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20890 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
20891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20893 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20895 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
20896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20898 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20900 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
20901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20903 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20905 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
20906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20908 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20910 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
20911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20913 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20915 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
20916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20918 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20920 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
20921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20923 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20925 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
20926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20928 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20930 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
20931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20933 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20935 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
20936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20938 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20940 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
20941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20943 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20945 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
20946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20948 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20950 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
20951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20953 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
20955 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
20956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20958 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20960 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
20961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20963 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
20965 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
20966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20968 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
20970 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20973 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
20975 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20978 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20980 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20983 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
20985 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20988 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
20990 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20993 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20995 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
20998 /* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
21000 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
21001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21003 /* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
21005 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
21006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21008 /* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
21010 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
21011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21013 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
21015 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
21016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21018 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
21020 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
21021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21023 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
21025 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
21026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21028 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
21030 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
21031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21033 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
21035 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
21036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21038 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
21040 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
21041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21043 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
21045 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21048 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
21050 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21053 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
21055 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21058 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
21060 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21063 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
21065 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21068 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
21070 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21073 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
21075 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21078 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
21080 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21083 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
21085 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21088 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
21090 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21093 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
21095 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21098 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
21100 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21103 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
21105 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21108 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
21110 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21113 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
21115 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21118 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
21120 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21123 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
21125 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21128 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
21130 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21133 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
21135 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21138 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
21140 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21143 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
21145 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21148 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
21150 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21153 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
21155 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21158 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
21160 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21163 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
21165 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21168 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
21170 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21173 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
21175 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21178 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21180 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21183 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21185 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21188 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21190 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21193 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21195 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21198 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21200 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21203 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21205 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21208 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21210 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21213 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21215 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21218 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21220 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21223 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21225 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21228 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21230 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21233 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21235 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21238 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21240 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21243 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21245 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21248 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21250 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21253 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21255 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21258 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21260 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21263 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21265 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21268 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21270 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21273 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21275 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21278 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21280 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21283 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
21285 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21288 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
21290 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21293 /* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
21295 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21298 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
21300 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
21301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21303 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
21305 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
21306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21308 /* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
21310 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mulu.w", 32,
21311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21313 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21315 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
21316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21318 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21320 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
21321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21323 /* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
21325 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mulu.w", 32,
21326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21328 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21330 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21333 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21335 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21338 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21340 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21343 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21345 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21348 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21350 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21353 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21355 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21358 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21360 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21363 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21365 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21368 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21370 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21373 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21375 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21378 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21380 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21383 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21385 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21388 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21390 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21393 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21395 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21398 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21400 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21403 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21405 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21408 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21410 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21413 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
21415 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21418 /* mulu.w${G} $Src16RnHI,$Dst16RnHI */
21420 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21423 /* mulu.w${G} $Src16AnHI,$Dst16RnHI */
21425 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21428 /* mulu.w${G} [$Src16An],$Dst16RnHI */
21430 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21433 /* mulu.w${G} $Src16RnHI,$Dst16AnHI */
21435 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
21436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21438 /* mulu.w${G} $Src16AnHI,$Dst16AnHI */
21440 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
21441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21443 /* mulu.w${G} [$Src16An],$Dst16AnHI */
21445 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mulu.w", 16,
21446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21448 /* mulu.w${G} $Src16RnHI,[$Dst16An] */
21450 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
21451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21453 /* mulu.w${G} $Src16AnHI,[$Dst16An] */
21455 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
21456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21458 /* mulu.w${G} [$Src16An],[$Dst16An] */
21460 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mulu.w", 16,
21461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21463 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
21465 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21468 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
21470 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21473 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21475 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21478 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
21480 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21483 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
21485 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21488 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21490 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21493 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
21495 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21498 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
21500 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21503 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
21505 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21508 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
21510 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21513 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
21515 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21518 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
21520 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21523 /* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
21525 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21528 /* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
21530 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21533 /* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
21535 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21538 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
21540 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21543 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
21545 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21548 /* mulu.w${G} [$Src16An],${Dsp-16-u16} */
21550 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21553 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
21555 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21558 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
21560 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21563 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
21565 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21568 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
21570 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21573 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
21575 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21578 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
21580 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21583 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21585 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21588 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21590 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21593 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21595 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21598 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21600 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21603 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21605 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21608 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21610 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21613 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21615 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21618 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21620 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21623 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21625 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21628 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21630 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21633 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21635 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21638 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21640 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21643 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21645 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21648 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21650 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21653 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21655 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21658 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21660 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21663 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21665 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21668 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21670 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21673 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21675 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21678 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21680 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21683 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21685 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21688 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
21690 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21693 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
21695 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21698 /* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
21700 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21703 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
21705 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
21706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21708 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
21710 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
21711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21713 /* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
21715 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mulu.b", 32,
21716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21718 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21720 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
21721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21723 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21725 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
21726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21728 /* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
21730 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mulu.b", 32,
21731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21733 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21735 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21738 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21740 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21743 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21745 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21748 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21750 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21753 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21755 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21758 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21760 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21763 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21765 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21768 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21770 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21773 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21775 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21778 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21780 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21783 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21785 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21788 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21790 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21793 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21795 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21798 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21800 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21803 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21805 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21808 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21810 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21813 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21815 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21818 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
21820 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21823 /* mulu.b${G} $Src16RnQI,$Dst16RnQI */
21825 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21828 /* mulu.b${G} $Src16AnQI,$Dst16RnQI */
21830 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21833 /* mulu.b${G} [$Src16An],$Dst16RnQI */
21835 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21838 /* mulu.b${G} $Src16RnQI,$Dst16AnQI */
21840 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
21841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21843 /* mulu.b${G} $Src16AnQI,$Dst16AnQI */
21845 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
21846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21848 /* mulu.b${G} [$Src16An],$Dst16AnQI */
21850 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mulu.b", 16,
21851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21853 /* mulu.b${G} $Src16RnQI,[$Dst16An] */
21855 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
21856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21858 /* mulu.b${G} $Src16AnQI,[$Dst16An] */
21860 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
21861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21863 /* mulu.b${G} [$Src16An],[$Dst16An] */
21865 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mulu.b", 16,
21866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21868 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
21870 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21873 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
21875 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21878 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21880 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21883 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
21885 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21888 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
21890 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21893 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21895 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21898 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
21900 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21903 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
21905 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21908 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
21910 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21913 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
21915 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21918 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
21920 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21923 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
21925 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21928 /* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
21930 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21933 /* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
21935 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21938 /* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
21940 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21943 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
21945 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21948 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
21950 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21953 /* mulu.b${G} [$Src16An],${Dsp-16-u16} */
21955 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
21958 /* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
21960 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
21961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21963 /* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
21965 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
21966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21968 /* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
21970 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
21971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21973 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
21975 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 40,
21976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21978 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
21980 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
21981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21983 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
21985 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
21986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21988 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
21990 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 48,
21991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21993 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
21995 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
21996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
21998 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
22000 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
22001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22003 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
22005 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 48,
22006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22008 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
22010 M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 56,
22011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22013 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
22015 M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 56,
22016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22018 /* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
22020 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
22021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22023 /* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
22025 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
22026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22028 /* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
22030 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
22031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22033 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
22035 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 32,
22036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22038 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22040 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
22041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22043 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22045 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
22046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22048 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
22050 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 40,
22051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22053 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22055 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
22056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22058 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
22060 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
22061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22063 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22065 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 40,
22066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22068 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
22070 M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 48,
22071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22073 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
22075 M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 48,
22076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22078 /* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
22080 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-Rn-direct-HI", "mulu.w", 32,
22081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22083 /* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
22085 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-direct-HI", "mulu.w", 32,
22086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22088 /* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
22090 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-indirect-HI", "mulu.w", 32,
22091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22093 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
22095 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mulu.w", 40,
22096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22098 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
22100 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mulu.w", 40,
22101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22103 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
22105 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mulu.w", 40,
22106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22108 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
22110 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mulu.w", 48,
22111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22113 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
22115 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mulu.w", 48,
22116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22118 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
22120 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mulu.w", 48,
22121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22123 /* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
22125 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-Rn-direct-QI", "mulu.b", 24,
22126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22128 /* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
22130 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-direct-QI", "mulu.b", 24,
22131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22133 /* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
22135 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-indirect-QI", "mulu.b", 24,
22136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22138 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
22140 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mulu.b", 32,
22141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22143 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22145 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mulu.b", 32,
22146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22148 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22150 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mulu.b", 32,
22151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22153 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
22155 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mulu.b", 40,
22156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22158 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22160 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mulu.b", 40,
22161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22163 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22165 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mulu.b", 40,
22166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
22168 /* mulex $R3 */
22170 M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, "mulex-dst32-R3-direct-Unprefixed-HI", "mulex", 16,
22171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22173 /* mulex $Dst32AnUnprefixedHI */
22175 M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, "mulex-dst32-An-direct-Unprefixed-HI", "mulex", 16,
22176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22178 /* mulex [$Dst32AnUnprefixed] */
22180 M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulex-dst32-An-indirect-Unprefixed-HI", "mulex", 16,
22181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22183 /* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
22185 M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-An-relative-Unprefixed-HI", "mulex", 24,
22186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22188 /* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
22190 M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-An-relative-Unprefixed-HI", "mulex", 32,
22191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22193 /* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
22195 M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-24-An-relative-Unprefixed-HI", "mulex", 40,
22196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22198 /* mulex ${Dsp-16-u8}[sb] */
22200 M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-SB-relative-Unprefixed-HI", "mulex", 24,
22201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22203 /* mulex ${Dsp-16-u16}[sb] */
22205 M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-SB-relative-Unprefixed-HI", "mulex", 32,
22206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22208 /* mulex ${Dsp-16-s8}[fb] */
22210 M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-FB-relative-Unprefixed-HI", "mulex", 24,
22211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22213 /* mulex ${Dsp-16-s16}[fb] */
22215 M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-FB-relative-Unprefixed-HI", "mulex", 32,
22216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22218 /* mulex ${Dsp-16-u16} */
22220 M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-16-absolute-Unprefixed-HI", "mulex", 32,
22221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22223 /* mulex ${Dsp-16-u24} */
22225 M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-24-absolute-Unprefixed-HI", "mulex", 40,
22226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22228 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22230 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22233 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
22235 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22238 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
22240 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22243 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22245 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22248 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
22250 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22253 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
22255 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22258 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22260 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22263 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22265 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22268 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
22270 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22273 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22275 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22278 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22280 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22283 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22285 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22288 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22290 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22293 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22295 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22298 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22300 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22303 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22305 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22308 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22310 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22313 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22315 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22318 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
22320 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22323 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
22325 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22328 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
22330 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22333 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
22335 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22338 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
22340 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22343 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
22345 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22348 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
22350 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22353 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
22355 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22358 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
22360 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22363 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
22365 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22368 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
22370 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22373 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
22375 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22378 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
22380 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22383 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
22385 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22388 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
22390 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22393 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
22395 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22398 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
22400 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22403 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
22405 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22408 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22410 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22413 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
22415 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22418 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
22420 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22423 /* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
22425 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22428 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22430 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22433 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
22435 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22438 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
22440 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22443 /* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
22445 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22448 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22450 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22453 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
22455 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22458 /* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
22460 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22463 /* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
22465 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22468 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22470 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22473 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22475 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22478 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22480 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22483 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
22485 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22488 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22490 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22493 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22495 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22498 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22500 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22503 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
22505 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22508 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22510 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22513 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22515 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22518 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22520 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22523 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
22525 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22528 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
22530 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22533 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22535 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22538 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
22540 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22543 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22545 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22548 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
22550 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22553 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22555 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22558 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
22560 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22563 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22565 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22568 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
22570 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22573 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22575 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22578 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
22580 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22583 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22585 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22588 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
22590 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22593 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
22595 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22598 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
22600 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22603 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
22605 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22608 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
22610 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22613 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22615 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22618 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
22620 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22623 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
22625 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22628 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
22630 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22633 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
22635 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22638 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
22640 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22643 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
22645 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22648 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22650 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
22651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22653 /* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
22655 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
22656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22658 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22660 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
22661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22663 /* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
22665 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
22666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22668 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22670 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
22671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22673 /* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
22675 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
22676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22678 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
22680 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
22681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22683 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
22685 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
22686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22688 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
22690 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
22691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22693 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
22695 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
22696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22698 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
22700 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
22701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22703 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
22705 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
22706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22708 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
22710 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
22711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22713 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
22715 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
22716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22718 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
22720 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
22721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22723 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
22725 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
22726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22728 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
22730 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
22731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22733 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
22735 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
22736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22738 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
22740 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
22741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22743 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
22745 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
22746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22748 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
22750 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
22751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22753 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
22755 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
22756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22758 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
22760 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
22761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22763 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
22765 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
22766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22768 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
22770 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22773 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
22775 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22778 /* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22780 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22783 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
22785 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22788 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
22790 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22793 /* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22795 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22798 /* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
22800 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22803 /* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
22805 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22808 /* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22810 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22813 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22815 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22818 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22820 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22823 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
22825 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22828 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22830 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22833 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22835 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22838 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
22840 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22843 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22845 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22848 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22850 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22853 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
22855 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22858 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
22860 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22863 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
22865 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22868 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
22870 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22873 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
22875 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22878 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
22880 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22883 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
22885 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22888 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
22890 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22893 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
22895 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22898 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
22900 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22903 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
22905 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22908 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
22910 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22913 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
22915 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22918 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
22920 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22923 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
22925 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22928 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
22930 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22933 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
22935 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22938 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
22940 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22943 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
22945 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22948 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
22950 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22953 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
22955 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22958 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
22960 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22963 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
22965 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22968 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
22970 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22973 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
22975 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22978 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22980 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22983 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22985 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22988 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
22990 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22993 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22995 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
22998 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
23000 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
23001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23003 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
23005 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
23006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23008 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
23010 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
23011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23013 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
23015 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
23016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23018 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
23020 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
23021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23023 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23025 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
23026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23028 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23030 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
23031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23033 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23035 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
23036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23038 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
23040 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23043 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
23045 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23048 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23050 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23053 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
23055 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23058 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23060 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23063 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23065 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23068 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
23070 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23073 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23075 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23078 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23080 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23083 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
23085 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23088 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
23090 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23093 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
23095 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23098 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
23100 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23103 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23105 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23108 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23110 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23113 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
23115 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23118 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
23120 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23123 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
23125 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23128 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23130 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23133 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
23135 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23138 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
23140 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23143 /* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
23145 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23148 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23150 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23153 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
23155 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23158 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
23160 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23163 /* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
23165 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23168 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23170 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23173 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
23175 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23178 /* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
23180 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23183 /* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
23185 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23188 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23190 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23193 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23195 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23198 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23200 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23203 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
23205 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23208 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23210 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23213 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23215 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23218 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23220 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23223 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
23225 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23228 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23230 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23233 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23235 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23238 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23240 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23243 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
23245 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23248 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
23250 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23253 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23255 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23258 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
23260 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23263 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23265 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23268 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
23270 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23273 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23275 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23278 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
23280 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23283 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23285 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23288 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
23290 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23293 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23295 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23298 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
23300 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23303 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23305 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23308 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
23310 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23313 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
23315 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23318 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
23320 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23323 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
23325 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23328 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
23330 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23333 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23335 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23338 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
23340 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23343 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
23345 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23348 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
23350 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23353 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
23355 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23358 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
23360 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23363 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
23365 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23368 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23370 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
23371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23373 /* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
23375 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
23376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23378 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23380 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
23381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23383 /* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
23385 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
23386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23388 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23390 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
23391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23393 /* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
23395 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
23396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23398 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
23400 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
23401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23403 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
23405 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
23406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23408 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
23410 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
23411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23413 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
23415 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
23416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23418 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
23420 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
23421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23423 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
23425 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
23426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23428 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
23430 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
23431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23433 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
23435 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
23436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23438 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
23440 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
23441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23443 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
23445 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
23446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23448 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
23450 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
23451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23453 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
23455 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
23456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23458 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
23460 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
23461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23463 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
23465 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
23466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23468 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
23470 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
23471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23473 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
23475 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
23476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23478 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
23480 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
23481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23483 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
23485 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
23486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23488 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
23490 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23493 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
23495 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23498 /* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23500 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23503 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
23505 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23508 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
23510 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23513 /* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23515 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23518 /* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
23520 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23523 /* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
23525 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23528 /* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23530 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23533 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23535 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23538 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23540 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23543 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
23545 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23548 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23550 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23553 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23555 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23558 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
23560 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23563 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23565 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23568 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23570 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23573 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
23575 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23578 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
23580 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23583 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
23585 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23588 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
23590 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23593 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
23595 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23598 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
23600 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23603 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
23605 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23608 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
23610 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23613 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
23615 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23618 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
23620 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23623 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
23625 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23628 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
23630 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23633 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
23635 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23638 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
23640 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23643 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
23645 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23648 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
23650 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23653 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
23655 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23658 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
23660 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23663 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
23665 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
23668 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
23670 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23673 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
23675 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23678 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
23680 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23683 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
23685 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23688 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
23690 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23693 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
23695 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23698 /* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
23700 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23703 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
23705 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23708 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
23710 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23713 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
23715 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23718 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
23720 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23723 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
23725 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23728 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
23730 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23733 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
23735 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23738 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
23740 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23743 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
23745 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23748 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
23750 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23753 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23755 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23758 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
23760 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23763 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23765 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23768 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23770 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23773 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
23775 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23778 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23780 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23783 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23785 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23788 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
23790 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23793 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23795 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23798 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23800 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23803 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
23805 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
23806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23808 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
23810 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
23811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23813 /* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
23815 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mul.w", 32,
23816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23818 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
23820 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mul.w", 32,
23821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23823 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
23825 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mul.w", 32,
23826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23828 /* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
23830 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mul.w", 32,
23831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23833 /* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
23835 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
23836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23838 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
23840 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
23841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23843 /* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
23845 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mul.w", 32,
23846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23848 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
23850 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23853 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
23855 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23858 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
23860 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23863 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
23865 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23868 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
23870 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23873 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
23875 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23878 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
23880 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23883 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23885 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23888 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23890 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23893 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
23895 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23898 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23900 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23903 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23905 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23908 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
23910 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23913 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23915 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23918 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23920 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23923 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
23925 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23928 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23930 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23933 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
23935 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23938 /* mul.w${G} $Src16RnHI,$Dst16RnHI */
23940 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
23941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23943 /* mul.w${G} $Src16AnHI,$Dst16RnHI */
23945 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
23946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23948 /* mul.w${G} [$Src16An],$Dst16RnHI */
23950 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mul.w", 16,
23951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23953 /* mul.w${G} $Src16RnHI,$Dst16AnHI */
23955 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mul.w", 16,
23956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23958 /* mul.w${G} $Src16AnHI,$Dst16AnHI */
23960 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mul.w", 16,
23961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23963 /* mul.w${G} [$Src16An],$Dst16AnHI */
23965 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mul.w", 16,
23966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23968 /* mul.w${G} $Src16RnHI,[$Dst16An] */
23970 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
23971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23973 /* mul.w${G} $Src16AnHI,[$Dst16An] */
23975 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
23976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23978 /* mul.w${G} [$Src16An],[$Dst16An] */
23980 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mul.w", 16,
23981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23983 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
23985 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23988 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
23990 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23993 /* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
23995 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
23998 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
24000 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
24001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24003 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
24005 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
24006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24008 /* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
24010 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
24011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24013 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
24015 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
24016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24018 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
24020 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
24021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24023 /* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
24025 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
24026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24028 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
24030 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
24031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24033 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
24035 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
24036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24038 /* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
24040 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
24041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24043 /* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
24045 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24048 /* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
24050 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24053 /* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
24055 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24058 /* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
24060 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24063 /* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
24065 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24068 /* mul.w${G} [$Src16An],${Dsp-16-u16} */
24070 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24073 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
24075 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24078 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
24080 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24083 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
24085 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24088 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
24090 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24093 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
24095 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24098 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
24100 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24103 /* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
24105 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24108 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
24110 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24113 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
24115 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24118 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
24120 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24123 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
24125 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24128 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
24130 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24133 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
24135 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24138 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
24140 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24143 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
24145 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24148 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
24150 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24153 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
24155 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24158 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
24160 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24163 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
24165 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24168 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
24170 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24173 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
24175 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24178 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
24180 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24183 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
24185 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24188 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
24190 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24193 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
24195 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24198 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
24200 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24203 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
24205 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24208 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
24210 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
24211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24213 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
24215 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
24216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24218 /* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
24220 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mul.b", 32,
24221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24223 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
24225 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mul.b", 32,
24226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24228 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
24230 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mul.b", 32,
24231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24233 /* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
24235 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mul.b", 32,
24236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24238 /* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
24240 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
24241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24243 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
24245 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
24246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24248 /* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
24250 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mul.b", 32,
24251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24253 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
24255 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24258 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
24260 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24263 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
24265 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24268 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
24270 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24273 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
24275 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24278 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
24280 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24283 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
24285 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24288 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
24290 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24293 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
24295 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24298 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
24300 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24303 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
24305 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24308 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
24310 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24313 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
24315 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24318 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
24320 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24323 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
24325 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24328 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
24330 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24333 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
24335 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24338 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
24340 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24343 /* mul.b${G} $Src16RnQI,$Dst16RnQI */
24345 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
24346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24348 /* mul.b${G} $Src16AnQI,$Dst16RnQI */
24350 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
24351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24353 /* mul.b${G} [$Src16An],$Dst16RnQI */
24355 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mul.b", 16,
24356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24358 /* mul.b${G} $Src16RnQI,$Dst16AnQI */
24360 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mul.b", 16,
24361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24363 /* mul.b${G} $Src16AnQI,$Dst16AnQI */
24365 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mul.b", 16,
24366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24368 /* mul.b${G} [$Src16An],$Dst16AnQI */
24370 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mul.b", 16,
24371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24373 /* mul.b${G} $Src16RnQI,[$Dst16An] */
24375 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
24376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24378 /* mul.b${G} $Src16AnQI,[$Dst16An] */
24380 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
24381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24383 /* mul.b${G} [$Src16An],[$Dst16An] */
24385 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mul.b", 16,
24386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24388 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
24390 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24393 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
24395 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24398 /* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
24400 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24403 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
24405 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24408 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
24410 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24413 /* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
24415 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24418 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
24420 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24423 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
24425 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24428 /* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
24430 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24433 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
24435 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24438 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
24440 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24443 /* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
24445 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24448 /* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
24450 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24453 /* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
24455 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24458 /* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
24460 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24463 /* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
24465 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24468 /* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
24470 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24473 /* mul.b${G} [$Src16An],${Dsp-16-u16} */
24475 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24478 /* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
24480 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
24481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24483 /* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
24485 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
24486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24488 /* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
24490 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
24491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24493 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24495 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 40,
24496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24498 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24500 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 40,
24501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24503 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24505 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 40,
24506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24508 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24510 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 48,
24511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24513 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24515 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 48,
24516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24518 /* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
24520 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 48,
24521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24523 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24525 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 48,
24526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24528 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24530 M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 56,
24531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24533 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
24535 M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 56,
24536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24538 /* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
24540 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
24541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24543 /* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
24545 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
24546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24548 /* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24550 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
24551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24553 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24555 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 32,
24556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24558 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24560 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 32,
24561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24563 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24565 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 32,
24566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24568 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24570 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 40,
24571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24573 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24575 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 40,
24576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24578 /* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24580 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 40,
24581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24583 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24585 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 40,
24586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24588 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24590 M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 48,
24591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24593 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
24595 M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 48,
24596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24598 /* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
24600 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-Rn-direct-HI", "mul.w", 32,
24601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24603 /* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
24605 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-An-direct-HI", "mul.w", 32,
24606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24608 /* mul.w${G} #${Imm-16-HI},[$Dst16An] */
24610 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mul16.w-imm-G-basic-dst16-An-indirect-HI", "mul.w", 32,
24611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24613 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
24615 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mul.w", 40,
24616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24618 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24620 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mul.w", 40,
24621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24623 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24625 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mul.w", 40,
24626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24628 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
24630 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mul.w", 48,
24631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24633 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24635 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mul.w", 48,
24636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24638 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24640 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mul16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mul.w", 48,
24641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24643 /* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
24645 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-Rn-direct-QI", "mul.b", 24,
24646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24648 /* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
24650 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-An-direct-QI", "mul.b", 24,
24651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24653 /* mul.b${G} #${Imm-16-QI},[$Dst16An] */
24655 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mul16.b-imm-G-basic-dst16-An-indirect-QI", "mul.b", 24,
24656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24658 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
24660 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mul.b", 32,
24661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24663 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24665 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mul.b", 32,
24666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24668 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24670 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mul.b", 32,
24671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24673 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
24675 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mul.b", 40,
24676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24678 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24680 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mul.b", 40,
24681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24683 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24685 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mul16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mul.b", 40,
24686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
24688 /* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
24690 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "movx", 24,
24691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24693 /* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
24695 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "movx", 24,
24696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24698 /* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24700 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "movx", 24,
24701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24703 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24705 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "movx", 32,
24706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24708 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24710 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "movx", 32,
24711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24713 /* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24715 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "movx", 32,
24716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24718 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24720 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "movx", 40,
24721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24723 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24725 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "movx", 40,
24726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24728 /* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24730 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "movx", 40,
24731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24733 /* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
24735 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "movx", 40,
24736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24738 /* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24740 M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "movx", 48,
24741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24743 /* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
24745 M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "movx", 48,
24746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24748 /* movhh $Dst32RnPrefixedQI,r0l */
24750 M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
24751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24753 /* movhh $Dst32AnPrefixedQI,r0l */
24755 M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-direct-Prefixed-QI", "movhh", 24,
24756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24758 /* movhh [$Dst32AnPrefixed],r0l */
24760 M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhh", 24,
24761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24763 /* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24765 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
24766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24768 /* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24770 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
24771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24773 /* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24775 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
24776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24778 /* movhh ${Dsp-24-u8}[sb],r0l */
24780 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
24781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24783 /* movhh ${Dsp-24-u16}[sb],r0l */
24785 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
24786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24788 /* movhh ${Dsp-24-s8}[fb],r0l */
24790 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
24791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24793 /* movhh ${Dsp-24-s16}[fb],r0l */
24795 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
24796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24798 /* movhh ${Dsp-24-u16},r0l */
24800 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
24801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24803 /* movhh ${Dsp-24-u24},r0l */
24805 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
24806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24808 /* movhl $Dst32RnPrefixedQI,r0l */
24810 M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
24811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24813 /* movhl $Dst32AnPrefixedQI,r0l */
24815 M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-direct-Prefixed-QI", "movhl", 24,
24816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24818 /* movhl [$Dst32AnPrefixed],r0l */
24820 M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhl", 24,
24821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24823 /* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24825 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
24826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24828 /* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24830 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
24831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24833 /* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24835 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
24836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24838 /* movhl ${Dsp-24-u8}[sb],r0l */
24840 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
24841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24843 /* movhl ${Dsp-24-u16}[sb],r0l */
24845 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
24846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24848 /* movhl ${Dsp-24-s8}[fb],r0l */
24850 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
24851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24853 /* movhl ${Dsp-24-s16}[fb],r0l */
24855 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
24856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24858 /* movhl ${Dsp-24-u16},r0l */
24860 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
24861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24863 /* movhl ${Dsp-24-u24},r0l */
24865 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
24866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24868 /* movlh $Dst32RnPrefixedQI,r0l */
24870 M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
24871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24873 /* movlh $Dst32AnPrefixedQI,r0l */
24875 M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-direct-Prefixed-QI", "movlh", 24,
24876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24878 /* movlh [$Dst32AnPrefixed],r0l */
24880 M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movlh", 24,
24881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24883 /* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24885 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
24886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24888 /* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24890 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
24891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24893 /* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24895 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
24896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24898 /* movlh ${Dsp-24-u8}[sb],r0l */
24900 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
24901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24903 /* movlh ${Dsp-24-u16}[sb],r0l */
24905 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
24906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24908 /* movlh ${Dsp-24-s8}[fb],r0l */
24910 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
24911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24913 /* movlh ${Dsp-24-s16}[fb],r0l */
24915 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
24916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24918 /* movlh ${Dsp-24-u16},r0l */
24920 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
24921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24923 /* movlh ${Dsp-24-u24},r0l */
24925 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
24926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24928 /* movll $Dst32RnPrefixedQI,r0l */
24930 M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movll", 24,
24931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24933 /* movll $Dst32AnPrefixedQI,r0l */
24935 M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-direct-Prefixed-QI", "movll", 24,
24936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24938 /* movll [$Dst32AnPrefixed],r0l */
24940 M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-indirect-Prefixed-QI", "movll", 24,
24941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24943 /* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24945 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
24946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24948 /* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24950 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
24951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24953 /* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24955 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
24956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24958 /* movll ${Dsp-24-u8}[sb],r0l */
24960 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
24961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24963 /* movll ${Dsp-24-u16}[sb],r0l */
24965 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
24966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24968 /* movll ${Dsp-24-s8}[fb],r0l */
24970 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
24971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24973 /* movll ${Dsp-24-s16}[fb],r0l */
24975 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
24976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24978 /* movll ${Dsp-24-u16},r0l */
24980 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
24981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24983 /* movll ${Dsp-24-u24},r0l */
24985 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
24986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24988 /* movhh r0l,$Dst32RnPrefixedQI */
24990 M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
24991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24993 /* movhh r0l,$Dst32AnPrefixedQI */
24995 M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhh", 24,
24996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
24998 /* movhh r0l,[$Dst32AnPrefixed] */
25000 M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhh", 24,
25001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25003 /* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25005 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
25006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25008 /* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25010 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
25011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25013 /* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25015 M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
25016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25018 /* movhh r0l,${Dsp-24-u8}[sb] */
25020 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
25021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25023 /* movhh r0l,${Dsp-24-u16}[sb] */
25025 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
25026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25028 /* movhh r0l,${Dsp-24-s8}[fb] */
25030 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
25031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25033 /* movhh r0l,${Dsp-24-s16}[fb] */
25035 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
25036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25038 /* movhh r0l,${Dsp-24-u16} */
25040 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
25041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25043 /* movhh r0l,${Dsp-24-u24} */
25045 M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
25046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25048 /* movhl r0l,$Dst32RnPrefixedQI */
25050 M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
25051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25053 /* movhl r0l,$Dst32AnPrefixedQI */
25055 M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhl", 24,
25056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25058 /* movhl r0l,[$Dst32AnPrefixed] */
25060 M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhl", 24,
25061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25063 /* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25065 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
25066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25068 /* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25070 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
25071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25073 /* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25075 M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
25076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25078 /* movhl r0l,${Dsp-24-u8}[sb] */
25080 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
25081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25083 /* movhl r0l,${Dsp-24-u16}[sb] */
25085 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
25086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25088 /* movhl r0l,${Dsp-24-s8}[fb] */
25090 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
25091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25093 /* movhl r0l,${Dsp-24-s16}[fb] */
25095 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
25096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25098 /* movhl r0l,${Dsp-24-u16} */
25100 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
25101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25103 /* movhl r0l,${Dsp-24-u24} */
25105 M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
25106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25108 /* movlh r0l,$Dst32RnPrefixedQI */
25110 M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
25111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25113 /* movlh r0l,$Dst32AnPrefixedQI */
25115 M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movlh", 24,
25116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25118 /* movlh r0l,[$Dst32AnPrefixed] */
25120 M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movlh", 24,
25121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25123 /* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25125 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
25126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25128 /* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25130 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
25131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25133 /* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25135 M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
25136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25138 /* movlh r0l,${Dsp-24-u8}[sb] */
25140 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
25141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25143 /* movlh r0l,${Dsp-24-u16}[sb] */
25145 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
25146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25148 /* movlh r0l,${Dsp-24-s8}[fb] */
25150 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
25151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25153 /* movlh r0l,${Dsp-24-s16}[fb] */
25155 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
25156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25158 /* movlh r0l,${Dsp-24-u16} */
25160 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
25161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25163 /* movlh r0l,${Dsp-24-u24} */
25165 M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
25166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25168 /* movll r0l,$Dst32RnPrefixedQI */
25170 M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movll", 24,
25171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25173 /* movll r0l,$Dst32AnPrefixedQI */
25175 M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-direct-Prefixed-QI", "movll", 24,
25176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25178 /* movll r0l,[$Dst32AnPrefixed] */
25180 M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movll", 24,
25181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25183 /* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25185 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
25186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25188 /* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25190 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
25191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25193 /* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25195 M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
25196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25198 /* movll r0l,${Dsp-24-u8}[sb] */
25200 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
25201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25203 /* movll r0l,${Dsp-24-u16}[sb] */
25205 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
25206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25208 /* movll r0l,${Dsp-24-s8}[fb] */
25210 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
25211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25213 /* movll r0l,${Dsp-24-s16}[fb] */
25215 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
25216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25218 /* movll r0l,${Dsp-24-u16} */
25220 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
25221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25223 /* movll r0l,${Dsp-24-u24} */
25225 M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
25226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25228 /* movhh $Dst16RnQI,r0l */
25230 M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, "movhh16.src-r0l-dst16-Rn-direct-QI", "movhh", 16,
25231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25233 /* movhh $Dst16AnQI,r0l */
25235 M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, "movhh16.src-r0l-dst16-An-direct-QI", "movhh", 16,
25236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25238 /* movhh [$Dst16An],r0l */
25240 M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhh16.src-r0l-dst16-An-indirect-QI", "movhh", 16,
25241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25243 /* movhh ${Dsp-16-u8}[$Dst16An],r0l */
25245 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-An-relative-QI", "movhh", 24,
25246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25248 /* movhh ${Dsp-16-u16}[$Dst16An],r0l */
25250 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-An-relative-QI", "movhh", 32,
25251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25253 /* movhh ${Dsp-16-u8}[sb],r0l */
25255 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-SB-relative-QI", "movhh", 24,
25256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25258 /* movhh ${Dsp-16-u16}[sb],r0l */
25260 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-SB-relative-QI", "movhh", 32,
25261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25263 /* movhh ${Dsp-16-s8}[fb],r0l */
25265 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-FB-relative-QI", "movhh", 24,
25266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25268 /* movhh ${Dsp-16-u16},r0l */
25270 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhh16.src-r0l-dst16-16-16-absolute-QI", "movhh", 32,
25271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25273 /* movhl $Dst16RnQI,r0l */
25275 M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, "movhl16.src-r0l-dst16-Rn-direct-QI", "movhl", 16,
25276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25278 /* movhl $Dst16AnQI,r0l */
25280 M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, "movhl16.src-r0l-dst16-An-direct-QI", "movhl", 16,
25281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25283 /* movhl [$Dst16An],r0l */
25285 M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhl16.src-r0l-dst16-An-indirect-QI", "movhl", 16,
25286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25288 /* movhl ${Dsp-16-u8}[$Dst16An],r0l */
25290 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-An-relative-QI", "movhl", 24,
25291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25293 /* movhl ${Dsp-16-u16}[$Dst16An],r0l */
25295 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-An-relative-QI", "movhl", 32,
25296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25298 /* movhl ${Dsp-16-u8}[sb],r0l */
25300 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-SB-relative-QI", "movhl", 24,
25301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25303 /* movhl ${Dsp-16-u16}[sb],r0l */
25305 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-SB-relative-QI", "movhl", 32,
25306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25308 /* movhl ${Dsp-16-s8}[fb],r0l */
25310 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-FB-relative-QI", "movhl", 24,
25311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25313 /* movhl ${Dsp-16-u16},r0l */
25315 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhl16.src-r0l-dst16-16-16-absolute-QI", "movhl", 32,
25316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25318 /* movlh $Dst16RnQI,r0l */
25320 M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, "movlh16.src-r0l-dst16-Rn-direct-QI", "movlh", 16,
25321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25323 /* movlh $Dst16AnQI,r0l */
25325 M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, "movlh16.src-r0l-dst16-An-direct-QI", "movlh", 16,
25326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25328 /* movlh [$Dst16An],r0l */
25330 M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movlh16.src-r0l-dst16-An-indirect-QI", "movlh", 16,
25331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25333 /* movlh ${Dsp-16-u8}[$Dst16An],r0l */
25335 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-An-relative-QI", "movlh", 24,
25336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25338 /* movlh ${Dsp-16-u16}[$Dst16An],r0l */
25340 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-An-relative-QI", "movlh", 32,
25341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25343 /* movlh ${Dsp-16-u8}[sb],r0l */
25345 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-SB-relative-QI", "movlh", 24,
25346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25348 /* movlh ${Dsp-16-u16}[sb],r0l */
25350 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-SB-relative-QI", "movlh", 32,
25351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25353 /* movlh ${Dsp-16-s8}[fb],r0l */
25355 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-FB-relative-QI", "movlh", 24,
25356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25358 /* movlh ${Dsp-16-u16},r0l */
25360 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movlh16.src-r0l-dst16-16-16-absolute-QI", "movlh", 32,
25361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25363 /* movll $Dst16RnQI,r0l */
25365 M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, "movll16.src-r0l-dst16-Rn-direct-QI", "movll", 16,
25366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25368 /* movll $Dst16AnQI,r0l */
25370 M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, "movll16.src-r0l-dst16-An-direct-QI", "movll", 16,
25371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25373 /* movll [$Dst16An],r0l */
25375 M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movll16.src-r0l-dst16-An-indirect-QI", "movll", 16,
25376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25378 /* movll ${Dsp-16-u8}[$Dst16An],r0l */
25380 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-An-relative-QI", "movll", 24,
25381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25383 /* movll ${Dsp-16-u16}[$Dst16An],r0l */
25385 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-An-relative-QI", "movll", 32,
25386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25388 /* movll ${Dsp-16-u8}[sb],r0l */
25390 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-SB-relative-QI", "movll", 24,
25391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25393 /* movll ${Dsp-16-u16}[sb],r0l */
25395 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-SB-relative-QI", "movll", 32,
25396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25398 /* movll ${Dsp-16-s8}[fb],r0l */
25400 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-FB-relative-QI", "movll", 24,
25401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25403 /* movll ${Dsp-16-u16},r0l */
25405 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movll16.src-r0l-dst16-16-16-absolute-QI", "movll", 32,
25406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25408 /* movhh r0l,$Dst16RnQI */
25410 M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, "movhh16.r0l-dst-dst16-Rn-direct-QI", "movhh", 16,
25411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25413 /* movhh r0l,$Dst16AnQI */
25415 M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, "movhh16.r0l-dst-dst16-An-direct-QI", "movhh", 16,
25416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25418 /* movhh r0l,[$Dst16An] */
25420 M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, "movhh16.r0l-dst-dst16-An-indirect-QI", "movhh", 16,
25421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25423 /* movhh r0l,${Dsp-16-u8}[$Dst16An] */
25425 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-An-relative-QI", "movhh", 24,
25426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25428 /* movhh r0l,${Dsp-16-u16}[$Dst16An] */
25430 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-An-relative-QI", "movhh", 32,
25431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25433 /* movhh r0l,${Dsp-16-u8}[sb] */
25435 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-SB-relative-QI", "movhh", 24,
25436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25438 /* movhh r0l,${Dsp-16-u16}[sb] */
25440 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-SB-relative-QI", "movhh", 32,
25441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25443 /* movhh r0l,${Dsp-16-s8}[fb] */
25445 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-FB-relative-QI", "movhh", 24,
25446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25448 /* movhh r0l,${Dsp-16-u16} */
25450 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhh16.r0l-dst-dst16-16-16-absolute-QI", "movhh", 32,
25451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25453 /* movhl r0l,$Dst16RnQI */
25455 M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, "movhl16.r0l-dst-dst16-Rn-direct-QI", "movhl", 16,
25456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25458 /* movhl r0l,$Dst16AnQI */
25460 M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, "movhl16.r0l-dst-dst16-An-direct-QI", "movhl", 16,
25461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25463 /* movhl r0l,[$Dst16An] */
25465 M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, "movhl16.r0l-dst-dst16-An-indirect-QI", "movhl", 16,
25466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25468 /* movhl r0l,${Dsp-16-u8}[$Dst16An] */
25470 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-An-relative-QI", "movhl", 24,
25471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25473 /* movhl r0l,${Dsp-16-u16}[$Dst16An] */
25475 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-An-relative-QI", "movhl", 32,
25476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25478 /* movhl r0l,${Dsp-16-u8}[sb] */
25480 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-SB-relative-QI", "movhl", 24,
25481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25483 /* movhl r0l,${Dsp-16-u16}[sb] */
25485 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-SB-relative-QI", "movhl", 32,
25486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25488 /* movhl r0l,${Dsp-16-s8}[fb] */
25490 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-FB-relative-QI", "movhl", 24,
25491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25493 /* movhl r0l,${Dsp-16-u16} */
25495 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhl16.r0l-dst-dst16-16-16-absolute-QI", "movhl", 32,
25496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25498 /* movlh r0l,$Dst16RnQI */
25500 M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, "movlh16.r0l-dst-dst16-Rn-direct-QI", "movlh", 16,
25501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25503 /* movlh r0l,$Dst16AnQI */
25505 M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, "movlh16.r0l-dst-dst16-An-direct-QI", "movlh", 16,
25506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25508 /* movlh r0l,[$Dst16An] */
25510 M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, "movlh16.r0l-dst-dst16-An-indirect-QI", "movlh", 16,
25511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25513 /* movlh r0l,${Dsp-16-u8}[$Dst16An] */
25515 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-An-relative-QI", "movlh", 24,
25516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25518 /* movlh r0l,${Dsp-16-u16}[$Dst16An] */
25520 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-An-relative-QI", "movlh", 32,
25521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25523 /* movlh r0l,${Dsp-16-u8}[sb] */
25525 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-SB-relative-QI", "movlh", 24,
25526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25528 /* movlh r0l,${Dsp-16-u16}[sb] */
25530 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-SB-relative-QI", "movlh", 32,
25531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25533 /* movlh r0l,${Dsp-16-s8}[fb] */
25535 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-FB-relative-QI", "movlh", 24,
25536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25538 /* movlh r0l,${Dsp-16-u16} */
25540 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movlh16.r0l-dst-dst16-16-16-absolute-QI", "movlh", 32,
25541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25543 /* movll r0l,$Dst16RnQI */
25545 M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, "movll16.r0l-dst-dst16-Rn-direct-QI", "movll", 16,
25546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25548 /* movll r0l,$Dst16AnQI */
25550 M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, "movll16.r0l-dst-dst16-An-direct-QI", "movll", 16,
25551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25553 /* movll r0l,[$Dst16An] */
25555 M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, "movll16.r0l-dst-dst16-An-indirect-QI", "movll", 16,
25556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25558 /* movll r0l,${Dsp-16-u8}[$Dst16An] */
25560 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-An-relative-QI", "movll", 24,
25561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25563 /* movll r0l,${Dsp-16-u16}[$Dst16An] */
25565 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-An-relative-QI", "movll", 32,
25566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25568 /* movll r0l,${Dsp-16-u8}[sb] */
25570 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-SB-relative-QI", "movll", 24,
25571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25573 /* movll r0l,${Dsp-16-u16}[sb] */
25575 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-SB-relative-QI", "movll", 32,
25576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25578 /* movll r0l,${Dsp-16-s8}[fb] */
25580 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-FB-relative-QI", "movll", 24,
25581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25583 /* movll r0l,${Dsp-16-u16} */
25585 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movll16.r0l-dst-dst16-16-16-absolute-QI", "movll", 32,
25586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25588 /* mova [$Dst32AnUnprefixed],a1 */
25590 M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25593 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
25595 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25598 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
25600 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25603 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
25605 M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25608 /* mova ${Dsp-16-u8}[sb],a1 */
25610 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25613 /* mova ${Dsp-16-u16}[sb],a1 */
25615 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25618 /* mova ${Dsp-16-s8}[fb],a1 */
25620 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25623 /* mova ${Dsp-16-s16}[fb],a1 */
25625 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25628 /* mova ${Dsp-16-u16},a1 */
25630 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25633 /* mova ${Dsp-16-u24},a1 */
25635 M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25638 /* mova [$Dst32AnUnprefixed],a0 */
25640 M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25643 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
25645 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25648 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
25650 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25653 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
25655 M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25658 /* mova ${Dsp-16-u8}[sb],a0 */
25660 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25663 /* mova ${Dsp-16-u16}[sb],a0 */
25665 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25668 /* mova ${Dsp-16-s8}[fb],a0 */
25670 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25673 /* mova ${Dsp-16-s16}[fb],a0 */
25675 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25678 /* mova ${Dsp-16-u16},a0 */
25680 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25683 /* mova ${Dsp-16-u24},a0 */
25685 M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25688 /* mova [$Dst32AnUnprefixed],r3r1 */
25690 M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25693 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
25695 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25698 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
25700 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25703 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
25705 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25708 /* mova ${Dsp-16-u8}[sb],r3r1 */
25710 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25713 /* mova ${Dsp-16-u16}[sb],r3r1 */
25715 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25718 /* mova ${Dsp-16-s8}[fb],r3r1 */
25720 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25723 /* mova ${Dsp-16-s16}[fb],r3r1 */
25725 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25728 /* mova ${Dsp-16-u16},r3r1 */
25730 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25733 /* mova ${Dsp-16-u24},r3r1 */
25735 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25738 /* mova [$Dst32AnUnprefixed],r2r0 */
25740 M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25743 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
25745 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25748 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
25750 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25753 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
25755 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25758 /* mova ${Dsp-16-u8}[sb],r2r0 */
25760 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25763 /* mova ${Dsp-16-u16}[sb],r2r0 */
25765 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25768 /* mova ${Dsp-16-s8}[fb],r2r0 */
25770 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25773 /* mova ${Dsp-16-s16}[fb],r2r0 */
25775 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25778 /* mova ${Dsp-16-u16},r2r0 */
25780 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25783 /* mova ${Dsp-16-u24},r2r0 */
25785 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
25788 /* mova [$Dst16An],a1 */
25790 M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a1-dst16-An-indirect-Mova-HI", "mova", 16,
25791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25793 /* mova ${Dsp-16-u8}[$Dst16An],a1 */
25795 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25798 /* mova ${Dsp-16-u16}[$Dst16An],a1 */
25800 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25803 /* mova ${Dsp-16-u8}[sb],a1 */
25805 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25808 /* mova ${Dsp-16-u16}[sb],a1 */
25810 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25813 /* mova ${Dsp-16-s8}[fb],a1 */
25815 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25818 /* mova ${Dsp-16-u16},a1 */
25820 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a1-dst16-16-16-absolute-Mova-HI", "mova", 32,
25821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25823 /* mova [$Dst16An],a0 */
25825 M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a0-dst16-An-indirect-Mova-HI", "mova", 16,
25826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25828 /* mova ${Dsp-16-u8}[$Dst16An],a0 */
25830 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25833 /* mova ${Dsp-16-u16}[$Dst16An],a0 */
25835 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25838 /* mova ${Dsp-16-u8}[sb],a0 */
25840 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25843 /* mova ${Dsp-16-u16}[sb],a0 */
25845 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25848 /* mova ${Dsp-16-s8}[fb],a0 */
25850 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25853 /* mova ${Dsp-16-u16},a0 */
25855 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a0-dst16-16-16-absolute-Mova-HI", "mova", 32,
25856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25858 /* mova [$Dst16An],r3 */
25860 M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r3-dst16-An-indirect-Mova-HI", "mova", 16,
25861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25863 /* mova ${Dsp-16-u8}[$Dst16An],r3 */
25865 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25868 /* mova ${Dsp-16-u16}[$Dst16An],r3 */
25870 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25873 /* mova ${Dsp-16-u8}[sb],r3 */
25875 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25878 /* mova ${Dsp-16-u16}[sb],r3 */
25880 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25883 /* mova ${Dsp-16-s8}[fb],r3 */
25885 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25888 /* mova ${Dsp-16-u16},r3 */
25890 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r3-dst16-16-16-absolute-Mova-HI", "mova", 32,
25891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25893 /* mova [$Dst16An],r2 */
25895 M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r2-dst16-An-indirect-Mova-HI", "mova", 16,
25896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25898 /* mova ${Dsp-16-u8}[$Dst16An],r2 */
25900 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25903 /* mova ${Dsp-16-u16}[$Dst16An],r2 */
25905 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25908 /* mova ${Dsp-16-u8}[sb],r2 */
25910 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25913 /* mova ${Dsp-16-u16}[sb],r2 */
25915 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25918 /* mova ${Dsp-16-s8}[fb],r2 */
25920 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25923 /* mova ${Dsp-16-u16},r2 */
25925 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r2-dst16-16-16-absolute-Mova-HI", "mova", 32,
25926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25928 /* mova [$Dst16An],r1 */
25930 M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r1-dst16-An-indirect-Mova-HI", "mova", 16,
25931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25933 /* mova ${Dsp-16-u8}[$Dst16An],r1 */
25935 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25938 /* mova ${Dsp-16-u16}[$Dst16An],r1 */
25940 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25943 /* mova ${Dsp-16-u8}[sb],r1 */
25945 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25948 /* mova ${Dsp-16-u16}[sb],r1 */
25950 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25953 /* mova ${Dsp-16-s8}[fb],r1 */
25955 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25958 /* mova ${Dsp-16-u16},r1 */
25960 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r1-dst16-16-16-absolute-Mova-HI", "mova", 32,
25961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25963 /* mova [$Dst16An],r0 */
25965 M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r0-dst16-An-indirect-Mova-HI", "mova", 16,
25966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25968 /* mova ${Dsp-16-u8}[$Dst16An],r0 */
25970 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25973 /* mova ${Dsp-16-u16}[$Dst16An],r0 */
25975 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25978 /* mova ${Dsp-16-u8}[sb],r0 */
25980 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25983 /* mova ${Dsp-16-u16}[sb],r0 */
25985 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25988 /* mova ${Dsp-16-s8}[fb],r0 */
25990 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25993 /* mova ${Dsp-16-u16},r0 */
25995 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r0-dst16-16-16-absolute-Mova-HI", "mova", 32,
25996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
25998 /* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
26000 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
26001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26003 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
26005 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
26006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26008 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
26010 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
26011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26013 /* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
26015 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
26016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26018 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
26020 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
26021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26023 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
26025 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
26026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26028 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
26030 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
26031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26033 /* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
26035 M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
26036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26038 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
26040 M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
26041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26043 /* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */
26045 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
26046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26048 /* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */
26050 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
26051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26053 /* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
26055 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
26056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26058 /* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
26060 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
26061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26063 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
26065 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
26066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26068 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
26070 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
26071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26073 /* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
26075 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
26076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26078 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
26080 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
26081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26083 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
26085 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
26086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26088 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
26090 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
26091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26093 /* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
26095 M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
26096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26098 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
26100 M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
26101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26103 /* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */
26105 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
26106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26108 /* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */
26110 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
26111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26113 /* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
26115 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
26116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26118 /* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
26120 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
26121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26123 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
26125 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
26126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26128 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
26130 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
26131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26133 /* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
26135 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
26136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26138 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
26140 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
26141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26143 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
26145 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
26146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26148 /* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */
26150 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "mov.w", 24,
26151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26153 /* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */
26155 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-direct-HI", "mov.w", 24,
26156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26158 /* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */
26160 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-indirect-HI", "mov.w", 24,
26161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26163 /* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
26165 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
26166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26168 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
26170 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
26171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26173 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
26175 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
26176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26178 /* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
26180 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
26181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26183 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
26185 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
26186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26188 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
26190 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
26191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26193 /* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */
26195 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "mov.b", 24,
26196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26198 /* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */
26200 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-direct-QI", "mov.b", 24,
26201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26203 /* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */
26205 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-indirect-QI", "mov.b", 24,
26206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26208 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26210 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
26211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26213 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
26215 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
26216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26218 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
26220 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
26221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26223 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26225 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
26226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26228 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
26230 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
26231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26233 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
26235 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
26236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26238 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
26240 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
26241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26243 /* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26245 M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
26246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26248 /* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
26250 M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
26251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26253 /* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */
26255 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
26256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26258 /* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */
26260 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
26261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26263 /* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
26265 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
26266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26268 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26270 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
26271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26273 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
26275 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
26276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26278 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
26280 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
26281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26283 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26285 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
26286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26288 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
26290 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
26291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26293 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
26295 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
26296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26298 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
26300 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
26301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26303 /* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26305 M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
26306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26308 /* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
26310 M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
26311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26313 /* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */
26315 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
26316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26318 /* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */
26320 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
26321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26323 /* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
26325 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
26326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26328 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
26330 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
26331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26333 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
26335 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
26336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26338 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
26340 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
26341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26343 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
26345 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
26346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26348 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
26350 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
26351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26353 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
26355 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
26356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26358 /* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */
26360 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-Rn-direct-HI", "mov.w", 24,
26361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26363 /* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */
26365 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-direct-HI", "mov.w", 24,
26366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26368 /* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */
26370 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-indirect-HI", "mov.w", 24,
26371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26373 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
26375 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
26376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26378 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
26380 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
26381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26383 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
26385 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
26386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26388 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
26390 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
26391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26393 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
26395 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
26396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26398 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
26400 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
26401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26403 /* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */
26405 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-Rn-direct-QI", "mov.b", 24,
26406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26408 /* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */
26410 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-direct-QI", "mov.b", 24,
26411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26413 /* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */
26415 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-indirect-QI", "mov.b", 24,
26416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26418 /* mov.l${S} ${Dsp-8-u8}[sb],a1 */
26420 M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
26421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26423 /* mov.l${S} ${Dsp-8-s8}[fb],a1 */
26425 M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
26426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26428 /* mov.l${S} ${Dsp-8-u8}[sb],a0 */
26430 M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
26431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26433 /* mov.l${S} ${Dsp-8-s8}[fb],a0 */
26435 M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
26436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26438 /* mov.l${S} ${Dsp-8-u16},a1 */
26440 M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a1-dst32-2-S-16-absolute-SI", "mov.l", 24,
26441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26443 /* mov.l${S} ${Dsp-8-u16},a0 */
26445 M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a0-dst32-2-S-16-absolute-SI", "mov.l", 24,
26446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26448 /* mov.w${S} r0,${Dsp-8-u8}[sb] */
26450 M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26453 /* mov.w${S} r0,${Dsp-8-s8}[fb] */
26455 M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26458 /* mov.b${S} r0l,${Dsp-8-u8}[sb] */
26460 M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26463 /* mov.b${S} r0l,${Dsp-8-s8}[fb] */
26465 M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26468 /* mov.w${S} r0,${Dsp-8-u16} */
26470 M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-r0-dst32-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
26471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26473 /* mov.b${S} r0l,${Dsp-8-u16} */
26475 M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-r0l-dst32-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
26476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26478 /* mov.w${S} ${Dsp-8-u8}[sb],r1 */
26480 M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26483 /* mov.w${S} ${Dsp-8-s8}[fb],r1 */
26485 M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26488 /* mov.b${S} ${Dsp-8-u8}[sb],r1l */
26490 M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26493 /* mov.b${S} ${Dsp-8-s8}[fb],r1l */
26495 M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26498 /* mov.w${S} ${Dsp-8-u16},r1 */
26500 M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r1-dst32-2-S-16-absolute-HI", "mov.w", 24,
26501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26503 /* mov.b${S} ${Dsp-8-u16},r1l */
26505 M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r1l-dst32-2-S-16-absolute-QI", "mov.b", 24,
26506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26508 /* mov.w${S} r0,r1 */
26510 M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1-dst32-2-S-R0-direct-HI", "mov.w", 8,
26511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26513 /* mov.b${S} r0l,r1l */
26515 M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, "mov32.b-dst32-2-S-basic-r1l-dst32-2-S-R0l-direct-QI", "mov.b", 8,
26516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26518 /* mov.w${S} ${Dsp-8-u8}[sb],r0 */
26520 M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26523 /* mov.w${S} ${Dsp-8-s8}[fb],r0 */
26525 M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26528 /* mov.b${S} ${Dsp-8-u8}[sb],r0l */
26530 M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26533 /* mov.b${S} ${Dsp-8-s8}[fb],r0l */
26535 M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26538 /* mov.w${S} ${Dsp-8-u16},r0 */
26540 M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r0-dst32-2-S-16-absolute-HI", "mov.w", 24,
26541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26543 /* mov.b${S} ${Dsp-8-u16},r0l */
26545 M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r0l-dst32-2-S-16-absolute-QI", "mov.b", 24,
26546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26548 /* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
26550 M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "mov16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "mov.b", 8,
26551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26553 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
26555 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-SB-relative-QI", "mov.b", 16,
26556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26558 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
26560 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-FB-relative-QI", "mov.b", 16,
26561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26563 /* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
26565 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-src2-src16-2-S-16-absolute-QI", "mov.b", 24,
26566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26568 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
26570 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
26571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26573 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
26575 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
26576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26578 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
26580 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-Rn-An-src16-2-S-16-absolute-QI", "mov.b", 24,
26581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
26583 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26585 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26588 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
26590 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26593 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
26595 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26598 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26600 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26603 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
26605 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26608 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
26610 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26613 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26615 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26618 /* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
26620 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26623 /* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
26625 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26628 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26630 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26633 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26635 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26638 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26640 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26643 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26645 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26648 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26650 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26653 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26655 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26658 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26660 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26663 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26665 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26668 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26670 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26673 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
26675 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26678 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
26680 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26683 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
26685 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26688 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
26690 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26693 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
26695 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26698 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
26700 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26703 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
26705 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26708 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
26710 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26713 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
26715 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26718 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
26720 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26723 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
26725 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26728 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
26730 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26733 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
26735 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26738 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
26740 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26743 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
26745 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26748 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
26750 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26753 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
26755 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26758 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
26760 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26763 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26765 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26768 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
26770 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26773 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
26775 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26778 /* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
26780 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26783 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26785 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26788 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
26790 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26793 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
26795 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26798 /* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
26800 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26803 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26805 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26808 /* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
26810 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26813 /* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
26815 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26818 /* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
26820 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26823 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26825 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26828 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26830 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26833 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26835 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26838 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
26840 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26843 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26845 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26848 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26850 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26853 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26855 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26858 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
26860 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26863 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26865 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26868 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26870 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26873 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26875 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26878 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
26880 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26883 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
26885 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26888 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26890 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26893 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
26895 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26898 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26900 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26903 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
26905 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26908 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26910 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26913 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
26915 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26918 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26920 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26923 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
26925 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26928 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26930 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26933 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
26935 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26938 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26940 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26943 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
26945 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26948 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
26950 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26953 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
26955 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26958 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
26960 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26963 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
26965 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26968 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26970 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26973 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
26975 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26978 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
26980 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26983 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
26985 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26988 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
26990 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26993 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
26995 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
26998 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
27000 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
27001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27003 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
27005 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
27006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27008 /* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
27010 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
27011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27013 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
27015 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
27016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27018 /* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
27020 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
27021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27023 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27025 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
27026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27028 /* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
27030 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
27031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27033 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
27035 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
27036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27038 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
27040 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
27041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27043 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
27045 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
27046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27048 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27050 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
27051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27053 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27055 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
27056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27058 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27060 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
27061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27063 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27065 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
27066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27068 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27070 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
27071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27073 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27075 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
27076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27078 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27080 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
27081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27083 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27085 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
27086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27088 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27090 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
27091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27093 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27095 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
27096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27098 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27100 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
27101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27103 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27105 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
27106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27108 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
27110 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
27111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27113 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27115 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
27116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27118 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
27120 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
27121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27123 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
27125 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27128 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
27130 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27133 /* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
27135 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27138 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
27140 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27143 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
27145 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27148 /* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
27150 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27153 /* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
27155 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27158 /* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
27160 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27163 /* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27165 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27168 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27170 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27173 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27175 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27178 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27180 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27183 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27185 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27188 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27190 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27193 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27195 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27198 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27200 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27203 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27205 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27208 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27210 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27213 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
27215 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27218 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
27220 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27223 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27225 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27228 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
27230 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27233 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
27235 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27238 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27240 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27243 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
27245 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27248 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
27250 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27253 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
27255 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27258 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
27260 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27263 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
27265 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27268 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
27270 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27273 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
27275 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27278 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
27280 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27283 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
27285 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27288 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
27290 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27293 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
27295 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27298 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
27300 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27303 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
27305 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
27306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
27308 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
27310 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
27311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
27313 /* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
27315 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-An-src16-2-S-16-absolute-QI", "mov.b", 24,
27316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
27318 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27320 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27323 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
27325 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27328 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
27330 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27333 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27335 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27338 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
27340 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27343 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
27345 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27348 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27350 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27353 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
27355 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27358 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
27360 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27363 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27365 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27368 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27370 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27373 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27375 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27378 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27380 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27383 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27385 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27388 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27390 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27393 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27395 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27398 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27400 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27403 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27405 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27408 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
27410 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27413 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
27415 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27418 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
27420 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27423 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
27425 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27428 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
27430 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27433 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
27435 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27438 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
27440 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27443 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
27445 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27448 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
27450 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27453 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
27455 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27458 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
27460 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27463 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
27465 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27468 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
27470 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27473 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
27475 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27478 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
27480 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27483 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
27485 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27488 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
27490 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27493 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
27495 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27498 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27500 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27503 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
27505 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27508 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
27510 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27513 /* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
27515 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27518 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27520 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27523 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
27525 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27528 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
27530 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27533 /* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
27535 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27538 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27540 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27543 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
27545 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27548 /* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
27550 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27553 /* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
27555 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27558 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27560 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27563 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27565 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27568 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27570 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27573 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
27575 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27578 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27580 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27583 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27585 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27588 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27590 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27593 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
27595 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27598 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27600 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27603 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27605 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27608 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27610 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27613 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
27615 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27618 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
27620 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27623 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
27625 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27628 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
27630 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27633 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
27635 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27638 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
27640 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27643 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
27645 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27648 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
27650 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27653 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
27655 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27658 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
27660 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27663 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
27665 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27668 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
27670 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27673 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
27675 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27678 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
27680 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27683 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
27685 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27688 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
27690 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27693 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
27695 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27698 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
27700 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27703 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
27705 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27708 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
27710 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27713 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
27715 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27718 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
27720 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27723 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
27725 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27728 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
27730 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27733 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
27735 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27738 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27740 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
27741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27743 /* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
27745 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
27746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27748 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27750 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
27751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27753 /* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
27755 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
27756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27758 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27760 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
27761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27763 /* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
27765 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
27766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27768 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
27770 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
27771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27773 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
27775 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
27776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27778 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
27780 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
27781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27783 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27785 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
27786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27788 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27790 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
27791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27793 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27795 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
27796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27798 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27800 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
27801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27803 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27805 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
27806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27808 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27810 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
27811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27813 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27815 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
27816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27818 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27820 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
27821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27823 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27825 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
27826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27828 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27830 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
27831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27833 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27835 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
27836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27838 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27840 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
27841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27843 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
27845 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
27846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27848 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27850 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
27851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27853 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
27855 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
27856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27858 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
27860 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27863 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
27865 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27868 /* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27870 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27873 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
27875 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27878 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
27880 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27883 /* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27885 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27888 /* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
27890 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27893 /* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
27895 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27898 /* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27900 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27903 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27905 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27908 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27910 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27913 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27915 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27918 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27920 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27923 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27925 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27928 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27930 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27933 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27935 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27938 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27940 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27943 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27945 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27948 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
27950 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27953 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
27955 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27958 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27960 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27963 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
27965 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27968 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
27970 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27973 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27975 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27978 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
27980 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27983 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
27985 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27988 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
27990 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27993 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
27995 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
27998 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
28000 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
28001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28003 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
28005 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
28006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28008 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
28010 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
28011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28013 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
28015 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
28016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28018 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
28020 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
28021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28023 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
28025 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
28026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28028 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
28030 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
28031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28033 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28035 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
28036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28038 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28040 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28043 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
28045 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28048 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
28050 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28053 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28055 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28058 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
28060 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28063 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
28065 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28068 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28070 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28073 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
28075 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28078 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
28080 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28083 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28085 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28088 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28090 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28093 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28095 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28098 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28100 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28103 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28105 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28108 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28110 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28113 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28115 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28118 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28120 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28123 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28125 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28128 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
28130 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28133 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28135 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28138 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28140 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28143 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
28145 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28148 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28150 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28153 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28155 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28158 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
28160 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28163 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28165 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28168 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28170 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28173 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
28175 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28178 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
28180 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28183 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
28185 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28188 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
28190 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28193 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28195 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28198 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28200 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28203 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
28205 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28208 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
28210 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28213 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
28215 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28218 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28220 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28223 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
28225 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28228 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
28230 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28233 /* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
28235 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28238 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28240 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28243 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
28245 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28248 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
28250 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28253 /* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
28255 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28258 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28260 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28263 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
28265 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28268 /* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
28270 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28273 /* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
28275 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28278 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28280 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28283 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28285 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28288 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28290 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28293 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
28295 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28298 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28300 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28303 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28305 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28308 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28310 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28313 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
28315 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28318 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28320 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28323 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28325 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28328 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28330 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28333 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
28335 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28338 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
28340 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28343 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28345 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28348 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
28350 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28353 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28355 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28358 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
28360 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28363 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28365 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28368 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
28370 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28373 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28375 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28378 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
28380 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28383 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28385 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28388 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
28390 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28393 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28395 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28398 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
28400 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28403 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
28405 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28408 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
28410 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28413 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
28415 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28418 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
28420 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28423 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28425 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28428 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
28430 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28433 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
28435 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28438 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
28440 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28443 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
28445 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28448 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
28450 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28453 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
28455 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28458 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28460 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
28461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28463 /* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
28465 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
28466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28468 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28470 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
28471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28473 /* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
28475 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
28476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28478 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28480 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
28481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28483 /* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
28485 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
28486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28488 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
28490 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
28491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28493 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
28495 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
28496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28498 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
28500 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
28501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28503 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
28505 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
28506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28508 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
28510 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
28511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28513 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
28515 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
28516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28518 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
28520 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
28521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28523 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
28525 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
28526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28528 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
28530 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
28531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28533 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
28535 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
28536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28538 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
28540 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
28541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28543 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
28545 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
28546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28548 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
28550 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
28551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28553 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
28555 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
28556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28558 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
28560 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
28561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28563 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
28565 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
28566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28568 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
28570 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
28571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28573 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
28575 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
28576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28578 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
28580 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28583 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
28585 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28588 /* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28590 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28593 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
28595 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28598 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
28600 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28603 /* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28605 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28608 /* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
28610 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28613 /* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
28615 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28618 /* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28620 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28623 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28625 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28628 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28630 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28633 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
28635 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28638 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28640 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28643 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28645 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28648 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
28650 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28653 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28655 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28658 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28660 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28663 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
28665 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28668 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
28670 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28673 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
28675 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28678 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
28680 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28683 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
28685 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28688 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
28690 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28693 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
28695 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28698 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
28700 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28703 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
28705 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28708 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
28710 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28713 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
28715 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28718 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
28720 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28723 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
28725 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28728 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
28730 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28733 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
28735 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28738 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
28740 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28743 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
28745 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28748 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
28750 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28753 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28755 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
28758 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
28760 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28763 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
28765 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28768 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
28770 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28773 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
28775 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28778 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
28780 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28783 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
28785 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28788 /* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
28790 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28793 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
28795 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28798 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
28800 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28803 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
28805 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28808 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
28810 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28813 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
28815 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28818 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
28820 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28823 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
28825 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28828 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
28830 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28833 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
28835 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28838 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28840 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28843 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28845 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28848 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
28850 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28853 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28855 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28858 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28860 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28863 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
28865 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28868 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28870 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28873 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28875 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28878 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
28880 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28883 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28885 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28888 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28890 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28893 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
28895 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
28896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28898 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
28900 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
28901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28903 /* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
28905 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mov.w", 32,
28906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28908 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
28910 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mov.w", 32,
28911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28913 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
28915 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mov.w", 32,
28916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28918 /* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
28920 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mov.w", 32,
28921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28923 /* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
28925 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
28926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28928 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
28930 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
28931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28933 /* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
28935 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mov.w", 32,
28936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28938 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
28940 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28943 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
28945 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28948 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
28950 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28953 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
28955 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28958 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
28960 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28963 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
28965 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28968 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
28970 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28973 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28975 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28978 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28980 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28983 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
28985 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28988 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28990 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28993 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28995 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
28998 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
29000 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
29001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29003 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29005 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
29006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29008 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29010 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
29011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29013 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
29015 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
29016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29018 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29020 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
29021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29023 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
29025 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mov.w", 48,
29026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29028 /* mov.w${G} $Src16RnHI,$Dst16RnHI */
29030 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
29031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29033 /* mov.w${G} $Src16AnHI,$Dst16RnHI */
29035 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
29036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29038 /* mov.w${G} [$Src16An],$Dst16RnHI */
29040 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mov.w", 16,
29041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29043 /* mov.w${G} $Src16RnHI,$Dst16AnHI */
29045 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mov.w", 16,
29046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29048 /* mov.w${G} $Src16AnHI,$Dst16AnHI */
29050 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mov.w", 16,
29051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29053 /* mov.w${G} [$Src16An],$Dst16AnHI */
29055 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mov.w", 16,
29056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29058 /* mov.w${G} $Src16RnHI,[$Dst16An] */
29060 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
29061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29063 /* mov.w${G} $Src16AnHI,[$Dst16An] */
29065 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
29066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29068 /* mov.w${G} [$Src16An],[$Dst16An] */
29070 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mov.w", 16,
29071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29073 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
29075 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29078 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
29080 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29083 /* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29085 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29088 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
29090 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29093 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
29095 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29098 /* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29100 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29103 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
29105 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29108 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
29110 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29113 /* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
29115 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29118 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
29120 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29123 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
29125 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29128 /* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
29130 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29133 /* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
29135 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29138 /* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
29140 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29143 /* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
29145 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29148 /* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
29150 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29153 /* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
29155 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29158 /* mov.w${G} [$Src16An],${Dsp-16-u16} */
29160 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29163 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
29165 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29168 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
29170 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29173 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
29175 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29178 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
29180 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29183 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
29185 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29188 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
29190 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29193 /* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
29195 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29198 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
29200 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29203 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
29205 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29208 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
29210 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29213 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
29215 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29218 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
29220 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29223 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
29225 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29228 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
29230 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29233 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
29235 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29238 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
29240 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29243 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
29245 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29248 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
29250 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29253 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
29255 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29258 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
29260 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29263 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
29265 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29268 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
29270 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29273 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
29275 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29278 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
29280 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29283 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
29285 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29288 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
29290 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29293 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
29295 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29298 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
29300 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
29301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29303 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
29305 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
29306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29308 /* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
29310 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mov.b", 32,
29311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29313 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
29315 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mov.b", 32,
29316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29318 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
29320 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mov.b", 32,
29321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29323 /* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
29325 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mov.b", 32,
29326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29328 /* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
29330 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
29331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29333 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
29335 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
29336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29338 /* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
29340 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mov.b", 32,
29341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29343 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
29345 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29348 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
29350 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29353 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
29355 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29358 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
29360 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29363 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
29365 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29368 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
29370 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29373 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
29375 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29378 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
29380 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29383 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
29385 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29388 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
29390 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29393 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
29395 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29398 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
29400 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29403 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
29405 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29408 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29410 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29413 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29415 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29418 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
29420 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29423 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29425 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29428 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
29430 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29433 /* mov.b${G} $Src16RnQI,$Dst16RnQI */
29435 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
29436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29438 /* mov.b${G} $Src16AnQI,$Dst16RnQI */
29440 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
29441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29443 /* mov.b${G} [$Src16An],$Dst16RnQI */
29445 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mov.b", 16,
29446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29448 /* mov.b${G} $Src16RnQI,$Dst16AnQI */
29450 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mov.b", 16,
29451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29453 /* mov.b${G} $Src16AnQI,$Dst16AnQI */
29455 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mov.b", 16,
29456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29458 /* mov.b${G} [$Src16An],$Dst16AnQI */
29460 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mov.b", 16,
29461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29463 /* mov.b${G} $Src16RnQI,[$Dst16An] */
29465 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
29466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29468 /* mov.b${G} $Src16AnQI,[$Dst16An] */
29470 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
29471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29473 /* mov.b${G} [$Src16An],[$Dst16An] */
29475 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mov.b", 16,
29476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29478 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
29480 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29483 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
29485 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29488 /* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29490 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29493 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
29495 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29498 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
29500 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29503 /* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29505 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29508 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
29510 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29513 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
29515 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29518 /* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
29520 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29523 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
29525 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29528 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
29530 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29533 /* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
29535 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29538 /* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
29540 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29543 /* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
29545 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29548 /* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
29550 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29553 /* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
29555 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29558 /* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
29560 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29563 /* mov.b${G} [$Src16An],${Dsp-16-u16} */
29565 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29568 /* mov.w${Z} #0,${Dsp-8-u8}[sb] */
29570 M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
29571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29573 /* mov.w${Z} #0,${Dsp-8-s8}[fb] */
29575 M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
29576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29578 /* mov.w${Z} #0,${Dsp-8-u16} */
29580 M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-Z-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
29581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29583 /* mov.w${Z} #0,r0 */
29585 M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-Z-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 8,
29586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29588 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29590 M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
29591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29593 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29595 M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
29596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29598 /* mov.b${Z} #0,${Dsp-8-u16} */
29600 M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-Z-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
29601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29603 /* mov.b${Z} #0,r0l */
29605 M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-Z-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 8,
29606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29608 /* mov.b${Z} #0,r0l */
29610 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 8,
29611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29613 /* mov.b${Z} #0,r0h */
29615 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 8,
29616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29618 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29620 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-SB-relative-QI", "mov.b", 16,
29621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29623 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29625 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-FB-relative-QI", "mov.b", 16,
29626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29628 /* mov.b${Z} #0,${Dsp-8-u16} */
29630 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24,
29631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29633 /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
29635 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
29636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29638 /* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
29640 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
29641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29643 /* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29645 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
29646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29648 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29650 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
29651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29653 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29655 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
29656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29658 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29660 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
29661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29663 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29665 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
29666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29668 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29670 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
29671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29673 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29675 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
29676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29678 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29680 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
29681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29683 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
29685 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
29686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29688 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
29690 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
29691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29693 /* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
29695 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
29696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29698 /* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
29700 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
29701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29703 /* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29705 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
29706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29708 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29710 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
29711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29713 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29715 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
29716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29718 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29720 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
29721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29723 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29725 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
29726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29728 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29730 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
29731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29733 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29735 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
29736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29738 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29740 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
29741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29743 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
29745 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
29746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29748 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
29750 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
29751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29753 /* mov.w${Q} #${Imm-8-s4},$Dst16RnHI */
29755 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "mov16.w-imm4-Q-16-dst16-Rn-direct-HI", "mov.w", 16,
29756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29758 /* mov.w${Q} #${Imm-8-s4},$Dst16AnHI */
29760 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "mov16.w-imm4-Q-16-dst16-An-direct-HI", "mov.w", 16,
29761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29763 /* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
29765 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "mov16.w-imm4-Q-16-dst16-An-indirect-HI", "mov.w", 16,
29766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29768 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29770 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "mov.w", 24,
29771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29773 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29775 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "mov.w", 32,
29776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29778 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29780 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "mov.w", 24,
29781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29783 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29785 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "mov.w", 32,
29786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29788 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29790 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "mov.w", 24,
29791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29793 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
29795 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm4-Q-16-dst16-16-16-absolute-HI", "mov.w", 32,
29796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29798 /* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
29800 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-Rn-direct-QI", "mov.b", 16,
29801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29803 /* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
29805 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-direct-QI", "mov.b", 16,
29806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29808 /* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
29810 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-indirect-QI", "mov.b", 16,
29811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29813 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29815 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.b", 24,
29816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29818 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29820 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.b", 32,
29821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29823 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29825 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.b", 24,
29826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29828 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29830 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.b", 32,
29831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29833 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29835 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.b", 24,
29836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29838 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
29840 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32,
29841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29843 /* mov.b${S} #${Imm-8-QI},r0l */
29845 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16,
29846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29848 /* mov.b${S} #${Imm-8-QI},r0h */
29850 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16,
29851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29853 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
29855 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24,
29856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29858 /* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
29860 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24,
29861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29863 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
29865 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32,
29866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
29868 /* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
29870 M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32,
29871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29873 /* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
29875 M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32,
29876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29878 /* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
29880 M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40,
29881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29883 /* mov.w${S} #${Imm-8-HI},r0 */
29885 M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24,
29886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29888 /* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
29890 M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24,
29891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29893 /* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
29895 M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24,
29896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29898 /* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
29900 M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32,
29901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29903 /* mov.b${S} #${Imm-8-QI},r0l */
29905 M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16,
29906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29908 /* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
29910 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48,
29911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29913 /* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
29915 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "mov.l", 48,
29916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29918 /* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
29920 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "mov.l", 48,
29921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29923 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29925 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 56,
29926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29928 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
29930 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 56,
29931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29933 /* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
29935 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 56,
29936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29938 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29940 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 64,
29941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29943 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
29945 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 64,
29946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29948 /* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
29950 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 64,
29951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29953 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
29955 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 64,
29956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29958 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29960 M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 72,
29961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29963 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
29965 M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 72,
29966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29968 /* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
29970 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
29971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29973 /* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
29975 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
29976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29978 /* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
29980 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
29981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29983 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29985 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 40,
29986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29988 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
29990 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 40,
29991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29993 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
29995 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 40,
29996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
29998 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
30000 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 48,
30001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30003 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
30005 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 48,
30006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30008 /* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
30010 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 48,
30011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30013 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
30015 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 48,
30016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30018 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30020 M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 56,
30021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30023 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
30025 M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 56,
30026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30028 /* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
30030 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
30031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30033 /* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
30035 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
30036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30038 /* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
30040 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
30041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30043 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
30045 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
30046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30048 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30050 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
30051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30053 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30055 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
30056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30058 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
30060 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
30061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30063 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30065 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
30066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30068 /* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
30070 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
30071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30073 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30075 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
30076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30078 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30080 M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
30081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30083 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
30085 M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
30086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30088 /* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
30090 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-Rn-direct-HI", "mov.w", 32,
30091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30093 /* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
30095 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-An-direct-HI", "mov.w", 32,
30096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30098 /* mov.w${G} #${Imm-16-HI},[$Dst16An] */
30100 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-imm-G-basic-dst16-An-indirect-HI", "mov.w", 32,
30101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30103 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
30105 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mov.w", 40,
30106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30108 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
30110 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mov.w", 40,
30111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30113 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
30115 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mov.w", 40,
30116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30118 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
30120 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mov.w", 48,
30121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30123 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
30125 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mov.w", 48,
30126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30128 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
30130 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mov.w", 48,
30131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30133 /* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
30135 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-Rn-direct-QI", "mov.b", 24,
30136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30138 /* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
30140 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-An-direct-QI", "mov.b", 24,
30141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30143 /* mov.b${G} #${Imm-16-QI},[$Dst16An] */
30145 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-imm-G-basic-dst16-An-indirect-QI", "mov.b", 24,
30146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30148 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
30150 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
30151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30153 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30155 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
30156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30158 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30160 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
30161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30163 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
30165 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
30166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30168 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30170 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
30171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30173 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30175 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
30176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
30178 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30180 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30183 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
30185 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30188 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
30190 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30193 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30195 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30198 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
30200 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30203 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
30205 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30208 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30210 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30213 /* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30215 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30218 /* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30220 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30223 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30225 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30228 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30230 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30233 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30235 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30238 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30240 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30243 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30245 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30248 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30250 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30253 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30255 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30258 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30260 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30263 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30265 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30268 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
30270 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30273 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
30275 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30278 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
30280 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30283 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
30285 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30288 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
30290 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30293 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
30295 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30298 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
30300 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30303 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
30305 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30308 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
30310 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30313 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
30315 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30318 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
30320 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30323 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
30325 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30328 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
30330 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30333 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
30335 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30338 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
30340 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30343 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
30345 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30348 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
30350 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30353 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
30355 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30358 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30360 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30363 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
30365 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30368 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
30370 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30373 /* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
30375 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30378 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30380 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30383 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
30385 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30388 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
30390 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30393 /* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
30395 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30398 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30400 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30403 /* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
30405 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30408 /* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
30410 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30413 /* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
30415 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30418 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
30420 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30423 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30425 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30428 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30430 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30433 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
30435 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30438 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
30440 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30443 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30445 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30448 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30450 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30453 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
30455 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30458 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
30460 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30463 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30465 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30468 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30470 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30473 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
30475 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30478 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
30480 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30483 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
30485 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30488 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
30490 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30493 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
30495 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30498 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
30500 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30503 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
30505 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30508 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
30510 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30513 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
30515 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30518 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
30520 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30523 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
30525 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30528 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
30530 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30533 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
30535 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30538 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
30540 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30543 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
30545 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30548 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
30550 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30553 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
30555 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30558 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
30560 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30563 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
30565 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30568 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
30570 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30573 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
30575 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30578 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
30580 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30583 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
30585 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30588 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
30590 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30593 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
30595 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30598 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30600 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
30601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30603 /* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
30605 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
30606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30608 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30610 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
30611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30613 /* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
30615 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
30616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30618 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30620 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
30621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30623 /* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
30625 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
30626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30628 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
30630 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
30631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30633 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
30635 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
30636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30638 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
30640 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
30641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30643 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
30645 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
30646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30648 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
30650 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
30651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30653 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
30655 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
30656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30658 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
30660 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
30661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30663 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
30665 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
30666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30668 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
30670 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
30671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30673 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
30675 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
30676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30678 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
30680 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
30681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30683 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
30685 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
30686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30688 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
30690 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
30691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30693 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
30695 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
30696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30698 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
30700 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
30701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30703 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
30705 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
30706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30708 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
30710 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
30711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30713 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
30715 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
30716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30718 /* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
30720 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30723 /* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
30725 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30728 /* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
30730 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30733 /* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
30735 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30738 /* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
30740 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30743 /* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
30745 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30748 /* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
30750 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30753 /* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
30755 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30758 /* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
30760 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30763 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30765 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30768 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30770 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30773 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
30775 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30778 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30780 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30783 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30785 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30788 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
30790 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30793 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30795 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30798 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30800 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30803 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
30805 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30808 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
30810 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30813 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
30815 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30818 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
30820 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30823 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
30825 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30828 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
30830 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30833 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
30835 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30838 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
30840 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30843 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
30845 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30848 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
30850 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30853 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
30855 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30858 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
30860 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30863 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
30865 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30868 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
30870 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30873 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
30875 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30878 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
30880 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30883 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
30885 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30888 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
30890 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30893 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
30895 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30898 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
30900 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30903 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
30905 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30908 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
30910 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30913 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
30915 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30918 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
30920 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30923 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
30925 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30928 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30930 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30933 /* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30935 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30938 /* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30940 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30943 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30945 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30948 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30950 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30953 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30955 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30958 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30960 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30963 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30965 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30968 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30970 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30973 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30975 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30978 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30980 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30983 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30985 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30988 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
30990 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30993 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
30995 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
30998 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
31000 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
31001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31003 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
31005 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
31006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31008 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
31010 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
31011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31013 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
31015 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
31016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31018 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
31020 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
31021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31023 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
31025 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
31026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31028 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
31030 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
31031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31033 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
31035 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31038 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
31040 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31043 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
31045 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31048 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31050 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31053 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31055 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31058 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31060 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31063 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31065 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31068 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31070 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31073 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31075 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31078 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31080 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31083 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
31085 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31088 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
31090 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31093 /* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
31095 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31098 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31100 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31103 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
31105 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31108 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
31110 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31113 /* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
31115 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31118 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31120 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31123 /* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31125 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31128 /* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31130 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31133 /* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31135 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31138 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31140 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31143 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31145 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31148 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31150 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31153 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
31155 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31158 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
31160 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31163 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31165 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31168 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31170 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31173 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
31175 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31178 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
31180 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31183 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31185 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31188 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31190 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31193 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
31195 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31198 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
31200 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31203 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
31205 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31208 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
31210 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31213 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
31215 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31218 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
31220 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31223 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
31225 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31228 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
31230 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31233 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
31235 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31238 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
31240 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31243 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
31245 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31248 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
31250 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31253 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
31255 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31258 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
31260 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31263 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
31265 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31268 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
31270 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31273 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
31275 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31278 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
31280 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31283 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
31285 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31288 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
31290 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31293 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
31295 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31298 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
31300 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31303 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
31305 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31308 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
31310 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31313 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
31315 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31318 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31320 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
31321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31323 /* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
31325 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
31326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31328 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31330 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
31331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31333 /* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
31335 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
31336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31338 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31340 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
31341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31343 /* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
31345 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
31346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31348 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
31350 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
31351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31353 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
31355 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
31356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31358 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
31360 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
31361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31363 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
31365 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
31366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31368 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
31370 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
31371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31373 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
31375 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
31376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31378 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
31380 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
31381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31383 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
31385 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
31386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31388 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
31390 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
31391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31393 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
31395 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
31396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31398 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
31400 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
31401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31403 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
31405 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
31406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31408 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
31410 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
31411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31413 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
31415 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
31416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31418 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
31420 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
31421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31423 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
31425 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
31426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31428 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
31430 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
31431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31433 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
31435 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
31436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31438 /* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
31440 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31443 /* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
31445 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31448 /* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
31450 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31453 /* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
31455 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31458 /* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
31460 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31463 /* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
31465 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31468 /* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
31470 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31473 /* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
31475 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31478 /* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
31480 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31483 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31485 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31488 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31490 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31493 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
31495 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31498 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31500 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31503 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31505 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31508 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
31510 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31513 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31515 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31518 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31520 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31523 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
31525 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31528 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
31530 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31533 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
31535 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31538 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
31540 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31543 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
31545 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31548 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
31550 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31553 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
31555 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31558 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
31560 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31563 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
31565 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31568 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
31570 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31573 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
31575 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31578 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
31580 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31583 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
31585 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31588 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
31590 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31593 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
31595 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31598 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
31600 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31603 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
31605 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31608 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
31610 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31613 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
31615 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31618 /* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
31620 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
31621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31623 /* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
31625 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "min.w", 40,
31626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31628 /* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
31630 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "min.w", 40,
31631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31633 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31635 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "min.w", 48,
31636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31638 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
31640 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 48,
31641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31643 /* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
31645 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 48,
31646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31648 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31650 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "min.w", 56,
31651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31653 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
31655 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 56,
31656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31658 /* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
31660 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 56,
31661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31663 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
31665 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "min.w", 56,
31666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31668 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31670 M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "min.w", 64,
31671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31673 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
31675 M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "min.w", 64,
31676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31678 /* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
31680 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
31681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31683 /* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
31685 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "min.b", 32,
31686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31688 /* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
31690 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "min.b", 32,
31691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31693 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31695 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "min.b", 40,
31696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31698 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
31700 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 40,
31701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31703 /* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
31705 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 40,
31706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31708 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31710 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "min.b", 48,
31711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31713 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
31715 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 48,
31716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31718 /* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
31720 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 48,
31721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31723 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
31725 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "min.b", 48,
31726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31728 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31730 M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "min.b", 56,
31731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31733 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
31735 M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "min.b", 56,
31736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31738 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31740 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31743 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
31745 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31748 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
31750 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31753 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31755 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31758 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
31760 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31763 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
31765 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31768 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31770 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31773 /* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
31775 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31778 /* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
31780 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31783 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
31785 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31788 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31790 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31793 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31795 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31798 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
31800 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31803 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31805 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31808 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31810 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31813 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
31815 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31818 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31820 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31823 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31825 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31828 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
31830 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31833 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
31835 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31838 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
31840 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31843 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
31845 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31848 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
31850 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31853 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
31855 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31858 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
31860 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31863 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
31865 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31868 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
31870 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31873 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
31875 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31878 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
31880 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31883 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
31885 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31888 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31890 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31893 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31895 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31898 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31900 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31903 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31905 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31908 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31910 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31913 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31915 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31918 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31920 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31923 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
31925 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31928 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
31930 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31933 /* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
31935 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31938 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31940 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31943 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
31945 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31948 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
31950 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31953 /* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
31955 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31958 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31960 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31963 /* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31965 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31968 /* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31970 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31973 /* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31975 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31978 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31980 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31983 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31985 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31988 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31990 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31993 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
31995 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
31998 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
32000 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
32001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32003 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32005 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
32006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32008 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32010 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
32011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32013 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
32015 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
32016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32018 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
32020 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
32021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32023 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32025 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
32026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32028 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32030 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
32031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32033 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
32035 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
32036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32038 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
32040 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32043 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
32045 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32048 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32050 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32053 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32055 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32058 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32060 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32063 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32065 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32068 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32070 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32073 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32075 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32078 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32080 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32083 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32085 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32088 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32090 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32093 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32095 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32098 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32100 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32103 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32105 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32108 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32110 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32113 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32115 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32118 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32120 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32123 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32125 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32128 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32130 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32133 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
32135 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32138 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32140 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32143 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32145 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32148 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32150 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32153 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
32155 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32158 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
32160 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
32161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32163 /* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
32165 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
32166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32168 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
32170 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
32171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32173 /* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
32175 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
32176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32178 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32180 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
32181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32183 /* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32185 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
32186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32188 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32190 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
32191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32193 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32195 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
32196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32198 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32200 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
32201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32203 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32205 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
32206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32208 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32210 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
32211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32213 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32215 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
32216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32218 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32220 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
32221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32223 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32225 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
32226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32228 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32230 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
32231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32233 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32235 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
32236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32238 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32240 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
32241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32243 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32245 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
32246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32248 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32250 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
32251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32253 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32255 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
32256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32258 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32260 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
32261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32263 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
32265 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
32266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32268 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
32270 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
32271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32273 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
32275 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
32276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32278 /* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
32280 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32283 /* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
32285 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32288 /* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
32290 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32293 /* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
32295 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32298 /* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
32300 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32303 /* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
32305 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32308 /* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
32310 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32313 /* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
32315 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32318 /* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
32320 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32323 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32325 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32328 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32330 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32333 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
32335 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32338 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32340 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32343 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32345 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32348 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
32350 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32353 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32355 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32358 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32360 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32363 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
32365 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32368 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
32370 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32373 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
32375 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32378 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
32380 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32383 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
32385 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32388 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
32390 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32393 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
32395 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32398 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
32400 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32403 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
32405 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32408 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
32410 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32413 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
32415 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32418 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
32420 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32423 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
32425 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32428 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
32430 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32433 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
32435 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32438 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
32440 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32443 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
32445 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32448 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
32450 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32453 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
32455 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32458 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32460 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32463 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
32465 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32468 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
32470 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32473 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32475 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32478 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
32480 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32483 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
32485 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32488 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32490 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32493 /* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
32495 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32498 /* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
32500 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32503 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
32505 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32508 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32510 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32513 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32515 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32518 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
32520 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32523 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32525 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32528 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32530 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32533 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
32535 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32538 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32540 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32543 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32545 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32548 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
32550 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32553 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
32555 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32558 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
32560 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32563 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
32565 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32568 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
32570 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32573 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
32575 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32578 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
32580 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32583 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
32585 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32588 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
32590 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32593 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
32595 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32598 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
32600 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32603 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
32605 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32608 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
32610 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32613 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
32615 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32618 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
32620 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32623 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
32625 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32628 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
32630 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32633 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
32635 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32638 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32640 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32643 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
32645 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32648 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
32650 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32653 /* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
32655 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32658 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32660 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32663 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
32665 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32668 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
32670 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32673 /* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
32675 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32678 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32680 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32683 /* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
32685 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32688 /* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
32690 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32693 /* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
32695 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32698 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
32700 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32703 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32705 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32708 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32710 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32713 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
32715 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32718 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
32720 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32723 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32725 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32728 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32730 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32733 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
32735 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32738 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
32740 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32743 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32745 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32748 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32750 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32753 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
32755 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32758 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
32760 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32763 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
32765 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32768 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32770 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32773 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32775 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32778 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32780 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32783 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32785 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32788 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32790 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32793 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32795 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32798 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32800 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32803 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32805 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32808 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32810 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32813 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32815 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32818 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32820 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32823 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32825 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32828 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32830 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32833 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32835 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32838 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32840 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32843 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32845 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32848 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32850 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32853 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
32855 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32858 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32860 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32863 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32865 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32868 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32870 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32873 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
32875 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32878 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32880 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
32881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32883 /* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
32885 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
32886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32888 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32890 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
32891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32893 /* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
32895 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
32896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32898 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32900 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
32901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32903 /* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32905 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
32906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32908 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32910 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
32911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32913 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32915 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
32916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32918 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32920 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
32921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32923 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32925 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
32926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32928 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32930 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
32931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32933 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32935 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
32936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32938 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32940 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
32941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32943 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32945 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
32946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32948 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32950 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
32951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32953 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32955 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
32956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32958 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32960 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
32961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32963 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32965 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
32966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32968 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32970 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
32971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32973 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32975 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
32976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32978 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32980 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
32981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32983 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
32985 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
32986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32988 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
32990 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
32991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32993 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
32995 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
32996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
32998 /* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
33000 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
33001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33003 /* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
33005 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
33006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33008 /* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
33010 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
33011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33013 /* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
33015 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
33016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33018 /* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
33020 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
33021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33023 /* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
33025 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
33026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33028 /* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
33030 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
33031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33033 /* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
33035 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
33036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33038 /* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
33040 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
33041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33043 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
33045 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33048 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
33050 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33053 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
33055 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33058 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33060 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33063 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33065 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33068 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
33070 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33073 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33075 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33078 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33080 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33083 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
33085 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33088 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
33090 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33093 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
33095 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33098 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
33100 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33103 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
33105 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33108 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
33110 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33113 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
33115 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33118 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
33120 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33123 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
33125 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33128 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
33130 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33133 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
33135 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33138 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
33140 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33143 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
33145 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33148 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
33150 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33153 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
33155 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33158 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
33160 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33163 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
33165 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33168 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
33170 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33173 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
33175 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33178 /* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
33180 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
33181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33183 /* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
33185 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "max.w", 40,
33186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33188 /* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
33190 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "max.w", 40,
33191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33193 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33195 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "max.w", 48,
33196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33198 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
33200 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 48,
33201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33203 /* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
33205 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 48,
33206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33208 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33210 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "max.w", 56,
33211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33213 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
33215 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 56,
33216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33218 /* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
33220 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 56,
33221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33223 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
33225 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "max.w", 56,
33226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33228 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33230 M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "max.w", 64,
33231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33233 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
33235 M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "max.w", 64,
33236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33238 /* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
33240 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
33241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33243 /* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
33245 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "max.b", 32,
33246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33248 /* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
33250 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "max.b", 32,
33251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33253 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33255 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "max.b", 40,
33256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33258 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
33260 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 40,
33261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33263 /* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
33265 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 40,
33266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33268 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33270 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "max.b", 48,
33271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33273 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
33275 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 48,
33276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33278 /* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
33280 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 48,
33281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33283 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
33285 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "max.b", 48,
33286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33288 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33290 M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "max.b", 56,
33291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33293 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
33295 M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "max.b", 56,
33296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33298 /* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
33300 M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-An-relative-HI", "ste.w", 32,
33301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33303 /* ste.w ${Dsp-16-u16}[sb],[a1a0] */
33305 M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "ste.w", 32,
33306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33308 /* ste.w ${Dsp-16-u16},[a1a0] */
33310 M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-a1a0-dst16-16-16-absolute-HI", "ste.w", 32,
33311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33313 /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
33315 M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-An-relative-HI", "ste.w", 56,
33316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33318 /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
33320 M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "ste.w", 56,
33321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33323 /* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
33325 M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20a0-dst16-16-16-absolute-HI", "ste.w", 56,
33326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33328 /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33330 M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-An-relative-HI", "ste.w", 56,
33331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33333 /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33335 M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-SB-relative-HI", "ste.w", 56,
33336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33338 /* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
33340 M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20-dst16-16-16-absolute-HI", "ste.w", 56,
33341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33343 /* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
33345 M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-An-relative-HI", "ste.w", 24,
33346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33348 /* ste.w ${Dsp-16-u8}[sb],[a1a0] */
33350 M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "ste.w", 24,
33351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33353 /* ste.w ${Dsp-16-s8}[fb],[a1a0] */
33355 M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "ste.w", 24,
33356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33358 /* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
33360 M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-An-relative-HI", "ste.w", 48,
33361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33363 /* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
33365 M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "ste.w", 48,
33366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33368 /* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
33370 M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "ste.w", 48,
33371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33373 /* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33375 M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-An-relative-HI", "ste.w", 48,
33376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33378 /* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33380 M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-SB-relative-HI", "ste.w", 48,
33381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33383 /* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33385 M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-FB-relative-HI", "ste.w", 48,
33386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33388 /* ste.w $Dst16RnHI,[a1a0] */
33390 M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "ste.w-basic-a1a0-dst16-Rn-direct-HI", "ste.w", 16,
33391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33393 /* ste.w $Dst16AnHI,[a1a0] */
33395 M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "ste.w-basic-a1a0-dst16-An-direct-HI", "ste.w", 16,
33396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33398 /* ste.w [$Dst16An],[a1a0] */
33400 M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "ste.w-basic-a1a0-dst16-An-indirect-HI", "ste.w", 16,
33401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33403 /* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
33405 M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "ste.w-basic-u20a0-dst16-Rn-direct-HI", "ste.w", 40,
33406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33408 /* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
33410 M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "ste.w-basic-u20a0-dst16-An-direct-HI", "ste.w", 40,
33411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33413 /* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
33415 M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "ste.w-basic-u20a0-dst16-An-indirect-HI", "ste.w", 40,
33416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33418 /* ste.w $Dst16RnHI,${Dsp-16-u20} */
33420 M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, "ste.w-basic-u20-dst16-Rn-direct-HI", "ste.w", 40,
33421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33423 /* ste.w $Dst16AnHI,${Dsp-16-u20} */
33425 M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, "ste.w-basic-u20-dst16-An-direct-HI", "ste.w", 40,
33426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33428 /* ste.w [$Dst16An],${Dsp-16-u20} */
33430 M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "ste.w-basic-u20-dst16-An-indirect-HI", "ste.w", 40,
33431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33433 /* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
33435 M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-An-relative-QI", "ste.b", 32,
33436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33438 /* ste.b ${Dsp-16-u16}[sb],[a1a0] */
33440 M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "ste.b", 32,
33441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33443 /* ste.b ${Dsp-16-u16},[a1a0] */
33445 M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-a1a0-dst16-16-16-absolute-QI", "ste.b", 32,
33446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33448 /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
33450 M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-An-relative-QI", "ste.b", 56,
33451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33453 /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
33455 M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "ste.b", 56,
33456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33458 /* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
33460 M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20a0-dst16-16-16-absolute-QI", "ste.b", 56,
33461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33463 /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33465 M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-An-relative-QI", "ste.b", 56,
33466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33468 /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33470 M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-SB-relative-QI", "ste.b", 56,
33471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33473 /* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
33475 M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20-dst16-16-16-absolute-QI", "ste.b", 56,
33476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33478 /* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
33480 M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-An-relative-QI", "ste.b", 24,
33481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33483 /* ste.b ${Dsp-16-u8}[sb],[a1a0] */
33485 M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "ste.b", 24,
33486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33488 /* ste.b ${Dsp-16-s8}[fb],[a1a0] */
33490 M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "ste.b", 24,
33491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33493 /* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
33495 M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-An-relative-QI", "ste.b", 48,
33496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33498 /* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
33500 M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "ste.b", 48,
33501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33503 /* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
33505 M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "ste.b", 48,
33506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33508 /* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33510 M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-An-relative-QI", "ste.b", 48,
33511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33513 /* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33515 M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-SB-relative-QI", "ste.b", 48,
33516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33518 /* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33520 M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-FB-relative-QI", "ste.b", 48,
33521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33523 /* ste.b $Dst16RnQI,[a1a0] */
33525 M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "ste.b-basic-a1a0-dst16-Rn-direct-QI", "ste.b", 16,
33526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33528 /* ste.b $Dst16AnQI,[a1a0] */
33530 M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "ste.b-basic-a1a0-dst16-An-direct-QI", "ste.b", 16,
33531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33533 /* ste.b [$Dst16An],[a1a0] */
33535 M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "ste.b-basic-a1a0-dst16-An-indirect-QI", "ste.b", 16,
33536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33538 /* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
33540 M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "ste.b-basic-u20a0-dst16-Rn-direct-QI", "ste.b", 40,
33541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33543 /* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
33545 M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "ste.b-basic-u20a0-dst16-An-direct-QI", "ste.b", 40,
33546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33548 /* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
33550 M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "ste.b-basic-u20a0-dst16-An-indirect-QI", "ste.b", 40,
33551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33553 /* ste.b $Dst16RnQI,${Dsp-16-u20} */
33555 M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, "ste.b-basic-u20-dst16-Rn-direct-QI", "ste.b", 40,
33556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33558 /* ste.b $Dst16AnQI,${Dsp-16-u20} */
33560 M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, "ste.b-basic-u20-dst16-An-direct-QI", "ste.b", 40,
33561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33563 /* ste.b [$Dst16An],${Dsp-16-u20} */
33565 M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "ste.b-basic-u20-dst16-An-indirect-QI", "ste.b", 40,
33566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33568 /* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
33570 M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-An-relative-HI", "lde.w", 32,
33571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33573 /* lde.w [a1a0],${Dsp-16-u16}[sb] */
33575 M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "lde.w", 32,
33576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33578 /* lde.w [a1a0],${Dsp-16-u16} */
33580 M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-a1a0-dst16-16-16-absolute-HI", "lde.w", 32,
33581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33583 /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
33585 M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-An-relative-HI", "lde.w", 56,
33586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33588 /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
33590 M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "lde.w", 56,
33591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33593 /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
33595 M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20a0-dst16-16-16-absolute-HI", "lde.w", 56,
33596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33598 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33600 M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-An-relative-HI", "lde.w", 56,
33601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33603 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33605 M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-SB-relative-HI", "lde.w", 56,
33606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33608 /* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
33610 M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20-dst16-16-16-absolute-HI", "lde.w", 56,
33611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33613 /* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
33615 M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-An-relative-HI", "lde.w", 24,
33616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33618 /* lde.w [a1a0],${Dsp-16-u8}[sb] */
33620 M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "lde.w", 24,
33621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33623 /* lde.w [a1a0],${Dsp-16-s8}[fb] */
33625 M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "lde.w", 24,
33626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33628 /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
33630 M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-An-relative-HI", "lde.w", 48,
33631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33633 /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
33635 M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "lde.w", 48,
33636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33638 /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
33640 M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "lde.w", 48,
33641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33643 /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33645 M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-An-relative-HI", "lde.w", 48,
33646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33648 /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33650 M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-SB-relative-HI", "lde.w", 48,
33651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33653 /* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33655 M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-FB-relative-HI", "lde.w", 48,
33656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33658 /* lde.w [a1a0],$Dst16RnHI */
33660 M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "lde.w-basic-a1a0-dst16-Rn-direct-HI", "lde.w", 16,
33661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33663 /* lde.w [a1a0],$Dst16AnHI */
33665 M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "lde.w-basic-a1a0-dst16-An-direct-HI", "lde.w", 16,
33666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33668 /* lde.w [a1a0],[$Dst16An] */
33670 M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "lde.w-basic-a1a0-dst16-An-indirect-HI", "lde.w", 16,
33671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33673 /* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
33675 M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "lde.w-basic-u20a0-dst16-Rn-direct-HI", "lde.w", 40,
33676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33678 /* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
33680 M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "lde.w-basic-u20a0-dst16-An-direct-HI", "lde.w", 40,
33681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33683 /* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
33685 M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "lde.w-basic-u20a0-dst16-An-indirect-HI", "lde.w", 40,
33686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33688 /* lde.w ${Dsp-16-u20},$Dst16RnHI */
33690 M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, "lde.w-basic-u20-dst16-Rn-direct-HI", "lde.w", 40,
33691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33693 /* lde.w ${Dsp-16-u20},$Dst16AnHI */
33695 M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, "lde.w-basic-u20-dst16-An-direct-HI", "lde.w", 40,
33696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33698 /* lde.w ${Dsp-16-u20},[$Dst16An] */
33700 M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "lde.w-basic-u20-dst16-An-indirect-HI", "lde.w", 40,
33701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33703 /* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
33705 M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-An-relative-QI", "lde.b", 32,
33706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33708 /* lde.b [a1a0],${Dsp-16-u16}[sb] */
33710 M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "lde.b", 32,
33711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33713 /* lde.b [a1a0],${Dsp-16-u16} */
33715 M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-a1a0-dst16-16-16-absolute-QI", "lde.b", 32,
33716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33718 /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
33720 M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-An-relative-QI", "lde.b", 56,
33721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33723 /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
33725 M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "lde.b", 56,
33726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33728 /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
33730 M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20a0-dst16-16-16-absolute-QI", "lde.b", 56,
33731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33733 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33735 M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-An-relative-QI", "lde.b", 56,
33736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33738 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33740 M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-SB-relative-QI", "lde.b", 56,
33741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33743 /* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
33745 M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20-dst16-16-16-absolute-QI", "lde.b", 56,
33746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33748 /* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
33750 M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-An-relative-QI", "lde.b", 24,
33751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33753 /* lde.b [a1a0],${Dsp-16-u8}[sb] */
33755 M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "lde.b", 24,
33756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33758 /* lde.b [a1a0],${Dsp-16-s8}[fb] */
33760 M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "lde.b", 24,
33761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33763 /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
33765 M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-An-relative-QI", "lde.b", 48,
33766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33768 /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
33770 M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "lde.b", 48,
33771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33773 /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
33775 M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "lde.b", 48,
33776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33778 /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33780 M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-An-relative-QI", "lde.b", 48,
33781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33783 /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33785 M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-SB-relative-QI", "lde.b", 48,
33786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33788 /* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33790 M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-FB-relative-QI", "lde.b", 48,
33791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33793 /* lde.b [a1a0],$Dst16RnQI */
33795 M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "lde.b-basic-a1a0-dst16-Rn-direct-QI", "lde.b", 16,
33796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33798 /* lde.b [a1a0],$Dst16AnQI */
33800 M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "lde.b-basic-a1a0-dst16-An-direct-QI", "lde.b", 16,
33801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33803 /* lde.b [a1a0],[$Dst16An] */
33805 M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "lde.b-basic-a1a0-dst16-An-indirect-QI", "lde.b", 16,
33806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33808 /* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
33810 M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "lde.b-basic-u20a0-dst16-Rn-direct-QI", "lde.b", 40,
33811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33813 /* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
33815 M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "lde.b-basic-u20a0-dst16-An-direct-QI", "lde.b", 40,
33816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33818 /* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
33820 M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "lde.b-basic-u20a0-dst16-An-indirect-QI", "lde.b", 40,
33821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33823 /* lde.b ${Dsp-16-u20},$Dst16RnQI */
33825 M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, "lde.b-basic-u20-dst16-Rn-direct-QI", "lde.b", 40,
33826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33828 /* lde.b ${Dsp-16-u20},$Dst16AnQI */
33830 M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, "lde.b-basic-u20-dst16-An-direct-QI", "lde.b", 40,
33831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33833 /* lde.b ${Dsp-16-u20},[$Dst16An] */
33835 M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "lde.b-basic-u20-dst16-An-indirect-QI", "lde.b", 40,
33836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
33838 /* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
33840 M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "stc", 24,
33841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33843 /* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
33845 M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-direct-Prefixed-SI", "stc", 24,
33846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33848 /* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
33850 M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-indirect-Prefixed-SI", "stc", 24,
33851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33853 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33855 M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "stc", 32,
33856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33858 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33860 M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "stc", 40,
33861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33863 /* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33865 M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "stc", 48,
33866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33868 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
33870 M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "stc", 32,
33871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33873 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
33875 M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "stc", 40,
33876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33878 /* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
33880 M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "stc", 32,
33881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33883 /* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
33885 M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "stc", 40,
33886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33888 /* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
33890 M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "stc", 40,
33891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33893 /* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
33895 M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "stc", 48,
33896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33898 /* stc ${cr2-32},$Dst32RnUnprefixedSI */
33900 M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "stc", 16,
33901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33903 /* stc ${cr2-32},$Dst32AnUnprefixedSI */
33905 M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-direct-Unprefixed-SI", "stc", 16,
33906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33908 /* stc ${cr2-32},[$Dst32AnUnprefixed] */
33910 M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "stc", 16,
33911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33913 /* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
33915 M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "stc", 24,
33916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33918 /* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
33920 M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "stc", 32,
33921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33923 /* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
33925 M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "stc", 40,
33926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33928 /* stc ${cr2-32},${Dsp-16-u8}[sb] */
33930 M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "stc", 24,
33931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33933 /* stc ${cr2-32},${Dsp-16-u16}[sb] */
33935 M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "stc", 32,
33936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33938 /* stc ${cr2-32},${Dsp-16-s8}[fb] */
33940 M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "stc", 24,
33941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33943 /* stc ${cr2-32},${Dsp-16-s16}[fb] */
33945 M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "stc", 32,
33946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33948 /* stc ${cr2-32},${Dsp-16-u16} */
33950 M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "stc", 32,
33951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33953 /* stc ${cr2-32},${Dsp-16-u24} */
33955 M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "stc", 40,
33956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33958 /* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
33960 M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "stc", 24,
33961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33963 /* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
33965 M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-direct-Prefixed-HI", "stc", 24,
33966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33968 /* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
33970 M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-indirect-Prefixed-HI", "stc", 24,
33971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33973 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33975 M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "stc", 32,
33976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33978 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33980 M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "stc", 40,
33981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33983 /* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33985 M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "stc", 48,
33986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33988 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
33990 M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "stc", 32,
33991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33993 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
33995 M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "stc", 40,
33996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
33998 /* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
34000 M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "stc", 32,
34001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34003 /* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
34005 M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "stc", 40,
34006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34008 /* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
34010 M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "stc", 40,
34011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34013 /* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
34015 M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "stc", 48,
34016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34018 /* stc pc,$Dst16RnHI */
34020 M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, "stc16.pc-dst16-Rn-direct-HI", "stc", 16,
34021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34023 /* stc pc,$Dst16AnHI */
34025 M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, "stc16.pc-dst16-An-direct-HI", "stc", 16,
34026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34028 /* stc pc,[$Dst16An] */
34030 M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, "stc16.pc-dst16-An-indirect-HI", "stc", 16,
34031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34033 /* stc pc,${Dsp-16-u8}[$Dst16An] */
34035 M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, "stc16.pc-dst16-16-8-An-relative-HI", "stc", 24,
34036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34038 /* stc pc,${Dsp-16-u16}[$Dst16An] */
34040 M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, "stc16.pc-dst16-16-16-An-relative-HI", "stc", 32,
34041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34043 /* stc pc,${Dsp-16-u8}[sb] */
34045 M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, "stc16.pc-dst16-16-8-SB-relative-HI", "stc", 24,
34046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34048 /* stc pc,${Dsp-16-u16}[sb] */
34050 M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, "stc16.pc-dst16-16-16-SB-relative-HI", "stc", 32,
34051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34053 /* stc pc,${Dsp-16-s8}[fb] */
34055 M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, "stc16.pc-dst16-16-8-FB-relative-HI", "stc", 24,
34056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34058 /* stc pc,${Dsp-16-u16} */
34060 M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, "stc16.pc-dst16-16-16-absolute-HI", "stc", 32,
34061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34063 /* stc ${cr16},$Dst16RnHI */
34065 M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, "stc16.src-dst16-Rn-direct-HI", "stc", 16,
34066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34068 /* stc ${cr16},$Dst16AnHI */
34070 M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, "stc16.src-dst16-An-direct-HI", "stc", 16,
34071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34073 /* stc ${cr16},[$Dst16An] */
34075 M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, "stc16.src-dst16-An-indirect-HI", "stc", 16,
34076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34078 /* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
34080 M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, "stc16.src-dst16-16-8-An-relative-HI", "stc", 24,
34081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34083 /* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
34085 M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, "stc16.src-dst16-16-16-An-relative-HI", "stc", 32,
34086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34088 /* stc ${cr16},${Dsp-16-u8}[sb] */
34090 M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, "stc16.src-dst16-16-8-SB-relative-HI", "stc", 24,
34091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34093 /* stc ${cr16},${Dsp-16-u16}[sb] */
34095 M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, "stc16.src-dst16-16-16-SB-relative-HI", "stc", 32,
34096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34098 /* stc ${cr16},${Dsp-16-s8}[fb] */
34100 M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, "stc16.src-dst16-16-8-FB-relative-HI", "stc", 24,
34101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34103 /* stc ${cr16},${Dsp-16-u16} */
34105 M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, "stc16.src-dst16-16-16-absolute-HI", "stc", 32,
34106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34108 /* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
34110 M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "ldc", 24,
34111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34113 /* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
34115 M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-direct-Prefixed-SI", "ldc", 24,
34116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34118 /* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
34120 M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-indirect-Prefixed-SI", "ldc", 24,
34121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34123 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34125 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "ldc", 32,
34126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34128 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34130 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "ldc", 40,
34131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34133 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34135 M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "ldc", 48,
34136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34138 /* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
34140 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "ldc", 32,
34141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34143 /* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
34145 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "ldc", 40,
34146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34148 /* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
34150 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "ldc", 32,
34151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34153 /* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
34155 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "ldc", 40,
34156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34158 /* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
34160 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "ldc", 40,
34161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34163 /* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
34165 M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "ldc", 48,
34166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34168 /* ldc $Dst32RnUnprefixedSI,${cr2-32} */
34170 M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "ldc", 16,
34171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34173 /* ldc $Dst32AnUnprefixedSI,${cr2-32} */
34175 M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-direct-Unprefixed-SI", "ldc", 16,
34176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34178 /* ldc [$Dst32AnUnprefixed],${cr2-32} */
34180 M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "ldc", 16,
34181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34183 /* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
34185 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "ldc", 24,
34186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34188 /* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
34190 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "ldc", 32,
34191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34193 /* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
34195 M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "ldc", 40,
34196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34198 /* ldc ${Dsp-16-u8}[sb],${cr2-32} */
34200 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "ldc", 24,
34201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34203 /* ldc ${Dsp-16-u16}[sb],${cr2-32} */
34205 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "ldc", 32,
34206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34208 /* ldc ${Dsp-16-s8}[fb],${cr2-32} */
34210 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "ldc", 24,
34211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34213 /* ldc ${Dsp-16-s16}[fb],${cr2-32} */
34215 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "ldc", 32,
34216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34218 /* ldc ${Dsp-16-u16},${cr2-32} */
34220 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "ldc", 32,
34221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34223 /* ldc ${Dsp-16-u24},${cr2-32} */
34225 M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "ldc", 40,
34226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34228 /* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
34230 M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "ldc", 24,
34231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34233 /* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
34235 M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-direct-Prefixed-HI", "ldc", 24,
34236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34238 /* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
34240 M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-indirect-Prefixed-HI", "ldc", 24,
34241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34243 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34245 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "ldc", 32,
34246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34248 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34250 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "ldc", 40,
34251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34253 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34255 M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "ldc", 48,
34256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34258 /* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
34260 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "ldc", 32,
34261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34263 /* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
34265 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "ldc", 40,
34266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34268 /* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
34270 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "ldc", 32,
34271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34273 /* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
34275 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "ldc", 40,
34276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34278 /* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
34280 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "ldc", 40,
34281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34283 /* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
34285 M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "ldc", 48,
34286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34288 /* ldc $Dst16RnHI,${cr16} */
34290 M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, "ldc16.dst-dst16-Rn-direct-HI", "ldc", 16,
34291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34293 /* ldc $Dst16AnHI,${cr16} */
34295 M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, "ldc16.dst-dst16-An-direct-HI", "ldc", 16,
34296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34298 /* ldc [$Dst16An],${cr16} */
34300 M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, "ldc16.dst-dst16-An-indirect-HI", "ldc", 16,
34301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34303 /* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
34305 M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, "ldc16.dst-dst16-16-8-An-relative-HI", "ldc", 24,
34306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34308 /* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
34310 M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, "ldc16.dst-dst16-16-16-An-relative-HI", "ldc", 32,
34311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34313 /* ldc ${Dsp-16-u8}[sb],${cr16} */
34315 M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, "ldc16.dst-dst16-16-8-SB-relative-HI", "ldc", 24,
34316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34318 /* ldc ${Dsp-16-u16}[sb],${cr16} */
34320 M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, "ldc16.dst-dst16-16-16-SB-relative-HI", "ldc", 32,
34321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34323 /* ldc ${Dsp-16-s8}[fb],${cr16} */
34325 M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, "ldc16.dst-dst16-16-8-FB-relative-HI", "ldc", 24,
34326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34328 /* ldc ${Dsp-16-u16},${cr16} */
34330 M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, "ldc16.dst-dst16-16-16-absolute-HI", "ldc", 32,
34331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34333 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34335 M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.w", 40,
34336 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34338 /* jsri.w ${Dsp-16-u24} */
34340 M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.w", 40,
34341 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34343 /* jsri.a $Dst32RnUnprefixedSI */
34345 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16,
34346 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34348 /* jsri.a $Dst32AnUnprefixedSI */
34350 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16,
34351 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34353 /* jsri.a [$Dst32AnUnprefixed] */
34355 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16,
34356 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34358 /* jsri.a $Dst16RnSI */
34360 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16,
34361 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34363 /* jsri.a $Dst16AnSI */
34365 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16,
34366 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34368 /* jsri.a [$Dst16An] */
34370 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
34371 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34373 /* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34375 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "jsri.a", 32,
34376 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34378 /* jsri.a ${Dsp-16-u16}[sb] */
34380 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32,
34381 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34383 /* jsri.a ${Dsp-16-s16}[fb] */
34385 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32,
34386 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34388 /* jsri.a ${Dsp-16-u16} */
34390 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32,
34391 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34393 /* jsri.a ${Dsp-16-u16}[$Dst16An] */
34395 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-An-relative-SI", "jsri.a", 32,
34396 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34398 /* jsri.a ${Dsp-16-u16}[sb] */
34400 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32,
34401 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34403 /* jsri.a ${Dsp-16-u16} */
34405 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-absolute-SI", "jsri.a", 32,
34406 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34408 /* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34410 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "jsri.a", 24,
34411 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34413 /* jsri.a ${Dsp-16-u8}[sb] */
34415 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "jsri.a", 24,
34416 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34418 /* jsri.a ${Dsp-16-s8}[fb] */
34420 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "jsri.a", 24,
34421 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34423 /* jsri.a ${Dsp-16-u8}[$Dst16An] */
34425 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-An-relative-SI", "jsri.a", 24,
34426 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34428 /* jsri.a ${Dsp-16-u8}[sb] */
34430 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-SB-relative-SI", "jsri.a", 24,
34431 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34433 /* jsri.a ${Dsp-16-s8}[fb] */
34435 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24,
34436 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34438 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34440 M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
34441 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34443 /* jsri.w ${Dsp-16-u24} */
34445 M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
34446 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34448 /* jsri.w $Dst32RnUnprefixedHI */
34450 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
34451 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34453 /* jsri.w $Dst32AnUnprefixedHI */
34455 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16,
34456 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34458 /* jsri.w [$Dst32AnUnprefixed] */
34460 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16,
34461 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34463 /* jsri.w $Dst16RnHI */
34465 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16,
34466 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34468 /* jsri.w $Dst16AnHI */
34470 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16,
34471 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34473 /* jsri.w [$Dst16An] */
34475 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
34476 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34478 /* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34480 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "jsri.w", 32,
34481 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34483 /* jsri.w ${Dsp-16-u16}[sb] */
34485 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32,
34486 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34488 /* jsri.w ${Dsp-16-s16}[fb] */
34490 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32,
34491 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34493 /* jsri.w ${Dsp-16-u16} */
34495 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32,
34496 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34498 /* jsri.w ${Dsp-16-u16}[$Dst16An] */
34500 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-An-relative-HI", "jsri.w", 32,
34501 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34503 /* jsri.w ${Dsp-16-u16}[sb] */
34505 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32,
34506 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34508 /* jsri.w ${Dsp-16-u16} */
34510 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-absolute-HI", "jsri.w", 32,
34511 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34513 /* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34515 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24,
34516 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34518 /* jsri.w ${Dsp-16-u8}[sb] */
34520 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24,
34521 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34523 /* jsri.w ${Dsp-16-s8}[fb] */
34525 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24,
34526 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34528 /* jsri.w ${Dsp-16-u8}[$Dst16An] */
34530 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24,
34531 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34533 /* jsri.w ${Dsp-16-u8}[sb] */
34535 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24,
34536 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34538 /* jsri.w ${Dsp-16-s8}[fb] */
34540 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
34541 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34543 /* jmpi.a $Dst32RnUnprefixedSI */
34545 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "jmpi.a", 16,
34546 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34548 /* jmpi.a $Dst32AnUnprefixedSI */
34550 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "jmpi.a", 16,
34551 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34553 /* jmpi.a [$Dst32AnUnprefixed] */
34555 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "jmpi.a", 16,
34556 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34558 /* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34560 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "jmpi.a", 24,
34561 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34563 /* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34565 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "jmpi.a", 32,
34566 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34568 /* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34570 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "jmpi.a", 40,
34571 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34573 /* jmpi.a ${Dsp-16-u8}[sb] */
34575 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "jmpi.a", 24,
34576 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34578 /* jmpi.a ${Dsp-16-u16}[sb] */
34580 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "jmpi.a", 32,
34581 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34583 /* jmpi.a ${Dsp-16-s8}[fb] */
34585 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "jmpi.a", 24,
34586 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34588 /* jmpi.a ${Dsp-16-s16}[fb] */
34590 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "jmpi.a", 32,
34591 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34593 /* jmpi.a ${Dsp-16-u16} */
34595 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "jmpi.a", 32,
34596 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34598 /* jmpi.a ${Dsp-16-u24} */
34600 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "jmpi.a", 40,
34601 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34603 /* jmpi.a $Dst16RnSI */
34605 M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, "jmpi16.a-16-dst16-Rn-direct-SI", "jmpi.a", 16,
34606 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34608 /* jmpi.a $Dst16AnSI */
34610 M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, "jmpi16.a-16-dst16-An-direct-SI", "jmpi.a", 16,
34611 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34613 /* jmpi.a [$Dst16An] */
34615 M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, "jmpi16.a-16-dst16-An-indirect-SI", "jmpi.a", 16,
34616 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34618 /* jmpi.a ${Dsp-16-u8}[$Dst16An] */
34620 M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-An-relative-SI", "jmpi.a", 24,
34621 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34623 /* jmpi.a ${Dsp-16-u16}[$Dst16An] */
34625 M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-An-relative-SI", "jmpi.a", 32,
34626 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34628 /* jmpi.a ${Dsp-16-u8}[sb] */
34630 M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-SB-relative-SI", "jmpi.a", 24,
34631 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34633 /* jmpi.a ${Dsp-16-u16}[sb] */
34635 M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-SB-relative-SI", "jmpi.a", 32,
34636 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34638 /* jmpi.a ${Dsp-16-s8}[fb] */
34640 M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-FB-relative-SI", "jmpi.a", 24,
34641 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34643 /* jmpi.a ${Dsp-16-u16} */
34645 M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, "jmpi16.a-16-dst16-16-16-absolute-SI", "jmpi.a", 32,
34646 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34648 /* jmpi.w $Dst32RnUnprefixedHI */
34650 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "jmpi.w", 16,
34651 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34653 /* jmpi.w $Dst32AnUnprefixedHI */
34655 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "jmpi.w", 16,
34656 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34658 /* jmpi.w [$Dst32AnUnprefixed] */
34660 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "jmpi.w", 16,
34661 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34663 /* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34665 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "jmpi.w", 24,
34666 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34668 /* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34670 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "jmpi.w", 32,
34671 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34673 /* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34675 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "jmpi.w", 40,
34676 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34678 /* jmpi.w ${Dsp-16-u8}[sb] */
34680 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "jmpi.w", 24,
34681 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34683 /* jmpi.w ${Dsp-16-u16}[sb] */
34685 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "jmpi.w", 32,
34686 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34688 /* jmpi.w ${Dsp-16-s8}[fb] */
34690 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "jmpi.w", 24,
34691 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34693 /* jmpi.w ${Dsp-16-s16}[fb] */
34695 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "jmpi.w", 32,
34696 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34698 /* jmpi.w ${Dsp-16-u16} */
34700 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "jmpi.w", 32,
34701 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34703 /* jmpi.w ${Dsp-16-u24} */
34705 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "jmpi.w", 40,
34706 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34708 /* jmpi.w $Dst16RnHI */
34710 M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, "jmpi16.w-16-dst16-Rn-direct-HI", "jmpi.w", 16,
34711 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34713 /* jmpi.w $Dst16AnHI */
34715 M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, "jmpi16.w-16-dst16-An-direct-HI", "jmpi.w", 16,
34716 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34718 /* jmpi.w [$Dst16An] */
34720 M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, "jmpi16.w-16-dst16-An-indirect-HI", "jmpi.w", 16,
34721 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34723 /* jmpi.w ${Dsp-16-u8}[$Dst16An] */
34725 M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-An-relative-HI", "jmpi.w", 24,
34726 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34728 /* jmpi.w ${Dsp-16-u16}[$Dst16An] */
34730 M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-An-relative-HI", "jmpi.w", 32,
34731 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34733 /* jmpi.w ${Dsp-16-u8}[sb] */
34735 M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-SB-relative-HI", "jmpi.w", 24,
34736 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34738 /* jmpi.w ${Dsp-16-u16}[sb] */
34740 M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-SB-relative-HI", "jmpi.w", 32,
34741 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34743 /* jmpi.w ${Dsp-16-s8}[fb] */
34745 M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-FB-relative-HI", "jmpi.w", 24,
34746 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34748 /* jmpi.w ${Dsp-16-u16} */
34750 M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, "jmpi16.w-16-dst16-16-16-absolute-HI", "jmpi.w", 32,
34751 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
34753 /* indexws.w $Dst32RnUnprefixedHI */
34755 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexws.w", 16,
34756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34758 /* indexws.w $Dst32AnUnprefixedHI */
34760 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexws.w", 16,
34761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34763 /* indexws.w [$Dst32AnUnprefixed] */
34765 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexws.w", 16,
34766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34768 /* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34770 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexws.w", 24,
34771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34773 /* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34775 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexws.w", 32,
34776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34778 /* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34780 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexws.w", 40,
34781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34783 /* indexws.w ${Dsp-16-u8}[sb] */
34785 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexws.w", 24,
34786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34788 /* indexws.w ${Dsp-16-u16}[sb] */
34790 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexws.w", 32,
34791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34793 /* indexws.w ${Dsp-16-s8}[fb] */
34795 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexws.w", 24,
34796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34798 /* indexws.w ${Dsp-16-s16}[fb] */
34800 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexws.w", 32,
34801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34803 /* indexws.w ${Dsp-16-u16} */
34805 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexws.w", 32,
34806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34808 /* indexws.w ${Dsp-16-u24} */
34810 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexws.w", 40,
34811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34813 /* indexws.b $Dst32RnUnprefixedQI */
34815 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexws.b", 16,
34816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34818 /* indexws.b $Dst32AnUnprefixedQI */
34820 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexws.b", 16,
34821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34823 /* indexws.b [$Dst32AnUnprefixed] */
34825 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexws.b", 16,
34826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34828 /* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34830 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexws.b", 24,
34831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34833 /* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34835 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexws.b", 32,
34836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34838 /* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34840 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexws.b", 40,
34841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34843 /* indexws.b ${Dsp-16-u8}[sb] */
34845 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexws.b", 24,
34846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34848 /* indexws.b ${Dsp-16-u16}[sb] */
34850 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexws.b", 32,
34851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34853 /* indexws.b ${Dsp-16-s8}[fb] */
34855 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexws.b", 24,
34856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34858 /* indexws.b ${Dsp-16-s16}[fb] */
34860 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexws.b", 32,
34861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34863 /* indexws.b ${Dsp-16-u16} */
34865 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexws.b", 32,
34866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34868 /* indexws.b ${Dsp-16-u24} */
34870 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexws.b", 40,
34871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34873 /* indexwd.w $Dst32RnUnprefixedHI */
34875 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexwd.w", 16,
34876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34878 /* indexwd.w $Dst32AnUnprefixedHI */
34880 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexwd.w", 16,
34881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34883 /* indexwd.w [$Dst32AnUnprefixed] */
34885 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexwd.w", 16,
34886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34888 /* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34890 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexwd.w", 24,
34891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34893 /* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34895 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexwd.w", 32,
34896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34898 /* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34900 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexwd.w", 40,
34901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34903 /* indexwd.w ${Dsp-16-u8}[sb] */
34905 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexwd.w", 24,
34906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34908 /* indexwd.w ${Dsp-16-u16}[sb] */
34910 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexwd.w", 32,
34911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34913 /* indexwd.w ${Dsp-16-s8}[fb] */
34915 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexwd.w", 24,
34916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34918 /* indexwd.w ${Dsp-16-s16}[fb] */
34920 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexwd.w", 32,
34921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34923 /* indexwd.w ${Dsp-16-u16} */
34925 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexwd.w", 32,
34926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34928 /* indexwd.w ${Dsp-16-u24} */
34930 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexwd.w", 40,
34931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34933 /* indexwd.b $Dst32RnUnprefixedQI */
34935 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexwd.b", 16,
34936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34938 /* indexwd.b $Dst32AnUnprefixedQI */
34940 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexwd.b", 16,
34941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34943 /* indexwd.b [$Dst32AnUnprefixed] */
34945 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexwd.b", 16,
34946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34948 /* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34950 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexwd.b", 24,
34951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34953 /* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34955 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexwd.b", 32,
34956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34958 /* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34960 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexwd.b", 40,
34961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34963 /* indexwd.b ${Dsp-16-u8}[sb] */
34965 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexwd.b", 24,
34966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34968 /* indexwd.b ${Dsp-16-u16}[sb] */
34970 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexwd.b", 32,
34971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34973 /* indexwd.b ${Dsp-16-s8}[fb] */
34975 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexwd.b", 24,
34976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34978 /* indexwd.b ${Dsp-16-s16}[fb] */
34980 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexwd.b", 32,
34981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34983 /* indexwd.b ${Dsp-16-u16} */
34985 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexwd.b", 32,
34986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34988 /* indexwd.b ${Dsp-16-u24} */
34990 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexwd.b", 40,
34991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34993 /* indexw.w $Dst32RnUnprefixedHI */
34995 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexw.w", 16,
34996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
34998 /* indexw.w $Dst32AnUnprefixedHI */
35000 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexw.w", 16,
35001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35003 /* indexw.w [$Dst32AnUnprefixed] */
35005 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexw.w", 16,
35006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35008 /* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35010 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexw.w", 24,
35011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35013 /* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35015 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexw.w", 32,
35016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35018 /* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35020 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexw.w", 40,
35021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35023 /* indexw.w ${Dsp-16-u8}[sb] */
35025 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexw.w", 24,
35026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35028 /* indexw.w ${Dsp-16-u16}[sb] */
35030 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexw.w", 32,
35031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35033 /* indexw.w ${Dsp-16-s8}[fb] */
35035 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexw.w", 24,
35036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35038 /* indexw.w ${Dsp-16-s16}[fb] */
35040 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexw.w", 32,
35041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35043 /* indexw.w ${Dsp-16-u16} */
35045 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexw.w", 32,
35046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35048 /* indexw.w ${Dsp-16-u24} */
35050 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexw.w", 40,
35051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35053 /* indexw.b $Dst32RnUnprefixedQI */
35055 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexw.b", 16,
35056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35058 /* indexw.b $Dst32AnUnprefixedQI */
35060 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexw.b", 16,
35061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35063 /* indexw.b [$Dst32AnUnprefixed] */
35065 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexw.b", 16,
35066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35068 /* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35070 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexw.b", 24,
35071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35073 /* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35075 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexw.b", 32,
35076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35078 /* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35080 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexw.b", 40,
35081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35083 /* indexw.b ${Dsp-16-u8}[sb] */
35085 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexw.b", 24,
35086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35088 /* indexw.b ${Dsp-16-u16}[sb] */
35090 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexw.b", 32,
35091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35093 /* indexw.b ${Dsp-16-s8}[fb] */
35095 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexw.b", 24,
35096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35098 /* indexw.b ${Dsp-16-s16}[fb] */
35100 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexw.b", 32,
35101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35103 /* indexw.b ${Dsp-16-u16} */
35105 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexw.b", 32,
35106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35108 /* indexw.b ${Dsp-16-u24} */
35110 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexw.b", 40,
35111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35113 /* indexls.w $Dst32RnUnprefixedHI */
35115 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexls.w", 16,
35116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35118 /* indexls.w $Dst32AnUnprefixedHI */
35120 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexls.w", 16,
35121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35123 /* indexls.w [$Dst32AnUnprefixed] */
35125 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexls.w", 16,
35126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35128 /* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35130 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexls.w", 24,
35131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35133 /* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35135 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexls.w", 32,
35136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35138 /* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35140 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexls.w", 40,
35141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35143 /* indexls.w ${Dsp-16-u8}[sb] */
35145 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexls.w", 24,
35146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35148 /* indexls.w ${Dsp-16-u16}[sb] */
35150 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexls.w", 32,
35151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35153 /* indexls.w ${Dsp-16-s8}[fb] */
35155 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexls.w", 24,
35156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35158 /* indexls.w ${Dsp-16-s16}[fb] */
35160 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexls.w", 32,
35161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35163 /* indexls.w ${Dsp-16-u16} */
35165 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexls.w", 32,
35166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35168 /* indexls.w ${Dsp-16-u24} */
35170 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexls.w", 40,
35171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35173 /* indexls.b $Dst32RnUnprefixedQI */
35175 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexls.b", 16,
35176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35178 /* indexls.b $Dst32AnUnprefixedQI */
35180 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexls.b", 16,
35181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35183 /* indexls.b [$Dst32AnUnprefixed] */
35185 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexls.b", 16,
35186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35188 /* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35190 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexls.b", 24,
35191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35193 /* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35195 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexls.b", 32,
35196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35198 /* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35200 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexls.b", 40,
35201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35203 /* indexls.b ${Dsp-16-u8}[sb] */
35205 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexls.b", 24,
35206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35208 /* indexls.b ${Dsp-16-u16}[sb] */
35210 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexls.b", 32,
35211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35213 /* indexls.b ${Dsp-16-s8}[fb] */
35215 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexls.b", 24,
35216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35218 /* indexls.b ${Dsp-16-s16}[fb] */
35220 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexls.b", 32,
35221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35223 /* indexls.b ${Dsp-16-u16} */
35225 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexls.b", 32,
35226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35228 /* indexls.b ${Dsp-16-u24} */
35230 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexls.b", 40,
35231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35233 /* indexld.w $Dst32RnUnprefixedHI */
35235 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexld.w", 16,
35236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35238 /* indexld.w $Dst32AnUnprefixedHI */
35240 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexld.w", 16,
35241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35243 /* indexld.w [$Dst32AnUnprefixed] */
35245 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexld.w", 16,
35246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35248 /* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35250 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexld.w", 24,
35251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35253 /* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35255 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexld.w", 32,
35256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35258 /* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35260 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexld.w", 40,
35261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35263 /* indexld.w ${Dsp-16-u8}[sb] */
35265 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexld.w", 24,
35266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35268 /* indexld.w ${Dsp-16-u16}[sb] */
35270 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexld.w", 32,
35271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35273 /* indexld.w ${Dsp-16-s8}[fb] */
35275 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexld.w", 24,
35276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35278 /* indexld.w ${Dsp-16-s16}[fb] */
35280 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexld.w", 32,
35281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35283 /* indexld.w ${Dsp-16-u16} */
35285 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexld.w", 32,
35286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35288 /* indexld.w ${Dsp-16-u24} */
35290 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexld.w", 40,
35291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35293 /* indexld.b $Dst32RnUnprefixedQI */
35295 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexld.b", 16,
35296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35298 /* indexld.b $Dst32AnUnprefixedQI */
35300 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexld.b", 16,
35301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35303 /* indexld.b [$Dst32AnUnprefixed] */
35305 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexld.b", 16,
35306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35308 /* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35310 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexld.b", 24,
35311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35313 /* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35315 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexld.b", 32,
35316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35318 /* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35320 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexld.b", 40,
35321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35323 /* indexld.b ${Dsp-16-u8}[sb] */
35325 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexld.b", 24,
35326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35328 /* indexld.b ${Dsp-16-u16}[sb] */
35330 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexld.b", 32,
35331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35333 /* indexld.b ${Dsp-16-s8}[fb] */
35335 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexld.b", 24,
35336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35338 /* indexld.b ${Dsp-16-s16}[fb] */
35340 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexld.b", 32,
35341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35343 /* indexld.b ${Dsp-16-u16} */
35345 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexld.b", 32,
35346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35348 /* indexld.b ${Dsp-16-u24} */
35350 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexld.b", 40,
35351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35353 /* indexl.w $Dst32RnUnprefixedHI */
35355 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexl.w", 16,
35356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35358 /* indexl.w $Dst32AnUnprefixedHI */
35360 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexl.w", 16,
35361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35363 /* indexl.w [$Dst32AnUnprefixed] */
35365 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexl.w", 16,
35366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35368 /* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35370 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexl.w", 24,
35371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35373 /* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35375 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexl.w", 32,
35376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35378 /* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35380 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexl.w", 40,
35381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35383 /* indexl.w ${Dsp-16-u8}[sb] */
35385 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexl.w", 24,
35386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35388 /* indexl.w ${Dsp-16-u16}[sb] */
35390 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexl.w", 32,
35391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35393 /* indexl.w ${Dsp-16-s8}[fb] */
35395 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexl.w", 24,
35396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35398 /* indexl.w ${Dsp-16-s16}[fb] */
35400 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexl.w", 32,
35401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35403 /* indexl.w ${Dsp-16-u16} */
35405 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexl.w", 32,
35406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35408 /* indexl.w ${Dsp-16-u24} */
35410 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexl.w", 40,
35411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35413 /* indexl.b $Dst32RnUnprefixedQI */
35415 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexl.b", 16,
35416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35418 /* indexl.b $Dst32AnUnprefixedQI */
35420 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexl.b", 16,
35421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35423 /* indexl.b [$Dst32AnUnprefixed] */
35425 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexl.b", 16,
35426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35428 /* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35430 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexl.b", 24,
35431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35433 /* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35435 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexl.b", 32,
35436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35438 /* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35440 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexl.b", 40,
35441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35443 /* indexl.b ${Dsp-16-u8}[sb] */
35445 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexl.b", 24,
35446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35448 /* indexl.b ${Dsp-16-u16}[sb] */
35450 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexl.b", 32,
35451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35453 /* indexl.b ${Dsp-16-s8}[fb] */
35455 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexl.b", 24,
35456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35458 /* indexl.b ${Dsp-16-s16}[fb] */
35460 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexl.b", 32,
35461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35463 /* indexl.b ${Dsp-16-u16} */
35465 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexl.b", 32,
35466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35468 /* indexl.b ${Dsp-16-u24} */
35470 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexl.b", 40,
35471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35473 /* indexbs.w $Dst32RnUnprefixedHI */
35475 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbs.w", 16,
35476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35478 /* indexbs.w $Dst32AnUnprefixedHI */
35480 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbs.w", 16,
35481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35483 /* indexbs.w [$Dst32AnUnprefixed] */
35485 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbs.w", 16,
35486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35488 /* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35490 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbs.w", 24,
35491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35493 /* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35495 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbs.w", 32,
35496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35498 /* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35500 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbs.w", 40,
35501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35503 /* indexbs.w ${Dsp-16-u8}[sb] */
35505 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbs.w", 24,
35506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35508 /* indexbs.w ${Dsp-16-u16}[sb] */
35510 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbs.w", 32,
35511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35513 /* indexbs.w ${Dsp-16-s8}[fb] */
35515 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbs.w", 24,
35516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35518 /* indexbs.w ${Dsp-16-s16}[fb] */
35520 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbs.w", 32,
35521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35523 /* indexbs.w ${Dsp-16-u16} */
35525 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbs.w", 32,
35526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35528 /* indexbs.w ${Dsp-16-u24} */
35530 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbs.w", 40,
35531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35533 /* indexbs.b $Dst32RnUnprefixedQI */
35535 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbs.b", 16,
35536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35538 /* indexbs.b $Dst32AnUnprefixedQI */
35540 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbs.b", 16,
35541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35543 /* indexbs.b [$Dst32AnUnprefixed] */
35545 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbs.b", 16,
35546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35548 /* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35550 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbs.b", 24,
35551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35553 /* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35555 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbs.b", 32,
35556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35558 /* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35560 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbs.b", 40,
35561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35563 /* indexbs.b ${Dsp-16-u8}[sb] */
35565 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbs.b", 24,
35566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35568 /* indexbs.b ${Dsp-16-u16}[sb] */
35570 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbs.b", 32,
35571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35573 /* indexbs.b ${Dsp-16-s8}[fb] */
35575 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbs.b", 24,
35576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35578 /* indexbs.b ${Dsp-16-s16}[fb] */
35580 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbs.b", 32,
35581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35583 /* indexbs.b ${Dsp-16-u16} */
35585 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbs.b", 32,
35586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35588 /* indexbs.b ${Dsp-16-u24} */
35590 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbs.b", 40,
35591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35593 /* indexbd.w $Dst32RnUnprefixedHI */
35595 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbd.w", 16,
35596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35598 /* indexbd.w $Dst32AnUnprefixedHI */
35600 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbd.w", 16,
35601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35603 /* indexbd.w [$Dst32AnUnprefixed] */
35605 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbd.w", 16,
35606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35608 /* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35610 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbd.w", 24,
35611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35613 /* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35615 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbd.w", 32,
35616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35618 /* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35620 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbd.w", 40,
35621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35623 /* indexbd.w ${Dsp-16-u8}[sb] */
35625 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbd.w", 24,
35626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35628 /* indexbd.w ${Dsp-16-u16}[sb] */
35630 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbd.w", 32,
35631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35633 /* indexbd.w ${Dsp-16-s8}[fb] */
35635 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbd.w", 24,
35636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35638 /* indexbd.w ${Dsp-16-s16}[fb] */
35640 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbd.w", 32,
35641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35643 /* indexbd.w ${Dsp-16-u16} */
35645 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbd.w", 32,
35646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35648 /* indexbd.w ${Dsp-16-u24} */
35650 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbd.w", 40,
35651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35653 /* indexbd.b $Dst32RnUnprefixedQI */
35655 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbd.b", 16,
35656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35658 /* indexbd.b $Dst32AnUnprefixedQI */
35660 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbd.b", 16,
35661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35663 /* indexbd.b [$Dst32AnUnprefixed] */
35665 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbd.b", 16,
35666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35668 /* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35670 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbd.b", 24,
35671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35673 /* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35675 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbd.b", 32,
35676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35678 /* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35680 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbd.b", 40,
35681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35683 /* indexbd.b ${Dsp-16-u8}[sb] */
35685 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbd.b", 24,
35686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35688 /* indexbd.b ${Dsp-16-u16}[sb] */
35690 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbd.b", 32,
35691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35693 /* indexbd.b ${Dsp-16-s8}[fb] */
35695 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbd.b", 24,
35696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35698 /* indexbd.b ${Dsp-16-s16}[fb] */
35700 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbd.b", 32,
35701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35703 /* indexbd.b ${Dsp-16-u16} */
35705 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbd.b", 32,
35706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35708 /* indexbd.b ${Dsp-16-u24} */
35710 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbd.b", 40,
35711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35713 /* indexb.w $Dst32RnUnprefixedHI */
35715 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexb.w", 16,
35716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35718 /* indexb.w $Dst32AnUnprefixedHI */
35720 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexb.w", 16,
35721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35723 /* indexb.w [$Dst32AnUnprefixed] */
35725 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexb.w", 16,
35726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35728 /* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35730 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexb.w", 24,
35731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35733 /* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35735 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexb.w", 32,
35736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35738 /* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35740 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexb.w", 40,
35741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35743 /* indexb.w ${Dsp-16-u8}[sb] */
35745 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexb.w", 24,
35746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35748 /* indexb.w ${Dsp-16-u16}[sb] */
35750 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexb.w", 32,
35751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35753 /* indexb.w ${Dsp-16-s8}[fb] */
35755 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexb.w", 24,
35756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35758 /* indexb.w ${Dsp-16-s16}[fb] */
35760 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexb.w", 32,
35761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35763 /* indexb.w ${Dsp-16-u16} */
35765 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexb.w", 32,
35766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35768 /* indexb.w ${Dsp-16-u24} */
35770 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexb.w", 40,
35771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35773 /* indexb.b $Dst32RnUnprefixedQI */
35775 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexb.b", 16,
35776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35778 /* indexb.b $Dst32AnUnprefixedQI */
35780 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexb.b", 16,
35781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35783 /* indexb.b [$Dst32AnUnprefixed] */
35785 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexb.b", 16,
35786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35788 /* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35790 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexb.b", 24,
35791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35793 /* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35795 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexb.b", 32,
35796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35798 /* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35800 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexb.b", 40,
35801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35803 /* indexb.b ${Dsp-16-u8}[sb] */
35805 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexb.b", 24,
35806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35808 /* indexb.b ${Dsp-16-u16}[sb] */
35810 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexb.b", 32,
35811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35813 /* indexb.b ${Dsp-16-s8}[fb] */
35815 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexb.b", 24,
35816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35818 /* indexb.b ${Dsp-16-s16}[fb] */
35820 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexb.b", 32,
35821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35823 /* indexb.b ${Dsp-16-u16} */
35825 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexb.b", 32,
35826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35828 /* indexb.b ${Dsp-16-u24} */
35830 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexb.b", 40,
35831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35833 /* inc.w $Dst32RnUnprefixedHI */
35835 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "inc.w", 16,
35836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35838 /* inc.w $Dst32AnUnprefixedHI */
35840 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "inc.w", 16,
35841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35843 /* inc.w [$Dst32AnUnprefixed] */
35845 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "inc.w", 16,
35846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35848 /* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35850 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "inc.w", 24,
35851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35853 /* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35855 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "inc.w", 32,
35856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35858 /* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35860 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "inc.w", 40,
35861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35863 /* inc.w ${Dsp-16-u8}[sb] */
35865 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "inc.w", 24,
35866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35868 /* inc.w ${Dsp-16-u16}[sb] */
35870 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "inc.w", 32,
35871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35873 /* inc.w ${Dsp-16-s8}[fb] */
35875 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "inc.w", 24,
35876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35878 /* inc.w ${Dsp-16-s16}[fb] */
35880 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "inc.w", 32,
35881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35883 /* inc.w ${Dsp-16-u16} */
35885 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "inc.w", 32,
35886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35888 /* inc.w ${Dsp-16-u24} */
35890 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "inc.w", 40,
35891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35893 /* inc.b $Dst32RnUnprefixedQI */
35895 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "inc.b", 16,
35896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35898 /* inc.b $Dst32AnUnprefixedQI */
35900 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "inc.b", 16,
35901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35903 /* inc.b [$Dst32AnUnprefixed] */
35905 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "inc.b", 16,
35906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35908 /* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35910 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "inc.b", 24,
35911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35913 /* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35915 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "inc.b", 32,
35916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35918 /* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35920 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "inc.b", 40,
35921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35923 /* inc.b ${Dsp-16-u8}[sb] */
35925 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "inc.b", 24,
35926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35928 /* inc.b ${Dsp-16-u16}[sb] */
35930 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "inc.b", 32,
35931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35933 /* inc.b ${Dsp-16-s8}[fb] */
35935 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "inc.b", 24,
35936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35938 /* inc.b ${Dsp-16-s16}[fb] */
35940 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "inc.b", 32,
35941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35943 /* inc.b ${Dsp-16-u16} */
35945 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "inc.b", 32,
35946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35948 /* inc.b ${Dsp-16-u24} */
35950 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "inc.b", 40,
35951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35953 /* inc.b r0l */
35955 M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, "inc16.b-dst16-3-S-R0l-direct-QI", "inc.b", 8,
35956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
35958 /* inc.b r0h */
35960 M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, "inc16.b-dst16-3-S-R0h-direct-QI", "inc.b", 8,
35961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
35963 /* inc.b ${Dsp-8-u8}[sb] */
35965 M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-SB-relative-QI", "inc.b", 16,
35966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
35968 /* inc.b ${Dsp-8-s8}[fb] */
35970 M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-FB-relative-QI", "inc.b", 16,
35971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
35973 /* inc.b ${Dsp-8-u16} */
35975 M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "inc16.b-dst16-3-S-8-16-absolute-QI", "inc.b", 24,
35976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
35978 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
35980 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35983 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
35985 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35988 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
35990 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35993 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
35995 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
35998 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
36000 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
36001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36003 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
36005 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
36006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36008 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36010 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
36011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36013 /* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36015 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
36016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36018 /* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36020 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
36021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36023 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36025 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
36026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36028 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36030 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
36031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36033 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36035 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
36036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36038 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36040 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
36041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36043 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36045 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
36046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36048 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36050 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
36051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36053 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36055 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
36056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36058 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36060 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
36061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36063 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36065 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
36066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36068 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36070 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
36071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36073 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36075 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
36076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36078 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36080 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
36081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36083 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36085 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
36086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36088 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36090 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
36091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36093 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36095 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
36096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36098 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36100 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
36101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36103 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36105 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
36106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36108 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36110 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
36111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36113 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36115 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
36116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36118 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36120 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
36121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36123 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36125 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
36126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36128 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36130 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
36131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36133 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36135 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
36136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36138 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36140 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
36141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36143 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36145 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
36146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36148 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36150 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
36151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36153 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36155 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
36156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36158 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36160 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36163 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
36165 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36168 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
36170 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36173 /* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
36175 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36178 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36180 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36183 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
36185 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36188 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
36190 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36193 /* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
36195 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36198 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36200 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36203 /* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
36205 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36208 /* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
36210 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36213 /* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
36215 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36218 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36220 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36223 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36225 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36228 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36230 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36233 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
36235 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36238 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36240 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36243 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36245 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36248 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36250 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36253 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
36255 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36258 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36260 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36263 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36265 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36268 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36270 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36273 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
36275 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36278 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
36280 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36283 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
36285 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36288 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
36290 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36293 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
36295 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36298 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
36300 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36303 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
36305 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36308 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
36310 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36313 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
36315 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36318 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
36320 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36323 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
36325 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36328 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
36330 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36333 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
36335 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36338 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
36340 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36343 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
36345 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36348 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
36350 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36353 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
36355 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36358 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
36360 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36363 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
36365 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36368 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
36370 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36373 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
36375 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36378 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
36380 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36383 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
36385 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36388 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
36390 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36393 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
36395 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36398 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36400 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
36401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36403 /* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
36405 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
36406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36408 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36410 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
36411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36413 /* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
36415 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
36416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36418 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36420 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
36421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36423 /* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
36425 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
36426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36428 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
36430 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
36431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36433 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
36435 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
36436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36438 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
36440 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
36441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36443 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
36445 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
36446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36448 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
36450 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
36451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36453 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
36455 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
36456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36458 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
36460 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
36461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36463 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
36465 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
36466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36468 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
36470 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
36471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36473 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
36475 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
36476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36478 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
36480 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
36481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36483 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
36485 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
36486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36488 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
36490 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
36491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36493 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
36495 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
36496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36498 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
36500 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
36501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36503 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
36505 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
36506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36508 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
36510 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
36511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36513 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
36515 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
36516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36518 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
36520 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36523 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
36525 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36528 /* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36530 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36533 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
36535 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36538 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
36540 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36543 /* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36545 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36548 /* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
36550 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36553 /* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
36555 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36558 /* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36560 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36563 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36565 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36568 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36570 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36573 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
36575 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36578 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36580 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36583 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36585 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36588 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
36590 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36593 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36595 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36598 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36600 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36603 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
36605 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36608 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
36610 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36613 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
36615 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36618 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
36620 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36623 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
36625 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36628 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
36630 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36633 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
36635 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36638 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
36640 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36643 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
36645 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36648 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
36650 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36653 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
36655 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36658 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
36660 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36663 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
36665 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36668 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
36670 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36673 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
36675 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36678 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
36680 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36683 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
36685 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36688 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
36690 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36693 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
36695 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36698 /* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
36700 M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "sub.w", 32,
36701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36703 /* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
36705 M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "sub.w", 32,
36706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36708 /* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
36710 M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "sub32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "sub.w", 40,
36711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36713 /* sub.w${S} #${Imm-8-HI},r0 */
36715 M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "sub32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "sub.w", 24,
36716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36718 /* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
36720 M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "sub.b", 24,
36721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36723 /* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
36725 M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "sub.b", 24,
36726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36728 /* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
36730 M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "sub32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "sub.b", 32,
36731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36733 /* sub.b${S} #${Imm-8-QI},r0l */
36735 M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "sub32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "sub.b", 16,
36736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36738 /* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
36740 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sub.l", 48,
36741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36743 /* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
36745 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sub.l", 48,
36746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36748 /* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
36750 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sub.l", 48,
36751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36753 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
36755 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 56,
36756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36758 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
36760 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 56,
36761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36763 /* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
36765 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 56,
36766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36768 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
36770 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 64,
36771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36773 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
36775 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 64,
36776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36778 /* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
36780 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 64,
36781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36783 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
36785 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 64,
36786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36788 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
36790 M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 72,
36791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36793 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
36795 M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 72,
36796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36798 /* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
36800 M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "sub16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "sub.b", 8,
36801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
36803 /* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
36805 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-SB-relative-QI", "sub.b", 16,
36806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
36808 /* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
36810 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-FB-relative-QI", "sub.b", 16,
36811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
36813 /* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
36815 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "sub16.b.S-src2-src16-2-S-16-absolute-QI", "sub.b", 24,
36816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
36818 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36820 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36823 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
36825 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36828 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
36830 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36833 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
36835 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36838 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
36840 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36843 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
36845 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36848 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36850 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36853 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36855 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36858 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36860 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36863 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36865 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36868 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36870 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36873 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36875 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36878 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36880 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36883 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36885 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36888 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36890 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36893 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36895 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36898 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36900 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36903 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36905 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36908 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36910 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36913 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36915 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36918 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36920 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36923 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36925 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36928 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36930 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36933 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36935 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36938 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36940 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36943 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36945 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36948 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36950 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36953 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36955 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36958 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36960 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36963 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36965 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36968 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36970 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36973 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36975 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36978 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36980 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36983 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36985 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36988 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36990 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36993 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36995 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
36998 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37000 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
37001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37003 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
37005 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
37006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37008 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
37010 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
37011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37013 /* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
37015 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
37016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37018 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37020 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
37021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37023 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
37025 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
37026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37028 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
37030 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
37031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37033 /* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
37035 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
37036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37038 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37040 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37043 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37045 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37048 /* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37050 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37053 /* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37055 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37058 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37060 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37063 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37065 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37068 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37070 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37073 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37075 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37078 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37080 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37083 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37085 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37088 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37090 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37093 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37095 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37098 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37100 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37103 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37105 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37108 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37110 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37113 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37115 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37118 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37120 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37123 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37125 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37128 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37130 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37133 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37135 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37138 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37140 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37143 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37145 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37148 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37150 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37153 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37155 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37158 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37160 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37163 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37165 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37168 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37170 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37173 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37175 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37178 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37180 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37183 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37185 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37188 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37190 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37193 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37195 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37198 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37200 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37203 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37205 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37208 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37210 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37213 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
37215 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37218 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37220 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37223 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37225 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37228 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37230 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37233 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
37235 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37238 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37240 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
37241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37243 /* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
37245 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
37246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37248 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37250 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
37251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37253 /* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
37255 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
37256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37258 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37260 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
37261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37263 /* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37265 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
37266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37268 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37270 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
37271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37273 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37275 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
37276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37278 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37280 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
37281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37283 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37285 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
37286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37288 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37290 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
37291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37293 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37295 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
37296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37298 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
37300 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
37301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37303 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
37305 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
37306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37308 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
37310 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
37311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37313 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
37315 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
37316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37318 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
37320 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
37321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37323 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
37325 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
37326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37328 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
37330 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
37331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37333 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
37335 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
37336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37338 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
37340 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
37341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37343 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
37345 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
37346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37348 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
37350 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
37351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37353 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
37355 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
37356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37358 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
37360 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
37361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37363 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
37365 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
37366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37368 /* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37370 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
37371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37373 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
37375 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
37376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37378 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
37380 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
37381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37383 /* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37385 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
37386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37388 /* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
37390 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
37391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37393 /* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
37395 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
37396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37398 /* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37400 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
37401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37403 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37405 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37408 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37410 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37413 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37415 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37418 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37420 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37423 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37425 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37428 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37430 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37433 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37435 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37438 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37440 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37443 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
37445 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37448 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
37450 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37453 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
37455 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37458 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
37460 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37463 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
37465 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37468 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
37470 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37473 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
37475 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37478 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
37480 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37483 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
37485 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37488 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
37490 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37493 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
37495 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37498 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
37500 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37503 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
37505 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37508 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
37510 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37513 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
37515 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37518 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
37520 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37523 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
37525 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37528 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
37530 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37533 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
37535 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37538 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37540 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37543 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
37545 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37548 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
37550 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37553 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37555 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37558 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
37560 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37563 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
37565 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37568 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37570 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37573 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
37575 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37578 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
37580 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37583 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37585 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37588 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37590 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37593 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37595 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37598 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37600 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37603 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37605 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37608 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37610 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37613 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37615 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37618 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37620 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37623 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37625 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37628 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
37630 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37633 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
37635 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37638 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
37640 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37643 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
37645 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37648 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
37650 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37653 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
37655 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37658 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
37660 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37663 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
37665 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37668 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
37670 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37673 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
37675 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37678 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
37680 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37683 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
37685 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37688 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
37690 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37693 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
37695 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37698 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
37700 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37703 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
37705 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37708 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
37710 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37713 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
37715 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37718 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37720 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37723 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
37725 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37728 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
37730 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37733 /* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
37735 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37738 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37740 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37743 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
37745 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37748 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
37750 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37753 /* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
37755 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37758 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37760 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37763 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37765 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37768 /* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37770 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37773 /* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37775 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37778 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37780 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37783 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37785 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37788 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37790 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37793 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37795 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37798 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37800 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37803 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37805 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37808 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37810 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37813 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37815 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37818 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37820 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37823 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37825 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37828 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37830 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37833 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37835 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37838 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37840 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37843 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37845 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37848 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37850 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37853 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37855 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37858 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37860 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37863 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37865 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37868 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37870 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37873 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37875 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37878 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37880 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37883 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37885 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37888 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37890 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37893 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37895 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37898 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37900 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37903 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37905 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37908 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37910 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37913 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37915 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37918 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37920 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37923 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37925 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37928 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37930 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37933 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
37935 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37938 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37940 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37943 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37945 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37948 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37950 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37953 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
37955 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37958 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37960 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
37961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37963 /* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
37965 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
37966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37968 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37970 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
37971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37973 /* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
37975 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
37976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37978 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37980 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
37981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37983 /* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37985 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
37986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37988 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37990 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
37991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37993 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37995 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
37996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
37998 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
38000 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
38001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38003 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
38005 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
38006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38008 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
38010 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
38011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38013 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
38015 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
38016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38018 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
38020 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
38021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38023 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
38025 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
38026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38028 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
38030 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
38031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38033 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
38035 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
38036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38038 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
38040 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
38041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38043 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
38045 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
38046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38048 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
38050 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
38051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38053 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
38055 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
38056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38058 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
38060 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
38061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38063 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
38065 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
38066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38068 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
38070 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
38071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38073 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
38075 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
38076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38078 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
38080 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
38081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38083 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
38085 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
38086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38088 /* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38090 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
38091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38093 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
38095 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
38096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38098 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
38100 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
38101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38103 /* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38105 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
38106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38108 /* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
38110 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
38111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38113 /* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
38115 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
38116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38118 /* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38120 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
38121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38123 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38125 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
38126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38128 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38130 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
38131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38133 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
38135 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
38136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38138 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38140 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
38141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38143 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38145 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
38146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38148 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
38150 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
38151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38153 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38155 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
38156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38158 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38160 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
38161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38163 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
38165 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
38166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38168 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
38170 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
38171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38173 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
38175 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
38176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38178 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
38180 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
38181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38183 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
38185 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
38186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38188 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
38190 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
38191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38193 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
38195 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
38196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38198 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
38200 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
38201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38203 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
38205 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
38206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38208 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
38210 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
38211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38213 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
38215 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
38216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38218 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
38220 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
38221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38223 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
38225 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
38226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38228 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
38230 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
38231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38233 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
38235 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
38236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38238 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
38240 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
38241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38243 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
38245 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
38246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38248 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
38250 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
38251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38253 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
38255 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
38256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
38258 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
38260 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
38261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38263 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
38265 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
38266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38268 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
38270 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
38271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38273 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
38275 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sub.w", 24,
38276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38278 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
38280 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
38281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38283 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
38285 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
38286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38288 /* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
38290 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
38291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38293 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
38295 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
38296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38298 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
38300 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
38301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38303 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
38305 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
38306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38308 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
38310 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
38311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38313 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
38315 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
38316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38318 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
38320 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
38321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38323 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
38325 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
38326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38328 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
38330 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
38331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38333 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
38335 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
38336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38338 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38340 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
38341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38343 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38345 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
38346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38348 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
38350 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
38351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38353 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38355 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
38356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38358 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38360 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
38361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38363 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
38365 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
38366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38368 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38370 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
38371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38373 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38375 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
38376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38378 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
38380 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
38381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38383 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38385 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
38386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38388 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38390 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
38391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38393 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
38395 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
38396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38398 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
38400 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
38401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38403 /* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
38405 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sub.w", 32,
38406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38408 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
38410 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sub.w", 32,
38411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38413 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
38415 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sub.w", 32,
38416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38418 /* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
38420 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sub.w", 32,
38421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38423 /* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38425 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
38426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38428 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38430 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
38431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38433 /* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
38435 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sub.w", 32,
38436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38438 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38440 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38443 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38445 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38448 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38450 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38453 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38455 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38458 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38460 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38463 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38465 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38468 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38470 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38473 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38475 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38478 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38480 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38483 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38485 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38488 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38490 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38493 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38495 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38498 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38500 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38503 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38505 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38508 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38510 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38513 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38515 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38518 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38520 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38523 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
38525 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38528 /* sub.w${G} $Src16RnHI,$Dst16RnHI */
38530 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
38531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38533 /* sub.w${G} $Src16AnHI,$Dst16RnHI */
38535 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
38536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38538 /* sub.w${G} [$Src16An],$Dst16RnHI */
38540 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sub.w", 16,
38541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38543 /* sub.w${G} $Src16RnHI,$Dst16AnHI */
38545 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sub.w", 16,
38546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38548 /* sub.w${G} $Src16AnHI,$Dst16AnHI */
38550 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sub.w", 16,
38551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38553 /* sub.w${G} [$Src16An],$Dst16AnHI */
38555 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sub.w", 16,
38556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38558 /* sub.w${G} $Src16RnHI,[$Dst16An] */
38560 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
38561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38563 /* sub.w${G} $Src16AnHI,[$Dst16An] */
38565 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
38566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38568 /* sub.w${G} [$Src16An],[$Dst16An] */
38570 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sub.w", 16,
38571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38573 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
38575 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38578 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
38580 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38583 /* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
38585 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38588 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
38590 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38593 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
38595 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38598 /* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
38600 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38603 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
38605 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38608 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
38610 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38613 /* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
38615 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38618 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
38620 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38623 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
38625 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38628 /* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
38630 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38633 /* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
38635 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38638 /* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
38640 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38643 /* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
38645 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38648 /* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
38650 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38653 /* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
38655 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38658 /* sub.w${G} [$Src16An],${Dsp-16-u16} */
38660 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38663 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
38665 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38668 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
38670 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38673 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
38675 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38678 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
38680 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38683 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
38685 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38688 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
38690 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38693 /* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
38695 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38698 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
38700 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38703 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
38705 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38708 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
38710 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38713 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
38715 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38718 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
38720 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38723 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
38725 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38728 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
38730 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38733 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
38735 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38738 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
38740 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38743 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38745 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38748 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38750 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38753 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
38755 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38758 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38760 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38763 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38765 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38768 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
38770 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38773 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38775 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38778 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38780 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38783 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
38785 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38788 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38790 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38793 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38795 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38798 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
38800 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
38801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38803 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
38805 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
38806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38808 /* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
38810 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sub.b", 32,
38811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38813 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
38815 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sub.b", 32,
38816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38818 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
38820 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sub.b", 32,
38821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38823 /* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
38825 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sub.b", 32,
38826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38828 /* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38830 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
38831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38833 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38835 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
38836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38838 /* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
38840 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sub.b", 32,
38841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38843 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38845 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38848 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38850 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38853 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38855 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38858 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38860 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38863 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38865 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38868 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38870 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38873 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38875 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38878 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38880 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38883 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38885 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38888 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38890 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38893 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38895 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38898 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38900 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38903 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38905 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38908 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38910 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38913 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38915 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38918 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38920 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38923 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38925 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38928 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
38930 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38933 /* sub.b${G} $Src16RnQI,$Dst16RnQI */
38935 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
38936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38938 /* sub.b${G} $Src16AnQI,$Dst16RnQI */
38940 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
38941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38943 /* sub.b${G} [$Src16An],$Dst16RnQI */
38945 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sub.b", 16,
38946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38948 /* sub.b${G} $Src16RnQI,$Dst16AnQI */
38950 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sub.b", 16,
38951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38953 /* sub.b${G} $Src16AnQI,$Dst16AnQI */
38955 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sub.b", 16,
38956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38958 /* sub.b${G} [$Src16An],$Dst16AnQI */
38960 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sub.b", 16,
38961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38963 /* sub.b${G} $Src16RnQI,[$Dst16An] */
38965 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
38966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38968 /* sub.b${G} $Src16AnQI,[$Dst16An] */
38970 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
38971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38973 /* sub.b${G} [$Src16An],[$Dst16An] */
38975 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sub.b", 16,
38976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38978 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
38980 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38983 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
38985 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38988 /* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
38990 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38993 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
38995 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
38998 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
39000 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
39001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39003 /* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
39005 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
39006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39008 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
39010 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
39011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39013 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
39015 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
39016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39018 /* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
39020 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
39021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39023 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
39025 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
39026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39028 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
39030 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
39031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39033 /* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
39035 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
39036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39038 /* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
39040 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
39041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39043 /* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
39045 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
39046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39048 /* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
39050 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
39051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39053 /* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
39055 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
39056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39058 /* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
39060 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
39061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39063 /* sub.b${G} [$Src16An],${Dsp-16-u16} */
39065 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sub.b", 32,
39066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39068 /* sub.b${S} #${Imm-8-QI},r0l */
39070 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "sub.b", 16,
39071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39073 /* sub.b${S} #${Imm-8-QI},r0h */
39075 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "sub.b", 16,
39076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39078 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
39080 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "sub.b", 24,
39081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39083 /* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
39085 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "sub.b", 24,
39086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39088 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
39090 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "sub.b", 32,
39091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39093 /* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
39095 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
39096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39098 /* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
39100 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
39101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39103 /* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
39105 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
39106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39108 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
39110 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 40,
39111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39113 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
39115 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 40,
39116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39118 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
39120 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 40,
39121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39123 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
39125 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 48,
39126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39128 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
39130 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 48,
39131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39133 /* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
39135 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 48,
39136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39138 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
39140 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 48,
39141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39143 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
39145 M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 56,
39146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39148 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
39150 M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 56,
39151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39153 /* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
39155 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
39156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39158 /* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
39160 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
39161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39163 /* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
39165 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
39166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39168 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
39170 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 32,
39171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39173 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
39175 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 32,
39176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39178 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
39180 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 32,
39181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39183 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
39185 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 40,
39186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39188 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
39190 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 40,
39191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39193 /* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
39195 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 40,
39196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39198 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
39200 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 40,
39201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39203 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
39205 M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 48,
39206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39208 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
39210 M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 48,
39211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39213 /* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
39215 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-Rn-direct-HI", "sub.w", 32,
39216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39218 /* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
39220 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-An-direct-HI", "sub.w", 32,
39221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39223 /* sub.w${G} #${Imm-16-HI},[$Dst16An] */
39225 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sub16.w-imm-G-basic-dst16-An-indirect-HI", "sub.w", 32,
39226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39228 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
39230 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sub.w", 40,
39231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39233 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
39235 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sub.w", 40,
39236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39238 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
39240 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sub.w", 40,
39241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39243 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
39245 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sub.w", 48,
39246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39248 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
39250 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sub.w", 48,
39251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39253 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
39255 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sub16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sub.w", 48,
39256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39258 /* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
39260 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-Rn-direct-QI", "sub.b", 24,
39261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39263 /* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
39265 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-An-direct-QI", "sub.b", 24,
39266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39268 /* sub.b${G} #${Imm-16-QI},[$Dst16An] */
39270 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sub16.b-imm-G-basic-dst16-An-indirect-QI", "sub.b", 24,
39271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39273 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
39275 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sub.b", 32,
39276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39278 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
39280 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sub.b", 32,
39281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39283 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
39285 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sub.b", 32,
39286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39288 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
39290 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sub.b", 40,
39291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39293 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
39295 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sub.b", 40,
39296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39298 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
39300 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sub16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sub.b", 40,
39301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
39303 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39305 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
39306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39308 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
39310 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
39311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39313 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
39315 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
39316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39318 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39320 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
39321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39323 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
39325 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
39326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39328 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
39330 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
39331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39333 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39335 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
39336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39338 /* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
39340 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
39341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39343 /* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
39345 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
39346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39348 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
39350 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
39351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39353 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39355 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
39356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39358 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39360 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
39361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39363 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
39365 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
39366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39368 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39370 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
39371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39373 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39375 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
39376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39378 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
39380 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
39381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39383 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39385 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
39386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39388 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39390 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
39391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39393 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
39395 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39398 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
39400 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39403 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
39405 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39408 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
39410 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39413 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
39415 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39418 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
39420 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39423 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
39425 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39428 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
39430 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39433 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
39435 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39438 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
39440 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39443 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
39445 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39448 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
39450 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39453 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
39455 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39458 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
39460 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39463 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
39465 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39468 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
39470 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39473 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
39475 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39478 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
39480 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39483 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39485 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39488 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
39490 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39493 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
39495 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39498 /* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
39500 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39503 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39505 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39508 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
39510 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39513 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
39515 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39518 /* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
39520 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39523 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39525 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39528 /* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
39530 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39533 /* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
39535 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39538 /* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
39540 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39543 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
39545 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39548 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39550 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39553 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39555 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39558 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
39560 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39563 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
39565 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39568 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39570 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39573 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39575 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39578 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
39580 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39583 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
39585 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39588 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39590 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39593 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39595 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39598 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
39600 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39603 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
39605 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39608 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
39610 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39613 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
39615 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39618 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
39620 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39623 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
39625 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39628 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
39630 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39633 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
39635 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39638 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
39640 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39643 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
39645 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39648 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
39650 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39653 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
39655 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39658 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
39660 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39663 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
39665 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39668 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
39670 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39673 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
39675 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39678 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
39680 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39683 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
39685 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39688 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
39690 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39693 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
39695 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39698 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
39700 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39703 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
39705 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39708 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
39710 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39713 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
39715 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39718 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
39720 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39723 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39725 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
39726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39728 /* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
39730 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
39731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39733 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39735 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
39736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39738 /* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
39740 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
39741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39743 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39745 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
39746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39748 /* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
39750 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
39751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39753 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
39755 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
39756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39758 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
39760 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
39761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39763 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
39765 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
39766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39768 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
39770 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
39771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39773 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
39775 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
39776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39778 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
39780 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
39781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39783 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
39785 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
39786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39788 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
39790 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
39791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39793 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
39795 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
39796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39798 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
39800 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
39801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39803 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
39805 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
39806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39808 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
39810 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
39811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39813 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
39815 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
39816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39818 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
39820 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
39821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39823 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
39825 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
39826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39828 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
39830 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
39831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39833 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
39835 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
39836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39838 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
39840 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
39841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39843 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
39845 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39848 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
39850 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39853 /* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
39855 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39858 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
39860 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39863 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
39865 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39868 /* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
39870 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39873 /* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
39875 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39878 /* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
39880 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39883 /* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
39885 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39888 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39890 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39893 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39895 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39898 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
39900 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39903 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39905 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39908 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39910 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39913 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
39915 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39918 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39920 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39923 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39925 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39928 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
39930 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39933 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
39935 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39938 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
39940 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39943 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
39945 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39948 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
39950 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39953 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
39955 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39958 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
39960 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39963 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
39965 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39968 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
39970 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39973 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
39975 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39978 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
39980 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39983 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
39985 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39988 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
39990 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39993 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
39995 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
39998 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
40000 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
40001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40003 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
40005 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
40006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40008 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
40010 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
40011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40013 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
40015 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
40016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40018 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
40020 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
40021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40023 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40025 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40028 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
40030 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40033 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
40035 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40038 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40040 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40043 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
40045 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40048 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
40050 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40053 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40055 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40058 /* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40060 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40063 /* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40065 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40068 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40070 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
40071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40073 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40075 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
40076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40078 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40080 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
40081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40083 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40085 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
40086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40088 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40090 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
40091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40093 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40095 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
40096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40098 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40100 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
40101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40103 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40105 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
40106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40108 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40110 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
40111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40113 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40115 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40118 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40120 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40123 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40125 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40128 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40130 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40133 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40135 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40138 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40140 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40143 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40145 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40148 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
40150 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40153 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
40155 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40158 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
40160 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40163 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
40165 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40168 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
40170 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40173 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
40175 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
40176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40178 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
40180 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
40181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40183 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
40185 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
40186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40188 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
40190 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
40191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40193 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
40195 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
40196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40198 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
40200 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
40201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40203 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40205 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40208 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
40210 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40213 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
40215 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40218 /* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
40220 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40223 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40225 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40228 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
40230 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40233 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
40235 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40238 /* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
40240 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40243 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40245 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40248 /* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
40250 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40253 /* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
40255 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40258 /* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
40260 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40263 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
40265 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40268 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40270 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40273 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40275 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40278 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
40280 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40283 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
40285 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40288 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40290 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40293 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40295 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40298 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
40300 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40303 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
40305 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40308 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40310 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40313 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40315 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40318 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
40320 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40323 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
40325 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40328 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
40330 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40333 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
40335 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40338 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
40340 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40343 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
40345 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40348 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
40350 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40353 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
40355 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40358 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
40360 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40363 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
40365 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40368 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
40370 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40373 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
40375 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40378 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
40380 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40383 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
40385 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40388 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
40390 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40393 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
40395 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40398 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
40400 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40403 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
40405 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40408 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
40410 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40413 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
40415 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40418 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
40420 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40423 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
40425 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40428 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
40430 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40433 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
40435 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40438 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
40440 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40443 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40445 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
40446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40448 /* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
40450 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
40451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40453 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40455 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
40456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40458 /* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
40460 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
40461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40463 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40465 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
40466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40468 /* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
40470 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
40471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40473 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
40475 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
40476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40478 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
40480 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
40481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40483 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
40485 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
40486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40488 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
40490 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
40491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40493 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
40495 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
40496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40498 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
40500 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
40501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40503 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
40505 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
40506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40508 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
40510 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
40511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40513 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
40515 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
40516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40518 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
40520 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
40521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40523 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
40525 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
40526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40528 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
40530 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
40531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40533 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
40535 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
40536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40538 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
40540 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
40541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40543 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
40545 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
40546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40548 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
40550 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
40551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40553 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
40555 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
40556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40558 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
40560 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
40561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40563 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
40565 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40568 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
40570 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40573 /* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
40575 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40578 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
40580 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40583 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
40585 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40588 /* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
40590 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40593 /* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
40595 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40598 /* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
40600 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40603 /* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
40605 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40608 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40610 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40613 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40615 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40618 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
40620 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40623 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40625 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40628 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40630 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40633 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
40635 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40638 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40640 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40643 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40645 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40648 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
40650 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40653 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
40655 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40658 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
40660 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40663 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
40665 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40668 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
40670 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40673 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
40675 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40678 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
40680 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40683 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
40685 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40688 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
40690 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40693 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
40695 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40698 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
40700 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40703 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
40705 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40708 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
40710 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40713 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
40715 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40718 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
40720 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40723 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
40725 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40728 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
40730 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40733 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
40735 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40738 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
40740 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40743 /* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
40745 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
40746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40748 /* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
40750 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
40751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40753 /* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
40755 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
40756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40758 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40760 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 48,
40761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40763 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
40765 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 48,
40766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40768 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
40770 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 48,
40771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40773 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40775 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 56,
40776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40778 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
40780 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 56,
40781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40783 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
40785 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 56,
40786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40788 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
40790 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 56,
40791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40793 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40795 M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 64,
40796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40798 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
40800 M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 64,
40801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40803 /* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
40805 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40808 /* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
40810 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40813 /* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
40815 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40818 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40820 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 40,
40821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40823 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
40825 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40828 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
40830 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40833 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40835 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 48,
40836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40838 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
40840 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40843 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
40845 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40848 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
40850 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 48,
40851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40853 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40855 M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 56,
40856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40858 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
40860 M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 56,
40861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40863 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
40865 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40868 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
40870 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40873 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
40875 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40878 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
40880 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40883 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
40885 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40888 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
40890 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40893 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40895 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40898 /* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40900 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40903 /* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40905 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40908 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40910 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40913 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40915 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40918 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40920 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40923 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40925 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40928 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40930 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40933 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40935 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40938 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40940 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40943 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40945 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40948 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40950 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40953 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40955 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40958 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40960 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40963 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40965 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40968 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40970 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40973 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40975 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40978 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40980 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40983 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40985 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40988 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
40990 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40993 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
40995 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
40998 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41000 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
41001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41003 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41005 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
41006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41008 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41010 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
41011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41013 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41015 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
41016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41018 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41020 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
41021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41023 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41025 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
41026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41028 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41030 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
41031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41033 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41035 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
41036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41038 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41040 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
41041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41043 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41045 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41048 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
41050 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41053 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
41055 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41058 /* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
41060 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41063 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41065 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41068 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
41070 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41073 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
41075 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41078 /* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
41080 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41083 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41085 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41088 /* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41090 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41093 /* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41095 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41098 /* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41100 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41103 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41105 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41108 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41110 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41113 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41115 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41118 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41120 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41123 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41125 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41128 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41130 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41133 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41135 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41138 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41140 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41143 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41145 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41148 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41150 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41153 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41155 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41158 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41160 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41163 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41165 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41168 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41170 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41173 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41175 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41178 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41180 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41183 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41185 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41188 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41190 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41193 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41195 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41198 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41200 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41203 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41205 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41208 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41210 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41213 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41215 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41218 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41220 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41223 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41225 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41228 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41230 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41233 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41235 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41238 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41240 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41243 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41245 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41248 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41250 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41253 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41255 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41258 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
41260 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41263 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41265 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41268 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41270 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41273 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41275 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41278 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
41280 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41283 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41285 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
41286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41288 /* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
41290 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
41291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41293 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41295 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
41296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41298 /* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
41300 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
41301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41303 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41305 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
41306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41308 /* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
41310 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
41311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41313 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
41315 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
41316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41318 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
41320 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
41321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41323 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
41325 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
41326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41328 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
41330 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
41331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41333 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
41335 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
41336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41338 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
41340 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
41341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41343 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
41345 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
41346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41348 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
41350 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
41351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41353 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
41355 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
41356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41358 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
41360 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
41361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41363 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
41365 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
41366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41368 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
41370 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
41371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41373 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
41375 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
41376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41378 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
41380 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
41381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41383 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
41385 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
41386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41388 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
41390 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
41391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41393 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
41395 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
41396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41398 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
41400 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
41401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41403 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
41405 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41408 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
41410 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41413 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
41415 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41418 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
41420 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41423 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
41425 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41428 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
41430 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41433 /* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
41435 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41438 /* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
41440 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41443 /* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
41445 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41448 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41450 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41453 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41455 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41458 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
41460 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41463 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41465 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41468 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41470 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41473 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
41475 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41478 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41480 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41483 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41485 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41488 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
41490 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41493 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
41495 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41498 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
41500 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41503 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
41505 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41508 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
41510 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41513 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
41515 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41518 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
41520 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41523 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
41525 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41528 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
41530 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41533 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
41535 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41538 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
41540 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41543 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
41545 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41548 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
41550 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41553 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
41555 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41558 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
41560 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41563 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
41565 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41568 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
41570 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41573 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
41575 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41578 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
41580 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41583 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41585 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41588 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
41590 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41593 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
41595 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41598 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41600 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41603 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
41605 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41608 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
41610 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41613 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41615 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41618 /* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41620 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41623 /* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41625 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41628 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41630 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41633 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41635 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41638 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41640 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41643 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
41645 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41648 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41650 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41653 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41655 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41658 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
41660 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41663 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41665 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41668 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41670 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41673 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
41675 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41678 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
41680 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41683 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
41685 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41688 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
41690 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41693 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
41695 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41698 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
41700 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41703 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
41705 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41708 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
41710 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41713 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
41715 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41718 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41720 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41723 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41725 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41728 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41730 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41733 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41735 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41738 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41740 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41743 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41745 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41748 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41750 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41753 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41755 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41758 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41760 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41763 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41765 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41768 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
41770 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41773 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
41775 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41778 /* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
41780 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41783 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41785 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41788 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
41790 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41793 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
41795 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41798 /* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
41800 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41803 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41805 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41808 /* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41810 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41813 /* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41815 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41818 /* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41820 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41823 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41825 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41828 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41830 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41833 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41835 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41838 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41840 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41843 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41845 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41848 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41850 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41853 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41855 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41858 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41860 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41863 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41865 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41868 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41870 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41873 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41875 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41878 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41880 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41883 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41885 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41888 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41890 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41893 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41895 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41898 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41900 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41903 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41905 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41908 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41910 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41913 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41915 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41918 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41920 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41923 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41925 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41928 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41930 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41933 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41935 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41938 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41940 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41943 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41945 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41948 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41950 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41953 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41955 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41958 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41960 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41963 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41965 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41968 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41970 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41973 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41975 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41978 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
41980 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41983 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41985 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41988 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41990 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41993 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41995 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
41998 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
42000 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
42001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42003 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
42005 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
42006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42008 /* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
42010 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
42011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42013 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
42015 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
42016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42018 /* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
42020 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
42021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42023 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42025 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
42026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42028 /* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
42030 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
42031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42033 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
42035 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
42036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42038 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
42040 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
42041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42043 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
42045 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
42046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42048 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
42050 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
42051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42053 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
42055 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
42056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42058 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
42060 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
42061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42063 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
42065 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
42066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42068 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
42070 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
42071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42073 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
42075 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
42076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42078 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
42080 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
42081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42083 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
42085 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
42086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42088 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
42090 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
42091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42093 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
42095 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
42096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42098 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
42100 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
42101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42103 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
42105 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
42106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42108 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
42110 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
42111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42113 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
42115 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
42116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42118 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
42120 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
42121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42123 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
42125 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
42126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42128 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
42130 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
42131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42133 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
42135 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
42136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42138 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
42140 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
42141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42143 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
42145 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
42146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42148 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
42150 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
42151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42153 /* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
42155 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
42156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42158 /* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
42160 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
42161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42163 /* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
42165 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
42166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42168 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42170 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
42171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42173 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42175 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
42176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42178 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
42180 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
42181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42183 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42185 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
42186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42188 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42190 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
42191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42193 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
42195 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
42196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42198 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42200 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
42201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42203 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42205 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
42206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42208 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
42210 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
42211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42213 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
42215 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
42216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42218 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
42220 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
42221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42223 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
42225 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
42226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42228 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
42230 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
42231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42233 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
42235 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
42236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42238 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
42240 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
42241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42243 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
42245 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
42246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42248 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
42250 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
42251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42253 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
42255 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
42256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42258 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
42260 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
42261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42263 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
42265 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
42266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42268 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
42270 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
42271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42273 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
42275 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
42276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42278 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
42280 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
42281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42283 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
42285 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
42286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42288 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
42290 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
42291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42293 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
42295 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
42296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42298 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
42300 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
42301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42303 /* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
42305 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
42306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42308 /* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
42310 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
42311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42313 /* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
42315 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
42316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42318 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42320 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 48,
42321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42323 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
42325 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
42326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42328 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
42330 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
42331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42333 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42335 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 56,
42336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42338 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
42340 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
42341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42343 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
42345 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
42346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42348 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
42350 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 56,
42351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42353 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42355 M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 64,
42356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42358 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
42360 M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 64,
42361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42363 /* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
42365 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
42366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42368 /* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
42370 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
42371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42373 /* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
42375 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
42376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42378 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42380 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 40,
42381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42383 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
42385 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
42386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42388 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
42390 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
42391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42393 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42395 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 48,
42396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42398 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
42400 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
42401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42403 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
42405 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
42406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42408 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
42410 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 48,
42411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42413 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42415 M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 56,
42416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42418 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
42420 M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 56,
42421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42423 /* divx.l $Dst32RnPrefixedSI */
42425 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divx.l", 24,
42426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42428 /* divx.l $Dst32AnPrefixedSI */
42430 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divx.l", 24,
42431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42433 /* divx.l [$Dst32AnPrefixed] */
42435 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divx.l", 24,
42436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42438 /* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42440 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divx.l", 32,
42441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42443 /* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42445 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divx.l", 40,
42446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42448 /* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42450 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divx.l", 48,
42451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42453 /* divx.l ${Dsp-24-u8}[sb] */
42455 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divx.l", 32,
42456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42458 /* divx.l ${Dsp-24-u16}[sb] */
42460 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divx.l", 40,
42461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42463 /* divx.l ${Dsp-24-s8}[fb] */
42465 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divx.l", 32,
42466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42468 /* divx.l ${Dsp-24-s16}[fb] */
42470 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divx.l", 40,
42471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42473 /* divx.l ${Dsp-24-u16} */
42475 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divx.l", 40,
42476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42478 /* divx.l ${Dsp-24-u24} */
42480 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divx.l", 48,
42481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42483 /* divu.l $Dst32RnPrefixedSI */
42485 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divu.l", 24,
42486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42488 /* divu.l $Dst32AnPrefixedSI */
42490 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divu.l", 24,
42491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42493 /* divu.l [$Dst32AnPrefixed] */
42495 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divu.l", 24,
42496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42498 /* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42500 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divu.l", 32,
42501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42503 /* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42505 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divu.l", 40,
42506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42508 /* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42510 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divu.l", 48,
42511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42513 /* divu.l ${Dsp-24-u8}[sb] */
42515 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divu.l", 32,
42516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42518 /* divu.l ${Dsp-24-u16}[sb] */
42520 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divu.l", 40,
42521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42523 /* divu.l ${Dsp-24-s8}[fb] */
42525 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divu.l", 32,
42526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42528 /* divu.l ${Dsp-24-s16}[fb] */
42530 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divu.l", 40,
42531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42533 /* divu.l ${Dsp-24-u16} */
42535 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divu.l", 40,
42536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42538 /* divu.l ${Dsp-24-u24} */
42540 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divu.l", 48,
42541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42543 /* div.l $Dst32RnPrefixedSI */
42545 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "div.l", 24,
42546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42548 /* div.l $Dst32AnPrefixedSI */
42550 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "div.l", 24,
42551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42553 /* div.l [$Dst32AnPrefixed] */
42555 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "div.l", 24,
42556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42558 /* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42560 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "div.l", 32,
42561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42563 /* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42565 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "div.l", 40,
42566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42568 /* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42570 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "div.l", 48,
42571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42573 /* div.l ${Dsp-24-u8}[sb] */
42575 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "div.l", 32,
42576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42578 /* div.l ${Dsp-24-u16}[sb] */
42580 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "div.l", 40,
42581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42583 /* div.l ${Dsp-24-s8}[fb] */
42585 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "div.l", 32,
42586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42588 /* div.l ${Dsp-24-s16}[fb] */
42590 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "div.l", 40,
42591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42593 /* div.l ${Dsp-24-u16} */
42595 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "div.l", 40,
42596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42598 /* div.l ${Dsp-24-u24} */
42600 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "div.l", 48,
42601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42603 /* divx.w $Dst32RnUnprefixedHI */
42605 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divx.w", 16,
42606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42608 /* divx.w $Dst32AnUnprefixedHI */
42610 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divx.w", 16,
42611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42613 /* divx.w [$Dst32AnUnprefixed] */
42615 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divx.w", 16,
42616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42618 /* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42620 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divx.w", 24,
42621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42623 /* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42625 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divx.w", 32,
42626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42628 /* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42630 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divx.w", 40,
42631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42633 /* divx.w ${Dsp-16-u8}[sb] */
42635 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divx.w", 24,
42636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42638 /* divx.w ${Dsp-16-u16}[sb] */
42640 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divx.w", 32,
42641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42643 /* divx.w ${Dsp-16-s8}[fb] */
42645 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divx.w", 24,
42646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42648 /* divx.w ${Dsp-16-s16}[fb] */
42650 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divx.w", 32,
42651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42653 /* divx.w ${Dsp-16-u16} */
42655 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divx.w", 32,
42656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42658 /* divx.w ${Dsp-16-u24} */
42660 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divx.w", 40,
42661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42663 /* divx.b $Dst32RnUnprefixedQI */
42665 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divx.b", 16,
42666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42668 /* divx.b $Dst32AnUnprefixedQI */
42670 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divx.b", 16,
42671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42673 /* divx.b [$Dst32AnUnprefixed] */
42675 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divx.b", 16,
42676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42678 /* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42680 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divx.b", 24,
42681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42683 /* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42685 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divx.b", 32,
42686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42688 /* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42690 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divx.b", 40,
42691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42693 /* divx.b ${Dsp-16-u8}[sb] */
42695 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divx.b", 24,
42696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42698 /* divx.b ${Dsp-16-u16}[sb] */
42700 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divx.b", 32,
42701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42703 /* divx.b ${Dsp-16-s8}[fb] */
42705 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divx.b", 24,
42706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42708 /* divx.b ${Dsp-16-s16}[fb] */
42710 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divx.b", 32,
42711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42713 /* divx.b ${Dsp-16-u16} */
42715 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divx.b", 32,
42716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42718 /* divx.b ${Dsp-16-u24} */
42720 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divx.b", 40,
42721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42723 /* divx.w $Dst16RnHI */
42725 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-Rn-direct-HI", "divx.w", 16,
42726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42728 /* divx.w $Dst16AnHI */
42730 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-direct-HI", "divx.w", 16,
42731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42733 /* divx.w [$Dst16An] */
42735 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-indirect-HI", "divx.w", 16,
42736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42738 /* divx.w ${Dsp-16-u8}[$Dst16An] */
42740 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divx.w", 24,
42741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42743 /* divx.w ${Dsp-16-u16}[$Dst16An] */
42745 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divx.w", 32,
42746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42748 /* divx.w ${Dsp-16-u8}[sb] */
42750 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divx.w", 24,
42751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42753 /* divx.w ${Dsp-16-u16}[sb] */
42755 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divx.w", 32,
42756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42758 /* divx.w ${Dsp-16-s8}[fb] */
42760 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divx.w", 24,
42761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42763 /* divx.w ${Dsp-16-u16} */
42765 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divx16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divx.w", 32,
42766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42768 /* divx.b $Dst16RnQI */
42770 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-Rn-direct-QI", "divx.b", 16,
42771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42773 /* divx.b $Dst16AnQI */
42775 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-direct-QI", "divx.b", 16,
42776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42778 /* divx.b [$Dst16An] */
42780 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-indirect-QI", "divx.b", 16,
42781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42783 /* divx.b ${Dsp-16-u8}[$Dst16An] */
42785 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divx.b", 24,
42786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42788 /* divx.b ${Dsp-16-u16}[$Dst16An] */
42790 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divx.b", 32,
42791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42793 /* divx.b ${Dsp-16-u8}[sb] */
42795 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divx.b", 24,
42796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42798 /* divx.b ${Dsp-16-u16}[sb] */
42800 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divx.b", 32,
42801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42803 /* divx.b ${Dsp-16-s8}[fb] */
42805 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divx.b", 24,
42806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42808 /* divx.b ${Dsp-16-u16} */
42810 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divx16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divx.b", 32,
42811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42813 /* divu.w $Dst32RnUnprefixedHI */
42815 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divu.w", 16,
42816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42818 /* divu.w $Dst32AnUnprefixedHI */
42820 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divu.w", 16,
42821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42823 /* divu.w [$Dst32AnUnprefixed] */
42825 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divu.w", 16,
42826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42828 /* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42830 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divu.w", 24,
42831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42833 /* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42835 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divu.w", 32,
42836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42838 /* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42840 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divu.w", 40,
42841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42843 /* divu.w ${Dsp-16-u8}[sb] */
42845 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divu.w", 24,
42846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42848 /* divu.w ${Dsp-16-u16}[sb] */
42850 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divu.w", 32,
42851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42853 /* divu.w ${Dsp-16-s8}[fb] */
42855 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divu.w", 24,
42856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42858 /* divu.w ${Dsp-16-s16}[fb] */
42860 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divu.w", 32,
42861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42863 /* divu.w ${Dsp-16-u16} */
42865 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divu.w", 32,
42866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42868 /* divu.w ${Dsp-16-u24} */
42870 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divu.w", 40,
42871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42873 /* divu.b $Dst32RnUnprefixedQI */
42875 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divu.b", 16,
42876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42878 /* divu.b $Dst32AnUnprefixedQI */
42880 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divu.b", 16,
42881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42883 /* divu.b [$Dst32AnUnprefixed] */
42885 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divu.b", 16,
42886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42888 /* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42890 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divu.b", 24,
42891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42893 /* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42895 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divu.b", 32,
42896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42898 /* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42900 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divu.b", 40,
42901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42903 /* divu.b ${Dsp-16-u8}[sb] */
42905 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divu.b", 24,
42906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42908 /* divu.b ${Dsp-16-u16}[sb] */
42910 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divu.b", 32,
42911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42913 /* divu.b ${Dsp-16-s8}[fb] */
42915 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divu.b", 24,
42916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42918 /* divu.b ${Dsp-16-s16}[fb] */
42920 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divu.b", 32,
42921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42923 /* divu.b ${Dsp-16-u16} */
42925 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divu.b", 32,
42926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42928 /* divu.b ${Dsp-16-u24} */
42930 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divu.b", 40,
42931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
42933 /* divu.w $Dst16RnHI */
42935 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-Rn-direct-HI", "divu.w", 16,
42936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42938 /* divu.w $Dst16AnHI */
42940 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-direct-HI", "divu.w", 16,
42941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42943 /* divu.w [$Dst16An] */
42945 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-indirect-HI", "divu.w", 16,
42946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42948 /* divu.w ${Dsp-16-u8}[$Dst16An] */
42950 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divu.w", 24,
42951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42953 /* divu.w ${Dsp-16-u16}[$Dst16An] */
42955 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divu.w", 32,
42956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42958 /* divu.w ${Dsp-16-u8}[sb] */
42960 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divu.w", 24,
42961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42963 /* divu.w ${Dsp-16-u16}[sb] */
42965 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divu.w", 32,
42966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42968 /* divu.w ${Dsp-16-s8}[fb] */
42970 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divu.w", 24,
42971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42973 /* divu.w ${Dsp-16-u16} */
42975 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divu16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divu.w", 32,
42976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42978 /* divu.b $Dst16RnQI */
42980 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-Rn-direct-QI", "divu.b", 16,
42981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42983 /* divu.b $Dst16AnQI */
42985 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-direct-QI", "divu.b", 16,
42986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42988 /* divu.b [$Dst16An] */
42990 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-indirect-QI", "divu.b", 16,
42991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42993 /* divu.b ${Dsp-16-u8}[$Dst16An] */
42995 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divu.b", 24,
42996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
42998 /* divu.b ${Dsp-16-u16}[$Dst16An] */
43000 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divu.b", 32,
43001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43003 /* divu.b ${Dsp-16-u8}[sb] */
43005 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divu.b", 24,
43006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43008 /* divu.b ${Dsp-16-u16}[sb] */
43010 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divu.b", 32,
43011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43013 /* divu.b ${Dsp-16-s8}[fb] */
43015 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divu.b", 24,
43016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43018 /* divu.b ${Dsp-16-u16} */
43020 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divu16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divu.b", 32,
43021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43023 /* div.w $Dst32RnUnprefixedHI */
43025 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "div.w", 16,
43026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43028 /* div.w $Dst32AnUnprefixedHI */
43030 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "div.w", 16,
43031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43033 /* div.w [$Dst32AnUnprefixed] */
43035 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "div.w", 16,
43036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43038 /* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43040 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "div.w", 24,
43041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43043 /* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43045 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "div.w", 32,
43046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43048 /* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43050 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "div.w", 40,
43051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43053 /* div.w ${Dsp-16-u8}[sb] */
43055 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "div.w", 24,
43056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43058 /* div.w ${Dsp-16-u16}[sb] */
43060 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "div.w", 32,
43061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43063 /* div.w ${Dsp-16-s8}[fb] */
43065 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "div.w", 24,
43066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43068 /* div.w ${Dsp-16-s16}[fb] */
43070 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "div.w", 32,
43071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43073 /* div.w ${Dsp-16-u16} */
43075 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "div.w", 32,
43076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43078 /* div.w ${Dsp-16-u24} */
43080 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "div.w", 40,
43081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43083 /* div.b $Dst32RnUnprefixedQI */
43085 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "div.b", 16,
43086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43088 /* div.b $Dst32AnUnprefixedQI */
43090 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "div.b", 16,
43091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43093 /* div.b [$Dst32AnUnprefixed] */
43095 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "div.b", 16,
43096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43098 /* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43100 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "div.b", 24,
43101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43103 /* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43105 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "div.b", 32,
43106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43108 /* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43110 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "div.b", 40,
43111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43113 /* div.b ${Dsp-16-u8}[sb] */
43115 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "div.b", 24,
43116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43118 /* div.b ${Dsp-16-u16}[sb] */
43120 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "div.b", 32,
43121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43123 /* div.b ${Dsp-16-s8}[fb] */
43125 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "div.b", 24,
43126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43128 /* div.b ${Dsp-16-s16}[fb] */
43130 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "div.b", 32,
43131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43133 /* div.b ${Dsp-16-u16} */
43135 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "div.b", 32,
43136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43138 /* div.b ${Dsp-16-u24} */
43140 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "div.b", 40,
43141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43143 /* div.w $Dst16RnHI */
43145 M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-Rn-direct-HI", "div.w", 16,
43146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43148 /* div.w $Dst16AnHI */
43150 M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-An-direct-HI", "div.w", 16,
43151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43153 /* div.w [$Dst16An] */
43155 M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "div16.w-dst16-16-HI-dst16-An-indirect-HI", "div.w", 16,
43156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43158 /* div.w ${Dsp-16-u8}[$Dst16An] */
43160 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "div.w", 24,
43161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43163 /* div.w ${Dsp-16-u16}[$Dst16An] */
43165 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "div.w", 32,
43166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43168 /* div.w ${Dsp-16-u8}[sb] */
43170 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "div.w", 24,
43171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43173 /* div.w ${Dsp-16-u16}[sb] */
43175 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "div.w", 32,
43176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43178 /* div.w ${Dsp-16-s8}[fb] */
43180 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "div.w", 24,
43181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43183 /* div.w ${Dsp-16-u16} */
43185 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "div16.w-dst16-16-HI-dst16-16-16-absolute-HI", "div.w", 32,
43186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43188 /* div.b $Dst16RnQI */
43190 M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-Rn-direct-QI", "div.b", 16,
43191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43193 /* div.b $Dst16AnQI */
43195 M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-An-direct-QI", "div.b", 16,
43196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43198 /* div.b [$Dst16An] */
43200 M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "div16.b-dst16-16-QI-dst16-An-indirect-QI", "div.b", 16,
43201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43203 /* div.b ${Dsp-16-u8}[$Dst16An] */
43205 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "div.b", 24,
43206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43208 /* div.b ${Dsp-16-u16}[$Dst16An] */
43210 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "div.b", 32,
43211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43213 /* div.b ${Dsp-16-u8}[sb] */
43215 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "div.b", 24,
43216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43218 /* div.b ${Dsp-16-u16}[sb] */
43220 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "div.b", 32,
43221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43223 /* div.b ${Dsp-16-s8}[fb] */
43225 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "div.b", 24,
43226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43228 /* div.b ${Dsp-16-u16} */
43230 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "div16.b-dst16-16-QI-dst16-16-16-absolute-QI", "div.b", 32,
43231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43233 /* dec.w $Dst32RnUnprefixedHI */
43235 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "dec.w", 16,
43236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43238 /* dec.w $Dst32AnUnprefixedHI */
43240 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "dec.w", 16,
43241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43243 /* dec.w [$Dst32AnUnprefixed] */
43245 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "dec.w", 16,
43246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43248 /* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43250 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "dec.w", 24,
43251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43253 /* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43255 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "dec.w", 32,
43256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43258 /* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43260 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "dec.w", 40,
43261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43263 /* dec.w ${Dsp-16-u8}[sb] */
43265 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "dec.w", 24,
43266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43268 /* dec.w ${Dsp-16-u16}[sb] */
43270 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "dec.w", 32,
43271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43273 /* dec.w ${Dsp-16-s8}[fb] */
43275 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "dec.w", 24,
43276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43278 /* dec.w ${Dsp-16-s16}[fb] */
43280 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "dec.w", 32,
43281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43283 /* dec.w ${Dsp-16-u16} */
43285 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "dec.w", 32,
43286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43288 /* dec.w ${Dsp-16-u24} */
43290 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "dec.w", 40,
43291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43293 /* dec.b $Dst32RnUnprefixedQI */
43295 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "dec.b", 16,
43296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43298 /* dec.b $Dst32AnUnprefixedQI */
43300 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "dec.b", 16,
43301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43303 /* dec.b [$Dst32AnUnprefixed] */
43305 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "dec.b", 16,
43306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43308 /* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43310 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "dec.b", 24,
43311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43313 /* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43315 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "dec.b", 32,
43316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43318 /* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43320 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "dec.b", 40,
43321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43323 /* dec.b ${Dsp-16-u8}[sb] */
43325 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "dec.b", 24,
43326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43328 /* dec.b ${Dsp-16-u16}[sb] */
43330 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "dec.b", 32,
43331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43333 /* dec.b ${Dsp-16-s8}[fb] */
43335 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "dec.b", 24,
43336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43338 /* dec.b ${Dsp-16-s16}[fb] */
43340 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "dec.b", 32,
43341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43343 /* dec.b ${Dsp-16-u16} */
43345 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "dec.b", 32,
43346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43348 /* dec.b ${Dsp-16-u24} */
43350 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "dec.b", 40,
43351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43353 /* dec.b r0l */
43355 M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, "dec16.b-dst16-3-S-R0l-direct-QI", "dec.b", 8,
43356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43358 /* dec.b r0h */
43360 M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, "dec16.b-dst16-3-S-R0h-direct-QI", "dec.b", 8,
43361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43363 /* dec.b ${Dsp-8-u8}[sb] */
43365 M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-SB-relative-QI", "dec.b", 16,
43366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43368 /* dec.b ${Dsp-8-s8}[fb] */
43370 M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-FB-relative-QI", "dec.b", 16,
43371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43373 /* dec.b ${Dsp-8-u16} */
43375 M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "dec16.b-dst16-3-S-8-16-absolute-QI", "dec.b", 24,
43376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
43378 /* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
43380 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmpx", 24,
43381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43383 /* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
43385 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmpx", 24,
43386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43388 /* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
43390 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmpx", 24,
43391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43393 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
43395 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmpx", 32,
43396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43398 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
43400 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmpx", 32,
43401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43403 /* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
43405 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmpx", 32,
43406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43408 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
43410 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmpx", 40,
43411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43413 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
43415 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmpx", 40,
43416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43418 /* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
43420 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmpx", 40,
43421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43423 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
43425 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmpx", 40,
43426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43428 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
43430 M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmpx", 48,
43431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43433 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
43435 M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmpx", 48,
43436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43438 /* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
43440 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-SB-relative-HI", "cmp.w", 16,
43441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43443 /* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
43445 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-FB-relative-HI", "cmp.w", 16,
43446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43448 /* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
43450 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-16-absolute-HI", "cmp.w", 24,
43451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43453 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
43455 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-SB-relative-QI", "cmp.b", 16,
43456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43458 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
43460 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-FB-relative-QI", "cmp.b", 16,
43461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43463 /* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
43465 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-16-absolute-QI", "cmp.b", 24,
43466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43468 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
43470 M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "cmp.w", 32,
43471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43473 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
43475 M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "cmp.w", 32,
43476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43478 /* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
43480 M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "cmp32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "cmp.w", 40,
43481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43483 /* cmp.w${S} #${Imm-8-HI},r0 */
43485 M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "cmp32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "cmp.w", 24,
43486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43488 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
43490 M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "cmp.b", 24,
43491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43493 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
43495 M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "cmp.b", 24,
43496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43498 /* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
43500 M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "cmp32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "cmp.b", 32,
43501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43503 /* cmp.b${S} #${Imm-8-QI},r0l */
43505 M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "cmp32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "cmp.b", 16,
43506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43508 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43510 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43513 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
43515 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43518 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
43520 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43523 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43525 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43528 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
43530 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43533 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
43535 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43538 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43540 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43543 /* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
43545 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43548 /* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
43550 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43553 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43555 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43558 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43560 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43563 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43565 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43568 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43570 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43573 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43575 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43578 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43580 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43583 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43585 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43588 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43590 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43593 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43595 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43598 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
43600 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43603 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
43605 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43608 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
43610 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43613 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
43615 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43618 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
43620 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43623 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
43625 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43628 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
43630 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43633 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
43635 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43638 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
43640 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43643 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
43645 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43648 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
43650 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43653 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
43655 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43658 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
43660 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43663 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
43665 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43668 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
43670 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43673 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
43675 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43678 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
43680 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43683 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
43685 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43688 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43690 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43693 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
43695 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43698 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
43700 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43703 /* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
43705 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43708 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43710 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43713 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
43715 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43718 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
43720 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43723 /* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
43725 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43728 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43730 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43733 /* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
43735 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43738 /* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
43740 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43743 /* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
43745 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43748 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43750 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43753 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43755 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43758 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43760 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43763 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
43765 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43768 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43770 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43773 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43775 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43778 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43780 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43783 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
43785 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43788 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43790 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43793 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43795 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43798 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43800 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43803 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
43805 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43808 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
43810 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43813 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
43815 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43818 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
43820 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43823 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
43825 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43828 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
43830 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43833 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
43835 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43838 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
43840 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43843 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
43845 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43848 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
43850 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43853 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
43855 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43858 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
43860 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43863 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
43865 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43868 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
43870 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43873 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
43875 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43878 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
43880 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43883 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
43885 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43888 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
43890 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43893 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
43895 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43898 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
43900 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43903 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
43905 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43908 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
43910 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43913 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
43915 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43918 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
43920 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43923 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
43925 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43928 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43930 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
43931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43933 /* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
43935 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
43936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43938 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43940 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
43941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43943 /* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
43945 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
43946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43948 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43950 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
43951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43953 /* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
43955 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
43956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43958 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
43960 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
43961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43963 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
43965 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
43966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43968 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
43970 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
43971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43973 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
43975 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
43976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43978 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
43980 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
43981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43983 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
43985 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
43986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43988 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
43990 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
43991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43993 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
43995 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
43996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
43998 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
44000 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
44001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44003 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
44005 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
44006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44008 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
44010 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
44011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44013 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
44015 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
44016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44018 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
44020 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
44021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44023 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
44025 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
44026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44028 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
44030 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
44031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44033 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
44035 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
44036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44038 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
44040 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
44041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44043 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
44045 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
44046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44048 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
44050 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
44051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44053 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
44055 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
44056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44058 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
44060 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
44061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44063 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
44065 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
44066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44068 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
44070 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
44071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44073 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
44075 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
44076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44078 /* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
44080 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
44081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44083 /* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
44085 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
44086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44088 /* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44090 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
44091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44093 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44095 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
44096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44098 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44100 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
44101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44103 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
44105 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
44106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44108 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44110 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
44111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44113 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44115 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
44116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44118 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
44120 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
44121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44123 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44125 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
44126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44128 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44130 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
44131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44133 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
44135 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
44136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44138 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
44140 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
44141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44143 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
44145 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
44146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44148 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
44150 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
44151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44153 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
44155 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
44156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44158 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
44160 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
44161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44163 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
44165 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
44166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44168 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
44170 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
44171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44173 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
44175 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
44176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44178 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
44180 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
44181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44183 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
44185 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
44186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44188 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
44190 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
44191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44193 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
44195 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
44196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44198 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
44200 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
44201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44203 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
44205 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
44206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44208 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
44210 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
44211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44213 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
44215 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
44216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44218 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
44220 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
44221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44223 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
44225 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
44226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44228 /* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
44230 M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "cmp16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "cmp.b", 8,
44231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
44233 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
44235 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-SB-relative-QI", "cmp.b", 16,
44236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
44238 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
44240 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-FB-relative-QI", "cmp.b", 16,
44241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
44243 /* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
44245 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "cmp16.b.S-src2-src16-2-S-16-absolute-QI", "cmp.b", 24,
44246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
44248 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44250 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
44251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44253 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
44255 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
44256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44258 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
44260 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
44261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44263 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44265 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
44266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44268 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
44270 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
44271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44273 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
44275 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
44276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44278 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44280 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
44281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44283 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
44285 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
44286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44288 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
44290 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
44291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44293 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44295 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
44296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44298 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44300 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
44301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44303 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44305 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
44306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44308 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44310 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
44311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44313 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44315 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
44316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44318 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44320 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
44321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44323 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44325 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
44326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44328 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44330 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
44331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44333 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44335 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
44336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44338 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
44340 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
44341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44343 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
44345 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
44346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44348 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
44350 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
44351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44353 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
44355 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
44356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44358 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
44360 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
44361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44363 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
44365 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
44366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44368 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
44370 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
44371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44373 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
44375 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
44376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44378 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
44380 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
44381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44383 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
44385 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
44386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44388 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
44390 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
44391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44393 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
44395 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
44396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44398 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
44400 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44403 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
44405 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44408 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
44410 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44413 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
44415 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44418 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
44420 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44423 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
44425 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44428 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44430 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44433 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
44435 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44438 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
44440 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44443 /* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
44445 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44448 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44450 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44453 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
44455 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44458 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
44460 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44463 /* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
44465 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44468 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44470 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44473 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
44475 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44478 /* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
44480 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44483 /* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
44485 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44488 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44490 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44493 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44495 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44498 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44500 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44503 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
44505 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44508 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44510 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44513 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44515 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44518 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44520 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44523 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
44525 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44528 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44530 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44533 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44535 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44538 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44540 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44543 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
44545 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44548 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
44550 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44553 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
44555 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44558 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
44560 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44563 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
44565 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44568 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
44570 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44573 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
44575 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44578 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
44580 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44583 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
44585 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44588 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
44590 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44593 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
44595 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44598 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
44600 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44603 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
44605 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44608 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
44610 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44613 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
44615 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44618 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
44620 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44623 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
44625 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44628 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
44630 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44633 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
44635 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44638 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
44640 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44643 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
44645 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44648 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
44650 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44653 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
44655 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44658 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
44660 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44663 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
44665 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44668 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44670 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
44671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44673 /* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
44675 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
44676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44678 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44680 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
44681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44683 /* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
44685 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
44686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44688 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44690 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
44691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44693 /* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
44695 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
44696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44698 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
44700 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
44701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44703 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
44705 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
44706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44708 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
44710 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
44711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44713 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
44715 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
44716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44718 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
44720 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
44721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44723 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
44725 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
44726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44728 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
44730 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
44731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44733 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
44735 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
44736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44738 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
44740 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
44741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44743 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
44745 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
44746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44748 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
44750 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
44751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44753 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
44755 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
44756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44758 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
44760 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
44761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44763 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
44765 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
44766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44768 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
44770 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
44771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44773 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
44775 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
44776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44778 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
44780 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
44781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44783 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
44785 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
44786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44788 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
44790 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44793 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
44795 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44798 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44800 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44803 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
44805 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44808 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
44810 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44813 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44815 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44818 /* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
44820 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44823 /* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
44825 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44828 /* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44830 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44833 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44835 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44838 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44840 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44843 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
44845 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44848 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44850 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44853 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44855 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44858 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
44860 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44863 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44865 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44868 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44870 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44873 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
44875 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44878 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
44880 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44883 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
44885 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44888 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
44890 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44893 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
44895 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44898 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
44900 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44903 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
44905 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44908 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
44910 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44913 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
44915 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44918 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
44920 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44923 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
44925 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44928 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
44930 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44933 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
44935 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44938 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
44940 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44943 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
44945 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44948 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
44950 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44953 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
44955 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44958 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
44960 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44963 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
44965 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44968 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
44970 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44973 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
44975 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44978 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
44980 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44983 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
44985 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44988 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
44990 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44993 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
44995 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
44998 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45000 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
45001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45003 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
45005 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
45006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45008 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
45010 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
45011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45013 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
45015 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
45016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45018 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
45020 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
45021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45023 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
45025 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
45026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45028 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45030 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
45031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45033 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45035 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
45036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45038 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45040 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
45041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45043 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45045 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
45046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45048 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45050 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
45051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45053 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45055 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
45056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45058 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
45060 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
45061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45063 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45065 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
45066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45068 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45070 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
45071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45073 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
45075 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
45076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45078 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45080 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
45081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45083 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45085 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
45086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45088 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
45090 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
45091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45093 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45095 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
45096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45098 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45100 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
45101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45103 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
45105 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
45106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45108 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
45110 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
45111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45113 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
45115 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
45116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45118 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
45120 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
45121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45123 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45125 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
45126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45128 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45130 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
45131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45133 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
45135 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
45136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45138 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
45140 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
45141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45143 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
45145 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
45146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45148 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45150 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45153 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
45155 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45158 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
45160 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45163 /* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
45165 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45168 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45170 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45173 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
45175 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45178 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
45180 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45183 /* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
45185 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45188 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45190 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45193 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
45195 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45198 /* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
45200 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45203 /* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
45205 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45208 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45210 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45213 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45215 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45218 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45220 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45223 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
45225 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45228 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45230 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45233 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45235 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45238 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45240 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45243 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
45245 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45248 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45250 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45253 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45255 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45258 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45260 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45263 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
45265 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45268 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
45270 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45273 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45275 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45278 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
45280 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45283 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45285 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45288 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
45290 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45293 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45295 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45298 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
45300 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45303 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45305 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45308 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
45310 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45313 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45315 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45318 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
45320 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45323 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45325 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45328 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
45330 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45333 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
45335 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45338 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
45340 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45343 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
45345 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45348 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
45350 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45353 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45355 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45358 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
45360 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45363 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
45365 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45368 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
45370 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45373 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
45375 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45378 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
45380 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45383 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
45385 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45388 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45390 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
45391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45393 /* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
45395 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
45396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45398 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45400 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
45401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45403 /* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
45405 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
45406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45408 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45410 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
45411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45413 /* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
45415 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
45416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45418 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
45420 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
45421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45423 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
45425 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
45426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45428 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
45430 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
45431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45433 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
45435 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
45436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45438 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
45440 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
45441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45443 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
45445 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
45446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45448 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
45450 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
45451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45453 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
45455 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
45456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45458 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
45460 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
45461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45463 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
45465 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
45466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45468 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
45470 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
45471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45473 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
45475 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
45476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45478 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
45480 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
45481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45483 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
45485 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
45486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45488 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
45490 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
45491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45493 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
45495 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
45496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45498 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
45500 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
45501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45503 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
45505 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
45506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45508 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
45510 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45513 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
45515 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45518 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45520 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45523 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
45525 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45528 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
45530 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45533 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45535 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45538 /* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
45540 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45543 /* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
45545 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45548 /* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45550 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45553 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45555 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45558 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45560 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45563 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
45565 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45568 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45570 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45573 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45575 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45578 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
45580 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45583 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45585 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45588 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45590 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45593 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
45595 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45598 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
45600 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45603 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
45605 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45608 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
45610 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45613 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
45615 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45618 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
45620 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45623 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
45625 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45628 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
45630 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45633 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
45635 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45638 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
45640 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45643 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
45645 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45648 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
45650 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45653 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
45655 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45658 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
45660 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45663 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
45665 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45668 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
45670 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45673 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
45675 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45678 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
45680 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45683 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
45685 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
45688 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
45690 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45693 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
45695 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45698 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
45700 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45703 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
45705 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45708 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
45710 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45713 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
45715 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45718 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
45720 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45723 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
45725 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45728 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
45730 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45733 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
45735 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45738 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
45740 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45743 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
45745 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45748 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
45750 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45753 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
45755 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45758 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
45760 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45763 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
45765 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45768 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45770 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45773 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45775 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45778 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
45780 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45783 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45785 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45788 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45790 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45793 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
45795 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45798 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45800 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45803 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45805 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45808 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
45810 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45813 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45815 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45818 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45820 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45823 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
45825 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45828 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
45830 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45833 /* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
45835 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45838 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
45840 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
45841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45843 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
45845 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
45846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45848 /* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
45850 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "cmp.w", 32,
45851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45853 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
45855 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
45856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45858 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
45860 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
45861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45863 /* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
45865 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "cmp.w", 32,
45866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45868 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
45870 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45873 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
45875 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45878 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
45880 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45883 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
45885 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45888 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
45890 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45893 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
45895 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45898 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
45900 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45903 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45905 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45908 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45910 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45913 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
45915 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45918 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45920 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45923 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45925 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45928 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
45930 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45933 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45935 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45938 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45940 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45943 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
45945 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45948 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45950 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45953 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
45955 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45958 /* cmp.w${G} $Src16RnHI,$Dst16RnHI */
45960 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45963 /* cmp.w${G} $Src16AnHI,$Dst16RnHI */
45965 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45968 /* cmp.w${G} [$Src16An],$Dst16RnHI */
45970 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45973 /* cmp.w${G} $Src16RnHI,$Dst16AnHI */
45975 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
45976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45978 /* cmp.w${G} $Src16AnHI,$Dst16AnHI */
45980 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
45981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45983 /* cmp.w${G} [$Src16An],$Dst16AnHI */
45985 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "cmp.w", 16,
45986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45988 /* cmp.w${G} $Src16RnHI,[$Dst16An] */
45990 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
45991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45993 /* cmp.w${G} $Src16AnHI,[$Dst16An] */
45995 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
45996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
45998 /* cmp.w${G} [$Src16An],[$Dst16An] */
46000 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "cmp.w", 16,
46001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46003 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
46005 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
46006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46008 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
46010 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
46011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46013 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
46015 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
46016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46018 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
46020 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
46021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46023 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
46025 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
46026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46028 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
46030 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
46031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46033 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
46035 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46038 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
46040 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46043 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
46045 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46048 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
46050 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46053 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
46055 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46058 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
46060 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46063 /* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
46065 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46068 /* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
46070 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46073 /* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
46075 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46078 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
46080 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
46081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46083 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
46085 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
46086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46088 /* cmp.w${G} [$Src16An],${Dsp-16-u16} */
46090 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
46091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46093 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
46095 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
46096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46098 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
46100 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
46101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46103 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
46105 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
46106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46108 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
46110 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
46111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46113 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
46115 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
46116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46118 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
46120 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
46121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46123 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
46125 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
46126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46128 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
46130 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
46131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46133 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
46135 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
46136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46138 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
46140 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
46141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46143 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
46145 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
46146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46148 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
46150 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
46151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46153 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
46155 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
46156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46158 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
46160 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
46161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46163 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
46165 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
46166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46168 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
46170 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
46171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46173 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
46175 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
46176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46178 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
46180 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
46181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46183 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
46185 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
46186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46188 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
46190 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
46191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46193 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
46195 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
46196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46198 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
46200 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
46201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46203 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
46205 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
46206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46208 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
46210 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
46211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46213 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
46215 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
46216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46218 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
46220 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
46221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46223 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
46225 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
46226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46228 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
46230 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
46231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46233 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
46235 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
46236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46238 /* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
46240 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "cmp.b", 32,
46241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46243 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
46245 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
46246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46248 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
46250 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
46251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46253 /* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
46255 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "cmp.b", 32,
46256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46258 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
46260 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
46261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46263 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
46265 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
46266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46268 /* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
46270 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "cmp.b", 32,
46271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46273 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
46275 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
46276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46278 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
46280 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
46281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46283 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
46285 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
46286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46288 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
46290 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
46291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46293 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
46295 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
46296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46298 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
46300 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
46301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46303 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
46305 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
46306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46308 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
46310 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
46311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46313 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
46315 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
46316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46318 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
46320 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
46321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46323 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
46325 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
46326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46328 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
46330 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
46331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46333 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
46335 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
46336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46338 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
46340 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
46341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46343 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
46345 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
46346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46348 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
46350 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
46351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46353 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
46355 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
46356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46358 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
46360 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
46361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46363 /* cmp.b${G} $Src16RnQI,$Dst16RnQI */
46365 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
46366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46368 /* cmp.b${G} $Src16AnQI,$Dst16RnQI */
46370 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
46371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46373 /* cmp.b${G} [$Src16An],$Dst16RnQI */
46375 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "cmp.b", 16,
46376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46378 /* cmp.b${G} $Src16RnQI,$Dst16AnQI */
46380 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
46381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46383 /* cmp.b${G} $Src16AnQI,$Dst16AnQI */
46385 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
46386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46388 /* cmp.b${G} [$Src16An],$Dst16AnQI */
46390 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "cmp.b", 16,
46391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46393 /* cmp.b${G} $Src16RnQI,[$Dst16An] */
46395 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
46396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46398 /* cmp.b${G} $Src16AnQI,[$Dst16An] */
46400 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
46401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46403 /* cmp.b${G} [$Src16An],[$Dst16An] */
46405 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "cmp.b", 16,
46406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46408 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
46410 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46413 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
46415 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46418 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
46420 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46423 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
46425 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46428 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
46430 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46433 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
46435 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46438 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
46440 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46443 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
46445 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46448 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
46450 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46453 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
46455 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46458 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
46460 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46463 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
46465 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46468 /* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
46470 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46473 /* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
46475 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46478 /* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
46480 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46483 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
46485 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46488 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
46490 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46493 /* cmp.b${G} [$Src16An],${Dsp-16-u16} */
46495 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46498 /* cmp.b${S} #${Imm-8-QI},r0l */
46500 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "cmp.b", 16,
46501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46503 /* cmp.b${S} #${Imm-8-QI},r0h */
46505 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "cmp.b", 16,
46506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46508 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
46510 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "cmp.b", 24,
46511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46513 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
46515 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "cmp.b", 24,
46516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46518 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
46520 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "cmp.b", 32,
46521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46523 /* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
46525 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
46526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46528 /* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
46530 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
46531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46533 /* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46535 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
46536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46538 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46540 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
46541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46543 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46545 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
46546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46548 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46550 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
46551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46553 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46555 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
46556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46558 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46560 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
46561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46563 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46565 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
46566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46568 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46570 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
46571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46573 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
46575 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
46576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46578 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
46580 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
46581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46583 /* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
46585 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
46586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46588 /* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
46590 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
46591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46593 /* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46595 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
46596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46598 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46600 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
46601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46603 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46605 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
46606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46608 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46610 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
46611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46613 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46615 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
46616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46618 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46620 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
46621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46623 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46625 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
46626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46628 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46630 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
46631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46633 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
46635 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
46636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46638 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
46640 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
46641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46643 /* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
46645 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-Rn-direct-HI", "cmp.w", 16,
46646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46648 /* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
46650 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-direct-HI", "cmp.w", 16,
46651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46653 /* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
46655 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-indirect-HI", "cmp.w", 16,
46656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46658 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46660 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "cmp.w", 24,
46661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46663 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46665 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "cmp.w", 32,
46666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46668 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46670 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46673 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46675 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46678 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46680 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46683 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
46685 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-absolute-HI", "cmp.w", 32,
46686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46688 /* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
46690 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-Rn-direct-QI", "cmp.b", 16,
46691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46693 /* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
46695 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-direct-QI", "cmp.b", 16,
46696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46698 /* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
46700 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-indirect-QI", "cmp.b", 16,
46701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46703 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46705 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "cmp.b", 24,
46706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46708 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46710 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "cmp.b", 32,
46711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46713 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46715 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46718 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46720 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46723 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46725 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46728 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
46730 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-absolute-QI", "cmp.b", 32,
46731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46733 /* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
46735 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
46736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46738 /* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
46740 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
46741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46743 /* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
46745 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
46746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46748 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46750 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 40,
46751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46753 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46755 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
46756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46758 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46760 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
46761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46763 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46765 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 48,
46766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46768 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46770 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
46771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46773 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
46775 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
46776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46778 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46780 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 48,
46781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46783 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46785 M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 56,
46786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46788 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
46790 M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 56,
46791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46793 /* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
46795 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
46796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46798 /* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
46800 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
46801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46803 /* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
46805 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
46806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46808 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46810 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 32,
46811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46813 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46815 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
46816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46818 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46820 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
46821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46823 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46825 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 40,
46826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46828 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46830 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
46831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46833 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
46835 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
46836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46838 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46840 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 40,
46841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46843 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46845 M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 48,
46846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46848 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
46850 M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 48,
46851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46853 /* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
46855 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-Rn-direct-HI", "cmp.w", 32,
46856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46858 /* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
46860 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-direct-HI", "cmp.w", 32,
46861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46863 /* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
46865 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-indirect-HI", "cmp.w", 32,
46866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46868 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
46870 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "cmp.w", 40,
46871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46873 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46875 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "cmp.w", 40,
46876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46878 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46880 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "cmp.w", 40,
46881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46883 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
46885 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "cmp.w", 48,
46886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46888 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46890 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "cmp.w", 48,
46891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46893 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46895 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-absolute-HI", "cmp.w", 48,
46896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46898 /* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
46900 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-Rn-direct-QI", "cmp.b", 24,
46901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46903 /* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
46905 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-direct-QI", "cmp.b", 24,
46906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46908 /* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
46910 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-indirect-QI", "cmp.b", 24,
46911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46913 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
46915 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "cmp.b", 32,
46916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46918 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46920 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "cmp.b", 32,
46921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46923 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46925 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "cmp.b", 32,
46926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46928 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
46930 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "cmp.b", 40,
46931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46933 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46935 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "cmp.b", 40,
46936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46938 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46940 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-absolute-QI", "cmp.b", 40,
46941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
46943 /* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
46945 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 48,
46946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46948 /* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
46950 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmp.l", 48,
46951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46953 /* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
46955 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmp.l", 48,
46956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46958 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46960 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 56,
46961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46963 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
46965 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 56,
46966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46968 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
46970 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 56,
46971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46973 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46975 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 64,
46976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46978 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
46980 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 64,
46981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46983 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
46985 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 64,
46986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46988 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
46990 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 64,
46991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46993 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46995 M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 72,
46996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
46998 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
47000 M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 72,
47001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47003 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
47005 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "clip.w", 56,
47006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47008 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
47010 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-direct-Prefixed-HI", "clip.w", 56,
47011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47013 /* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
47015 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "clip.w", 56,
47016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47018 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
47020 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "clip.w", 64,
47021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47023 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
47025 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "clip.w", 64,
47026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47028 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
47030 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "clip.w", 64,
47031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47033 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
47035 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "clip.w", 72,
47036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47038 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
47040 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "clip.w", 72,
47041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47043 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
47045 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "clip.w", 72,
47046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47048 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
47050 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "clip.w", 72,
47051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47053 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
47055 M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "clip.w", 80,
47056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47058 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
47060 M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "clip.w", 80,
47061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47063 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
47065 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "clip.b", 40,
47066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47068 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
47070 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-direct-Prefixed-QI", "clip.b", 40,
47071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47073 /* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
47075 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "clip.b", 40,
47076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47078 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
47080 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "clip.b", 48,
47081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47083 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
47085 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "clip.b", 48,
47086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47088 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
47090 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "clip.b", 48,
47091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47093 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
47095 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "clip.b", 56,
47096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47098 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
47100 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "clip.b", 56,
47101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47103 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
47105 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "clip.b", 56,
47106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47108 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
47110 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "clip.b", 56,
47111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47113 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
47115 M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "clip.b", 64,
47116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47118 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
47120 M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "clip.b", 64,
47121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47123 /* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47125 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bxor", 24,
47126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47128 /* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47130 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bxor", 24,
47131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47133 /* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47135 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bxor", 24,
47136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47138 /* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47140 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bxor", 32,
47141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47143 /* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47145 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bxor", 40,
47146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47148 /* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47150 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bxor", 48,
47151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47153 /* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47155 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bxor", 32,
47156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47158 /* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47160 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bxor", 40,
47161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47163 /* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47165 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bxor", 32,
47166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47168 /* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47170 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bxor", 40,
47171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47173 /* bxor${X} ${BitBase32-24-u19-Prefixed} */
47175 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bxor", 40,
47176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47178 /* bxor${X} ${BitBase32-24-u27-Prefixed} */
47180 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bxor", 48,
47181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47183 /* bxor${X} $Bitno16R,$Bit16Rn */
47185 M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bxor16-X-bit16-16-bit16-Rn-direct", "bxor", 24,
47186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47188 /* bxor${X} $Bitno16R,$Bit16An */
47190 M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bxor16-X-bit16-16-bit16-An-direct", "bxor", 24,
47191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47193 /* bxor${X} [$Bit16An] */
47195 M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bxor16-X-bit16-16-bit16-An-indirect", "bxor", 16,
47196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47198 /* bxor${X} ${Dsp-16-u8}[$Bit16An] */
47200 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-An-relative", "bxor", 24,
47201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47203 /* bxor${X} ${Dsp-16-u16}[$Bit16An] */
47205 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-An-relative", "bxor", 32,
47206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47208 /* bxor${X} ${BitBase16-16-u8}[sb] */
47210 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-SB-relative", "bxor", 24,
47211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47213 /* bxor${X} ${BitBase16-16-u16}[sb] */
47215 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-SB-relative", "bxor", 32,
47216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47218 /* bxor${X} ${BitBase16-16-s8}[fb] */
47220 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-FB-relative", "bxor", 24,
47221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47223 /* bxor${X} ${BitBase16-16-u16} */
47225 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bxor16-X-bit16-16-bit16-16-16-absolute", "bxor", 32,
47226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47228 /* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47230 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btsts", 16,
47231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47233 /* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47235 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btsts", 16,
47236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47238 /* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47240 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btsts", 16,
47241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47243 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47245 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btsts", 24,
47246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47248 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47250 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btsts", 32,
47251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47253 /* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47255 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btsts", 40,
47256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47258 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47260 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btsts", 24,
47261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47263 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47265 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btsts", 32,
47266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47268 /* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47270 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btsts", 24,
47271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47273 /* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47275 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btsts", 32,
47276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47278 /* btsts${X} ${BitBase32-16-u19-Unprefixed} */
47280 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btsts", 32,
47281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47283 /* btsts${X} ${BitBase32-16-u27-Unprefixed} */
47285 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btsts", 40,
47286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47288 /* btsts${X} $Bitno16R,$Bit16Rn */
47290 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, "btsts16-X-bit16-16-bit16-Rn-direct", "btsts", 24,
47291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47293 /* btsts${X} $Bitno16R,$Bit16An */
47295 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, "btsts16-X-bit16-16-bit16-An-direct", "btsts", 24,
47296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47298 /* btsts${X} [$Bit16An] */
47300 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, "btsts16-X-bit16-16-bit16-An-indirect", "btsts", 16,
47301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47303 /* btsts${X} ${Dsp-16-u8}[$Bit16An] */
47305 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-An-relative", "btsts", 24,
47306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47308 /* btsts${X} ${Dsp-16-u16}[$Bit16An] */
47310 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-An-relative", "btsts", 32,
47311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47313 /* btsts${X} ${BitBase16-16-u8}[sb] */
47315 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-SB-relative", "btsts", 24,
47316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47318 /* btsts${X} ${BitBase16-16-u16}[sb] */
47320 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-SB-relative", "btsts", 32,
47321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47323 /* btsts${X} ${BitBase16-16-s8}[fb] */
47325 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-FB-relative", "btsts", 24,
47326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47328 /* btsts${X} ${BitBase16-16-u16} */
47330 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btsts16-X-bit16-16-bit16-16-16-absolute", "btsts", 32,
47331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47333 /* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47335 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btstc", 16,
47336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47338 /* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47340 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btstc", 16,
47341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47343 /* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47345 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btstc", 16,
47346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47348 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47350 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btstc", 24,
47351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47353 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47355 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btstc", 32,
47356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47358 /* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47360 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btstc", 40,
47361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47363 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47365 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btstc", 24,
47366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47368 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47370 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btstc", 32,
47371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47373 /* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47375 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btstc", 24,
47376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47378 /* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47380 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btstc", 32,
47381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47383 /* btstc${X} ${BitBase32-16-u19-Unprefixed} */
47385 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btstc", 32,
47386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47388 /* btstc${X} ${BitBase32-16-u27-Unprefixed} */
47390 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btstc", 40,
47391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47393 /* btstc${X} $Bitno16R,$Bit16Rn */
47395 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, "btstc16-X-bit16-16-bit16-Rn-direct", "btstc", 24,
47396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47398 /* btstc${X} $Bitno16R,$Bit16An */
47400 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, "btstc16-X-bit16-16-bit16-An-direct", "btstc", 24,
47401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47403 /* btstc${X} [$Bit16An] */
47405 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, "btstc16-X-bit16-16-bit16-An-indirect", "btstc", 16,
47406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47408 /* btstc${X} ${Dsp-16-u8}[$Bit16An] */
47410 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-An-relative", "btstc", 24,
47411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47413 /* btstc${X} ${Dsp-16-u16}[$Bit16An] */
47415 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-An-relative", "btstc", 32,
47416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47418 /* btstc${X} ${BitBase16-16-u8}[sb] */
47420 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-SB-relative", "btstc", 24,
47421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47423 /* btstc${X} ${BitBase16-16-u16}[sb] */
47425 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-SB-relative", "btstc", 32,
47426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47428 /* btstc${X} ${BitBase16-16-s8}[fb] */
47430 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-FB-relative", "btstc", 24,
47431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47433 /* btstc${X} ${BitBase16-16-u16} */
47435 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btstc16-X-bit16-16-bit16-16-16-absolute", "btstc", 32,
47436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47438 /* btst${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47440 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btst", 16,
47441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47443 /* btst${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47445 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btst", 16,
47446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47448 /* btst${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47450 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btst", 16,
47451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47453 /* btst${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47455 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btst", 24,
47456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47458 /* btst${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47460 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btst", 32,
47461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47463 /* btst${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47465 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btst", 40,
47466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47468 /* btst${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47470 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btst", 24,
47471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47473 /* btst${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47475 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btst", 32,
47476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47478 /* btst${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47480 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btst", 24,
47481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47483 /* btst${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47485 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btst", 32,
47486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47488 /* btst${X} ${BitBase32-16-u19-Unprefixed} */
47490 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btst", 32,
47491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47493 /* btst${X} ${BitBase32-16-u27-Unprefixed} */
47495 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btst", 40,
47496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47498 /* btst${G} $Bitno16R,$Bit16Rn */
47500 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, "btst16-G-bit16-16-8-bit16-Rn-direct", "btst", 24,
47501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47503 /* btst${G} $Bitno16R,$Bit16An */
47505 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, "btst16-G-bit16-16-8-bit16-An-direct", "btst", 24,
47506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47508 /* btst${G} ${Dsp-16-u8}[$Bit16An] */
47510 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-An-relative", "btst", 24,
47511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47513 /* btst${G} ${BitBase16-16-u8}[sb] */
47515 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-SB-relative", "btst", 24,
47516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47518 /* btst${G} ${BitBase16-16-s8}[fb] */
47520 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-FB-relative", "btst", 24,
47521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47523 /* btst${S} ${BitBase16-8-u11-S}[sb] */
47525 M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "btst16-S-bit16-11-S-bit16-11-SB-relative-S", "btst", 16,
47526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47528 /* btst${G} ${Dsp-16-u16}[$Bit16An] */
47530 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-An-relative", "btst", 32,
47531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47533 /* btst${G} ${BitBase16-16-u16}[sb] */
47535 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-SB-relative", "btst", 32,
47536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47538 /* btst${G} ${BitBase16-16-u16} */
47540 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "btst16-G-bit16-16-16-bit16-16-16-absolute", "btst", 32,
47541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47543 /* btst${G} [$Bit16An] */
47545 M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "btst16-G-bit16-16-basic-bit16-An-indirect", "btst", 16,
47546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47548 /* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47550 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bset", 16,
47551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47553 /* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47555 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bset", 16,
47556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47558 /* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47560 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bset", 16,
47561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47563 /* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47565 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bset", 24,
47566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47568 /* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47570 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bset", 32,
47571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47573 /* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47575 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bset", 40,
47576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47578 /* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47580 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bset", 24,
47581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47583 /* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47585 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bset", 32,
47586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47588 /* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47590 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bset", 24,
47591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47593 /* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47595 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bset", 32,
47596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47598 /* bset${X} ${BitBase32-16-u19-Unprefixed} */
47600 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bset", 32,
47601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47603 /* bset${X} ${BitBase32-16-u27-Unprefixed} */
47605 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bset", 40,
47606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47608 /* bset${G} $Bitno16R,$Bit16Rn */
47610 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, "bset16-G-bit16-16-8-bit16-Rn-direct", "bset", 24,
47611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47613 /* bset${G} $Bitno16R,$Bit16An */
47615 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, "bset16-G-bit16-16-8-bit16-An-direct", "bset", 24,
47616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47618 /* bset${G} ${Dsp-16-u8}[$Bit16An] */
47620 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-An-relative", "bset", 24,
47621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47623 /* bset${G} ${BitBase16-16-u8}[sb] */
47625 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-SB-relative", "bset", 24,
47626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47628 /* bset${G} ${BitBase16-16-s8}[fb] */
47630 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-FB-relative", "bset", 24,
47631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47633 /* bset${S} ${BitBase16-8-u11-S}[sb] */
47635 M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bset16-S-bit16-11-S-bit16-11-SB-relative-S", "bset", 16,
47636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47638 /* bset${G} ${Dsp-16-u16}[$Bit16An] */
47640 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-An-relative", "bset", 32,
47641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47643 /* bset${G} ${BitBase16-16-u16}[sb] */
47645 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-SB-relative", "bset", 32,
47646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47648 /* bset${G} ${BitBase16-16-u16} */
47650 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bset16-G-bit16-16-16-bit16-16-16-absolute", "bset", 32,
47651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47653 /* bset${G} [$Bit16An] */
47655 M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bset16-G-bit16-16-basic-bit16-An-indirect", "bset", 16,
47656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47658 /* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47660 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bor", 24,
47661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47663 /* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47665 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bor", 24,
47666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47668 /* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47670 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bor", 24,
47671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47673 /* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47675 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bor", 32,
47676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47678 /* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47680 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bor", 40,
47681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47683 /* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47685 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bor", 48,
47686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47688 /* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47690 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bor", 32,
47691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47693 /* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47695 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bor", 40,
47696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47698 /* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47700 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bor", 32,
47701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47703 /* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47705 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bor", 40,
47706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47708 /* bor${X} ${BitBase32-24-u19-Prefixed} */
47710 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bor", 40,
47711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47713 /* bor${X} ${BitBase32-24-u27-Prefixed} */
47715 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bor", 48,
47716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47718 /* bor${X} $Bitno16R,$Bit16Rn */
47720 M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, "bor16-X-bit16-16-bit16-Rn-direct", "bor", 24,
47721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47723 /* bor${X} $Bitno16R,$Bit16An */
47725 M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, "bor16-X-bit16-16-bit16-An-direct", "bor", 24,
47726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47728 /* bor${X} [$Bit16An] */
47730 M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bor16-X-bit16-16-bit16-An-indirect", "bor", 16,
47731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47733 /* bor${X} ${Dsp-16-u8}[$Bit16An] */
47735 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-8-An-relative", "bor", 24,
47736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47738 /* bor${X} ${Dsp-16-u16}[$Bit16An] */
47740 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-16-An-relative", "bor", 32,
47741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47743 /* bor${X} ${BitBase16-16-u8}[sb] */
47745 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-SB-relative", "bor", 24,
47746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47748 /* bor${X} ${BitBase16-16-u16}[sb] */
47750 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-16-SB-relative", "bor", 32,
47751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47753 /* bor${X} ${BitBase16-16-s8}[fb] */
47755 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-FB-relative", "bor", 24,
47756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47758 /* bor${X} ${BitBase16-16-u16} */
47760 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bor16-X-bit16-16-bit16-16-16-absolute", "bor", 32,
47761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47763 /* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47765 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnxor", 24,
47766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47768 /* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47770 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnxor", 24,
47771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47773 /* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47775 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnxor", 24,
47776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47778 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47780 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnxor", 32,
47781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47783 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47785 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnxor", 40,
47786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47788 /* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47790 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnxor", 48,
47791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47793 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47795 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnxor", 32,
47796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47798 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47800 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnxor", 40,
47801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47803 /* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47805 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnxor", 32,
47806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47808 /* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47810 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnxor", 40,
47811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47813 /* bnxor${X} ${BitBase32-24-u19-Prefixed} */
47815 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnxor", 40,
47816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47818 /* bnxor${X} ${BitBase32-24-u27-Prefixed} */
47820 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnxor", 48,
47821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47823 /* bnxor${X} $Bitno16R,$Bit16Rn */
47825 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnxor16-X-bit16-16-bit16-Rn-direct", "bnxor", 24,
47826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47828 /* bnxor${X} $Bitno16R,$Bit16An */
47830 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnxor16-X-bit16-16-bit16-An-direct", "bnxor", 24,
47831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47833 /* bnxor${X} [$Bit16An] */
47835 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnxor16-X-bit16-16-bit16-An-indirect", "bnxor", 16,
47836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47838 /* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
47840 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-An-relative", "bnxor", 24,
47841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47843 /* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
47845 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-An-relative", "bnxor", 32,
47846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47848 /* bnxor${X} ${BitBase16-16-u8}[sb] */
47850 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-SB-relative", "bnxor", 24,
47851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47853 /* bnxor${X} ${BitBase16-16-u16}[sb] */
47855 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-SB-relative", "bnxor", 32,
47856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47858 /* bnxor${X} ${BitBase16-16-s8}[fb] */
47860 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-FB-relative", "bnxor", 24,
47861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47863 /* bnxor${X} ${BitBase16-16-u16} */
47865 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnxor16-X-bit16-16-bit16-16-16-absolute", "bnxor", 32,
47866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47868 /* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47870 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bntst", 24,
47871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47873 /* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47875 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bntst", 24,
47876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47878 /* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47880 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bntst", 24,
47881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47883 /* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47885 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bntst", 32,
47886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47888 /* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47890 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bntst", 40,
47891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47893 /* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47895 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bntst", 48,
47896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47898 /* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
47900 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bntst", 32,
47901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47903 /* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
47905 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bntst", 40,
47906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47908 /* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
47910 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bntst", 32,
47911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47913 /* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
47915 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bntst", 40,
47916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47918 /* bntst${X} ${BitBase32-24-u19-Prefixed} */
47920 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bntst", 40,
47921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47923 /* bntst${X} ${BitBase32-24-u27-Prefixed} */
47925 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bntst", 48,
47926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47928 /* bntst${X} $Bitno16R,$Bit16Rn */
47930 M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, "bntst16-X-bit16-16-bit16-Rn-direct", "bntst", 24,
47931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47933 /* bntst${X} $Bitno16R,$Bit16An */
47935 M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, "bntst16-X-bit16-16-bit16-An-direct", "bntst", 24,
47936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47938 /* bntst${X} [$Bit16An] */
47940 M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, "bntst16-X-bit16-16-bit16-An-indirect", "bntst", 16,
47941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47943 /* bntst${X} ${Dsp-16-u8}[$Bit16An] */
47945 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-An-relative", "bntst", 24,
47946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47948 /* bntst${X} ${Dsp-16-u16}[$Bit16An] */
47950 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-An-relative", "bntst", 32,
47951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47953 /* bntst${X} ${BitBase16-16-u8}[sb] */
47955 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-SB-relative", "bntst", 24,
47956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47958 /* bntst${X} ${BitBase16-16-u16}[sb] */
47960 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-SB-relative", "bntst", 32,
47961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47963 /* bntst${X} ${BitBase16-16-s8}[fb] */
47965 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-FB-relative", "bntst", 24,
47966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47968 /* bntst${X} ${BitBase16-16-u16} */
47970 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bntst16-X-bit16-16-bit16-16-16-absolute", "bntst", 32,
47971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
47973 /* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47975 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bnot", 16,
47976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47978 /* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47980 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bnot", 16,
47981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47983 /* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47985 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bnot", 16,
47986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47988 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47990 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bnot", 24,
47991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47993 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47995 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bnot", 32,
47996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
47998 /* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48000 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bnot", 40,
48001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48003 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
48005 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bnot", 24,
48006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48008 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
48010 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bnot", 32,
48011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48013 /* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
48015 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bnot", 24,
48016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48018 /* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
48020 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bnot", 32,
48021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48023 /* bnot${X} ${BitBase32-16-u19-Unprefixed} */
48025 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bnot", 32,
48026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48028 /* bnot${X} ${BitBase32-16-u27-Unprefixed} */
48030 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bnot", 40,
48031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48033 /* bnot${G} $Bitno16R,$Bit16Rn */
48035 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, "bnot16-G-bit16-16-8-bit16-Rn-direct", "bnot", 24,
48036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48038 /* bnot${G} $Bitno16R,$Bit16An */
48040 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, "bnot16-G-bit16-16-8-bit16-An-direct", "bnot", 24,
48041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48043 /* bnot${G} ${Dsp-16-u8}[$Bit16An] */
48045 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-An-relative", "bnot", 24,
48046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48048 /* bnot${G} ${BitBase16-16-u8}[sb] */
48050 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-SB-relative", "bnot", 24,
48051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48053 /* bnot${G} ${BitBase16-16-s8}[fb] */
48055 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-FB-relative", "bnot", 24,
48056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48058 /* bnot${S} ${BitBase16-8-u11-S}[sb] */
48060 M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bnot16-S-bit16-11-S-bit16-11-SB-relative-S", "bnot", 16,
48061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48063 /* bnot${G} ${Dsp-16-u16}[$Bit16An] */
48065 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-An-relative", "bnot", 32,
48066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48068 /* bnot${G} ${BitBase16-16-u16}[sb] */
48070 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-SB-relative", "bnot", 32,
48071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48073 /* bnot${G} ${BitBase16-16-u16} */
48075 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bnot16-G-bit16-16-16-bit16-16-16-absolute", "bnot", 32,
48076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48078 /* bnot${G} [$Bit16An] */
48080 M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bnot16-G-bit16-16-basic-bit16-An-indirect", "bnot", 16,
48081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48083 /* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48085 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnor", 24,
48086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48088 /* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48090 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnor", 24,
48091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48093 /* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48095 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnor", 24,
48096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48098 /* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48100 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnor", 32,
48101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48103 /* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48105 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnor", 40,
48106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48108 /* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48110 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnor", 48,
48111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48113 /* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
48115 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnor", 32,
48116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48118 /* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
48120 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnor", 40,
48121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48123 /* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
48125 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnor", 32,
48126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48128 /* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
48130 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnor", 40,
48131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48133 /* bnor${X} ${BitBase32-24-u19-Prefixed} */
48135 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnor", 40,
48136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48138 /* bnor${X} ${BitBase32-24-u27-Prefixed} */
48140 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnor", 48,
48141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48143 /* bnor${X} $Bitno16R,$Bit16Rn */
48145 M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnor16-X-bit16-16-bit16-Rn-direct", "bnor", 24,
48146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48148 /* bnor${X} $Bitno16R,$Bit16An */
48150 M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnor16-X-bit16-16-bit16-An-direct", "bnor", 24,
48151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48153 /* bnor${X} [$Bit16An] */
48155 M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnor16-X-bit16-16-bit16-An-indirect", "bnor", 16,
48156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48158 /* bnor${X} ${Dsp-16-u8}[$Bit16An] */
48160 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-An-relative", "bnor", 24,
48161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48163 /* bnor${X} ${Dsp-16-u16}[$Bit16An] */
48165 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-An-relative", "bnor", 32,
48166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48168 /* bnor${X} ${BitBase16-16-u8}[sb] */
48170 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-SB-relative", "bnor", 24,
48171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48173 /* bnor${X} ${BitBase16-16-u16}[sb] */
48175 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-SB-relative", "bnor", 32,
48176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48178 /* bnor${X} ${BitBase16-16-s8}[fb] */
48180 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-FB-relative", "bnor", 24,
48181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48183 /* bnor${X} ${BitBase16-16-u16} */
48185 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnor16-X-bit16-16-bit16-16-16-absolute", "bnor", 32,
48186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48188 /* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48190 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnand", 24,
48191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48193 /* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48195 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnand", 24,
48196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48198 /* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48200 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnand", 24,
48201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48203 /* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48205 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnand", 32,
48206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48208 /* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48210 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnand", 40,
48211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48213 /* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48215 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnand", 48,
48216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48218 /* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
48220 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnand", 32,
48221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48223 /* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
48225 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnand", 40,
48226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48228 /* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
48230 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnand", 32,
48231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48233 /* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
48235 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnand", 40,
48236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48238 /* bnand${X} ${BitBase32-24-u19-Prefixed} */
48240 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnand", 40,
48241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48243 /* bnand${X} ${BitBase32-24-u27-Prefixed} */
48245 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnand", 48,
48246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48248 /* bnand${X} $Bitno16R,$Bit16Rn */
48250 M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, "bnand16-X-bit16-16-bit16-Rn-direct", "bnand", 24,
48251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48253 /* bnand${X} $Bitno16R,$Bit16An */
48255 M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, "bnand16-X-bit16-16-bit16-An-direct", "bnand", 24,
48256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48258 /* bnand${X} [$Bit16An] */
48260 M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, "bnand16-X-bit16-16-bit16-An-indirect", "bnand", 16,
48261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48263 /* bnand${X} ${Dsp-16-u8}[$Bit16An] */
48265 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-An-relative", "bnand", 24,
48266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48268 /* bnand${X} ${Dsp-16-u16}[$Bit16An] */
48270 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-An-relative", "bnand", 32,
48271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48273 /* bnand${X} ${BitBase16-16-u8}[sb] */
48275 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-SB-relative", "bnand", 24,
48276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48278 /* bnand${X} ${BitBase16-16-u16}[sb] */
48280 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-SB-relative", "bnand", 32,
48281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48283 /* bnand${X} ${BitBase16-16-s8}[fb] */
48285 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-FB-relative", "bnand", 24,
48286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48288 /* bnand${X} ${BitBase16-16-u16} */
48290 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnand16-X-bit16-16-bit16-16-16-absolute", "bnand", 32,
48291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48293 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
48295 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-Rn-direct-Unprefixed", "bm", 24,
48296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48298 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
48300 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-direct-Unprefixed", "bm", 24,
48301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48303 /* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
48305 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-indirect-Unprefixed", "bm", 24,
48306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48308 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48310 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-An-relative-Unprefixed", "bm", 32,
48311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48313 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
48315 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-SB-relative-Unprefixed", "bm", 32,
48316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48318 /* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
48320 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-FB-relative-Unprefixed", "bm", 32,
48321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48323 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48325 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-An-relative-Unprefixed", "bm", 40,
48326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48328 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
48330 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-SB-relative-Unprefixed", "bm", 40,
48331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48333 /* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
48335 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-FB-relative-Unprefixed", "bm", 40,
48336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48338 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
48340 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-absolute-Unprefixed", "bm", 40,
48341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48343 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48345 M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-An-relative-Unprefixed", "bm", 48,
48346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48348 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
48350 M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-absolute-Unprefixed", "bm", 48,
48351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48353 /* bm${cond16-24} $Bitno16R,$Bit16Rn */
48355 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-Rn-direct", "bm", 32,
48356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48358 /* bm${cond16-24} $Bitno16R,$Bit16An */
48360 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-An-direct", "bm", 32,
48361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48363 /* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
48365 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-An-relative", "bm", 32,
48366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48368 /* bm${cond16-24} ${BitBase16-16-u8}[sb] */
48370 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-SB-relative", "bm", 32,
48371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48373 /* bm${cond16-24} ${BitBase16-16-s8}[fb] */
48375 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-FB-relative", "bm", 32,
48376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48378 /* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
48380 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-An-relative", "bm", 40,
48381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48383 /* bm${cond16-32} ${BitBase16-16-u16}[sb] */
48385 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-SB-relative", "bm", 40,
48386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48388 /* bm${cond16-32} ${BitBase16-16-u16} */
48390 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, "bm16-bit16-16-16-cond16-32-bit16-16-16-absolute", "bm", 40,
48391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48393 /* bm${cond16-16} [$Bit16An] */
48395 M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, "bm16-bit16-16-basic-cond16-16-bit16-An-indirect", "bm", 24,
48396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48398 /* bitindex.w $Dst32RnUnprefixedHI */
48400 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "bitindex.w", 16,
48401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48403 /* bitindex.w $Dst32AnUnprefixedHI */
48405 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "bitindex.w", 16,
48406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48408 /* bitindex.w [$Dst32AnUnprefixed] */
48410 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "bitindex.w", 16,
48411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48413 /* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48415 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "bitindex.w", 24,
48416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48418 /* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48420 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "bitindex.w", 32,
48421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48423 /* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48425 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "bitindex.w", 40,
48426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48428 /* bitindex.w ${Dsp-16-u8}[sb] */
48430 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "bitindex.w", 24,
48431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48433 /* bitindex.w ${Dsp-16-u16}[sb] */
48435 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "bitindex.w", 32,
48436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48438 /* bitindex.w ${Dsp-16-s8}[fb] */
48440 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "bitindex.w", 24,
48441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48443 /* bitindex.w ${Dsp-16-s16}[fb] */
48445 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "bitindex.w", 32,
48446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48448 /* bitindex.w ${Dsp-16-u16} */
48450 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "bitindex.w", 32,
48451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48453 /* bitindex.w ${Dsp-16-u24} */
48455 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "bitindex.w", 40,
48456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48458 /* bitindex.b $Dst32RnUnprefixedQI */
48460 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "bitindex.b", 16,
48461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48463 /* bitindex.b $Dst32AnUnprefixedQI */
48465 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "bitindex.b", 16,
48466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48468 /* bitindex.b [$Dst32AnUnprefixed] */
48470 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "bitindex.b", 16,
48471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48473 /* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48475 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "bitindex.b", 24,
48476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48478 /* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48480 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "bitindex.b", 32,
48481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48483 /* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48485 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "bitindex.b", 40,
48486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48488 /* bitindex.b ${Dsp-16-u8}[sb] */
48490 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "bitindex.b", 24,
48491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48493 /* bitindex.b ${Dsp-16-u16}[sb] */
48495 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "bitindex.b", 32,
48496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48498 /* bitindex.b ${Dsp-16-s8}[fb] */
48500 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "bitindex.b", 24,
48501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48503 /* bitindex.b ${Dsp-16-s16}[fb] */
48505 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "bitindex.b", 32,
48506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48508 /* bitindex.b ${Dsp-16-u16} */
48510 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "bitindex.b", 32,
48511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48513 /* bitindex.b ${Dsp-16-u24} */
48515 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "bitindex.b", 40,
48516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48518 /* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
48520 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bclr", 16,
48521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48523 /* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
48525 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bclr", 16,
48526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48528 /* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
48530 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bclr", 16,
48531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48533 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48535 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bclr", 24,
48536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48538 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48540 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bclr", 32,
48541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48543 /* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48545 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bclr", 40,
48546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48548 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
48550 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bclr", 24,
48551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48553 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
48555 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bclr", 32,
48556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48558 /* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
48560 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bclr", 24,
48561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48563 /* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
48565 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bclr", 32,
48566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48568 /* bclr${X} ${BitBase32-16-u19-Unprefixed} */
48570 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bclr", 32,
48571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48573 /* bclr${X} ${BitBase32-16-u27-Unprefixed} */
48575 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bclr", 40,
48576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48578 /* bclr${G} $Bitno16R,$Bit16Rn */
48580 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, "bclr16-G-bit16-16-8-bit16-Rn-direct", "bclr", 24,
48581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48583 /* bclr${G} $Bitno16R,$Bit16An */
48585 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, "bclr16-G-bit16-16-8-bit16-An-direct", "bclr", 24,
48586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48588 /* bclr${G} ${Dsp-16-u8}[$Bit16An] */
48590 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-An-relative", "bclr", 24,
48591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48593 /* bclr${G} ${BitBase16-16-u8}[sb] */
48595 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-SB-relative", "bclr", 24,
48596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48598 /* bclr${G} ${BitBase16-16-s8}[fb] */
48600 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-FB-relative", "bclr", 24,
48601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48603 /* bclr${S} ${BitBase16-8-u11-S}[sb] */
48605 M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bclr16-S-bit16-11-S-bit16-11-SB-relative-S", "bclr", 16,
48606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48608 /* bclr${G} ${Dsp-16-u16}[$Bit16An] */
48610 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-An-relative", "bclr", 32,
48611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48613 /* bclr${G} ${BitBase16-16-u16}[sb] */
48615 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-SB-relative", "bclr", 32,
48616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48618 /* bclr${G} ${BitBase16-16-u16} */
48620 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bclr16-G-bit16-16-16-bit16-16-16-absolute", "bclr", 32,
48621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48623 /* bclr${G} [$Bit16An] */
48625 M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bclr16-G-bit16-16-basic-bit16-An-indirect", "bclr", 16,
48626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48628 /* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48630 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "band", 24,
48631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48633 /* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48635 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "band", 24,
48636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48638 /* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48640 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "band", 24,
48641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48643 /* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48645 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "band", 32,
48646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48648 /* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48650 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "band", 40,
48651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48653 /* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48655 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "band", 48,
48656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48658 /* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
48660 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "band", 32,
48661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48663 /* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
48665 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "band", 40,
48666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48668 /* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
48670 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "band", 32,
48671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48673 /* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
48675 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "band", 40,
48676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48678 /* band${X} ${BitBase32-24-u19-Prefixed} */
48680 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "band", 40,
48681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48683 /* band${X} ${BitBase32-24-u27-Prefixed} */
48685 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "band", 48,
48686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48688 /* band${X} $Bitno16R,$Bit16Rn */
48690 M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, "band16-X-bit16-16-bit16-Rn-direct", "band", 24,
48691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48693 /* band${X} $Bitno16R,$Bit16An */
48695 M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, "band16-X-bit16-16-bit16-An-direct", "band", 24,
48696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48698 /* band${X} [$Bit16An] */
48700 M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, "band16-X-bit16-16-bit16-An-indirect", "band", 16,
48701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48703 /* band${X} ${Dsp-16-u8}[$Bit16An] */
48705 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "band16-X-bit16-16-bit16-16-8-An-relative", "band", 24,
48706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48708 /* band${X} ${Dsp-16-u16}[$Bit16An] */
48710 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "band16-X-bit16-16-bit16-16-16-An-relative", "band", 32,
48711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48713 /* band${X} ${BitBase16-16-u8}[sb] */
48715 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "band16-X-bit16-16-bit16-16-8-SB-relative", "band", 24,
48716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48718 /* band${X} ${BitBase16-16-u16}[sb] */
48720 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "band16-X-bit16-16-bit16-16-16-SB-relative", "band", 32,
48721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48723 /* band${X} ${BitBase16-16-s8}[fb] */
48725 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "band16-X-bit16-16-bit16-16-8-FB-relative", "band", 24,
48726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48728 /* band${X} ${BitBase16-16-u16} */
48730 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "band16-X-bit16-16-bit16-16-16-absolute", "band", 32,
48731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48733 /* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
48735 M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "and.w", 32,
48736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48738 /* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
48740 M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "and.w", 32,
48741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48743 /* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
48745 M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "and32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "and.w", 40,
48746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48748 /* and.w${S} #${Imm-8-HI},r0 */
48750 M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "and32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "and.w", 24,
48751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48753 /* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
48755 M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "and.b", 24,
48756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48758 /* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
48760 M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "and.b", 24,
48761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48763 /* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
48765 M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "and32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "and.b", 32,
48766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48768 /* and.b${S} #${Imm-8-QI},r0l */
48770 M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "and32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "and.b", 16,
48771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48773 /* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
48775 M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "and16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "and.b", 8,
48776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48778 /* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
48780 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-SB-relative-QI", "and.b", 16,
48781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48783 /* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
48785 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-FB-relative-QI", "and.b", 16,
48786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48788 /* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
48790 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "and16.b.S-src2-src16-2-S-16-absolute-QI", "and.b", 24,
48791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
48793 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48795 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48798 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
48800 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48803 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
48805 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48808 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48810 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48813 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
48815 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48818 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
48820 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48823 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48825 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48828 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
48830 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48833 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
48835 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48838 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48840 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48843 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48845 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48848 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48850 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48853 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48855 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48858 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48860 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48863 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48865 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48868 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48870 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48873 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48875 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48878 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48880 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48883 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
48885 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48888 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
48890 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48893 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
48895 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48898 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
48900 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48903 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
48905 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48908 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
48910 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48913 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
48915 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48918 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
48920 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48923 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
48925 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48928 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
48930 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48933 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
48935 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48938 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
48940 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48943 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
48945 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48948 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
48950 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48953 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
48955 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48958 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
48960 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48963 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
48965 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48968 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
48970 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48973 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48975 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48978 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
48980 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48983 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
48985 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48988 /* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
48990 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48993 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48995 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
48998 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
49000 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
49001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49003 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
49005 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
49006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49008 /* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
49010 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
49011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49013 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49015 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
49016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49018 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49020 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
49021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49023 /* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49025 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
49026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49028 /* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49030 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
49031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49033 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49035 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49038 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49040 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49043 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49045 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49048 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49050 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49053 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49055 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49058 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49060 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49063 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49065 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49068 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49070 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49073 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49075 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49078 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49080 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49083 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49085 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49088 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49090 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49093 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49095 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49098 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49100 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49103 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49105 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49108 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49110 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49113 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49115 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49118 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49120 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49123 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49125 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49128 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49130 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49133 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49135 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49138 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49140 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49143 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49145 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49148 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49150 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49153 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49155 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49158 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49160 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49163 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49165 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49168 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49170 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49173 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49175 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49178 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49180 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49183 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49185 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49188 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
49190 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49193 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49195 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49198 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49200 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49203 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49205 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49208 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
49210 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49213 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49215 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
49216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49218 /* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
49220 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
49221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49223 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49225 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
49226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49228 /* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
49230 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
49231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49233 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49235 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
49236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49238 /* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49240 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
49241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49243 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49245 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
49246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49248 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49250 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
49251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49253 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49255 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
49256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49258 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49260 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
49261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49263 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49265 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
49266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49268 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49270 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
49271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49273 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49275 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
49276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49278 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49280 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
49281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49283 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49285 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
49286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49288 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49290 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
49291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49293 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49295 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
49296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49298 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
49300 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
49301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49303 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
49305 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
49306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49308 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
49310 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
49311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49313 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
49315 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
49316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49318 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
49320 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
49321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49323 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
49325 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
49326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49328 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
49330 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
49331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49333 /* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
49335 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
49336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49338 /* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
49340 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
49341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49343 /* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49345 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
49346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49348 /* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
49350 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
49351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49353 /* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
49355 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
49356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49358 /* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49360 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
49361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49363 /* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
49365 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
49366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49368 /* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
49370 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
49371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49373 /* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49375 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
49376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49378 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49380 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
49381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49383 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49385 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
49386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49388 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49390 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
49391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49393 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49395 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49398 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49400 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49403 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49405 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49408 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49410 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49413 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49415 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49418 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49420 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49423 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
49425 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49428 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
49430 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49433 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
49435 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49438 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
49440 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49443 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
49445 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49448 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
49450 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49453 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
49455 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49458 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
49460 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49463 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
49465 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49468 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
49470 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49473 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
49475 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49478 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
49480 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49483 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
49485 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49488 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
49490 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49493 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
49495 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49498 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
49500 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49503 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
49505 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49508 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
49510 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49513 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49515 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49518 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
49520 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49523 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
49525 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49528 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49530 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49533 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
49535 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49538 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
49540 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49543 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49545 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49548 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49550 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49553 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49555 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49558 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49560 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49563 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49565 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49568 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49570 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49573 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49575 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49578 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49580 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49583 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49585 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49588 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49590 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49593 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49595 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49598 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49600 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49603 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
49605 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49608 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
49610 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49613 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
49615 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49618 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
49620 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49623 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
49625 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49628 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
49630 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49633 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
49635 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49638 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
49640 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49643 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
49645 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49648 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
49650 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49653 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
49655 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49658 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
49660 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49663 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
49665 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49668 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
49670 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49673 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
49675 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49678 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
49680 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49683 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
49685 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49688 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
49690 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49693 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49695 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49698 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
49700 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49703 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
49705 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49708 /* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
49710 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49713 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49715 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49718 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
49720 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49723 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
49725 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49728 /* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
49730 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49733 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49735 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49738 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49740 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49743 /* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49745 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49748 /* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49750 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49753 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49755 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49758 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49760 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49763 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49765 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49768 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49770 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49773 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49775 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49778 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49780 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49783 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49785 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49788 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49790 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49793 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49795 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49798 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49800 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49803 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49805 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49808 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49810 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49813 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49815 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49818 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49820 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49823 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49825 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49828 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49830 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49833 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49835 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49838 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49840 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49843 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49845 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49848 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49850 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49853 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49855 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49858 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49860 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49863 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49865 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49868 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49870 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49873 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49875 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49878 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49880 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49883 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49885 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49888 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49890 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49893 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49895 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49898 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49900 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49903 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49905 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49908 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
49910 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49913 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49915 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49918 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49920 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49923 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49925 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49928 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
49930 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49933 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49935 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
49936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49938 /* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
49940 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
49941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49943 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49945 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
49946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49948 /* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
49950 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
49951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49953 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49955 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
49956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49958 /* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49960 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
49961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49963 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49965 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
49966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49968 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49970 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
49971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49973 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49975 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
49976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49978 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49980 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
49981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49983 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49985 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
49986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49988 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49990 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
49991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49993 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49995 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
49996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
49998 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
50000 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
50001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50003 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
50005 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
50006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50008 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
50010 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
50011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50013 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
50015 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
50016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50018 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
50020 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
50021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50023 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
50025 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
50026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50028 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
50030 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
50031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50033 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
50035 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
50036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50038 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
50040 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
50041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50043 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
50045 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
50046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50048 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
50050 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
50051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50053 /* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
50055 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
50056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50058 /* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
50060 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
50061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50063 /* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50065 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
50066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50068 /* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
50070 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
50071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50073 /* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
50075 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
50076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50078 /* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50080 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
50081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50083 /* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
50085 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
50086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50088 /* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
50090 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
50091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50093 /* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50095 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
50096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50098 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50100 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
50101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50103 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50105 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
50106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50108 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
50110 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
50111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50113 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50115 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
50116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50118 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50120 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
50121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50123 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
50125 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
50126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50128 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50130 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
50131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50133 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50135 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
50136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50138 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
50140 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
50141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50143 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
50145 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
50146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50148 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
50150 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
50151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50153 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
50155 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
50156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50158 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
50160 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
50161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50163 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
50165 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
50166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50168 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
50170 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
50171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50173 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
50175 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
50176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50178 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
50180 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
50181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50183 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
50185 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
50186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50188 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
50190 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
50191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50193 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
50195 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
50196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50198 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
50200 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
50201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50203 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
50205 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
50206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50208 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
50210 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
50211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50213 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
50215 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
50216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50218 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
50220 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
50221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50223 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
50225 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
50226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50228 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
50230 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
50231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
50233 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
50235 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
50236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50238 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
50240 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
50241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50243 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
50245 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
50246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50248 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
50250 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "and.w", 24,
50251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50253 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
50255 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "and.w", 24,
50256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50258 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
50260 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "and.w", 24,
50261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50263 /* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50265 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "and.w", 24,
50266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50268 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50270 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
50271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50273 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50275 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
50276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50278 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50280 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
50281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50283 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50285 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
50286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50288 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50290 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
50291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50293 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50295 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
50296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50298 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50300 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
50301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50303 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50305 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
50306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50308 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50310 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
50311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50313 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50315 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
50316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50318 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50320 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
50321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50323 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50325 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
50326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50328 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50330 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
50331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50333 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50335 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
50336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50338 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50340 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
50341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50343 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50345 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
50346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50348 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50350 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
50351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50353 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50355 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
50356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50358 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50360 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
50361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50363 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50365 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
50366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50368 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
50370 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
50371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50373 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
50375 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
50376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50378 /* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
50380 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "and.w", 32,
50381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50383 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
50385 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "and.w", 32,
50386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50388 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
50390 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "and.w", 32,
50391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50393 /* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
50395 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "and.w", 32,
50396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50398 /* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50400 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "and.w", 32,
50401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50403 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50405 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "and.w", 32,
50406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50408 /* and.w${G} ${Dsp-16-u16},[$Dst16An] */
50410 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "and.w", 32,
50411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50413 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50415 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50418 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50420 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50423 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50425 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50428 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50430 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50433 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50435 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50438 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50440 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50443 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50445 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50448 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50450 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50453 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50455 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50458 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50460 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50463 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50465 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50468 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50470 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50473 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50475 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50478 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50480 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50483 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50485 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50488 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50490 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
50491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50493 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50495 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
50496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50498 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
50500 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "and.w", 48,
50501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50503 /* and.w${G} $Src16RnHI,$Dst16RnHI */
50505 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
50506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50508 /* and.w${G} $Src16AnHI,$Dst16RnHI */
50510 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
50511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50513 /* and.w${G} [$Src16An],$Dst16RnHI */
50515 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "and.w", 16,
50516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50518 /* and.w${G} $Src16RnHI,$Dst16AnHI */
50520 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "and.w", 16,
50521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50523 /* and.w${G} $Src16AnHI,$Dst16AnHI */
50525 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "and.w", 16,
50526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50528 /* and.w${G} [$Src16An],$Dst16AnHI */
50530 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "and.w", 16,
50531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50533 /* and.w${G} $Src16RnHI,[$Dst16An] */
50535 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "and.w", 16,
50536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50538 /* and.w${G} $Src16AnHI,[$Dst16An] */
50540 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "and.w", 16,
50541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50543 /* and.w${G} [$Src16An],[$Dst16An] */
50545 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "and.w", 16,
50546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50548 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
50550 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50553 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
50555 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50558 /* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50560 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50563 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
50565 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50568 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
50570 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50573 /* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50575 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50578 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
50580 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50583 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
50585 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50588 /* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
50590 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50593 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
50595 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50598 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
50600 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50603 /* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
50605 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50608 /* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
50610 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50613 /* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
50615 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50618 /* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
50620 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50623 /* and.w${G} $Src16RnHI,${Dsp-16-u16} */
50625 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
50626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50628 /* and.w${G} $Src16AnHI,${Dsp-16-u16} */
50630 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
50631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50633 /* and.w${G} [$Src16An],${Dsp-16-u16} */
50635 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "and.w", 32,
50636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50638 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
50640 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50643 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
50645 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50648 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
50650 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50653 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
50655 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "and.b", 24,
50656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50658 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
50660 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "and.b", 24,
50661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50663 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
50665 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "and.b", 24,
50666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50668 /* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50670 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50673 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50675 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50678 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50680 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50683 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50685 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50688 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50690 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50693 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50695 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50698 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50700 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50703 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50705 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50708 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50710 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50713 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50715 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50718 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50720 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50723 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50725 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50728 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50730 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50733 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50735 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50738 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50740 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50743 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50745 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50748 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50750 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50753 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50755 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50758 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50760 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50763 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50765 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50768 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50770 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50773 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
50775 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
50776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50778 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
50780 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
50781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50783 /* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
50785 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "and.b", 32,
50786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50788 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
50790 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "and.b", 32,
50791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50793 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
50795 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "and.b", 32,
50796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50798 /* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
50800 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "and.b", 32,
50801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50803 /* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50805 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "and.b", 32,
50806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50808 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50810 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "and.b", 32,
50811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50813 /* and.b${G} ${Dsp-16-u16},[$Dst16An] */
50815 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "and.b", 32,
50816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50818 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50820 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50823 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50825 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50828 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50830 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50833 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50835 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50838 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50840 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50843 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50845 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50848 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50850 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50853 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50855 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50858 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50860 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50863 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50865 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50868 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50870 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50873 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50875 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50878 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50880 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50883 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50885 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50888 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50890 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50893 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50895 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
50896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50898 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50900 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
50901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50903 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
50905 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "and.b", 48,
50906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50908 /* and.b${G} $Src16RnQI,$Dst16RnQI */
50910 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
50911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50913 /* and.b${G} $Src16AnQI,$Dst16RnQI */
50915 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
50916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50918 /* and.b${G} [$Src16An],$Dst16RnQI */
50920 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "and.b", 16,
50921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50923 /* and.b${G} $Src16RnQI,$Dst16AnQI */
50925 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "and.b", 16,
50926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50928 /* and.b${G} $Src16AnQI,$Dst16AnQI */
50930 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "and.b", 16,
50931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50933 /* and.b${G} [$Src16An],$Dst16AnQI */
50935 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "and.b", 16,
50936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50938 /* and.b${G} $Src16RnQI,[$Dst16An] */
50940 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "and.b", 16,
50941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50943 /* and.b${G} $Src16AnQI,[$Dst16An] */
50945 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "and.b", 16,
50946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50948 /* and.b${G} [$Src16An],[$Dst16An] */
50950 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "and.b", 16,
50951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50953 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
50955 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50958 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
50960 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50963 /* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50965 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50968 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
50970 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50973 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
50975 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50978 /* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50980 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50983 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
50985 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50988 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
50990 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50993 /* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
50995 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
50998 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
51000 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
51001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51003 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
51005 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
51006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51008 /* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
51010 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
51011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51013 /* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
51015 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
51016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51018 /* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
51020 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
51021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51023 /* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
51025 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
51026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51028 /* and.b${G} $Src16RnQI,${Dsp-16-u16} */
51030 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
51031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51033 /* and.b${G} $Src16AnQI,${Dsp-16-u16} */
51035 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
51036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51038 /* and.b${G} [$Src16An],${Dsp-16-u16} */
51040 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "and.b", 32,
51041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51043 /* and.b${S} #${Imm-8-QI},r0l */
51045 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "and.b", 16,
51046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51048 /* and.b${S} #${Imm-8-QI},r0h */
51050 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "and.b", 16,
51051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51053 /* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
51055 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "and.b", 24,
51056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51058 /* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
51060 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "and.b", 24,
51061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51063 /* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
51065 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "and.b", 32,
51066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51068 /* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
51070 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
51071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51073 /* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
51075 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "and.w", 32,
51076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51078 /* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
51080 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
51081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51083 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51085 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 40,
51086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51088 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51090 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 40,
51091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51093 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51095 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 40,
51096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51098 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51100 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 48,
51101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51103 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51105 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 48,
51106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51108 /* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
51110 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 48,
51111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51113 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51115 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "and.w", 48,
51116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51118 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51120 M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 56,
51121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51123 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
51125 M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "and.w", 56,
51126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51128 /* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
51130 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
51131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51133 /* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
51135 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "and.b", 24,
51136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51138 /* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
51140 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
51141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51143 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51145 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 32,
51146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51148 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51150 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 32,
51151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51153 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51155 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 32,
51156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51158 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51160 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 40,
51161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51163 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51165 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 40,
51166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51168 /* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
51170 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 40,
51171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51173 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51175 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "and.b", 40,
51176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51178 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51180 M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 48,
51181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51183 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
51185 M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "and.b", 48,
51186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51188 /* and.w${G} #${Imm-16-HI},$Dst16RnHI */
51190 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "and16.w-imm-G-basic-dst16-Rn-direct-HI", "and.w", 32,
51191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51193 /* and.w${G} #${Imm-16-HI},$Dst16AnHI */
51195 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "and16.w-imm-G-basic-dst16-An-direct-HI", "and.w", 32,
51196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51198 /* and.w${G} #${Imm-16-HI},[$Dst16An] */
51200 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "and16.w-imm-G-basic-dst16-An-indirect-HI", "and.w", 32,
51201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51203 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
51205 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "and.w", 40,
51206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51208 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51210 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "and.w", 40,
51211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51213 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51215 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "and.w", 40,
51216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51218 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
51220 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "and.w", 48,
51221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51223 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51225 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "and.w", 48,
51226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51228 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51230 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "and16.w-imm-G-16-16-dst16-16-16-absolute-HI", "and.w", 48,
51231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51233 /* and.b${G} #${Imm-16-QI},$Dst16RnQI */
51235 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "and16.b-imm-G-basic-dst16-Rn-direct-QI", "and.b", 24,
51236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51238 /* and.b${G} #${Imm-16-QI},$Dst16AnQI */
51240 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "and16.b-imm-G-basic-dst16-An-direct-QI", "and.b", 24,
51241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51243 /* and.b${G} #${Imm-16-QI},[$Dst16An] */
51245 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "and16.b-imm-G-basic-dst16-An-indirect-QI", "and.b", 24,
51246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51248 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
51250 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "and.b", 32,
51251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51253 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51255 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "and.b", 32,
51256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51258 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51260 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "and.b", 32,
51261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51263 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
51265 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "and.b", 40,
51266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51268 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51270 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "and.b", 40,
51271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51273 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51275 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "and16.b-imm-G-16-16-dst16-16-16-absolute-QI", "and.b", 40,
51276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51278 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
51280 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adjnz.w", 32,
51281 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51283 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51285 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adjnz.w", 32,
51286 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51288 /* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51290 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adjnz.w", 32,
51291 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51293 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
51295 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adjnz.w", 40,
51296 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51298 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51300 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adjnz.w", 40,
51301 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51303 /* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
51305 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adjnz.w", 40,
51306 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51308 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
51310 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adjnz.w", 40,
51311 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51313 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
51315 M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adjnz.w", 48,
51316 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51318 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
51320 M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adjnz.w", 48,
51321 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51323 /* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
51325 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adjnz.w", 24,
51326 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51328 /* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
51330 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "adjnz.w", 24,
51331 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51333 /* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
51335 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adjnz.w", 24,
51336 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51338 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
51340 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adjnz.b", 32,
51341 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51343 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51345 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adjnz.b", 32,
51346 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51348 /* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51350 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adjnz.b", 32,
51351 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51353 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
51355 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adjnz.b", 40,
51356 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51358 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51360 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adjnz.b", 40,
51361 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51363 /* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
51365 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adjnz.b", 40,
51366 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51368 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
51370 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adjnz.b", 40,
51371 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51373 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
51375 M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adjnz.b", 48,
51376 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51378 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
51380 M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adjnz.b", 48,
51381 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51383 /* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
51385 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adjnz.b", 24,
51386 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51388 /* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
51390 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "adjnz.b", 24,
51391 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51393 /* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
51395 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adjnz.b", 24,
51396 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51398 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
51400 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "adjnz.w", 32,
51401 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51403 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51405 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "adjnz.w", 32,
51406 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51408 /* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51410 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "adjnz.w", 32,
51411 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51413 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51415 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "adjnz.w", 40,
51416 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51418 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51420 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "adjnz.w", 40,
51421 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51423 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51425 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "adjnz.w", 40,
51426 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51428 /* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
51430 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-Rn-direct-HI", "adjnz.w", 24,
51431 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51433 /* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
51435 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-direct-HI", "adjnz.w", 24,
51436 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51438 /* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51440 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-indirect-HI", "adjnz.w", 24,
51441 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51443 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
51445 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "adjnz.b", 32,
51446 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51448 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51450 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "adjnz.b", 32,
51451 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51453 /* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51455 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "adjnz.b", 32,
51456 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51458 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51460 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "adjnz.b", 40,
51461 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51463 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51465 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "adjnz.b", 40,
51466 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51468 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51470 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "adjnz.b", 40,
51471 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51473 /* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
51475 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-Rn-direct-QI", "adjnz.b", 24,
51476 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51478 /* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
51480 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-direct-QI", "adjnz.b", 24,
51481 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51483 /* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51485 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-indirect-QI", "adjnz.b", 24,
51486 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
51488 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51490 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51493 /* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
51495 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51498 /* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
51500 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51503 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51505 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51508 /* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
51510 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51513 /* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
51515 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51518 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51520 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51523 /* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
51525 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51528 /* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
51530 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51533 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51535 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51538 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51540 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51543 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51545 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51548 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51550 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51553 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51555 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51558 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51560 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51563 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51565 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51568 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51570 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51573 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51575 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51578 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
51580 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51583 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
51585 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51588 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
51590 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51593 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
51595 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51598 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
51600 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51603 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
51605 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51608 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
51610 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51613 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
51615 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51618 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
51620 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51623 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
51625 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51628 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
51630 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51633 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
51635 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51638 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
51640 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51643 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
51645 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51648 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
51650 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51653 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
51655 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51658 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
51660 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51663 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
51665 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51668 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51670 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51673 /* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
51675 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51678 /* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
51680 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51683 /* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
51685 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51688 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51690 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51693 /* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
51695 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51698 /* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
51700 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51703 /* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
51705 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51708 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51710 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51713 /* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
51715 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51718 /* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
51720 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51723 /* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
51725 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51728 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51730 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51733 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51735 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51738 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51740 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51743 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
51745 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51748 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51750 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51753 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51755 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51758 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51760 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51763 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
51765 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51768 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51770 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51773 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51775 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51778 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51780 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51783 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
51785 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51788 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
51790 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51793 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51795 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51798 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
51800 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51803 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51805 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51808 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
51810 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51813 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51815 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51818 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
51820 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51823 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51825 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51828 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
51830 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51833 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51835 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51838 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
51840 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51843 /* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51845 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51848 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
51850 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51853 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
51855 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51858 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
51860 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51863 /* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
51865 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51868 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
51870 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51873 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51875 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51878 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
51880 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51883 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
51885 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51888 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
51890 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51893 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
51895 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51898 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
51900 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51903 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
51905 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51908 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51910 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
51911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51913 /* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
51915 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
51916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51918 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51920 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
51921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51923 /* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
51925 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
51926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51928 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51930 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
51931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51933 /* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
51935 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
51936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51938 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
51940 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
51941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51943 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
51945 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
51946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51948 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
51950 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
51951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51953 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
51955 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
51956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51958 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
51960 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
51961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51963 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
51965 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
51966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51968 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
51970 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
51971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51973 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
51975 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
51976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51978 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
51980 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
51981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51983 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
51985 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
51986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51988 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
51990 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
51991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51993 /* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
51995 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
51996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
51998 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
52000 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
52001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52003 /* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
52005 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
52006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52008 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
52010 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
52011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52013 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
52015 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
52016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52018 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
52020 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
52021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52023 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
52025 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
52026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52028 /* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
52030 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
52031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52033 /* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
52035 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
52036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52038 /* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
52040 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
52041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52043 /* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
52045 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
52046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52048 /* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
52050 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
52051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52053 /* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
52055 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
52056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52058 /* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
52060 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
52061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52063 /* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
52065 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
52066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52068 /* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
52070 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
52071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52073 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
52075 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
52076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52078 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
52080 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
52081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52083 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
52085 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
52086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52088 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
52090 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
52091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52093 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
52095 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
52096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52098 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
52100 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
52101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52103 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
52105 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
52106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52108 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
52110 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
52111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52113 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
52115 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
52116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52118 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
52120 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
52121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52123 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
52125 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
52126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52128 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
52130 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
52131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52133 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
52135 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
52136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52138 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
52140 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
52141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52143 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
52145 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
52146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52148 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
52150 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
52151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52153 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
52155 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
52156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52158 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
52160 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
52161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52163 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
52165 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
52166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52168 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
52170 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
52171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52173 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
52175 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
52176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52178 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
52180 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
52181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52183 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
52185 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
52186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52188 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
52190 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
52191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52193 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
52195 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
52196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52198 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
52200 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
52201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52203 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
52205 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
52206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52208 /* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
52210 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
52211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52213 /* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
52215 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "addx", 24,
52216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52218 /* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
52220 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "addx", 24,
52221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52223 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
52225 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "addx", 32,
52226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52228 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
52230 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 32,
52231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52233 /* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
52235 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 32,
52236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52238 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
52240 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "addx", 40,
52241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52243 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
52245 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 40,
52246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52248 /* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
52250 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 40,
52251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52253 /* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
52255 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "addx", 40,
52256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52258 /* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
52260 M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "addx", 48,
52261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52263 /* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
52265 M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "addx", 48,
52266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52268 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52270 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
52271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52273 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
52275 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
52276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52278 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
52280 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
52281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52283 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52285 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
52286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52288 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
52290 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
52291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52293 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
52295 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
52296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52298 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52300 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
52301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52303 /* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52305 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
52306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52308 /* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52310 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
52311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52313 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52315 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
52316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52318 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52320 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
52321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52323 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52325 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
52326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52328 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52330 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
52331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52333 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52335 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
52336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52338 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52340 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
52341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52343 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52345 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
52346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52348 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52350 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
52351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52353 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52355 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
52356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52358 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52360 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
52361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52363 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52365 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
52366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52368 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
52370 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
52371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52373 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
52375 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
52376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52378 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
52380 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
52381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52383 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
52385 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
52386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52388 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
52390 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
52391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52393 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
52395 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
52396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52398 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
52400 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
52401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52403 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
52405 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52408 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
52410 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52413 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
52415 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52418 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
52420 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52423 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
52425 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52428 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
52430 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52433 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
52435 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52438 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
52440 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52443 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
52445 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52448 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52450 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52453 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
52455 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52458 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
52460 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52463 /* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
52465 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52468 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52470 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52473 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
52475 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52478 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
52480 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52483 /* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
52485 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52488 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52490 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52493 /* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
52495 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52498 /* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
52500 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52503 /* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
52505 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52508 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
52510 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52513 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52515 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52518 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52520 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52523 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
52525 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52528 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
52530 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52533 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52535 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52538 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52540 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52543 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
52545 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52548 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
52550 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52553 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52555 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52558 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52560 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52563 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
52565 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52568 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
52570 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52573 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52575 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52578 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52580 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52583 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52585 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52588 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52590 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52593 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52595 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52598 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52600 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52603 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52605 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52608 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52610 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52613 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52615 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52618 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52620 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52623 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52625 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52628 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52630 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52633 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52635 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52638 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52640 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52643 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52645 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52648 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52650 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52653 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52655 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52658 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52660 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52663 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
52665 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52668 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52670 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52673 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52675 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52678 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52680 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52683 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
52685 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52688 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52690 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
52691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52693 /* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
52695 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
52696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52698 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52700 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
52701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52703 /* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
52705 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
52706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52708 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52710 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
52711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52713 /* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
52715 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
52716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52718 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
52720 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
52721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52723 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
52725 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
52726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52728 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
52730 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
52731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52733 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
52735 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
52736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52738 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
52740 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
52741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52743 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
52745 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
52746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52748 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
52750 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
52751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52753 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
52755 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
52756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52758 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
52760 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
52761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52763 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
52765 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
52766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52768 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
52770 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
52771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52773 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
52775 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
52776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52778 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
52780 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
52781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52783 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
52785 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
52786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52788 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
52790 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
52791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52793 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
52795 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
52796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52798 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
52800 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
52801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52803 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
52805 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
52806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52808 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
52810 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52813 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
52815 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52818 /* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
52820 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52823 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
52825 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52828 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
52830 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52833 /* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
52835 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52838 /* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
52840 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52843 /* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
52845 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52848 /* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
52850 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52853 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52855 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52858 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52860 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52863 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
52865 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52868 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52870 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52873 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52875 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52878 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
52880 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52883 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52885 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52888 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52890 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52893 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
52895 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52898 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
52900 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52903 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
52905 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52908 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
52910 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52913 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
52915 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52918 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
52920 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52923 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
52925 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52928 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
52930 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52933 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
52935 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52938 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
52940 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52943 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
52945 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52948 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
52950 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52953 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
52955 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52958 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
52960 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52963 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
52965 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52968 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
52970 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52973 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
52975 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52978 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
52980 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52983 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
52985 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52988 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
52990 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52993 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
52995 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
52998 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
53000 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
53001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53003 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53005 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
53006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53008 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
53010 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
53011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53013 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
53015 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
53016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53018 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53020 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53023 /* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53025 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53028 /* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53030 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53033 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53035 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
53036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53038 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53040 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
53041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53043 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53045 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
53046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53048 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53050 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
53051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53053 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53055 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
53056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53058 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53060 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
53061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53063 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53065 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
53066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53068 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53070 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
53071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53073 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53075 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
53076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53078 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53080 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53083 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53085 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53088 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53090 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53093 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53095 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53098 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53100 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53103 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53105 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53108 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53110 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53113 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53115 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53118 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53120 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53123 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53125 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53128 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53130 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53133 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53135 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53138 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53140 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
53141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53143 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53145 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
53146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53148 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53150 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
53151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53153 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53155 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
53156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53158 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53160 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
53161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53163 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53165 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
53166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53168 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53170 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53173 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
53175 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53178 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
53180 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53183 /* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
53185 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53188 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53190 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53193 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
53195 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53198 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
53200 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53203 /* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
53205 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53208 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53210 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53213 /* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
53215 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53218 /* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
53220 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53223 /* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
53225 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53228 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
53230 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53233 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53235 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53238 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53240 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53243 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
53245 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53248 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
53250 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53253 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53255 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53258 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53260 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53263 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
53265 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53268 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
53270 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53273 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53275 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53278 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53280 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53283 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
53285 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53288 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
53290 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53293 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
53295 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53298 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
53300 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53303 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
53305 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53308 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
53310 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53313 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
53315 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53318 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
53320 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53323 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
53325 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53328 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
53330 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53333 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
53335 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53338 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
53340 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53343 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
53345 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53348 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
53350 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53353 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
53355 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53358 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
53360 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53363 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
53365 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53368 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
53370 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53373 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
53375 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53378 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
53380 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53383 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
53385 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53388 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
53390 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53393 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
53395 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53398 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
53400 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53403 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
53405 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53408 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53410 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
53411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53413 /* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
53415 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
53416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53418 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53420 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
53421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53423 /* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
53425 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
53426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53428 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53430 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
53431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53433 /* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
53435 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
53436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53438 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
53440 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
53441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53443 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
53445 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
53446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53448 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
53450 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
53451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53453 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
53455 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
53456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53458 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
53460 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
53461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53463 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
53465 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
53466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53468 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
53470 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
53471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53473 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
53475 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
53476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53478 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
53480 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
53481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53483 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
53485 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
53486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53488 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
53490 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
53491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53493 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
53495 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
53496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53498 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
53500 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
53501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53503 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
53505 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
53506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53508 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
53510 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
53511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53513 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
53515 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
53516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53518 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
53520 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
53521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53523 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
53525 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
53526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53528 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
53530 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53533 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
53535 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53538 /* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
53540 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53543 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
53545 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53548 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
53550 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53553 /* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
53555 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53558 /* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
53560 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53563 /* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
53565 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53568 /* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
53570 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53573 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53575 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53578 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53580 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53583 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
53585 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53588 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53590 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53593 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53595 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53598 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
53600 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53603 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53605 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53608 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53610 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53613 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
53615 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53618 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
53620 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53623 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
53625 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53628 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
53630 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53633 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
53635 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53638 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
53640 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53643 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
53645 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53648 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
53650 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53653 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
53655 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53658 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
53660 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53663 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
53665 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53668 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
53670 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53673 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
53675 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53678 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
53680 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53683 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
53685 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53688 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
53690 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53693 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
53695 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53698 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
53700 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53703 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
53705 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53708 /* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
53710 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
53711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53713 /* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
53715 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
53716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53718 /* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
53720 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
53721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53723 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53725 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 48,
53726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53728 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
53730 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 48,
53731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53733 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
53735 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 48,
53736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53738 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53740 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 56,
53741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53743 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
53745 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 56,
53746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53748 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
53750 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 56,
53751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53753 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
53755 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 56,
53756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53758 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53760 M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 64,
53761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53763 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
53765 M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 64,
53766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53768 /* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
53770 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
53771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53773 /* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
53775 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
53776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53778 /* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
53780 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53783 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53785 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 40,
53786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53788 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
53790 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53793 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
53795 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53798 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53800 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 48,
53801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53803 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
53805 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53808 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
53810 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53813 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
53815 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 48,
53816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53818 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53820 M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 56,
53821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53823 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
53825 M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 56,
53826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53828 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53830 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53833 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
53835 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53838 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
53840 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53843 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53845 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53848 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
53850 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53853 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
53855 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53858 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53860 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53863 /* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53865 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53868 /* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53870 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53873 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53875 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53878 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53880 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53883 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53885 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53888 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53890 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53893 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53895 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53898 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53900 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53903 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53905 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53908 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53910 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53913 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53915 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53918 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53920 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53923 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53925 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53928 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53930 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53933 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53935 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53938 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53940 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53943 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53945 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53948 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53950 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53953 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53955 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53958 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53960 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53963 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53965 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53968 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53970 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53973 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53975 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53978 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53980 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53983 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53985 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53988 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53990 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53993 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53995 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
53998 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54000 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
54001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54003 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54005 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
54006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54008 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54010 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
54011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54013 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
54015 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
54016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54018 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
54020 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
54021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54023 /* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
54025 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
54026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54028 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54030 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54033 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
54035 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54038 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
54040 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54043 /* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
54045 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54048 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54050 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54053 /* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54055 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54058 /* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54060 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54063 /* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54065 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54068 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54070 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54073 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54075 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54078 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54080 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54083 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54085 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54088 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54090 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54093 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54095 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54098 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54100 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54103 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54105 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54108 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54110 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54113 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54115 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54118 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54120 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54123 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54125 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54128 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54130 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54133 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54135 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54138 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54140 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54143 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54145 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54148 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54150 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54153 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54155 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54158 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54160 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54163 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54165 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54168 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54170 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54173 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54175 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54178 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54180 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54183 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54185 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54188 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54190 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54193 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54195 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54198 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54200 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54203 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54205 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54208 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54210 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54213 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54215 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54218 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54220 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54223 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
54225 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54228 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54230 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54233 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54235 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54238 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54240 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54243 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
54245 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54248 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54250 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
54251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54253 /* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
54255 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
54256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54258 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54260 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
54261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54263 /* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
54265 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
54266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54268 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54270 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
54271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54273 /* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54275 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
54276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54278 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54280 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
54281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54283 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54285 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
54286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54288 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54290 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
54291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54293 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54295 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
54296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54298 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54300 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
54301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54303 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54305 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
54306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54308 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54310 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
54311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54313 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
54315 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
54316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54318 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
54320 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
54321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54323 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
54325 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
54326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54328 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
54330 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
54331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54333 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
54335 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
54336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54338 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
54340 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
54341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54343 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
54345 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
54346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54348 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
54350 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
54351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54353 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
54355 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
54356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54358 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
54360 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
54361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54363 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
54365 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
54366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54368 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
54370 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
54371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54373 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
54375 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
54376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54378 /* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
54380 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
54381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54383 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
54385 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
54386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54388 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
54390 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
54391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54393 /* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
54395 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
54396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54398 /* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
54400 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54403 /* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
54405 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54408 /* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
54410 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54413 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54415 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54418 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54420 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54423 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
54425 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54428 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54430 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54433 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54435 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54438 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
54440 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54443 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54445 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54448 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54450 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54453 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
54455 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54458 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
54460 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54463 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
54465 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54468 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
54470 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54473 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
54475 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54478 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
54480 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54483 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
54485 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54488 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
54490 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54493 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
54495 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54498 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
54500 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54503 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
54505 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54508 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
54510 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54513 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
54515 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54518 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
54520 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54523 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
54525 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54528 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
54530 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54533 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
54535 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54538 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
54540 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54543 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
54545 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54548 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54550 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54553 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
54555 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54558 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
54560 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54563 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54565 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54568 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
54570 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54573 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
54575 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54578 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54580 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54583 /* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
54585 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54588 /* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
54590 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54593 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
54595 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54598 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54600 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54603 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54605 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54608 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
54610 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54613 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54615 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54618 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54620 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54623 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
54625 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54628 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54630 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54633 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54635 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54638 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
54640 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54643 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
54645 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54648 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54650 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54653 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54655 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54658 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54660 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54663 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54665 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54668 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54670 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54673 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54675 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54678 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54680 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54683 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54685 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54688 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54690 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54693 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54695 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54698 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54700 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54703 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54705 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54708 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54710 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54713 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54715 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54718 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54720 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54723 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54725 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54728 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54730 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54733 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
54735 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54738 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
54740 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54743 /* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
54745 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54748 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54750 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54753 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
54755 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54758 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
54760 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54763 /* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
54765 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54768 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54770 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54773 /* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54775 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54778 /* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54780 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54783 /* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54785 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54788 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54790 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54793 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54795 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54798 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54800 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54803 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54805 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54808 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54810 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54813 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54815 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54818 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54820 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54823 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54825 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54828 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54830 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54833 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54835 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54838 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54840 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54843 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54845 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54848 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54850 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54853 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54855 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54858 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54860 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54863 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54865 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54868 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54870 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54873 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54875 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54878 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54880 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54883 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54885 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54888 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54890 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54893 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54895 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54898 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54900 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54903 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54905 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54908 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54910 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54913 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54915 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54918 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54920 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54923 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54925 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54928 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54930 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54933 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54935 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54938 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54940 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54943 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
54945 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54948 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54950 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54953 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54955 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54958 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54960 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54963 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
54965 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54968 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54970 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
54971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54973 /* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
54975 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
54976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54978 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54980 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
54981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54983 /* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
54985 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
54986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54988 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54990 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
54991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54993 /* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54995 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
54996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
54998 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
55000 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
55001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55003 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
55005 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
55006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55008 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
55010 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
55011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55013 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
55015 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
55016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55018 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55020 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
55021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55023 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55025 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
55026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55028 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55030 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
55031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55033 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55035 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
55036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55038 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55040 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
55041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55043 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55045 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
55046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55048 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55050 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
55051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55053 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55055 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
55056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55058 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55060 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
55061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55063 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55065 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
55066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55068 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55070 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
55071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55073 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
55075 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
55076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55078 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55080 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
55081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55083 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
55085 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
55086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55088 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
55090 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
55091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55093 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
55095 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
55096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55098 /* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
55100 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
55101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55103 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
55105 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
55106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55108 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
55110 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
55111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55113 /* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
55115 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
55116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55118 /* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
55120 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
55121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55123 /* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
55125 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
55126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55128 /* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55130 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
55131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55133 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55135 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
55136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55138 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55140 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
55141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55143 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55145 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
55146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55148 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55150 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
55151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55153 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55155 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
55156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55158 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55160 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
55161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55163 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55165 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
55166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55168 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55170 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
55171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55173 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55175 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
55176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55178 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
55180 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
55181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55183 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
55185 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
55186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55188 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
55190 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
55191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55193 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
55195 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
55196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55198 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
55200 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
55201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55203 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
55205 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
55206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55208 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
55210 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
55211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55213 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
55215 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
55216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55218 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
55220 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
55221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55223 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
55225 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
55226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55228 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
55230 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
55231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55233 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
55235 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
55236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55238 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
55240 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
55241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55243 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
55245 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
55246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55248 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
55250 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
55251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55253 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
55255 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
55256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55258 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
55260 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
55261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55263 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
55265 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
55266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55268 /* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
55270 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
55271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55273 /* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
55275 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
55276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55278 /* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
55280 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
55281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55283 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55285 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 48,
55286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55288 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
55290 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 48,
55291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55293 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
55295 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 48,
55296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55298 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55300 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 56,
55301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55303 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
55305 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 56,
55306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55308 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
55310 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 56,
55311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55313 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
55315 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 56,
55316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55318 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55320 M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 64,
55321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55323 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
55325 M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 64,
55326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55328 /* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
55330 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
55331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55333 /* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
55335 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
55336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55338 /* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
55340 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
55341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55343 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55345 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 40,
55346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55348 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
55350 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 40,
55351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55353 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
55355 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 40,
55356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55358 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55360 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 48,
55361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55363 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
55365 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 48,
55366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55368 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
55370 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 48,
55371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55373 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
55375 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 48,
55376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55378 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55380 M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 56,
55381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55383 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
55385 M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 56,
55386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55388 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55390 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
55391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55393 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
55395 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
55396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55398 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
55400 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
55401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55403 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55405 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55408 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
55410 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55413 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
55415 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55418 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55420 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55423 /* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
55425 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55428 /* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
55430 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55433 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
55435 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55438 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55440 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55443 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55445 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55448 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
55450 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55453 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55455 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55458 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55460 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55463 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
55465 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55468 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55470 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55473 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55475 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55478 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
55480 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55483 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
55485 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55488 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
55490 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55493 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
55495 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55498 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
55500 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55503 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
55505 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55508 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
55510 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55513 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
55515 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55518 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
55520 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55523 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
55525 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55528 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
55530 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55533 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
55535 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55538 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
55540 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55543 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
55545 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55548 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
55550 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55553 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
55555 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55558 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
55560 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55563 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
55565 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55568 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55570 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55573 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
55575 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55578 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
55580 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55583 /* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
55585 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55588 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55590 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55593 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
55595 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55598 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
55600 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55603 /* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
55605 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55608 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55610 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55613 /* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
55615 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55618 /* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
55620 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55623 /* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
55625 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55628 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
55630 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55633 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55635 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55638 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55640 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55643 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
55645 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55648 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
55650 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55653 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55655 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55658 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55660 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55663 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
55665 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55668 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
55670 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55673 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55675 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55678 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55680 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55683 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
55685 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55688 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
55690 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55693 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
55695 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55698 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
55700 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55703 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
55705 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55708 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
55710 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55713 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
55715 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55718 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
55720 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55723 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
55725 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55728 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
55730 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55733 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
55735 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55738 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
55740 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55743 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
55745 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55748 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
55750 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55753 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
55755 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55758 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
55760 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55763 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
55765 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55768 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
55770 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55773 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
55775 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55778 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
55780 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55783 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
55785 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55788 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
55790 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55793 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
55795 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55798 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
55800 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55803 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
55805 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55808 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55810 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
55811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55813 /* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
55815 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
55816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55818 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55820 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
55821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55823 /* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
55825 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
55826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55828 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55830 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
55831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55833 /* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
55835 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
55836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55838 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
55840 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
55841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55843 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
55845 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
55846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55848 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
55850 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
55851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55853 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
55855 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
55856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55858 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55860 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
55861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55863 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55865 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
55866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55868 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55870 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
55871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55873 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55875 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
55876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55878 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55880 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
55881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55883 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55885 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
55886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55888 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55890 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
55891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55893 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55895 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
55896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55898 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55900 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
55901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55903 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55905 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
55906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55908 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55910 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
55911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55913 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
55915 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
55916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55918 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55920 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
55921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55923 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
55925 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
55926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55928 /* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
55930 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55933 /* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
55935 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55938 /* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
55940 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55943 /* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
55945 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55948 /* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
55950 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55953 /* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
55955 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55958 /* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
55960 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55963 /* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
55965 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55968 /* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55970 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55973 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55975 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55978 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55980 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55983 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55985 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55988 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55990 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55993 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55995 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
55998 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
56000 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
56001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56003 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56005 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
56006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56008 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56010 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
56011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56013 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
56015 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
56016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56018 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
56020 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
56021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56023 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
56025 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
56026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56028 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
56030 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
56031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56033 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
56035 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
56036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56038 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
56040 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
56041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56043 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
56045 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
56046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56048 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
56050 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
56051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56053 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
56055 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
56056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56058 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
56060 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
56061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56063 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
56065 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
56066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56068 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
56070 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
56071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56073 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
56075 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
56076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56078 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
56080 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
56081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56083 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
56085 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
56086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56088 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
56090 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
56091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56093 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
56095 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
56096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56098 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
56100 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
56101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56103 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
56105 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
56106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56108 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56110 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
56111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56113 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
56115 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
56116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56118 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
56120 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
56121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56123 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56125 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
56126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56128 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
56130 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
56131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56133 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
56135 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
56136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56138 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56140 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
56141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56143 /* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
56145 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
56146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56148 /* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
56150 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
56151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56153 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
56155 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
56156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56158 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
56160 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
56161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56163 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
56165 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
56166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56168 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
56170 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
56171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56173 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
56175 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
56176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56178 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
56180 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
56181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56183 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
56185 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
56186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56188 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
56190 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
56191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56193 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
56195 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
56196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56198 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
56200 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
56201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56203 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
56205 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
56206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56208 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
56210 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
56211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56213 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
56215 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
56216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56218 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
56220 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
56221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56223 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
56225 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
56226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56228 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
56230 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
56231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56233 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
56235 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
56236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56238 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
56240 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
56241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56243 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
56245 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
56246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56248 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
56250 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
56251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56253 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
56255 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
56256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56258 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
56260 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
56261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56263 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
56265 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
56266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56268 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
56270 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
56271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56273 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
56275 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
56276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56278 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
56280 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
56281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56283 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
56285 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
56286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56288 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56290 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56293 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
56295 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56298 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
56300 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56303 /* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
56305 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56308 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56310 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56313 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
56315 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56318 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
56320 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56323 /* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
56325 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56328 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56330 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56333 /* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
56335 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56338 /* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
56340 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56343 /* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
56345 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56348 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
56350 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56353 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
56355 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56358 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
56360 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56363 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
56365 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56368 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
56370 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56373 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
56375 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56378 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
56380 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56383 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
56385 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56388 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
56390 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56393 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
56395 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56398 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
56400 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56403 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
56405 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56408 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
56410 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56413 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
56415 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56418 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
56420 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56423 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
56425 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56428 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
56430 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56433 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
56435 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56438 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
56440 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56443 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
56445 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56448 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
56450 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56453 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
56455 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56458 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
56460 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56463 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
56465 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56468 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
56470 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56473 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
56475 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56478 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
56480 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56483 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
56485 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56488 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
56490 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56493 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
56495 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56498 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
56500 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56503 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
56505 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56508 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
56510 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56513 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
56515 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56518 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
56520 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56523 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
56525 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56528 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56530 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
56531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56533 /* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
56535 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
56536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56538 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56540 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
56541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56543 /* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
56545 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
56546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56548 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56550 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
56551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56553 /* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
56555 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
56556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56558 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
56560 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
56561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56563 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
56565 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
56566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56568 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
56570 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
56571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56573 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
56575 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
56576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56578 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
56580 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
56581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56583 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
56585 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
56586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56588 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
56590 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
56591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56593 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
56595 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
56596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56598 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
56600 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
56601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56603 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
56605 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
56606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56608 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
56610 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
56611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56613 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
56615 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
56616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56618 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
56620 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
56621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56623 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
56625 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
56626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56628 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
56630 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
56631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56633 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
56635 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
56636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56638 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
56640 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
56641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56643 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
56645 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
56646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56648 /* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
56650 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56653 /* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
56655 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56658 /* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
56660 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56663 /* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
56665 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56668 /* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
56670 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56673 /* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
56675 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56678 /* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
56680 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56683 /* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
56685 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56688 /* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
56690 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56693 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56695 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56698 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56700 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56703 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
56705 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56708 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56710 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56713 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56715 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56718 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
56720 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56723 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56725 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56728 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56730 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56733 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
56735 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56738 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
56740 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56743 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
56745 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56748 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
56750 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56753 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
56755 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56758 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
56760 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56763 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
56765 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56768 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
56770 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56773 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
56775 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56778 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
56780 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56783 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
56785 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56788 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
56790 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56793 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
56795 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56798 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
56800 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56803 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
56805 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56808 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
56810 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56813 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
56815 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56818 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
56820 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56823 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
56825 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
56828 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
56830 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56833 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
56835 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56838 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
56840 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56843 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
56845 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56848 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
56850 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56853 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
56855 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56858 /* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
56860 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56863 /* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
56865 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56868 /* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
56870 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56873 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
56875 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56878 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
56880 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56883 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
56885 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56888 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
56890 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56893 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
56895 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56898 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
56900 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56903 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
56905 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56908 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
56910 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56913 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
56915 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56918 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
56920 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56923 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
56925 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56928 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
56930 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56933 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
56935 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56938 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
56940 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56943 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
56945 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56948 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
56950 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56953 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
56955 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56958 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
56960 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56963 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
56965 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
56966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56968 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
56970 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
56971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56973 /* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
56975 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "adc.w", 32,
56976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56978 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
56980 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "adc.w", 32,
56981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56983 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
56985 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "adc.w", 32,
56986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56988 /* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
56990 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "adc.w", 32,
56991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56993 /* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
56995 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
56996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
56998 /* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
57000 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
57001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57003 /* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
57005 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "adc.w", 32,
57006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57008 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
57010 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
57011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57013 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
57015 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
57016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57018 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
57020 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
57021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57023 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
57025 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
57026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57028 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
57030 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
57031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57033 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
57035 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
57036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57038 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
57040 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
57041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57043 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57045 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
57046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57048 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57050 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
57051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57053 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
57055 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
57056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57058 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57060 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
57061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57063 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57065 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
57066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57068 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
57070 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
57071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57073 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57075 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
57076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57078 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57080 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
57081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57083 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
57085 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
57086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57088 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57090 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
57091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57093 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
57095 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "adc.w", 48,
57096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57098 /* adc.w${X} $Src16RnHI,$Dst16RnHI */
57100 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
57101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57103 /* adc.w${X} $Src16AnHI,$Dst16RnHI */
57105 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
57106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57108 /* adc.w${X} [$Src16An],$Dst16RnHI */
57110 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "adc.w", 16,
57111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57113 /* adc.w${X} $Src16RnHI,$Dst16AnHI */
57115 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "adc.w", 16,
57116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57118 /* adc.w${X} $Src16AnHI,$Dst16AnHI */
57120 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "adc.w", 16,
57121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57123 /* adc.w${X} [$Src16An],$Dst16AnHI */
57125 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "adc.w", 16,
57126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57128 /* adc.w${X} $Src16RnHI,[$Dst16An] */
57130 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
57131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57133 /* adc.w${X} $Src16AnHI,[$Dst16An] */
57135 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
57136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57138 /* adc.w${X} [$Src16An],[$Dst16An] */
57140 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "adc.w", 16,
57141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57143 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
57145 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
57146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57148 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
57150 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
57151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57153 /* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
57155 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
57156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57158 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
57160 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
57161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57163 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
57165 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
57166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57168 /* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
57170 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
57171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57173 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
57175 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
57176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57178 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
57180 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
57181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57183 /* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
57185 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
57186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57188 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
57190 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
57191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57193 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
57195 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
57196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57198 /* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
57200 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
57201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57203 /* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
57205 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
57206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57208 /* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
57210 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
57211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57213 /* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
57215 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
57216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57218 /* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
57220 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
57221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57223 /* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
57225 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
57226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57228 /* adc.w${X} [$Src16An],${Dsp-16-u16} */
57230 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "adc.w", 32,
57231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57233 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
57235 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
57236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57238 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
57240 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
57241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57243 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
57245 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
57246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57248 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
57250 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "adc.b", 24,
57251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57253 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
57255 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
57256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57258 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
57260 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
57261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57263 /* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
57265 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
57266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57268 /* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
57270 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
57271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57273 /* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
57275 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
57276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57278 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
57280 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
57281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57283 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
57285 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
57286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57288 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
57290 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
57291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57293 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
57295 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
57296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57298 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
57300 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
57301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57303 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
57305 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
57306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57308 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
57310 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
57311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57313 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57315 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
57316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57318 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57320 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
57321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57323 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
57325 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
57326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57328 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57330 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
57331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57333 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57335 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
57336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57338 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
57340 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
57341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57343 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
57345 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
57346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57348 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
57350 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
57351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57353 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
57355 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
57356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57358 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
57360 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
57361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57363 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
57365 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
57366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57368 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
57370 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
57371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57373 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
57375 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
57376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57378 /* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
57380 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "adc.b", 32,
57381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57383 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
57385 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "adc.b", 32,
57386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57388 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
57390 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "adc.b", 32,
57391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57393 /* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
57395 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "adc.b", 32,
57396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57398 /* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
57400 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
57401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57403 /* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
57405 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
57406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57408 /* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
57410 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "adc.b", 32,
57411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57413 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
57415 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57418 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
57420 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57423 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
57425 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57428 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
57430 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57433 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
57435 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57438 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
57440 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57443 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
57445 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57448 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57450 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57453 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57455 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57458 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
57460 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57463 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57465 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57468 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57470 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57473 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
57475 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57478 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57480 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57483 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57485 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57488 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
57490 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57493 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57495 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57498 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
57500 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57503 /* adc.b${X} $Src16RnQI,$Dst16RnQI */
57505 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
57506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57508 /* adc.b${X} $Src16AnQI,$Dst16RnQI */
57510 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
57511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57513 /* adc.b${X} [$Src16An],$Dst16RnQI */
57515 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "adc.b", 16,
57516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57518 /* adc.b${X} $Src16RnQI,$Dst16AnQI */
57520 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "adc.b", 16,
57521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57523 /* adc.b${X} $Src16AnQI,$Dst16AnQI */
57525 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "adc.b", 16,
57526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57528 /* adc.b${X} [$Src16An],$Dst16AnQI */
57530 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "adc.b", 16,
57531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57533 /* adc.b${X} $Src16RnQI,[$Dst16An] */
57535 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
57536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57538 /* adc.b${X} $Src16AnQI,[$Dst16An] */
57540 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
57541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57543 /* adc.b${X} [$Src16An],[$Dst16An] */
57545 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "adc.b", 16,
57546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57548 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
57550 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57553 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
57555 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57558 /* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
57560 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57563 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
57565 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57568 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
57570 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57573 /* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
57575 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57578 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
57580 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57583 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
57585 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57588 /* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
57590 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57593 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
57595 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57598 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
57600 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57603 /* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
57605 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57608 /* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
57610 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57613 /* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
57615 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57618 /* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
57620 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57623 /* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
57625 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57628 /* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
57630 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57633 /* adc.b${X} [$Src16An],${Dsp-16-u16} */
57635 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57638 /* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
57640 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
57641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57643 /* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
57645 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "adc.w", 40,
57646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57648 /* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
57650 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
57651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57653 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57655 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 48,
57656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57658 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
57660 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 48,
57661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57663 /* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
57665 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 48,
57666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57668 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57670 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 56,
57671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57673 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
57675 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 56,
57676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57678 /* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
57680 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 56,
57681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57683 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
57685 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "adc.w", 56,
57686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57688 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57690 M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 64,
57691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57693 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
57695 M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "adc.w", 64,
57696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57698 /* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
57700 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
57701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57703 /* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
57705 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "adc.b", 32,
57706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57708 /* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
57710 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
57711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57713 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57715 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 40,
57716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57718 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
57720 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 40,
57721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57723 /* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
57725 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 40,
57726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57728 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57730 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 48,
57731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57733 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
57735 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 48,
57736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57738 /* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
57740 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 48,
57741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57743 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
57745 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "adc.b", 48,
57746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57748 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57750 M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 56,
57751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57753 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
57755 M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "adc.b", 56,
57756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57758 /* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
57760 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-Rn-direct-HI", "adc.w", 32,
57761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57763 /* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
57765 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-An-direct-HI", "adc.w", 32,
57766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57768 /* adc.w${X} #${Imm-16-HI},[$Dst16An] */
57770 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "adc16.w-imm-G-basic-dst16-An-indirect-HI", "adc.w", 32,
57771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57773 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
57775 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "adc.w", 40,
57776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57778 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
57780 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "adc.w", 40,
57781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57783 /* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
57785 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "adc.w", 40,
57786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57788 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
57790 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "adc.w", 48,
57791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57793 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
57795 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "adc.w", 48,
57796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57798 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
57800 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "adc16.w-imm-G-16-16-dst16-16-16-absolute-HI", "adc.w", 48,
57801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57803 /* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
57805 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-Rn-direct-QI", "adc.b", 24,
57806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57808 /* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
57810 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-An-direct-QI", "adc.b", 24,
57811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57813 /* adc.b${X} #${Imm-16-QI},[$Dst16An] */
57815 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "adc16.b-imm-G-basic-dst16-An-indirect-QI", "adc.b", 24,
57816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57818 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
57820 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "adc.b", 32,
57821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57823 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
57825 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "adc.b", 32,
57826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57828 /* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
57830 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "adc.b", 32,
57831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57833 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
57835 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "adc.b", 40,
57836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57838 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
57840 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "adc.b", 40,
57841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57843 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
57845 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "adc16.b-imm-G-16-16-dst16-16-16-absolute-QI", "adc.b", 40,
57846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
57848 /* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
57850 M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "add.w", 32,
57851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57853 /* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
57855 M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "add.w", 32,
57856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57858 /* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
57860 M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "add32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "add.w", 40,
57861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57863 /* add.w${S} #${Imm-8-HI},r0 */
57865 M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "add32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "add.w", 24,
57866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57868 /* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
57870 M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "add.b", 24,
57871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57873 /* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
57875 M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "add.b", 24,
57876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57878 /* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
57880 M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "add32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "add.b", 32,
57881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57883 /* add.b${S} #${Imm-8-QI},r0l */
57885 M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "add32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "add.b", 16,
57886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57888 /* add.l${S} #${Imm1-S},a0 */
57890 M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A0-direct-HI", "add.l", 8,
57891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57893 /* add.l${S} #${Imm1-S},a1 */
57895 M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A1-direct-HI", "add.l", 8,
57896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57898 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57900 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57903 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
57905 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57908 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
57910 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57913 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57915 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57918 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
57920 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57923 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
57925 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57928 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57930 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57933 /* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57935 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57938 /* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
57940 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57943 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57945 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57948 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57950 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57953 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57955 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57958 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57960 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57963 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57965 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57968 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57970 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57973 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57975 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57978 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57980 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57983 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57985 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57988 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
57990 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57993 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57995 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
57998 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58000 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
58001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58003 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58005 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
58006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58008 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58010 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
58011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58013 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58015 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
58016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58018 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58020 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
58021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58023 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58025 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
58026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58028 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58030 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
58031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58033 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58035 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
58036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58038 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58040 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
58041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58043 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58045 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
58046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58048 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58050 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
58051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58053 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58055 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
58056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58058 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58060 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
58061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58063 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58065 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
58066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58068 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58070 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
58071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58073 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58075 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
58076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58078 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58080 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58083 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
58085 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58088 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
58090 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58093 /* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
58095 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58098 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58100 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58103 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
58105 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58108 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
58110 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58113 /* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
58115 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58118 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58120 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58123 /* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58125 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58128 /* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58130 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58133 /* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58135 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58138 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58140 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58143 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58145 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58148 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58150 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58153 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58155 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58158 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58160 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58163 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58165 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58168 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58170 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58173 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58175 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58178 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58180 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58183 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58185 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58188 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58190 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58193 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58195 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58198 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58200 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58203 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58205 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58208 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58210 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58213 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58215 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58218 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58220 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58223 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58225 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58228 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58230 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58233 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58235 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58238 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58240 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58243 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58245 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58248 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58250 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58253 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58255 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58258 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58260 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58263 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58265 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58268 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58270 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58273 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58275 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58278 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58280 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58283 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58285 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58288 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58290 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58293 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
58295 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58298 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
58300 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58303 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
58305 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58308 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
58310 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58313 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
58315 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58318 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58320 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
58321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58323 /* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
58325 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
58326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58328 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58330 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
58331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58333 /* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
58335 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
58336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58338 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58340 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
58341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58343 /* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
58345 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
58346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58348 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
58350 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
58351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58353 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
58355 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
58356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58358 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
58360 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
58361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58363 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
58365 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
58366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58368 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
58370 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
58371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58373 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
58375 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
58376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58378 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
58380 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
58381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58383 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
58385 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
58386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58388 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
58390 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
58391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58393 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
58395 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
58396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58398 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
58400 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
58401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58403 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
58405 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
58406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58408 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
58410 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
58411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58413 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
58415 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
58416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58418 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
58420 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
58421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58423 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
58425 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
58426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58428 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
58430 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
58431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58433 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
58435 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
58436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58438 /* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
58440 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58443 /* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
58445 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58448 /* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58450 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58453 /* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
58455 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58458 /* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
58460 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58463 /* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58465 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58468 /* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
58470 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58473 /* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
58475 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58478 /* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58480 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58483 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58485 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58488 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58490 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58493 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
58495 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58498 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58500 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58503 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58505 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58508 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
58510 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58513 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58515 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58518 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58520 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58523 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
58525 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58528 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
58530 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58533 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
58535 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58538 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
58540 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58543 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
58545 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58548 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
58550 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58553 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
58555 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58558 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
58560 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58563 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
58565 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58568 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
58570 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58573 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
58575 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58578 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
58580 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58583 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
58585 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58588 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
58590 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58593 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
58595 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58598 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
58600 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58603 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
58605 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58608 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
58610 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58613 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
58615 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58618 /* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
58620 M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "add16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "add.b", 8,
58621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
58623 /* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
58625 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-SB-relative-QI", "add.b", 16,
58626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
58628 /* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
58630 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-FB-relative-QI", "add.b", 16,
58631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
58633 /* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
58635 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "add16.b.S-src2-src16-2-S-16-absolute-QI", "add.b", 24,
58636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
58638 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58640 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58643 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
58645 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58648 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
58650 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58653 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58655 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58658 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
58660 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58663 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
58665 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58668 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58670 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58673 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
58675 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58678 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58680 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58683 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58685 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58688 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58690 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58693 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58695 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58698 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58700 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58703 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58705 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58708 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58710 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58713 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58715 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58718 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58720 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58723 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58725 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58728 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58730 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58733 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58735 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58738 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58740 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58743 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58745 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58748 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58750 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58753 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58755 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58758 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58760 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58763 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58765 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58768 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58770 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58773 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58775 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58778 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58780 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58783 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58785 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58788 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58790 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58793 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58795 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58798 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58800 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58803 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58805 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58808 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58810 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58813 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58815 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58818 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58820 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58823 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
58825 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58828 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
58830 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58833 /* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
58835 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58838 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58840 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58843 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
58845 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58848 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
58850 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58853 /* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
58855 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58858 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58860 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58863 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58865 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58868 /* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58870 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58873 /* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58875 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58878 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58880 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58883 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58885 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58888 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58890 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58893 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58895 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58898 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58900 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58903 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58905 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58908 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58910 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58913 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58915 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58918 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58920 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58923 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58925 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58928 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58930 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58933 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58935 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58938 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58940 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58943 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58945 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58948 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58950 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58953 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58955 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58958 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58960 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58963 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58965 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58968 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58970 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58973 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58975 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58978 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58980 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58983 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58985 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58988 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58990 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58993 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58995 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
58998 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
59000 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
59001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59003 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
59005 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
59006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59008 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
59010 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
59011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59013 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
59015 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
59016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59018 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59020 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
59021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59023 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59025 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
59026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59028 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59030 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
59031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59033 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
59035 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
59036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59038 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59040 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59043 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59045 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59048 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59050 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59053 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
59055 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59058 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
59060 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
59061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59063 /* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
59065 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
59066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59068 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
59070 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
59071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59073 /* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
59075 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
59076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59078 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59080 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
59081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59083 /* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59085 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
59086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59088 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59090 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
59091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59093 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59095 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
59096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59098 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59100 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
59101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59103 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59105 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
59106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59108 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59110 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
59111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59113 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59115 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
59116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59118 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59120 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
59121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59123 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59125 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
59126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59128 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59130 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
59131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59133 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59135 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
59136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59138 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59140 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
59141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59143 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59145 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
59146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59148 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59150 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
59151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59153 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59155 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
59156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59158 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59160 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
59161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59163 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
59165 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
59166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59168 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59170 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
59171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59173 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
59175 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
59176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59178 /* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
59180 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
59181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59183 /* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
59185 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
59186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59188 /* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
59190 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
59191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59193 /* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
59195 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
59196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59198 /* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
59200 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
59201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59203 /* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
59205 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
59206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59208 /* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
59210 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
59211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59213 /* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
59215 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
59216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59218 /* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59220 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
59221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59223 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59225 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
59226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59228 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59230 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
59231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59233 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59235 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
59236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59238 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59240 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
59241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59243 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59245 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
59246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59248 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59250 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
59251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59253 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59255 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
59256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59258 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59260 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
59261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59263 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59265 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
59266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59268 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
59270 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
59271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59273 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
59275 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
59276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59278 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59280 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
59281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59283 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
59285 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
59286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59288 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
59290 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
59291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59293 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59295 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
59296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59298 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
59300 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
59301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59303 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
59305 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
59306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59308 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
59310 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
59311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59313 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
59315 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
59316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59318 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
59320 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
59321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59323 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
59325 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
59326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59328 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
59330 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
59331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59333 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
59335 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
59336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59338 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
59340 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
59341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59343 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
59345 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
59346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59348 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
59350 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
59351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59353 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
59355 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
59356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59358 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59360 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
59361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59363 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
59365 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
59366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59368 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
59370 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
59371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59373 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59375 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
59376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59378 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
59380 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
59381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59383 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
59385 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
59386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59388 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59390 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
59391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59393 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
59395 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
59396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59398 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
59400 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
59401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59403 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59405 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59408 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59410 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59413 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59415 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59418 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59420 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59423 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59425 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59428 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59430 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59433 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59435 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59438 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59440 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59443 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59445 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59448 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
59450 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59453 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59455 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59458 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59460 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59463 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
59465 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59468 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59470 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59473 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59475 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59478 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
59480 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59483 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59485 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59488 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59490 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59493 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
59495 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59498 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
59500 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59503 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
59505 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59508 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
59510 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59513 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59515 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59518 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59520 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59523 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
59525 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59528 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
59530 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59533 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
59535 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59538 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59540 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59543 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
59545 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59548 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
59550 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59553 /* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
59555 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59558 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59560 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59563 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
59565 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59568 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
59570 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59573 /* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
59575 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59578 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59580 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59583 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
59585 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59588 /* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
59590 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59593 /* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
59595 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59598 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59600 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59603 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59605 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59608 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59610 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59613 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
59615 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59618 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59620 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59623 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59625 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59628 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59630 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59633 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
59635 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59638 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59640 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59643 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59645 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59648 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59650 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59653 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
59655 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59658 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
59660 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59663 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59665 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59668 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
59670 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59673 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59675 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59678 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
59680 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59683 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59685 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59688 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
59690 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59693 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59695 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59698 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
59700 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59703 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59705 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59708 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
59710 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59713 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59715 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59718 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
59720 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59723 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
59725 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59728 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
59730 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59733 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
59735 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59738 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59740 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59743 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59745 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59748 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59750 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59753 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
59755 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59758 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59760 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59763 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59765 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59768 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59770 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59773 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
59775 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59778 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59780 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
59781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59783 /* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
59785 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
59786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59788 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59790 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
59791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59793 /* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
59795 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
59796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59798 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59800 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
59801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59803 /* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59805 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
59806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59808 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59810 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
59811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59813 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59815 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
59816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59818 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59820 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
59821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59823 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59825 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
59826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59828 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59830 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
59831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59833 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59835 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
59836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59838 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59840 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
59841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59843 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59845 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
59846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59848 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59850 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
59851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59853 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59855 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
59856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59858 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59860 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
59861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59863 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59865 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
59866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59868 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59870 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
59871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59873 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59875 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
59876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59878 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59880 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
59881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59883 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
59885 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
59886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59888 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59890 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
59891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59893 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
59895 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
59896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59898 /* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
59900 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59903 /* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
59905 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59908 /* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59910 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59913 /* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
59915 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59918 /* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
59920 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59923 /* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59925 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59928 /* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
59930 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59933 /* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
59935 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59938 /* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59940 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59943 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59945 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59948 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59950 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59953 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59955 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59958 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59960 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59963 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59965 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59968 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59970 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59973 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59975 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59978 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59980 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59983 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59985 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59988 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
59990 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59993 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
59995 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
59998 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
60000 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
60001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60003 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
60005 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
60006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60008 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
60010 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
60011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60013 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
60015 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
60016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60018 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
60020 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
60021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60023 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
60025 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
60026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60028 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
60030 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
60031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60033 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
60035 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60038 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
60040 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60043 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
60045 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60048 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
60050 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60053 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
60055 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60058 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
60060 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60063 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
60065 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60068 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
60070 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60073 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
60075 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60078 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
60080 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
60081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60083 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
60085 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
60086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60088 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
60090 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
60091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60093 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
60095 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "add.w", 24,
60096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60098 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
60100 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "add.w", 24,
60101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60103 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
60105 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "add.w", 24,
60106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60108 /* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60110 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "add.w", 24,
60111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60113 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60115 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
60116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60118 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60120 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
60121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60123 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60125 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
60126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60128 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60130 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
60131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60133 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60135 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
60136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60138 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60140 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
60141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60143 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60145 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
60146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60148 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60150 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
60151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60153 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60155 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
60156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60158 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60160 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
60161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60163 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60165 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
60166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60168 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60170 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
60171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60173 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60175 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
60176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60178 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60180 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
60181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60183 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60185 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
60186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60188 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60190 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
60191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60193 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60195 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
60196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60198 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60200 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
60201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60203 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60205 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
60206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60208 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60210 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
60211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60213 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
60215 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
60216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60218 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
60220 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
60221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60223 /* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
60225 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "add.w", 32,
60226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60228 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
60230 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "add.w", 32,
60231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60233 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
60235 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "add.w", 32,
60236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60238 /* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
60240 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "add.w", 32,
60241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60243 /* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60245 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "add.w", 32,
60246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60248 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60250 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "add.w", 32,
60251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60253 /* add.w${G} ${Dsp-16-u16},[$Dst16An] */
60255 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "add.w", 32,
60256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60258 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60260 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
60261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60263 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60265 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
60266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60268 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60270 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "add.w", 40,
60271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60273 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60275 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
60276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60278 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60280 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
60281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60283 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60285 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "add.w", 48,
60286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60288 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60290 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
60291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60293 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60295 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
60296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60298 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60300 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
60301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60303 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60305 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
60306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60308 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60310 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
60311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60313 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60315 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
60316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60318 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60320 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
60321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60323 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60325 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
60326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60328 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60330 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
60331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60333 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60335 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
60336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60338 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60340 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
60341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60343 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
60345 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "add.w", 48,
60346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60348 /* add.w${G} $Src16RnHI,$Dst16RnHI */
60350 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
60351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60353 /* add.w${G} $Src16AnHI,$Dst16RnHI */
60355 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
60356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60358 /* add.w${G} [$Src16An],$Dst16RnHI */
60360 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "add.w", 16,
60361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60363 /* add.w${G} $Src16RnHI,$Dst16AnHI */
60365 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "add.w", 16,
60366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60368 /* add.w${G} $Src16AnHI,$Dst16AnHI */
60370 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "add.w", 16,
60371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60373 /* add.w${G} [$Src16An],$Dst16AnHI */
60375 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "add.w", 16,
60376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60378 /* add.w${G} $Src16RnHI,[$Dst16An] */
60380 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "add.w", 16,
60381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60383 /* add.w${G} $Src16AnHI,[$Dst16An] */
60385 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "add.w", 16,
60386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60388 /* add.w${G} [$Src16An],[$Dst16An] */
60390 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "add.w", 16,
60391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60393 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
60395 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60398 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
60400 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60403 /* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60405 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60408 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
60410 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60413 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
60415 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60418 /* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60420 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60423 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
60425 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60428 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
60430 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60433 /* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
60435 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60438 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
60440 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60443 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
60445 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60448 /* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
60450 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60453 /* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
60455 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60458 /* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
60460 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60463 /* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
60465 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60468 /* add.w${G} $Src16RnHI,${Dsp-16-u16} */
60470 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
60471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60473 /* add.w${G} $Src16AnHI,${Dsp-16-u16} */
60475 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
60476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60478 /* add.w${G} [$Src16An],${Dsp-16-u16} */
60480 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "add.w", 32,
60481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60483 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
60485 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60488 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
60490 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60493 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
60495 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60498 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
60500 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "add.b", 24,
60501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60503 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
60505 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "add.b", 24,
60506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60508 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
60510 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "add.b", 24,
60511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60513 /* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60515 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60518 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60520 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60523 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60525 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60528 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60530 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60533 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60535 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60538 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60540 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60543 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60545 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60548 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60550 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60553 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60555 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60558 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60560 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60563 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60565 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60568 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60570 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60573 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60575 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60578 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60580 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60583 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60585 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60588 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60590 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60593 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60595 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60598 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60600 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60603 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60605 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60608 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60610 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60613 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60615 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60618 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
60620 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
60621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60623 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
60625 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
60626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60628 /* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
60630 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "add.b", 32,
60631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60633 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
60635 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "add.b", 32,
60636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60638 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
60640 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "add.b", 32,
60641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60643 /* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
60645 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "add.b", 32,
60646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60648 /* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60650 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "add.b", 32,
60651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60653 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60655 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "add.b", 32,
60656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60658 /* add.b${G} ${Dsp-16-u16},[$Dst16An] */
60660 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "add.b", 32,
60661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60663 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60665 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60668 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60670 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60673 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60675 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60678 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60680 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60683 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60685 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60688 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60690 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60693 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60695 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60698 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60700 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60703 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60705 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60708 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60710 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60713 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60715 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60718 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60720 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60723 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60725 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60728 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60730 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60733 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60735 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60738 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60740 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
60741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60743 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60745 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
60746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60748 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
60750 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "add.b", 48,
60751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60753 /* add.b${G} $Src16RnQI,$Dst16RnQI */
60755 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
60756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60758 /* add.b${G} $Src16AnQI,$Dst16RnQI */
60760 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
60761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60763 /* add.b${G} [$Src16An],$Dst16RnQI */
60765 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "add.b", 16,
60766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60768 /* add.b${G} $Src16RnQI,$Dst16AnQI */
60770 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "add.b", 16,
60771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60773 /* add.b${G} $Src16AnQI,$Dst16AnQI */
60775 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "add.b", 16,
60776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60778 /* add.b${G} [$Src16An],$Dst16AnQI */
60780 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "add.b", 16,
60781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60783 /* add.b${G} $Src16RnQI,[$Dst16An] */
60785 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "add.b", 16,
60786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60788 /* add.b${G} $Src16AnQI,[$Dst16An] */
60790 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "add.b", 16,
60791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60793 /* add.b${G} [$Src16An],[$Dst16An] */
60795 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "add.b", 16,
60796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60798 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
60800 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60803 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
60805 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60808 /* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60810 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60813 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
60815 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60818 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
60820 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60823 /* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60825 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60828 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
60830 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60833 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
60835 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60838 /* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
60840 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60843 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
60845 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60848 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
60850 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60853 /* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
60855 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60858 /* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
60860 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60863 /* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
60865 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60868 /* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
60870 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60873 /* add.b${G} $Src16RnQI,${Dsp-16-u16} */
60875 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
60876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60878 /* add.b${G} $Src16AnQI,${Dsp-16-u16} */
60880 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
60881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60883 /* add.b${G} [$Src16An],${Dsp-16-u16} */
60885 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "add.b", 32,
60886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60888 /* add.b${S} #${Imm-8-QI},r0l */
60890 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "add.b", 16,
60891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60893 /* add.b${S} #${Imm-8-QI},r0h */
60895 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "add.b", 16,
60896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60898 /* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
60900 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "add.b", 24,
60901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60903 /* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
60905 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "add.b", 24,
60906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60908 /* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
60910 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "add.b", 32,
60911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
60913 /* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
60915 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
60916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60918 /* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
60920 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 16,
60921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60923 /* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60925 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
60926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60928 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60930 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
60931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60933 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60935 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
60936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60938 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60940 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
60941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60943 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60945 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
60946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60948 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60950 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
60951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60953 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60955 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
60956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60958 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60960 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
60961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60963 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
60965 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
60966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60968 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
60970 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
60971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60973 /* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
60975 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
60976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60978 /* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
60980 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 16,
60981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60983 /* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60985 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
60986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60988 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60990 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
60991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60993 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60995 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
60996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
60998 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61000 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
61001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61003 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
61005 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
61006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61008 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
61010 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
61011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61013 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
61015 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
61016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61018 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
61020 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
61021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61023 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
61025 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
61026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61028 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
61030 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
61031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61033 /* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
61035 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
61036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61038 /* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
61040 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 16,
61041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61043 /* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
61045 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
61046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61048 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61050 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
61051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61053 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61055 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
61056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61058 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61060 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
61061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61063 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
61065 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
61066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61068 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
61070 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
61071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61073 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
61075 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
61076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61078 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
61080 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
61081 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61083 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
61085 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
61086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61088 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
61090 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
61091 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61093 /* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
61095 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-Rn-direct-HI", "add.w", 16,
61096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61098 /* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
61100 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-An-direct-HI", "add.w", 16,
61101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61103 /* add.w${Q} #${Imm-8-s4},[$Dst16An] */
61105 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "add16.w-imm4-Q-16-dst16-An-indirect-HI", "add.w", 16,
61106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61108 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
61110 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "add.w", 24,
61111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61113 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
61115 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "add.w", 32,
61116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61118 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
61120 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "add.w", 24,
61121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61123 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
61125 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "add.w", 32,
61126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61128 /* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
61130 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "add.w", 24,
61131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61133 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
61135 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm4-Q-16-dst16-16-16-absolute-HI", "add.w", 32,
61136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61138 /* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
61140 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-Rn-direct-QI", "add.b", 16,
61141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61143 /* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
61145 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-An-direct-QI", "add.b", 16,
61146 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61148 /* add.b${Q} #${Imm-8-s4},[$Dst16An] */
61150 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "add16.b-imm4-Q-16-dst16-An-indirect-QI", "add.b", 16,
61151 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61153 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
61155 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "add.b", 24,
61156 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61158 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
61160 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "add.b", 32,
61161 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61163 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
61165 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "add.b", 24,
61166 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61168 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
61170 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "add.b", 32,
61171 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61173 /* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
61175 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "add.b", 24,
61176 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61178 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
61180 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm4-Q-16-dst16-16-16-absolute-QI", "add.b", 32,
61181 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61183 /* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
61185 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
61186 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61188 /* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
61190 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 32,
61191 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61193 /* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
61195 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
61196 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61198 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61200 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 40,
61201 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61203 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61205 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 40,
61206 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61208 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61210 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 40,
61211 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61213 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61215 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 48,
61216 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61218 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61220 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 48,
61221 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61223 /* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
61225 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 48,
61226 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61228 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61230 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 48,
61231 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61233 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61235 M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 56,
61236 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61238 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
61240 M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 56,
61241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61243 /* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
61245 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
61246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61248 /* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
61250 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 24,
61251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61253 /* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
61255 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
61256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61258 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61260 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 32,
61261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61263 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61265 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 32,
61266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61268 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61270 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 32,
61271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61273 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61275 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 40,
61276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61278 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61280 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 40,
61281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61283 /* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
61285 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 40,
61286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61288 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61290 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 40,
61291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61293 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61295 M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 48,
61296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61298 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
61300 M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 48,
61301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61303 /* add.w${G} #${Imm-16-HI},$Dst16RnHI */
61305 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "add16.w-imm-G-basic-dst16-Rn-direct-HI", "add.w", 32,
61306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61308 /* add.w${G} #${Imm-16-HI},$Dst16AnHI */
61310 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "add16.w-imm-G-basic-dst16-An-direct-HI", "add.w", 32,
61311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61313 /* add.w${G} #${Imm-16-HI},[$Dst16An] */
61315 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "add16.w-imm-G-basic-dst16-An-indirect-HI", "add.w", 32,
61316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61318 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
61320 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "add.w", 40,
61321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61323 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61325 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "add.w", 40,
61326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61328 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61330 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "add.w", 40,
61331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61333 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
61335 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "add.w", 48,
61336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61338 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61340 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "add.w", 48,
61341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61343 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61345 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm-G-16-16-dst16-16-16-absolute-HI", "add.w", 48,
61346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61348 /* add.b${G} #${Imm-16-QI},$Dst16RnQI */
61350 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "add16.b-imm-G-basic-dst16-Rn-direct-QI", "add.b", 24,
61351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61353 /* add.b${G} #${Imm-16-QI},$Dst16AnQI */
61355 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "add16.b-imm-G-basic-dst16-An-direct-QI", "add.b", 24,
61356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61358 /* add.b${G} #${Imm-16-QI},[$Dst16An] */
61360 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "add16.b-imm-G-basic-dst16-An-indirect-QI", "add.b", 24,
61361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61363 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
61365 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "add.b", 32,
61366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61368 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61370 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "add.b", 32,
61371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61373 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61375 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "add.b", 32,
61376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61378 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
61380 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "add.b", 40,
61381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61383 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61385 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "add.b", 40,
61386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61388 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61390 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm-G-16-16-dst16-16-16-absolute-QI", "add.b", 40,
61391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61393 /* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
61395 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 48,
61396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61398 /* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
61400 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 48,
61401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61403 /* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
61405 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 48,
61406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61408 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61410 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 56,
61411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61413 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
61415 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 56,
61416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61418 /* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
61420 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 56,
61421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61423 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61425 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 64,
61426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61428 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
61430 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 64,
61431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61433 /* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
61435 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 64,
61436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61438 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
61440 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 64,
61441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61443 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61445 M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 72,
61446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61448 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
61450 M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 72,
61451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61453 /* adcf.w $Dst32RnUnprefixedHI */
61455 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adcf.w", 16,
61456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61458 /* adcf.w $Dst32AnUnprefixedHI */
61460 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "adcf.w", 16,
61461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61463 /* adcf.w [$Dst32AnUnprefixed] */
61465 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adcf.w", 16,
61466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61468 /* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61470 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adcf.w", 24,
61471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61473 /* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61475 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adcf.w", 32,
61476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61478 /* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61480 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adcf.w", 40,
61481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61483 /* adcf.w ${Dsp-16-u8}[sb] */
61485 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adcf.w", 24,
61486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61488 /* adcf.w ${Dsp-16-u16}[sb] */
61490 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adcf.w", 32,
61491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61493 /* adcf.w ${Dsp-16-s8}[fb] */
61495 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adcf.w", 24,
61496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61498 /* adcf.w ${Dsp-16-s16}[fb] */
61500 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adcf.w", 32,
61501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61503 /* adcf.w ${Dsp-16-u16} */
61505 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adcf.w", 32,
61506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61508 /* adcf.w ${Dsp-16-u24} */
61510 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adcf.w", 40,
61511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61513 /* adcf.b $Dst32RnUnprefixedQI */
61515 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adcf.b", 16,
61516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61518 /* adcf.b $Dst32AnUnprefixedQI */
61520 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "adcf.b", 16,
61521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61523 /* adcf.b [$Dst32AnUnprefixed] */
61525 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adcf.b", 16,
61526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61528 /* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61530 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adcf.b", 24,
61531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61533 /* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61535 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adcf.b", 32,
61536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61538 /* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61540 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adcf.b", 40,
61541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61543 /* adcf.b ${Dsp-16-u8}[sb] */
61545 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adcf.b", 24,
61546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61548 /* adcf.b ${Dsp-16-u16}[sb] */
61550 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adcf.b", 32,
61551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61553 /* adcf.b ${Dsp-16-s8}[fb] */
61555 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adcf.b", 24,
61556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61558 /* adcf.b ${Dsp-16-s16}[fb] */
61560 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adcf.b", 32,
61561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61563 /* adcf.b ${Dsp-16-u16} */
61565 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adcf.b", 32,
61566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61568 /* adcf.b ${Dsp-16-u24} */
61570 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adcf.b", 40,
61571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61573 /* adcf.w $Dst16RnHI */
61575 M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, "adcf16.w-16-dst16-Rn-direct-HI", "adcf.w", 16,
61576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61578 /* adcf.w $Dst16AnHI */
61580 M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, "adcf16.w-16-dst16-An-direct-HI", "adcf.w", 16,
61581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61583 /* adcf.w [$Dst16An] */
61585 M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, "adcf16.w-16-dst16-An-indirect-HI", "adcf.w", 16,
61586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61588 /* adcf.w ${Dsp-16-u8}[$Dst16An] */
61590 M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-8-An-relative-HI", "adcf.w", 24,
61591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61593 /* adcf.w ${Dsp-16-u16}[$Dst16An] */
61595 M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-16-An-relative-HI", "adcf.w", 32,
61596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61598 /* adcf.w ${Dsp-16-u8}[sb] */
61600 M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-SB-relative-HI", "adcf.w", 24,
61601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61603 /* adcf.w ${Dsp-16-u16}[sb] */
61605 M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-16-SB-relative-HI", "adcf.w", 32,
61606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61608 /* adcf.w ${Dsp-16-s8}[fb] */
61610 M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-FB-relative-HI", "adcf.w", 24,
61611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61613 /* adcf.w ${Dsp-16-u16} */
61615 M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, "adcf16.w-16-dst16-16-16-absolute-HI", "adcf.w", 32,
61616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61618 /* adcf.b $Dst16RnQI */
61620 M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, "adcf16.b-16-dst16-Rn-direct-QI", "adcf.b", 16,
61621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61623 /* adcf.b $Dst16AnQI */
61625 M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, "adcf16.b-16-dst16-An-direct-QI", "adcf.b", 16,
61626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61628 /* adcf.b [$Dst16An] */
61630 M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, "adcf16.b-16-dst16-An-indirect-QI", "adcf.b", 16,
61631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61633 /* adcf.b ${Dsp-16-u8}[$Dst16An] */
61635 M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-8-An-relative-QI", "adcf.b", 24,
61636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61638 /* adcf.b ${Dsp-16-u16}[$Dst16An] */
61640 M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-16-An-relative-QI", "adcf.b", 32,
61641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61643 /* adcf.b ${Dsp-16-u8}[sb] */
61645 M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-SB-relative-QI", "adcf.b", 24,
61646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61648 /* adcf.b ${Dsp-16-u16}[sb] */
61650 M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-16-SB-relative-QI", "adcf.b", 32,
61651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61653 /* adcf.b ${Dsp-16-s8}[fb] */
61655 M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-FB-relative-QI", "adcf.b", 24,
61656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61658 /* adcf.b ${Dsp-16-u16} */
61660 M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, "adcf16.b-16-dst16-16-16-absolute-QI", "adcf.b", 32,
61661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61663 /* abs.w $Dst32RnUnprefixedHI */
61665 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "abs.w", 16,
61666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61668 /* abs.w $Dst32AnUnprefixedHI */
61670 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "abs.w", 16,
61671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61673 /* abs.w [$Dst32AnUnprefixed] */
61675 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "abs.w", 16,
61676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61678 /* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61680 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "abs.w", 24,
61681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61683 /* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61685 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "abs.w", 32,
61686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61688 /* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61690 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "abs.w", 40,
61691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61693 /* abs.w ${Dsp-16-u8}[sb] */
61695 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "abs.w", 24,
61696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61698 /* abs.w ${Dsp-16-u16}[sb] */
61700 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "abs.w", 32,
61701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61703 /* abs.w ${Dsp-16-s8}[fb] */
61705 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "abs.w", 24,
61706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61708 /* abs.w ${Dsp-16-s16}[fb] */
61710 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "abs.w", 32,
61711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61713 /* abs.w ${Dsp-16-u16} */
61715 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "abs.w", 32,
61716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61718 /* abs.w ${Dsp-16-u24} */
61720 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "abs.w", 40,
61721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61723 /* abs.b $Dst32RnUnprefixedQI */
61725 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "abs.b", 16,
61726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61728 /* abs.b $Dst32AnUnprefixedQI */
61730 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "abs.b", 16,
61731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61733 /* abs.b [$Dst32AnUnprefixed] */
61735 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "abs.b", 16,
61736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61738 /* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61740 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "abs.b", 24,
61741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61743 /* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61745 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "abs.b", 32,
61746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61748 /* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61750 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "abs.b", 40,
61751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61753 /* abs.b ${Dsp-16-u8}[sb] */
61755 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "abs.b", 24,
61756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61758 /* abs.b ${Dsp-16-u16}[sb] */
61760 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "abs.b", 32,
61761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61763 /* abs.b ${Dsp-16-s8}[fb] */
61765 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "abs.b", 24,
61766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61768 /* abs.b ${Dsp-16-s16}[fb] */
61770 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "abs.b", 32,
61771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61773 /* abs.b ${Dsp-16-u16} */
61775 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "abs.b", 32,
61776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61778 /* abs.b ${Dsp-16-u24} */
61780 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "abs.b", 40,
61781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61783 /* abs.w $Dst16RnHI */
61785 M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, "abs16.w-16-dst16-Rn-direct-HI", "abs.w", 16,
61786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61788 /* abs.w $Dst16AnHI */
61790 M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, "abs16.w-16-dst16-An-direct-HI", "abs.w", 16,
61791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61793 /* abs.w [$Dst16An] */
61795 M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, "abs16.w-16-dst16-An-indirect-HI", "abs.w", 16,
61796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61798 /* abs.w ${Dsp-16-u8}[$Dst16An] */
61800 M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, "abs16.w-16-dst16-16-8-An-relative-HI", "abs.w", 24,
61801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61803 /* abs.w ${Dsp-16-u16}[$Dst16An] */
61805 M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, "abs16.w-16-dst16-16-16-An-relative-HI", "abs.w", 32,
61806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61808 /* abs.w ${Dsp-16-u8}[sb] */
61810 M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, "abs16.w-16-dst16-16-8-SB-relative-HI", "abs.w", 24,
61811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61813 /* abs.w ${Dsp-16-u16}[sb] */
61815 M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, "abs16.w-16-dst16-16-16-SB-relative-HI", "abs.w", 32,
61816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61818 /* abs.w ${Dsp-16-s8}[fb] */
61820 M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, "abs16.w-16-dst16-16-8-FB-relative-HI", "abs.w", 24,
61821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61823 /* abs.w ${Dsp-16-u16} */
61825 M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, "abs16.w-16-dst16-16-16-absolute-HI", "abs.w", 32,
61826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61828 /* abs.b $Dst16RnQI */
61830 M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, "abs16.b-16-dst16-Rn-direct-QI", "abs.b", 16,
61831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61833 /* abs.b $Dst16AnQI */
61835 M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, "abs16.b-16-dst16-An-direct-QI", "abs.b", 16,
61836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61838 /* abs.b [$Dst16An] */
61840 M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, "abs16.b-16-dst16-An-indirect-QI", "abs.b", 16,
61841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61843 /* abs.b ${Dsp-16-u8}[$Dst16An] */
61845 M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, "abs16.b-16-dst16-16-8-An-relative-QI", "abs.b", 24,
61846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61848 /* abs.b ${Dsp-16-u16}[$Dst16An] */
61850 M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, "abs16.b-16-dst16-16-16-An-relative-QI", "abs.b", 32,
61851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61853 /* abs.b ${Dsp-16-u8}[sb] */
61855 M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, "abs16.b-16-dst16-16-8-SB-relative-QI", "abs.b", 24,
61856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61858 /* abs.b ${Dsp-16-u16}[sb] */
61860 M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, "abs16.b-16-dst16-16-16-SB-relative-QI", "abs.b", 32,
61861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61863 /* abs.b ${Dsp-16-s8}[fb] */
61865 M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, "abs16.b-16-dst16-16-8-FB-relative-QI", "abs.b", 24,
61866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61868 /* abs.b ${Dsp-16-u16} */
61870 M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, "abs16.b-16-dst16-16-16-absolute-QI", "abs.b", 32,
61871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61873 /* add.w$Q #${Imm-12-s4},sp */
61875 M32C_INSN_ADD16_WQ_SP, "add16-wQ-sp", "add.w", 16,
61876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61878 /* add.b$G #${Imm-16-QI},sp */
61880 M32C_INSN_ADD16_B_G_SP, "add16.b-G-sp", "add.b", 24,
61881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61883 /* add.w$G #${Imm-16-HI},sp */
61885 M32C_INSN_ADD16_W_G_SP, "add16.w-G-sp", "add.w", 32,
61886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61888 /* add.l$Q #${Imm3-S},sp */
61890 M32C_INSN_ADD32_L_IMM3_Q, "add32.l-imm3-Q", "add.l", 8,
61891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61893 /* add.l$S #${Imm-16-QI},sp */
61895 M32C_INSN_ADD32_L_IMM8_S, "add32.l-imm8-S", "add.l", 24,
61896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61898 /* add.l$G #${Imm-16-HI},sp */
61900 M32C_INSN_ADD32_L_IMM16_G, "add32.l-imm16-G", "add.l", 32,
61901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61903 /* dadc.b #${Imm-16-QI} */
61905 M32C_INSN_DADC16_B_IMM8, "dadc16.b-imm8", "dadc.b", 24,
61906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61908 /* dadc.w #${Imm-16-HI} */
61910 M32C_INSN_DADC16_W_IMM16, "dadc16.w-imm16", "dadc.w", 32,
61911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61913 /* dadc.b r0h,r0l */
61915 M32C_INSN_DADC16_B_R0H_R0L, "dadc16.b-r0h-r0l", "dadc.b", 16,
61916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61918 /* dadc.w r1,r0 */
61920 M32C_INSN_DADC16_W_R1_R0, "dadc16.w-r1-r0", "dadc.w", 16,
61921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61923 /* dadd.b #${Imm-16-QI} */
61925 M32C_INSN_DADD16_B_IMM8, "dadd16.b-imm8", "dadd.b", 24,
61926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61928 /* dadd.w #${Imm-16-HI} */
61930 M32C_INSN_DADD16_W_IMM16, "dadd16.w-imm16", "dadd.w", 32,
61931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61933 /* dadd.b r0h,r0l */
61935 M32C_INSN_DADD16_B_R0H_R0L, "dadd16.b-r0h-r0l", "dadd.b", 16,
61936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61938 /* dadd.w r1,r0 */
61940 M32C_INSN_DADD16_W_R1_R0, "dadd16.w-r1-r0", "dadd.w", 16,
61941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61943 /* bm$cond16c c */
61945 M32C_INSN_BM16_C, "bm16-c", "bm", 16,
61946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61948 /* bm$cond32 c */
61950 M32C_INSN_BM32_C, "bm32-c", "bm", 16,
61951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61953 /* brk */
61955 M32C_INSN_BRK16, "brk16", "brk", 8,
61956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61958 /* brk */
61960 M32C_INSN_BRK32, "brk32", "brk", 8,
61961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61963 /* brk2 */
61965 M32C_INSN_BRK232, "brk232", "brk2", 8,
61966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61968 /* dec.w ${Dst16An-S} */
61970 M32C_INSN_DEC16_W, "dec16.w", "dec.w", 8,
61971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61973 /* div.b #${Imm-16-QI} */
61975 M32C_INSN_DIV16_B_IMM_16_QI, "div16.b-Imm-16-QI", "div.b", 24,
61976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61978 /* div.w #${Imm-16-HI} */
61980 M32C_INSN_DIV16_W_IMM_16_HI, "div16.w-Imm-16-HI", "div.w", 32,
61981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61983 /* div.b #${Imm-16-QI} */
61985 M32C_INSN_DIV32_B_IMM_16_QI, "div32.b-Imm-16-QI", "div.b", 24,
61986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61988 /* div.w #${Imm-16-HI} */
61990 M32C_INSN_DIV32_W_IMM_16_HI, "div32.w-Imm-16-HI", "div.w", 32,
61991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
61993 /* divu.b #${Imm-16-QI} */
61995 M32C_INSN_DIVU16_B_IMM_16_QI, "divu16.b-Imm-16-QI", "divu.b", 24,
61996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
61998 /* divu.w #${Imm-16-HI} */
62000 M32C_INSN_DIVU16_W_IMM_16_HI, "divu16.w-Imm-16-HI", "divu.w", 32,
62001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62003 /* divu.b #${Imm-16-QI} */
62005 M32C_INSN_DIVU32_B_IMM_16_QI, "divu32.b-Imm-16-QI", "divu.b", 24,
62006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62008 /* divu.w #${Imm-16-HI} */
62010 M32C_INSN_DIVU32_W_IMM_16_HI, "divu32.w-Imm-16-HI", "divu.w", 32,
62011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62013 /* divx.b #${Imm-16-QI} */
62015 M32C_INSN_DIVX16_B_IMM_16_QI, "divx16.b-Imm-16-QI", "divx.b", 24,
62016 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62018 /* divx.w #${Imm-16-HI} */
62020 M32C_INSN_DIVX16_W_IMM_16_HI, "divx16.w-Imm-16-HI", "divx.w", 32,
62021 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62023 /* divx.b #${Imm-16-QI} */
62025 M32C_INSN_DIVX32_B_IMM_16_QI, "divx32.b-Imm-16-QI", "divx.b", 24,
62026 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62028 /* divx.w #${Imm-16-HI} */
62030 M32C_INSN_DIVX32_W_IMM_16_HI, "divx32.w-Imm-16-HI", "divx.w", 32,
62031 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62033 /* dsbb.b #${Imm-16-QI} */
62035 M32C_INSN_DSBB16_B_IMM8, "dsbb16.b-imm8", "dsbb.b", 24,
62036 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62038 /* dsbb.w #${Imm-16-HI} */
62040 M32C_INSN_DSBB16_W_IMM16, "dsbb16.w-imm16", "dsbb.w", 32,
62041 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62043 /* dsbb.b r0h,r0l */
62045 M32C_INSN_DSBB16_B_R0H_R0L, "dsbb16.b-r0h-r0l", "dsbb.b", 16,
62046 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62048 /* dsbb.w r1,r0 */
62050 M32C_INSN_DSBB16_W_R1_R0, "dsbb16.w-r1-r0", "dsbb.w", 16,
62051 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62053 /* dsub.b #${Imm-16-QI} */
62055 M32C_INSN_DSUB16_B_IMM8, "dsub16.b-imm8", "dsub.b", 24,
62056 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62058 /* dsub.w #${Imm-16-HI} */
62060 M32C_INSN_DSUB16_W_IMM16, "dsub16.w-imm16", "dsub.w", 32,
62061 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62063 /* dsub.b r0h,r0l */
62065 M32C_INSN_DSUB16_B_R0H_R0L, "dsub16.b-r0h-r0l", "dsub.b", 16,
62066 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62068 /* dsub.w r1,r0 */
62070 M32C_INSN_DSUB16_W_R1_R0, "dsub16.w-r1-r0", "dsub.w", 16,
62071 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62073 /* enter #${Dsp-16-u8} */
62075 M32C_INSN_ENTER16, "enter16", "enter", 24,
62076 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62078 /* exitd */
62080 M32C_INSN_EXITD16, "exitd16", "exitd", 16,
62081 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62083 /* enter #${Dsp-8-u8} */
62085 M32C_INSN_ENTER32, "enter32", "enter", 16,
62086 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62088 /* exitd */
62090 M32C_INSN_EXITD32, "exitd32", "exitd", 8,
62091 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62093 /* fclr ${flags16} */
62095 M32C_INSN_FCLR16, "fclr16", "fclr", 16,
62096 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62098 /* fset ${flags16} */
62100 M32C_INSN_FSET16, "fset16", "fset", 16,
62101 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62103 /* fclr ${flags32} */
62105 M32C_INSN_FCLR, "fclr", "fclr", 16,
62106 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62108 /* fset ${flags32} */
62110 M32C_INSN_FSET, "fset", "fset", 16,
62111 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62113 /* inc.w ${Dst16An-S} */
62115 M32C_INSN_INC16_W, "inc16.w", "inc.w", 8,
62116 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62118 /* freit */
62120 M32C_INSN_FREIT32, "freit32", "freit", 8,
62121 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62123 /* int #${Dsp-10-u6} */
62125 M32C_INSN_INT16, "int16", "int", 16,
62126 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62128 /* into */
62130 M32C_INSN_INTO16, "into16", "into", 8,
62131 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62133 /* int #${Dsp-8-u6} */
62135 M32C_INSN_INT32, "int32", "int", 16,
62136 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62138 /* into */
62140 M32C_INSN_INTO32, "into32", "into", 8,
62141 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62143 /* j$cond16j5 ${Lab-8-8} */
62145 M32C_INSN_JCND16_5, "jcnd16-5", "j", 16,
62146 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62148 /* j$cond16j ${Lab-16-8} */
62150 M32C_INSN_JCND16, "jcnd16", "j", 24,
62151 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62153 /* j$cond32j ${Lab-8-8} */
62155 M32C_INSN_JCND32, "jcnd32", "j", 16,
62156 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62158 /* jmp.s ${Lab-5-3} */
62160 M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8,
62161 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62163 /* jmp.b ${Lab-8-8} */
62165 M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16,
62166 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62168 /* jmp.w ${Lab-8-16} */
62170 M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24,
62171 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62173 /* jmp.a ${Lab-8-24} */
62175 M32C_INSN_JMP16_A, "jmp16.a", "jmp.a", 32,
62176 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62178 /* jmps #${Imm-8-QI} */
62180 M32C_INSN_JMPS16, "jmps16", "jmps", 16,
62181 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62183 /* jmp.s ${Lab32-jmp-s} */
62185 M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8,
62186 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62188 /* jmp.b ${Lab-8-8} */
62190 M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16,
62191 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62193 /* jmp.w ${Lab-8-16} */
62195 M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24,
62196 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62198 /* jmp.a ${Lab-8-24} */
62200 M32C_INSN_JMP32_A, "jmp32.a", "jmp.a", 32,
62201 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62203 /* jmps #${Imm-8-QI} */
62205 M32C_INSN_JMPS32, "jmps32", "jmps", 16,
62206 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62208 /* jsr.w ${Lab-8-16} */
62210 M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24,
62211 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62213 /* jsr.a ${Lab-8-24} */
62215 M32C_INSN_JSR16_A, "jsr16.a", "jsr.a", 32,
62216 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62218 /* jsr.w ${Lab-8-16} */
62220 M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24,
62221 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62223 /* jsr.a ${Lab-8-24} */
62225 M32C_INSN_JSR32_A, "jsr32.a", "jsr.a", 32,
62226 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62228 /* jsrs #${Imm-8-QI} */
62230 M32C_INSN_JSRS16, "jsrs16", "jsrs", 16,
62231 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62233 /* jsrs #${Imm-8-QI} */
62235 M32C_INSN_JSRS, "jsrs", "jsrs", 16,
62236 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62238 /* ldc #${Imm-16-HI},${cr16} */
62240 M32C_INSN_LDC16_IMM16, "ldc16.imm16", "ldc", 32,
62241 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62243 /* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
62245 M32C_INSN_LDC32_IMM16_CR1, "ldc32.imm16-cr1", "ldc", 32,
62246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62248 /* ldc #${Dsp-16-u24},${cr2-32} */
62250 M32C_INSN_LDC32_IMM16_CR2, "ldc32.imm16-cr2", "ldc", 40,
62251 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62253 /* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
62255 M32C_INSN_LDC32_IMM16_CR3, "ldc32.imm16-cr3", "ldc", 40,
62256 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62258 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
62260 M32C_INSN_LDCTX16, "ldctx16", "ldctx", 56,
62261 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62263 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
62265 M32C_INSN_LDCTX32, "ldctx32", "ldctx", 56,
62266 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62268 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
62270 M32C_INSN_STCTX16, "stctx16", "stctx", 56,
62271 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62273 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
62275 M32C_INSN_STCTX32, "stctx32", "stctx", 56,
62276 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62278 /* ldipl #${Imm-13-u3} */
62280 M32C_INSN_LDIPL16_IMM, "ldipl16.imm", "ldipl", 16,
62281 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62283 /* ldipl #${Imm-13-u3} */
62285 M32C_INSN_LDIPL32_IMM, "ldipl32.imm", "ldipl", 16,
62286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62288 /* mov.b$S #${Imm-8-QI},a0 */
62290 M32C_INSN_MOV16_B_S_IMM_A0, "mov16.b.S-imm-a0", "mov.b", 16,
62291 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62293 /* mov.b$S #${Imm-8-QI},a1 */
62295 M32C_INSN_MOV16_B_S_IMM_A1, "mov16.b.S-imm-a1", "mov.b", 16,
62296 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62298 /* mov.w$S #${Imm-8-HI},a0 */
62300 M32C_INSN_MOV16_W_S_IMM_A0, "mov16.w.S-imm-a0", "mov.w", 24,
62301 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62303 /* mov.w$S #${Imm-8-HI},a1 */
62305 M32C_INSN_MOV16_W_S_IMM_A1, "mov16.w.S-imm-a1", "mov.w", 24,
62306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62308 /* mov.w$S #${Imm-8-HI},a0 */
62310 M32C_INSN_MOV32_W_A0, "mov32-w-a0", "mov.w", 24,
62311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62313 /* mov.w$S #${Imm-8-HI},a1 */
62315 M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24,
62316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62318 /* mov.l$S #${Dsp-8-s24},a0 */
62320 M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32,
62321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62323 /* mov.l$S #${Dsp-8-s24},a1 */
62325 M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32,
62326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62328 /* mov.b$S r0l,a1 */
62330 M32C_INSN_MOV16_B_S_R0L_A1, "mov16.b.S-r0l-a1", "mov.b", 8,
62331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62333 /* mov.b$S r0h,a0 */
62335 M32C_INSN_MOV16_B_S_R0H_A0, "mov16.b.S-r0h-a0", "mov.b", 8,
62336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62338 /* nop */
62340 M32C_INSN_NOP16, "nop16", "nop", 8,
62341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62343 /* nop */
62345 M32C_INSN_NOP32, "nop32", "nop", 8,
62346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62348 /* popc ${cr16} */
62350 M32C_INSN_POPC16_IMM16, "popc16.imm16", "popc", 16,
62351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62353 /* popc ${cr1-Unprefixed-32} */
62355 M32C_INSN_POPC32_IMM16_CR1, "popc32.imm16-cr1", "popc", 16,
62356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62358 /* popc ${cr2-32} */
62360 M32C_INSN_POPC32_IMM16_CR2, "popc32.imm16-cr2", "popc", 16,
62361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62363 /* pushc ${cr16} */
62365 M32C_INSN_PUSHC16_IMM16, "pushc16.imm16", "pushc", 16,
62366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62368 /* pushc ${cr1-Unprefixed-32} */
62370 M32C_INSN_PUSHC32_IMM16_CR1, "pushc32.imm16-cr1", "pushc", 16,
62371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62373 /* pushc ${cr2-32} */
62375 M32C_INSN_PUSHC32_IMM16_CR2, "pushc32.imm16-cr2", "pushc", 16,
62376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62378 /* popm ${Regsetpop} */
62380 M32C_INSN_POPM16, "popm16", "popm", 16,
62381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62383 /* pushm ${Regsetpush} */
62385 M32C_INSN_PUSHM16, "pushm16", "pushm", 16,
62386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62388 /* popm ${Regsetpop} */
62390 M32C_INSN_POPM, "popm", "popm", 16,
62391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62393 /* pushm ${Regsetpush} */
62395 M32C_INSN_PUSHM, "pushm", "pushm", 16,
62396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62398 /* push.b$G #${Imm-16-QI} */
62400 M32C_INSN_PUSH16_B_G_IMM, "push16.b.G-imm", "push.b", 24,
62401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62403 /* push.w$G #${Imm-16-HI} */
62405 M32C_INSN_PUSH16_W_G_IMM, "push16.w.G-imm", "push.w", 32,
62406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62408 /* push.b #Imm-8-QI */
62410 M32C_INSN_PUSH32_B_IMM, "push32.b.imm", "push.b", 16,
62411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62413 /* push.w #${Imm-8-HI} */
62415 M32C_INSN_PUSH32_W_IMM, "push32.w.imm", "push.w", 24,
62416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62418 /* push.l #${Imm-16-SI} */
62420 M32C_INSN_PUSH32_L_IMM, "push32.l.imm", "push.l", 48,
62421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62423 /* reit */
62425 M32C_INSN_REIT16, "reit16", "reit", 8,
62426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62428 /* reit */
62430 M32C_INSN_REIT32, "reit32", "reit", 8,
62431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62433 /* rmpa.b */
62435 M32C_INSN_RMPA16_B, "rmpa16.b", "rmpa.b", 16,
62436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62438 /* rmpa.w */
62440 M32C_INSN_RMPA16_W, "rmpa16.w", "rmpa.w", 16,
62441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62443 /* rmpa.b */
62445 M32C_INSN_RMPA32_B, "rmpa32.b", "rmpa.b", 16,
62446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62448 /* rmpa.w */
62450 M32C_INSN_RMPA32_W, "rmpa32.w", "rmpa.w", 16,
62451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62453 /* rts */
62455 M32C_INSN_RTS16, "rts16", "rts", 8,
62456 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62458 /* rts */
62460 M32C_INSN_RTS32, "rts32", "rts", 8,
62461 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62463 /* scmpu.b */
62465 M32C_INSN_SCMPU_B, "scmpu.b", "scmpu.b", 16,
62466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62468 /* scmpu.w */
62470 M32C_INSN_SCMPU_W, "scmpu.w", "scmpu.w", 16,
62471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62473 /* sha.l #${Imm-sh-12-s4},r2r0 */
62475 M32C_INSN_SHA16_L_IMM_R2R0, "sha16-L-imm-r2r0", "sha.l", 16,
62476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62478 /* sha.l #${Imm-sh-12-s4},r3r1 */
62480 M32C_INSN_SHA16_L_IMM_R3R1, "sha16-L-imm-r3r1", "sha.l", 16,
62481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62483 /* sha.l r1h,r2r0 */
62485 M32C_INSN_SHA16_L_R1H_R2R0, "sha16-L-r1h-r2r0", "sha.l", 16,
62486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62488 /* sha.l r1h,r3r1 */
62490 M32C_INSN_SHA16_L_R1H_R3R1, "sha16-L-r1h-r3r1", "sha.l", 16,
62491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62493 /* shl.l #${Imm-sh-12-s4},r2r0 */
62495 M32C_INSN_SHL16_L_IMM_R2R0, "shl16-L-imm-r2r0", "shl.l", 16,
62496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62498 /* shl.l #${Imm-sh-12-s4},r3r1 */
62500 M32C_INSN_SHL16_L_IMM_R3R1, "shl16-L-imm-r3r1", "shl.l", 16,
62501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62503 /* shl.l r1h,r2r0 */
62505 M32C_INSN_SHL16_L_R1H_R2R0, "shl16-L-r1h-r2r0", "shl.l", 16,
62506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62508 /* shl.l r1h,r3r1 */
62510 M32C_INSN_SHL16_L_R1H_R3R1, "shl16-L-r1h-r3r1", "shl.l", 16,
62511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62513 /* sin.b */
62515 M32C_INSN_SIN32_B, "sin32.b", "sin.b", 16,
62516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62518 /* sin.w */
62520 M32C_INSN_SIN32_W, "sin32.w", "sin.w", 16,
62521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62523 /* smovb.b */
62525 M32C_INSN_SMOVB16_B, "smovb16.b", "smovb.b", 16,
62526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62528 /* smovb.w */
62530 M32C_INSN_SMOVB16_W, "smovb16.w", "smovb.w", 16,
62531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62533 /* smovb.b */
62535 M32C_INSN_SMOVB32_B, "smovb32.b", "smovb.b", 16,
62536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62538 /* smovb.w */
62540 M32C_INSN_SMOVB32_W, "smovb32.w", "smovb.w", 16,
62541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62543 /* smovf.b */
62545 M32C_INSN_SMOVF16_B, "smovf16.b", "smovf.b", 16,
62546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62548 /* smovf.w */
62550 M32C_INSN_SMOVF16_W, "smovf16.w", "smovf.w", 16,
62551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62553 /* smovf.b */
62555 M32C_INSN_SMOVF32_B, "smovf32.b", "smovf.b", 16,
62556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62558 /* smovf.w */
62560 M32C_INSN_SMOVF32_W, "smovf32.w", "smovf.w", 16,
62561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62563 /* smovu.b */
62565 M32C_INSN_SMOVU_B, "smovu.b", "smovu.b", 16,
62566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62568 /* smovu.w */
62570 M32C_INSN_SMOVU_W, "smovu.w", "smovu.w", 16,
62571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62573 /* sout.b */
62575 M32C_INSN_SOUT_B, "sout.b", "sout.b", 16,
62576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62578 /* sout.w */
62580 M32C_INSN_SOUT_W, "sout.w", "sout.w", 16,
62581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62583 /* sstr.b */
62585 M32C_INSN_SSTR16_B, "sstr16.b", "sstr.b", 16,
62586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62588 /* sstr.w */
62590 M32C_INSN_SSTR16_W, "sstr16.w", "sstr.w", 16,
62591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62593 /* sstr.b */
62595 M32C_INSN_SSTR_B, "sstr.b", "sstr.b", 16,
62596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62598 /* sstr.w */
62600 M32C_INSN_SSTR_W, "sstr.w", "sstr.w", 16,
62601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62603 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
62605 M32C_INSN_STZX16_IMM8_IMM8_R0H, "stzx16-imm8-imm8-r0h", "stzx", 24,
62606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62608 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
62610 M32C_INSN_STZX16_IMM8_IMM8_R0L, "stzx16-imm8-imm8-r0l", "stzx", 24,
62611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62613 /* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */
62615 M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, "stzx16-imm8-imm8-dsp8sb", "stzx", 32,
62616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62618 /* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */
62620 M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, "stzx16-imm8-imm8-dsp8fb", "stzx", 32,
62621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62623 /* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */
62625 M32C_INSN_STZX16_IMM8_IMM8_ABS16, "stzx16-imm8-imm8-abs16", "stzx", 40,
62626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62628 /* und */
62630 M32C_INSN_UND16, "und16", "und", 8,
62631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62633 /* und */
62635 M32C_INSN_UND32, "und32", "und", 8,
62636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62638 /* wait */
62640 M32C_INSN_WAIT16, "wait16", "wait", 16,
62641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62643 /* wait */
62645 M32C_INSN_WAIT, "wait", "wait", 16,
62646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62648 /* exts.w r0 */
62650 M32C_INSN_EXTS16_W_R0, "exts16.w-r0", "exts.w", 16,
62651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
62653 /* src-indirect */
62655 M32C_INSN_SRCIND, "srcind", "src-indirect", 8,
62656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62658 /* dest-indirect */
62660 M32C_INSN_DESTIND, "destind", "dest-indirect", 8,
62661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62663 /* src-dest-indirect */
62665 M32C_INSN_SRCDESTIND, "srcdestind", "src-dest-indirect", 8,
62666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
62670 #undef OP
62671 #undef A
62673 /* Initialize anything needed to be done once, before any cpu_open call. */
62675 static void
62676 init_tables (void)
62680 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
62681 static void build_hw_table (CGEN_CPU_TABLE *);
62682 static void build_ifield_table (CGEN_CPU_TABLE *);
62683 static void build_operand_table (CGEN_CPU_TABLE *);
62684 static void build_insn_table (CGEN_CPU_TABLE *);
62685 static void m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *);
62687 /* Subroutine of m32c_cgen_cpu_open to look up a mach via its bfd name. */
62689 static const CGEN_MACH *
62690 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
62692 while (table->name)
62694 if (strcmp (name, table->bfd_name) == 0)
62695 return table;
62696 ++table;
62698 abort ();
62701 /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62703 static void
62704 build_hw_table (CGEN_CPU_TABLE *cd)
62706 int i;
62707 int machs = cd->machs;
62708 const CGEN_HW_ENTRY *init = & m32c_cgen_hw_table[0];
62709 /* MAX_HW is only an upper bound on the number of selected entries.
62710 However each entry is indexed by it's enum so there can be holes in
62711 the table. */
62712 const CGEN_HW_ENTRY **selected =
62713 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
62715 cd->hw_table.init_entries = init;
62716 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
62717 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
62718 /* ??? For now we just use machs to determine which ones we want. */
62719 for (i = 0; init[i].name != NULL; ++i)
62720 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
62721 & machs)
62722 selected[init[i].type] = &init[i];
62723 cd->hw_table.entries = selected;
62724 cd->hw_table.num_entries = MAX_HW;
62727 /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62729 static void
62730 build_ifield_table (CGEN_CPU_TABLE *cd)
62732 cd->ifld_table = & m32c_cgen_ifld_table[0];
62735 /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62737 static void
62738 build_operand_table (CGEN_CPU_TABLE *cd)
62740 int i;
62741 int machs = cd->machs;
62742 const CGEN_OPERAND *init = & m32c_cgen_operand_table[0];
62743 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
62744 However each entry is indexed by it's enum so there can be holes in
62745 the table. */
62746 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
62748 cd->operand_table.init_entries = init;
62749 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
62750 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
62751 /* ??? For now we just use mach to determine which ones we want. */
62752 for (i = 0; init[i].name != NULL; ++i)
62753 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
62754 & machs)
62755 selected[init[i].type] = &init[i];
62756 cd->operand_table.entries = selected;
62757 cd->operand_table.num_entries = MAX_OPERANDS;
62760 /* Subroutine of m32c_cgen_cpu_open to build the hardware table.
62761 ??? This could leave out insns not supported by the specified mach/isa,
62762 but that would cause errors like "foo only supported by bar" to become
62763 "unknown insn", so for now we include all insns and require the app to
62764 do the checking later.
62765 ??? On the other hand, parsing of such insns may require their hardware or
62766 operand elements to be in the table [which they mightn't be]. */
62768 static void
62769 build_insn_table (CGEN_CPU_TABLE *cd)
62771 int i;
62772 const CGEN_IBASE *ib = & m32c_cgen_insn_table[0];
62773 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
62775 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
62776 for (i = 0; i < MAX_INSNS; ++i)
62777 insns[i].base = &ib[i];
62778 cd->insn_table.init_entries = insns;
62779 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
62780 cd->insn_table.num_init_entries = MAX_INSNS;
62783 /* Subroutine of m32c_cgen_cpu_open to rebuild the tables. */
62785 static void
62786 m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
62788 int i;
62789 CGEN_BITSET *isas = cd->isas;
62790 unsigned int machs = cd->machs;
62792 cd->int_insn_p = CGEN_INT_INSN_P;
62794 /* Data derived from the isa spec. */
62795 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
62796 cd->default_insn_bitsize = UNSET;
62797 cd->base_insn_bitsize = UNSET;
62798 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
62799 cd->max_insn_bitsize = 0;
62800 for (i = 0; i < MAX_ISAS; ++i)
62801 if (cgen_bitset_contains (isas, i))
62803 const CGEN_ISA *isa = & m32c_cgen_isa_table[i];
62805 /* Default insn sizes of all selected isas must be
62806 equal or we set the result to 0, meaning "unknown". */
62807 if (cd->default_insn_bitsize == UNSET)
62808 cd->default_insn_bitsize = isa->default_insn_bitsize;
62809 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
62810 ; /* This is ok. */
62811 else
62812 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
62814 /* Base insn sizes of all selected isas must be equal
62815 or we set the result to 0, meaning "unknown". */
62816 if (cd->base_insn_bitsize == UNSET)
62817 cd->base_insn_bitsize = isa->base_insn_bitsize;
62818 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
62819 ; /* This is ok. */
62820 else
62821 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
62823 /* Set min,max insn sizes. */
62824 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
62825 cd->min_insn_bitsize = isa->min_insn_bitsize;
62826 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
62827 cd->max_insn_bitsize = isa->max_insn_bitsize;
62830 /* Data derived from the mach spec. */
62831 for (i = 0; i < MAX_MACHS; ++i)
62832 if (((1 << i) & machs) != 0)
62834 const CGEN_MACH *mach = & m32c_cgen_mach_table[i];
62836 if (mach->insn_chunk_bitsize != 0)
62838 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
62840 fprintf (stderr, "m32c_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
62841 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
62842 abort ();
62845 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
62849 /* Determine which hw elements are used by MACH. */
62850 build_hw_table (cd);
62852 /* Build the ifield table. */
62853 build_ifield_table (cd);
62855 /* Determine which operands are used by MACH/ISA. */
62856 build_operand_table (cd);
62858 /* Build the instruction table. */
62859 build_insn_table (cd);
62862 /* Initialize a cpu table and return a descriptor.
62863 It's much like opening a file, and must be the first function called.
62864 The arguments are a set of (type/value) pairs, terminated with
62865 CGEN_CPU_OPEN_END.
62867 Currently supported values:
62868 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
62869 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
62870 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
62871 CGEN_CPU_OPEN_ENDIAN: specify endian choice
62872 CGEN_CPU_OPEN_END: terminates arguments
62874 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
62875 precluded.
62877 ??? We only support ISO C stdargs here, not K&R.
62878 Laziness, plus experiment to see if anything requires K&R - eventually
62879 K&R will no longer be supported - e.g. GDB is currently trying this. */
62881 CGEN_CPU_DESC
62882 m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
62884 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
62885 static int init_p;
62886 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
62887 unsigned int machs = 0; /* 0 = "unspecified" */
62888 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
62889 va_list ap;
62891 if (! init_p)
62893 init_tables ();
62894 init_p = 1;
62897 memset (cd, 0, sizeof (*cd));
62899 va_start (ap, arg_type);
62900 while (arg_type != CGEN_CPU_OPEN_END)
62902 switch (arg_type)
62904 case CGEN_CPU_OPEN_ISAS :
62905 isas = va_arg (ap, CGEN_BITSET *);
62906 break;
62907 case CGEN_CPU_OPEN_MACHS :
62908 machs = va_arg (ap, unsigned int);
62909 break;
62910 case CGEN_CPU_OPEN_BFDMACH :
62912 const char *name = va_arg (ap, const char *);
62913 const CGEN_MACH *mach =
62914 lookup_mach_via_bfd_name (m32c_cgen_mach_table, name);
62916 machs |= 1 << mach->num;
62917 break;
62919 case CGEN_CPU_OPEN_ENDIAN :
62920 endian = va_arg (ap, enum cgen_endian);
62921 break;
62922 default :
62923 fprintf (stderr, "m32c_cgen_cpu_open: unsupported argument `%d'\n",
62924 arg_type);
62925 abort (); /* ??? return NULL? */
62927 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
62929 va_end (ap);
62931 /* Mach unspecified means "all". */
62932 if (machs == 0)
62933 machs = (1 << MAX_MACHS) - 1;
62934 /* Base mach is always selected. */
62935 machs |= 1;
62936 if (endian == CGEN_ENDIAN_UNKNOWN)
62938 /* ??? If target has only one, could have a default. */
62939 fprintf (stderr, "m32c_cgen_cpu_open: no endianness specified\n");
62940 abort ();
62943 cd->isas = cgen_bitset_copy (isas);
62944 cd->machs = machs;
62945 cd->endian = endian;
62946 /* FIXME: for the sparc case we can determine insn-endianness statically.
62947 The worry here is where both data and insn endian can be independently
62948 chosen, in which case this function will need another argument.
62949 Actually, will want to allow for more arguments in the future anyway. */
62950 cd->insn_endian = endian;
62952 /* Table (re)builder. */
62953 cd->rebuild_tables = m32c_cgen_rebuild_tables;
62954 m32c_cgen_rebuild_tables (cd);
62956 /* Default to not allowing signed overflow. */
62957 cd->signed_overflow_ok_p = 0;
62959 return (CGEN_CPU_DESC) cd;
62962 /* Cover fn to m32c_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
62963 MACH_NAME is the bfd name of the mach. */
62965 CGEN_CPU_DESC
62966 m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
62968 return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
62969 CGEN_CPU_OPEN_ENDIAN, endian,
62970 CGEN_CPU_OPEN_END);
62973 /* Close a cpu table.
62974 ??? This can live in a machine independent file, but there's currently
62975 no place to put this file (there's no libcgen). libopcodes is the wrong
62976 place as some simulator ports use this but they don't use libopcodes. */
62978 void
62979 m32c_cgen_cpu_close (CGEN_CPU_DESC cd)
62981 unsigned int i;
62982 const CGEN_INSN *insns;
62984 if (cd->macro_insn_table.init_entries)
62986 insns = cd->macro_insn_table.init_entries;
62987 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
62988 if (CGEN_INSN_RX ((insns)))
62989 regfree (CGEN_INSN_RX (insns));
62992 if (cd->insn_table.init_entries)
62994 insns = cd->insn_table.init_entries;
62995 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
62996 if (CGEN_INSN_RX (insns))
62997 regfree (CGEN_INSN_RX (insns));
63000 if (cd->macro_insn_table.init_entries)
63001 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
63003 if (cd->insn_table.init_entries)
63004 free ((CGEN_INSN *) cd->insn_table.init_entries);
63006 if (cd->hw_table.entries)
63007 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
63009 if (cd->operand_table.entries)
63010 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
63012 free (cd);